src/libs/LPC17xx/score_cm3.h

   1 /******************************************************************************
   2  * @file:    core_cm3.h
   3  * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File
   4  * @version: V1.30 PRE-RELEASE
   5  * @date:    30. July 2009
   6  *----------------------------------------------------------------------------
   7  *
   8  * Copyright (C) 2009 ARM Limited. All rights reserved.
   9  *
  10  * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
  11  * processor based microcontrollers.  This file can be freely distributed
  12  * within development tools that are supporting such ARM based processors.
  13  *
  14  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  15  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
  16  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
  17  * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
  18  * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
  19  *
  20  ******************************************************************************/
  21
  22 #ifndef __CM3_CORE_H__
  23 #define __CM3_CORE_H__
  24
  25 #ifdef __cplusplus
  26  extern "C" {
  27 #endif
  28
  29 #define __CM3_CMSIS_VERSION_MAIN  (0x01)                                                       /*!< [31:16] CMSIS HAL main version */
  30 #define __CM3_CMSIS_VERSION_SUB   (0x30)                                                       /*!< [15:0]  CMSIS HAL sub version  */
  31 #define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number       */
  32
  33 #define __CORTEX_M                (0x03)                                                       /*!< Cortex core                    */
  34
  35 /**
  36  *  Lint configuration \n
  37  *  ----------------------- \n
  38  *
  39  *  The following Lint messages will be suppressed and not shown: \n
  40  *  \n
  41  *    --- Error 10: --- \n
  42  *    register uint32_t __regBasePri         __asm("basepri"); \n
  43  *    Error 10: Expecting ';' \n
  44  *     \n
  45  *    --- Error 530: --- \n
  46  *    return(__regBasePri); \n
  47  *    Warning 530: Symbol '__regBasePri' (line 264) not initialized \n
  48  *     \n
  49  *    --- Error 550: --- \n
  50  *      __regBasePri = (basePri & 0x1ff); \n
  51  *    } \n
  52  *    Warning 550: Symbol '__regBasePri' (line 271) not accessed \n
  53  *     \n
  54  *    --- Error 754: --- \n
  55  *    uint32_t RESERVED0[24]; \n
  56  *    Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced \n
  57  *     \n
  58  *    --- Error 750: --- \n
  59  *    #define __CM3_CORE_H__ \n
  60  *    Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n
  61  *     \n
  62  *    --- Error 528: --- \n
  63  *    static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
  64  *    Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n
  65  *     \n
  66  *    --- Error 751: --- \n
  67  *    } InterruptType_Type; \n
  68  *    Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n
  69  * \n
  70  * \n
  71  *    Note:  To re-enable a Message, insert a space before 'lint' * \n
  72  *
  73  */
  74
  75 /*lint -save */
  76 /*lint -e10  */
  77 /*lint -e530 */
  78 /*lint -e550 */
  79 /*lint -e754 */
  80 /*lint -e750 */
  81 /*lint -e528 */
  82 /*lint -e751 */
  83
  84
  85 #include <stdint.h>                           /* Include standard types */
  86
  87 #if defined (__ICCARM__)
  88   #include <intrinsics.h>                     /* IAR Intrinsics   */
  89 #endif
  90
  91
  92 #ifndef __NVIC_PRIO_BITS
  93   #define __NVIC_PRIO_BITS    4               /*!< standard definition for NVIC Priority Bits */
  94 #endif
  95
  96
  97
  98
  99 /**
 100  * IO definitions
 101  *
 102  * define access restrictions to peripheral registers
 103  */
 104
 105 #ifdef __cplusplus
 106 #define     __I     volatile                  /*!< defines 'read only' permissions      */
 107 #else
 108 #define     __I     volatile const            /*!< defines 'read only' permissions      */
 109 #endif
 110 #define     __O     volatile                  /*!< defines 'write only' permissions     */
 111 #define     __IO    volatile                  /*!< defines 'read / write' permissions   */
 112
 113
 114
 115 /*******************************************************************************
 116  *                 Register Abstraction
 117  ******************************************************************************/
 118
 119
 120 /* System Reset */
 121 #define NVIC_VECTRESET              0         /*!< Vector Reset Bit             */
 122 #define NVIC_SYSRESETREQ            2         /*!< System Reset Request         */
 123 #define NVIC_AIRCR_VECTKEY    (0x5FA << 16)   /*!< AIRCR Key for write access   */
 124 #define NVIC_AIRCR_ENDIANESS        15        /*!< Endianess                    */
 125
 126 /* Core Debug */
 127 #define CoreDebug_DEMCR_TRCENA (1 << 24)      /*!< DEMCR TRCENA enable          */
 128 #define ITM_TCR_ITMENA              1         /*!< ITM enable                   */
 129
 130
 131
 132
 133 /* memory mapping struct for Nested Vectored Interrupt Controller (NVIC) */
 134 typedef struct
 135 {
 136   __IO uint32_t ISER[8];                      /*!< Interrupt Set Enable Register            */
 137        uint32_t RESERVED0[24];
 138   __IO uint32_t ICER[8];                      /*!< Interrupt Clear Enable Register          */
 139        uint32_t RSERVED1[24];
 140   __IO uint32_t ISPR[8];                      /*!< Interrupt Set Pending Register           */
 141        uint32_t RESERVED2[24];
 142   __IO uint32_t ICPR[8];                      /*!< Interrupt Clear Pending Register         */
 143        uint32_t RESERVED3[24];
 144   __IO uint32_t IABR[8];                      /*!< Interrupt Active bit Register            */
 145        uint32_t RESERVED4[56];
 146   __IO uint8_t  IP[240];                      /*!< Interrupt Priority Register, 8Bit wide   */
 147        uint32_t RESERVED5[644];
 148   __O  uint32_t STIR;                         /*!< Software Trigger Interrupt Register      */
 149 }  NVIC_Type;
 150
 151
 152 /* memory mapping struct for System Control Block */
 153 typedef struct
 154 {
 155   __I  uint32_t CPUID;                        /*!< CPU ID Base Register                                     */
 156   __IO uint32_t ICSR;                         /*!< Interrupt Control State Register                         */
 157   __IO uint32_t VTOR;                         /*!< Vector Table Offset Register                             */
 158   __IO uint32_t AIRCR;                        /*!< Application Interrupt / Reset Control Register           */
 159   __IO uint32_t SCR;                          /*!< System Control Register                                  */
 160   __IO uint32_t CCR;                          /*!< Configuration Control Register                           */
 161   __IO uint8_t  SHP[12];                      /*!< System Handlers Priority Registers (4-7, 8-11, 12-15)    */
 162   __IO uint32_t SHCSR;                        /*!< System Handler Control and State Register                */
 163   __IO uint32_t CFSR;                         /*!< Configurable Fault Status Register                       */
 164   __IO uint32_t HFSR;                         /*!< Hard Fault Status Register                               */
 165   __IO uint32_t DFSR;                         /*!< Debug Fault Status Register                              */
 166   __IO uint32_t MMFAR;                        /*!< Mem Manage Address Register                              */
 167   __IO uint32_t BFAR;                         /*!< Bus Fault Address Register                               */
 168   __IO uint32_t AFSR;                         /*!< Auxiliary Fault Status Register                          */
 169   __I  uint32_t PFR[2];                       /*!< Processor Feature Register                               */
 170   __I  uint32_t DFR;                          /*!< Debug Feature Register                                   */
 171   __I  uint32_t ADR;                          /*!< Auxiliary Feature Register                               */
 172   __I  uint32_t MMFR[4];                      /*!< Memory Model Feature Register                            */
 173   __I  uint32_t ISAR[5];                      /*!< ISA Feature Register                                     */
 174 } SCB_Type;
 175
 176
 177 /* memory mapping struct for SysTick */
 178 typedef struct
 179 {
 180   __IO uint32_t CTRL;                         /*!< SysTick Control and Status Register */
 181   __IO uint32_t LOAD;                         /*!< SysTick Reload Value Register       */
 182   __IO uint32_t VAL;                          /*!< SysTick Current Value Register      */
 183   __I  uint32_t CALIB;                        /*!< SysTick Calibration Register        */
 184 } SysTick_Type;
 185
 186
 187 /* memory mapping structur for ITM */
 188 typedef struct
 189 {
 190   __O  union
 191   {
 192     __O  uint8_t    u8;                       /*!< ITM Stimulus Port 8-bit               */
 193     __O  uint16_t   u16;                      /*!< ITM Stimulus Port 16-bit              */
 194     __O  uint32_t   u32;                      /*!< ITM Stimulus Port 32-bit              */
 195   }  PORT [32];                               /*!< ITM Stimulus Port Registers           */
 196        uint32_t RESERVED0[864];
 197   __IO uint32_t TER;                          /*!< ITM Trace Enable Register             */
 198        uint32_t RESERVED1[15];
 199   __IO uint32_t TPR;                          /*!< ITM Trace Privilege Register          */
 200        uint32_t RESERVED2[15];
 201   __IO uint32_t TCR;                          /*!< ITM Trace Control Register            */
 202        uint32_t RESERVED3[29];
 203   __IO uint32_t IWR;                          /*!< ITM Integration Write Register        */
 204   __IO uint32_t IRR;                          /*!< ITM Integration Read Register         */
 205   __IO uint32_t IMCR;                         /*!< ITM Integration Mode Control Register */
 206        uint32_t RESERVED4[43];
 207   __IO uint32_t LAR;                          /*!< ITM Lock Access Register              */
 208   __IO uint32_t LSR;                          /*!< ITM Lock Status Register              */
 209        uint32_t RESERVED5[6];
 210   __I  uint32_t PID4;                         /*!< ITM Product ID Registers              */
 211   __I  uint32_t PID5;
 212   __I  uint32_t PID6;
 213   __I  uint32_t PID7;
 214   __I  uint32_t PID0;
 215   __I  uint32_t PID1;
 216   __I  uint32_t PID2;
 217   __I  uint32_t PID3;
 218   __I  uint32_t CID0;
 219   __I  uint32_t CID1;
 220   __I  uint32_t CID2;
 221   __I  uint32_t CID3;
 222 } ITM_Type;
 223
 224
 225 /* memory mapped struct for Interrupt Type */
 226 typedef struct
 227 {
 228        uint32_t RESERVED0;
 229   __I  uint32_t ICTR;                         /*!< Interrupt Control Type Register  */
 230 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
 231   __IO uint32_t ACTLR;                        /*!< Auxiliary Control Register       */
 232 #else
 233        uint32_t RESERVED1;
 234 #endif
 235 } InterruptType_Type;
 236
 237
 238 /* Memory Protection Unit */
 239 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
 240 typedef struct
 241 {
 242   __I  uint32_t TYPE;                         /*!< MPU Type Register                               */
 243   __IO uint32_t CTRL;                         /*!< MPU Control Register                            */
 244   __IO uint32_t RNR;                          /*!< MPU Region RNRber Register                      */
 245   __IO uint32_t RBAR;                         /*!< MPU Region Base Address Register                */
 246   __IO uint32_t RASR;                         /*!< MPU Region Attribute and Size Register          */
 247   __IO uint32_t RBAR_A1;                      /*!< MPU Alias 1 Region Base Address Register        */
 248   __IO uint32_t RASR_A1;                      /*!< MPU Alias 1 Region Attribute and Size Register  */
 249   __IO uint32_t RBAR_A2;                      /*!< MPU Alias 2 Region Base Address Register        */
 250   __IO uint32_t RASR_A2;                      /*!< MPU Alias 2 Region Attribute and Size Register  */
 251   __IO uint32_t RBAR_A3;                      /*!< MPU Alias 3 Region Base Address Register        */
 252   __IO uint32_t RASR_A3;                      /*!< MPU Alias 3 Region Attribute and Size Register  */
 253 } MPU_Type;
 254 #endif
 255
 256
 257 /* Core Debug Register */
 258 typedef struct
 259 {
 260   __IO uint32_t DHCSR;                        /*!< Debug Halting Control and Status Register       */
 261   __O  uint32_t DCRSR;                        /*!< Debug Core Register Selector Register           */
 262   __IO uint32_t DCRDR;                        /*!< Debug Core Register Data Register               */
 263   __IO uint32_t DEMCR;                        /*!< Debug Exception and Monitor Control Register    */
 264 } CoreDebug_Type;
 265
 266
 267 /* Memory mapping of Cortex-M3 Hardware */
 268 #define SCS_BASE            (0xE000E000)                              /*!< System Control Space Base Address    */
 269 #define ITM_BASE            (0xE0000000)                              /*!< ITM Base Address                     */
 270 #define CoreDebug_BASE      (0xE000EDF0)                              /*!< Core Debug Base Address              */
 271 #define SysTick_BASE        (SCS_BASE +  0x0010)                      /*!< SysTick Base Address                 */
 272 #define NVIC_BASE           (SCS_BASE +  0x0100)                      /*!< NVIC Base Address                    */
 273 #define SCB_BASE            (SCS_BASE +  0x0D00)                      /*!< System Control Block Base Address    */
 274
 275 #define InterruptType       ((InterruptType_Type *) SCS_BASE)         /*!< Interrupt Type Register              */
 276 #define SCB                 ((SCB_Type *)           SCB_BASE)         /*!< SCB configuration struct             */
 277 #define SysTick             ((SysTick_Type *)       SysTick_BASE)     /*!< SysTick configuration struct         */
 278 #define NVIC                ((NVIC_Type *)          NVIC_BASE)        /*!< NVIC configuration struct            */
 279 #define ITM                 ((ITM_Type *)           ITM_BASE)         /*!< ITM configuration struct             */
 280 #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct      */
 281
 282 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
 283   #define MPU_BASE          (SCS_BASE +  0x0D90)                      /*!< Memory Protection Unit               */
 284   #define MPU               ((MPU_Type*)            MPU_BASE)         /*!< Memory Protection Unit               */
 285 #endif
 286
 287
 288 /*******************************************************************************
 289  *                Hardware Abstraction Layer
 290  ******************************************************************************/
 291
 292
 293 #if defined ( __CC_ARM   )
 294   #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
 295   #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
 296
 297 #elif defined ( __ICCARM__ )
 298   #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler           */
 299   #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
 300
 301 #elif defined   (  __GNUC__  )
 302   #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
 303   #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
 304
 305 #elif defined   (  __TASKING__  )
 306   #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler          */
 307   #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler       */
 308
 309 #endif
 310
 311
 312 /* ###################  Compiler specific Intrinsics  ########################### */
 313
 314 #if defined ( __CC_ARM   ) /*------------------RealView Compiler -----------------*/
 315 /* ARM armcc specific functions */
 316
 317 #define __enable_fault_irq                __enable_fiq
 318 #define __disable_fault_irq               __disable_fiq
 319
 320 #define __NOP                             __nop
 321 #define __WFI                             __wfi
 322 #define __WFE                             __wfe
 323 #define __SEV                             __sev
 324 #define __ISB()                           __isb(0)
 325 #define __DSB()                           __dsb(0)
 326 #define __DMB()                           __dmb(0)
 327 #define __REV                             __rev
 328 #define __RBIT                            __rbit
 329 #define __LDREXB(ptr)                     ((unsigned char ) __ldrex(ptr))
 330 #define __LDREXH(ptr)                     ((unsigned short) __ldrex(ptr))
 331 #define __LDREXW(ptr)                     ((unsigned int  ) __ldrex(ptr))
 332 #define __STREXB(value, ptr)              __strex(value, ptr)
 333 #define __STREXH(value, ptr)              __strex(value, ptr)
 334 #define __STREXW(value, ptr)              __strex(value, ptr)
 335
 336
 337 /* intrinsic unsigned long long __ldrexd(volatile void *ptr) */
 338 /* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */
 339 /* intrinsic void __enable_irq();     */
 340 /* intrinsic void __disable_irq();    */
 341
 342
 343 #if (__ARMCC_VERSION < 400000)
 344
 345 #else  /* (__ARMCC_VERSION >= 400000)  */
 346
 347
 348 /**
 349  * @brief  Remove the exclusive lock created by ldrex
 350  *
 351  * @param  none
 352  * @return none
 353  *
 354  * Removes the exclusive lock which is created by ldrex.
 355  */
 356 #define __CLREX                           __clrex
 357
 358 /**
 359  * @brief  Return the Base Priority value
 360  *
 361  * @param  none
 362  * @return uint32_t BasePriority
 363  *
 364  * Return the content of the base priority register
 365  */
 366 static __INLINE uint32_t  __get_BASEPRI(void)
 367 {
 368   register uint32_t __regBasePri         __ASM("basepri");
 369   return(__regBasePri);
 370 }
 371
 372 /**
 373  * @brief  Set the Base Priority value
 374  *
 375  * @param  uint32_t BasePriority
 376  * @return none
 377  *
 378  * Set the base priority register
 379  */
 380 static __INLINE void __set_BASEPRI(uint32_t basePri)
 381 {
 382   register uint32_t __regBasePri         __ASM("basepri");
 383   __regBasePri = (basePri & 0xff);
 384 }
 385
 386 /**
 387  * @brief  Return the Priority Mask value
 388  *
 389  * @param  none
 390  * @return uint32_t PriMask
 391  *
 392  * Return the state of the priority mask bit from the priority mask
 393  * register
 394  */
 395 static __INLINE uint32_t __get_PRIMASK(void)
 396 {
 397   register uint32_t __regPriMask         __ASM("primask");
 398   return(__regPriMask);
 399 }
 400
 401 /**
 402  * @brief  Set the Priority Mask value
 403  *
 404  * @param  uint32_t PriMask
 405  * @return none
 406  *
 407  * Set the priority mask bit in the priority mask register
 408  */
 409 static __INLINE void __set_PRIMASK(uint32_t priMask)
 410 {
 411   register uint32_t __regPriMask         __ASM("primask");
 412   __regPriMask = (priMask);
 413 }
 414
 415 /**
 416  * @brief  Return the Fault Mask value
 417  *
 418  * @param  none
 419  * @return uint32_t FaultMask
 420  *
 421  * Return the content of the fault mask register
 422  */
 423 static __INLINE uint32_t __get_FAULTMASK(void)
 424 {
 425   register uint32_t __regFaultMask       __ASM("faultmask");
 426   return(__regFaultMask);
 427 }
 428
 429 /**
 430  * @brief  Set the Fault Mask value
 431  *
 432  * @param  uint32_t faultMask value
 433  * @return none
 434  *
 435  * Set the fault mask register
 436  */
 437 static __INLINE void __set_FAULTMASK(uint32_t faultMask)
 438 {
 439   register uint32_t __regFaultMask       __ASM("faultmask");
 440   __regFaultMask = (faultMask & 1);
 441 }
 442
 443 /**
 444  * @brief  Return the Control Register value
 445  *
 446  * @param  none
 447  * @return uint32_t Control value
 448  *
 449  * Return the content of the control register
 450  */
 451 static __INLINE uint32_t __get_CONTROL(void)
 452 {
 453   register uint32_t __regControl         __ASM("control");
 454   return(__regControl);
 455 }
 456
 457 /**
 458  * @brief  Set the Control Register value
 459  *
 460  * @param  uint32_t Control value
 461  * @return none
 462  *
 463  * Set the control register
 464  */
 465 static __INLINE void __set_CONTROL(uint32_t control)
 466 {
 467   register uint32_t __regControl         __ASM("control");
 468   __regControl = control;
 469 }
 470
 471 #endif /* __ARMCC_VERSION  */
 472
 473
 474
 475 #elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
 476 /* IAR iccarm specific functions */
 477
 478 #define __enable_irq                              __enable_interrupt        /*!< global Interrupt enable */
 479 #define __disable_irq                             __disable_interrupt       /*!< global Interrupt disable */
 480
 481 static __INLINE void __enable_fault_irq()         { __ASM ("cpsie f"); }
 482 static __INLINE void __disable_fault_irq()        { __ASM ("cpsid f"); }
 483
 484 #define __NOP                                     __no_operation()          /*!< no operation intrinsic in IAR Compiler */
 485 static __INLINE  void __WFI()                     { __ASM ("wfi"); }
 486 static __INLINE  void __WFE()                     { __ASM ("wfe"); }
 487 static __INLINE  void __SEV()                     { __ASM ("sev"); }
 488 static __INLINE  void __CLREX()                   { __ASM ("clrex"); }
 489
 490 /* intrinsic void __ISB(void)                                     */
 491 /* intrinsic void __DSB(void)                                     */
 492 /* intrinsic void __DMB(void)                                     */
 493 /* intrinsic void __set_PRIMASK();                                */
 494 /* intrinsic void __get_PRIMASK();                                */
 495 /* intrinsic void __set_FAULTMASK();                              */
 496 /* intrinsic void __get_FAULTMASK();                              */
 497 /* intrinsic uint32_t __REV(uint32_t value);                      */
 498 /* intrinsic uint32_t __REVSH(uint32_t value);                    */
 499 /* intrinsic unsigned long __STREX(unsigned long, unsigned long); */
 500 /* intrinsic unsigned long __LDREX(unsigned long *);              */
 501
 502
 503 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
 504 /* GNU gcc specific functions */
 505
 506 static __INLINE void __enable_irq()               { __ASM volatile ("cpsie i"); }
 507 static __INLINE void __disable_irq()              { __ASM volatile ("cpsid i"); }
 508
 509 static __INLINE void __enable_fault_irq()         { __ASM volatile ("cpsie f"); }
 510 static __INLINE void __disable_fault_irq()        { __ASM volatile ("cpsid f"); }
 511
 512 static __INLINE void __NOP()                      { __ASM volatile ("nop"); }
 513 static __INLINE void __WFI()                      { __ASM volatile ("wfi"); }
 514 static __INLINE void __WFE()                      { __ASM volatile ("wfe"); }
 515 static __INLINE void __SEV()                      { __ASM volatile ("sev"); }
 516 static __INLINE void __ISB()                      { __ASM volatile ("isb"); }
 517 static __INLINE void __DSB()                      { __ASM volatile ("dsb"); }
 518 static __INLINE void __DMB()                      { __ASM volatile ("dmb"); }
 519 static __INLINE void __CLREX()                    { __ASM volatile ("clrex"); }
 520
 521
 522 #elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
 523 /* TASKING carm specific functions */
 524
 525 /*
 526  * The CMSIS functions have been implemented as intrinsics in the compiler.
 527  * Please use "carm -?i" to get an up to date list of all instrinsics,
 528  * Including the CMSIS ones.
 529  */
 530
 531 #endif
 532
 533
 534
 535 /* ##########################   NVIC functions  #################################### */
 536
 537
 538 /**
 539  * @brief  Set the Priority Grouping in NVIC Interrupt Controller
 540  *
 541  * @param  uint32_t priority_grouping is priority grouping field
 542  * @return none
 543  *
 544  * Set the priority grouping field using the required unlock sequence.
 545  * The parameter priority_grouping is assigned to the field
 546  * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.
 547  * In case of a conflict between priority grouping and available
 548  * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
 549  */
 550 static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
 551 {
 552   uint32_t reg_value;
 553   uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);                         /* only values 0..7 are used          */
 554
 555   reg_value  = SCB->AIRCR;                                                    /* read old register configuration    */
 556   reg_value &= ~((0xFFFFU << 16) | (0x0F << 8));                              /* clear bits to change               */
 557   reg_value  = ((reg_value | NVIC_AIRCR_VECTKEY | (PriorityGroupTmp << 8)));  /* Insert write key and priorty group */
 558   SCB->AIRCR = reg_value;
 559 }
 560
 561 /**
 562  * @brief  Get the Priority Grouping from NVIC Interrupt Controller
 563  *
 564  * @param  none
 565  * @return uint32_t   priority grouping field
 566  *
 567  * Get the priority grouping from NVIC Interrupt Controller.
 568  * priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
 569  */
 570 static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
 571 {
 572   return ((SCB->AIRCR >> 8) & 0x07);                                          /* read priority grouping field */
 573 }
 574
 575 /**
 576  * @brief  Enable Interrupt in NVIC Interrupt Controller
 577  *
 578  * @param  IRQn_Type IRQn specifies the interrupt number
 579  * @return none
 580  *
 581  * Enable a device specific interupt in the NVIC interrupt controller.
 582  * The interrupt number cannot be a negative value.
 583  */
 584 static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
 585 {
 586   NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
 587 }
 588
 589 /**
 590  * @brief  Disable the interrupt line for external interrupt specified
 591  *
 592  * @param  IRQn_Type IRQn is the positive number of the external interrupt
 593  * @return none
 594  *
 595  * Disable a device specific interupt in the NVIC interrupt controller.
 596  * The interrupt number cannot be a negative value.
 597  */
 598 static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
 599 {
 600   NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
 601 }
 602
 603 /**
 604  * @brief  Read the interrupt pending bit for a device specific interrupt source
 605  *
 606  * @param  IRQn_Type IRQn is the number of the device specifc interrupt
 607  * @return uint32_t 1 if pending interrupt else 0
 608  *
 609  * Read the pending register in NVIC and return 1 if its status is pending,
 610  * otherwise it returns 0
 611  */
 612 static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
 613 {
 614   return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
 615 }
 616
 617 /**
 618  * @brief  Set the pending bit for an external interrupt
 619  *
 620  * @param  IRQn_Type IRQn is the Number of the interrupt
 621  * @return none
 622  *
 623  * Set the pending bit for the specified interrupt.
 624  * The interrupt number cannot be a negative value.
 625  */
 626 static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
 627 {
 628   NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
 629 }
 630
 631 /**
 632  * @brief  Clear the pending bit for an external interrupt
 633  *
 634  * @param  IRQn_Type IRQn is the Number of the interrupt
 635  * @return none
 636  *
 637  * Clear the pending bit for the specified interrupt.
 638  * The interrupt number cannot be a negative value.
 639  */
 640 static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
 641 {
 642   NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
 643 }
 644
 645 /**
 646  * @brief  Read the active bit for an external interrupt
 647  *
 648  * @param  IRQn_Type  IRQn is the Number of the interrupt
 649  * @return uint32_t   1 if active else 0
 650  *
 651  * Read the active register in NVIC and returns 1 if its status is active,
 652  * otherwise it returns 0.
 653  */
 654 static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
 655 {
 656   return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
 657 }
 658
 659 /**
 660  * @brief  Set the priority for an interrupt
 661  *
 662  * @param  IRQn_Type IRQn is the Number of the interrupt
 663  * @param  priority is the priority for the interrupt
 664  * @return none
 665  *
 666  * Set the priority for the specified interrupt. The interrupt
 667  * number can be positive to specify an external (device specific)
 668  * interrupt, or negative to specify an internal (core) interrupt. \n
 669  *
 670  * Note: The priority cannot be set for every core interrupt.
 671  */
 672 static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
 673 {
 674   if(IRQn < 0) {
 675     SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */
 676   else {
 677     NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts      */
 678 }
 679
 680 /**
 681  * @brief  Read the priority for an interrupt
 682  *
 683  * @param  IRQn_Type IRQn is the Number of the interrupt
 684  * @return uint32_t  priority is the priority for the interrupt
 685  *
 686  * Read the priority for the specified interrupt. The interrupt
 687  * number can be positive to specify an external (device specific)
 688  * interrupt, or negative to specify an internal (core) interrupt.
 689  *
 690  * The returned priority value is automatically aligned to the implemented
 691  * priority bits of the microcontroller.
 692  *
 693  * Note: The priority cannot be set for every core interrupt.
 694  */
 695 static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
 696 {
 697
 698   if(IRQn < 0) {
 699     return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M3 system interrupts */
 700   else {
 701     return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
 702 }
 703
 704
 705 /**
 706  * @brief  Encode the priority for an interrupt
 707  *
 708  * @param  uint32_t PriorityGroup   is the used priority group
 709  * @param  uint32_t PreemptPriority is the preemptive priority value (starting from 0)
 710  * @param  uint32_t SubPriority     is the sub priority value (starting from 0)
 711  * @return uint32_t                    the priority for the interrupt
 712  *
 713  * Encode the priority for an interrupt with the given priority group,
 714  * preemptive priority value and sub priority value.
 715  * In case of a conflict between priority grouping and available
 716  * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
 717  *
 718  * The returned priority value can be used for NVIC_SetPriority(...) function
 719  */
 720 static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
 721 {
 722   uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);                         /* only values 0..7 are used          */
 723   uint32_t PreemptPriorityBits;
 724   uint32_t SubPriorityBits;
 725
 726   PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
 727   SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
 728
 729   return (
 730            ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
 731            ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
 732          );
 733 }
 734
 735
 736 /**
 737  * @brief  Decode the priority of an interrupt
 738  *
 739  * @param  uint32_t   Priority       the priority for the interrupt
 740  * @param  uint32_t   PrioGroup   is the used priority group
 741  * @param  uint32_t* pPreemptPrio is the preemptive priority value (starting from 0)
 742  * @param  uint32_t* pSubPrio     is the sub priority value (starting from 0)
 743  * @return none
 744  *
 745  * Decode an interrupt priority value with the given priority group to
 746  * preemptive priority value and sub priority value.
 747  * In case of a conflict between priority grouping and available
 748  * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
 749  *
 750  * The priority value can be retrieved with NVIC_GetPriority(...) function
 751  */
 752 static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
 753 {
 754   uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);                         /* only values 0..7 are used          */
 755   uint32_t PreemptPriorityBits;
 756   uint32_t SubPriorityBits;
 757
 758   PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
 759   SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
 760
 761   *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
 762   *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
 763 }
 764
 765
 766
 767 /* ##################################    SysTick function  ############################################ */
 768
 769 #if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)
 770
 771 /* SysTick constants */
 772 #define SYSTICK_ENABLE              0                                          /* Config-Bit to start or stop the SysTick Timer                         */
 773 #define SYSTICK_TICKINT             1                                          /* Config-Bit to enable or disable the SysTick interrupt                 */
 774 #define SYSTICK_CLKSOURCE           2                                          /* Clocksource has the offset 2 in SysTick Control and Status Register   */
 775 #define SYSTICK_MAXCOUNT       ((1<<24) -1)                                    /* SysTick MaxCount                                                      */
 776
 777 /**
 778  * @brief  Initialize and start the SysTick counter and its interrupt.
 779  *
 780  * @param  uint32_t ticks is the number of ticks between two interrupts
 781  * @return  none
 782  *
 783  * Initialise the system tick timer and its interrupt and start the
 784  * system tick timer / counter in free running mode to generate
 785  * periodical interrupts.
 786  *
 787  * NOTE: Modified for Smoothie by adding enable_irq argument.
 788  * Currently used by Spindle module.
 789  */
 790 static __INLINE uint32_t SysTick_Config(uint32_t ticks, bool enable_irq)
 791 {
 792   if (ticks > SYSTICK_MAXCOUNT)  return (1);                                             /* Reload value impossible */
 793
 794   SysTick->LOAD  =  ticks;                                      /* set reload register */
 795   SysTick->VAL   =  (0x00);                                                              /* Load the SysTick Counter Value */
 796   SysTick->CTRL = (1 << SYSTICK_CLKSOURCE) | (1<<SYSTICK_ENABLE); /* Enable SysTick IRQ and SysTick Timer */
 797
 798   if (enable_irq)
 799   {
 800     NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);                            /* set Priority for Cortex-M0 System Interrupts */
 801     SysTick->CTRL |= (1<<SYSTICK_TICKINT);
 802   }
 803
 804   return (0);                                                                            /* Function successful */
 805 }
 806
 807 #endif
 808
 809
 810
 811
 812
 813 /* ##################################    Reset function  ############################################ */
 814
 815 /**
 816  * @brief  Initiate a system reset request.
 817  *
 818  * @param   none
 819  * @return  none
 820  *
 821  * Initialize a system reset request to reset the MCU
 822  */
 823 static __INLINE void NVIC_SystemReset(void)
 824 {
 825   SCB->AIRCR  = (NVIC_AIRCR_VECTKEY | (SCB->AIRCR & (0x700)) | (1<<NVIC_SYSRESETREQ)); /* Keep priority group unchanged */
 826   __DSB();                                                                             /* Ensure completion of memory access */
 827   while(1);                                                                            /* wait until reset */
 828 }
 829
 830
 831 /* ##################################### Debug In/Output function ########################################### */
 832
 833 extern volatile int ITM_RxBuffer;                    /* variable to receive characters                             */
 834 #define             ITM_RXBUFFER_EMPTY    0x5AA55AA5 /* value identifying ITM_RxBuffer is ready for next character */
 835
 836
 837 /**
 838  * @brief  Outputs a character via the ITM channel 0
 839  *
 840  * @param   uint32_t character to output
 841  * @return  uint32_t input character
 842  *
 843  * The function outputs a character via the ITM channel 0.
 844  * The function returns when no debugger is connected that has booked the output.
 845  * It is blocking when a debugger is connected, but the previous character send is not transmitted.
 846  */
 847 static __INLINE uint32_t ITM_SendChar (uint32_t ch)
 848 {
 849   if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA)  &&
 850       (ITM->TCR & ITM_TCR_ITMENA)                  &&
 851       (ITM->TER & (1UL << 0))  )
 852   {
 853     while (ITM->PORT[0].u32 == 0);
 854     ITM->PORT[0].u8 = (uint8_t) ch;
 855   }
 856   return (ch);
 857 }
 858
 859
 860 /**
 861  * @brief  Inputs a character via variable ITM_RxBuffer
 862  *
 863  * @param   none
 864  * @return  uint32_t input character
 865  *
 866  * The function inputs a character via variable ITM_RxBuffer.
 867  * The function returns when no debugger is connected that has booked the output.
 868  * It is blocking when a debugger is connected, but the previous character send is not transmitted.
 869  */
 870 static __INLINE int ITM_ReceiveChar (void) {
 871   int ch = -1;                               /* no character available */
 872
 873   if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
 874     ch = ITM_RxBuffer;
 875     ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
 876   }
 877
 878   return (ch);
 879 }
 880
 881
 882 /**
 883  * @brief  Check if  a character via variable ITM_RxBuffer is available
 884  *
 885  * @param   none
 886  * @return  int  1 = character available, 0 = no character available
 887  *
 888  * The function checks  variable ITM_RxBuffer whether a character is available or not.
 889  * The function returns '1' if a character is available and '0' if no character is available.
 890  */
 891 static __INLINE int ITM_CheckChar (void) {
 892
 893   if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
 894     return (0);                                 /* no character available */
 895   } else {
 896     return (1);                                 /*    character available */
 897   }
 898 }
 899
 900
 901
 902 #ifdef __cplusplus
 903 }
 904 #endif
 905
 906 #endif /* __CM3_CORE_H__ */
 907
 908 /*lint -restore */