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172d42d9 AG |
1 | ;/***************************************************************************** |
2 | ; * @file: startup_LPC17xx.s | |
3 | ; * @purpose: CMSIS Cortex-M3 Core Device Startup File | |
4 | ; * for the NXP LPC17xx Device Series | |
5 | ; * @version: V1.02, modified for mbed | |
6 | ; * @date: 27. July 2009, modified 3rd Aug 2009 | |
7 | ; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ | |
8 | ; * | |
9 | ; * Copyright (C) 2009 ARM Limited. All rights reserved. | |
10 | ; * ARM Limited (ARM) is supplying this software for use with Cortex-M3 | |
11 | ; * processor based microcontrollers. This file can be freely distributed | |
12 | ; * within development tools that are supporting such ARM based processors. | |
13 | ; * | |
14 | ; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED | |
15 | ; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF | |
16 | ; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. | |
17 | ; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR | |
18 | ; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. | |
19 | ; * | |
20 | ; *****************************************************************************/ | |
21 | ||
22 | Stack_Size EQU 0x00000400 | |
23 | ||
24 | AREA STACK, NOINIT, READWRITE, ALIGN=3 | |
25 | EXPORT __initial_sp | |
26 | ||
27 | Stack_Mem SPACE Stack_Size | |
28 | __initial_sp EQU 0x10008000 ; Top of RAM from LPC1768 | |
29 | ||
30 | ||
31 | Heap_Size EQU 0x00000000 | |
32 | ||
33 | AREA HEAP, NOINIT, READWRITE, ALIGN=3 | |
34 | EXPORT __heap_base | |
35 | EXPORT __heap_limit | |
36 | ||
37 | __heap_base | |
38 | Heap_Mem SPACE Heap_Size | |
39 | __heap_limit | |
40 | ||
41 | PRESERVE8 | |
42 | THUMB | |
43 | ||
44 | ; Vector Table Mapped to Address 0 at Reset | |
45 | ||
46 | AREA RESET, DATA, READONLY | |
47 | EXPORT __Vectors | |
48 | ||
49 | __Vectors DCD __initial_sp ; Top of Stack | |
50 | DCD Reset_Handler ; Reset Handler | |
51 | DCD NMI_Handler ; NMI Handler | |
52 | DCD HardFault_Handler ; Hard Fault Handler | |
53 | DCD MemManage_Handler ; MPU Fault Handler | |
54 | DCD BusFault_Handler ; Bus Fault Handler | |
55 | DCD UsageFault_Handler ; Usage Fault Handler | |
56 | DCD 0 ; Reserved | |
57 | DCD 0 ; Reserved | |
58 | DCD 0 ; Reserved | |
59 | DCD 0 ; Reserved | |
60 | DCD SVC_Handler ; SVCall Handler | |
61 | DCD DebugMon_Handler ; Debug Monitor Handler | |
62 | DCD 0 ; Reserved | |
63 | DCD PendSV_Handler ; PendSV Handler | |
64 | DCD SysTick_Handler ; SysTick Handler | |
65 | ||
66 | ; External Interrupts | |
67 | DCD WDT_IRQHandler ; 16: Watchdog Timer | |
68 | DCD TIMER0_IRQHandler ; 17: Timer0 | |
69 | DCD TIMER1_IRQHandler ; 18: Timer1 | |
70 | DCD TIMER2_IRQHandler ; 19: Timer2 | |
71 | DCD TIMER3_IRQHandler ; 20: Timer3 | |
72 | DCD UART0_IRQHandler ; 21: UART0 | |
73 | DCD UART1_IRQHandler ; 22: UART1 | |
74 | DCD UART2_IRQHandler ; 23: UART2 | |
75 | DCD UART3_IRQHandler ; 24: UART3 | |
76 | DCD PWM1_IRQHandler ; 25: PWM1 | |
77 | DCD I2C0_IRQHandler ; 26: I2C0 | |
78 | DCD I2C1_IRQHandler ; 27: I2C1 | |
79 | DCD I2C2_IRQHandler ; 28: I2C2 | |
80 | DCD SPI_IRQHandler ; 29: SPI | |
81 | DCD SSP0_IRQHandler ; 30: SSP0 | |
82 | DCD SSP1_IRQHandler ; 31: SSP1 | |
83 | DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL) | |
84 | DCD RTC_IRQHandler ; 33: Real Time Clock | |
85 | DCD EINT0_IRQHandler ; 34: External Interrupt 0 | |
86 | DCD EINT1_IRQHandler ; 35: External Interrupt 1 | |
87 | DCD EINT2_IRQHandler ; 36: External Interrupt 2 | |
88 | DCD EINT3_IRQHandler ; 37: External Interrupt 3 | |
89 | DCD ADC_IRQHandler ; 38: A/D Converter | |
90 | DCD BOD_IRQHandler ; 39: Brown-Out Detect | |
91 | DCD USB_IRQHandler ; 40: USB | |
92 | DCD CAN_IRQHandler ; 41: CAN | |
93 | DCD DMA_IRQHandler ; 42: General Purpose DMA | |
94 | DCD I2S_IRQHandler ; 43: I2S | |
95 | DCD ENET_IRQHandler ; 44: Ethernet | |
96 | DCD RIT_IRQHandler ; 45: Repetitive Interrupt Timer | |
97 | DCD MCPWM_IRQHandler ; 46: Motor Control PWM | |
98 | DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface | |
99 | DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL) | |
100 | ||
101 | ||
102 | IF :LNOT::DEF:NO_CRP | |
103 | AREA |.ARM.__at_0x02FC|, CODE, READONLY | |
104 | CRP_Key DCD 0xFFFFFFFF | |
105 | ENDIF | |
106 | ||
107 | ||
108 | AREA |.text|, CODE, READONLY | |
109 | ||
110 | ||
111 | ; Reset Handler | |
112 | ||
113 | Reset_Handler PROC | |
114 | EXPORT Reset_Handler [WEAK] | |
115 | IMPORT SystemInit | |
116 | IMPORT __main | |
117 | LDR R0, =SystemInit | |
118 | BLX R0 | |
119 | LDR R0, =__main | |
120 | BX R0 | |
121 | ENDP | |
122 | ||
123 | ||
124 | ; Dummy Exception Handlers (infinite loops which can be modified) | |
125 | ||
126 | NMI_Handler PROC | |
127 | EXPORT NMI_Handler [WEAK] | |
128 | B . | |
129 | ENDP | |
130 | HardFault_Handler\ | |
131 | PROC | |
132 | EXPORT HardFault_Handler [WEAK] | |
133 | B . | |
134 | ENDP | |
135 | MemManage_Handler\ | |
136 | PROC | |
137 | EXPORT MemManage_Handler [WEAK] | |
138 | B . | |
139 | ENDP | |
140 | BusFault_Handler\ | |
141 | PROC | |
142 | EXPORT BusFault_Handler [WEAK] | |
143 | B . | |
144 | ENDP | |
145 | UsageFault_Handler\ | |
146 | PROC | |
147 | EXPORT UsageFault_Handler [WEAK] | |
148 | B . | |
149 | ENDP | |
150 | SVC_Handler PROC | |
151 | EXPORT SVC_Handler [WEAK] | |
152 | B . | |
153 | ENDP | |
154 | DebugMon_Handler\ | |
155 | PROC | |
156 | EXPORT DebugMon_Handler [WEAK] | |
157 | B . | |
158 | ENDP | |
159 | PendSV_Handler PROC | |
160 | EXPORT PendSV_Handler [WEAK] | |
161 | B . | |
162 | ENDP | |
163 | SysTick_Handler PROC | |
164 | EXPORT SysTick_Handler [WEAK] | |
165 | B . | |
166 | ENDP | |
167 | ||
168 | Default_Handler PROC | |
169 | ||
170 | EXPORT WDT_IRQHandler [WEAK] | |
171 | EXPORT TIMER0_IRQHandler [WEAK] | |
172 | EXPORT TIMER1_IRQHandler [WEAK] | |
173 | EXPORT TIMER2_IRQHandler [WEAK] | |
174 | EXPORT TIMER3_IRQHandler [WEAK] | |
175 | EXPORT UART0_IRQHandler [WEAK] | |
176 | EXPORT UART1_IRQHandler [WEAK] | |
177 | EXPORT UART2_IRQHandler [WEAK] | |
178 | EXPORT UART3_IRQHandler [WEAK] | |
179 | EXPORT PWM1_IRQHandler [WEAK] | |
180 | EXPORT I2C0_IRQHandler [WEAK] | |
181 | EXPORT I2C1_IRQHandler [WEAK] | |
182 | EXPORT I2C2_IRQHandler [WEAK] | |
183 | EXPORT SPI_IRQHandler [WEAK] | |
184 | EXPORT SSP0_IRQHandler [WEAK] | |
185 | EXPORT SSP1_IRQHandler [WEAK] | |
186 | EXPORT PLL0_IRQHandler [WEAK] | |
187 | EXPORT RTC_IRQHandler [WEAK] | |
188 | EXPORT EINT0_IRQHandler [WEAK] | |
189 | EXPORT EINT1_IRQHandler [WEAK] | |
190 | EXPORT EINT2_IRQHandler [WEAK] | |
191 | EXPORT EINT3_IRQHandler [WEAK] | |
192 | EXPORT ADC_IRQHandler [WEAK] | |
193 | EXPORT BOD_IRQHandler [WEAK] | |
194 | EXPORT USB_IRQHandler [WEAK] | |
195 | EXPORT CAN_IRQHandler [WEAK] | |
196 | EXPORT DMA_IRQHandler [WEAK] | |
197 | EXPORT I2S_IRQHandler [WEAK] | |
198 | EXPORT ENET_IRQHandler [WEAK] | |
199 | EXPORT RIT_IRQHandler [WEAK] | |
200 | EXPORT MCPWM_IRQHandler [WEAK] | |
201 | EXPORT QEI_IRQHandler [WEAK] | |
202 | EXPORT PLL1_IRQHandler [WEAK] | |
203 | ||
204 | WDT_IRQHandler | |
205 | TIMER0_IRQHandler | |
206 | TIMER1_IRQHandler | |
207 | TIMER2_IRQHandler | |
208 | TIMER3_IRQHandler | |
209 | UART0_IRQHandler | |
210 | UART1_IRQHandler | |
211 | UART2_IRQHandler | |
212 | UART3_IRQHandler | |
213 | PWM1_IRQHandler | |
214 | I2C0_IRQHandler | |
215 | I2C1_IRQHandler | |
216 | I2C2_IRQHandler | |
217 | SPI_IRQHandler | |
218 | SSP0_IRQHandler | |
219 | SSP1_IRQHandler | |
220 | PLL0_IRQHandler | |
221 | RTC_IRQHandler | |
222 | EINT0_IRQHandler | |
223 | EINT1_IRQHandler | |
224 | EINT2_IRQHandler | |
225 | EINT3_IRQHandler | |
226 | ADC_IRQHandler | |
227 | BOD_IRQHandler | |
228 | USB_IRQHandler | |
229 | CAN_IRQHandler | |
230 | DMA_IRQHandler | |
231 | I2S_IRQHandler | |
232 | ENET_IRQHandler | |
233 | RIT_IRQHandler | |
234 | MCPWM_IRQHandler | |
235 | QEI_IRQHandler | |
236 | PLL1_IRQHandler | |
237 | ||
238 | B . | |
239 | ||
240 | ENDP | |
241 | ||
242 | ALIGN | |
243 | END |