HCoop / bpt / guile.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge remote-tracking branch 'origin/stable-2.0'
[bpt/guile.git] / libguile / vm-i-scheme.c
CommitLineData
776491ca 1/* Copyright (C) 2001, 2009, 2010, 2011, 2012, 2013 Free Software Foundation, Inc.
a98cef7e 2 *
560b9c25 3 * This library is free software; you can redistribute it and/or
53befeb7
NJ		 4 * modify it under the terms of the GNU Lesser General Public License
5 * as published by the Free Software Foundation; either version 3 of
6 * the License, or (at your option) any later version.
a98cef7e 7 *
53befeb7
NJ		 8 * This library is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
560b9c25
AW		 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * Lesser General Public License for more details.
a98cef7e 12 *
560b9c25
AW		 13 * You should have received a copy of the GNU Lesser General Public
14 * License along with this library; if not, write to the Free Software
53befeb7
NJ		 15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
16 * 02110-1301 USA
560b9c25 17 */
a98cef7e
KN		 18
19/* This file is included in vm_engine.c */
20
a80be762
KN		 21\f
22/*
23 * Predicates
24 */
25
93d197be 26#define ARGS1(a1) SCM a1 = sp[0];
11ea1aba
AW		 27#define ARGS2(a1,a2) SCM a1 = sp[-1], a2 = sp[0]; sp--; NULLSTACK (1);
28#define ARGS3(a1,a2,a3) SCM a1 = sp[-2], a2 = sp[-1], a3 = sp[0]; sp -= 2; NULLSTACK (2);
93d197be
AW		 29
30#define RETURN(x) do { *sp = x; NEXT; } while (0)
31
827dc8dc 32VM_DEFINE_FUNCTION (128, not, "not", 1)
a98cef7e 33{
a80be762 34 ARGS1 (x);
2533f10b 35 RETURN (scm_from_bool (scm_is_false (x)));
17e90c5e
KN		 36}
37
827dc8dc 38VM_DEFINE_FUNCTION (129, not_not, "not-not", 1)
17e90c5e 39{
a80be762 40 ARGS1 (x);
2533f10b 41 RETURN (scm_from_bool (!scm_is_false (x)));
17e90c5e
KN		 42}
43
827dc8dc 44VM_DEFINE_FUNCTION (130, eq, "eq?", 2)
17e90c5e 45{
a80be762 46 ARGS2 (x, y);
5c8cefe5 47 RETURN (scm_from_bool (scm_is_eq (x, y)));
17e90c5e
KN		 48}
49
827dc8dc 50VM_DEFINE_FUNCTION (131, not_eq, "not-eq?", 2)
17e90c5e 51{
a80be762 52 ARGS2 (x, y);
5c8cefe5 53 RETURN (scm_from_bool (!scm_is_eq (x, y)));
17e90c5e
KN		 54}
55
827dc8dc 56VM_DEFINE_FUNCTION (132, nullp, "null?", 1)
17e90c5e 57{
a80be762 58 ARGS1 (x);
2533f10b 59 RETURN (scm_from_bool (scm_is_null (x)));
a98cef7e
KN		 60}
61
827dc8dc 62VM_DEFINE_FUNCTION (133, not_nullp, "not-null?", 1)
a98cef7e 63{
a80be762 64 ARGS1 (x);
2533f10b 65 RETURN (scm_from_bool (!scm_is_null (x)));
a80be762
KN		 66}
67
9348168e
BT		 68VM_DEFINE_FUNCTION (134, nilp, "nil?", 1)
69{
70 ARGS1 (x);
71 RETURN (scm_from_bool (scm_is_lisp_false (x)));
72}
73
74VM_DEFINE_FUNCTION (135, not_nilp, "not-nil?", 1)
75{
76 ARGS1 (x);
77 RETURN (scm_from_bool (!scm_is_lisp_false (x)));
78}
79
80VM_DEFINE_FUNCTION (136, eqv, "eqv?", 2)
a80be762
KN		 81{
82 ARGS2 (x, y);
5c8cefe5 83 if (scm_is_eq (x, y))
a80be762
KN		 84 RETURN (SCM_BOOL_T);
85 if (SCM_IMP (x) || SCM_IMP (y))
86 RETURN (SCM_BOOL_F);
1865ad56 87 SYNC_REGISTER ();
a80be762
KN		 88 RETURN (scm_eqv_p (x, y));
89}
90
9348168e 91VM_DEFINE_FUNCTION (137, equal, "equal?", 2)
a80be762
KN		 92{
93 ARGS2 (x, y);
5c8cefe5 94 if (scm_is_eq (x, y))
a80be762
KN		 95 RETURN (SCM_BOOL_T);
96 if (SCM_IMP (x) || SCM_IMP (y))
97 RETURN (SCM_BOOL_F);
1865ad56 98 SYNC_REGISTER ();
a80be762 99 RETURN (scm_equal_p (x, y));
a98cef7e
KN		 100}
101
9348168e 102VM_DEFINE_FUNCTION (138, pairp, "pair?", 1)
a98cef7e 103{
a80be762 104 ARGS1 (x);
5c8cefe5 105 RETURN (scm_from_bool (scm_is_pair (x)));
a98cef7e
KN		 106}
107
9348168e 108VM_DEFINE_FUNCTION (139, listp, "list?", 1)
a98cef7e 109{
a80be762 110 ARGS1 (x);
9bd48cb1 111 RETURN (scm_from_bool (scm_ilength (x) >= 0));
a98cef7e
KN		 112}
113
9348168e 114VM_DEFINE_FUNCTION (140, symbolp, "symbol?", 1)
cf45ff03
AW		 115{
116 ARGS1 (x);
117 RETURN (scm_from_bool (scm_is_symbol (x)));
118}
119
9348168e 120VM_DEFINE_FUNCTION (141, vectorp, "vector?", 1)
cf45ff03
AW		 121{
122 ARGS1 (x);
123 RETURN (scm_from_bool (SCM_I_IS_VECTOR (x)));
124}
125
a80be762
KN		 126\f
127/*
128 * Basic data
129 */
130
9348168e 131VM_DEFINE_FUNCTION (142, cons, "cons", 2)
a98cef7e 132{
a80be762 133 ARGS2 (x, y);
52182d52
AW		 134 SYNC_BEFORE_GC ();
135 x = scm_cons (x, y);
a80be762 136 RETURN (x);
a98cef7e
KN		 137}
138
41e49280 139#define VM_VALIDATE_CONS(x, proc) \
53bdfcf0 140 VM_ASSERT (scm_is_pair (x), vm_error_not_a_pair (proc, x))
5e390de6 141
9348168e 142VM_DEFINE_FUNCTION (143, car, "car", 1)
a98cef7e 143{
a80be762 144 ARGS1 (x);
41e49280 145 VM_VALIDATE_CONS (x, "car");
a80be762 146 RETURN (SCM_CAR (x));
a98cef7e
KN		 147}
148
9348168e 149VM_DEFINE_FUNCTION (144, cdr, "cdr", 1)
a98cef7e 150{
a80be762 151 ARGS1 (x);
41e49280 152 VM_VALIDATE_CONS (x, "cdr");
a80be762 153 RETURN (SCM_CDR (x));
a98cef7e
KN		 154}
155
9348168e 156VM_DEFINE_INSTRUCTION (145, set_car, "set-car!", 0, 2, 0)
a98cef7e 157{
60ed31d2 158 SCM x, y;
eae2438d 159 POP2 (y, x);
41e49280 160 VM_VALIDATE_CONS (x, "set-car!");
a80be762 161 SCM_SETCAR (x, y);
60ed31d2 162 NEXT;
a98cef7e
KN		 163}
164
9348168e 165VM_DEFINE_INSTRUCTION (146, set_cdr, "set-cdr!", 0, 2, 0)
a98cef7e 166{
60ed31d2 167 SCM x, y;
eae2438d 168 POP2 (y, x);
41e49280 169 VM_VALIDATE_CONS (x, "set-cdr!");
a80be762 170 SCM_SETCDR (x, y);
60ed31d2 171 NEXT;
a98cef7e
KN		 172}
173
a80be762
KN		 174\f
175/*
176 * Numeric relational tests
177 */
178
b2b33168
AW		 179#define REL(crel,srel) \
180 { \
181 ARGS2 (x, y); \
182 if (SCM_I_INUMP (x) && SCM_I_INUMP (y)) \
183 RETURN (scm_from_bool (((scm_t_signed_bits) SCM_UNPACK (x)) \
184 crel ((scm_t_signed_bits) SCM_UNPACK (y)))); \
185 SYNC_REGISTER (); \
186 RETURN (srel (x, y)); \
187 }
a80be762 188
9348168e 189VM_DEFINE_FUNCTION (147, ee, "ee?", 2)
a80be762
KN		 190{
191 REL (==, scm_num_eq_p);
192}
193
9348168e 194VM_DEFINE_FUNCTION (148, lt, "lt?", 2)
a80be762
KN		 195{
196 REL (<, scm_less_p);
197}
198
9348168e 199VM_DEFINE_FUNCTION (149, le, "le?", 2)
a80be762
KN		 200{
201 REL (<=, scm_leq_p);
202}
203
9348168e 204VM_DEFINE_FUNCTION (150, gt, "gt?", 2)
a80be762
KN		 205{
206 REL (>, scm_gr_p);
207}
208
9348168e 209VM_DEFINE_FUNCTION (151, ge, "ge?", 2)
a80be762
KN		 210{
211 REL (>=, scm_geq_p);
212}
213
a0ec1ca1
AW		 214#undef REL
215
a80be762
KN		 216\f
217/*
218 * Numeric functions
219 */
220
e78d4bf9 221/* The maximum/minimum tagged integers. */
478fa0d5
MW		 222#define INUM_MAX \
223 ((scm_t_signed_bits) SCM_UNPACK (SCM_I_MAKINUM (SCM_MOST_POSITIVE_FIXNUM)))
224#define INUM_MIN \
225 ((scm_t_signed_bits) SCM_UNPACK (SCM_I_MAKINUM (SCM_MOST_NEGATIVE_FIXNUM)))
cb1482e7
MW		 226#define INUM_STEP \
227 ((scm_t_signed_bits) SCM_UNPACK (SCM_INUM1) \
228 - (scm_t_signed_bits) SCM_UNPACK (SCM_INUM0))
e78d4bf9 229
a80be762
KN		 230#define FUNC2(CFUNC,SFUNC) \
231{ \
d8eeb67c 232 ARGS2 (x, y); \
2d80426a 233 if (SCM_I_INUMP (x) && SCM_I_INUMP (y)) \
a80be762 234 { \
c0ee3245 235 scm_t_int64 n = SCM_I_INUM (x) CFUNC SCM_I_INUM (y);\
a80be762 236 if (SCM_FIXABLE (n)) \
2d80426a 237 RETURN (SCM_I_MAKINUM (n)); \
a80be762 238 } \
b2642276 239 SYNC_REGISTER (); \
a80be762
KN		 240 RETURN (SFUNC (x, y)); \
241}
242
0c57673a
LC		 243/* Assembly tagged integer arithmetic routines. This code uses the
244 `asm goto' feature introduced in GCC 4.5. */
245
9f621170
MW		 246#if SCM_GNUC_PREREQ (4, 5) && (defined __x86_64__ || defined __i386__)
247
248# undef _CX
249# ifdef __x86_64__
250# define _CX "rcx"
251# else
252# define _CX "ecx"
253# endif
0c57673a
LC		 254
255/* The macros below check the CPU's overflow flag to improve fixnum
9f621170
MW		 256 arithmetic. The _CX register (%rcx or %ecx) is explicitly
257 clobbered because `asm goto' can't have outputs, in which case the
258 `r' constraint could be used to let the register allocator choose a
259 register.
0c57673a
LC		 260
261 TODO: Use `cold' label attribute in GCC 4.6.
262 http://gcc.gnu.org/ml/gcc-patches/2010-10/msg01777.html */
263
264# define ASM_ADD(x, y) \
265 { \
9f621170
MW		 266 asm volatile goto ("mov %1, %%"_CX"; " \
267 "test %[tag], %%cl; je %l[slow_add]; " \
268 "test %[tag], %0; je %l[slow_add]; " \
269 "sub %[tag], %%"_CX"; " \
270 "add %0, %%"_CX"; jo %l[slow_add]; " \
271 "mov %%"_CX", (%[vsp])\n" \
0c57673a
LC		 272 : /* no outputs */ \
273 : "r" (x), "r" (y), \
274 [vsp] "r" (sp), [tag] "i" (scm_tc2_int) \
48b6f151 275 : _CX, "memory", "cc" \
0c57673a
LC		 276 : slow_add); \
277 NEXT; \
278 } \
279 slow_add: \
280 do { } while (0)
281
282# define ASM_SUB(x, y) \
283 { \
9f621170
MW		 284 asm volatile goto ("mov %0, %%"_CX"; " \
285 "test %[tag], %%cl; je %l[slow_sub]; " \
286 "test %[tag], %1; je %l[slow_sub]; " \
287 "sub %1, %%"_CX"; jo %l[slow_sub]; " \
288 "add %[tag], %%"_CX"; " \
289 "mov %%"_CX", (%[vsp])\n" \
0c57673a
LC		 290 : /* no outputs */ \
291 : "r" (x), "r" (y), \
292 [vsp] "r" (sp), [tag] "i" (scm_tc2_int) \
48b6f151 293 : _CX, "memory", "cc" \
0c57673a
LC		 294 : slow_sub); \
295 NEXT; \
296 } \
297 slow_sub: \
298 do { } while (0)
299
4fa65b90
MW		 300# define ASM_MUL(x, y) \
301 { \
302 scm_t_signed_bits xx = SCM_I_INUM (x); \
303 asm volatile goto ("mov %1, %%"_CX"; " \
304 "test %[tag], %%cl; je %l[slow_mul]; " \
305 "sub %[tag], %%"_CX"; " \
306 "test %[tag], %0; je %l[slow_mul]; " \
307 "imul %2, %%"_CX"; jo %l[slow_mul]; " \
308 "add %[tag], %%"_CX"; " \
309 "mov %%"_CX", (%[vsp])\n" \
310 : /* no outputs */ \
311 : "r" (x), "r" (y), "r" (xx), \
312 [vsp] "r" (sp), [tag] "i" (scm_tc2_int) \
313 : _CX, "memory", "cc" \
314 : slow_mul); \
315 NEXT; \
316 } \
317 slow_mul: \
318 do { } while (0)
319
0c57673a
LC		 320#endif
321
f91a1864
MW		 322#if SCM_GNUC_PREREQ (4, 5) && defined __arm__
323
324# define ASM_ADD(x, y) \
325 if (SCM_LIKELY (SCM_I_INUMP (x) && SCM_I_INUMP (y))) \
326 { \
327 asm volatile goto ("adds r0, %0, %1; bvs %l[slow_add]; " \
328 "str r0, [%[vsp]]\n" \
329 : /* no outputs */ \
330 : "r" (x), "r" (y - scm_tc2_int), \
331 [vsp] "r" (sp) \
332 : "r0", "memory", "cc" \
333 : slow_add); \
334 NEXT; \
335 } \
336 slow_add: \
337 do { } while (0)
338
339# define ASM_SUB(x, y) \
340 if (SCM_LIKELY (SCM_I_INUMP (x) && SCM_I_INUMP (y))) \
341 { \
342 asm volatile goto ("subs r0, %0, %1; bvs %l[slow_sub]; " \
343 "str r0, [%[vsp]]\n" \
344 : /* no outputs */ \
345 : "r" (x), "r" (y - scm_tc2_int), \
346 [vsp] "r" (sp) \
347 : "r0", "memory", "cc" \
348 : slow_sub); \
349 NEXT; \
350 } \
351 slow_sub: \
352 do { } while (0)
353
afa3c37d
MW		 354# if defined (__ARM_ARCH_3M__) || defined (__ARM_ARCH_4__) \
355 || defined (__ARM_ARCH_4T__) || defined (__ARM_ARCH_5__) \
356 || defined (__ARM_ARCH_5T__) || defined (__ARM_ARCH_5E__) \
357 || defined (__ARM_ARCH_5TE__) || defined (__ARM_ARCH_5TEJ__) \
358 || defined (__ARM_ARCH_6__) || defined (__ARM_ARCH_6J__) \
359 || defined (__ARM_ARCH_6K__) || defined (__ARM_ARCH_6Z__) \
360 || defined (__ARM_ARCH_6ZK__) || defined (__ARM_ARCH_6T2__) \
361 || defined (__ARM_ARCH_6M__) || defined (__ARM_ARCH_7__) \
362 || defined (__ARM_ARCH_7A__) || defined (__ARM_ARCH_7R__) \
363 || defined (__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) \
364 || defined (__ARM_ARCH_8A__)
365
366/* The ARM architectures listed above support the SMULL instruction */
367
368# define ASM_MUL(x, y) \
f91a1864
MW		 369 if (SCM_LIKELY (SCM_I_INUMP (x) && SCM_I_INUMP (y))) \
370 { \
371 scm_t_signed_bits rlo, rhi; \
372 asm ("smull %0, %1, %2, %3\n" \
373 : "=r" (rlo), "=r" (rhi) \
374 : "r" (SCM_UNPACK (x) - scm_tc2_int), \
375 "r" (SCM_I_INUM (y))); \
376 if (SCM_LIKELY (SCM_SRS (rlo, 31) == rhi)) \
377 RETURN (SCM_PACK (rlo + scm_tc2_int)); \
378 } \
379 do { } while (0)
380
afa3c37d
MW		 381# endif
382
f91a1864 383#endif
0c57673a 384
9348168e 385VM_DEFINE_FUNCTION (152, add, "add", 2)
a80be762 386{
0c57673a 387#ifndef ASM_ADD
a80be762 388 FUNC2 (+, scm_sum);
0c57673a
LC		 389#else
390 ARGS2 (x, y);
391 ASM_ADD (x, y);
392 SYNC_REGISTER ();
393 RETURN (scm_sum (x, y));
394#endif
a80be762
KN		 395}
396
9348168e 397VM_DEFINE_FUNCTION (153, add1, "add1", 1)
7382f23e
AW		 398{
399 ARGS1 (x);
e78d4bf9 400
cb1482e7
MW		 401 /* Check for overflow. We must avoid overflow in the signed
402 addition below, even if X is not an inum. */
403 if (SCM_LIKELY ((scm_t_signed_bits) SCM_UNPACK (x) <= INUM_MAX - INUM_STEP))
7382f23e 404 {
e78d4bf9
LC		 405 SCM result;
406
cb1482e7
MW		 407 /* Add 1 to the integer without untagging. */
408 result = SCM_PACK ((scm_t_signed_bits) SCM_UNPACK (x) + INUM_STEP);
e78d4bf9
LC		 409
410 if (SCM_LIKELY (SCM_I_INUMP (result)))
411 RETURN (result);
7382f23e 412 }
e78d4bf9 413
7382f23e
AW		 414 SYNC_REGISTER ();
415 RETURN (scm_sum (x, SCM_I_MAKINUM (1)));
416}
417
9348168e 418VM_DEFINE_FUNCTION (154, sub, "sub", 2)
a80be762 419{
0c57673a 420#ifndef ASM_SUB
a80be762 421 FUNC2 (-, scm_difference);
0c57673a
LC		 422#else
423 ARGS2 (x, y);
424 ASM_SUB (x, y);
425 SYNC_REGISTER ();
426 RETURN (scm_difference (x, y));
427#endif
a80be762
KN		 428}
429
9348168e 430VM_DEFINE_FUNCTION (155, sub1, "sub1", 1)
7382f23e
AW		 431{
432 ARGS1 (x);
e78d4bf9 433
cb1482e7
MW		 434 /* Check for overflow. We must avoid overflow in the signed
435 subtraction below, even if X is not an inum. */
436 if (SCM_LIKELY ((scm_t_signed_bits) SCM_UNPACK (x) >= INUM_MIN + INUM_STEP))
7382f23e 437 {
e78d4bf9
LC		 438 SCM result;
439
cb1482e7
MW		 440 /* Substract 1 from the integer without untagging. */
441 result = SCM_PACK ((scm_t_signed_bits) SCM_UNPACK (x) - INUM_STEP);
e78d4bf9
LC		 442
443 if (SCM_LIKELY (SCM_I_INUMP (result)))
444 RETURN (result);
7382f23e 445 }
e78d4bf9 446
7382f23e
AW		 447 SYNC_REGISTER ();
448 RETURN (scm_difference (x, SCM_I_MAKINUM (1)));
449}
450
9348168e 451VM_DEFINE_FUNCTION (156, mul, "mul", 2)
a80be762
KN		 452{
453 ARGS2 (x, y);
4fa65b90
MW		 454#ifdef ASM_MUL
455 ASM_MUL (x, y);
456#endif
1865ad56 457 SYNC_REGISTER ();
a80be762
KN		 458 RETURN (scm_product (x, y));
459}
460
d8d7c7bf
MW		 461#undef ASM_ADD
462#undef ASM_SUB
463#undef ASM_MUL
464#undef FUNC2
465#undef INUM_MAX
466#undef INUM_MIN
467#undef INUM_STEP
4fa65b90 468
9348168e 469VM_DEFINE_FUNCTION (157, div, "div", 2)
a80be762
KN		 470{
471 ARGS2 (x, y);
1865ad56 472 SYNC_REGISTER ();
a80be762
KN		 473 RETURN (scm_divide (x, y));
474}
475
9348168e 476VM_DEFINE_FUNCTION (158, quo, "quo", 2)
a80be762
KN		 477{
478 ARGS2 (x, y);
1865ad56 479 SYNC_REGISTER ();
a80be762
KN		 480 RETURN (scm_quotient (x, y));
481}
482
9348168e 483VM_DEFINE_FUNCTION (159, rem, "rem", 2)
a80be762
KN		 484{
485 ARGS2 (x, y);
1865ad56 486 SYNC_REGISTER ();
a80be762
KN		 487 RETURN (scm_remainder (x, y));
488}
489
9348168e 490VM_DEFINE_FUNCTION (160, mod, "mod", 2)
a80be762
KN		 491{
492 ARGS2 (x, y);
1865ad56 493 SYNC_REGISTER ();
a80be762
KN		 494 RETURN (scm_modulo (x, y));
495}
496
9348168e 497VM_DEFINE_FUNCTION (161, ash, "ash", 2)
b10d9330
AW		 498{
499 ARGS2 (x, y);
500 if (SCM_I_INUMP (x) && SCM_I_INUMP (y))
501 {
502 if (SCM_I_INUM (y) < 0)
ca7b6f68
MW		 503 /* Right shift, will be a fixnum. */
504 RETURN (SCM_I_MAKINUM
505 (SCM_SRS (SCM_I_INUM (x),
506 (-SCM_I_INUM (y) <= SCM_I_FIXNUM_BIT-1)
507 ? -SCM_I_INUM (y) : SCM_I_FIXNUM_BIT-1)));
8ecd1943
AW		 508 else
509 /* Left shift. See comments in scm_ash. */
510 {
e25f3727 511 scm_t_signed_bits nn, bits_to_shift;
8ecd1943
AW		 512
513 nn = SCM_I_INUM (x);
514 bits_to_shift = SCM_I_INUM (y);
515
516 if (bits_to_shift < SCM_I_FIXNUM_BIT-1
e25f3727 517 && ((scm_t_bits)
8ecd1943
AW		 518 (SCM_SRS (nn, (SCM_I_FIXNUM_BIT-1 - bits_to_shift)) + 1)
519 <= 1))
520 RETURN (SCM_I_MAKINUM (nn << bits_to_shift));
521 /* fall through */
522 }
b10d9330
AW		 523 /* fall through */
524 }
525 SYNC_REGISTER ();
526 RETURN (scm_ash (x, y));
527}
528
9348168e 529VM_DEFINE_FUNCTION (162, logand, "logand", 2)
b10d9330
AW		 530{
531 ARGS2 (x, y);
532 if (SCM_I_INUMP (x) && SCM_I_INUMP (y))
b2df1682
MW		 533 /* Compute bitwise AND without untagging */
534 RETURN (SCM_PACK (SCM_UNPACK (x) & SCM_UNPACK (y)));
b10d9330
AW		 535 SYNC_REGISTER ();
536 RETURN (scm_logand (x, y));
537}
538
9348168e 539VM_DEFINE_FUNCTION (163, logior, "logior", 2)
b10d9330
AW		 540{
541 ARGS2 (x, y);
542 if (SCM_I_INUMP (x) && SCM_I_INUMP (y))
b2df1682
MW		 543 /* Compute bitwise OR without untagging */
544 RETURN (SCM_PACK (SCM_UNPACK (x) | SCM_UNPACK (y)));
b10d9330
AW		 545 SYNC_REGISTER ();
546 RETURN (scm_logior (x, y));
547}
548
9348168e 549VM_DEFINE_FUNCTION (164, logxor, "logxor", 2)
b10d9330
AW		 550{
551 ARGS2 (x, y);
552 if (SCM_I_INUMP (x) && SCM_I_INUMP (y))
553 RETURN (SCM_I_MAKINUM (SCM_I_INUM (x) ^ SCM_I_INUM (y)));
554 SYNC_REGISTER ();
555 RETURN (scm_logxor (x, y));
556}
557
1e4b834a 558\f
d5a4f51f
AW		 559/*
560 * Strings
561 */
562
5ddd9645 563VM_DEFINE_FUNCTION (165, string_length, "string-length", 1)
d5a4f51f
AW		 564{
565 ARGS1 (str);
566 if (SCM_LIKELY (scm_is_string (str)))
567 RETURN (SCM_I_MAKINUM (scm_i_string_length (str)));
568 else
569 {
570 SYNC_REGISTER ();
571 RETURN (scm_string_length (str));
572 }
573}
574
5ddd9645 575VM_DEFINE_FUNCTION (166, string_ref, "string-ref", 2)
d5a4f51f
AW		 576{
577 scm_t_signed_bits i = 0;
578 ARGS2 (str, idx);
579 if (SCM_LIKELY (scm_is_string (str)
580 && SCM_I_INUMP (idx)
581 && ((i = SCM_I_INUM (idx)) >= 0)
582 && i < scm_i_string_length (str)))
583 RETURN (SCM_MAKE_CHAR (scm_i_string_ref (str, i)));
584 else
585 {
586 SYNC_REGISTER ();
587 RETURN (scm_string_ref (str, idx));
588 }
589}
590
591/* No string-set! instruction, as there is no good fast path there. */
592
593\f
1e4b834a 594/*
827dc8dc 595 * Vectors and arrays
1e4b834a 596 */
aec4a84a 597
5ddd9645 598VM_DEFINE_FUNCTION (167, vector_length, "vector-length", 1)
d5a4f51f
AW		 599{
600 ARGS1 (vect);
601 if (SCM_LIKELY (SCM_I_IS_VECTOR (vect)))
602 RETURN (SCM_I_MAKINUM (SCM_I_VECTOR_LENGTH (vect)));
603 else
604 {
605 SYNC_REGISTER ();
606 RETURN (scm_vector_length (vect));
607 }
608}
609
5ddd9645 610VM_DEFINE_FUNCTION (168, vector_ref, "vector-ref", 2)
d6f1ce3d 611{
e25f3727 612 scm_t_signed_bits i = 0;
d6f1ce3d 613 ARGS2 (vect, idx);
7b702b53 614 if (SCM_LIKELY (SCM_I_IS_NONWEAK_VECTOR (vect)
d6f1ce3d
AW		 615 && SCM_I_INUMP (idx)
616 && ((i = SCM_I_INUM (idx)) >= 0)
617 && i < SCM_I_VECTOR_LENGTH (vect)))
618 RETURN (SCM_I_VECTOR_ELTS (vect)[i]);
619 else
9b29d607
AW		 620 {
621 SYNC_REGISTER ();
622 RETURN (scm_vector_ref (vect, idx));
623 }
d6f1ce3d
AW		 624}
625
5ddd9645 626VM_DEFINE_INSTRUCTION (169, vector_set, "vector-set", 0, 3, 0)
d6f1ce3d 627{
e25f3727 628 scm_t_signed_bits i = 0;
d6f1ce3d 629 SCM vect, idx, val;
eae2438d 630 POP3 (val, idx, vect);
7b702b53 631 if (SCM_LIKELY (SCM_I_IS_NONWEAK_VECTOR (vect)
d6f1ce3d
AW		 632 && SCM_I_INUMP (idx)
633 && ((i = SCM_I_INUM (idx)) >= 0)
634 && i < SCM_I_VECTOR_LENGTH (vect)))
635 SCM_I_VECTOR_WELTS (vect)[i] = val;
636 else
9b29d607
AW		 637 {
638 SYNC_REGISTER ();
639 scm_vector_set_x (vect, idx, val);
640 }
d6f1ce3d
AW		 641 NEXT;
642}
643
5ddd9645 644VM_DEFINE_INSTRUCTION (170, make_array, "make-array", 3, -1, 1)
827dc8dc
AW		 645{
646 scm_t_uint32 len;
647 SCM shape, ret;
648
649 len = FETCH ();
650 len = (len << 8) + FETCH ();
651 len = (len << 8) + FETCH ();
652 POP (shape);
653 SYNC_REGISTER ();
384dce46 654 PRE_CHECK_UNDERFLOW (len);
827dc8dc
AW		 655 ret = scm_from_contiguous_array (shape, sp - len + 1, len);
656 DROPN (len);
657 PUSH (ret);
658 NEXT;
659}
660
661\f
662/*
663 * Structs
664 */
41e49280 665#define VM_VALIDATE_STRUCT(obj, proc) \
776491ca 666 VM_ASSERT (SCM_STRUCTP (obj), vm_error_not_a_struct (proc, obj))
827dc8dc 667
5ddd9645 668VM_DEFINE_FUNCTION (171, struct_p, "struct?", 1)
827dc8dc
AW		 669{
670 ARGS1 (obj);
671 RETURN (scm_from_bool (SCM_STRUCTP (obj)));
672}
673
5ddd9645 674VM_DEFINE_FUNCTION (172, struct_vtable, "struct-vtable", 1)
827dc8dc
AW		 675{
676 ARGS1 (obj);
41e49280 677 VM_VALIDATE_STRUCT (obj, "struct_vtable");
827dc8dc
AW		 678 RETURN (SCM_STRUCT_VTABLE (obj));
679}
680
5ddd9645 681VM_DEFINE_INSTRUCTION (173, make_struct, "make-struct", 2, -1, 1)
827dc8dc
AW		 682{
683 unsigned h = FETCH ();
684 unsigned l = FETCH ();
9a974fd3
AW		 685 scm_t_bits n = ((h << 8U) + l);
686 SCM vtable = sp[-(n - 1)];
687 const SCM *inits = sp - n + 2;
688 SCM ret;
827dc8dc 689
9823fd39
LC		 690 SYNC_REGISTER ();
691
827dc8dc
AW		 692 if (SCM_LIKELY (SCM_STRUCTP (vtable)
693 && SCM_VTABLE_FLAG_IS_SET (vtable, SCM_VTABLE_FLAG_SIMPLE)
9a974fd3
AW		 694 && (SCM_STRUCT_DATA_REF (vtable, scm_vtable_index_size) + 1
695 == n)
696 && !SCM_VTABLE_INSTANCE_FINALIZER (vtable)))
827dc8dc 697 {
9a974fd3
AW		 698 /* Verily, we are making a simple struct with the right number of
699 initializers, and no finalizer. */
700 ret = scm_words ((scm_t_bits)SCM_STRUCT_DATA (vtable) | scm_tc3_struct,
701 n + 1);
702 SCM_SET_CELL_WORD_1 (ret, (scm_t_bits)SCM_CELL_OBJECT_LOC (ret, 2));
703 memcpy (SCM_STRUCT_DATA (ret), inits, (n - 1) * sizeof (SCM));
827dc8dc 704 }
9a974fd3
AW		 705 else
706 ret = scm_c_make_structv (vtable, 0, n - 1, (scm_t_bits *) inits);
707
c99865c1 708 DROPN (n);
9a974fd3 709 PUSH (ret);
827dc8dc 710
9a974fd3 711 NEXT;
827dc8dc
AW		 712}
713
5ddd9645 714VM_DEFINE_FUNCTION (174, struct_ref, "struct-ref", 2)
827dc8dc
AW		 715{
716 ARGS2 (obj, pos);
717
718 if (SCM_LIKELY (SCM_STRUCTP (obj)
719 && SCM_STRUCT_VTABLE_FLAG_IS_SET (obj,
720 SCM_VTABLE_FLAG_SIMPLE)
721 && SCM_I_INUMP (pos)))
722 {
723 SCM vtable;
724 scm_t_bits index, len;
725
e25f3727
AW		 726 /* True, an inum is a signed value, but cast to unsigned it will
727 certainly be more than the length, so we will fall through if
728 index is negative. */
827dc8dc
AW		 729 index = SCM_I_INUM (pos);
730 vtable = SCM_STRUCT_VTABLE (obj);
731 len = SCM_STRUCT_DATA_REF (vtable, scm_vtable_index_size);
732
733 if (SCM_LIKELY (index < len))
734 {
735 scm_t_bits *data = SCM_STRUCT_DATA (obj);
736 RETURN (SCM_PACK (data[index]));
737 }
738 }
739
9823fd39 740 SYNC_REGISTER ();
827dc8dc
AW		 741 RETURN (scm_struct_ref (obj, pos));
742}
743
5ddd9645 744VM_DEFINE_FUNCTION (175, struct_set, "struct-set", 3)
827dc8dc
AW		 745{
746 ARGS3 (obj, pos, val);
747
748 if (SCM_LIKELY (SCM_STRUCTP (obj)
749 && SCM_STRUCT_VTABLE_FLAG_IS_SET (obj,
750 SCM_VTABLE_FLAG_SIMPLE)
751 && SCM_STRUCT_VTABLE_FLAG_IS_SET (obj,
752 SCM_VTABLE_FLAG_SIMPLE_RW)
753 && SCM_I_INUMP (pos)))
754 {
755 SCM vtable;
756 scm_t_bits index, len;
757
e25f3727 758 /* See above regarding index being >= 0. */
827dc8dc
AW		 759 index = SCM_I_INUM (pos);
760 vtable = SCM_STRUCT_VTABLE (obj);
761 len = SCM_STRUCT_DATA_REF (vtable, scm_vtable_index_size);
762 if (SCM_LIKELY (index < len))
763 {
764 scm_t_bits *data = SCM_STRUCT_DATA (obj);
765 data[index] = SCM_UNPACK (val);
766 RETURN (val);
767 }
768 }
769
9823fd39 770 SYNC_REGISTER ();
827dc8dc
AW		 771 RETURN (scm_struct_set_x (obj, pos, val));
772}
773
774\f
775/*
776 * GOOPS support
777 */
5ddd9645 778VM_DEFINE_FUNCTION (176, class_of, "class-of", 1)
827dc8dc
AW		 779{
780 ARGS1 (obj);
1a461493
AW		 781 if (SCM_INSTANCEP (obj))
782 RETURN (SCM_CLASS_OF (obj));
783 SYNC_REGISTER ();
784 RETURN (scm_class_of (obj));
827dc8dc
AW		 785}
786
e25f3727 787/* FIXME: No checking whatsoever. */
5ddd9645 788VM_DEFINE_FUNCTION (177, slot_ref, "slot-ref", 2)
827dc8dc
AW		 789{
790 size_t slot;
791 ARGS2 (instance, idx);
792 slot = SCM_I_INUM (idx);
793 RETURN (SCM_PACK (SCM_STRUCT_DATA (instance) [slot]));
794}
795
e25f3727 796/* FIXME: No checking whatsoever. */
5ddd9645 797VM_DEFINE_INSTRUCTION (178, slot_set, "slot-set", 0, 3, 0)
827dc8dc
AW		 798{
799 SCM instance, idx, val;
800 size_t slot;
eae2438d 801 POP3 (val, idx, instance);
827dc8dc
AW		 802 slot = SCM_I_INUM (idx);
803 SCM_STRUCT_DATA (instance) [slot] = SCM_UNPACK (val);
804 NEXT;
805}
806
807\f
808/*
809 * Bytevectors
810 */
41e49280 811#define VM_VALIDATE_BYTEVECTOR(x, proc) \
53bdfcf0 812 VM_ASSERT (SCM_BYTEVECTOR_P (x), vm_error_not_a_bytevector (proc, x))
e6eb2467
AW		 813
814#define BV_REF_WITH_ENDIANNESS(stem, fn_stem) \
815{ \
816 SCM endianness; \
817 POP (endianness); \
818 if (scm_is_eq (endianness, scm_i_native_endianness)) \
819 goto VM_LABEL (bv_##stem##_native_ref); \
820 { \
821 ARGS2 (bv, idx); \
9823fd39 822 SYNC_REGISTER (); \
e6eb2467
AW		 823 RETURN (scm_bytevector_##fn_stem##_ref (bv, idx, endianness)); \
824 } \
825}
826
daccfef4
LC		 827/* Return true (non-zero) if PTR has suitable alignment for TYPE. */
828#define ALIGNED_P(ptr, type) \
1002c774 829 ((scm_t_uintptr) (ptr) % alignof_type (type) == 0)
daccfef4 830
5ddd9645 831VM_DEFINE_FUNCTION (179, bv_u16_ref, "bv-u16-ref", 3)
e6eb2467 832BV_REF_WITH_ENDIANNESS (u16, u16)
5ddd9645 833VM_DEFINE_FUNCTION (180, bv_s16_ref, "bv-s16-ref", 3)
e6eb2467 834BV_REF_WITH_ENDIANNESS (s16, s16)
5ddd9645 835VM_DEFINE_FUNCTION (181, bv_u32_ref, "bv-u32-ref", 3)
e6eb2467 836BV_REF_WITH_ENDIANNESS (u32, u32)
5ddd9645 837VM_DEFINE_FUNCTION (182, bv_s32_ref, "bv-s32-ref", 3)
e6eb2467 838BV_REF_WITH_ENDIANNESS (s32, s32)
5ddd9645 839VM_DEFINE_FUNCTION (183, bv_u64_ref, "bv-u64-ref", 3)
e6eb2467 840BV_REF_WITH_ENDIANNESS (u64, u64)
5ddd9645 841VM_DEFINE_FUNCTION (184, bv_s64_ref, "bv-s64-ref", 3)
e6eb2467 842BV_REF_WITH_ENDIANNESS (s64, s64)
5ddd9645 843VM_DEFINE_FUNCTION (185, bv_f32_ref, "bv-f32-ref", 3)
e6eb2467 844BV_REF_WITH_ENDIANNESS (f32, ieee_single)
5ddd9645 845VM_DEFINE_FUNCTION (186, bv_f64_ref, "bv-f64-ref", 3)
e6eb2467
AW		 846BV_REF_WITH_ENDIANNESS (f64, ieee_double)
847
848#undef BV_REF_WITH_ENDIANNESS
849
9823fd39
LC		 850#define BV_FIXABLE_INT_REF(stem, fn_stem, type, size) \
851{ \
e25f3727 852 scm_t_signed_bits i; \
daccfef4 853 const scm_t_ ## type *int_ptr; \
9823fd39 854 ARGS2 (bv, idx); \
daccfef4 855 \
41e49280 856 VM_VALIDATE_BYTEVECTOR (bv, "bv-" #stem "-ref"); \
daccfef4
LC		 857 i = SCM_I_INUM (idx); \
858 int_ptr = (scm_t_ ## type *) (SCM_BYTEVECTOR_CONTENTS (bv) + i); \
859 \
9823fd39 860 if (SCM_LIKELY (SCM_I_INUMP (idx) \
daccfef4 861 && (i >= 0) \
9823fd39 862 && (i + size <= SCM_BYTEVECTOR_LENGTH (bv)) \
daccfef4
LC		 863 && (ALIGNED_P (int_ptr, scm_t_ ## type)))) \
864 RETURN (SCM_I_MAKINUM (*int_ptr)); \
9823fd39
LC		 865 else \
866 { \
867 SYNC_REGISTER (); \
868 RETURN (scm_bytevector_ ## fn_stem ## _ref (bv, idx)); \
869 } \
870}
871
872#define BV_INT_REF(stem, type, size) \
873{ \
e25f3727 874 scm_t_signed_bits i; \
daccfef4 875 const scm_t_ ## type *int_ptr; \
9823fd39 876 ARGS2 (bv, idx); \
daccfef4 877 \
41e49280 878 VM_VALIDATE_BYTEVECTOR (bv, "bv-" #stem "-ref"); \
daccfef4
LC		 879 i = SCM_I_INUM (idx); \
880 int_ptr = (scm_t_ ## type *) (SCM_BYTEVECTOR_CONTENTS (bv) + i); \
881 \
9823fd39 882 if (SCM_LIKELY (SCM_I_INUMP (idx) \
daccfef4 883 && (i >= 0) \
9823fd39 884 && (i + size <= SCM_BYTEVECTOR_LENGTH (bv)) \
daccfef4
LC		 885 && (ALIGNED_P (int_ptr, scm_t_ ## type)))) \
886 { \
887 scm_t_ ## type x = *int_ptr; \
9823fd39
LC		 888 if (SCM_FIXABLE (x)) \
889 RETURN (SCM_I_MAKINUM (x)); \
890 else \
891 { \
892 SYNC_REGISTER (); \
893 RETURN (scm_from_ ## type (x)); \
894 } \
895 } \
896 else \
897 { \
898 SYNC_REGISTER (); \
899 RETURN (scm_bytevector_ ## stem ## _native_ref (bv, idx)); \
900 } \
901}
902
903#define BV_FLOAT_REF(stem, fn_stem, type, size) \
904{ \
e25f3727 905 scm_t_signed_bits i; \
daccfef4 906 const type *float_ptr; \
9823fd39 907 ARGS2 (bv, idx); \
daccfef4 908 \
41e49280 909 VM_VALIDATE_BYTEVECTOR (bv, "bv-" #stem "-ref"); \
daccfef4
LC		 910 i = SCM_I_INUM (idx); \
911 float_ptr = (type *) (SCM_BYTEVECTOR_CONTENTS (bv) + i); \
912 \
9823fd39
LC		 913 SYNC_REGISTER (); \
914 if (SCM_LIKELY (SCM_I_INUMP (idx) \
daccfef4 915 && (i >= 0) \
9823fd39 916 && (i + size <= SCM_BYTEVECTOR_LENGTH (bv)) \
daccfef4
LC		 917 && (ALIGNED_P (float_ptr, type)))) \
918 RETURN (scm_from_double (*float_ptr)); \
9823fd39
LC		 919 else \
920 RETURN (scm_bytevector_ ## fn_stem ## _native_ref (bv, idx)); \
e6eb2467
AW		 921}
922
5ddd9645 923VM_DEFINE_FUNCTION (187, bv_u8_ref, "bv-u8-ref", 2)
e6eb2467 924BV_FIXABLE_INT_REF (u8, u8, uint8, 1)
5ddd9645 925VM_DEFINE_FUNCTION (188, bv_s8_ref, "bv-s8-ref", 2)
e6eb2467 926BV_FIXABLE_INT_REF (s8, s8, int8, 1)
5ddd9645 927VM_DEFINE_FUNCTION (189, bv_u16_native_ref, "bv-u16-native-ref", 2)
e6eb2467 928BV_FIXABLE_INT_REF (u16, u16_native, uint16, 2)
5ddd9645 929VM_DEFINE_FUNCTION (190, bv_s16_native_ref, "bv-s16-native-ref", 2)
e6eb2467 930BV_FIXABLE_INT_REF (s16, s16_native, int16, 2)
5ddd9645 931VM_DEFINE_FUNCTION (191, bv_u32_native_ref, "bv-u32-native-ref", 2)
dddacb23
LC		 932#if SIZEOF_VOID_P > 4
933BV_FIXABLE_INT_REF (u32, u32_native, uint32, 4)
934#else
e6eb2467 935BV_INT_REF (u32, uint32, 4)
dddacb23 936#endif
5ddd9645 937VM_DEFINE_FUNCTION (192, bv_s32_native_ref, "bv-s32-native-ref", 2)
dddacb23
LC		 938#if SIZEOF_VOID_P > 4
939BV_FIXABLE_INT_REF (s32, s32_native, int32, 4)
940#else
e6eb2467 941BV_INT_REF (s32, int32, 4)
dddacb23 942#endif
5ddd9645 943VM_DEFINE_FUNCTION (193, bv_u64_native_ref, "bv-u64-native-ref", 2)
e6eb2467 944BV_INT_REF (u64, uint64, 8)
5ddd9645 945VM_DEFINE_FUNCTION (194, bv_s64_native_ref, "bv-s64-native-ref", 2)
e6eb2467 946BV_INT_REF (s64, int64, 8)
5ddd9645 947VM_DEFINE_FUNCTION (195, bv_f32_native_ref, "bv-f32-native-ref", 2)
e6eb2467 948BV_FLOAT_REF (f32, ieee_single, float, 4)
5ddd9645 949VM_DEFINE_FUNCTION (196, bv_f64_native_ref, "bv-f64-native-ref", 2)
e6eb2467
AW		 950BV_FLOAT_REF (f64, ieee_double, double, 8)
951
952#undef BV_FIXABLE_INT_REF
953#undef BV_INT_REF
954#undef BV_FLOAT_REF
955
956
957
958#define BV_SET_WITH_ENDIANNESS(stem, fn_stem) \
959{ \
960 SCM endianness; \
961 POP (endianness); \
962 if (scm_is_eq (endianness, scm_i_native_endianness)) \
963 goto VM_LABEL (bv_##stem##_native_set); \
964 { \
eae2438d 965 SCM bv, idx, val; POP3 (val, idx, bv); \
ad301b6d 966 SYNC_REGISTER (); \
d6f1ce3d
AW		 967 scm_bytevector_##fn_stem##_set_x (bv, idx, val, endianness); \
968 NEXT; \
e6eb2467
AW		 969 } \
970}
971
5ddd9645 972VM_DEFINE_INSTRUCTION (197, bv_u16_set, "bv-u16-set", 0, 4, 0)
e6eb2467 973BV_SET_WITH_ENDIANNESS (u16, u16)
5ddd9645 974VM_DEFINE_INSTRUCTION (198, bv_s16_set, "bv-s16-set", 0, 4, 0)
e6eb2467 975BV_SET_WITH_ENDIANNESS (s16, s16)
5ddd9645 976VM_DEFINE_INSTRUCTION (199, bv_u32_set, "bv-u32-set", 0, 4, 0)
e6eb2467 977BV_SET_WITH_ENDIANNESS (u32, u32)
5ddd9645 978VM_DEFINE_INSTRUCTION (200, bv_s32_set, "bv-s32-set", 0, 4, 0)
e6eb2467 979BV_SET_WITH_ENDIANNESS (s32, s32)
5ddd9645 980VM_DEFINE_INSTRUCTION (201, bv_u64_set, "bv-u64-set", 0, 4, 0)
e6eb2467 981BV_SET_WITH_ENDIANNESS (u64, u64)
5ddd9645 982VM_DEFINE_INSTRUCTION (202, bv_s64_set, "bv-s64-set", 0, 4, 0)
e6eb2467 983BV_SET_WITH_ENDIANNESS (s64, s64)
5ddd9645 984VM_DEFINE_INSTRUCTION (203, bv_f32_set, "bv-f32-set", 0, 4, 0)
e6eb2467 985BV_SET_WITH_ENDIANNESS (f32, ieee_single)
5ddd9645 986VM_DEFINE_INSTRUCTION (204, bv_f64_set, "bv-f64-set", 0, 4, 0)
e6eb2467
AW		 987BV_SET_WITH_ENDIANNESS (f64, ieee_double)
988
989#undef BV_SET_WITH_ENDIANNESS
990
daccfef4
LC		 991#define BV_FIXABLE_INT_SET(stem, fn_stem, type, min, max, size) \
992{ \
e25f3727 993 scm_t_signed_bits i, j = 0; \
daccfef4
LC		 994 SCM bv, idx, val; \
995 scm_t_ ## type *int_ptr; \
996 \
eae2438d 997 POP3 (val, idx, bv); \
41e49280 998 VM_VALIDATE_BYTEVECTOR (bv, "bv-" #stem "-set"); \
daccfef4
LC		 999 i = SCM_I_INUM (idx); \
1000 int_ptr = (scm_t_ ## type *) (SCM_BYTEVECTOR_CONTENTS (bv) + i); \
1001 \
1002 if (SCM_LIKELY (SCM_I_INUMP (idx) \
1003 && (i >= 0) \
1004 && (i + size <= SCM_BYTEVECTOR_LENGTH (bv)) \
1005 && (ALIGNED_P (int_ptr, scm_t_ ## type)) \
1006 && (SCM_I_INUMP (val)) \
1007 && ((j = SCM_I_INUM (val)) >= min) \
1008 && (j <= max))) \
1009 *int_ptr = (scm_t_ ## type) j; \
1010 else \
ad301b6d
AW		 1011 { \
1012 SYNC_REGISTER (); \
1013 scm_bytevector_ ## fn_stem ## _set_x (bv, idx, val); \
1014 } \
daccfef4
LC		 1015 NEXT; \
1016}
1017
1018#define BV_INT_SET(stem, type, size) \
1019{ \
e25f3727 1020 scm_t_signed_bits i = 0; \
daccfef4
LC		 1021 SCM bv, idx, val; \
1022 scm_t_ ## type *int_ptr; \
1023 \
eae2438d 1024 POP3 (val, idx, bv); \
41e49280 1025 VM_VALIDATE_BYTEVECTOR (bv, "bv-" #stem "-set"); \
daccfef4
LC		 1026 i = SCM_I_INUM (idx); \
1027 int_ptr = (scm_t_ ## type *) (SCM_BYTEVECTOR_CONTENTS (bv) + i); \
1028 \
1029 if (SCM_LIKELY (SCM_I_INUMP (idx) \
1030 && (i >= 0) \
1031 && (i + size <= SCM_BYTEVECTOR_LENGTH (bv)) \
1032 && (ALIGNED_P (int_ptr, scm_t_ ## type)))) \
1033 *int_ptr = scm_to_ ## type (val); \
1034 else \
ad301b6d
AW		 1035 { \
1036 SYNC_REGISTER (); \
1037 scm_bytevector_ ## stem ## _native_set_x (bv, idx, val); \
1038 } \
1039 NEXT; \
daccfef4
LC		 1040}
1041
ad301b6d
AW		 1042#define BV_FLOAT_SET(stem, fn_stem, type, size) \
1043{ \
1044 scm_t_signed_bits i = 0; \
1045 SCM bv, idx, val; \
1046 type *float_ptr; \
1047 \
eae2438d 1048 POP3 (val, idx, bv); \
ad301b6d
AW		 1049 VM_VALIDATE_BYTEVECTOR (bv, "bv-" #stem "-set"); \
1050 i = SCM_I_INUM (idx); \
1051 float_ptr = (type *) (SCM_BYTEVECTOR_CONTENTS (bv) + i); \
1052 \
1053 if (SCM_LIKELY (SCM_I_INUMP (idx) \
1054 && (i >= 0) \
1055 && (i + size <= SCM_BYTEVECTOR_LENGTH (bv)) \
1056 && (ALIGNED_P (float_ptr, type)))) \
1057 *float_ptr = scm_to_double (val); \
1058 else \
1059 { \
1060 SYNC_REGISTER (); \
1061 scm_bytevector_ ## fn_stem ## _native_set_x (bv, idx, val); \
1062 } \
1063 NEXT; \
e6eb2467
AW		 1064}
1065
5ddd9645 1066VM_DEFINE_INSTRUCTION (205, bv_u8_set, "bv-u8-set", 0, 3, 0)
e6eb2467 1067BV_FIXABLE_INT_SET (u8, u8, uint8, 0, SCM_T_UINT8_MAX, 1)
5ddd9645 1068VM_DEFINE_INSTRUCTION (206, bv_s8_set, "bv-s8-set", 0, 3, 0)
e6eb2467 1069BV_FIXABLE_INT_SET (s8, s8, int8, SCM_T_INT8_MIN, SCM_T_INT8_MAX, 1)
5ddd9645 1070VM_DEFINE_INSTRUCTION (207, bv_u16_native_set, "bv-u16-native-set", 0, 3, 0)
d6f1ce3d 1071BV_FIXABLE_INT_SET (u16, u16_native, uint16, 0, SCM_T_UINT16_MAX, 2)
5ddd9645 1072VM_DEFINE_INSTRUCTION (208, bv_s16_native_set, "bv-s16-native-set", 0, 3, 0)
d6f1ce3d 1073BV_FIXABLE_INT_SET (s16, s16_native, int16, SCM_T_INT16_MIN, SCM_T_INT16_MAX, 2)
5ddd9645 1074VM_DEFINE_INSTRUCTION (209, bv_u32_native_set, "bv-u32-native-set", 0, 3, 0)
dddacb23
LC		 1075#if SIZEOF_VOID_P > 4
1076BV_FIXABLE_INT_SET (u32, u32_native, uint32, 0, SCM_T_UINT32_MAX, 4)
1077#else
e6eb2467 1078BV_INT_SET (u32, uint32, 4)
dddacb23 1079#endif
5ddd9645 1080VM_DEFINE_INSTRUCTION (210, bv_s32_native_set, "bv-s32-native-set", 0, 3, 0)
dddacb23
LC		 1081#if SIZEOF_VOID_P > 4
1082BV_FIXABLE_INT_SET (s32, s32_native, int32, SCM_T_INT32_MIN, SCM_T_INT32_MAX, 4)
1083#else
e6eb2467 1084BV_INT_SET (s32, int32, 4)
dddacb23 1085#endif
5ddd9645 1086VM_DEFINE_INSTRUCTION (211, bv_u64_native_set, "bv-u64-native-set", 0, 3, 0)
e6eb2467 1087BV_INT_SET (u64, uint64, 8)
5ddd9645 1088VM_DEFINE_INSTRUCTION (212, bv_s64_native_set, "bv-s64-native-set", 0, 3, 0)
e6eb2467 1089BV_INT_SET (s64, int64, 8)
5ddd9645 1090VM_DEFINE_INSTRUCTION (213, bv_f32_native_set, "bv-f32-native-set", 0, 3, 0)
e6eb2467 1091BV_FLOAT_SET (f32, ieee_single, float, 4)
5ddd9645 1092VM_DEFINE_INSTRUCTION (214, bv_f64_native_set, "bv-f64-native-set", 0, 3, 0)
e6eb2467
AW		 1093BV_FLOAT_SET (f64, ieee_double, double, 8)
1094
1095#undef BV_FIXABLE_INT_SET
1096#undef BV_INT_SET
1097#undef BV_FLOAT_SET
1098
a0ec1ca1
AW		 1099#undef ALIGNED_P
1100#undef VM_VALIDATE_BYTEVECTOR
1101
1102#undef VM_VALIDATE_STRUCT
1103#undef VM_VALIDATE_CONS
1104
1105#undef ARGS1
1106#undef ARGS2
1107#undef ARGS3
1108#undef RETURN
1109
53e28ed9
AW		 1110/*
1111(defun renumber-ops ()
1112 "start from top of buffer and renumber 'VM_DEFINE_FOO (\n' sequences"
1113 (interactive "")
1114 (save-excursion
827dc8dc 1115 (let ((counter 127)) (goto-char (point-min))
53e28ed9
AW		 1116 (while (re-search-forward "^VM_DEFINE_[^ ]+ (\\([^,]+\\)," (point-max) t)
1117 (replace-match
1118 (number-to-string (setq counter (1+ counter)))
1119 t t nil 1)))))
1120*/
1e4b834a 1121
17e90c5e
KN		 1122/*
1123 Local Variables:
1124 c-file-style: "gnu"
1125 End:
1126*/
Unnamed repository; edit this file 'description' to name the repository.