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VM: Implement ASM_ADD, ASM_SUB, and ASM_MUL for ARM processors.
[bpt/guile.git] / libguile / vm-i-scheme.c
CommitLineData
776491ca 1/* Copyright (C) 2001, 2009, 2010, 2011, 2012, 2013 Free Software Foundation, Inc.
a98cef7e 2 *
560b9c25 3 * This library is free software; you can redistribute it and/or
53befeb7
NJ		 4 * modify it under the terms of the GNU Lesser General Public License
5 * as published by the Free Software Foundation; either version 3 of
6 * the License, or (at your option) any later version.
a98cef7e 7 *
53befeb7
NJ		 8 * This library is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
560b9c25
AW		 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * Lesser General Public License for more details.
a98cef7e 12 *
560b9c25
AW		 13 * You should have received a copy of the GNU Lesser General Public
14 * License along with this library; if not, write to the Free Software
53befeb7
NJ		 15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
16 * 02110-1301 USA
560b9c25 17 */
a98cef7e
KN		 18
19/* This file is included in vm_engine.c */
20
a80be762
KN		 21\f
22/*
23 * Predicates
24 */
25
93d197be 26#define ARGS1(a1) SCM a1 = sp[0];
11ea1aba
AW		 27#define ARGS2(a1,a2) SCM a1 = sp[-1], a2 = sp[0]; sp--; NULLSTACK (1);
28#define ARGS3(a1,a2,a3) SCM a1 = sp[-2], a2 = sp[-1], a3 = sp[0]; sp -= 2; NULLSTACK (2);
93d197be 29
a18e13a5 30#define RETURN(x) do { *sp = x; NEXT; } while (0)
93d197be 31
827dc8dc 32VM_DEFINE_FUNCTION (128, not, "not", 1)
a98cef7e 33{
a80be762 34 ARGS1 (x);
2533f10b 35 RETURN (scm_from_bool (scm_is_false (x)));
17e90c5e
KN		 36}
37
827dc8dc 38VM_DEFINE_FUNCTION (129, not_not, "not-not", 1)
17e90c5e 39{
a80be762 40 ARGS1 (x);
2533f10b 41 RETURN (scm_from_bool (!scm_is_false (x)));
17e90c5e
KN		 42}
43
827dc8dc 44VM_DEFINE_FUNCTION (130, eq, "eq?", 2)
17e90c5e 45{
a80be762 46 ARGS2 (x, y);
5c8cefe5 47 RETURN (scm_from_bool (scm_is_eq (x, y)));
17e90c5e
KN		 48}
49
827dc8dc 50VM_DEFINE_FUNCTION (131, not_eq, "not-eq?", 2)
17e90c5e 51{
a80be762 52 ARGS2 (x, y);
5c8cefe5 53 RETURN (scm_from_bool (!scm_is_eq (x, y)));
17e90c5e
KN		 54}
55
827dc8dc 56VM_DEFINE_FUNCTION (132, nullp, "null?", 1)
17e90c5e 57{
a80be762 58 ARGS1 (x);
2533f10b 59 RETURN (scm_from_bool (scm_is_null (x)));
a98cef7e
KN		 60}
61
827dc8dc 62VM_DEFINE_FUNCTION (133, not_nullp, "not-null?", 1)
a98cef7e 63{
a80be762 64 ARGS1 (x);
2533f10b 65 RETURN (scm_from_bool (!scm_is_null (x)));
a80be762
KN		 66}
67
827dc8dc 68VM_DEFINE_FUNCTION (134, eqv, "eqv?", 2)
a80be762
KN		 69{
70 ARGS2 (x, y);
5c8cefe5 71 if (scm_is_eq (x, y))
a80be762 72 RETURN (SCM_BOOL_T);
a18e13a5 73 if (SCM_IMP (x) || SCM_IMP (y))
a80be762 74 RETURN (SCM_BOOL_F);
a18e13a5
AW		 75 SYNC_REGISTER ();
76 RETURN (scm_eqv_p (x, y));
a80be762
KN		 77}
78
827dc8dc 79VM_DEFINE_FUNCTION (135, equal, "equal?", 2)
a80be762
KN		 80{
81 ARGS2 (x, y);
5c8cefe5 82 if (scm_is_eq (x, y))
a80be762 83 RETURN (SCM_BOOL_T);
a18e13a5 84 if (SCM_IMP (x) || SCM_IMP (y))
a80be762 85 RETURN (SCM_BOOL_F);
a18e13a5
AW		 86 SYNC_REGISTER ();
87 RETURN (scm_equal_p (x, y));
a98cef7e
KN		 88}
89
827dc8dc 90VM_DEFINE_FUNCTION (136, pairp, "pair?", 1)
a98cef7e 91{
a80be762 92 ARGS1 (x);
5c8cefe5 93 RETURN (scm_from_bool (scm_is_pair (x)));
a98cef7e
KN		 94}
95
827dc8dc 96VM_DEFINE_FUNCTION (137, listp, "list?", 1)
a98cef7e 97{
a80be762 98 ARGS1 (x);
9bd48cb1 99 RETURN (scm_from_bool (scm_ilength (x) >= 0));
a98cef7e
KN		 100}
101
cf45ff03
AW		 102VM_DEFINE_FUNCTION (138, symbolp, "symbol?", 1)
103{
104 ARGS1 (x);
105 RETURN (scm_from_bool (scm_is_symbol (x)));
106}
107
108VM_DEFINE_FUNCTION (139, vectorp, "vector?", 1)
109{
110 ARGS1 (x);
111 RETURN (scm_from_bool (SCM_I_IS_VECTOR (x)));
112}
113
a80be762
KN		 114\f
115/*
116 * Basic data
117 */
118
cf45ff03 119VM_DEFINE_FUNCTION (140, cons, "cons", 2)
a98cef7e 120{
a80be762
KN		 121 ARGS2 (x, y);
122 CONS (x, x, y);
123 RETURN (x);
a98cef7e
KN		 124}
125
41e49280 126#define VM_VALIDATE_CONS(x, proc) \
53bdfcf0 127 VM_ASSERT (scm_is_pair (x), vm_error_not_a_pair (proc, x))
5e390de6 128
cf45ff03 129VM_DEFINE_FUNCTION (141, car, "car", 1)
a98cef7e 130{
a80be762 131 ARGS1 (x);
41e49280 132 VM_VALIDATE_CONS (x, "car");
a80be762 133 RETURN (SCM_CAR (x));
a98cef7e
KN		 134}
135
cf45ff03 136VM_DEFINE_FUNCTION (142, cdr, "cdr", 1)
a98cef7e 137{
a80be762 138 ARGS1 (x);
41e49280 139 VM_VALIDATE_CONS (x, "cdr");
a80be762 140 RETURN (SCM_CDR (x));
a98cef7e
KN		 141}
142
cf45ff03 143VM_DEFINE_INSTRUCTION (143, set_car, "set-car!", 0, 2, 0)
a98cef7e 144{
60ed31d2 145 SCM x, y;
eae2438d 146 POP2 (y, x);
41e49280 147 VM_VALIDATE_CONS (x, "set-car!");
a80be762 148 SCM_SETCAR (x, y);
60ed31d2 149 NEXT;
a98cef7e
KN		 150}
151
cf45ff03 152VM_DEFINE_INSTRUCTION (144, set_cdr, "set-cdr!", 0, 2, 0)
a98cef7e 153{
60ed31d2 154 SCM x, y;
eae2438d 155 POP2 (y, x);
41e49280 156 VM_VALIDATE_CONS (x, "set-cdr!");
a80be762 157 SCM_SETCDR (x, y);
60ed31d2 158 NEXT;
a98cef7e
KN		 159}
160
a80be762
KN		 161\f
162/*
163 * Numeric relational tests
164 */
165
166#undef REL
b2b33168
AW		 167#define REL(crel,srel) \
168 { \
169 ARGS2 (x, y); \
170 if (SCM_I_INUMP (x) && SCM_I_INUMP (y)) \
171 RETURN (scm_from_bool (((scm_t_signed_bits) SCM_UNPACK (x)) \
172 crel ((scm_t_signed_bits) SCM_UNPACK (y)))); \
a18e13a5
AW		 173 SYNC_REGISTER (); \
174 RETURN (srel (x, y)); \
b2b33168 175 }
a80be762 176
cf45ff03 177VM_DEFINE_FUNCTION (145, ee, "ee?", 2)
a80be762
KN		 178{
179 REL (==, scm_num_eq_p);
180}
181
cf45ff03 182VM_DEFINE_FUNCTION (146, lt, "lt?", 2)
a80be762
KN		 183{
184 REL (<, scm_less_p);
185}
186
cf45ff03 187VM_DEFINE_FUNCTION (147, le, "le?", 2)
a80be762
KN		 188{
189 REL (<=, scm_leq_p);
190}
191
cf45ff03 192VM_DEFINE_FUNCTION (148, gt, "gt?", 2)
a80be762
KN		 193{
194 REL (>, scm_gr_p);
195}
196
cf45ff03 197VM_DEFINE_FUNCTION (149, ge, "ge?", 2)
a80be762
KN		 198{
199 REL (>=, scm_geq_p);
200}
201
202\f
203/*
204 * Numeric functions
205 */
206
e78d4bf9 207/* The maximum/minimum tagged integers. */
0c57673a
LC		 208#undef INUM_MAX
209#undef INUM_MIN
cb1482e7 210#undef INUM_STEP
478fa0d5
MW		 211#define INUM_MAX \
212 ((scm_t_signed_bits) SCM_UNPACK (SCM_I_MAKINUM (SCM_MOST_POSITIVE_FIXNUM)))
213#define INUM_MIN \
214 ((scm_t_signed_bits) SCM_UNPACK (SCM_I_MAKINUM (SCM_MOST_NEGATIVE_FIXNUM)))
cb1482e7
MW		 215#define INUM_STEP \
216 ((scm_t_signed_bits) SCM_UNPACK (SCM_INUM1) \
217 - (scm_t_signed_bits) SCM_UNPACK (SCM_INUM0))
e78d4bf9 218
a80be762 219#undef FUNC2
a18e13a5
AW		 220#define FUNC2(CFUNC,SFUNC) \
221{ \
222 ARGS2 (x, y); \
223 if (SCM_I_INUMP (x) && SCM_I_INUMP (y)) \
224 { \
225 scm_t_int64 n = SCM_I_INUM (x) CFUNC SCM_I_INUM (y);\
226 if (SCM_FIXABLE (n)) \
227 RETURN (SCM_I_MAKINUM (n)); \
228 } \
229 SYNC_REGISTER (); \
230 RETURN (SFUNC (x, y)); \
231}
a80be762 232
0c57673a
LC		 233/* Assembly tagged integer arithmetic routines. This code uses the
234 `asm goto' feature introduced in GCC 4.5. */
235
9f621170
MW		 236#if SCM_GNUC_PREREQ (4, 5) && (defined __x86_64__ || defined __i386__)
237
238# undef _CX
239# ifdef __x86_64__
240# define _CX "rcx"
241# else
242# define _CX "ecx"
243# endif
0c57673a
LC		 244
245/* The macros below check the CPU's overflow flag to improve fixnum
9f621170
MW		 246 arithmetic. The _CX register (%rcx or %ecx) is explicitly
247 clobbered because `asm goto' can't have outputs, in which case the
248 `r' constraint could be used to let the register allocator choose a
249 register.
0c57673a
LC		 250
251 TODO: Use `cold' label attribute in GCC 4.6.
252 http://gcc.gnu.org/ml/gcc-patches/2010-10/msg01777.html */
253
254# define ASM_ADD(x, y) \
255 { \
9f621170
MW		 256 asm volatile goto ("mov %1, %%"_CX"; " \
257 "test %[tag], %%cl; je %l[slow_add]; " \
258 "test %[tag], %0; je %l[slow_add]; " \
259 "sub %[tag], %%"_CX"; " \
260 "add %0, %%"_CX"; jo %l[slow_add]; " \
261 "mov %%"_CX", (%[vsp])\n" \
0c57673a
LC		 262 : /* no outputs */ \
263 : "r" (x), "r" (y), \
264 [vsp] "r" (sp), [tag] "i" (scm_tc2_int) \
ddf4ff24 265 : "rcx", "memory", "cc" \
0c57673a
LC		 266 : slow_add); \
267 NEXT; \
268 } \
269 slow_add: \
270 do { } while (0)
271
272# define ASM_SUB(x, y) \
273 { \
9f621170
MW		 274 asm volatile goto ("mov %0, %%"_CX"; " \
275 "test %[tag], %%cl; je %l[slow_sub]; " \
276 "test %[tag], %1; je %l[slow_sub]; " \
277 "sub %1, %%"_CX"; jo %l[slow_sub]; " \
278 "add %[tag], %%"_CX"; " \
279 "mov %%"_CX", (%[vsp])\n" \
0c57673a
LC		 280 : /* no outputs */ \
281 : "r" (x), "r" (y), \
282 [vsp] "r" (sp), [tag] "i" (scm_tc2_int) \
ddf4ff24 283 : "rcx", "memory", "cc" \
0c57673a
LC		 284 : slow_sub); \
285 NEXT; \
286 } \
287 slow_sub: \
288 do { } while (0)
289
4fa65b90
MW		 290# define ASM_MUL(x, y) \
291 { \
292 scm_t_signed_bits xx = SCM_I_INUM (x); \
293 asm volatile goto ("mov %1, %%"_CX"; " \
294 "test %[tag], %%cl; je %l[slow_mul]; " \
295 "sub %[tag], %%"_CX"; " \
296 "test %[tag], %0; je %l[slow_mul]; " \
297 "imul %2, %%"_CX"; jo %l[slow_mul]; " \
298 "add %[tag], %%"_CX"; " \
299 "mov %%"_CX", (%[vsp])\n" \
300 : /* no outputs */ \
301 : "r" (x), "r" (y), "r" (xx), \
302 [vsp] "r" (sp), [tag] "i" (scm_tc2_int) \
303 : _CX, "memory", "cc" \
304 : slow_mul); \
305 NEXT; \
306 } \
307 slow_mul: \
308 do { } while (0)
309
0c57673a
LC		 310#endif
311
f91a1864
MW		 312#if SCM_GNUC_PREREQ (4, 5) && defined __arm__
313
314# define ASM_ADD(x, y) \
315 if (SCM_LIKELY (SCM_I_INUMP (x) && SCM_I_INUMP (y))) \
316 { \
317 asm volatile goto ("adds r0, %0, %1; bvs %l[slow_add]; " \
318 "str r0, [%[vsp]]\n" \
319 : /* no outputs */ \
320 : "r" (x), "r" (y - scm_tc2_int), \
321 [vsp] "r" (sp) \
322 : "r0", "memory", "cc" \
323 : slow_add); \
324 NEXT; \
325 } \
326 slow_add: \
327 do { } while (0)
328
329# define ASM_SUB(x, y) \
330 if (SCM_LIKELY (SCM_I_INUMP (x) && SCM_I_INUMP (y))) \
331 { \
332 asm volatile goto ("subs r0, %0, %1; bvs %l[slow_sub]; " \
333 "str r0, [%[vsp]]\n" \
334 : /* no outputs */ \
335 : "r" (x), "r" (y - scm_tc2_int), \
336 [vsp] "r" (sp) \
337 : "r0", "memory", "cc" \
338 : slow_sub); \
339 NEXT; \
340 } \
341 slow_sub: \
342 do { } while (0)
343
344# define ASM_MUL(x, y) \
345 if (SCM_LIKELY (SCM_I_INUMP (x) && SCM_I_INUMP (y))) \
346 { \
347 scm_t_signed_bits rlo, rhi; \
348 asm ("smull %0, %1, %2, %3\n" \
349 : "=r" (rlo), "=r" (rhi) \
350 : "r" (SCM_UNPACK (x) - scm_tc2_int), \
351 "r" (SCM_I_INUM (y))); \
352 if (SCM_LIKELY (SCM_SRS (rlo, 31) == rhi)) \
353 RETURN (SCM_PACK (rlo + scm_tc2_int)); \
354 } \
355 do { } while (0)
356
357#endif
0c57673a 358
cf45ff03 359VM_DEFINE_FUNCTION (150, add, "add", 2)
a80be762 360{
0c57673a 361#ifndef ASM_ADD
a80be762 362 FUNC2 (+, scm_sum);
0c57673a
LC		 363#else
364 ARGS2 (x, y);
365 ASM_ADD (x, y);
366 SYNC_REGISTER ();
367 RETURN (scm_sum (x, y));
368#endif
a80be762
KN		 369}
370
cf45ff03 371VM_DEFINE_FUNCTION (151, add1, "add1", 1)
7382f23e
AW		 372{
373 ARGS1 (x);
e78d4bf9 374
cb1482e7
MW		 375 /* Check for overflow. We must avoid overflow in the signed
376 addition below, even if X is not an inum. */
377 if (SCM_LIKELY ((scm_t_signed_bits) SCM_UNPACK (x) <= INUM_MAX - INUM_STEP))
7382f23e 378 {
e78d4bf9
LC		 379 SCM result;
380
cb1482e7
MW		 381 /* Add 1 to the integer without untagging. */
382 result = SCM_PACK ((scm_t_signed_bits) SCM_UNPACK (x) + INUM_STEP);
e78d4bf9
LC		 383
384 if (SCM_LIKELY (SCM_I_INUMP (result)))
a18e13a5 385 RETURN (result);
7382f23e 386 }
e78d4bf9 387
7382f23e
AW		 388 SYNC_REGISTER ();
389 RETURN (scm_sum (x, SCM_I_MAKINUM (1)));
390}
391
cf45ff03 392VM_DEFINE_FUNCTION (152, sub, "sub", 2)
a80be762 393{
0c57673a 394#ifndef ASM_SUB
a80be762 395 FUNC2 (-, scm_difference);
0c57673a
LC		 396#else
397 ARGS2 (x, y);
398 ASM_SUB (x, y);
399 SYNC_REGISTER ();
400 RETURN (scm_difference (x, y));
401#endif
a80be762
KN		 402}
403
cf45ff03 404VM_DEFINE_FUNCTION (153, sub1, "sub1", 1)
7382f23e
AW		 405{
406 ARGS1 (x);
e78d4bf9 407
cb1482e7
MW		 408 /* Check for overflow. We must avoid overflow in the signed
409 subtraction below, even if X is not an inum. */
410 if (SCM_LIKELY ((scm_t_signed_bits) SCM_UNPACK (x) >= INUM_MIN + INUM_STEP))
7382f23e 411 {
e78d4bf9
LC		 412 SCM result;
413
cb1482e7
MW		 414 /* Substract 1 from the integer without untagging. */
415 result = SCM_PACK ((scm_t_signed_bits) SCM_UNPACK (x) - INUM_STEP);
e78d4bf9
LC		 416
417 if (SCM_LIKELY (SCM_I_INUMP (result)))
a18e13a5 418 RETURN (result);
7382f23e 419 }
e78d4bf9 420
7382f23e
AW		 421 SYNC_REGISTER ();
422 RETURN (scm_difference (x, SCM_I_MAKINUM (1)));
423}
424
cf45ff03 425VM_DEFINE_FUNCTION (154, mul, "mul", 2)
a80be762
KN		 426{
427 ARGS2 (x, y);
4fa65b90
MW		 428#ifdef ASM_MUL
429 ASM_MUL (x, y);
430#endif
1865ad56 431 SYNC_REGISTER ();
a80be762
KN		 432 RETURN (scm_product (x, y));
433}
434
4fa65b90
MW		 435# undef ASM_ADD
436# undef ASM_SUB
437# undef ASM_MUL
438
cf45ff03 439VM_DEFINE_FUNCTION (155, div, "div", 2)
a80be762
KN		 440{
441 ARGS2 (x, y);
1865ad56 442 SYNC_REGISTER ();
a80be762
KN		 443 RETURN (scm_divide (x, y));
444}
445
cf45ff03 446VM_DEFINE_FUNCTION (156, quo, "quo", 2)
a80be762
KN		 447{
448 ARGS2 (x, y);
1865ad56 449 SYNC_REGISTER ();
a80be762
KN		 450 RETURN (scm_quotient (x, y));
451}
452
cf45ff03 453VM_DEFINE_FUNCTION (157, rem, "rem", 2)
a80be762
KN		 454{
455 ARGS2 (x, y);
1865ad56 456 SYNC_REGISTER ();
a80be762
KN		 457 RETURN (scm_remainder (x, y));
458}
459
cf45ff03 460VM_DEFINE_FUNCTION (158, mod, "mod", 2)
a80be762
KN		 461{
462 ARGS2 (x, y);
1865ad56 463 SYNC_REGISTER ();
a80be762
KN		 464 RETURN (scm_modulo (x, y));
465}
466
cf45ff03 467VM_DEFINE_FUNCTION (159, ash, "ash", 2)
b10d9330
AW		 468{
469 ARGS2 (x, y);
470 if (SCM_I_INUMP (x) && SCM_I_INUMP (y))
471 {
472 if (SCM_I_INUM (y) < 0)
7e8166f5
MW		 473 {
474 /* Right shift, will be a fixnum. */
475 if (SCM_I_INUM (y) > -SCM_I_FIXNUM_BIT)
476 RETURN (SCM_I_MAKINUM (SCM_I_INUM (x) >> -SCM_I_INUM (y)));
477 /* fall through */
478 }
8ecd1943
AW		 479 else
480 /* Left shift. See comments in scm_ash. */
481 {
e25f3727 482 scm_t_signed_bits nn, bits_to_shift;
8ecd1943
AW		 483
484 nn = SCM_I_INUM (x);
485 bits_to_shift = SCM_I_INUM (y);
486
487 if (bits_to_shift < SCM_I_FIXNUM_BIT-1
e25f3727 488 && ((scm_t_bits)
8ecd1943
AW		 489 (SCM_SRS (nn, (SCM_I_FIXNUM_BIT-1 - bits_to_shift)) + 1)
490 <= 1))
a18e13a5 491 RETURN (SCM_I_MAKINUM (nn << bits_to_shift));
8ecd1943
AW		 492 /* fall through */
493 }
b10d9330
AW		 494 /* fall through */
495 }
496 SYNC_REGISTER ();
497 RETURN (scm_ash (x, y));
498}
499
cf45ff03 500VM_DEFINE_FUNCTION (160, logand, "logand", 2)
b10d9330
AW		 501{
502 ARGS2 (x, y);
a18e13a5 503 if (SCM_I_INUMP (x) && SCM_I_INUMP (y))
b2df1682
MW		 504 /* Compute bitwise AND without untagging */
505 RETURN (SCM_PACK (SCM_UNPACK (x) & SCM_UNPACK (y)));
a18e13a5
AW		 506 SYNC_REGISTER ();
507 RETURN (scm_logand (x, y));
b10d9330
AW		 508}
509
cf45ff03 510VM_DEFINE_FUNCTION (161, logior, "logior", 2)
b10d9330
AW		 511{
512 ARGS2 (x, y);
a18e13a5 513 if (SCM_I_INUMP (x) && SCM_I_INUMP (y))
b2df1682
MW		 514 /* Compute bitwise OR without untagging */
515 RETURN (SCM_PACK (SCM_UNPACK (x) | SCM_UNPACK (y)));
a18e13a5
AW		 516 SYNC_REGISTER ();
517 RETURN (scm_logior (x, y));
b10d9330
AW		 518}
519
cf45ff03 520VM_DEFINE_FUNCTION (162, logxor, "logxor", 2)
b10d9330
AW		 521{
522 ARGS2 (x, y);
a18e13a5 523 if (SCM_I_INUMP (x) && SCM_I_INUMP (y))
b10d9330 524 RETURN (SCM_I_MAKINUM (SCM_I_INUM (x) ^ SCM_I_INUM (y)));
a18e13a5
AW		 525 SYNC_REGISTER ();
526 RETURN (scm_logxor (x, y));
b10d9330
AW		 527}
528
1e4b834a
AW		 529\f
530/*
827dc8dc 531 * Vectors and arrays
1e4b834a 532 */
aec4a84a 533
cf45ff03 534VM_DEFINE_FUNCTION (163, vector_ref, "vector-ref", 2)
d6f1ce3d 535{
e25f3727 536 scm_t_signed_bits i = 0;
d6f1ce3d 537 ARGS2 (vect, idx);
7b702b53 538 if (SCM_LIKELY (SCM_I_IS_NONWEAK_VECTOR (vect)
d6f1ce3d
AW		 539 && SCM_I_INUMP (idx)
540 && ((i = SCM_I_INUM (idx)) >= 0)
541 && i < SCM_I_VECTOR_LENGTH (vect)))
542 RETURN (SCM_I_VECTOR_ELTS (vect)[i]);
543 else
9b29d607
AW		 544 {
545 SYNC_REGISTER ();
546 RETURN (scm_vector_ref (vect, idx));
547 }
d6f1ce3d
AW		 548}
549
cf45ff03 550VM_DEFINE_INSTRUCTION (164, vector_set, "vector-set", 0, 3, 0)
d6f1ce3d 551{
e25f3727 552 scm_t_signed_bits i = 0;
d6f1ce3d 553 SCM vect, idx, val;
eae2438d 554 POP3 (val, idx, vect);
7b702b53 555 if (SCM_LIKELY (SCM_I_IS_NONWEAK_VECTOR (vect)
d6f1ce3d
AW		 556 && SCM_I_INUMP (idx)
557 && ((i = SCM_I_INUM (idx)) >= 0)
558 && i < SCM_I_VECTOR_LENGTH (vect)))
559 SCM_I_VECTOR_WELTS (vect)[i] = val;
560 else
9b29d607
AW		 561 {
562 SYNC_REGISTER ();
563 scm_vector_set_x (vect, idx, val);
564 }
d6f1ce3d
AW		 565 NEXT;
566}
567
cf45ff03 568VM_DEFINE_INSTRUCTION (165, make_array, "make-array", 3, -1, 1)
827dc8dc
AW		 569{
570 scm_t_uint32 len;
571 SCM shape, ret;
572
573 len = FETCH ();
574 len = (len << 8) + FETCH ();
575 len = (len << 8) + FETCH ();
576 POP (shape);
577 SYNC_REGISTER ();
384dce46 578 PRE_CHECK_UNDERFLOW (len);
827dc8dc
AW		 579 ret = scm_from_contiguous_array (shape, sp - len + 1, len);
580 DROPN (len);
581 PUSH (ret);
582 NEXT;
583}
584
585\f
586/*
587 * Structs
588 */
41e49280 589#define VM_VALIDATE_STRUCT(obj, proc) \
776491ca 590 VM_ASSERT (SCM_STRUCTP (obj), vm_error_not_a_struct (proc, obj))
827dc8dc 591
cf45ff03 592VM_DEFINE_FUNCTION (166, struct_p, "struct?", 1)
827dc8dc
AW		 593{
594 ARGS1 (obj);
595 RETURN (scm_from_bool (SCM_STRUCTP (obj)));
596}
597
cf45ff03 598VM_DEFINE_FUNCTION (167, struct_vtable, "struct-vtable", 1)
827dc8dc
AW		 599{
600 ARGS1 (obj);
41e49280 601 VM_VALIDATE_STRUCT (obj, "struct_vtable");
827dc8dc
AW		 602 RETURN (SCM_STRUCT_VTABLE (obj));
603}
604
cf45ff03 605VM_DEFINE_INSTRUCTION (168, make_struct, "make-struct", 2, -1, 1)
827dc8dc
AW		 606{
607 unsigned h = FETCH ();
608 unsigned l = FETCH ();
9a974fd3
AW		 609 scm_t_bits n = ((h << 8U) + l);
610 SCM vtable = sp[-(n - 1)];
611 const SCM *inits = sp - n + 2;
612 SCM ret;
827dc8dc 613
9823fd39
LC		 614 SYNC_REGISTER ();
615
827dc8dc
AW		 616 if (SCM_LIKELY (SCM_STRUCTP (vtable)
617 && SCM_VTABLE_FLAG_IS_SET (vtable, SCM_VTABLE_FLAG_SIMPLE)
9a974fd3
AW		 618 && (SCM_STRUCT_DATA_REF (vtable, scm_vtable_index_size) + 1
619 == n)
620 && !SCM_VTABLE_INSTANCE_FINALIZER (vtable)))
827dc8dc 621 {
9a974fd3
AW		 622 /* Verily, we are making a simple struct with the right number of
623 initializers, and no finalizer. */
624 ret = scm_words ((scm_t_bits)SCM_STRUCT_DATA (vtable) | scm_tc3_struct,
625 n + 1);
626 SCM_SET_CELL_WORD_1 (ret, (scm_t_bits)SCM_CELL_OBJECT_LOC (ret, 2));
627 memcpy (SCM_STRUCT_DATA (ret), inits, (n - 1) * sizeof (SCM));
827dc8dc 628 }
9a974fd3
AW		 629 else
630 ret = scm_c_make_structv (vtable, 0, n - 1, (scm_t_bits *) inits);
631
c99865c1 632 DROPN (n);
9a974fd3 633 PUSH (ret);
827dc8dc 634
9a974fd3 635 NEXT;
827dc8dc
AW		 636}
637
cf45ff03 638VM_DEFINE_FUNCTION (169, struct_ref, "struct-ref", 2)
827dc8dc
AW		 639{
640 ARGS2 (obj, pos);
641
642 if (SCM_LIKELY (SCM_STRUCTP (obj)
643 && SCM_STRUCT_VTABLE_FLAG_IS_SET (obj,
644 SCM_VTABLE_FLAG_SIMPLE)
645 && SCM_I_INUMP (pos)))
646 {
647 SCM vtable;
648 scm_t_bits index, len;
649
e25f3727
AW		 650 /* True, an inum is a signed value, but cast to unsigned it will
651 certainly be more than the length, so we will fall through if
652 index is negative. */
827dc8dc
AW		 653 index = SCM_I_INUM (pos);
654 vtable = SCM_STRUCT_VTABLE (obj);
655 len = SCM_STRUCT_DATA_REF (vtable, scm_vtable_index_size);
656
657 if (SCM_LIKELY (index < len))
658 {
a18e13a5
AW		 659 scm_t_bits *data = SCM_STRUCT_DATA (obj);
660 RETURN (SCM_PACK (data[index]));
827dc8dc
AW		 661 }
662 }
663
9823fd39 664 SYNC_REGISTER ();
827dc8dc
AW		 665 RETURN (scm_struct_ref (obj, pos));
666}
667
cf45ff03 668VM_DEFINE_FUNCTION (170, struct_set, "struct-set", 3)
827dc8dc
AW		 669{
670 ARGS3 (obj, pos, val);
671
672 if (SCM_LIKELY (SCM_STRUCTP (obj)
673 && SCM_STRUCT_VTABLE_FLAG_IS_SET (obj,
674 SCM_VTABLE_FLAG_SIMPLE)
675 && SCM_STRUCT_VTABLE_FLAG_IS_SET (obj,
676 SCM_VTABLE_FLAG_SIMPLE_RW)
677 && SCM_I_INUMP (pos)))
678 {
679 SCM vtable;
680 scm_t_bits index, len;
681
e25f3727 682 /* See above regarding index being >= 0. */
827dc8dc
AW		 683 index = SCM_I_INUM (pos);
684 vtable = SCM_STRUCT_VTABLE (obj);
685 len = SCM_STRUCT_DATA_REF (vtable, scm_vtable_index_size);
686 if (SCM_LIKELY (index < len))
687 {
a18e13a5
AW		 688 scm_t_bits *data = SCM_STRUCT_DATA (obj);
689 data[index] = SCM_UNPACK (val);
690 RETURN (val);
827dc8dc
AW		 691 }
692 }
693
9823fd39 694 SYNC_REGISTER ();
827dc8dc
AW		 695 RETURN (scm_struct_set_x (obj, pos, val));
696}
697
698\f
699/*
700 * GOOPS support
701 */
cf45ff03 702VM_DEFINE_FUNCTION (171, class_of, "class-of", 1)
827dc8dc
AW		 703{
704 ARGS1 (obj);
1a461493
AW		 705 if (SCM_INSTANCEP (obj))
706 RETURN (SCM_CLASS_OF (obj));
a18e13a5
AW		 707 SYNC_REGISTER ();
708 RETURN (scm_class_of (obj));
827dc8dc
AW		 709}
710
e25f3727 711/* FIXME: No checking whatsoever. */
cf45ff03 712VM_DEFINE_FUNCTION (172, slot_ref, "slot-ref", 2)
827dc8dc
AW		 713{
714 size_t slot;
715 ARGS2 (instance, idx);
716 slot = SCM_I_INUM (idx);
717 RETURN (SCM_PACK (SCM_STRUCT_DATA (instance) [slot]));
718}
719
e25f3727 720/* FIXME: No checking whatsoever. */
cf45ff03 721VM_DEFINE_INSTRUCTION (173, slot_set, "slot-set", 0, 3, 0)
827dc8dc
AW		 722{
723 SCM instance, idx, val;
724 size_t slot;
eae2438d 725 POP3 (val, idx, instance);
827dc8dc
AW		 726 slot = SCM_I_INUM (idx);
727 SCM_STRUCT_DATA (instance) [slot] = SCM_UNPACK (val);
728 NEXT;
729}
730
731\f
732/*
733 * Bytevectors
734 */
41e49280 735#define VM_VALIDATE_BYTEVECTOR(x, proc) \
53bdfcf0 736 VM_ASSERT (SCM_BYTEVECTOR_P (x), vm_error_not_a_bytevector (proc, x))
e6eb2467
AW		 737
738#define BV_REF_WITH_ENDIANNESS(stem, fn_stem) \
739{ \
740 SCM endianness; \
741 POP (endianness); \
742 if (scm_is_eq (endianness, scm_i_native_endianness)) \
a39b116f 743 goto VM_LABEL (bv_##stem##_native_ref); \
e6eb2467
AW		 744 { \
745 ARGS2 (bv, idx); \
9823fd39 746 SYNC_REGISTER (); \
e6eb2467
AW		 747 RETURN (scm_bytevector_##fn_stem##_ref (bv, idx, endianness)); \
748 } \
749}
750
daccfef4
LC		 751/* Return true (non-zero) if PTR has suitable alignment for TYPE. */
752#define ALIGNED_P(ptr, type) \
1002c774 753 ((scm_t_uintptr) (ptr) % alignof_type (type) == 0)
daccfef4 754
cf45ff03 755VM_DEFINE_FUNCTION (174, bv_u16_ref, "bv-u16-ref", 3)
e6eb2467 756BV_REF_WITH_ENDIANNESS (u16, u16)
cf45ff03 757VM_DEFINE_FUNCTION (175, bv_s16_ref, "bv-s16-ref", 3)
e6eb2467 758BV_REF_WITH_ENDIANNESS (s16, s16)
cf45ff03 759VM_DEFINE_FUNCTION (176, bv_u32_ref, "bv-u32-ref", 3)
e6eb2467 760BV_REF_WITH_ENDIANNESS (u32, u32)
cf45ff03 761VM_DEFINE_FUNCTION (177, bv_s32_ref, "bv-s32-ref", 3)
e6eb2467 762BV_REF_WITH_ENDIANNESS (s32, s32)
cf45ff03 763VM_DEFINE_FUNCTION (178, bv_u64_ref, "bv-u64-ref", 3)
e6eb2467 764BV_REF_WITH_ENDIANNESS (u64, u64)
cf45ff03 765VM_DEFINE_FUNCTION (179, bv_s64_ref, "bv-s64-ref", 3)
e6eb2467 766BV_REF_WITH_ENDIANNESS (s64, s64)
cf45ff03 767VM_DEFINE_FUNCTION (180, bv_f32_ref, "bv-f32-ref", 3)
e6eb2467 768BV_REF_WITH_ENDIANNESS (f32, ieee_single)
cf45ff03 769VM_DEFINE_FUNCTION (181, bv_f64_ref, "bv-f64-ref", 3)
e6eb2467
AW		 770BV_REF_WITH_ENDIANNESS (f64, ieee_double)
771
772#undef BV_REF_WITH_ENDIANNESS
773
9823fd39
LC		 774#define BV_FIXABLE_INT_REF(stem, fn_stem, type, size) \
775{ \
e25f3727 776 scm_t_signed_bits i; \
daccfef4 777 const scm_t_ ## type *int_ptr; \
9823fd39 778 ARGS2 (bv, idx); \
daccfef4 779 \
41e49280 780 VM_VALIDATE_BYTEVECTOR (bv, "bv-" #stem "-ref"); \
daccfef4
LC		 781 i = SCM_I_INUM (idx); \
782 int_ptr = (scm_t_ ## type *) (SCM_BYTEVECTOR_CONTENTS (bv) + i); \
783 \
9823fd39 784 if (SCM_LIKELY (SCM_I_INUMP (idx) \
daccfef4 785 && (i >= 0) \
9823fd39 786 && (i + size <= SCM_BYTEVECTOR_LENGTH (bv)) \
daccfef4 787 && (ALIGNED_P (int_ptr, scm_t_ ## type)))) \
a18e13a5 788 RETURN (SCM_I_MAKINUM (*int_ptr)); \
9823fd39
LC		 789 else \
790 { \
791 SYNC_REGISTER (); \
a18e13a5 792 RETURN (scm_bytevector_ ## fn_stem ## _ref (bv, idx)); \
9823fd39
LC		 793 } \
794}
795
796#define BV_INT_REF(stem, type, size) \
797{ \
e25f3727 798 scm_t_signed_bits i; \
daccfef4 799 const scm_t_ ## type *int_ptr; \
9823fd39 800 ARGS2 (bv, idx); \
daccfef4 801 \
41e49280 802 VM_VALIDATE_BYTEVECTOR (bv, "bv-" #stem "-ref"); \
daccfef4
LC		 803 i = SCM_I_INUM (idx); \
804 int_ptr = (scm_t_ ## type *) (SCM_BYTEVECTOR_CONTENTS (bv) + i); \
805 \
9823fd39 806 if (SCM_LIKELY (SCM_I_INUMP (idx) \
daccfef4 807 && (i >= 0) \
9823fd39 808 && (i + size <= SCM_BYTEVECTOR_LENGTH (bv)) \
daccfef4
LC		 809 && (ALIGNED_P (int_ptr, scm_t_ ## type)))) \
810 { \
811 scm_t_ ## type x = *int_ptr; \
9823fd39
LC		 812 if (SCM_FIXABLE (x)) \
813 RETURN (SCM_I_MAKINUM (x)); \
814 else \
815 { \
816 SYNC_REGISTER (); \
817 RETURN (scm_from_ ## type (x)); \
818 } \
819 } \
820 else \
821 { \
822 SYNC_REGISTER (); \
823 RETURN (scm_bytevector_ ## stem ## _native_ref (bv, idx)); \
824 } \
825}
826
827#define BV_FLOAT_REF(stem, fn_stem, type, size) \
828{ \
e25f3727 829 scm_t_signed_bits i; \
daccfef4 830 const type *float_ptr; \
9823fd39 831 ARGS2 (bv, idx); \
daccfef4 832 \
41e49280 833 VM_VALIDATE_BYTEVECTOR (bv, "bv-" #stem "-ref"); \
daccfef4
LC		 834 i = SCM_I_INUM (idx); \
835 float_ptr = (type *) (SCM_BYTEVECTOR_CONTENTS (bv) + i); \
836 \
9823fd39
LC		 837 SYNC_REGISTER (); \
838 if (SCM_LIKELY (SCM_I_INUMP (idx) \
daccfef4 839 && (i >= 0) \
9823fd39 840 && (i + size <= SCM_BYTEVECTOR_LENGTH (bv)) \
daccfef4
LC		 841 && (ALIGNED_P (float_ptr, type)))) \
842 RETURN (scm_from_double (*float_ptr)); \
9823fd39
LC		 843 else \
844 RETURN (scm_bytevector_ ## fn_stem ## _native_ref (bv, idx)); \
e6eb2467
AW		 845}
846
cf45ff03 847VM_DEFINE_FUNCTION (182, bv_u8_ref, "bv-u8-ref", 2)
e6eb2467 848BV_FIXABLE_INT_REF (u8, u8, uint8, 1)
cf45ff03 849VM_DEFINE_FUNCTION (183, bv_s8_ref, "bv-s8-ref", 2)
e6eb2467 850BV_FIXABLE_INT_REF (s8, s8, int8, 1)
cf45ff03 851VM_DEFINE_FUNCTION (184, bv_u16_native_ref, "bv-u16-native-ref", 2)
e6eb2467 852BV_FIXABLE_INT_REF (u16, u16_native, uint16, 2)
cf45ff03 853VM_DEFINE_FUNCTION (185, bv_s16_native_ref, "bv-s16-native-ref", 2)
e6eb2467 854BV_FIXABLE_INT_REF (s16, s16_native, int16, 2)
cf45ff03 855VM_DEFINE_FUNCTION (186, bv_u32_native_ref, "bv-u32-native-ref", 2)
dddacb23
LC		 856#if SIZEOF_VOID_P > 4
857BV_FIXABLE_INT_REF (u32, u32_native, uint32, 4)
858#else
e6eb2467 859BV_INT_REF (u32, uint32, 4)
dddacb23 860#endif
cf45ff03 861VM_DEFINE_FUNCTION (187, bv_s32_native_ref, "bv-s32-native-ref", 2)
dddacb23
LC		 862#if SIZEOF_VOID_P > 4
863BV_FIXABLE_INT_REF (s32, s32_native, int32, 4)
864#else
e6eb2467 865BV_INT_REF (s32, int32, 4)
dddacb23 866#endif
cf45ff03 867VM_DEFINE_FUNCTION (188, bv_u64_native_ref, "bv-u64-native-ref", 2)
e6eb2467 868BV_INT_REF (u64, uint64, 8)
cf45ff03 869VM_DEFINE_FUNCTION (189, bv_s64_native_ref, "bv-s64-native-ref", 2)
e6eb2467 870BV_INT_REF (s64, int64, 8)
cf45ff03 871VM_DEFINE_FUNCTION (190, bv_f32_native_ref, "bv-f32-native-ref", 2)
e6eb2467 872BV_FLOAT_REF (f32, ieee_single, float, 4)
cf45ff03 873VM_DEFINE_FUNCTION (191, bv_f64_native_ref, "bv-f64-native-ref", 2)
e6eb2467
AW		 874BV_FLOAT_REF (f64, ieee_double, double, 8)
875
876#undef BV_FIXABLE_INT_REF
877#undef BV_INT_REF
878#undef BV_FLOAT_REF
879
880
881
882#define BV_SET_WITH_ENDIANNESS(stem, fn_stem) \
883{ \
884 SCM endianness; \
885 POP (endianness); \
886 if (scm_is_eq (endianness, scm_i_native_endianness)) \
a39b116f 887 goto VM_LABEL (bv_##stem##_native_set); \
e6eb2467 888 { \
eae2438d 889 SCM bv, idx, val; POP3 (val, idx, bv); \
ad301b6d 890 SYNC_REGISTER (); \
d6f1ce3d
AW		 891 scm_bytevector_##fn_stem##_set_x (bv, idx, val, endianness); \
892 NEXT; \
e6eb2467
AW		 893 } \
894}
895
cf45ff03 896VM_DEFINE_INSTRUCTION (192, bv_u16_set, "bv-u16-set", 0, 4, 0)
e6eb2467 897BV_SET_WITH_ENDIANNESS (u16, u16)
cf45ff03 898VM_DEFINE_INSTRUCTION (193, bv_s16_set, "bv-s16-set", 0, 4, 0)
e6eb2467 899BV_SET_WITH_ENDIANNESS (s16, s16)
cf45ff03 900VM_DEFINE_INSTRUCTION (194, bv_u32_set, "bv-u32-set", 0, 4, 0)
e6eb2467 901BV_SET_WITH_ENDIANNESS (u32, u32)
cf45ff03 902VM_DEFINE_INSTRUCTION (195, bv_s32_set, "bv-s32-set", 0, 4, 0)
e6eb2467 903BV_SET_WITH_ENDIANNESS (s32, s32)
cf45ff03 904VM_DEFINE_INSTRUCTION (196, bv_u64_set, "bv-u64-set", 0, 4, 0)
e6eb2467 905BV_SET_WITH_ENDIANNESS (u64, u64)
cf45ff03 906VM_DEFINE_INSTRUCTION (197, bv_s64_set, "bv-s64-set", 0, 4, 0)
e6eb2467 907BV_SET_WITH_ENDIANNESS (s64, s64)
cf45ff03 908VM_DEFINE_INSTRUCTION (198, bv_f32_set, "bv-f32-set", 0, 4, 0)
e6eb2467 909BV_SET_WITH_ENDIANNESS (f32, ieee_single)
cf45ff03 910VM_DEFINE_INSTRUCTION (199, bv_f64_set, "bv-f64-set", 0, 4, 0)
e6eb2467
AW		 911BV_SET_WITH_ENDIANNESS (f64, ieee_double)
912
913#undef BV_SET_WITH_ENDIANNESS
914
daccfef4
LC		 915#define BV_FIXABLE_INT_SET(stem, fn_stem, type, min, max, size) \
916{ \
e25f3727 917 scm_t_signed_bits i, j = 0; \
daccfef4
LC		 918 SCM bv, idx, val; \
919 scm_t_ ## type *int_ptr; \
920 \
eae2438d 921 POP3 (val, idx, bv); \
41e49280 922 VM_VALIDATE_BYTEVECTOR (bv, "bv-" #stem "-set"); \
daccfef4
LC		 923 i = SCM_I_INUM (idx); \
924 int_ptr = (scm_t_ ## type *) (SCM_BYTEVECTOR_CONTENTS (bv) + i); \
925 \
926 if (SCM_LIKELY (SCM_I_INUMP (idx) \
927 && (i >= 0) \
928 && (i + size <= SCM_BYTEVECTOR_LENGTH (bv)) \
929 && (ALIGNED_P (int_ptr, scm_t_ ## type)) \
930 && (SCM_I_INUMP (val)) \
931 && ((j = SCM_I_INUM (val)) >= min) \
932 && (j <= max))) \
933 *int_ptr = (scm_t_ ## type) j; \
934 else \
ad301b6d
AW		 935 { \
936 SYNC_REGISTER (); \
937 scm_bytevector_ ## fn_stem ## _set_x (bv, idx, val); \
938 } \
daccfef4
LC		 939 NEXT; \
940}
941
942#define BV_INT_SET(stem, type, size) \
943{ \
e25f3727 944 scm_t_signed_bits i = 0; \
daccfef4
LC		 945 SCM bv, idx, val; \
946 scm_t_ ## type *int_ptr; \
947 \
eae2438d 948 POP3 (val, idx, bv); \
41e49280 949 VM_VALIDATE_BYTEVECTOR (bv, "bv-" #stem "-set"); \
daccfef4
LC		 950 i = SCM_I_INUM (idx); \
951 int_ptr = (scm_t_ ## type *) (SCM_BYTEVECTOR_CONTENTS (bv) + i); \
952 \
953 if (SCM_LIKELY (SCM_I_INUMP (idx) \
954 && (i >= 0) \
955 && (i + size <= SCM_BYTEVECTOR_LENGTH (bv)) \
956 && (ALIGNED_P (int_ptr, scm_t_ ## type)))) \
957 *int_ptr = scm_to_ ## type (val); \
958 else \
ad301b6d
AW		 959 { \
960 SYNC_REGISTER (); \
961 scm_bytevector_ ## stem ## _native_set_x (bv, idx, val); \
962 } \
963 NEXT; \
daccfef4
LC		 964}
965
ad301b6d
AW		 966#define BV_FLOAT_SET(stem, fn_stem, type, size) \
967{ \
968 scm_t_signed_bits i = 0; \
969 SCM bv, idx, val; \
970 type *float_ptr; \
971 \
eae2438d 972 POP3 (val, idx, bv); \
ad301b6d
AW		 973 VM_VALIDATE_BYTEVECTOR (bv, "bv-" #stem "-set"); \
974 i = SCM_I_INUM (idx); \
975 float_ptr = (type *) (SCM_BYTEVECTOR_CONTENTS (bv) + i); \
976 \
977 if (SCM_LIKELY (SCM_I_INUMP (idx) \
978 && (i >= 0) \
979 && (i + size <= SCM_BYTEVECTOR_LENGTH (bv)) \
980 && (ALIGNED_P (float_ptr, type)))) \
981 *float_ptr = scm_to_double (val); \
982 else \
983 { \
984 SYNC_REGISTER (); \
985 scm_bytevector_ ## fn_stem ## _native_set_x (bv, idx, val); \
986 } \
987 NEXT; \
e6eb2467
AW		 988}
989
cf45ff03 990VM_DEFINE_INSTRUCTION (200, bv_u8_set, "bv-u8-set", 0, 3, 0)
e6eb2467 991BV_FIXABLE_INT_SET (u8, u8, uint8, 0, SCM_T_UINT8_MAX, 1)
cf45ff03 992VM_DEFINE_INSTRUCTION (201, bv_s8_set, "bv-s8-set", 0, 3, 0)
e6eb2467 993BV_FIXABLE_INT_SET (s8, s8, int8, SCM_T_INT8_MIN, SCM_T_INT8_MAX, 1)
cf45ff03 994VM_DEFINE_INSTRUCTION (202, bv_u16_native_set, "bv-u16-native-set", 0, 3, 0)
d6f1ce3d 995BV_FIXABLE_INT_SET (u16, u16_native, uint16, 0, SCM_T_UINT16_MAX, 2)
cf45ff03 996VM_DEFINE_INSTRUCTION (203, bv_s16_native_set, "bv-s16-native-set", 0, 3, 0)
d6f1ce3d 997BV_FIXABLE_INT_SET (s16, s16_native, int16, SCM_T_INT16_MIN, SCM_T_INT16_MAX, 2)
cf45ff03 998VM_DEFINE_INSTRUCTION (204, bv_u32_native_set, "bv-u32-native-set", 0, 3, 0)
dddacb23
LC		 999#if SIZEOF_VOID_P > 4
1000BV_FIXABLE_INT_SET (u32, u32_native, uint32, 0, SCM_T_UINT32_MAX, 4)
1001#else
e6eb2467 1002BV_INT_SET (u32, uint32, 4)
dddacb23 1003#endif
cf45ff03 1004VM_DEFINE_INSTRUCTION (205, bv_s32_native_set, "bv-s32-native-set", 0, 3, 0)
dddacb23
LC		 1005#if SIZEOF_VOID_P > 4
1006BV_FIXABLE_INT_SET (s32, s32_native, int32, SCM_T_INT32_MIN, SCM_T_INT32_MAX, 4)
1007#else
e6eb2467 1008BV_INT_SET (s32, int32, 4)
dddacb23 1009#endif
cf45ff03 1010VM_DEFINE_INSTRUCTION (206, bv_u64_native_set, "bv-u64-native-set", 0, 3, 0)
e6eb2467 1011BV_INT_SET (u64, uint64, 8)
cf45ff03 1012VM_DEFINE_INSTRUCTION (207, bv_s64_native_set, "bv-s64-native-set", 0, 3, 0)
e6eb2467 1013BV_INT_SET (s64, int64, 8)
cf45ff03 1014VM_DEFINE_INSTRUCTION (208, bv_f32_native_set, "bv-f32-native-set", 0, 3, 0)
e6eb2467 1015BV_FLOAT_SET (f32, ieee_single, float, 4)
cf45ff03 1016VM_DEFINE_INSTRUCTION (209, bv_f64_native_set, "bv-f64-native-set", 0, 3, 0)
e6eb2467
AW		 1017BV_FLOAT_SET (f64, ieee_double, double, 8)
1018
1019#undef BV_FIXABLE_INT_SET
1020#undef BV_INT_SET
1021#undef BV_FLOAT_SET
1022
53e28ed9
AW		 1023/*
1024(defun renumber-ops ()
1025 "start from top of buffer and renumber 'VM_DEFINE_FOO (\n' sequences"
1026 (interactive "")
1027 (save-excursion
827dc8dc 1028 (let ((counter 127)) (goto-char (point-min))
53e28ed9
AW		 1029 (while (re-search-forward "^VM_DEFINE_[^ ]+ (\\([^,]+\\)," (point-max) t)
1030 (replace-match
1031 (number-to-string (setq counter (1+ counter)))
1032 t t nil 1)))))
1033*/
1e4b834a 1034
17e90c5e
KN		 1035/*
1036 Local Variables:
1037 c-file-style: "gnu"
1038 End:
1039*/
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