2 * UAE - The Un*x Amiga Emulator - CPU core
4 * Read 68000 CPU specs from file "table68k"
6 * Copyright 1995,1996 Bernd Schmidt
8 * Adaptation to Hatari by Thomas Huth
9 * Adaptation to Virtual Jaguar by James Hammons
11 * This file is distributed under the GNU Public License, version 3 or at
12 * your option any later version. Read the file GPLv3 for details.
16 /* 2008/04/26 [NP] Handle sz_byte for Areg as a valid srcmode if current instruction is a MOVE */
17 /* (e.g. move.b a1,(a0) ($1089)) (fix Blood Money on Superior 65) */
20 //const char ReadCpu_fileid[] = "Hatari readcpu.c : " __DATE__ " " __TIME__;
29 const struct mnemolookup lookuptab
[] = {
30 { i_ILLG
, "ILLEGAL" },
72 { i_MVR2USP
, "MVR2USP" },
73 { i_MVUSP2R
, "MVUSP2R" },
110 { i_ROXLW
, "ROXLW" },
111 { i_ROXRW
, "ROXRW" },
113 { i_MOVE2C
, "MOVE2C" },
114 { i_MOVEC2
, "MOVEC2" },
119 { i_BFTST
, "BFTST" },
120 { i_BFEXTU
, "BFEXTU" },
121 { i_BFCHG
, "BFCHG" },
122 { i_BFEXTS
, "BFEXTS" },
123 { i_BFCLR
, "BFCLR" },
124 { i_BFFFO
, "BFFFO" },
125 { i_BFSET
, "BFSET" },
126 { i_BFINS
, "BFINS" },
131 { i_CALLM
, "CALLM" },
133 { i_TRAPcc
, "TRAPcc" },
134 { i_MOVES
, "MOVES" },
136 { i_FDBcc
, "FDBcc" },
138 { i_FTRAPcc
, "FTRAPcc" },
141 { i_FSAVE
, "FSAVE" },
142 { i_FRESTORE
, "FRESTORE" },
144 { i_CINVL
, "CINVL" },
145 { i_CINVP
, "CINVP" },
146 { i_CINVA
, "CINVA" },
147 { i_CPUSHL
, "CPUSHL" },
148 { i_CPUSHP
, "CPUSHP" },
149 { i_CPUSHA
, "CPUSHA" },
150 { i_MOVE16
, "MOVE16" },
152 { i_MMUOP
, "MMUOP" },
157 struct instr
* table68k
;
160 STATIC_INLINE amodes
mode_from_str(const char * str
)
162 if (strncmp (str
, "Dreg", 4) == 0) return Dreg
;
163 if (strncmp (str
, "Areg", 4) == 0) return Areg
;
164 if (strncmp (str
, "Aind", 4) == 0) return Aind
;
165 if (strncmp (str
, "Apdi", 4) == 0) return Apdi
;
166 if (strncmp (str
, "Aipi", 4) == 0) return Aipi
;
167 if (strncmp (str
, "Ad16", 4) == 0) return Ad16
;
168 if (strncmp (str
, "Ad8r", 4) == 0) return Ad8r
;
169 if (strncmp (str
, "absw", 4) == 0) return absw
;
170 if (strncmp (str
, "absl", 4) == 0) return absl
;
171 if (strncmp (str
, "PC16", 4) == 0) return PC16
;
172 if (strncmp (str
, "PC8r", 4) == 0) return PC8r
;
173 if (strncmp (str
, "Immd", 4) == 0) return imm
;
180 STATIC_INLINE amodes
mode_from_mr(int mode
, int reg
)
201 case 7: return am_illg
;
210 static void build_insn(int insn
)
219 int flaglive
= 0, flagdead
= 0;
222 /* Note: We treat anything with unknown flags as a jump. That
223 is overkill, but "the programmer" was lazy quite often, and
224 *this* programmer can't be bothered to work out what can and
225 can't trap. Usually, this will be overwritten with the gencomp
226 based information, anyway. */
230 switch (id
.flaginfo
[j
].flagset
)
232 case fa_unset
: break;
233 case fa_isjmp
: isjmp
= 1; break;
234 case fa_isbranch
: isjmp
= 1; break;
235 case fa_zero
: flagdead
|= 1 << j
; break;
236 case fa_one
: flagdead
|= 1 << j
; break;
237 case fa_dontcare
: flagdead
|= 1 << j
; break;
238 case fa_unknown
: isjmp
= 1; flagdead
= -1; goto out1
;
239 case fa_set
: flagdead
|= 1 << j
; break;
246 switch (id
.flaginfo
[j
].flaguse
)
248 case fu_unused
: break;
249 case fu_isjmp
: isjmp
= 1; flaglive
|= 1 << j
; break;
250 case fu_maybecc
: isjmp
= 1; flaglive
|= 1 << j
; break;
251 case fu_unknown
: isjmp
= 1; flaglive
|= 1 << j
; break;
252 case fu_used
: flaglive
|= 1 << j
; break;
258 for(variants
=0; variants
<(1 << id
.n_variable
); variants
++)
264 uint16_t opc
= id
.bits
;
271 wordsizes sz
= sz_long
;
272 int srcgather
= 0, dstgather
= 0;
273 int usesrc
= 0, usedst
= 0;
275 int srcpos
= -1, dstpos
= -1;
277 amodes srcmode
= am_unknown
, destmode
= am_unknown
;
278 int srcreg
= -1, destreg
= -1;
280 for(i
=0; i
<lastbit
; i
++)
281 bitcnt
[i
] = bitval
[i
] = 0;
283 vmsk
= 1 << id
.n_variable
;
285 for(i
=0, msk
=0x8000; i
<16; i
++, msk
>>= 1)
287 if (!(msk
& id
.mask
))
289 int currbit
= id
.bitpos
[bitno
++];
292 bit_set
= (variants
& vmsk
? 1 : 0);
297 bitpos
[currbit
] = 15 - i
;
299 bitval
[currbit
] <<= 1;
300 bitval
[currbit
] |= bit_set
;
304 if (bitval
[bitj
] == 0)
307 /* first check whether this one does not match after all */
308 if (bitval
[bitz
] == 3 || bitval
[bitC
] == 1)
311 if (bitcnt
[bitI
] && (bitval
[bitI
] == 0x00 || bitval
[bitI
] == 0xff))
314 /* bitI and bitC get copied to biti and bitc */
317 bitval
[biti
] = bitval
[bitI
]; bitpos
[biti
] = bitpos
[bitI
];
321 bitval
[bitc
] = bitval
[bitC
];
324 while (opcstr
[pos
] && !isspace((unsigned)opcstr
[pos
]))
326 if (opcstr
[pos
] == '.')
332 case 'B': sz
= sz_byte
; break;
333 case 'W': sz
= sz_word
; break;
334 case 'L': sz
= sz_long
; break;
336 switch (bitval
[bitz
])
338 case 0: sz
= sz_byte
; break;
339 case 1: sz
= sz_word
; break;
340 case 2: sz
= sz_long
; break;
349 mnemonic
[mnp
] = opcstr
[pos
];
351 if (mnemonic
[mnp
] == 'f')
354 switch (bitval
[bitf
])
356 case 0: mnemonic
[mnp
] = 'R'; break;
357 case 1: mnemonic
[mnp
] = 'L'; break;
370 /* now, we have read the mnemonic and the size */
371 while (opcstr
[pos
] && isspace((unsigned)opcstr
[pos
]))
374 /* A goto a day keeps the D******a away. */
375 if (opcstr
[pos
] == 0)
378 /* parse the source address */
380 switch (opcstr
[pos
++])
385 switch (opcstr
[pos
++])
387 case 'r': srcreg
= bitval
[bitr
]; srcgather
= 1; srcpos
= bitpos
[bitr
]; break;
388 case 'R': srcreg
= bitval
[bitR
]; srcgather
= 1; srcpos
= bitpos
[bitR
]; break;
396 switch (opcstr
[pos
++])
398 case 'r': srcreg
= bitval
[bitr
]; srcgather
= 1; srcpos
= bitpos
[bitr
]; break;
399 case 'R': srcreg
= bitval
[bitR
]; srcgather
= 1; srcpos
= bitpos
[bitR
]; break;
405 case 'p': srcmode
= Apdi
; pos
++; break;
406 case 'P': srcmode
= Aipi
; pos
++; break;
414 switch (opcstr
[pos
++])
416 case 'z': srcmode
= imm
; break;
417 case '0': srcmode
= imm0
; break;
418 case '1': srcmode
= imm1
; break;
419 case '2': srcmode
= imm2
; break;
421 srcmode
= immi
; srcreg
= (int32_t)(int8_t)bitval
[biti
];
423 if (CPU_EMU_SIZE
< 4)
425 /* Used for branch instructions */
428 srcpos
= bitpos
[biti
];
433 srcmode
= immi
; srcreg
= bitval
[bitj
];
435 if (CPU_EMU_SIZE
< 3)
437 /* 1..8 for ADDQ/SUBQ and rotshi insns */
440 srcpos
= bitpos
[bitj
];
445 srcmode
= immi
; srcreg
= bitval
[bitJ
];
447 if (CPU_EMU_SIZE
< 5)
452 srcpos
= bitpos
[bitJ
];
457 srcmode
= immi
; srcreg
= bitval
[bitk
];
459 if (CPU_EMU_SIZE
< 3)
463 srcpos
= bitpos
[bitk
];
468 srcmode
= immi
; srcreg
= bitval
[bitK
];
470 if (CPU_EMU_SIZE
< 5)
475 srcpos
= bitpos
[bitK
];
480 srcmode
= immi
; srcreg
= bitval
[bitK
];
482 if (CPU_EMU_SIZE
< 5)
487 srcpos
= bitpos
[bitp
];
496 srcreg
= bitval
[bitD
];
497 srcmode
= mode_from_mr(bitval
[bitd
],bitval
[bitD
]);
499 if (srcmode
== am_illg
)
503 && (srcmode
== Areg
|| srcmode
== Dreg
|| srcmode
== Aind
504 || srcmode
== Ad16
|| srcmode
== Ad8r
|| srcmode
== Aipi
508 srcpos
= bitpos
[bitD
];
511 if (opcstr
[pos
] == '[')
515 if (opcstr
[pos
] == '!')
522 if (mode_from_str(opcstr
+ pos
) == srcmode
)
527 while (opcstr
[pos
] == ',');
533 if (opcstr
[pos
+ 4] == '-')
536 if (mode_from_str(opcstr
+ pos
) == srcmode
)
537 srcmode
= mode_from_str(opcstr
+ pos
+ 5);
546 while(mode_from_str(opcstr
+ pos
) != srcmode
)
550 if (opcstr
[pos
] == ']')
556 while(opcstr
[pos
] != ']')
565 /* Some addressing modes are invalid as destination */
566 if (srcmode
== imm
|| srcmode
== PC16
|| srcmode
== PC8r
)
571 srcreg
= bitval
[bitS
];
572 srcmode
= mode_from_mr(bitval
[bits
],bitval
[bitS
]);
574 if (srcmode
== am_illg
)
578 && (srcmode
== Areg
|| srcmode
== Dreg
|| srcmode
== Aind
579 || srcmode
== Ad16
|| srcmode
== Ad8r
|| srcmode
== Aipi
583 srcpos
= bitpos
[bitS
];
586 if (opcstr
[pos
] == '[')
590 if (opcstr
[pos
] == '!')
597 if (mode_from_str(opcstr
+ pos
) == srcmode
)
602 while (opcstr
[pos
] == ',');
608 if (opcstr
[pos
+ 4] == '-')
611 if (mode_from_str(opcstr
+ pos
) == srcmode
)
612 srcmode
= mode_from_str(opcstr
+ pos
+ 5);
621 while(mode_from_str(opcstr
+pos
) != srcmode
)
625 if (opcstr
[pos
] == ']')
631 while(opcstr
[pos
] != ']')
642 /* safety check - might have changed */
643 if (srcmode
!= Areg
&& srcmode
!= Dreg
&& srcmode
!= Aind
644 && srcmode
!= Ad16
&& srcmode
!= Ad8r
&& srcmode
!= Aipi
645 && srcmode
!= Apdi
&& srcmode
!= immi
)
650 // if (srcmode == Areg && sz == sz_byte)
651 if (srcmode
== Areg
&& sz
== sz_byte
&& strcmp(mnemonic
, "MOVE") != 0 ) // [NP] move.b is valid on 68000
654 if (opcstr
[pos
] != ',')
659 /* parse the destination address */
662 switch (opcstr
[pos
++])
667 switch (opcstr
[pos
++])
669 case 'r': destreg
= bitval
[bitr
]; dstgather
= 1; dstpos
= bitpos
[bitr
]; break;
670 case 'R': destreg
= bitval
[bitR
]; dstgather
= 1; dstpos
= bitpos
[bitR
]; break;
674 if (dstpos
< 0 || dstpos
>= 32)
681 switch (opcstr
[pos
++])
683 case 'r': destreg
= bitval
[bitr
]; dstgather
= 1; dstpos
= bitpos
[bitr
]; break;
684 case 'R': destreg
= bitval
[bitR
]; dstgather
= 1; dstpos
= bitpos
[bitR
]; break;
685 case 'x': destreg
= 0; dstgather
= 0; dstpos
= 0; break;
689 if (dstpos
< 0 || dstpos
>= 32)
694 case 'p': destmode
= Apdi
; pos
++; break;
695 case 'P': destmode
= Aipi
; pos
++; break;
703 switch (opcstr
[pos
++])
705 case 'z': destmode
= imm
; break;
706 case '0': destmode
= imm0
; break;
707 case '1': destmode
= imm1
; break;
708 case '2': destmode
= imm2
; break;
709 case 'i': destmode
= immi
; destreg
= (int32_t)(int8_t)bitval
[biti
]; break;
710 case 'j': destmode
= immi
; destreg
= bitval
[bitj
]; break;
711 case 'J': destmode
= immi
; destreg
= bitval
[bitJ
]; break;
712 case 'k': destmode
= immi
; destreg
= bitval
[bitk
]; break;
713 case 'K': destmode
= immi
; destreg
= bitval
[bitK
]; break;
718 destreg
= bitval
[bitD
];
719 destmode
= mode_from_mr(bitval
[bitd
],bitval
[bitD
]);
721 if (destmode
== am_illg
)
725 && (destmode
== Areg
|| destmode
== Dreg
|| destmode
== Aind
726 || destmode
== Ad16
|| destmode
== Ad8r
|| destmode
== Aipi
727 || destmode
== Apdi
))
730 dstpos
= bitpos
[bitD
];
733 if (opcstr
[pos
] == '[')
737 if (opcstr
[pos
] == '!')
744 if (mode_from_str(opcstr
+ pos
) == destmode
)
749 while (opcstr
[pos
] == ',');
755 if (opcstr
[pos
+4] == '-')
758 if (mode_from_str(opcstr
+ pos
) == destmode
)
759 destmode
= mode_from_str(opcstr
+ pos
+ 5);
768 while(mode_from_str(opcstr
+ pos
) != destmode
)
772 if (opcstr
[pos
] == ']')
778 while(opcstr
[pos
] != ']')
787 /* Some addressing modes are invalid as destination */
788 if (destmode
== imm
|| destmode
== PC16
|| destmode
== PC8r
)
793 destreg
= bitval
[bitS
];
794 destmode
= mode_from_mr(bitval
[bits
], bitval
[bitS
]);
796 if (destmode
== am_illg
)
799 && (destmode
== Areg
|| destmode
== Dreg
|| destmode
== Aind
800 || destmode
== Ad16
|| destmode
== Ad8r
|| destmode
== Aipi
801 || destmode
== Apdi
))
804 dstpos
= bitpos
[bitS
];
807 if (opcstr
[pos
] == '[')
811 if (opcstr
[pos
] == '!')
818 if (mode_from_str(opcstr
+ pos
) == destmode
)
823 while (opcstr
[pos
] == ',');
829 if (opcstr
[pos
+4] == '-')
832 if (mode_from_str(opcstr
+ pos
) == destmode
)
833 destmode
= mode_from_str(opcstr
+ pos
+ 5);
842 while (mode_from_str(opcstr
+ pos
) != destmode
)
846 if (opcstr
[pos
] == ']')
852 while (opcstr
[pos
] != ']')
863 /* safety check - might have changed */
864 if (destmode
!= Areg
&& destmode
!= Dreg
&& destmode
!= Aind
865 && destmode
!= Ad16
&& destmode
!= Ad8r
&& destmode
!= Aipi
871 if (destmode
== Areg
&& sz
== sz_byte
)
874 if (sz
== sz_byte
&& (destmode
== Aipi
|| destmode
== Apdi
)) {
879 /* now, we have a match */
880 if (table68k
[opc
].mnemo
!= i_ILLG
)
881 fprintf(stderr
, "Double match: %x: %s\n", opc
, opcstr
);
885 for(find
=0; ; find
++)
887 if (strcmp(mnemonic
, lookuptab
[find
].name
) == 0)
889 table68k
[opc
].mnemo
= lookuptab
[find
].mnemo
;
893 if (strlen(lookuptab
[find
].name
) == 0)
899 table68k
[opc
].mnemo
= lookuptab
[find
].mnemo
;
902 table68k
[opc
].cc
= bitval
[bitc
];
904 if (table68k
[opc
].mnemo
== i_BTST
905 || table68k
[opc
].mnemo
== i_BSET
906 || table68k
[opc
].mnemo
== i_BCLR
907 || table68k
[opc
].mnemo
== i_BCHG
)
909 sz
= (destmode
== Dreg
? sz_long
: sz_byte
);
912 table68k
[opc
].size
= sz
;
913 table68k
[opc
].sreg
= srcreg
;
914 table68k
[opc
].dreg
= destreg
;
915 table68k
[opc
].smode
= srcmode
;
916 table68k
[opc
].dmode
= destmode
;
917 table68k
[opc
].spos
= (srcgather
? srcpos
: -1);
918 table68k
[opc
].dpos
= (dstgather
? dstpos
: -1);
919 table68k
[opc
].suse
= usesrc
;
920 table68k
[opc
].duse
= usedst
;
921 table68k
[opc
].stype
= srctype
;
922 table68k
[opc
].plev
= id
.plevel
;
923 table68k
[opc
].clev
= id
.cpulevel
;
925 for (i
= 0; i
< 5; i
++) {
926 table68k
[opc
].flaginfo
[i
].flagset
= id
.flaginfo
[i
].flagset
;
927 table68k
[opc
].flaginfo
[i
].flaguse
= id
.flaginfo
[i
].flaguse
;
930 table68k
[opc
].flagdead
= flagdead
;
931 table68k
[opc
].flaglive
= flaglive
;
932 table68k
[opc
].isjmp
= isjmp
;
940 void read_table68k(void)
943 table68k
= (struct instr
*)malloc(65536 * sizeof(struct instr
));
945 for(i
=0; i
<65536; i
++)
947 table68k
[i
].mnemo
= i_ILLG
;
948 table68k
[i
].handler
= -1;
951 for(i
=0; i
<n_defs68k
; i
++)
959 static void handle_merges (long int opcode
)
966 //0011 DDDd ddss sSSS:00:-NZ00:-----:12: MOVE.W s,d[!Areg]
968 //0011 0001 1100 0011 : DDD = 0, ddd = 7, sss = 0, SSS = 3
970 if (table68k
[opcode
].spos
== -1)
977 switch (table68k
[opcode
].stype
)
980 smsk
= 7; sbitdst
= 8; break;
982 smsk
= 255; sbitdst
= 256; break;
984 smsk
= 15; sbitdst
= 16; break;
986 smsk
= 7; sbitdst
= 8; break;
988 smsk
= 7; sbitdst
= 8; break;
990 smsk
= 63; sbitdst
= 64; break;
992 smsk
= 3; sbitdst
= 4; break;
994 smsk
= 0; sbitdst
= 0;
999 smsk
<<= table68k
[opcode
].spos
;
1002 if (table68k
[opcode
].dpos
== -1)
1009 dmsk
= 7 << table68k
[opcode
].dpos
;
1013 for(srcreg
=0; srcreg
<sbitdst
; srcreg
++)
1015 for(dstreg
=0; dstreg
<dstend
; dstreg
++)
1017 uint16_t code
= opcode
;
1019 code
= (code
& ~smsk
) | (srcreg
<< table68k
[opcode
].spos
);
1020 code
= (code
& ~dmsk
) | (dstreg
<< table68k
[opcode
].dpos
);
1022 /* Check whether this is in fact the same instruction.
1023 * The instructions should never differ, except for the
1025 if (table68k
[code
].mnemo
!= table68k
[opcode
].mnemo
1026 || table68k
[code
].size
!= table68k
[opcode
].size
1027 || table68k
[code
].suse
!= table68k
[opcode
].suse
1028 || table68k
[code
].duse
!= table68k
[opcode
].duse
)
1034 if (table68k
[opcode
].suse
1035 && (table68k
[opcode
].spos
!= table68k
[code
].spos
1036 || table68k
[opcode
].smode
!= table68k
[code
].smode
1037 || table68k
[opcode
].stype
!= table68k
[code
].stype
))
1043 if (table68k
[opcode
].duse
1044 && (table68k
[opcode
].dpos
!= table68k
[code
].dpos
1045 || table68k
[opcode
].dmode
!= table68k
[code
].dmode
))
1053 table68k
[code
].handler
= opcode
;
1056 if (opcode
== 0x31C3 || code
== 0x31C3)
1058 printf("Relocate... ($%04X->$%04X)\n", (uint16_t)opcode
, code
);
1059 printf(" handler: %08X\n", table68k
[code
].handler
);
1060 printf(" dreg: %i\n", table68k
[code
].dreg
);
1061 printf(" sreg: %i\n", table68k
[code
].sreg
);
1062 printf(" dpos: %i\n", table68k
[code
].dpos
);
1063 printf(" spos: %i\n", table68k
[code
].spos
);
1064 printf(" sduse: %i\n", table68k
[code
].sduse
);
1065 printf("flagdead: %i\n", table68k
[code
].flagdead
);
1066 printf("flaglive: %i\n", table68k
[code
].flaglive
);
1075 unsigned char sduse;
1076 int flagdead:8, flaglive:8;
1077 unsigned int mnemo:8;
1079 unsigned int plev:2;
1080 unsigned int size:2;
1081 unsigned int smode:5;
1082 unsigned int stype:3;
1083 unsigned int dmode:5;
1084 unsigned int suse:1;
1085 unsigned int duse:1;
1086 unsigned int unused1:1;
1087 unsigned int clev:3;
1088 unsigned int isjmp:1;
1089 unsigned int unused2:4;
1097 // What this really does is expand the # of handlers, which is why the
1098 // opcode has to be passed into the opcode handler...
1099 // E.g., $F620 maps into $F621-F627 as well; this code does this expansion.
1100 void do_merges(void)
1106 for(opcode
=0; opcode
<65536; opcode
++)
1108 if (table68k
[opcode
].handler
!= -1 || table68k
[opcode
].mnemo
== i_ILLG
)
1112 handle_merges(opcode
);
1115 nr_cpuop_funcs
= nr
;
1119 int get_no_mismatches(void)