#ifndef MBED_ADC_H\r
#define MBED_ADC_H\r
\r
-#include "mbed.h"\r
+#include "PinNames.h" // mbed.h lib\r
#define XTAL_FREQ 12000000\r
#define MAX_ADC_CLOCK 13000000\r
#define CLKS_PER_SAMPLE 64\r
void(*_adc_m_isr)(void);\r
};\r
\r
-#endif
\ No newline at end of file
+#endif\r
#include "libs/nuts_bolts.h"
#include "libs/Module.h"
#include "libs/Kernel.h"
+#include "PinNames.h" // mbed.h lib
#include "libs/ADC/adc.h"
#include "libs/Pin.h"
return pin;
}
- ConfigValue* by_default(double value){
+ ConfigValue* by_default(double val){
this->default_set = true;
- this->default_double = value;
+ this->default_double = val;
return this;
}
- ConfigValue* by_default(std::string value){
+ ConfigValue* by_default(std::string val){
this->default_set = true;
- this->default_string = value;
+ this->default_string = val;
return this;
}
#ifndef DIGIPOT_H
#define DIGIPOT_H
-#include "I2C.h" // mbed.h lib
#include "libs/Kernel.h"
+#include "I2C.h" // mbed.h lib
#include "libs/utils.h"
#include <string>
#include <math.h>
+
class Digipot{
public:
Digipot(){ }
current = min( max( current, 0.0L ), 2.0L );
// I2C com
- this->i2c = new I2C(p9, p10);
+ this->i2c = new mbed::I2C(p9, p10);
// Initial setup
this->i2c_send( 0x58, 0x40, 0xff );
}
- I2C* i2c;
+ mbed::I2C* i2c;
};
--- /dev/null
+/******************************************************************************\r
+ * @file: LPC17xx.h\r
+ * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File for \r
+ * NXP LPC17xx Device Series \r
+ * @version: V1.04\r
+ * @date: 2. July 2009\r
+ *----------------------------------------------------------------------------\r
+ *\r
+ * Copyright (C) 2008 ARM Limited. All rights reserved.\r
+ *\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M3 \r
+ * processor based microcontrollers. This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+\r
+#ifndef __LPC17xx_H__\r
+#define __LPC17xx_H__\r
+\r
+/*\r
+ * ==========================================================================\r
+ * ---------- Interrupt Number Definition -----------------------------------\r
+ * ==========================================================================\r
+ */\r
+\r
+typedef enum IRQn\r
+{\r
+/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/\r
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */\r
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
+\r
+/****** LPC17xx Specific Interrupt Numbers *******************************************************/\r
+ WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */\r
+ TIMER0_IRQn = 1, /*!< Timer0 Interrupt */\r
+ TIMER1_IRQn = 2, /*!< Timer1 Interrupt */\r
+ TIMER2_IRQn = 3, /*!< Timer2 Interrupt */\r
+ TIMER3_IRQn = 4, /*!< Timer3 Interrupt */\r
+ UART0_IRQn = 5, /*!< UART0 Interrupt */\r
+ UART1_IRQn = 6, /*!< UART1 Interrupt */\r
+ UART2_IRQn = 7, /*!< UART2 Interrupt */\r
+ UART3_IRQn = 8, /*!< UART3 Interrupt */\r
+ PWM1_IRQn = 9, /*!< PWM1 Interrupt */\r
+ I2C0_IRQn = 10, /*!< I2C0 Interrupt */\r
+ I2C1_IRQn = 11, /*!< I2C1 Interrupt */\r
+ I2C2_IRQn = 12, /*!< I2C2 Interrupt */\r
+ SPI_IRQn = 13, /*!< SPI Interrupt */\r
+ SSP0_IRQn = 14, /*!< SSP0 Interrupt */\r
+ SSP1_IRQn = 15, /*!< SSP1 Interrupt */\r
+ PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */\r
+ RTC_IRQn = 17, /*!< Real Time Clock Interrupt */\r
+ EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */\r
+ EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */\r
+ EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */\r
+ EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */\r
+ ADC_IRQn = 22, /*!< A/D Converter Interrupt */\r
+ BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */\r
+ USB_IRQn = 24, /*!< USB Interrupt */\r
+ CAN_IRQn = 25, /*!< CAN Interrupt */\r
+ DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */\r
+ I2S_IRQn = 27, /*!< I2S Interrupt */\r
+ ENET_IRQn = 28, /*!< Ethernet Interrupt */\r
+ RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */\r
+ MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */\r
+ QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */\r
+ PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */\r
+} IRQn_Type;\r
+\r
+\r
+/*\r
+ * ==========================================================================\r
+ * ----------- Processor and Core Peripheral Section ------------------------\r
+ * ==========================================================================\r
+ */\r
+\r
+/* Configuration of the Cortex-M3 Processor and Core Peripherals */\r
+#define __MPU_PRESENT 1 /*!< MPU present or not */\r
+#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
+\r
+\r
+#include "score_cm3.h" /* Cortex-M3 processor and core peripherals */\r
+//#include "system_LPC17xx.h" /* System Header */\r
+\r
+\r
+/******************************************************************************/\r
+/* Device Specific Peripheral registers structures */\r
+/******************************************************************************/\r
+\r
+#if defined ( __CC_ARM )\r
+#pragma anon_unions\r
+#endif\r
+\r
+/*------------- System Control (SC) ------------------------------------------*/\r
+typedef struct\r
+{\r
+ __IO uint32_t FLASHCFG; /* Flash Accelerator Module */\r
+ uint32_t RESERVED0[31];\r
+ __IO uint32_t PLL0CON; /* Clocking and Power Control */\r
+ __IO uint32_t PLL0CFG;\r
+ __I uint32_t PLL0STAT;\r
+ __O uint32_t PLL0FEED;\r
+ uint32_t RESERVED1[4];\r
+ __IO uint32_t PLL1CON;\r
+ __IO uint32_t PLL1CFG;\r
+ __I uint32_t PLL1STAT;\r
+ __O uint32_t PLL1FEED;\r
+ uint32_t RESERVED2[4];\r
+ __IO uint32_t PCON;\r
+ __IO uint32_t PCONP;\r
+ uint32_t RESERVED3[15];\r
+ __IO uint32_t CCLKCFG;\r
+ __IO uint32_t USBCLKCFG;\r
+ __IO uint32_t CLKSRCSEL;\r
+ uint32_t RESERVED4[12];\r
+ __IO uint32_t EXTINT; /* External Interrupts */\r
+ uint32_t RESERVED5;\r
+ __IO uint32_t EXTMODE;\r
+ __IO uint32_t EXTPOLAR;\r
+ uint32_t RESERVED6[12];\r
+ __IO uint32_t RSID; /* Reset */\r
+ uint32_t RESERVED7[7];\r
+ __IO uint32_t SCS; /* Syscon Miscellaneous Registers */\r
+ __IO uint32_t IRCTRIM; /* Clock Dividers */\r
+ __IO uint32_t PCLKSEL0;\r
+ __IO uint32_t PCLKSEL1;\r
+ uint32_t RESERVED8[4];\r
+ __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */\r
+ uint32_t RESERVED9;\r
+ __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */\r
+ } LPC_SC_TypeDef;\r
+\r
+/*------------- Pin Connect Block (PINCON) -----------------------------------*/\r
+typedef struct\r
+{\r
+ __IO uint32_t PINSEL0;\r
+ __IO uint32_t PINSEL1;\r
+ __IO uint32_t PINSEL2;\r
+ __IO uint32_t PINSEL3;\r
+ __IO uint32_t PINSEL4;\r
+ __IO uint32_t PINSEL5;\r
+ __IO uint32_t PINSEL6;\r
+ __IO uint32_t PINSEL7;\r
+ __IO uint32_t PINSEL8;\r
+ __IO uint32_t PINSEL9;\r
+ __IO uint32_t PINSEL10;\r
+ uint32_t RESERVED0[5];\r
+ __IO uint32_t PINMODE0;\r
+ __IO uint32_t PINMODE1;\r
+ __IO uint32_t PINMODE2;\r
+ __IO uint32_t PINMODE3;\r
+ __IO uint32_t PINMODE4;\r
+ __IO uint32_t PINMODE5;\r
+ __IO uint32_t PINMODE6;\r
+ __IO uint32_t PINMODE7;\r
+ __IO uint32_t PINMODE8;\r
+ __IO uint32_t PINMODE9;\r
+ __IO uint32_t PINMODE_OD0;\r
+ __IO uint32_t PINMODE_OD1;\r
+ __IO uint32_t PINMODE_OD2;\r
+ __IO uint32_t PINMODE_OD3;\r
+ __IO uint32_t PINMODE_OD4;\r
+ __IO uint32_t I2CPADCFG;\r
+} LPC_PINCON_TypeDef;\r
+\r
+/*------------- General Purpose Input/Output (GPIO) --------------------------*/\r
+typedef struct\r
+{\r
+ __IO uint32_t FIODIR;\r
+ uint32_t RESERVED0[3];\r
+ __IO uint32_t FIOMASK;\r
+ __IO uint32_t FIOPIN;\r
+ __IO uint32_t FIOSET;\r
+ __O uint32_t FIOCLR;\r
+} LPC_GPIO_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __I uint32_t IntStatus;\r
+ __I uint32_t IO0IntStatR;\r
+ __I uint32_t IO0IntStatF;\r
+ __O uint32_t IO0IntClr;\r
+ __IO uint32_t IO0IntEnR;\r
+ __IO uint32_t IO0IntEnF;\r
+ uint32_t RESERVED0[3];\r
+ __I uint32_t IO2IntStatR;\r
+ __I uint32_t IO2IntStatF;\r
+ __O uint32_t IO2IntClr;\r
+ __IO uint32_t IO2IntEnR;\r
+ __IO uint32_t IO2IntEnF;\r
+} LPC_GPIOINT_TypeDef;\r
+\r
+/*------------- Timer (TIM) --------------------------------------------------*/\r
+typedef struct\r
+{\r
+ __IO uint32_t IR;\r
+ __IO uint32_t TCR;\r
+ __IO uint32_t TC;\r
+ __IO uint32_t PR;\r
+ __IO uint32_t PC;\r
+ __IO uint32_t MCR;\r
+ __IO uint32_t MR0;\r
+ __IO uint32_t MR1;\r
+ __IO uint32_t MR2;\r
+ __IO uint32_t MR3;\r
+ __IO uint32_t CCR;\r
+ __I uint32_t CR0;\r
+ __I uint32_t CR1;\r
+ uint32_t RESERVED0[2];\r
+ __IO uint32_t EMR;\r
+ uint32_t RESERVED1[12];\r
+ __IO uint32_t CTCR;\r
+} LPC_TIM_TypeDef;\r
+\r
+/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/\r
+typedef struct\r
+{\r
+ __IO uint32_t IR;\r
+ __IO uint32_t TCR;\r
+ __IO uint32_t TC;\r
+ __IO uint32_t PR;\r
+ __IO uint32_t PC;\r
+ __IO uint32_t MCR;\r
+ __IO uint32_t MR0;\r
+ __IO uint32_t MR1;\r
+ __IO uint32_t MR2;\r
+ __IO uint32_t MR3;\r
+ __IO uint32_t CCR;\r
+ __I uint32_t CR0;\r
+ __I uint32_t CR1;\r
+ __I uint32_t CR2;\r
+ __I uint32_t CR3;\r
+ uint32_t RESERVED0;\r
+ __IO uint32_t MR4;\r
+ __IO uint32_t MR5;\r
+ __IO uint32_t MR6;\r
+ __IO uint32_t PCR;\r
+ __IO uint32_t LER;\r
+ uint32_t RESERVED1[7];\r
+ __IO uint32_t CTCR;\r
+} LPC_PWM_TypeDef;\r
+\r
+/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/\r
+typedef struct\r
+{\r
+ union {\r
+ __I uint8_t RBR;\r
+ __O uint8_t THR;\r
+ __IO uint8_t DLL;\r
+ uint32_t RESERVED0;\r
+ };\r
+ union {\r
+ __IO uint8_t DLM;\r
+ __IO uint32_t IER;\r
+ };\r
+ union {\r
+ __I uint32_t IIR;\r
+ __O uint8_t FCR;\r
+ };\r
+ __IO uint8_t LCR;\r
+ uint8_t RESERVED1[7];\r
+ __I uint8_t LSR;\r
+ uint8_t RESERVED2[7];\r
+ __IO uint8_t SCR;\r
+ uint8_t RESERVED3[3];\r
+ __IO uint32_t ACR;\r
+ __IO uint8_t ICR;\r
+ uint8_t RESERVED4[3];\r
+ __IO uint8_t FDR;\r
+ uint8_t RESERVED5[7];\r
+ __IO uint8_t TER;\r
+ uint8_t RESERVED6[39];\r
+ __I uint8_t FIFOLVL;\r
+} LPC_UART_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ union {\r
+ __I uint8_t RBR;\r
+ __O uint8_t THR;\r
+ __IO uint8_t DLL;\r
+ uint32_t RESERVED0;\r
+ };\r
+ union {\r
+ __IO uint8_t DLM;\r
+ __IO uint32_t IER;\r
+ };\r
+ union {\r
+ __I uint32_t IIR;\r
+ __O uint8_t FCR;\r
+ };\r
+ __IO uint8_t LCR;\r
+ uint8_t RESERVED1[7];\r
+ __I uint8_t LSR;\r
+ uint8_t RESERVED2[7];\r
+ __IO uint8_t SCR;\r
+ uint8_t RESERVED3[3];\r
+ __IO uint32_t ACR;\r
+ __IO uint8_t ICR;\r
+ uint8_t RESERVED4[3];\r
+ __IO uint8_t FDR;\r
+ uint8_t RESERVED5[7];\r
+ __IO uint8_t TER;\r
+ uint8_t RESERVED6[39];\r
+ __I uint8_t FIFOLVL;\r
+ uint8_t RESERVED7[363];\r
+ __IO uint32_t DMAREQSEL;\r
+} LPC_UART0_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ union {\r
+ __I uint8_t RBR;\r
+ __O uint8_t THR;\r
+ __IO uint8_t DLL;\r
+ uint32_t RESERVED0;\r
+ };\r
+ union {\r
+ __IO uint8_t DLM;\r
+ __IO uint32_t IER;\r
+ };\r
+ union {\r
+ __I uint32_t IIR;\r
+ __O uint8_t FCR;\r
+ };\r
+ __IO uint8_t LCR;\r
+ uint8_t RESERVED1[3];\r
+ __IO uint8_t MCR;\r
+ uint8_t RESERVED2[3];\r
+ __I uint8_t LSR;\r
+ uint8_t RESERVED3[3];\r
+ __I uint8_t MSR;\r
+ uint8_t RESERVED4[3];\r
+ __IO uint8_t SCR;\r
+ uint8_t RESERVED5[3];\r
+ __IO uint32_t ACR;\r
+ uint32_t RESERVED6;\r
+ __IO uint32_t FDR;\r
+ uint32_t RESERVED7;\r
+ __IO uint8_t TER;\r
+ uint8_t RESERVED8[27];\r
+ __IO uint8_t RS485CTRL;\r
+ uint8_t RESERVED9[3];\r
+ __IO uint8_t ADRMATCH;\r
+ uint8_t RESERVED10[3];\r
+ __IO uint8_t RS485DLY;\r
+ uint8_t RESERVED11[3];\r
+ __I uint8_t FIFOLVL;\r
+} LPC_UART1_TypeDef;\r
+\r
+/*------------- Serial Peripheral Interface (SPI) ----------------------------*/\r
+typedef struct\r
+{\r
+ __IO uint32_t SPCR;\r
+ __I uint32_t SPSR;\r
+ __IO uint32_t SPDR;\r
+ __IO uint32_t SPCCR;\r
+ uint32_t RESERVED0[3];\r
+ __IO uint32_t SPINT;\r
+} LPC_SPI_TypeDef;\r
+\r
+/*------------- Synchronous Serial Communication (SSP) -----------------------*/\r
+typedef struct\r
+{\r
+ __IO uint32_t CR0;\r
+ __IO uint32_t CR1;\r
+ __IO uint32_t DR;\r
+ __I uint32_t SR;\r
+ __IO uint32_t CPSR;\r
+ __IO uint32_t IMSC;\r
+ __IO uint32_t RIS;\r
+ __IO uint32_t MIS;\r
+ __IO uint32_t ICR;\r
+ __IO uint32_t DMACR;\r
+} LPC_SSP_TypeDef;\r
+\r
+/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/\r
+typedef struct\r
+{\r
+ __IO uint32_t I2CONSET;\r
+ __I uint32_t I2STAT;\r
+ __IO uint32_t I2DAT;\r
+ __IO uint32_t I2ADR0;\r
+ __IO uint32_t I2SCLH;\r
+ __IO uint32_t I2SCLL;\r
+ __O uint32_t I2CONCLR;\r
+ __IO uint32_t MMCTRL;\r
+ __IO uint32_t I2ADR1;\r
+ __IO uint32_t I2ADR2;\r
+ __IO uint32_t I2ADR3;\r
+ __I uint32_t I2DATA_BUFFER;\r
+ __IO uint32_t I2MASK0;\r
+ __IO uint32_t I2MASK1;\r
+ __IO uint32_t I2MASK2;\r
+ __IO uint32_t I2MASK3;\r
+} LPC_I2C_TypeDef;\r
+\r
+/*------------- Inter IC Sound (I2S) -----------------------------------------*/\r
+typedef struct\r
+{\r
+ __IO uint32_t I2SDAO;\r
+ __IO uint32_t I2SDAI;\r
+ __O uint32_t I2STXFIFO;\r
+ __I uint32_t I2SRXFIFO;\r
+ __I uint32_t I2SSTATE;\r
+ __IO uint32_t I2SDMA1;\r
+ __IO uint32_t I2SDMA2;\r
+ __IO uint32_t I2SIRQ;\r
+ __IO uint32_t I2STXRATE;\r
+ __IO uint32_t I2SRXRATE;\r
+ __IO uint32_t I2STXBITRATE;\r
+ __IO uint32_t I2SRXBITRATE;\r
+ __IO uint32_t I2STXMODE;\r
+ __IO uint32_t I2SRXMODE;\r
+} LPC_I2S_TypeDef;\r
+\r
+/*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/\r
+typedef struct\r
+{\r
+ __IO uint32_t RICOMPVAL;\r
+ __IO uint32_t RIMASK;\r
+ __IO uint8_t RICTRL;\r
+ uint8_t RESERVED0[3];\r
+ __IO uint32_t RICOUNTER;\r
+} LPC_RIT_TypeDef;\r
+\r
+/*------------- Real-Time Clock (RTC) ----------------------------------------*/\r
+typedef struct\r
+{\r
+ __IO uint8_t ILR;\r
+ uint8_t RESERVED0[7];\r
+ __IO uint8_t CCR;\r
+ uint8_t RESERVED1[3];\r
+ __IO uint8_t CIIR;\r
+ uint8_t RESERVED2[3];\r
+ __IO uint8_t AMR;\r
+ uint8_t RESERVED3[3];\r
+ __I uint32_t CTIME0;\r
+ __I uint32_t CTIME1;\r
+ __I uint32_t CTIME2;\r
+ __IO uint8_t SEC;\r
+ uint8_t RESERVED4[3];\r
+ __IO uint8_t MIN;\r
+ uint8_t RESERVED5[3];\r
+ __IO uint8_t HOUR;\r
+ uint8_t RESERVED6[3];\r
+ __IO uint8_t DOM;\r
+ uint8_t RESERVED7[3];\r
+ __IO uint8_t DOW;\r
+ uint8_t RESERVED8[3];\r
+ __IO uint16_t DOY;\r
+ uint16_t RESERVED9;\r
+ __IO uint8_t MONTH;\r
+ uint8_t RESERVED10[3];\r
+ __IO uint16_t YEAR;\r
+ uint16_t RESERVED11;\r
+ __IO uint32_t CALIBRATION;\r
+ __IO uint32_t GPREG0;\r
+ __IO uint32_t GPREG1;\r
+ __IO uint32_t GPREG2;\r
+ __IO uint32_t GPREG3;\r
+ __IO uint32_t GPREG4;\r
+ __IO uint8_t RTC_AUXEN;\r
+ uint8_t RESERVED12[3];\r
+ __IO uint8_t RTC_AUX;\r
+ uint8_t RESERVED13[3];\r
+ __IO uint8_t ALSEC;\r
+ uint8_t RESERVED14[3];\r
+ __IO uint8_t ALMIN;\r
+ uint8_t RESERVED15[3];\r
+ __IO uint8_t ALHOUR;\r
+ uint8_t RESERVED16[3];\r
+ __IO uint8_t ALDOM;\r
+ uint8_t RESERVED17[3];\r
+ __IO uint8_t ALDOW;\r
+ uint8_t RESERVED18[3];\r
+ __IO uint16_t ALDOY;\r
+ uint16_t RESERVED19;\r
+ __IO uint8_t ALMON;\r
+ uint8_t RESERVED20[3];\r
+ __IO uint16_t ALYEAR;\r
+ uint16_t RESERVED21;\r
+} LPC_RTC_TypeDef;\r
+\r
+/*------------- Watchdog Timer (WDT) -----------------------------------------*/\r
+typedef struct\r
+{\r
+ __IO uint8_t WDMOD;\r
+ uint8_t RESERVED0[3];\r
+ __IO uint32_t WDTC;\r
+ __O uint8_t WDFEED;\r
+ uint8_t RESERVED1[3];\r
+ __I uint32_t WDTV;\r
+ __IO uint32_t WDCLKSEL;\r
+} LPC_WDT_TypeDef;\r
+\r
+/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/\r
+typedef struct\r
+{\r
+ __IO uint32_t ADCR;\r
+ __IO uint32_t ADGDR;\r
+ uint32_t RESERVED0;\r
+ __IO uint32_t ADINTEN;\r
+ __I uint32_t ADDR0;\r
+ __I uint32_t ADDR1;\r
+ __I uint32_t ADDR2;\r
+ __I uint32_t ADDR3;\r
+ __I uint32_t ADDR4;\r
+ __I uint32_t ADDR5;\r
+ __I uint32_t ADDR6;\r
+ __I uint32_t ADDR7;\r
+ __I uint32_t ADSTAT;\r
+ __IO uint32_t ADTRM;\r
+} LPC_ADC_TypeDef;\r
+\r
+/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/\r
+typedef struct\r
+{\r
+ __IO uint32_t DACR;\r
+ __IO uint32_t DACCTRL;\r
+ __IO uint16_t DACCNTVAL;\r
+} LPC_DAC_TypeDef;\r
+\r
+/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/\r
+typedef struct\r
+{\r
+ __I uint32_t MCCON;\r
+ __O uint32_t MCCON_SET;\r
+ __O uint32_t MCCON_CLR;\r
+ __I uint32_t MCCAPCON;\r
+ __O uint32_t MCCAPCON_SET;\r
+ __O uint32_t MCCAPCON_CLR;\r
+ __IO uint32_t MCTIM0;\r
+ __IO uint32_t MCTIM1;\r
+ __IO uint32_t MCTIM2;\r
+ __IO uint32_t MCPER0;\r
+ __IO uint32_t MCPER1;\r
+ __IO uint32_t MCPER2;\r
+ __IO uint32_t MCPW0;\r
+ __IO uint32_t MCPW1;\r
+ __IO uint32_t MCPW2;\r
+ __IO uint32_t MCDEADTIME;\r
+ __IO uint32_t MCCCP;\r
+ __IO uint32_t MCCR0;\r
+ __IO uint32_t MCCR1;\r
+ __IO uint32_t MCCR2;\r
+ __I uint32_t MCINTEN;\r
+ __O uint32_t MCINTEN_SET;\r
+ __O uint32_t MCINTEN_CLR;\r
+ __I uint32_t MCCNTCON;\r
+ __O uint32_t MCCNTCON_SET;\r
+ __O uint32_t MCCNTCON_CLR;\r
+ __I uint32_t MCINTFLAG;\r
+ __O uint32_t MCINTFLAG_SET;\r
+ __O uint32_t MCINTFLAG_CLR;\r
+ __O uint32_t MCCAP_CLR;\r
+} LPC_MCPWM_TypeDef;\r
+\r
+/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/\r
+typedef struct\r
+{\r
+ __O uint32_t QEICON;\r
+ __I uint32_t QEISTAT;\r
+ __IO uint32_t QEICONF;\r
+ __I uint32_t QEIPOS;\r
+ __IO uint32_t QEIMAXPOS;\r
+ __IO uint32_t CMPOS0;\r
+ __IO uint32_t CMPOS1;\r
+ __IO uint32_t CMPOS2;\r
+ __I uint32_t INXCNT;\r
+ __IO uint32_t INXCMP;\r
+ __IO uint32_t QEILOAD;\r
+ __I uint32_t QEITIME;\r
+ __I uint32_t QEIVEL;\r
+ __I uint32_t QEICAP;\r
+ __IO uint32_t VELCOMP;\r
+ __IO uint32_t FILTER;\r
+ uint32_t RESERVED0[998];\r
+ __O uint32_t QEIIEC;\r
+ __O uint32_t QEIIES;\r
+ __I uint32_t QEIINTSTAT;\r
+ __I uint32_t QEIIE;\r
+ __O uint32_t QEICLR;\r
+ __O uint32_t QEISET;\r
+} LPC_QEI_TypeDef;\r
+\r
+/*------------- Controller Area Network (CAN) --------------------------------*/\r
+typedef struct\r
+{\r
+ __IO uint32_t mask[512]; /* ID Masks */\r
+} LPC_CANAF_RAM_TypeDef;\r
+\r
+typedef struct /* Acceptance Filter Registers */\r
+{\r
+ __IO uint32_t AFMR;\r
+ __IO uint32_t SFF_sa;\r
+ __IO uint32_t SFF_GRP_sa;\r
+ __IO uint32_t EFF_sa;\r
+ __IO uint32_t EFF_GRP_sa;\r
+ __IO uint32_t ENDofTable;\r
+ __I uint32_t LUTerrAd;\r
+ __I uint32_t LUTerr;\r
+ __IO uint32_t FCANIE;\r
+ __IO uint32_t FCANIC0;\r
+ __IO uint32_t FCANIC1;\r
+} LPC_CANAF_TypeDef;\r
+\r
+typedef struct /* Central Registers */\r
+{\r
+ __I uint32_t CANTxSR;\r
+ __I uint32_t CANRxSR;\r
+ __I uint32_t CANMSR;\r
+} LPC_CANCR_TypeDef;\r
+\r
+typedef struct /* Controller Registers */\r
+{\r
+ __IO uint32_t MOD;\r
+ __O uint32_t CMR;\r
+ __IO uint32_t GSR;\r
+ __I uint32_t ICR;\r
+ __IO uint32_t IER;\r
+ __IO uint32_t BTR;\r
+ __IO uint32_t EWL;\r
+ __I uint32_t SR;\r
+ __IO uint32_t RFS;\r
+ __IO uint32_t RID;\r
+ __IO uint32_t RDA;\r
+ __IO uint32_t RDB;\r
+ __IO uint32_t TFI1;\r
+ __IO uint32_t TID1;\r
+ __IO uint32_t TDA1;\r
+ __IO uint32_t TDB1;\r
+ __IO uint32_t TFI2;\r
+ __IO uint32_t TID2;\r
+ __IO uint32_t TDA2;\r
+ __IO uint32_t TDB2;\r
+ __IO uint32_t TFI3;\r
+ __IO uint32_t TID3;\r
+ __IO uint32_t TDA3;\r
+ __IO uint32_t TDB3;\r
+} LPC_CAN_TypeDef;\r
+\r
+/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/\r
+typedef struct /* Common Registers */\r
+{\r
+ __I uint32_t DMACIntStat;\r
+ __I uint32_t DMACIntTCStat;\r
+ __O uint32_t DMACIntTCClear;\r
+ __I uint32_t DMACIntErrStat;\r
+ __O uint32_t DMACIntErrClr;\r
+ __I uint32_t DMACRawIntTCStat;\r
+ __I uint32_t DMACRawIntErrStat;\r
+ __I uint32_t DMACEnbldChns;\r
+ __IO uint32_t DMACSoftBReq;\r
+ __IO uint32_t DMACSoftSReq;\r
+ __IO uint32_t DMACSoftLBReq;\r
+ __IO uint32_t DMACSoftLSReq;\r
+ __IO uint32_t DMACConfig;\r
+ __IO uint32_t DMACSync;\r
+} LPC_GPDMA_TypeDef;\r
+\r
+typedef struct /* Channel Registers */\r
+{\r
+ __IO uint32_t DMACCSrcAddr;\r
+ __IO uint32_t DMACCDestAddr;\r
+ __IO uint32_t DMACCLLI;\r
+ __IO uint32_t DMACCControl;\r
+ __IO uint32_t DMACCConfig;\r
+} LPC_GPDMACH_TypeDef;\r
+\r
+/*------------- Universal Serial Bus (USB) -----------------------------------*/\r
+typedef struct\r
+{\r
+ __I uint32_t HcRevision; /* USB Host Registers */\r
+ __IO uint32_t HcControl;\r
+ __IO uint32_t HcCommandStatus;\r
+ __IO uint32_t HcInterruptStatus;\r
+ __IO uint32_t HcInterruptEnable;\r
+ __IO uint32_t HcInterruptDisable;\r
+ __IO uint32_t HcHCCA;\r
+ __I uint32_t HcPeriodCurrentED;\r
+ __IO uint32_t HcControlHeadED;\r
+ __IO uint32_t HcControlCurrentED;\r
+ __IO uint32_t HcBulkHeadED;\r
+ __IO uint32_t HcBulkCurrentED;\r
+ __I uint32_t HcDoneHead;\r
+ __IO uint32_t HcFmInterval;\r
+ __I uint32_t HcFmRemaining;\r
+ __I uint32_t HcFmNumber;\r
+ __IO uint32_t HcPeriodicStart;\r
+ __IO uint32_t HcLSTreshold;\r
+ __IO uint32_t HcRhDescriptorA;\r
+ __IO uint32_t HcRhDescriptorB;\r
+ __IO uint32_t HcRhStatus;\r
+ __IO uint32_t HcRhPortStatus1;\r
+ __IO uint32_t HcRhPortStatus2;\r
+ uint32_t RESERVED0[40];\r
+ __I uint32_t Module_ID;\r
+\r
+ __I uint32_t OTGIntSt; /* USB On-The-Go Registers */\r
+ __IO uint32_t OTGIntEn;\r
+ __O uint32_t OTGIntSet;\r
+ __O uint32_t OTGIntClr;\r
+ __IO uint32_t OTGStCtrl;\r
+ __IO uint32_t OTGTmr;\r
+ uint32_t RESERVED1[58];\r
+\r
+ __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */\r
+ __IO uint32_t USBDevIntEn;\r
+ __O uint32_t USBDevIntClr;\r
+ __O uint32_t USBDevIntSet;\r
+\r
+ __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */\r
+ __I uint32_t USBCmdData;\r
+\r
+ __I uint32_t USBRxData; /* USB Device Transfer Registers */\r
+ __O uint32_t USBTxData;\r
+ __I uint32_t USBRxPLen;\r
+ __O uint32_t USBTxPLen;\r
+ __IO uint32_t USBCtrl;\r
+ __O uint32_t USBDevIntPri;\r
+\r
+ __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */\r
+ __IO uint32_t USBEpIntEn;\r
+ __O uint32_t USBEpIntClr;\r
+ __O uint32_t USBEpIntSet;\r
+ __O uint32_t USBEpIntPri;\r
+\r
+ __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/\r
+ __O uint32_t USBEpInd;\r
+ __IO uint32_t USBMaxPSize;\r
+\r
+ __I uint32_t USBDMARSt; /* USB Device DMA Registers */\r
+ __O uint32_t USBDMARClr;\r
+ __O uint32_t USBDMARSet;\r
+ uint32_t RESERVED2[9];\r
+ __IO uint32_t USBUDCAH;\r
+ __I uint32_t USBEpDMASt;\r
+ __O uint32_t USBEpDMAEn;\r
+ __O uint32_t USBEpDMADis;\r
+ __I uint32_t USBDMAIntSt;\r
+ __IO uint32_t USBDMAIntEn;\r
+ uint32_t RESERVED3[2];\r
+ __I uint32_t USBEoTIntSt;\r
+ __O uint32_t USBEoTIntClr;\r
+ __O uint32_t USBEoTIntSet;\r
+ __I uint32_t USBNDDRIntSt;\r
+ __O uint32_t USBNDDRIntClr;\r
+ __O uint32_t USBNDDRIntSet;\r
+ __I uint32_t USBSysErrIntSt;\r
+ __O uint32_t USBSysErrIntClr;\r
+ __O uint32_t USBSysErrIntSet;\r
+ uint32_t RESERVED4[15];\r
+\r
+ __I uint32_t I2C_RX; /* USB OTG I2C Registers */\r
+ __O uint32_t I2C_WO;\r
+ __I uint32_t I2C_STS;\r
+ __IO uint32_t I2C_CTL;\r
+ __IO uint32_t I2C_CLKHI;\r
+ __O uint32_t I2C_CLKLO;\r
+ uint32_t RESERVED5[823];\r
+\r
+ union {\r
+ __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */\r
+ __IO uint32_t OTGClkCtrl;\r
+ };\r
+ union {\r
+ __I uint32_t USBClkSt;\r
+ __I uint32_t OTGClkSt;\r
+ };\r
+} LPC_USB_TypeDef;\r
+\r
+/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/\r
+typedef struct\r
+{\r
+ __IO uint32_t MAC1; /* MAC Registers */\r
+ __IO uint32_t MAC2;\r
+ __IO uint32_t IPGT;\r
+ __IO uint32_t IPGR;\r
+ __IO uint32_t CLRT;\r
+ __IO uint32_t MAXF;\r
+ __IO uint32_t SUPP;\r
+ __IO uint32_t TEST;\r
+ __IO uint32_t MCFG;\r
+ __IO uint32_t MCMD;\r
+ __IO uint32_t MADR;\r
+ __O uint32_t MWTD;\r
+ __I uint32_t MRDD;\r
+ __I uint32_t MIND;\r
+ uint32_t RESERVED0[2];\r
+ __IO uint32_t SA0;\r
+ __IO uint32_t SA1;\r
+ __IO uint32_t SA2;\r
+ uint32_t RESERVED1[45];\r
+ __IO uint32_t Command; /* Control Registers */\r
+ __I uint32_t Status;\r
+ __IO uint32_t RxDescriptor;\r
+ __IO uint32_t RxStatus;\r
+ __IO uint32_t RxDescriptorNumber;\r
+ __I uint32_t RxProduceIndex;\r
+ __IO uint32_t RxConsumeIndex;\r
+ __IO uint32_t TxDescriptor;\r
+ __IO uint32_t TxStatus;\r
+ __IO uint32_t TxDescriptorNumber;\r
+ __IO uint32_t TxProduceIndex;\r
+ __I uint32_t TxConsumeIndex;\r
+ uint32_t RESERVED2[10];\r
+ __I uint32_t TSV0;\r
+ __I uint32_t TSV1;\r
+ __I uint32_t RSV;\r
+ uint32_t RESERVED3[3];\r
+ __IO uint32_t FlowControlCounter;\r
+ __I uint32_t FlowControlStatus;\r
+ uint32_t RESERVED4[34];\r
+ __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */\r
+ __IO uint32_t RxFilterWoLStatus;\r
+ __IO uint32_t RxFilterWoLClear;\r
+ uint32_t RESERVED5;\r
+ __IO uint32_t HashFilterL;\r
+ __IO uint32_t HashFilterH;\r
+ uint32_t RESERVED6[882];\r
+ __I uint32_t IntStatus; /* Module Control Registers */\r
+ __IO uint32_t IntEnable;\r
+ __O uint32_t IntClear;\r
+ __O uint32_t IntSet;\r
+ uint32_t RESERVED7;\r
+ __IO uint32_t PowerDown;\r
+ uint32_t RESERVED8;\r
+ __IO uint32_t Module_ID;\r
+} LPC_EMAC_TypeDef;\r
+\r
+#if defined ( __CC_ARM )\r
+#pragma anon_unions\r
+#endif\r
+\r
+\r
+/******************************************************************************/\r
+/* Peripheral memory map */\r
+/******************************************************************************/\r
+/* Base addresses */\r
+#define LPC_FLASH_BASE (0x00000000UL)\r
+#define LPC_RAM_BASE (0x10000000UL)\r
+#define LPC_GPIO_BASE (0x2009C000UL)\r
+#define LPC_APB0_BASE (0x40000000UL)\r
+#define LPC_APB1_BASE (0x40080000UL)\r
+#define LPC_AHB_BASE (0x50000000UL)\r
+#define LPC_CM3_BASE (0xE0000000UL)\r
+\r
+/* APB0 peripherals */\r
+#define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)\r
+#define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)\r
+#define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)\r
+#define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)\r
+#define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)\r
+#define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)\r
+#define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)\r
+#define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000)\r
+#define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)\r
+#define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)\r
+#define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000)\r
+#define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)\r
+#define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)\r
+#define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)\r
+#define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)\r
+#define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)\r
+#define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)\r
+#define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)\r
+#define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)\r
+\r
+/* APB1 peripherals */\r
+#define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)\r
+#define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)\r
+#define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)\r
+#define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)\r
+#define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)\r
+#define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)\r
+#define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)\r
+#define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)\r
+#define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000)\r
+#define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)\r
+#define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)\r
+#define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)\r
+\r
+/* AHB peripherals */\r
+#define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000)\r
+#define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000)\r
+#define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100)\r
+#define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120)\r
+#define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140)\r
+#define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160)\r
+#define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180)\r
+#define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0)\r
+#define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0)\r
+#define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0)\r
+#define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)\r
+\r
+/* GPIOs */\r
+#define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000)\r
+#define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020)\r
+#define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040)\r
+#define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060)\r
+#define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080)\r
+\r
+\r
+/******************************************************************************/\r
+/* Peripheral declaration */\r
+/******************************************************************************/\r
+#define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )\r
+#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )\r
+#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )\r
+#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )\r
+#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )\r
+#define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )\r
+#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )\r
+#define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )\r
+#define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )\r
+#define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )\r
+#define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )\r
+#define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE )\r
+#define LPC_UART0 ((LPC_UART0_TypeDef *) LPC_UART0_BASE )\r
+#define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )\r
+#define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )\r
+#define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )\r
+#define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )\r
+#define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )\r
+#define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )\r
+#define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )\r
+#define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )\r
+#define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE )\r
+#define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )\r
+#define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )\r
+#define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE )\r
+#define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )\r
+#define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )\r
+#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )\r
+#define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )\r
+#define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)\r
+#define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )\r
+#define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )\r
+#define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )\r
+#define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )\r
+#define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )\r
+#define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )\r
+#define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )\r
+#define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )\r
+#define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )\r
+#define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )\r
+#define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )\r
+#define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )\r
+#define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )\r
+#define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )\r
+#define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )\r
+#define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )\r
+#define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )\r
+\r
+#endif // __LPC17xx_H__\r
--- /dev/null
+/******************************************************************************\r
+ * @file: core_cm3.h\r
+ * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File\r
+ * @version: V1.30 PRE-RELEASE\r
+ * @date: 30. July 2009\r
+ *----------------------------------------------------------------------------\r
+ *\r
+ * Copyright (C) 2009 ARM Limited. All rights reserved.\r
+ *\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-Mx \r
+ * processor based microcontrollers. This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifndef __CM3_CORE_H__\r
+#define __CM3_CORE_H__\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+\r
+#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */\r
+#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */\r
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (0x03) /*!< Cortex core */\r
+\r
+/**\r
+ * Lint configuration \n\r
+ * ----------------------- \n\r
+ *\r
+ * The following Lint messages will be suppressed and not shown: \n\r
+ * \n\r
+ * --- Error 10: --- \n\r
+ * register uint32_t __regBasePri __asm("basepri"); \n\r
+ * Error 10: Expecting ';' \n\r
+ * \n\r
+ * --- Error 530: --- \n\r
+ * return(__regBasePri); \n\r
+ * Warning 530: Symbol '__regBasePri' (line 264) not initialized \n\r
+ * \n\r
+ * --- Error 550: --- \n\r
+ * __regBasePri = (basePri & 0x1ff); \n\r
+ * } \n\r
+ * Warning 550: Symbol '__regBasePri' (line 271) not accessed \n\r
+ * \n\r
+ * --- Error 754: --- \n\r
+ * uint32_t RESERVED0[24]; \n\r
+ * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced \n\r
+ * \n\r
+ * --- Error 750: --- \n\r
+ * #define __CM3_CORE_H__ \n\r
+ * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n\r
+ * \n\r
+ * --- Error 528: --- \n\r
+ * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n\r
+ * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n\r
+ * \n\r
+ * --- Error 751: --- \n\r
+ * } InterruptType_Type; \n\r
+ * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n\r
+ * \n\r
+ * \n\r
+ * Note: To re-enable a Message, insert a space before 'lint' * \n\r
+ *\r
+ */\r
+\r
+/*lint -save */\r
+/*lint -e10 */\r
+/*lint -e530 */\r
+/*lint -e550 */\r
+/*lint -e754 */\r
+/*lint -e750 */\r
+/*lint -e528 */\r
+/*lint -e751 */\r
+\r
+\r
+#include <stdint.h> /* Include standard types */\r
+\r
+#if defined (__ICCARM__)\r
+ #include <intrinsics.h> /* IAR Intrinsics */\r
+#endif\r
+\r
+\r
+#ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */\r
+#endif\r
+\r
+\r
+\r
+\r
+/**\r
+ * IO definitions\r
+ *\r
+ * define access restrictions to peripheral registers\r
+ */\r
+\r
+#ifdef __cplusplus\r
+#define __I volatile /*!< defines 'read only' permissions */\r
+#else\r
+#define __I volatile const /*!< defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< defines 'write only' permissions */\r
+#define __IO volatile /*!< defines 'read / write' permissions */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ ******************************************************************************/\r
+\r
+\r
+/* System Reset */\r
+#define NVIC_VECTRESET 0 /*!< Vector Reset Bit */\r
+#define NVIC_SYSRESETREQ 2 /*!< System Reset Request */\r
+#define NVIC_AIRCR_VECTKEY (0x5FA << 16) /*!< AIRCR Key for write access */\r
+#define NVIC_AIRCR_ENDIANESS 15 /*!< Endianess */\r
+\r
+/* Core Debug */\r
+#define CoreDebug_DEMCR_TRCENA (1 << 24) /*!< DEMCR TRCENA enable */\r
+#define ITM_TCR_ITMENA 1 /*!< ITM enable */\r
+\r
+\r
+\r
+\r
+/* memory mapping struct for Nested Vectored Interrupt Controller (NVIC) */\r
+typedef struct\r
+{\r
+ __IO uint32_t ISER[8]; /*!< Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[24];\r
+ __IO uint32_t ICER[8]; /*!< Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[24];\r
+ __IO uint32_t ISPR[8]; /*!< Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[24];\r
+ __IO uint32_t ICPR[8]; /*!< Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[24];\r
+ __IO uint32_t IABR[8]; /*!< Interrupt Active bit Register */\r
+ uint32_t RESERVED4[56];\r
+ __IO uint8_t IP[240]; /*!< Interrupt Priority Register, 8Bit wide */\r
+ uint32_t RESERVED5[644];\r
+ __O uint32_t STIR; /*!< Software Trigger Interrupt Register */\r
+} NVIC_Type;\r
+\r
+\r
+/* memory mapping struct for System Control Block */\r
+typedef struct\r
+{\r
+ __I uint32_t CPUID; /*!< CPU ID Base Register */\r
+ __IO uint32_t ICSR; /*!< Interrupt Control State Register */\r
+ __IO uint32_t VTOR; /*!< Vector Table Offset Register */\r
+ __IO uint32_t AIRCR; /*!< Application Interrupt / Reset Control Register */\r
+ __IO uint32_t SCR; /*!< System Control Register */\r
+ __IO uint32_t CCR; /*!< Configuration Control Register */\r
+ __IO uint8_t SHP[12]; /*!< System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IO uint32_t SHCSR; /*!< System Handler Control and State Register */\r
+ __IO uint32_t CFSR; /*!< Configurable Fault Status Register */\r
+ __IO uint32_t HFSR; /*!< Hard Fault Status Register */\r
+ __IO uint32_t DFSR; /*!< Debug Fault Status Register */\r
+ __IO uint32_t MMFAR; /*!< Mem Manage Address Register */\r
+ __IO uint32_t BFAR; /*!< Bus Fault Address Register */\r
+ __IO uint32_t AFSR; /*!< Auxiliary Fault Status Register */\r
+ __I uint32_t PFR[2]; /*!< Processor Feature Register */\r
+ __I uint32_t DFR; /*!< Debug Feature Register */\r
+ __I uint32_t ADR; /*!< Auxiliary Feature Register */\r
+ __I uint32_t MMFR[4]; /*!< Memory Model Feature Register */\r
+ __I uint32_t ISAR[5]; /*!< ISA Feature Register */\r
+} SCB_Type;\r
+\r
+\r
+/* memory mapping struct for SysTick */\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /*!< SysTick Control and Status Register */\r
+ __IO uint32_t LOAD; /*!< SysTick Reload Value Register */\r
+ __IO uint32_t VAL; /*!< SysTick Current Value Register */\r
+ __I uint32_t CALIB; /*!< SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+\r
+/* memory mapping structur for ITM */\r
+typedef struct\r
+{\r
+ __O union \r
+ {\r
+ __O uint8_t u8; /*!< ITM Stimulus Port 8-bit */\r
+ __O uint16_t u16; /*!< ITM Stimulus Port 16-bit */\r
+ __O uint32_t u32; /*!< ITM Stimulus Port 32-bit */\r
+ } PORT [32]; /*!< ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864];\r
+ __IO uint32_t TER; /*!< ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15];\r
+ __IO uint32_t TPR; /*!< ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15];\r
+ __IO uint32_t TCR; /*!< ITM Trace Control Register */\r
+ uint32_t RESERVED3[29];\r
+ __IO uint32_t IWR; /*!< ITM Integration Write Register */\r
+ __IO uint32_t IRR; /*!< ITM Integration Read Register */\r
+ __IO uint32_t IMCR; /*!< ITM Integration Mode Control Register */\r
+ uint32_t RESERVED4[43];\r
+ __IO uint32_t LAR; /*!< ITM Lock Access Register */\r
+ __IO uint32_t LSR; /*!< ITM Lock Status Register */\r
+ uint32_t RESERVED5[6];\r
+ __I uint32_t PID4; /*!< ITM Product ID Registers */\r
+ __I uint32_t PID5;\r
+ __I uint32_t PID6;\r
+ __I uint32_t PID7;\r
+ __I uint32_t PID0;\r
+ __I uint32_t PID1;\r
+ __I uint32_t PID2;\r
+ __I uint32_t PID3;\r
+ __I uint32_t CID0;\r
+ __I uint32_t CID1;\r
+ __I uint32_t CID2;\r
+ __I uint32_t CID3;\r
+} ITM_Type;\r
+\r
+\r
+/* memory mapped struct for Interrupt Type */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0;\r
+ __I uint32_t ICTR; /*!< Interrupt Control Type Register */\r
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))\r
+ __IO uint32_t ACTLR; /*!< Auxiliary Control Register */\r
+#else\r
+ uint32_t RESERVED1;\r
+#endif\r
+} InterruptType_Type;\r
+\r
+\r
+/* Memory Protection Unit */\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)\r
+typedef struct\r
+{\r
+ __I uint32_t TYPE; /*!< MPU Type Register */\r
+ __IO uint32_t CTRL; /*!< MPU Control Register */\r
+ __IO uint32_t RNR; /*!< MPU Region RNRber Register */\r
+ __IO uint32_t RBAR; /*!< MPU Region Base Address Register */\r
+ __IO uint32_t RASR; /*!< MPU Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A1; /*!< MPU Alias 1 Region Base Address Register */\r
+ __IO uint32_t RASR_A1; /*!< MPU Alias 1 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A2; /*!< MPU Alias 2 Region Base Address Register */\r
+ __IO uint32_t RASR_A2; /*!< MPU Alias 2 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A3; /*!< MPU Alias 3 Region Base Address Register */\r
+ __IO uint32_t RASR_A3; /*!< MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type;\r
+#endif\r
+\r
+\r
+/* Core Debug Register */\r
+typedef struct\r
+{\r
+ __IO uint32_t DHCSR; /*!< Debug Halting Control and Status Register */\r
+ __O uint32_t DCRSR; /*!< Debug Core Register Selector Register */\r
+ __IO uint32_t DCRDR; /*!< Debug Core Register Data Register */\r
+ __IO uint32_t DEMCR; /*!< Debug Exception and Monitor Control Register */\r
+} CoreDebug_Type;\r
+\r
+\r
+/* Memory mapping of Cortex-M3 Hardware */\r
+#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */\r
+#define ITM_BASE (0xE0000000) /*!< ITM Base Address */\r
+#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */\r
+\r
+#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */\r
+#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */\r
+#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */\r
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ ******************************************************************************/\r
+\r
+\r
+#if defined ( __CC_ARM )\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */\r
+\r
+#elif defined ( __GNUC__ )\r
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
+\r
+#elif defined ( __TASKING__ )\r
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
+\r
+#endif\r
+\r
+\r
+/* ################### Compiler specific Intrinsics ########################### */\r
+\r
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
+/* ARM armcc specific functions */\r
+\r
+#define __enable_fault_irq __enable_fiq\r
+#define __disable_fault_irq __disable_fiq\r
+\r
+#define __NOP __nop\r
+#define __WFI __wfi\r
+#define __WFE __wfe\r
+#define __SEV __sev\r
+#define __ISB() __isb(0)\r
+#define __DSB() __dsb(0)\r
+#define __DMB() __dmb(0)\r
+#define __REV __rev\r
+#define __RBIT __rbit\r
+#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))\r
+#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))\r
+#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))\r
+#define __STREXB(value, ptr) __strex(value, ptr)\r
+#define __STREXH(value, ptr) __strex(value, ptr)\r
+#define __STREXW(value, ptr) __strex(value, ptr)\r
+\r
+\r
+/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */\r
+/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */\r
+/* intrinsic void __enable_irq(); */\r
+/* intrinsic void __disable_irq(); */\r
+\r
+\r
+#if (__ARMCC_VERSION < 400000)\r
+\r
+#else /* (__ARMCC_VERSION >= 400000) */\r
+\r
+\r
+/**\r
+ * @brief Remove the exclusive lock created by ldrex\r
+ *\r
+ * @param none\r
+ * @return none\r
+ *\r
+ * Removes the exclusive lock which is created by ldrex.\r
+ */\r
+#define __CLREX __clrex\r
+\r
+/**\r
+ * @brief Return the Base Priority value\r
+ *\r
+ * @param none\r
+ * @return uint32_t BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+static __INLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ return(__regBasePri);\r
+}\r
+\r
+/**\r
+ * @brief Set the Base Priority value\r
+ *\r
+ * @param uint32_t BasePriority\r
+ * @return none\r
+ *\r
+ * Set the base priority register\r
+ */\r
+static __INLINE void __set_BASEPRI(uint32_t basePri)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ __regBasePri = (basePri & 0xff);\r
+}\r
+\r
+/**\r
+ * @brief Return the Priority Mask value\r
+ *\r
+ * @param none\r
+ * @return uint32_t PriMask\r
+ *\r
+ * Return the state of the priority mask bit from the priority mask\r
+ * register\r
+ */\r
+static __INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ return(__regPriMask);\r
+}\r
+\r
+/**\r
+ * @brief Set the Priority Mask value\r
+ *\r
+ * @param uint32_t PriMask\r
+ * @return none\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+static __INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ __regPriMask = (priMask);\r
+}\r
+\r
+/**\r
+ * @brief Return the Fault Mask value\r
+ *\r
+ * @param none\r
+ * @return uint32_t FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+static __INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ return(__regFaultMask);\r
+}\r
+\r
+/**\r
+ * @brief Set the Fault Mask value\r
+ *\r
+ * @param uint32_t faultMask value\r
+ * @return none\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+static __INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ __regFaultMask = (faultMask & 1);\r
+}\r
+\r
+/**\r
+ * @brief Return the Control Register value\r
+ * \r
+ * @param none\r
+ * @return uint32_t Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+static __INLINE uint32_t __get_CONTROL(void)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ return(__regControl);\r
+}\r
+\r
+/**\r
+ * @brief Set the Control Register value\r
+ *\r
+ * @param uint32_t Control value\r
+ * @return none\r
+ *\r
+ * Set the control register\r
+ */\r
+static __INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ __regControl = control;\r
+}\r
+\r
+#endif /* __ARMCC_VERSION */ \r
+\r
+\r
+\r
+#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/\r
+/* IAR iccarm specific functions */\r
+\r
+#define __enable_irq __enable_interrupt /*!< global Interrupt enable */\r
+#define __disable_irq __disable_interrupt /*!< global Interrupt disable */\r
+\r
+static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }\r
+static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }\r
+\r
+#define __NOP __no_operation() /*!< no operation intrinsic in IAR Compiler */ \r
+static __INLINE void __WFI() { __ASM ("wfi"); }\r
+static __INLINE void __WFE() { __ASM ("wfe"); }\r
+static __INLINE void __SEV() { __ASM ("sev"); }\r
+static __INLINE void __CLREX() { __ASM ("clrex"); }\r
+\r
+/* intrinsic void __ISB(void) */\r
+/* intrinsic void __DSB(void) */\r
+/* intrinsic void __DMB(void) */\r
+/* intrinsic void __set_PRIMASK(); */\r
+/* intrinsic void __get_PRIMASK(); */\r
+/* intrinsic void __set_FAULTMASK(); */\r
+/* intrinsic void __get_FAULTMASK(); */\r
+/* intrinsic uint32_t __REV(uint32_t value); */\r
+/* intrinsic uint32_t __REVSH(uint32_t value); */\r
+/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */\r
+/* intrinsic unsigned long __LDREX(unsigned long *); */\r
+\r
+\r
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+\r
+static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); }\r
+static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); }\r
+\r
+static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); }\r
+static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); }\r
+\r
+static __INLINE void __NOP() { __ASM volatile ("nop"); }\r
+static __INLINE void __WFI() { __ASM volatile ("wfi"); }\r
+static __INLINE void __WFE() { __ASM volatile ("wfe"); }\r
+static __INLINE void __SEV() { __ASM volatile ("sev"); }\r
+static __INLINE void __ISB() { __ASM volatile ("isb"); }\r
+static __INLINE void __DSB() { __ASM volatile ("dsb"); }\r
+static __INLINE void __DMB() { __ASM volatile ("dmb"); }\r
+static __INLINE void __CLREX() { __ASM volatile ("clrex"); }\r
+\r
+\r
+#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/\r
+/* TASKING carm specific functions */\r
+\r
+/*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all instrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+#endif\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+\r
+\r
+/**\r
+ * @brief Set the Priority Grouping in NVIC Interrupt Controller\r
+ *\r
+ * @param uint32_t priority_grouping is priority grouping field\r
+ * @return none \r
+ *\r
+ * Set the priority grouping field using the required unlock sequence.\r
+ * The parameter priority_grouping is assigned to the field \r
+ * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.\r
+ * In case of a conflict between priority grouping and available\r
+ * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+ */\r
+static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ \r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~((0xFFFFU << 16) | (0x0F << 8)); /* clear bits to change */\r
+ reg_value = ((reg_value | NVIC_AIRCR_VECTKEY | (PriorityGroupTmp << 8))); /* Insert write key and priorty group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
+\r
+/**\r
+ * @brief Get the Priority Grouping from NVIC Interrupt Controller\r
+ *\r
+ * @param none\r
+ * @return uint32_t priority grouping field \r
+ *\r
+ * Get the priority grouping from NVIC Interrupt Controller.\r
+ * priority grouping is SCB->AIRCR [10:8] PRIGROUP field.\r
+ */\r
+static __INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((SCB->AIRCR >> 8) & 0x07); /* read priority grouping field */\r
+}\r
+\r
+/**\r
+ * @brief Enable Interrupt in NVIC Interrupt Controller\r
+ *\r
+ * @param IRQn_Type IRQn specifies the interrupt number\r
+ * @return none \r
+ *\r
+ * Enable a device specific interupt in the NVIC interrupt controller.\r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */\r
+}\r
+\r
+/**\r
+ * @brief Disable the interrupt line for external interrupt specified\r
+ * \r
+ * @param IRQn_Type IRQn is the positive number of the external interrupt\r
+ * @return none\r
+ * \r
+ * Disable a device specific interupt in the NVIC interrupt controller.\r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */\r
+}\r
+\r
+/**\r
+ * @brief Read the interrupt pending bit for a device specific interrupt source\r
+ * \r
+ * @param IRQn_Type IRQn is the number of the device specifc interrupt\r
+ * @return uint32_t 1 if pending interrupt else 0\r
+ *\r
+ * Read the pending register in NVIC and return 1 if its status is pending, \r
+ * otherwise it returns 0\r
+ */\r
+static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */\r
+}\r
+\r
+/**\r
+ * @brief Set the pending bit for an external interrupt\r
+ * \r
+ * @param IRQn_Type IRQn is the Number of the interrupt\r
+ * @return none\r
+ *\r
+ * Set the pending bit for the specified interrupt.\r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */\r
+}\r
+\r
+/**\r
+ * @brief Clear the pending bit for an external interrupt\r
+ *\r
+ * @param IRQn_Type IRQn is the Number of the interrupt\r
+ * @return none\r
+ *\r
+ * Clear the pending bit for the specified interrupt. \r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
+}\r
+\r
+/**\r
+ * @brief Read the active bit for an external interrupt\r
+ *\r
+ * @param IRQn_Type IRQn is the Number of the interrupt\r
+ * @return uint32_t 1 if active else 0\r
+ *\r
+ * Read the active register in NVIC and returns 1 if its status is active, \r
+ * otherwise it returns 0.\r
+ */\r
+static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */\r
+}\r
+\r
+/**\r
+ * @brief Set the priority for an interrupt\r
+ *\r
+ * @param IRQn_Type IRQn is the Number of the interrupt\r
+ * @param priority is the priority for the interrupt\r
+ * @return none\r
+ *\r
+ * Set the priority for the specified interrupt. The interrupt \r
+ * number can be positive to specify an external (device specific) \r
+ * interrupt, or negative to specify an internal (core) interrupt. \n\r
+ *\r
+ * Note: The priority cannot be set for every core interrupt.\r
+ */\r
+static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if(IRQn < 0) {\r
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */\r
+ else {\r
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */\r
+}\r
+\r
+/**\r
+ * @brief Read the priority for an interrupt\r
+ *\r
+ * @param IRQn_Type IRQn is the Number of the interrupt\r
+ * @return uint32_t priority is the priority for the interrupt\r
+ *\r
+ * Read the priority for the specified interrupt. The interrupt \r
+ * number can be positive to specify an external (device specific) \r
+ * interrupt, or negative to specify an internal (core) interrupt.\r
+ *\r
+ * The returned priority value is automatically aligned to the implemented\r
+ * priority bits of the microcontroller.\r
+ *\r
+ * Note: The priority cannot be set for every core interrupt.\r
+ */\r
+static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if(IRQn < 0) {\r
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */\r
+ else {\r
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
+}\r
+\r
+\r
+/**\r
+ * @brief Encode the priority for an interrupt\r
+ *\r
+ * @param uint32_t PriorityGroup is the used priority group\r
+ * @param uint32_t PreemptPriority is the preemptive priority value (starting from 0)\r
+ * @param uint32_t SubPriority is the sub priority value (starting from 0)\r
+ * @return uint32_t the priority for the interrupt\r
+ *\r
+ * Encode the priority for an interrupt with the given priority group,\r
+ * preemptive priority value and sub priority value.\r
+ * In case of a conflict between priority grouping and available\r
+ * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
+ *\r
+ * The returned priority value can be used for NVIC_SetPriority(...) function\r
+ */\r
+static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+ \r
+ return (\r
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |\r
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ * @brief Decode the priority of an interrupt\r
+ *\r
+ * @param uint32_t Priority the priority for the interrupt\r
+ * @param uint32_t PrioGroup is the used priority group\r
+ * @param uint32_t* pPreemptPrio is the preemptive priority value (starting from 0)\r
+ * @param uint32_t* pSubPrio is the sub priority value (starting from 0)\r
+ * @return none\r
+ *\r
+ * Decode an interrupt priority value with the given priority group to \r
+ * preemptive priority value and sub priority value.\r
+ * In case of a conflict between priority grouping and available\r
+ * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
+ *\r
+ * The priority value can be retrieved with NVIC_GetPriority(...) function\r
+ */\r
+static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+ \r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);\r
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);\r
+}\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+\r
+#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)\r
+\r
+/* SysTick constants */\r
+#define SYSTICK_ENABLE 0 /* Config-Bit to start or stop the SysTick Timer */\r
+#define SYSTICK_TICKINT 1 /* Config-Bit to enable or disable the SysTick interrupt */\r
+#define SYSTICK_CLKSOURCE 2 /* Clocksource has the offset 2 in SysTick Control and Status Register */\r
+#define SYSTICK_MAXCOUNT ((1<<24) -1) /* SysTick MaxCount */\r
+\r
+/**\r
+ * @brief Initialize and start the SysTick counter and its interrupt.\r
+ *\r
+ * @param uint32_t ticks is the number of ticks between two interrupts\r
+ * @return none\r
+ *\r
+ * Initialise the system tick timer and its interrupt and start the\r
+ * system tick timer / counter in free running mode to generate \r
+ * periodical interrupts.\r
+ */\r
+static __INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{ \r
+ if (ticks > SYSTICK_MAXCOUNT) return (1); /* Reload value impossible */\r
+\r
+ SysTick->LOAD = (ticks & SYSTICK_MAXCOUNT) - 1; /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */\r
+ SysTick->VAL = (0x00); /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = (1 << SYSTICK_CLKSOURCE) | (1<<SYSTICK_ENABLE) | (1<<SYSTICK_TICKINT); /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+\r
+\r
+\r
+\r
+/* ################################## Reset function ############################################ */\r
+\r
+/**\r
+ * @brief Initiate a system reset request.\r
+ *\r
+ * @param none\r
+ * @return none\r
+ *\r
+ * Initialize a system reset request to reset the MCU\r
+ */\r
+static __INLINE void NVIC_SystemReset(void)\r
+{\r
+ SCB->AIRCR = (NVIC_AIRCR_VECTKEY | (SCB->AIRCR & (0x700)) | (1<<NVIC_SYSRESETREQ)); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */ \r
+ while(1); /* wait until reset */\r
+}\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+\r
+extern volatile int ITM_RxBuffer; /* variable to receive characters */\r
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /* value identifying ITM_RxBuffer is ready for next character */\r
+\r
+\r
+/**\r
+ * @brief Outputs a character via the ITM channel 0\r
+ *\r
+ * @param uint32_t character to output\r
+ * @return uint32_t input character\r
+ *\r
+ * The function outputs a character via the ITM channel 0. \r
+ * The function returns when no debugger is connected that has booked the output. \r
+ * It is blocking when a debugger is connected, but the previous character send is not transmitted. \r
+ */\r
+static __INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+ if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &&\r
+ (ITM->TCR & ITM_TCR_ITMENA) &&\r
+ (ITM->TER & (1UL << 0)) ) \r
+ {\r
+ while (ITM->PORT[0].u32 == 0);\r
+ ITM->PORT[0].u8 = (uint8_t) ch;\r
+ } \r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Inputs a character via variable ITM_RxBuffer\r
+ *\r
+ * @param none\r
+ * @return uint32_t input character\r
+ *\r
+ * The function inputs a character via variable ITM_RxBuffer. \r
+ * The function returns when no debugger is connected that has booked the output. \r
+ * It is blocking when a debugger is connected, but the previous character send is not transmitted. \r
+ */\r
+static __INLINE int ITM_ReceiveChar (void) {\r
+ int ch = -1; /* no character available */\r
+\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {\r
+ ch = ITM_RxBuffer;\r
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
+ }\r
+ \r
+ return (ch); \r
+}\r
+\r
+\r
+/**\r
+ * @brief Check if a character via variable ITM_RxBuffer is available\r
+ *\r
+ * @param none\r
+ * @return int 1 = character available, 0 = no character available\r
+ *\r
+ * The function checks variable ITM_RxBuffer whether a character is available or not. \r
+ * The function returns '1' if a character is available and '0' if no character is available. \r
+ */\r
+static __INLINE int ITM_CheckChar (void) {\r
+\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {\r
+ return (0); /* no character available */\r
+ } else {\r
+ return (1); /* character available */\r
+ }\r
+}\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CM3_CORE_H__ */\r
+\r
+/*lint -restore */\r
#define PIN_H
#include <stdlib.h>
-#include "LPC17xx.h" // mbed.h lib
+#include "libs/LPC17xx/sLPC17xx.h" // smoothed mbed.h lib
#include "libs/Kernel.h"
#include "libs/utils.h"
#include <string>
}
inline bool get(){
- if( this->inverting ){
- return ~(( this->port->FIOPIN >> this->pin ) & 1);
- }else{
- return (( this->port->FIOPIN >> this->pin ) & 1);
- }
+ return this->inverting ^ (( this->port->FIOPIN >> this->pin ) & 1);
}
inline void set(bool value){
- // TODO : This should be bitmath
- if( this->inverting ){ value = !value; }
+// value = this->inverting ^ value;
if( value ){
this->port->FIOSET = 1 << this->pin;
}else{
#include "libs/Kernel.h"
#include "SlowTicker.h"
#include "libs/Hook.h"
+#include "system_LPC17xx.h" // mbed.h lib
SlowTicker* global_slow_ticker;
#include "libs/Module.h"
#include "libs/Kernel.h"
#include "StepTicker.h"
+#include "system_LPC17xx.h" // mbed.h lib
StepTicker* global_step_ticker;
// Treats every received line as a command and passes it ( via event call ) to the command dispatcher.
// The command dispatcher will then ask other modules if they can do something with it
SerialConsole::SerialConsole( PinName rx_pin, PinName tx_pin, int baud_rate ){
- this->serial = new Serial( rx_pin, tx_pin );
+ this->serial = new mbed::Serial( rx_pin, tx_pin );
this->serial->baud(baud_rate);
}
// Called when the module has just been loaded
void SerialConsole::on_module_loaded() {
// We want to be called every time a new char is received
- this->serial->attach(this, &SerialConsole::on_serial_char_received, Serial::RxIrq);
+ this->serial->attach(this, &SerialConsole::on_serial_char_received, mbed::Serial::RxIrq);
// We only call the command dispatcher in the main loop, nowhere else
this->register_for_event(ON_MAIN_LOOP);
#define SERIALCONSOLE_H
#include "libs/Module.h"
+#include "Serial.h" // mbed.h lib
#include "libs/Kernel.h"
#include <vector>
#include <string>
using std::string;
-#include "SerialConsole.h"
#include "libs/RingBuffer.h"
#include "libs/StreamOutput.h"
+
#define baud_rate_setting_checksum 10922
class SerialConsole : public Module, public StreamOutput {
//string receive_buffer; // Received chars are stored here until a newline character is received
//vector<std::string> received_lines; // Received lines are stored here until they are requested
RingBuffer<char,256> buffer; // Receive buffer
- Serial* serial;
+ mbed::Serial* serial;
};
#endif
#include "../communication/utils/Gcode.h"
#include "libs/Module.h"
#include "libs/Kernel.h"
+#include "wait_api.h" // mbed lib
#include "Block.h"
#include "Planner.h"
#include "Player.h"
#ifndef LASER_MODULE_H
#define LASER_MODULE_H
-#include "PwmOut.h" // mbed.h lib
#include "libs/Module.h"
+#include "PwmOut.h" // mbed.h lib
#include "libs/Kernel.h"
#include "modules/communication/utils/Gcode.h"
+
#define laser_module_enable_checksum 35529
class Laser : public Module{
void on_speed_change(void* argument);
void set_proportional_power();
- PwmOut laser_pin; // PWM output to regulate the laser power
+ mbed::PwmOut laser_pin; // PWM output to regulate the laser power
bool laser_on; // Laser status
};
#include "libs/Kernel.h"
+#include "wait_api.h" // mbed.h lib
#include "SimpleShell.h"
#include "libs/nuts_bolts.h"
#include "libs/utils.h"
HCoop / clinton / Smoothieware.git / commitdiff