1 ;; verilog-mode.el --- major mode for editing verilog source in Emacs
3 ;; Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
4 ;; 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
6 ;; Author: Michael McNamara (mac@verilog.com)
7 ;; http://www.verilog.com
9 ;; AUTO features, signal, modsig; by: Wilson Snyder
10 ;; (wsnyder@wsnyder.org)
11 ;; http://www.veripool.com
12 ;; Keywords: languages
14 ;; Yoni Rabkin <yoni@rabkins.net> contacted the maintainer of this
15 ;; file on 19/3/2008, and the maintainer agreed that when a bug is
16 ;; filed in the Emacs bug reporting system against this file, a copy
17 ;; of the bug report be sent to the maintainer's email address.
19 ;; This code supports Emacs 21.1 and later
20 ;; And XEmacs 21.1 and later
21 ;; Please do not make changes that break Emacs 21. Thanks!
25 ;; This file is part of GNU Emacs.
27 ;; GNU Emacs is free software; you can redistribute it and/or modify
28 ;; it under the terms of the GNU General Public License as published by
29 ;; the Free Software Foundation; either version 3, or (at your option)
32 ;; GNU Emacs is distributed in the hope that it will be useful,
33 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
34 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
35 ;; GNU General Public License for more details.
37 ;; You should have received a copy of the GNU General Public License
38 ;; along with GNU Emacs; see the file COPYING. If not, write to the
39 ;; Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
40 ;; Boston, MA 02110-1301, USA.
44 ;; This mode borrows heavily from the Pascal-mode and the cc-mode of Emacs
49 ;; A major mode for editing Verilog HDL source code. When you have
50 ;; entered Verilog mode, you may get more info by pressing C-h m. You
51 ;; may also get online help describing various functions by: C-h f
52 ;; <Name of function you want described>
54 ;; KNOWN BUGS / BUG REPORTS
55 ;; =======================
57 ;; Verilog is a rapidly evolving language, and hence this mode is
58 ;; under continuous development. Hence this is beta code, and likely
59 ;; has bugs. Please report any and all bugs to me at mac@verilog.com.
60 ;; Please use verilog-submit-bug-report to submit a report; type C-c
61 ;; C-b to invoke this and as a result I will have a much easier time
62 ;; of reproducing the bug you find, and hence fixing it.
64 ;; INSTALLING THE MODE
65 ;; ===================
67 ;; An older version of this mode may be already installed as a part of
68 ;; your environment, and one method of updating would be to update
69 ;; your Emacs environment. Sometimes this is difficult for local
70 ;; political/control reasons, and hence you can always install a
71 ;; private copy (or even a shared copy) which overrides the system
74 ;; You can get step by step help in installing this file by going to
75 ;; <http://www.verilog.com/emacs_install.html>
77 ;; The short list of installation instructions are: To set up
78 ;; automatic Verilog mode, put this file in your load path, and put
79 ;; the following in code (please un comment it first!) in your
80 ;; .emacs, or in your site's site-load.el
82 ; (autoload 'verilog-mode "verilog-mode" "Verilog mode" t )
83 ; (setq auto-mode-alist (cons '("\\.v\\'" . verilog-mode) auto-mode-alist))
84 ; (setq auto-mode-alist (cons '("\\.dv\\'" . verilog-mode) auto-mode-alist))
86 ;; If you want to customize Verilog mode to fit your needs better,
87 ;; you may add these lines (the values of the variables presented
88 ;; here are the defaults). Note also that if you use an Emacs that
89 ;; supports custom, it's probably better to use the custom menu to
92 ;; Be sure to examine at the help for verilog-auto, and the other
93 ;; verilog-auto-* functions for some major coding time savers.
95 ; ;; User customization for Verilog mode
96 ; (setq verilog-indent-level 3
97 ; verilog-indent-level-module 3
98 ; verilog-indent-level-declaration 3
99 ; verilog-indent-level-behavioral 3
100 ; verilog-indent-level-directive 1
101 ; verilog-case-indent 2
102 ; verilog-auto-newline t
103 ; verilog-auto-indent-on-newline t
104 ; verilog-tab-always-indent t
105 ; verilog-auto-endcomments t
106 ; verilog-minimum-comment-distance 40
107 ; verilog-indent-begin-after-if t
108 ; verilog-auto-lineup '(all)
109 ; verilog-highlight-p1800-keywords nil
110 ; verilog-linter "my_lint_shell_command"
117 ;; See commit history at http://www.veripool.com/verilog-mode.html
118 ;; (This section is required to appease checkdoc.)
122 ;; This variable will always hold the version number of the mode
123 (defconst verilog-mode-version
"404"
124 "Version of this Verilog mode.")
125 (defconst verilog-mode-release-date
"2008-03-02-GNU"
126 "Release date of this Verilog mode.")
127 (defconst verilog-mode-release-emacs t
128 "If non-nil, this version of Verilog mode was released with Emacs itself.")
130 (defun verilog-version ()
131 "Inform caller of the version of this file."
133 (message "Using verilog-mode version %s" verilog-mode-version
))
135 ;; Insure we have certain packages, and deal with it if we don't
136 ;; Be sure to note which Emacs flavor and version added each feature.
138 ;; The below were disabled when GNU Emacs 22 was released;
139 ;; perhaps some still need to be there to support Emacs 21.
140 (when (featurep 'xemacs
)
145 (require 'regexp-opt
)
147 ;; Bug in 19.28 through 19.30 skeleton.el, not provided.
154 (defmacro when
(cond &rest body
)
155 (list 'if cond
(cons 'progn body
))))
158 (if (fboundp 'unless
)
160 (defmacro unless
(cond &rest body
)
161 (cons 'if
(cons cond
(cons nil body
)))))
164 (if (fboundp 'store-match-data
)
166 (defmacro store-match-data
(&rest args
) nil
))
169 (if (fboundp 'char-before
)
171 (defmacro char-before
(&rest body
)
172 (char-after (1- (point)))))
178 (if (fboundp 'match-string-no-properties
)
180 (defsubst match-string-no-properties
(num &optional string
)
181 "Return string of text matched by last search, without text properties.
182 NUM specifies which parenthesized expression in the last regexp.
183 Value is nil if NUMth pair didn't match, or there were less than NUM pairs.
184 Zero means the entire text matched by the whole regexp or whole string.
185 STRING should be given if the last search was by `string-match' on STRING."
186 (if (match-beginning num
)
190 (match-beginning num
) (match-end num
))))
191 (set-text-properties 0 (length result
) nil result
)
193 (buffer-substring-no-properties (match-beginning num
)
198 (if (and (featurep 'custom
) (fboundp 'custom-declare-variable
))
199 nil
;; We've got what we needed
200 ;; We have the old custom-library, hack around it!
201 (defmacro defgroup
(&rest args
) nil
)
202 (defmacro customize
(&rest args
)
204 "Sorry, Customize is not available with this version of Emacs"))
205 (defmacro defcustom
(var value doc
&rest args
)
206 `(defvar ,var
,value
,doc
))
208 (if (fboundp 'defface
)
210 (defmacro defface
(var values doc
&rest args
)
214 (if (and (featurep 'custom
) (fboundp 'customize-group
))
215 nil
;; We've got what we needed
216 ;; We have an intermediate custom-library, hack around it!
217 (defmacro customize-group
(var &rest args
)
221 ;; Provide a regular expression optimization routine, using regexp-opt
222 ;; if provided by the user's elisp libraries
224 ;; The below were disabled when GNU Emacs 22 was released;
225 ;; perhaps some still need to be there to support Emacs 21.
226 (if (featurep 'xemacs
)
227 (if (fboundp 'regexp-opt
)
228 ;; regexp-opt is defined, does it take 3 or 2 arguments?
229 (if (fboundp 'function-max-args
)
230 (let ((args (function-max-args `regexp-opt
)))
232 ((eq args
3) ;; It takes 3
233 (condition-case nil
; Hide this defun from emacses
234 ;with just a two input regexp
235 (defun verilog-regexp-opt (a b
)
236 "Deal with differing number of required arguments for `regexp-opt'.
237 Call 'regexp-opt' on A and B."
241 ((eq args
2) ;; It takes 2
242 (defun verilog-regexp-opt (a b
)
243 "Call 'regexp-opt' on A and B."
247 ;; We can't tell; assume it takes 2
248 (defun verilog-regexp-opt (a b
)
249 "Call 'regexp-opt' on A and B."
252 ;; There is no regexp-opt, provide our own
253 (defun verilog-regexp-opt (strings &optional paren shy
)
254 (let ((open (if paren
"\\(" "")) (close (if paren
"\\)" "")))
255 (concat open
(mapconcat 'regexp-quote strings
"\\|") close
)))
258 (defalias 'verilog-regexp-opt
'regexp-opt
)))
261 (defun verilog-regexp-words (a)
262 "Call 'regexp-opt' with word delimiters for the words A."
263 (concat "\\<" (verilog-regexp-opt a t
) "\\>")))
265 (defun verilog-easy-menu-filter (menu)
266 "Filter a easy-menu-define to support new features."
267 (cond ((not (featurep 'xemacs
))
268 menu
) ;; GNU Emacs - passthru
269 ;; Xemacs doesn't support :help. Strip it.
270 ;; Recursively filter the a submenu
272 (mapcar 'verilog-easy-menu-filter menu
))
273 ;; Look for [:help "blah"] and remove
275 (let ((i 0) (out []))
276 (while (< i
(length menu
))
277 (if (equal `:help
(aref menu i
))
279 (setq out
(vconcat out
(vector (aref menu i
)))
282 (t menu
))) ;; Default - ok
283 ;;(verilog-easy-menu-filter
284 ;; `("Verilog" ("MA" ["SAA" nil :help "Help SAA"] ["SAB" nil :help "Help SAA"])
285 ;; "----" ["MB" nil :help "Help MB"]))
287 (defun verilog-customize ()
288 "Customize variables and other settings used by Verilog-Mode."
290 (customize-group 'verilog-mode
))
292 (defun verilog-font-customize ()
293 "Customize fonts used by Verilog-Mode."
295 (if (fboundp 'customize-apropos
)
296 (customize-apropos "font-lock-*" 'faces
)))
298 (defun verilog-booleanp (value)
299 "Return t if VALUE is boolean.
300 This implements GNU Emacs 22.1's `booleanp' function in earlier Emacs.
301 This function may be removed when Emacs 21 is no longer supported."
302 (or (equal value t
) (equal value nil
)))
304 (defalias 'verilog-syntax-ppss
305 (if (fboundp 'syntax-ppss
) 'syntax-ppss
306 (lambda (&optional pos
) (parse-partial-sexp (point-min) (or pos
(point))))))
308 (defgroup verilog-mode nil
309 "Facilitates easy editing of Verilog source text."
313 ; (defgroup verilog-mode-fonts nil
314 ; "Facilitates easy customization fonts used in Verilog source text"
315 ; :link '(customize-apropos "font-lock-*" 'faces)
316 ; :group 'verilog-mode)
318 (defgroup verilog-mode-indent nil
319 "Customize indentation and highlighting of Verilog source text."
320 :group
'verilog-mode
)
322 (defgroup verilog-mode-actions nil
323 "Customize actions on Verilog source text."
324 :group
'verilog-mode
)
326 (defgroup verilog-mode-auto nil
327 "Customize AUTO actions when expanding Verilog source text."
328 :group
'verilog-mode
)
330 (defcustom verilog-linter
331 "echo 'No verilog-linter set, see \"M-x describe-variable verilog-linter\"'"
332 "*Unix program and arguments to call to run a lint checker on Verilog source.
333 Depending on the `verilog-set-compile-command', this may be invoked when
334 you type \\[compile]. When the compile completes, \\[next-error] will take
335 you to the next lint error."
337 :group
'verilog-mode-actions
)
338 ;; We don't mark it safe, as it's used as a shell command
340 (defcustom verilog-coverage
341 "echo 'No verilog-coverage set, see \"M-x describe-variable verilog-coverage\"'"
342 "*Program and arguments to use to annotate for coverage Verilog source.
343 Depending on the `verilog-set-compile-command', this may be invoked when
344 you type \\[compile]. When the compile completes, \\[next-error] will take
345 you to the next lint error."
347 :group
'verilog-mode-actions
)
348 ;; We don't mark it safe, as it's used as a shell command
350 (defcustom verilog-simulator
351 "echo 'No verilog-simulator set, see \"M-x describe-variable verilog-simulator\"'"
352 "*Program and arguments to use to interpret Verilog source.
353 Depending on the `verilog-set-compile-command', this may be invoked when
354 you type \\[compile]. When the compile completes, \\[next-error] will take
355 you to the next lint error."
357 :group
'verilog-mode-actions
)
358 ;; We don't mark it safe, as it's used as a shell command
360 (defcustom verilog-compiler
361 "echo 'No verilog-compiler set, see \"M-x describe-variable verilog-compiler\"'"
362 "*Program and arguments to use to compile Verilog source.
363 Depending on the `verilog-set-compile-command', this may be invoked when
364 you type \\[compile]. When the compile completes, \\[next-error] will take
365 you to the next lint error."
367 :group
'verilog-mode-actions
)
368 ;; We don't mark it safe, as it's used as a shell command
370 (defvar verilog-tool
'verilog-linter
371 "Which tool to use for building compiler-command.
372 Either nil, `verilog-linter, `verilog-coverage, `verilog-simulator, or
373 `verilog-compiler. Alternatively use the \"Choose Compilation Action\"
374 menu. See `verilog-set-compile-command' for more information.")
376 (defcustom verilog-highlight-translate-off nil
377 "*Non-nil means background-highlight code excluded from translation.
378 That is, all code between \"// synopsys translate_off\" and
379 \"// synopsys translate_on\" is highlighted using a different background color
380 \(face `verilog-font-lock-translate-off-face').
382 Note: This will slow down on-the-fly fontification (and thus editing).
384 Note: Activate the new setting in a Verilog buffer by re-fontifying it (menu
385 entry \"Fontify Buffer\"). XEmacs: turn off and on font locking."
387 :group
'verilog-mode-indent
)
388 ;; Note we don't use :safe, as that would break on Emacsen before 22.0.
389 (put 'verilog-highlight-translate-off
'safe-local-variable
'verilog-booleanp
)
391 (defcustom verilog-indent-level
3
392 "*Indentation of Verilog statements with respect to containing block."
393 :group
'verilog-mode-indent
395 (put 'verilog-indent-level
'safe-local-variable
'integerp
)
397 (defcustom verilog-indent-level-module
3
398 "*Indentation of Module level Verilog statements (eg always, initial).
399 Set to 0 to get initial and always statements lined up on the left side of
401 :group
'verilog-mode-indent
403 (put 'verilog-indent-level-module
'safe-local-variable
'integerp
)
405 (defcustom verilog-indent-level-declaration
3
406 "*Indentation of declarations with respect to containing block.
407 Set to 0 to get them list right under containing block."
408 :group
'verilog-mode-indent
410 (put 'verilog-indent-level-declaration
'safe-local-variable
'integerp
)
412 (defcustom verilog-indent-declaration-macros nil
413 "*How to treat macro expansions in a declaration.
418 If non nil, treat as:
422 :group
'verilog-mode-indent
424 (put 'verilog-indent-declaration-macros
'safe-local-variable
'verilog-booleanp
)
426 (defcustom verilog-indent-lists t
427 "*How to treat indenting items in a list.
428 If t (the default), indent as:
429 always @( posedge a or
433 always @( posedge a or
435 :group
'verilog-mode-indent
437 (put 'verilog-indent-lists
'safe-local-variable
'verilog-booleanp
)
439 (defcustom verilog-indent-level-behavioral
3
440 "*Absolute indentation of first begin in a task or function block.
441 Set to 0 to get such code to start at the left side of the screen."
442 :group
'verilog-mode-indent
444 (put 'verilog-indent-level-behavioral
'safe-local-variable
'integerp
)
446 (defcustom verilog-indent-level-directive
1
447 "*Indentation to add to each level of `ifdef declarations.
448 Set to 0 to have all directives start at the left side of the screen."
449 :group
'verilog-mode-indent
451 (put 'verilog-indent-level-directive
'safe-local-variable
'integerp
)
453 (defcustom verilog-cexp-indent
2
454 "*Indentation of Verilog statements split across lines."
455 :group
'verilog-mode-indent
457 (put 'verilog-cexp-indent
'safe-local-variable
'integerp
)
459 (defcustom verilog-case-indent
2
460 "*Indentation for case statements."
461 :group
'verilog-mode-indent
463 (put 'verilog-case-indent
'safe-local-variable
'integerp
)
465 (defcustom verilog-auto-newline t
466 "*True means automatically newline after semicolons."
467 :group
'verilog-mode-indent
469 (put 'verilog-auto-newline
'safe-local-variable
'verilog-booleanp
)
471 (defcustom verilog-auto-indent-on-newline t
472 "*True means automatically indent line after newline."
473 :group
'verilog-mode-indent
475 (put 'verilog-auto-indent-on-newline
'safe-local-variable
'verilog-booleanp
)
477 (defcustom verilog-tab-always-indent t
478 "*True means TAB should always re-indent the current line.
479 A nil value means TAB will only reindent when at the beginning of the line."
480 :group
'verilog-mode-indent
482 (put 'verilog-tab-always-indent
'safe-local-variable
'verilog-booleanp
)
484 (defcustom verilog-tab-to-comment nil
485 "*True means TAB moves to the right hand column in preparation for a comment."
486 :group
'verilog-mode-actions
488 (put 'verilog-tab-to-comment
'safe-local-variable
'verilog-booleanp
)
490 (defcustom verilog-indent-begin-after-if t
491 "*If true, indent begin statements following if, else, while, for and repeat.
492 Otherwise, line them up."
493 :group
'verilog-mode-indent
495 (put 'verilog-indent-begin-after-if
'safe-local-variable
'verilog-booleanp
)
498 (defcustom verilog-align-ifelse nil
499 "*If true, align `else' under matching `if'.
500 Otherwise else is lined up with first character on line holding matching if."
501 :group
'verilog-mode-indent
503 (put 'verilog-align-ifelse
'safe-local-variable
'verilog-booleanp
)
505 (defcustom verilog-minimum-comment-distance
10
506 "*Minimum distance (in lines) between begin and end required before a comment.
507 Setting this variable to zero results in every end acquiring a comment; the
508 default avoids too many redundant comments in tight quarters."
509 :group
'verilog-mode-indent
511 (put 'verilog-minimum-comment-distance
'safe-local-variable
'integerp
)
513 (defcustom verilog-auto-lineup
'(declaration)
514 "*Algorithm for lining up statements on multiple lines.
516 If this list contains the symbol 'all', then all line ups described below
519 If this list contains the symbol 'declaration', then declarations are lined up
520 with any preceding declarations, taking into account widths and the like, so
521 for example the code:
528 If this list contains the symbol 'assignment', then assignments are lined up
529 with any preceding assignments, so for example the code
530 a_long_variable = b + c;
533 a_long_variable = b + c;
536 ;; The following is not implemented:
537 ;If this list contains the symbol 'case', then case items are lined up
538 ;with any preceding case items, so for example the code
540 ; a_long_state : a = 3;
545 ; a_long_state : a = 3;
550 :group
'verilog-mode-indent
552 (put 'verilog-auto-lineup
'safe-local-variable
'listp
)
554 (defcustom verilog-highlight-p1800-keywords nil
555 "*True means highlight words newly reserved by IEEE-1800.
556 These will appear in `verilog-font-lock-p1800-face' in order to gently
557 suggest changing where these words are used as variables to something else.
558 A nil value means highlight these words as appropriate for the SystemVerilog
559 IEEE-1800 standard. Note that changing this will require restarting Emacs
560 to see the effect as font color choices are cached by Emacs."
561 :group
'verilog-mode-indent
563 (put 'verilog-highlight-p1800-keywords
'safe-local-variable
'verilog-booleanp
)
565 (defcustom verilog-highlight-grouping-keywords nil
566 "*True means highlight grouping keywords 'begin' and 'end' more dramatically.
567 If false, these words are in the font-lock-type-face; if True then they are in
568 `verilog-font-lock-ams-face'. Some find that special highlighting on these
569 grouping constructs allow the structure of the code to be understood at a glance."
570 :group
'verilog-mode-indent
572 (put 'verilog-highlight-grouping-keywords
'safe-local-variable
'verilog-booleanp
)
574 (defcustom verilog-auto-endcomments t
575 "*True means insert a comment /* ... */ after 'end's.
576 The name of the function or case will be set between the braces."
577 :group
'verilog-mode-actions
579 (put 'verilog-auto-endcomments
'safe-local-variable
'verilog-booleanp
)
581 (defcustom verilog-auto-read-includes nil
582 "*True means to automatically read includes before AUTOs.
583 This will do a `verilog-read-defines' and `verilog-read-includes' before
584 each AUTO expansion. This makes it easier to embed defines and includes,
585 but can result in very slow reading times if there are many or large
587 :group
'verilog-mode-actions
589 (put 'verilog-auto-read-includes
'safe-local-variable
'verilog-booleanp
)
591 (defcustom verilog-auto-save-policy nil
592 "*Non-nil indicates action to take when saving a Verilog buffer with AUTOs.
593 A value of `force' will always do a \\[verilog-auto] automatically if
594 needed on every save. A value of `detect' will do \\[verilog-auto]
595 automatically when it thinks necessary. A value of `ask' will query the
596 user when it thinks updating is needed.
598 You should not rely on the 'ask or 'detect policies, they are safeguards
599 only. They do not detect when AUTOINSTs need to be updated because a
600 sub-module's port list has changed."
601 :group
'verilog-mode-actions
602 :type
'(choice (const nil
) (const ask
) (const detect
) (const force
)))
604 (defcustom verilog-auto-star-expand t
605 "*Non-nil indicates to expand a SystemVerilog .* instance ports.
606 They will be expanded in the same way as if there was a AUTOINST in the
607 instantiation. See also `verilog-auto-star' and `verilog-auto-star-save'."
608 :group
'verilog-mode-actions
610 (put 'verilog-auto-star-expand
'safe-local-variable
'verilog-booleanp
)
612 (defcustom verilog-auto-star-save nil
613 "*Non-nil indicates to save to disk SystemVerilog .* instance expansions.
614 A nil value indicates direct connections will be removed before saving.
615 Only meaningful to those created due to `verilog-auto-star-expand' being set.
617 Instead of setting this, you may want to use /*AUTOINST*/, which will
619 :group
'verilog-mode-actions
621 (put 'verilog-auto-star-save
'safe-local-variable
'verilog-booleanp
)
623 (defvar verilog-auto-update-tick nil
624 "Modification tick at which autos were last performed.")
626 (defvar verilog-auto-last-file-locals nil
627 "Text from file-local-variables during last evaluation.")
629 (defvar verilog-error-regexp-add-didit nil
)
630 (defvar verilog-error-regexp nil
)
631 (setq verilog-error-regexp-add-didit nil
635 ;; ("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 1 2)
636 ; Most SureFire tools
637 ("\\(WARNING\\|ERROR\\|INFO\\)[^:]*: \\([^,]+\\), \\(line \\|\\)\\([0-9]+\\):" 2 4 )
639 \\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\
640 :\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 2 5)
642 ; Error! in file /homes/mac/Axis/Xsim/test.v at line 13 [OBJ_NOT_DECLARED]
643 ("\\(Error\\|Warning\\).*in file (\\([^ \t]+\\) at line *\\([0-9]+\\))" 2 3)
645 ("\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 2 3)
646 ("Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 2)
647 ("\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 2 3)
648 ("syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 1 2)
650 ("%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 3 4)
651 ("%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 3 4)
653 ("\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 3)
654 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\([0-9]+\\):.*$" 1 2) ; vxl
655 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+line[ \t]+\\([0-9]+\\):.*$" 1 2)
657 (".*\\*[WE],[0-9A-Z]+ (\\([^ \t,]+\\),\\([0-9]+\\)|" 1 2)
659 ("In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\[\\(Warning\\|Error\\|Failure\\)\\][^\n]*" 1 2)
661 ; "*List of regexps for Verilog compilers, like verilint. See compilation-error-regexp-alist for the formatting."
664 (defvar verilog-error-font-lock-keywords
666 ("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 1 bold t
)
667 ("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 2 bold t
)
669 ("\\(WARNING\\|ERROR\\|INFO\\): \\([^,]+\\), line \\([0-9]+\\):" 2 bold t
)
670 ("\\(WARNING\\|ERROR\\|INFO\\): \\([^,]+\\), line \\([0-9]+\\):" 3 bold t
)
673 \\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\
674 :\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 bold t
)
676 \\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\
677 :\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 bold t
)
679 ("\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 2 bold t
)
680 ("\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 3 bold t
)
682 ("%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 3 bold t
)
683 ("%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 4 bold t
)
685 ("Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 bold t
)
686 ("Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 bold t
)
688 ("\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 2 bold t
)
689 ("\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 3 bold t
)
691 ("syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 1 bold t
)
692 ("syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 2 bold t
)
694 ("\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 bold t
)
695 ("\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 bold t
)
697 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\([0-9]+\\):.*$" 1 bold t
)
698 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\([0-9]+\\):.*$" 2 bold t
)
700 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+line[ \t]+\\([0-9]+\\):.*$" 1 bold t
)
701 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+line[ \t]+\\([0-9]+\\):.*$" 2 bold t
)
703 (".*[WE],[0-9A-Z]+ (\\([^ \t,]+\\),\\([0-9]+\\)|" 1 bold t
)
704 (".*[WE],[0-9A-Z]+ (\\([^ \t,]+\\),\\([0-9]+\\)|" 2 bold t
)
706 ("In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\[\\(Warning\\|Error\\|Failure\\)\\][^\n]*" 1 bold t
)
707 ("In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\[\\(Warning\\|Error\\|Failure\\)\\][^\n]*" 2 bold t
)
709 "*Keywords to also highlight in Verilog *compilation* buffers.")
711 (defcustom verilog-library-flags
'("")
712 "*List of standard Verilog arguments to use for /*AUTOINST*/.
713 These arguments are used to find files for `verilog-auto', and match
714 the flags accepted by a standard Verilog-XL simulator.
716 -f filename Reads more `verilog-library-flags' from the filename.
717 +incdir+dir Adds the directory to `verilog-library-directories'.
718 -Idir Adds the directory to `verilog-library-directories'.
719 -y dir Adds the directory to `verilog-library-directories'.
720 +libext+.v Adds the extensions to `verilog-library-extensions'.
721 -v filename Adds the filename to `verilog-library-files'.
723 filename Adds the filename to `verilog-library-files'.
724 This is not recommended, -v is a better choice.
726 You might want these defined in each file; put at the *END* of your file
730 // verilog-library-flags:(\"-y dir -y otherdir\")
733 Verilog-mode attempts to detect changes to this local variable, but they
734 are only insured to be correct when the file is first visited. Thus if you
735 have problems, use \\[find-alternate-file] RET to have these take effect.
737 See also the variables mentioned above."
738 :group
'verilog-mode-auto
739 :type
'(repeat string
))
740 (put 'verilog-library-flags
'safe-local-variable
'listp
)
742 (defcustom verilog-library-directories
'(".")
743 "*List of directories when looking for files for /*AUTOINST*/.
744 The directory may be relative to the current file, or absolute.
745 Environment variables are also expanded in the directory names.
746 Having at least the current directory is a good idea.
748 You might want these defined in each file; put at the *END* of your file
752 // verilog-library-directories:(\".\" \"subdir\" \"subdir2\")
755 Verilog-mode attempts to detect changes to this local variable, but they
756 are only insured to be correct when the file is first visited. Thus if you
757 have problems, use \\[find-alternate-file] RET to have these take effect.
759 See also `verilog-library-flags', `verilog-library-files'
760 and `verilog-library-extensions'."
761 :group
'verilog-mode-auto
762 :type
'(repeat file
))
763 (put 'verilog-library-directories
'safe-local-variable
'listp
)
765 (defcustom verilog-library-files
'()
766 "*List of files to search for modules.
767 AUTOINST will use this when it needs to resolve a module name.
768 This is a complete path, usually to a technology file with many standard
771 You might want these defined in each file; put at the *END* of your file
775 // verilog-library-files:(\"/some/path/technology.v\" \"/some/path/tech2.v\")
778 Verilog-mode attempts to detect changes to this local variable, but they
779 are only insured to be correct when the file is first visited. Thus if you
780 have problems, use \\[find-alternate-file] RET to have these take effect.
782 See also `verilog-library-flags', `verilog-library-directories'."
783 :group
'verilog-mode-auto
784 :type
'(repeat directory
))
785 (put 'verilog-library-files
'safe-local-variable
'listp
)
787 (defcustom verilog-library-extensions
'(".v")
788 "*List of extensions to use when looking for files for /*AUTOINST*/.
789 See also `verilog-library-flags', `verilog-library-directories'."
790 :type
'(repeat string
)
791 :group
'verilog-mode-auto
)
792 (put 'verilog-library-extensions
'safe-local-variable
'listp
)
794 (defcustom verilog-active-low-regexp nil
795 "*If set, treat signals matching this regexp as active low.
796 This is used for AUTORESET and AUTOTIEOFF. For proper behavior,
797 you will probably also need `verilog-auto-reset-widths' set."
798 :group
'verilog-mode-auto
800 (put 'verilog-active-low-regexp
'safe-local-variable
'stringp
)
802 (defcustom verilog-auto-sense-include-inputs nil
803 "*If true, AUTOSENSE should include all inputs.
804 If nil, only inputs that are NOT output signals in the same block are
806 :group
'verilog-mode-auto
808 (put 'verilog-auto-sense-include-inputs
'safe-local-variable
'verilog-booleanp
)
810 (defcustom verilog-auto-sense-defines-constant nil
811 "*If true, AUTOSENSE should assume all defines represent constants.
812 When true, the defines will not be included in sensitivity lists. To
813 maintain compatibility with other sites, this should be set at the bottom
814 of each Verilog file that requires it, rather than being set globally."
815 :group
'verilog-mode-auto
817 (put 'verilog-auto-sense-defines-constant
'safe-local-variable
'verilog-booleanp
)
819 (defcustom verilog-auto-reset-widths t
820 "*If true, AUTORESET should determine the width of signals.
821 This is then used to set the width of the zero (32'h0 for example). This
822 is required by some lint tools that aren't smart enough to ignore widths of
823 the constant zero. This may result in ugly code when parameters determine
824 the MSB or LSB of a signal inside an AUTORESET."
826 :group
'verilog-mode-auto
)
827 (put 'verilog-auto-reset-widths
'safe-local-variable
'verilog-booleanp
)
829 (defcustom verilog-assignment-delay
""
830 "*Text used for delays in delayed assignments. Add a trailing space if set."
831 :group
'verilog-mode-auto
833 (put 'verilog-assignment-delay
'safe-local-variable
'stringp
)
835 (defcustom verilog-auto-inst-vector t
836 "*If true, when creating default ports with AUTOINST, use bus subscripts.
837 If nil, skip the subscript when it matches the entire bus as declared in
838 the module (AUTOWIRE signals always are subscripted, you must manually
839 declare the wire to have the subscripts removed.) Setting this to nil may
840 speed up some simulators, but is less general and harder to read, so avoid."
841 :group
'verilog-mode-auto
843 (put 'verilog-auto-inst-vector
'safe-local-variable
'verilog-booleanp
)
845 (defcustom verilog-auto-inst-template-numbers nil
846 "*If true, when creating templated ports with AUTOINST, add a comment.
847 The comment will add the line number of the template that was used for that
848 port declaration. Setting this aids in debugging, but nil is suggested for
849 regular use to prevent large numbers of merge conflicts."
850 :group
'verilog-mode-auto
852 (put 'verilog-auto-inst-template-numbers
'safe-local-variable
'verilog-booleanp
)
854 (defvar verilog-auto-inst-column
40
855 "Column number for first part of auto-inst.")
857 (defcustom verilog-auto-input-ignore-regexp nil
858 "*If set, when creating AUTOINPUT list, ignore signals matching this regexp.
859 See the \\[verilog-faq] for examples on using this."
860 :group
'verilog-mode-auto
862 (put 'verilog-auto-input-ignore-regexp
'safe-local-variable
'stringp
)
864 (defcustom verilog-auto-inout-ignore-regexp nil
865 "*If set, when creating AUTOINOUT list, ignore signals matching this regexp.
866 See the \\[verilog-faq] for examples on using this."
867 :group
'verilog-mode-auto
869 (put 'verilog-auto-inout-ignore-regexp
'safe-local-variable
'stringp
)
871 (defcustom verilog-auto-output-ignore-regexp nil
872 "*If set, when creating AUTOOUTPUT list, ignore signals matching this regexp.
873 See the \\[verilog-faq] for examples on using this."
874 :group
'verilog-mode-auto
876 (put 'verilog-auto-output-ignore-regexp
'safe-local-variable
'stringp
)
878 (defcustom verilog-auto-unused-ignore-regexp nil
879 "*If set, when creating AUTOUNUSED list, ignore signals matching this regexp.
880 See the \\[verilog-faq] for examples on using this."
881 :group
'verilog-mode-auto
883 (put 'verilog-auto-unused-ignore-regexp
'safe-local-variable
'stringp
)
885 (defcustom verilog-typedef-regexp nil
886 "*If non-nil, regular expression that matches Verilog-2001 typedef names.
887 For example, \"_t$\" matches typedefs named with _t, as in the C language."
888 :group
'verilog-mode-auto
890 (put 'verilog-typedef-regexp
'safe-local-variable
'stringp
)
892 (defcustom verilog-mode-hook
'verilog-set-compile-command
893 "*Hook run after Verilog mode is loaded."
895 :group
'verilog-mode
)
897 (defcustom verilog-auto-hook nil
898 "*Hook run after `verilog-mode' updates AUTOs."
899 :group
'verilog-mode-auto
902 (defcustom verilog-before-auto-hook nil
903 "*Hook run before `verilog-mode' updates AUTOs."
904 :group
'verilog-mode-auto
907 (defcustom verilog-delete-auto-hook nil
908 "*Hook run after `verilog-mode' deletes AUTOs."
909 :group
'verilog-mode-auto
912 (defcustom verilog-before-delete-auto-hook nil
913 "*Hook run before `verilog-mode' deletes AUTOs."
914 :group
'verilog-mode-auto
917 (defcustom verilog-getopt-flags-hook nil
918 "*Hook run after `verilog-getopt-flags' determines the Verilog option lists."
919 :group
'verilog-mode-auto
922 (defcustom verilog-before-getopt-flags-hook nil
923 "*Hook run before `verilog-getopt-flags' determines the Verilog option lists."
924 :group
'verilog-mode-auto
927 (defvar verilog-imenu-generic-expression
928 '((nil "^\\s-*\\(\\(m\\(odule\\|acromodule\\)\\)\\|primitive\\)\\s-+\\([a-zA-Z0-9_.:]+\\)" 4)
929 ("*Vars*" "^\\s-*\\(reg\\|wire\\)\\s-+\\(\\|\\[[^]]+\\]\\s-+\\)\\([A-Za-z0-9_]+\\)" 3))
930 "Imenu expression for Verilog mode. See `imenu-generic-expression'.")
933 ;; provide a verilog-header function.
934 ;; Customization variables:
936 (defvar verilog-date-scientific-format nil
937 "*If non-nil, dates are written in scientific format (e.g. 1997/09/17).
938 If nil, in European format (e.g. 17.09.1997). The brain-dead American
939 format (e.g. 09/17/1997) is not supported.")
941 (defvar verilog-company nil
942 "*Default name of Company for Verilog header.
943 If set will become buffer local.")
944 (make-variable-buffer-local 'verilog-company
)
946 (defvar verilog-project nil
947 "*Default name of Project for Verilog header.
948 If set will become buffer local.")
949 (make-variable-buffer-local 'verilog-project
)
951 (defvar verilog-mode-map
952 (let ((map (make-sparse-keymap)))
953 (define-key map
";" 'electric-verilog-semi
)
954 (define-key map
[(control 59)] 'electric-verilog-semi-with-comment
)
955 (define-key map
":" 'electric-verilog-colon
)
956 ;;(define-key map "=" 'electric-verilog-equal)
957 (define-key map
"\`" 'electric-verilog-tick
)
958 (define-key map
"\t" 'electric-verilog-tab
)
959 (define-key map
"\r" 'electric-verilog-terminate-line
)
960 ;; backspace/delete key bindings
961 (define-key map
[backspace] 'backward-delete-char-untabify)
962 (unless (boundp 'delete-key-deletes-forward) ; XEmacs variable
963 (define-key map [delete] 'delete-char)
964 (define-key map [(meta delete)] 'kill-word))
965 (define-key map "\M-\C-b" 'electric-verilog-backward-sexp)
966 (define-key map "\M-\C-f" 'electric-verilog-forward-sexp)
967 (define-key map "\M-\r" `electric-verilog-terminate-and-indent)
968 (define-key map "\M-\t" 'verilog-complete-word)
969 (define-key map "\M-?" 'verilog-show-completions)
970 (define-key map "\C-c\`" 'verilog-lint-off)
971 (define-key map "\C-c\*" 'verilog-delete-auto-star-implicit)
972 (define-key map "\C-c\C-r" 'verilog-label-be)
973 (define-key map "\C-c\C-i" 'verilog-pretty-declarations)
974 (define-key map "\C-c=" 'verilog-pretty-expr)
975 (define-key map "\C-c\C-b" 'verilog-submit-bug-report)
976 (define-key map "\M-*" 'verilog-star-comment)
977 (define-key map "\C-c\C-c" 'verilog-comment-region)
978 (define-key map "\C-c\C-u" 'verilog-uncomment-region)
979 (when (featurep 'xemacs)
980 (define-key map [(meta control h)] 'verilog-mark-defun)
981 (define-key map "\M-\C-a" 'verilog-beg-of-defun)
982 (define-key map "\M-\C-e" 'verilog-end-of-defun))
983 (define-key map "\C-c\C-d" 'verilog-goto-defun)
984 (define-key map "\C-c\C-k" 'verilog-delete-auto)
985 (define-key map "\C-c\C-a" 'verilog-auto)
986 (define-key map "\C-c\C-s" 'verilog-auto-save-compile)
987 (define-key map "\C-c\C-z" 'verilog-inject-auto)
988 (define-key map "\C-c\C-e" 'verilog-expand-vector)
989 (define-key map "\C-c\C-h" 'verilog-header)
991 "Keymap used in Verilog mode.")
995 verilog-menu verilog-mode-map "Menu for Verilog mode"
996 (verilog-easy-menu-filter
998 ("Choose Compilation Action"
1001 (setq verilog-tool nil)
1002 (verilog-set-compile-command))
1004 :selected (equal verilog-tool nil)
1005 :help "When invoking compilation, use compile-command"]
1008 (setq verilog-tool 'verilog-linter)
1009 (verilog-set-compile-command))
1011 :selected (equal verilog-tool `verilog-linter)
1012 :help "When invoking compilation, use lint checker"]
1015 (setq verilog-tool 'verilog-coverage)
1016 (verilog-set-compile-command))
1018 :selected (equal verilog-tool `verilog-coverage)
1019 :help "When invoking compilation, annotate for coverage"]
1022 (setq verilog-tool 'verilog-simulator)
1023 (verilog-set-compile-command))
1025 :selected (equal verilog-tool `verilog-simulator)
1026 :help "When invoking compilation, interpret Verilog source"]
1029 (setq verilog-tool 'verilog-compiler)
1030 (verilog-set-compile-command))
1032 :selected (equal verilog-tool `verilog-compiler)
1033 :help "When invoking compilation, compile Verilog source"]
1036 ["Beginning of function" verilog-beg-of-defun
1038 :help "Move backward to the beginning of the current function or procedure"]
1039 ["End of function" verilog-end-of-defun
1041 :help "Move forward to the end of the current function or procedure"]
1042 ["Mark function" verilog-mark-defun
1044 :help "Mark the current Verilog function or procedure"]
1045 ["Goto function/module" verilog-goto-defun
1046 :help "Move to specified Verilog module/task/function"]
1047 ["Move to beginning of block" electric-verilog-backward-sexp
1048 :help "Move backward over one balanced expression"]
1049 ["Move to end of block" electric-verilog-forward-sexp
1050 :help "Move forward over one balanced expression"]
1053 ["Comment Region" verilog-comment-region
1054 :help "Put marked area into a comment"]
1055 ["UnComment Region" verilog-uncomment-region
1056 :help "Uncomment an area commented with Comment Region"]
1057 ["Multi-line comment insert" verilog-star-comment
1058 :help "Insert Verilog /* */ comment at point"]
1059 ["Lint error to comment" verilog-lint-off
1060 :help "Convert a Verilog linter warning line into a disable statement"]
1064 :help "Perform compilation-action (above) on the current buffer"]
1065 ["AUTO, Save, Compile" verilog-auto-save-compile
1066 :help "Recompute AUTOs, save buffer, and compile"]
1067 ["Next Compile Error" next-error
1068 :help "Visit next compilation error message and corresponding source code"]
1069 ["Ignore Lint Warning at point" verilog-lint-off
1070 :help "Convert a Verilog linter warning line into a disable statement"]
1072 ["Line up declarations around point" verilog-pretty-declarations
1073 :help "Line up declarations around point"]
1074 ["Line up equations around point" verilog-pretty-expr
1075 :help "Line up expressions around point"]
1076 ["Redo/insert comments on every end" verilog-label-be
1077 :help "Label matching begin ... end statements"]
1078 ["Expand [x:y] vector line" verilog-expand-vector
1079 :help "Take a signal vector on the current line and expand it to multiple lines"]
1080 ["Insert begin-end block" verilog-insert-block
1081 :help "Insert begin ... end"]
1082 ["Complete word" verilog-complete-word
1083 :help "Complete word at point"]
1085 ["Recompute AUTOs" verilog-auto
1086 :help "Expand AUTO meta-comment statements"]
1087 ["Kill AUTOs" verilog-delete-auto
1088 :help "Remove AUTO expansions"]
1089 ["Inject AUTOs" verilog-inject-auto
1090 :help "Inject AUTOs into legacy non-AUTO buffer"]
1092 ["AUTO General" (describe-function 'verilog-auto)
1093 :help "Help introduction on AUTOs"]
1094 ["AUTO Library Flags" (describe-variable 'verilog-library-flags)
1095 :help "Help on verilog-library-flags"]
1096 ["AUTO Library Path" (describe-variable 'verilog-library-directories)
1097 :help "Help on verilog-library-directories"]
1098 ["AUTO Library Files" (describe-variable 'verilog-library-files)
1099 :help "Help on verilog-library-files"]
1100 ["AUTO Library Extensions" (describe-variable 'verilog-library-extensions)
1101 :help "Help on verilog-library-extensions"]
1102 ["AUTO `define Reading" (describe-function 'verilog-read-defines)
1103 :help "Help on reading `defines"]
1104 ["AUTO `include Reading" (describe-function 'verilog-read-includes)
1105 :help "Help on parsing `includes"]
1106 ["AUTOARG" (describe-function 'verilog-auto-arg)
1107 :help "Help on AUTOARG - declaring module port list"]
1108 ["AUTOASCIIENUM" (describe-function 'verilog-auto-ascii-enum)
1109 :help "Help on AUTOASCIIENUM - creating ASCII for enumerations"]
1110 ["AUTOINOUTMODULE" (describe-function 'verilog-auto-inout-module)
1111 :help "Help on AUTOINOUTMODULE - copying i/o from another file"]
1112 ["AUTOINOUT" (describe-function 'verilog-auto-inout)
1113 :help "Help on AUTOINOUT - adding inouts from cells"]
1114 ["AUTOINPUT" (describe-function 'verilog-auto-input)
1115 :help "Help on AUTOINPUT - adding inputs from cells"]
1116 ["AUTOINST" (describe-function 'verilog-auto-inst)
1117 :help "Help on AUTOINST - adding pins for cells"]
1118 ["AUTOINST (.*)" (describe-function 'verilog-auto-star)
1119 :help "Help on expanding Verilog-2001 .* pins"]
1120 ["AUTOINSTPARAM" (describe-function 'verilog-auto-inst-param)
1121 :help "Help on AUTOINSTPARAM - adding parameter pins to cells"]
1122 ["AUTOOUTPUT" (describe-function 'verilog-auto-output)
1123 :help "Help on AUTOOUTPUT - adding outputs from cells"]
1124 ["AUTOOUTPUTEVERY" (describe-function 'verilog-auto-output-every)
1125 :help "Help on AUTOOUTPUTEVERY - adding outputs of all signals"]
1126 ["AUTOREG" (describe-function 'verilog-auto-reg)
1127 :help "Help on AUTOREG - declaring registers for non-wires"]
1128 ["AUTOREGINPUT" (describe-function 'verilog-auto-reg-input)
1129 :help "Help on AUTOREGINPUT - declaring inputs for non-wires"]
1130 ["AUTORESET" (describe-function 'verilog-auto-reset)
1131 :help "Help on AUTORESET - resetting always blocks"]
1132 ["AUTOSENSE" (describe-function 'verilog-auto-sense)
1133 :help "Help on AUTOSENSE - sensitivity lists for always blocks"]
1134 ["AUTOTIEOFF" (describe-function 'verilog-auto-tieoff)
1135 :help "Help on AUTOTIEOFF - tieing off unused outputs"]
1136 ["AUTOUNUSED" (describe-function 'verilog-auto-unused)
1137 :help "Help on AUTOUNUSED - terminating unused inputs"]
1138 ["AUTOWIRE" (describe-function 'verilog-auto-wire)
1139 :help "Help on AUTOWIRE - declaring wires for cells"]
1142 ["Submit bug report" verilog-submit-bug-report
1143 :help "Submit via mail a bug report on verilog-mode.el"]
1144 ["Version and FAQ" verilog-faq
1145 :help "Show the current version, and where to get the FAQ etc"]
1146 ["Customize Verilog Mode..." verilog-customize
1147 :help "Customize variables and other settings used by Verilog-Mode"]
1148 ["Customize Verilog Fonts & Colors" verilog-font-customize
1149 :help "Customize fonts used by Verilog-Mode."])))
1152 verilog-stmt-menu verilog-mode-map "Menu for statement templates in Verilog."
1153 (verilog-easy-menu-filter
1155 ["Header" verilog-sk-header
1156 :help "Insert a header block at the top of file"]
1157 ["Comment" verilog-sk-comment
1158 :help "Insert a comment block"]
1160 ["Module" verilog-sk-module
1161 :help "Insert a module .. (/*AUTOARG*/);.. endmodule block"]
1162 ["Primitive" verilog-sk-primitive
1163 :help "Insert a primitive .. (.. );.. endprimitive block"]
1165 ["Input" verilog-sk-input
1166 :help "Insert an input declaration"]
1167 ["Output" verilog-sk-output
1168 :help "Insert an output declaration"]
1169 ["Inout" verilog-sk-inout
1170 :help "Insert an inout declaration"]
1171 ["Wire" verilog-sk-wire
1172 :help "Insert a wire declaration"]
1173 ["Reg" verilog-sk-reg
1174 :help "Insert a register declaration"]
1175 ["Define thing under point as a register" verilog-sk-define-signal
1176 :help "Define signal under point as a register at the top of the module"]
1178 ["Initial" verilog-sk-initial
1179 :help "Insert an initial begin .. end block"]
1180 ["Always" verilog-sk-always
1181 :help "Insert an always @(AS) begin .. end block"]
1182 ["Function" verilog-sk-function
1183 :help "Insert a function .. begin .. end endfunction block"]
1184 ["Task" verilog-sk-task
1185 :help "Insert a task .. begin .. end endtask block"]
1186 ["Specify" verilog-sk-specify
1187 :help "Insert a specify .. endspecify block"]
1188 ["Generate" verilog-sk-generate
1189 :help "Insert a generate .. endgenerate block"]
1191 ["Begin" verilog-sk-begin
1192 :help "Insert a begin .. end block"]
1194 :help "Insert an if (..) begin .. end block"]
1195 ["(if) else" verilog-sk-else-if
1196 :help "Insert an else if (..) begin .. end block"]
1197 ["For" verilog-sk-for
1198 :help "Insert a for (...) begin .. end block"]
1199 ["While" verilog-sk-while
1200 :help "Insert a while (...) begin .. end block"]
1201 ["Fork" verilog-sk-fork
1202 :help "Insert a fork begin .. end .. join block"]
1203 ["Repeat" verilog-sk-repeat
1204 :help "Insert a repeat (..) begin .. end block"]
1205 ["Case" verilog-sk-case
1206 :help "Insert a case block, prompting for details"]
1207 ["Casex" verilog-sk-casex
1208 :help "Insert a casex (...) item: begin.. end endcase block"]
1209 ["Casez" verilog-sk-casez
1210 :help "Insert a casez (...) item: begin.. end endcase block"])))
1212 (defvar verilog-mode-abbrev-table nil
1213 "Abbrev table in use in Verilog-mode buffers.")
1215 (define-abbrev-table 'verilog-mode-abbrev-table ())
1221 (defsubst verilog-string-replace-matches (from-string to-string fixedcase literal string)
1222 "Replace occurrences of FROM-STRING with TO-STRING.
1223 FIXEDCASE and LITERAL as in `replace-match`. STRING is what to replace.
1224 The case (verilog-string-replace-matches \"o\" \"oo\" nil nil \"foobar\")
1225 will break, as the o's continuously replace. xa -> x works ok though."
1226 ;; Hopefully soon to a emacs built-in
1228 (while (string-match from-string string start)
1229 (setq string (replace-match to-string fixedcase literal string)
1230 start (min (length string) (match-end 0))))
1233 (defsubst verilog-string-remove-spaces (string)
1234 "Remove spaces surrounding STRING."
1236 (setq string (verilog-string-replace-matches "^\\s-+" "" nil nil string))
1237 (setq string (verilog-string-replace-matches "\\s-+$" "" nil nil string))
1240 (defsubst verilog-re-search-forward (REGEXP BOUND NOERROR)
1241 ; checkdoc-params: (REGEXP BOUND NOERROR)
1242 "Like `re-search-forward', but skips over match in comments or strings."
1243 (store-match-data '(nil nil)) ;; So match-end will return nil if no matches found
1245 (re-search-forward REGEXP BOUND NOERROR)
1246 (and (verilog-skip-forward-comment-or-string)
1248 (store-match-data '(nil nil))
1254 (defsubst verilog-re-search-backward (REGEXP BOUND NOERROR)
1255 ; checkdoc-params: (REGEXP BOUND NOERROR)
1256 "Like `re-search-backward', but skips over match in comments or strings."
1257 (store-match-data '(nil nil)) ;; So match-end will return nil if no matches found
1259 (re-search-backward REGEXP BOUND NOERROR)
1260 (and (verilog-skip-backward-comment-or-string)
1262 (store-match-data '(nil nil))
1268 (defsubst verilog-re-search-forward-quick (regexp bound noerror)
1269 "Like `verilog-re-search-forward', including use of REGEXP BOUND and NOERROR,
1270 but trashes match data and is faster for REGEXP that doesn't match often.
1271 This may at some point use text properties to ignore comments,
1272 so there may be a large up front penalty for the first search."
1274 (while (and (not pt)
1275 (re-search-forward regexp bound noerror))
1276 (if (not (verilog-inside-comment-p))
1277 (setq pt (match-end 0))))
1280 (defsubst verilog-re-search-backward-quick (regexp bound noerror)
1281 ; checkdoc-params: (REGEXP BOUND NOERROR)
1282 "Like `verilog-re-search-backward', including use of REGEXP BOUND and NOERROR,
1283 but trashes match data and is faster for REGEXP that doesn't match often.
1284 This may at some point use text properties to ignore comments,
1285 so there may be a large up front penalty for the first search."
1287 (while (and (not pt)
1288 (re-search-backward regexp bound noerror))
1289 (if (not (verilog-inside-comment-p))
1290 (setq pt (match-end 0))))
1293 (defsubst verilog-get-beg-of-line (&optional arg)
1295 (beginning-of-line arg)
1298 (defsubst verilog-get-end-of-line (&optional arg)
1303 (defsubst verilog-within-string ()
1305 (nth 3 (parse-partial-sexp (verilog-get-beg-of-line) (point)))))
1307 (defvar compile-command)
1309 ;; compilation program
1310 (defun verilog-set-compile-command ()
1311 "Function to compute shell command to compile Verilog.
1313 This reads `verilog-tool' and sets `compile-command'. This specifies the
1314 program that executes when you type \\[compile] or
1315 \\[verilog-auto-save-compile].
1317 By default `verilog-tool' uses a Makefile if one exists in the current
1318 directory. If not, it is set to the `verilog-linter', `verilog-coverage',
1319 `verilog-simulator', or `verilog-compiler' variables, as selected with the
1320 Verilog -> \"Choose Compilation Action\" menu.
1322 You should set `verilog-tool' or the other variables to the path and
1323 arguments for your Verilog simulator. For example:
1326 \"(cd /tmp; surecov %s)\".
1328 In the former case, the path to the current buffer is concat'ed to the
1329 value of `verilog-tool'; in the later, the path to the current buffer is
1330 substituted for the %s.
1332 Where __FILE__ appears in the string, the `buffer-file-name' of the
1333 current buffer, without the directory portion, will be substituted."
1336 ((or (file-exists-p "makefile") ;If there is a makefile, use it
1337 (file-exists-p "Makefile"))
1338 (make-local-variable 'compile-command)
1339 (setq compile-command "make "))
1341 (make-local-variable 'compile-command)
1342 (setq compile-command
1344 (if (string-match "%s" (eval verilog-tool))
1345 (format (eval verilog-tool) (or buffer-file-name ""))
1346 (concat (eval verilog-tool) " " (or buffer-file-name "")))
1348 (verilog-modify-compile-command))
1350 (defun verilog-modify-compile-command ()
1351 "Replace meta-information in `compile-command'.
1352 Where __FILE__ appears in the string, the current buffer's file-name,
1353 without the directory portion, will be substituted."
1355 (stringp compile-command)
1356 (string-match "\\b__FILE__\\b" compile-command))
1357 (make-local-variable 'compile-command)
1358 (setq compile-command
1359 (verilog-string-replace-matches
1360 "\\b__FILE__\\b" (file-name-nondirectory (buffer-file-name))
1361 t t compile-command))))
1363 ;; Following code only gets called from compilation-mode-hook.
1364 (defvar compilation-error-regexp-alist)
1366 (defun verilog-error-regexp-add ()
1367 "Add the messages to the `compilation-error-regexp-alist'.
1368 Called by `compilation-mode-hook'. This allows \\[next-error] to
1370 (if (not verilog-error-regexp-add-didit)
1372 (setq verilog-error-regexp-add-didit t)
1373 (setq-default compilation-error-regexp-alist
1374 (append verilog-error-regexp
1375 (default-value 'compilation-error-regexp-alist)))
1376 ;; Could be buffer local at this point; maybe also in let; change all three
1377 (setq compilation-error-regexp-alist
1378 (default-value 'compilation-error-regexp-alist))
1379 (set (make-local-variable 'compilation-error-regexp-alist)
1380 (default-value 'compilation-error-regexp-alist)))))
1382 (add-hook 'compilation-mode-hook 'verilog-error-regexp-add)
1384 (defconst verilog-directive-re
1385 ;; "`case" "`default" "`define" "`define" "`else" "`endfor" "`endif"
1386 ;; "`endprotect" "`endswitch" "`endwhile" "`for" "`format" "`if" "`ifdef"
1387 ;; "`ifndef" "`include" "`let" "`protect" "`switch" "`timescale"
1388 ;; "`time_scale" "`undef" "`while"
1389 "\\<`\\(case\\|def\\(ault\\|ine\\(\\)?\\)\\|e\\(lse\\|nd\\(for\\|if\\|protect\\|switch\\|while\\)\\)\\|for\\(mat\\)?\\|i\\(f\\(def\\|ndef\\)?\\|nclude\\)\\|let\\|protect\\|switch\\|time\\(_scale\\|scale\\)\\|undef\\|while\\)\\>")
1391 (defconst verilog-directive-begin
1392 "\\<`\\(for\\|i\\(f\\|fdef\\|fndef\\)\\|switch\\|while\\)\\>")
1394 (defconst verilog-directive-middle
1395 "\\<`\\(else\\|default\\|case\\)\\>")
1397 (defconst verilog-directive-end
1398 "`\\(endfor\\|endif\\|endswitch\\|endwhile\\)\\>")
1400 (defconst verilog-directive-re-1
1401 (concat "[ \t]*" verilog-directive-re))
1404 ;; Regular expressions used to calculate indent, etc.
1406 (defconst verilog-symbol-re "\\<[a-zA-Z_][a-zA-Z_0-9.]*\\>")
1407 (defconst verilog-case-re "\\(\\<case[xz]?\\>\\|\\<randcase\\>\\)")
1415 (defconst verilog-no-indent-begin-re
1416 "\\<\\(if\\|else\\|while\\|for\\|repeat\\|always\\|always_comb\\|always_ff\\|always_latch\\)\\>")
1418 (defconst verilog-ends-re
1419 ;; Parenthesis indicate type of keyword found
1421 "\\(\\<else\\>\\)\\|" ; 1
1422 "\\(\\<if\\>\\)\\|" ; 2
1423 "\\(\\<end\\>\\)\\|" ; 3
1424 "\\(\\<endcase\\>\\)\\|" ; 4
1425 "\\(\\<endfunction\\>\\)\\|" ; 5
1426 "\\(\\<endtask\\>\\)\\|" ; 6
1427 "\\(\\<endspecify\\>\\)\\|" ; 7
1428 "\\(\\<endtable\\>\\)\\|" ; 8
1429 "\\(\\<endgenerate\\>\\)\\|" ; 9
1430 "\\(\\<join\\(_any\\|_none\\)?\\>\\)\\|" ; 10
1431 "\\(\\<endclass\\>\\)\\|" ; 11
1432 "\\(\\<endgroup\\>\\)" ; 12
1435 (defconst verilog-auto-end-comment-lines-re
1436 ;; Matches to names in this list cause auto-end-commentation
1438 verilog-directive-re "\\)\\|\\("
1440 (verilog-regexp-words
1468 ;;; NOTE: verilog-leap-to-head expects that verilog-end-block-re and
1469 ;;; verilog-end-block-ordered-re matches exactly the same strings.
1470 (defconst verilog-end-block-ordered-re
1471 ;; Parenthesis indicate type of keyword found
1472 (concat "\\(\\<endcase\\>\\)\\|" ; 1
1473 "\\(\\<end\\>\\)\\|" ; 2
1474 "\\(\\<end" ; 3, but not used
1475 "\\(" ; 4, but not used
1476 "\\(function\\)\\|" ; 5
1478 "\\(module\\)\\|" ; 7
1479 "\\(primitive\\)\\|" ; 8
1480 "\\(interface\\)\\|" ; 9
1481 "\\(package\\)\\|" ; 10
1482 "\\(class\\)\\|" ; 11
1483 "\\(group\\)\\|" ; 12
1484 "\\(program\\)\\|" ; 13
1485 "\\(sequence\\)\\|" ; 14
1486 "\\(clocking\\)\\|" ; 15
1488 (defconst verilog-end-block-re
1490 (verilog-regexp-words
1492 `("end" ;; closes begin
1493 "endcase" ;; closes any of case, casex casez or randcase
1494 "join" "join_any" "join_none" ;; closes fork
1511 (defconst verilog-endcomment-reason-re
1512 ;; Parenthesis indicate type of keyword found
1514 "\\(\\<fork\\>\\)\\|"
1515 "\\(\\<begin\\>\\)\\|"
1517 "\\(\\<clocking\\>\\)\\|"
1518 "\\(\\<else\\>\\)\\|"
1519 "\\(\\<end\\>.*\\<else\\>\\)\\|"
1520 "\\(\\<task\\>\\)\\|"
1521 "\\(\\<function\\>\\)\\|"
1522 "\\(\\<initial\\>\\)\\|"
1523 "\\(\\<interface\\>\\)\\|"
1524 "\\(\\<package\\>\\)\\|"
1525 "\\(\\<final\\>\\)\\|"
1526 "\\(\\<always\\>\\(\[ \t\]*@\\)?\\)\\|"
1527 "\\(\\<always_comb\\>\\(\[ \t\]*@\\)?\\)\\|"
1528 "\\(\\<always_ff\\>\\(\[ \t\]*@\\)?\\)\\|"
1529 "\\(\\<always_latch\\>\\(\[ \t\]*@\\)?\\)\\|"
1531 "\\(\\<while\\>\\)\\|"
1532 "\\(\\<for\\(ever\\|each\\)?\\>\\)\\|"
1533 "\\(\\<repeat\\>\\)\\|\\(\\<wait\\>\\)\\|"
1536 (defconst verilog-named-block-re "begin[ \t]*:")
1538 ;; These words begin a block which can occur inside a module which should be indented,
1539 ;; and closed with the respective word from the end-block list
1541 (defconst verilog-beg-block-re
1543 (verilog-regexp-words
1545 "case" "casex" "casez" "randcase"
1555 ;; These are the same words, in a specific order in the regular
1556 ;; expression so that matching will work nicely for
1557 ;; verilog-forward-sexp and verilog-calc-indent
1559 (defconst verilog-beg-block-re-ordered
1562 "\\|\\(randcase\\|\\(unique\\s-+\\|priority\\s-+\\)?case[xz]?\\)" ; 2,3
1563 "\\|\\(\\(disable\\s-+\\)?fork\\)" ;4
1566 "\\|\\(specify\\)" ;7
1567 "\\|\\(function\\)" ;8
1569 "\\|\\(generate\\)" ;10
1570 "\\|\\(covergroup\\)" ;11
1571 "\\|\\(property\\)" ;12
1572 "\\|\\(\\(rand\\)?sequence\\)" ;13
1573 "\\|\\(clocking\\)" ;14
1576 (defconst verilog-end-block-ordered-rry
1577 [ "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<endcase\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)"
1578 "\\(\\<randcase\\>\\|\\<case[xz]?\\>\\)\\|\\(\\<endcase\\>\\)"
1579 "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)"
1580 "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)"
1581 "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)"
1582 "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)"
1583 "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)"
1584 "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)"
1585 "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)"
1586 "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)"
1587 "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)"
1588 "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)"
1589 "\\(\\<clocking\\>\\)\\|\\(\\<endclocking\\>\\)"
1592 (defconst verilog-nameable-item-re
1594 (verilog-regexp-words
1597 "join" "join_any" "join_none"
1614 (defconst verilog-declaration-opener
1616 (verilog-regexp-words
1617 `("module" "begin" "task" "function"))))
1619 (defconst verilog-declaration-prefix-re
1621 (verilog-regexp-words
1624 "inout" "input" "output" "ref"
1626 "const" "static" "protected" "local"
1628 "localparam" "parameter" "var"
1632 (defconst verilog-declaration-core-re
1634 (verilog-regexp-words
1636 ;; port direction (by themselves)
1637 "inout" "input" "output"
1638 ;; integer_atom_type
1639 "byte" "shortint" "int" "longint" "integer" "time"
1640 ;; integer_vector_type
1643 "shortreal" "real" "realtime"
1645 "supply0" "supply1" "tri" "triand" "trior" "trireg" "tri0" "tri1" "uwire" "wire" "wand" "wor"
1647 "string" "event" "chandle" "virtual" "enum" "genvar"
1650 "mailbox" "semaphore"
1652 (defconst verilog-declaration-re
1653 (concat "\\(" verilog-declaration-prefix-re "\\s-*\\)?" verilog-declaration-core-re))
1654 (defconst verilog-range-re "\\(\\[[^]]*\\]\\s-*\\)+")
1655 (defconst verilog-optional-signed-re "\\s-*\\(signed\\)?")
1656 (defconst verilog-optional-signed-range-re
1658 "\\s-*\\(\\<\\(reg\\|wire\\)\\>\\s-*\\)?\\(\\<signed\\>\\s-*\\)?\\(" verilog-range-re "\\)?"))
1659 (defconst verilog-macroexp-re "`\\sw+")
1661 (defconst verilog-delay-re "#\\s-*\\(\\([0-9_]+\\('s?[hdxbo][0-9a-fA-F_xz]+\\)?\\)\\|\\(([^()]*)\\)\\|\\(\\sw+\\)\\)")
1662 (defconst verilog-declaration-re-2-no-macro
1663 (concat "\\s-*" verilog-declaration-re
1664 "\\s-*\\(\\(" verilog-optional-signed-range-re "\\)\\|\\(" verilog-delay-re "\\)"
1666 (defconst verilog-declaration-re-2-macro
1667 (concat "\\s-*" verilog-declaration-re
1668 "\\s-*\\(\\(" verilog-optional-signed-range-re "\\)\\|\\(" verilog-delay-re "\\)"
1669 "\\|\\(" verilog-macroexp-re "\\)"
1671 (defconst verilog-declaration-re-1-macro
1672 (concat "^" verilog-declaration-re-2-macro))
1674 (defconst verilog-declaration-re-1-no-macro (concat "^" verilog-declaration-re-2-no-macro))
1676 (defconst verilog-defun-re
1677 (eval-when-compile (verilog-regexp-words `("macromodule" "module" "class" "program" "interface" "package" "primitive" "config"))))
1678 (defconst verilog-end-defun-re
1679 (eval-when-compile (verilog-regexp-words `("endmodule" "endclass" "endprogram" "endinterface" "endpackage" "endprimitive" "endconfig"))))
1680 (defconst verilog-zero-indent-re
1681 (concat verilog-defun-re "\\|" verilog-end-defun-re))
1683 (defconst verilog-behavioral-block-beg-re
1684 (eval-when-compile (verilog-regexp-words `("initial" "final" "always" "always_comb" "always_latch" "always_ff"
1685 "function" "task"))))
1687 (defconst verilog-indent-re
1689 (verilog-regexp-words
1692 "always" "always_latch" "always_ff" "always_comb"
1694 ; "unique" "priority"
1695 "case" "casex" "casez" "randcase" "endcase"
1697 "clocking" "endclocking"
1698 "config" "endconfig"
1699 "covergroup" "endgroup"
1700 "fork" "join" "join_any" "join_none"
1701 "function" "endfunction"
1703 "generate" "endgenerate"
1705 "interface" "endinterface"
1706 "module" "macromodule" "endmodule"
1707 "package" "endpackage"
1708 "primitive" "endprimative"
1709 "program" "endprogram"
1710 "property" "endproperty"
1711 "sequence" "randsequence" "endsequence"
1712 "specify" "endspecify"
1718 "`if" "`ifdef" "`ifndef" "`else" "`endif"
1719 "`while" "`endwhile"
1724 "`protect" "`endprotect"
1725 "`switch" "`endswitch"
1730 (defconst verilog-defun-level-re
1732 (verilog-regexp-words
1734 "module" "macromodule" "primitive" "class" "program" "initial" "final" "always" "always_comb"
1735 "always_ff" "always_latch" "endtask" "endfunction" "interface" "package"
1738 (defconst verilog-defun-level-not-generate-re
1740 (verilog-regexp-words
1742 "module" "macromodule" "primitive" "class" "program" "interface" "package" "config"))))
1744 (defconst verilog-cpp-level-re
1746 (verilog-regexp-words
1748 "endmodule" "endprimitive" "endinterface" "endpackage" "endprogram" "endclass"
1750 (defconst verilog-disable-fork-re "disable\\s-+fork")
1751 (defconst verilog-extended-case-re "\\(unique\\s-+\\|priority\\s-+\\)?case[xz]?")
1752 (defconst verilog-extended-complete-re
1753 (concat "\\(\\<extern\\s-+\\|\\<virtual\\s-+\\|\\<protected\\s-+\\)*\\(\\<function\\>\\|\\<task\\>\\)"
1754 "\\|\\(\\<typedef\\>\\s-+\\)*\\(\\<struct\\>\\|\\<union\\>\\|\\<class\\>\\)"
1755 "\\|" verilog-extended-case-re ))
1756 (defconst verilog-basic-complete-re
1758 (verilog-regexp-words
1760 "always" "assign" "always_latch" "always_ff" "always_comb" "constraint"
1761 "import" "initial" "final" "module" "macromodule" "repeat" "randcase" "while"
1762 "if" "for" "forever" "foreach" "else" "parameter" "do"
1764 (defconst verilog-complete-reg
1766 verilog-extended-complete-re
1768 verilog-basic-complete-re))
1770 (defconst verilog-end-statement-re
1771 (concat "\\(" verilog-beg-block-re "\\)\\|\\("
1772 verilog-end-block-re "\\)"))
1774 (defconst verilog-endcase-re
1775 (concat verilog-case-re "\\|"
1780 (defconst verilog-exclude-str-start "/* -----\\/----- EXCLUDED -----\\/-----"
1781 "String used to mark beginning of excluded text.")
1782 (defconst verilog-exclude-str-end " -----/\\----- EXCLUDED -----/\\----- */"
1783 "String used to mark end of excluded text.")
1784 (defconst verilog-preprocessor-re
1786 (verilog-regexp-words
1788 "`define" "`include" "`ifdef" "`ifndef" "`if" "`endif" "`else"
1791 (defconst verilog-keywords
1792 '( "`case" "`default" "`define" "`else" "`endfor" "`endif"
1793 "`endprotect" "`endswitch" "`endwhile" "`for" "`format" "`if" "`ifdef"
1794 "`ifndef" "`include" "`let" "`protect" "`switch" "`timescale"
1795 "`time_scale" "`undef" "`while"
1797 "after" "alias" "always" "always_comb" "always_ff" "always_latch" "and"
1798 "assert" "assign" "assume" "automatic" "before" "begin" "bind"
1799 "bins" "binsof" "bit" "break" "buf" "bufif0" "bufif1" "byte"
1800 "case" "casex" "casez" "cell" "chandle" "class" "clocking" "cmos"
1801 "config" "const" "constraint" "context" "continue" "cover"
1802 "covergroup" "coverpoint" "cross" "deassign" "default" "defparam"
1803 "design" "disable" "dist" "do" "edge" "else" "end" "endcase"
1804 "endclass" "endclocking" "endconfig" "endfunction" "endgenerate"
1805 "endgroup" "endinterface" "endmodule" "endpackage" "endprimitive"
1806 "endprogram" "endproperty" "endspecify" "endsequence" "endtable"
1807 "endtask" "enum" "event" "expect" "export" "extends" "extern"
1808 "final" "first_match" "for" "force" "foreach" "forever" "fork"
1809 "forkjoin" "function" "generate" "genvar" "highz0" "highz1" "if"
1810 "iff" "ifnone" "ignore_bins" "illegal_bins" "import" "incdir"
1811 "include" "initial" "inout" "input" "inside" "instance" "int"
1812 "integer" "interface" "intersect" "join" "join_any" "join_none"
1813 "large" "liblist" "library" "local" "localparam" "logic"
1814 "longint" "macromodule" "mailbox" "matches" "medium" "modport" "module"
1815 "nand" "negedge" "new" "nmos" "nor" "noshowcancelled" "not"
1816 "notif0" "notif1" "null" "or" "output" "package" "packed"
1817 "parameter" "pmos" "posedge" "primitive" "priority" "program"
1818 "property" "protected" "pull0" "pull1" "pulldown" "pullup"
1819 "pulsestyle_onevent" "pulsestyle_ondetect" "pure" "rand" "randc"
1820 "randcase" "randsequence" "rcmos" "real" "realtime" "ref" "reg"
1821 "release" "repeat" "return" "rnmos" "rpmos" "rtran" "rtranif0"
1822 "rtranif1" "scalared" "semaphore" "sequence" "shortint" "shortreal"
1823 "showcancelled" "signed" "small" "solve" "specify" "specparam"
1824 "static" "string" "strong0" "strong1" "struct" "super" "supply0"
1825 "supply1" "table" "tagged" "task" "this" "throughout" "time"
1826 "timeprecision" "timeunit" "tran" "tranif0" "tranif1" "tri"
1827 "tri0" "tri1" "triand" "trior" "trireg" "type" "typedef" "union"
1828 "unique" "unsigned" "use" "uwire" "var" "vectored" "virtual" "void"
1829 "wait" "wait_order" "wand" "weak0" "weak1" "while" "wildcard"
1830 "wire" "with" "within" "wor" "xnor" "xor"
1832 "List of Verilog keywords.")
1834 (defconst verilog-comment-start-regexp "//\\|/\\*"
1835 "Dual comment value for `comment-start-regexp'.")
1837 (defvar verilog-mode-syntax-table
1838 (let ((table (make-syntax-table)))
1839 ;; Populate the syntax TABLE.
1840 (modify-syntax-entry ?\\ "\\" table)
1841 (modify-syntax-entry ?+ "." table)
1842 (modify-syntax-entry ?- "." table)
1843 (modify-syntax-entry ?= "." table)
1844 (modify-syntax-entry ?% "." table)
1845 (modify-syntax-entry ?< "." table)
1846 (modify-syntax-entry ?> "." table)
1847 (modify-syntax-entry ?& "." table)
1848 (modify-syntax-entry ?| "." table)
1849 (modify-syntax-entry ?` "w" table)
1850 (modify-syntax-entry ?_ "w" table)
1851 (modify-syntax-entry ?\' "." table)
1853 ;; Set up TABLE to handle block and line style comments.
1854 (if (featurep 'xemacs)
1856 ;; XEmacs (formerly Lucid) has the best implementation
1857 (modify-syntax-entry ?/ ". 1456" table)
1858 (modify-syntax-entry ?* ". 23" table)
1859 (modify-syntax-entry ?\n "> b" table))
1860 ;; Emacs does things differently, but we can work with it
1861 (modify-syntax-entry ?/ ". 124b" table)
1862 (modify-syntax-entry ?* ". 23" table)
1863 (modify-syntax-entry ?\n "> b" table))
1865 "Syntax table used in Verilog mode buffers.")
1867 (defvar verilog-font-lock-keywords nil
1868 "Default highlighting for Verilog mode.")
1870 (defvar verilog-font-lock-keywords-1 nil
1871 "Subdued level highlighting for Verilog mode.")
1873 (defvar verilog-font-lock-keywords-2 nil
1874 "Medium level highlighting for Verilog mode.
1875 See also `verilog-font-lock-extra-types'.")
1877 (defvar verilog-font-lock-keywords-3 nil
1878 "Gaudy level highlighting for Verilog mode.
1879 See also `verilog-font-lock-extra-types'.")
1880 (defvar verilog-font-lock-translate-off-face
1881 'verilog-font-lock-translate-off-face
1882 "Font to use for translated off regions.")
1883 (defface verilog-font-lock-translate-off-face
1886 (:background "gray90" :italic t ))
1889 (:background "gray10" :italic t ))
1890 (((class grayscale) (background light))
1891 (:foreground "DimGray" :italic t))
1892 (((class grayscale) (background dark))
1893 (:foreground "LightGray" :italic t))
1895 "Font lock mode face used to background highlight translate-off regions."
1896 :group 'font-lock-highlighting-faces)
1898 (defvar verilog-font-lock-p1800-face
1899 'verilog-font-lock-p1800-face
1900 "Font to use for p1800 keywords.")
1901 (defface verilog-font-lock-p1800-face
1904 (:foreground "DarkOrange3" :bold t ))
1907 (:foreground "orange1" :bold t ))
1909 "Font lock mode face used to highlight P1800 keywords."
1910 :group 'font-lock-highlighting-faces)
1912 (defvar verilog-font-lock-ams-face
1913 'verilog-font-lock-ams-face
1914 "Font to use for Analog/Mixed Signal keywords.")
1915 (defface verilog-font-lock-ams-face
1918 (:foreground "Purple" :bold t ))
1921 (:foreground "orange1" :bold t ))
1923 "Font lock mode face used to highlight AMS keywords."
1924 :group 'font-lock-highlighting-faces)
1926 (defvar verilog-font-grouping-keywords-face
1927 'verilog-font-lock-grouping-keywords-face
1928 "Font to use for Verilog Grouping Keywords (such as begin..end).")
1929 (defface verilog-font-lock-grouping-keywords-face
1932 (:foreground "red4" :bold t ))
1935 (:foreground "red4" :bold t ))
1937 "Font lock mode face used to highlight verilog grouping keywords."
1938 :group 'font-lock-highlighting-faces)
1940 (let* ((verilog-type-font-keywords
1944 "and" "bit" "buf" "bufif0" "bufif1" "cmos" "defparam"
1945 "event" "genvar" "inout" "input" "integer" "localparam"
1946 "logic" "mailbox" "nand" "nmos" "not" "notif0" "notif1" "or"
1947 "output" "parameter" "pmos" "pull0" "pull1" "pullup"
1948 "rcmos" "real" "realtime" "reg" "rnmos" "rpmos" "rtran"
1949 "rtranif0" "rtranif1" "semaphore" "signed" "struct" "supply"
1950 "supply0" "supply1" "time" "tran" "tranif0" "tranif1"
1951 "tri" "tri0" "tri1" "triand" "trior" "trireg" "typedef"
1952 "uwire" "vectored" "wand" "wire" "wor" "xnor" "xor"
1955 (verilog-pragma-keywords
1958 '("surefire" "synopsys" "rtl_synthesis" "verilint" ) nil
1961 (verilog-p1800-keywords
1964 '("alias" "assert" "assume" "automatic" "before" "bind"
1965 "bins" "binsof" "break" "byte" "cell" "chandle" "class"
1966 "clocking" "config" "const" "constraint" "context" "continue"
1967 "cover" "covergroup" "coverpoint" "cross" "deassign" "design"
1968 "dist" "do" "edge" "endclass" "endclocking" "endconfig"
1969 "endgroup" "endprogram" "endproperty" "endsequence" "enum"
1970 "expect" "export" "extends" "extern" "first_match" "foreach"
1971 "forkjoin" "genvar" "highz0" "highz1" "ifnone" "ignore_bins"
1972 "illegal_bins" "import" "incdir" "include" "inside" "instance"
1973 "int" "intersect" "large" "liblist" "library" "local" "longint"
1974 "matches" "medium" "modport" "new" "noshowcancelled" "null"
1975 "packed" "program" "property" "protected" "pull0" "pull1"
1976 "pulsestyle_onevent" "pulsestyle_ondetect" "pure" "rand" "randc"
1977 "randcase" "randsequence" "ref" "release" "return" "scalared"
1978 "sequence" "shortint" "shortreal" "showcancelled" "small" "solve"
1979 "specparam" "static" "string" "strong0" "strong1" "struct"
1980 "super" "tagged" "this" "throughout" "timeprecision" "timeunit"
1981 "type" "union" "unsigned" "use" "var" "virtual" "void"
1982 "wait_order" "weak0" "weak1" "wildcard" "with" "within"
1985 (verilog-ams-keywords
1988 '("above" "abs" "absdelay" "acos" "acosh" "ac_stim"
1989 "aliasparam" "analog" "analysis" "asin" "asinh" "atan" "atan2" "atanh"
1990 "branch" "ceil" "connectmodule" "connectrules" "cos" "cosh" "ddt"
1991 "ddx" "discipline" "driver_update" "enddiscipline" "endconnectrules"
1992 "endnature" "endparamset" "exclude" "exp" "final_step" "flicker_noise"
1993 "floor" "flow" "from" "ground" "hypot" "idt" "idtmod" "inf"
1994 "initial_step" "laplace_nd" "laplace_np" "laplace_zd" "laplace_zp"
1995 "last_crossing" "limexp" "ln" "log" "max" "min" "nature"
1996 "net_resolution" "noise_table" "paramset" "potential" "pow" "sin"
1997 "sinh" "slew" "sqrt" "tan" "tanh" "timer" "transition" "white_noise"
1998 "wreal" "zi_nd" "zi_np" "zi_zd" ) nil )))
2000 (verilog-font-keywords
2004 "assign" "case" "casex" "casez" "randcase" "deassign"
2005 "default" "disable" "else" "endcase" "endfunction"
2006 "endgenerate" "endinterface" "endmodule" "endprimitive"
2007 "endspecify" "endtable" "endtask" "final" "for" "force" "return" "break"
2008 "continue" "forever" "fork" "function" "generate" "if" "iff" "initial"
2009 "interface" "join" "join_any" "join_none" "macromodule" "module" "negedge"
2010 "package" "endpackage" "always" "always_comb" "always_ff"
2011 "always_latch" "posedge" "primitive" "priority" "release"
2012 "repeat" "specify" "table" "task" "unique" "wait" "while"
2013 "class" "program" "endclass" "endprogram"
2016 (verilog-font-grouping-keywords
2019 '( "begin" "end" ) nil ))))
2021 (setq verilog-font-lock-keywords
2023 ;; Fontify all builtin keywords
2024 (concat "\\<\\(" verilog-font-keywords "\\|"
2025 ;; And user/system tasks and functions
2026 "\\$[a-zA-Z][a-zA-Z0-9_\\$]*"
2028 ;; Fontify all types
2029 (if verilog-highlight-grouping-keywords
2030 (cons (concat "\\<\\(" verilog-font-grouping-keywords "\\)\\>")
2031 'verilog-font-lock-ams-face)
2032 (cons (concat "\\<\\(" verilog-font-grouping-keywords "\\)\\>")
2033 'font-lock-type-face))
2034 (cons (concat "\\<\\(" verilog-type-font-keywords "\\)\\>")
2035 'font-lock-type-face)
2036 ;; Fontify IEEE-P1800 keywords appropriately
2037 (if verilog-highlight-p1800-keywords
2038 (cons (concat "\\<\\(" verilog-p1800-keywords "\\)\\>")
2039 'verilog-font-lock-p1800-face)
2040 (cons (concat "\\<\\(" verilog-p1800-keywords "\\)\\>")
2041 'font-lock-type-face))
2042 ;; Fontify Verilog-AMS keywords
2043 (cons (concat "\\<\\(" verilog-ams-keywords "\\)\\>")
2044 'verilog-font-lock-ams-face)))
2046 (setq verilog-font-lock-keywords-1
2047 (append verilog-font-lock-keywords
2049 ;; Fontify module definitions
2051 "\\<\\(\\(macro\\)?module\\|primitive\\|class\\|program\\|interface\\|package\\|task\\)\\>\\s-*\\(\\sw+\\)"
2052 '(1 font-lock-keyword-face)
2053 '(3 font-lock-function-name-face 'prepend))
2054 ;; Fontify function definitions
2056 (concat "\\<function\\>\\s-+\\(integer\\|real\\(time\\)?\\|time\\)\\s-+\\(\\sw+\\)" )
2057 '(1 font-lock-keyword-face)
2058 '(3 font-lock-reference-face prepend))
2059 '("\\<function\\>\\s-+\\(\\[[^]]+\\]\\)\\s-+\\(\\sw+\\)"
2060 (1 font-lock-keyword-face)
2061 (2 font-lock-reference-face append))
2062 '("\\<function\\>\\s-+\\(\\sw+\\)"
2063 1 'font-lock-reference-face append))))
2065 (setq verilog-font-lock-keywords-2
2066 (append verilog-font-lock-keywords-1
2069 (concat "\\(//\\s-*" verilog-pragma-keywords "\\s-.*\\)")
2070 ;; Fontify escaped names
2071 '("\\(\\\\\\S-*\\s-\\)" 0 font-lock-function-name-face)
2072 ;; Fontify macro definitions/ uses
2073 '("`\\s-*[A-Za-z][A-Za-z0-9_]*" 0 (if (boundp 'font-lock-preprocessor-face)
2074 'font-lock-preprocessor-face
2075 'font-lock-type-face))
2076 ;; Fontify delays/numbers
2077 '("\\(@\\)\\|\\(#\\s-*\\(\\(\[0-9_.\]+\\('s?[hdxbo][0-9a-fA-F_xz]*\\)?\\)\\|\\(([^()]+)\\|\\sw+\\)\\)\\)"
2078 0 font-lock-type-face append)
2079 ;; Fontify instantiation names
2080 '("\\([A-Za-z][A-Za-z0-9_]+\\)\\s-*(" 1 font-lock-function-name-face)
2083 (setq verilog-font-lock-keywords-3
2084 (append verilog-font-lock-keywords-2
2085 (when verilog-highlight-translate-off
2087 ;; Fontify things in translate off regions
2088 '(verilog-match-translate-off
2089 (0 'verilog-font-lock-translate-off-face prepend))
2093 (defun verilog-inside-comment-p ()
2094 "Check if point inside a nested comment."
2096 (let ((st-point (point)) hitbeg)
2097 (or (search-backward "//" (verilog-get-beg-of-line) t)
2099 ;; This is for tricky case //*, we keep searching if /*
2100 ;; is proceeded by // on same line.
2102 (and (setq hitbeg (search-backward "/*" nil t))
2105 (search-backward "//" (verilog-get-beg-of-line) t))))
2107 (not (search-forward "*/" st-point t)))))))
2109 (defun verilog-declaration-end ()
2110 (search-forward ";"))
2112 (defun verilog-point-text (&optional pointnum)
2113 "Return text describing where POINTNUM or current point is (for errors).
2114 Use filename, if current buffer being edited shorten to just buffer name."
2115 (concat (or (and (equal (window-buffer (selected-window)) (current-buffer))
2119 ":" (int-to-string (count-lines (point-min) (or pointnum (point))))))
2121 (defun electric-verilog-backward-sexp ()
2122 "Move backward over one balanced expression."
2124 ;; before that see if we are in a comment
2125 (verilog-backward-sexp))
2127 (defun electric-verilog-forward-sexp ()
2128 "Move forward over one balanced expression."
2130 ;; before that see if we are in a comment
2131 (verilog-forward-sexp))
2133 ;;;used by hs-minor-mode
2134 (defun verilog-forward-sexp-function (arg)
2136 (verilog-backward-sexp)
2137 (verilog-forward-sexp)))
2140 (defun verilog-backward-sexp ()
2145 (if (not (looking-at "\\<"))
2148 ((verilog-skip-backward-comment-or-string))
2149 ((looking-at "\\<else\\>")
2151 verilog-end-block-re
2152 "\\|\\(\\<else\\>\\)"
2153 "\\|\\(\\<if\\>\\)"))
2154 (while (and (not found)
2155 (verilog-re-search-backward reg nil 'move))
2157 ((match-end 1) ; matched verilog-end-block-re
2158 ; try to leap back to matching outward block by striding across
2159 ; indent level changing tokens then immediately
2160 ; previous line governs indentation.
2161 (verilog-leap-to-head))
2162 ((match-end 2) ; else, we're in deep
2163 (setq elsec (1+ elsec)))
2164 ((match-end 3) ; found it
2165 (setq elsec (1- elsec))
2167 ;; Now previous line describes syntax
2168 (setq found 't))))))
2169 ((looking-at verilog-end-block-re)
2170 (verilog-leap-to-head))
2171 ((looking-at "\\(endmodule\\>\\)\\|\\(\\<endprimitive\\>\\)\\|\\(\\<endclass\\>\\)\\|\\(\\<endprogram\\>\\)\\|\\(\\<endinterface\\>\\)\\|\\(\\<endpackage\\>\\)")
2174 (verilog-re-search-backward "\\<\\(macro\\)?module\\>" nil 'move))
2176 (verilog-re-search-backward "\\<primitive\\>" nil 'move))
2178 (verilog-re-search-backward "\\<class\\>" nil 'move))
2180 (verilog-re-search-backward "\\<program\\>" nil 'move))
2182 (verilog-re-search-backward "\\<interface\\>" nil 'move))
2184 (verilog-re-search-backward "\\<package\\>" nil 'move))
2187 (backward-sexp 1))))
2192 (defun verilog-forward-sexp ()
2196 (if (not (looking-at "\\<"))
2199 ((verilog-skip-forward-comment-or-string)
2200 (verilog-forward-syntactic-ws))
2201 ((looking-at verilog-beg-block-re-ordered) ;; begin|(case)|xx|(fork)|class|table|specify|function|task|generate|covergroup|property|sequence|clocking
2203 ((match-end 1) ; end
2204 ;; Search forward for matching begin
2205 (setq reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)" ))
2206 ((match-end 2) ; endcase
2207 ;; Search forward for matching case
2208 (setq reg "\\(\\<randcase\\>\\|\\(\\<unique\\>\\s-+\\|\\<priority\\>\\s-+\\)?\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" )
2209 (setq md 3) ;; ender is third item in regexp
2211 ((match-end 4) ; join
2212 ;; might be "disable fork"
2214 (looking-at verilog-disable-fork-re)
2215 (and (looking-at "fork")
2218 (looking-at verilog-disable-fork-re))))
2220 (goto-char (match-end 0))
2224 ;; Search forward for matching fork
2225 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" ))))
2226 ((match-end 5) ; endclass
2227 ;; Search forward for matching class
2228 (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
2229 ((match-end 6) ; endtable
2230 ;; Search forward for matching table
2231 (setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" ))
2232 ((match-end 7) ; endspecify
2233 ;; Search forward for matching specify
2234 (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
2235 ((match-end 8) ; endfunction
2236 ;; Search forward for matching function
2237 (setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" ))
2238 ((match-end 9) ; endtask
2239 ;; Search forward for matching task
2240 (setq reg "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)" ))
2241 ((match-end 10) ; endgenerate
2242 ;; Search forward for matching generate
2243 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
2244 ((match-end 11) ; endgroup
2245 ;; Search forward for matching covergroup
2246 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" ))
2247 ((match-end 12) ; endproperty
2248 ;; Search forward for matching property
2249 (setq reg "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)" ))
2250 ((match-end 13) ; endsequence
2251 ;; Search forward for matching sequence
2252 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)" )
2253 (setq md 3)) ; 3 to get to endsequence in the reg above
2254 ((match-end 14) ; endclocking
2255 ;; Search forward for matching clocking
2256 (setq reg "\\(\\<clocking\\>\\)\\|\\(\\<endclocking\\>\\)" )))
2261 (while (verilog-re-search-forward reg nil 'move)
2263 ((match-end md) ; the closer in reg, so we are climbing out
2264 (setq nest (1- nest))
2265 (if (= 0 nest) ; we are out!
2267 ((match-end 1) ; the opener in reg, so we are deeper now
2268 (setq nest (1+ nest)))))))))
2269 ((looking-at (concat
2270 "\\(\\<\\(macro\\)?module\\>\\)\\|"
2271 "\\(\\<primitive\\>\\)\\|"
2272 "\\(\\<class\\>\\)\\|"
2273 "\\(\\<program\\>\\)\\|"
2274 "\\(\\<interface\\>\\)\\|"
2275 "\\(\\<package\\>\\)"))
2278 (verilog-re-search-forward "\\<endmodule\\>" nil 'move))
2280 (verilog-re-search-forward "\\<endprimitive\\>" nil 'move))
2282 (verilog-re-search-forward "\\<endclass\\>" nil 'move))
2284 (verilog-re-search-forward "\\<endprogram\\>" nil 'move))
2286 (verilog-re-search-forward "\\<endinterface\\>" nil 'move))
2288 (verilog-re-search-forward "\\<endpackage\\>" nil 'move))
2291 (if (= (following-char) ?\) )
2293 (forward-sexp 1)))))
2296 (if (= (following-char) ?\) )
2298 (forward-sexp 1))))))
2300 (defun verilog-declaration-beg ()
2301 (verilog-re-search-backward verilog-declaration-re (bobp) t))
2303 (defun verilog-font-lock-init ()
2304 "Initialize fontification."
2305 ;; highlight keywords and standardized types, attributes, enumeration
2306 ;; values, and subprograms
2307 (setq verilog-font-lock-keywords-3
2308 (append verilog-font-lock-keywords-2
2309 (when verilog-highlight-translate-off
2311 ;; Fontify things in translate off regions
2312 '(verilog-match-translate-off
2313 (0 'verilog-font-lock-translate-off-face prepend))))))
2314 (put 'verilog-mode 'font-lock-defaults
2315 '((verilog-font-lock-keywords
2316 verilog-font-lock-keywords-1
2317 verilog-font-lock-keywords-2
2318 verilog-font-lock-keywords-3)
2319 nil ; nil means highlight strings & comments as well as keywords
2320 nil ; nil means keywords must match case
2321 nil ; syntax table handled elsewhere
2322 ;; Function to move to beginning of reasonable region to highlight
2323 verilog-beg-of-defun)))
2325 ;; initialize fontification for Verilog Mode
2326 (verilog-font-lock-init)
2332 (defvar verilog-which-tool 1)
2334 (defun verilog-mode ()
2335 "Major mode for editing Verilog code.
2336 \\<verilog-mode-map>
2337 See \\[describe-function] verilog-auto (\\[verilog-auto]) for details on how
2338 AUTOs can improve coding efficiency.
2340 Use \\[verilog-faq] for a pointer to frequently asked questions.
2342 NEWLINE, TAB indents for Verilog code.
2343 Delete converts tabs to spaces as it moves back.
2345 Supports highlighting.
2347 Turning on Verilog mode calls the value of the variable `verilog-mode-hook'
2348 with no args, if that value is non-nil.
2350 Variables controlling indentation/edit style:
2352 variable `verilog-indent-level' (default 3)
2353 Indentation of Verilog statements with respect to containing block.
2354 `verilog-indent-level-module' (default 3)
2355 Absolute indentation of Module level Verilog statements.
2356 Set to 0 to get initial and always statements lined up
2357 on the left side of your screen.
2358 `verilog-indent-level-declaration' (default 3)
2359 Indentation of declarations with respect to containing block.
2360 Set to 0 to get them list right under containing block.
2361 `verilog-indent-level-behavioral' (default 3)
2362 Indentation of first begin in a task or function block
2363 Set to 0 to get such code to lined up underneath the task or
2365 `verilog-indent-level-directive' (default 1)
2366 Indentation of `ifdef/`endif blocks.
2367 `verilog-cexp-indent' (default 1)
2368 Indentation of Verilog statements broken across lines i.e.:
2371 `verilog-case-indent' (default 2)
2372 Indentation for case statements.
2373 `verilog-auto-newline' (default nil)
2374 Non-nil means automatically newline after semicolons and the punctuation
2376 `verilog-auto-indent-on-newline' (default t)
2377 Non-nil means automatically indent line after newline.
2378 `verilog-tab-always-indent' (default t)
2379 Non-nil means TAB in Verilog mode should always reindent the current line,
2380 regardless of where in the line point is when the TAB command is used.
2381 `verilog-indent-begin-after-if' (default t)
2382 Non-nil means to indent begin statements following a preceding
2383 if, else, while, for and repeat statements, if any. Otherwise,
2384 the begin is lined up with the preceding token. If t, you get:
2386 begin // amount of indent based on `verilog-cexp-indent'
2390 `verilog-auto-endcomments' (default t)
2391 Non-nil means a comment /* ... */ is set after the ends which ends
2392 cases, tasks, functions and modules.
2393 The type and name of the object will be set between the braces.
2394 `verilog-minimum-comment-distance' (default 10)
2395 Minimum distance (in lines) between begin and end required before a comment
2396 will be inserted. Setting this variable to zero results in every
2397 end acquiring a comment; the default avoids too many redundant
2398 comments in tight quarters.
2399 `verilog-auto-lineup' (default `(all))
2400 List of contexts where auto lineup of code should be done.
2402 Variables controlling other actions:
2404 `verilog-linter' (default surelint)
2405 Unix program to call to run the lint checker. This is the default
2406 command for \\[compile-command] and \\[verilog-auto-save-compile].
2408 See \\[customize] for the complete list of variables.
2410 AUTO expansion functions are, in part:
2412 \\[verilog-auto] Expand AUTO statements.
2413 \\[verilog-delete-auto] Remove the AUTOs.
2414 \\[verilog-inject-auto] Insert AUTOs for the first time.
2416 Some other functions are:
2418 \\[verilog-complete-word] Complete word with appropriate possibilities.
2419 \\[verilog-mark-defun] Mark function.
2420 \\[verilog-beg-of-defun] Move to beginning of current function.
2421 \\[verilog-end-of-defun] Move to end of current function.
2422 \\[verilog-label-be] Label matching begin ... end, fork ... join, etc statements.
2424 \\[verilog-comment-region] Put marked area in a comment.
2425 \\[verilog-uncomment-region] Uncomment an area commented with \\[verilog-comment-region].
2426 \\[verilog-insert-block] Insert begin ... end.
2427 \\[verilog-star-comment] Insert /* ... */.
2429 \\[verilog-sk-always] Insert an always @(AS) begin .. end block.
2430 \\[verilog-sk-begin] Insert a begin .. end block.
2431 \\[verilog-sk-case] Insert a case block, prompting for details.
2432 \\[verilog-sk-for] Insert a for (...) begin .. end block, prompting for details.
2433 \\[verilog-sk-generate] Insert a generate .. endgenerate block.
2434 \\[verilog-sk-header] Insert a header block at the top of file.
2435 \\[verilog-sk-initial] Insert an initial begin .. end block.
2436 \\[verilog-sk-fork] Insert a fork begin .. end .. join block.
2437 \\[verilog-sk-module] Insert a module .. (/*AUTOARG*/);.. endmodule block.
2438 \\[verilog-sk-primitive] Insert a primitive .. (.. );.. endprimitive block.
2439 \\[verilog-sk-repeat] Insert a repeat (..) begin .. end block.
2440 \\[verilog-sk-specify] Insert a specify .. endspecify block.
2441 \\[verilog-sk-task] Insert a task .. begin .. end endtask block.
2442 \\[verilog-sk-while] Insert a while (...) begin .. end block, prompting for details.
2443 \\[verilog-sk-casex] Insert a casex (...) item: begin.. end endcase block, prompting for details.
2444 \\[verilog-sk-casez] Insert a casez (...) item: begin.. end endcase block, prompting for details.
2445 \\[verilog-sk-if] Insert an if (..) begin .. end block.
2446 \\[verilog-sk-else-if] Insert an else if (..) begin .. end block.
2447 \\[verilog-sk-comment] Insert a comment block.
2448 \\[verilog-sk-assign] Insert an assign .. = ..; statement.
2449 \\[verilog-sk-function] Insert a function .. begin .. end endfunction block.
2450 \\[verilog-sk-input] Insert an input declaration, prompting for details.
2451 \\[verilog-sk-output] Insert an output declaration, prompting for details.
2452 \\[verilog-sk-state-machine] Insert a state machine definition, prompting for details.
2453 \\[verilog-sk-inout] Insert an inout declaration, prompting for details.
2454 \\[verilog-sk-wire] Insert a wire declaration, prompting for details.
2455 \\[verilog-sk-reg] Insert a register declaration, prompting for details.
2456 \\[verilog-sk-define-signal] Define signal under point as a register at the top of the module.
2458 All key bindings can be seen in a Verilog-buffer with \\[describe-bindings].
2459 Key bindings specific to `verilog-mode-map' are:
2461 \\{verilog-mode-map}"
2463 (kill-all-local-variables)
2464 (use-local-map verilog-mode-map)
2465 (setq major-mode 'verilog-mode)
2466 (setq mode-name "Verilog")
2467 (setq local-abbrev-table verilog-mode-abbrev-table)
2468 (set (make-local-variable 'beginning-of-defun-function)
2469 'verilog-beg-of-defun)
2470 (set (make-local-variable 'end-of-defun-function)
2471 'verilog-end-of-defun)
2472 (set-syntax-table verilog-mode-syntax-table)
2473 (make-local-variable 'indent-line-function)
2474 (setq indent-line-function 'verilog-indent-line-relative)
2475 (setq comment-indent-function 'verilog-comment-indent)
2476 (make-local-variable 'parse-sexp-ignore-comments)
2477 (setq parse-sexp-ignore-comments nil)
2478 (make-local-variable 'comment-start)
2479 (make-local-variable 'comment-end)
2480 (make-local-variable 'comment-multi-line)
2481 (make-local-variable 'comment-start-skip)
2482 (setq comment-start "// "
2484 comment-start-skip "/\\*+ *\\|// *"
2485 comment-multi-line nil)
2486 ;; Set up for compilation
2487 (setq verilog-which-tool 1)
2488 (setq verilog-tool 'verilog-linter)
2489 (verilog-set-compile-command)
2490 (when (boundp 'hack-local-variables-hook) ;; Also modify any file-local-variables
2491 (add-hook 'hack-local-variables-hook 'verilog-modify-compile-command t))
2494 (when (featurep 'xemacs)
2495 (easy-menu-add verilog-stmt-menu)
2496 (easy-menu-add verilog-menu)
2497 (setq mode-popup-menu (cons "Verilog Mode" verilog-stmt-menu)))
2499 ;; Stuff for GNU Emacs
2500 (set (make-local-variable 'font-lock-defaults)
2501 '((verilog-font-lock-keywords verilog-font-lock-keywords-1
2502 verilog-font-lock-keywords-2
2503 verilog-font-lock-keywords-3)
2504 nil nil nil verilog-beg-of-defun))
2505 ;;------------------------------------------------------------
2506 ;; now hook in 'verilog-colorize-include-files (eldo-mode.el&spice-mode.el)
2507 ;; all buffer local:
2508 (when (featurep 'xemacs)
2509 (make-local-hook 'font-lock-mode-hook)
2510 (make-local-hook 'font-lock-after-fontify-buffer-hook); doesn't exist in Emacs
2511 (make-local-hook 'after-change-functions))
2512 (add-hook 'font-lock-mode-hook 'verilog-colorize-include-files-buffer t t)
2513 (add-hook 'font-lock-after-fontify-buffer-hook 'verilog-colorize-include-files-buffer t t) ; not in Emacs
2514 (add-hook 'after-change-functions 'verilog-colorize-include-files t t)
2516 ;; Tell imenu how to handle Verilog.
2517 (make-local-variable 'imenu-generic-expression)
2518 (setq imenu-generic-expression verilog-imenu-generic-expression)
2520 (unless (assq 'verilog-mode hs-special-modes-alist)
2521 (setq hs-special-modes-alist
2522 (cons '(verilog-mode-mode "\\<begin\\>" "\\<end\\>" nil
2523 verilog-forward-sexp-function)
2524 hs-special-modes-alist)))
2527 (add-hook 'write-contents-hooks 'verilog-auto-save-check) ; already local
2528 ;; (verilog-auto-reeval-locals t) ; Save locals in case user changes them
2529 ;; (verilog-getopt-flags)
2530 (run-hooks 'verilog-mode-hook))
2534 ;; Electric functions
2536 (defun electric-verilog-terminate-line (&optional arg)
2537 "Terminate line and indent next line.
2538 With optional ARG, remove existing end of line comments."
2540 ;; before that see if we are in a comment
2541 (let ((state (save-excursion (verilog-syntax-ppss))))
2543 ((nth 7 state) ; Inside // comment
2546 (delete-horizontal-space)
2551 (beginning-of-line)))
2552 (verilog-indent-line))
2553 ((nth 4 state) ; Inside any comment (hence /**/)
2555 (verilog-more-comment))
2557 ;; First, check if current line should be indented
2559 (delete-horizontal-space)
2561 (skip-chars-forward " \t")
2562 (if (looking-at verilog-auto-end-comment-lines-re)
2563 (let ((indent-str (verilog-indent-line)))
2564 ;; Maybe we should set some endcomments
2565 (if verilog-auto-endcomments
2566 (verilog-set-auto-endcomments indent-str arg))
2568 (delete-horizontal-space)
2575 (delete-horizontal-space)
2577 ;; see if we should line up assignments
2579 (if (or (memq 'all verilog-auto-lineup)
2580 (memq 'assignments verilog-auto-lineup))
2581 (verilog-pretty-expr))
2585 (if verilog-auto-indent-on-newline
2586 (verilog-indent-line)))
2590 (defun electric-verilog-terminate-and-indent ()
2591 "Insert a newline and indent for the next statement."
2593 (electric-verilog-terminate-line 1))
2595 (defun electric-verilog-semi ()
2596 "Insert `;' character and reindent the line."
2598 (insert last-command-char)
2600 (if (or (verilog-in-comment-or-string-p)
2601 (verilog-in-escaped-name-p))
2605 (verilog-forward-ws&directives)
2606 (verilog-indent-line))
2607 (if (and verilog-auto-newline
2608 (not (verilog-parenthesis-depth)))
2609 (electric-verilog-terminate-line))))
2611 (defun electric-verilog-semi-with-comment ()
2612 "Insert `;' character, reindent the line and indent for comment."
2617 (verilog-indent-line))
2618 (indent-for-comment))
2620 (defun electric-verilog-colon ()
2621 "Insert `:' and do all indentations except line indent on this line."
2623 (insert last-command-char)
2624 ;; Do nothing if within string.
2626 (verilog-within-string)
2627 (not (verilog-in-case-region-p)))
2631 (lim (progn (verilog-beg-of-statement) (point))))
2633 (verilog-backward-case-item lim)
2634 (verilog-indent-line)))
2635 ;; (let ((verilog-tab-always-indent nil))
2636 ;; (verilog-indent-line))
2639 ;;(defun electric-verilog-equal ()
2640 ;; "Insert `=', and do indentation if within block."
2642 ;; (insert last-command-char)
2643 ;; Could auto line up expressions, but not yet
2644 ;; (if (eq (car (verilog-calculate-indent)) 'block)
2645 ;; (let ((verilog-tab-always-indent nil))
2646 ;; (verilog-indent-command)))
2649 (defun electric-verilog-tick ()
2650 "Insert back-tick, and indent to column 0 if this is a CPP directive."
2652 (insert last-command-char)
2656 (looking-at verilog-directive-re-1))
2657 (verilog-indent-line))))
2659 (defun electric-verilog-tab ()
2660 "Function called when TAB is pressed in Verilog mode."
2662 ;; If verilog-tab-always-indent, indent the beginning of the line.
2663 (if (or verilog-tab-always-indent
2665 (skip-chars-backward " \t")
2667 (let* ((oldpnt (point))
2671 (skip-chars-forward " \t")
2672 (verilog-indent-line)
2673 (back-to-indentation)
2675 (if (< (point) boi-point)
2676 (back-to-indentation)
2677 (cond ((not verilog-tab-to-comment))
2681 (indent-for-comment)
2682 (when (and (eolp) (= oldpnt (point)))
2683 ; kill existing comment
2685 (re-search-forward comment-start-skip oldpnt 'move)
2686 (goto-char (match-beginning 0))
2687 (skip-chars-backward " \t")
2688 (kill-region (point) oldpnt))))))
2689 (progn (insert "\t"))))
2694 ;; Interactive functions
2697 (defun verilog-indent-buffer ()
2698 "Indent-region the entire buffer as Verilog code.
2699 To call this from the command line, see \\[verilog-batch-indent]."
2702 (indent-region (point-min) (point-max) nil))
2704 (defun verilog-insert-block ()
2705 "Insert Verilog begin ... end; block in the code with right indentation."
2707 (verilog-indent-line)
2709 (electric-verilog-terminate-line)
2711 (electric-verilog-terminate-line)
2714 (verilog-indent-line)))
2716 (defun verilog-star-comment ()
2717 "Insert Verilog star comment at point."
2719 (verilog-indent-line)
2727 (defun verilog-insert-1 (fmt max)
2728 "Use format string FMT to insert integers 0 to MAX - 1.
2729 Inserts one integer per line, at the current column. Stops early
2730 if it reaches the end of the buffer."
2731 (let ((col (current-column))
2735 (insert (format fmt n))
2737 ;; Note that this function does not bother to check for lines
2738 ;; shorter than col.
2742 (move-to-column col))))))
2744 (defun verilog-insert-indices (max)
2745 "Insert a set of indices into a rectangle.
2746 The upper left corner is defined by point. Indices begin with 0
2747 and extend to the MAX - 1. If no prefix arg is given, the user
2748 is prompted for a value. The indices are surrounded by square
2749 brackets \[]. For example, the following code with the point
2750 located after the first 'a' gives:
2756 a = b ==> insert-indices ==> a[ 4] = b
2762 (interactive "NMAX: ")
2763 (verilog-insert-1 "[%3d]" max))
2765 (defun verilog-generate-numbers (max)
2766 "Insert a set of generated numbers into a rectangle.
2767 The upper left corner is defined by point. The numbers are padded to three
2768 digits, starting with 000 and extending to (MAX - 1). If no prefix argument
2769 is supplied, then the user is prompted for the MAX number. Consider the
2770 following code fragment:
2776 buf buf ==> generate-numbers ==> buf buf004
2782 (interactive "NMAX: ")
2783 (verilog-insert-1 "%3.3d" max))
2785 (defun verilog-mark-defun ()
2786 "Mark the current Verilog function (or procedure).
2787 This puts the mark at the end, and point at the beginning."
2789 (if (featurep 'xemacs)
2792 (verilog-end-of-defun)
2794 (verilog-beg-of-defun)
2795 (if (fboundp 'zmacs-activate-region)
2796 (zmacs-activate-region)))
2799 (defun verilog-comment-region (start end)
2800 ; checkdoc-params: (start end)
2801 "Put the region into a Verilog comment.
2802 The comments that are in this area are \"deformed\":
2803 `*)' becomes `!(*' and `}' becomes `!{'.
2804 These deformed comments are returned to normal if you use
2805 \\[verilog-uncomment-region] to undo the commenting.
2807 The commented area starts with `verilog-exclude-str-start', and ends with
2808 `verilog-exclude-str-end'. But if you change these variables,
2809 \\[verilog-uncomment-region] won't recognize the comments."
2812 ;; Insert start and endcomments
2814 (if (and (save-excursion (skip-chars-forward " \t") (eolp))
2815 (not (save-excursion (skip-chars-backward " \t") (bolp))))
2817 (beginning-of-line))
2818 (insert verilog-exclude-str-end)
2823 (insert verilog-exclude-str-start)
2825 ;; Replace end-comments within commented area
2828 (while (re-search-backward "\\*/" start t)
2829 (replace-match "*-/" t t)))
2831 (let ((s+1 (1+ start)))
2832 (while (re-search-backward "/\\*" s+1 t)
2833 (replace-match "/-*" t t))))))
2835 (defun verilog-uncomment-region ()
2836 "Uncomment a commented area; change deformed comments back to normal.
2837 This command does nothing if the pointer is not in a commented
2838 area. See also `verilog-comment-region'."
2841 (let ((start (point))
2843 ;; Find the boundaries of the comment
2845 (setq start (progn (search-backward verilog-exclude-str-start nil t)
2847 (setq end (progn (search-forward verilog-exclude-str-end nil t)
2849 ;; Check if we're really inside a comment
2850 (if (or (equal start (point)) (<= end (point)))
2851 (message "Not standing within commented area.")
2853 ;; Remove endcomment
2856 (let ((pos (point)))
2858 (delete-region pos (1+ (point))))
2859 ;; Change comments back to normal
2861 (while (re-search-backward "\\*-/" start t)
2862 (replace-match "*/" t t)))
2864 (while (re-search-backward "/-\\*" start t)
2865 (replace-match "/*" t t)))
2866 ;; Remove start comment
2869 (let ((pos (point)))
2871 (delete-region pos (1+ (point)))))))))
2873 (defun verilog-beg-of-defun ()
2874 "Move backward to the beginning of the current function or procedure."
2876 (verilog-re-search-backward verilog-defun-re nil 'move))
2878 (defun verilog-end-of-defun ()
2879 "Move forward to the end of the current function or procedure."
2881 (verilog-re-search-forward verilog-end-defun-re nil 'move))
2883 (defun verilog-get-beg-of-defun (&optional warn)
2885 (cond ((verilog-re-search-forward-quick verilog-defun-re nil t)
2888 (error "%s: Can't find module beginning" (verilog-point-text))
2890 (defun verilog-get-end-of-defun (&optional warn)
2892 (cond ((verilog-re-search-forward-quick verilog-end-defun-re nil t)
2895 (error "%s: Can't find endmodule" (verilog-point-text))
2898 (defun verilog-label-be (&optional arg)
2899 "Label matching begin ... end, fork ... join and case ... endcase statements.
2900 With ARG, first kill any existing labels."
2905 (verilog-beg-of-defun)
2908 (verilog-end-of-defun)
2910 (goto-char (marker-position b))
2912 (message "Relabeling module..."))
2914 (> (marker-position e) (point))
2915 (verilog-re-search-forward
2917 "\\<end\\(\\(function\\)\\|\\(task\\)\\|\\(module\\)\\|\\(primitive\\)\\|\\(interface\\)\\|\\(package\\)\\|\\(case\\)\\)?\\>"
2918 "\\|\\(`endif\\)\\|\\(`else\\)")
2920 (goto-char (match-beginning 0))
2921 (let ((indent-str (verilog-indent-line)))
2922 (verilog-set-auto-endcomments indent-str 't)
2924 (delete-horizontal-space))
2926 (if (= 9 (% cnt 10))
2927 (message "%d..." cnt)))
2932 (message "%d lines auto commented" cnt))))
2934 (defun verilog-beg-of-statement ()
2935 "Move backward to beginning of statement."
2937 ;; Move back token by token until we see the end
2938 ;; of some ealier line.
2940 ;; If the current point does not begin a new
2941 ;; statement, as in the character ahead of us is a ';', or SOF
2942 ;; or the string after us unambiguosly starts a statement,
2943 ;; or the token before us unambiguously ends a statement,
2944 ;; then move back a token and test again.
2947 (= (preceding-char) ?\;)
2952 (looking-at verilog-extended-complete-re)
2953 (not (save-excursion
2954 (verilog-backward-token)
2955 (looking-at verilog-extended-complete-re))))
2956 (looking-at verilog-basic-complete-re)
2958 (verilog-backward-token)
2960 (looking-at verilog-end-block-re)
2961 (looking-at verilog-preprocessor-re)))))
2962 (verilog-backward-syntactic-ws)
2963 (verilog-backward-token))
2964 ;; Now point is where the previous line ended.
2965 (verilog-forward-syntactic-ws))
2967 (defun verilog-beg-of-statement-1 ()
2968 "Move backward to beginning of statement."
2972 (while (and (not (looking-at verilog-complete-reg))
2974 (verilog-backward-token)
2975 (not (looking-at verilog-complete-reg))
2976 (verilog-backward-syntactic-ws)
2979 (not (= (preceding-char) ?\;))))
2981 (verilog-forward-ws&directives)))
2983 (defun verilog-end-of-statement ()
2984 "Move forward to end of current statement."
2987 (or (looking-at verilog-beg-block-re)
2988 ;; Skip to end of statement
2989 (setq pos (catch 'found
2992 (verilog-skip-forward-comment-or-string)
2993 (cond ((looking-at "[ \t]*;")
2994 (skip-chars-forward "^;")
2996 (throw 'found (point)))
2999 (looking-at verilog-beg-block-re))
3000 (goto-char (match-beginning 0))
3002 ((looking-at "[ \t]*)")
3003 (throw 'found (point)))
3005 (throw 'found (point))))))))
3007 ;; Skip a whole block
3010 (verilog-re-search-forward verilog-end-statement-re nil 'move)
3011 (setq nest (if (match-end 1)
3015 (throw 'found (point)))
3017 (throw 'found (verilog-end-of-statement))))))
3020 (defun verilog-in-case-region-p ()
3021 "Return true if in a case region.
3022 More specifically, point @ in the line foo : @ begin"
3026 (progn (verilog-forward-syntactic-ws)
3027 (looking-at "\\<begin\\>"))
3028 (progn (verilog-backward-syntactic-ws)
3029 (= (preceding-char) ?\:)))
3033 (verilog-re-search-backward
3034 (concat "\\(\\<module\\>\\)\\|\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|"
3035 "\\(\\<endcase\\>\\)\\>")
3039 (setq nest (1+ nest)))
3043 (setq nest (1- nest)))
3045 (throw 'found (= nest 0)))))))
3047 (defun verilog-in-struct-region-p ()
3048 "Return true if in a struct region.
3049 More specifically, in a list after a struct|union keyword."
3052 (let* ((state (verilog-syntax-ppss))
3053 (depth (nth 0 state)))
3055 (progn (backward-up-list depth)
3056 (verilog-beg-of-statement)
3057 (looking-at "\\<typedef\\>?\\s-*\\<struct\\|union\\>"))))))
3059 (defun verilog-in-generate-region-p ()
3060 "Return true if in a generate region.
3061 More specifically, after a generate and before an endgenerate."
3063 (let ((lim (save-excursion (verilog-beg-of-defun) (point)))
3068 (verilog-re-search-backward "\\<\\(generate\\)\\|\\(endgenerate\\)\\>" lim 'move)
3070 ((match-end 1) ; generate
3071 (setq nest (1- nest)))
3072 ((match-end 2) ; endgenerate
3073 (setq nest (1+ nest)))))))
3074 (= nest 0) )) ; return nest
3076 (defun verilog-in-fork-region-p ()
3077 "Return true if between a fork and join."
3079 (let ((lim (save-excursion (verilog-beg-of-defun) (point)))
3084 (verilog-re-search-backward "\\<\\(fork\\)\\|\\(join\\(_any\\|_none\\)?\\)\\>" lim 'move)
3086 ((match-end 1) ; fork
3087 (setq nest (1- nest)))
3088 ((match-end 2) ; join
3089 (setq nest (1+ nest)))))))
3090 (= nest 0) )) ; return nest
3092 (defun verilog-backward-case-item (lim)
3093 "Skip backward to nearest enclosing case item.
3094 Limit search to point LIM."
3100 (verilog-re-search-backward verilog-endcomment-reason-re
3103 ;; Try to find the real :
3104 (if (save-excursion (search-backward ":" lim1 t))
3110 (verilog-re-search-backward "\\(\\[\\)\\|\\(\\]\\)\\|\\(:\\)"
3114 (setq colon (1+ colon))
3116 (error "%s: unbalanced [" (verilog-point-text))))
3118 (setq colon (1- colon)))
3121 (setq colon (1+ colon)))))
3122 ;; Skip back to beginning of case item
3123 (skip-chars-backward "\t ")
3124 (verilog-skip-backward-comment-or-string)
3129 (verilog-re-search-backward
3130 "\\<\\(case[zx]?\\)\\>\\|;\\|\\<end\\>" nil 'move)
3134 (goto-char (match-end 1))
3135 (verilog-forward-ws&directives)
3136 (if (looking-at "(")
3139 (verilog-forward-ws&directives)))
3142 (goto-char (match-end 0))
3143 (verilog-forward-ws&directives)
3145 (error "Malformed case item"))))
3146 (setq str (buffer-substring b e))
3150 "[ \t]*\\(\\(\n\\)\\|\\(//\\)\\|\\(/\\*\\)\\)" str))
3151 (setq str (concat (substring str 0 e) "...")))
3160 (defun verilog-kill-existing-comment ()
3161 "Kill auto comment on this line."
3169 (search-forward "//" e t))))
3171 (delete-region (- b 2) e)))))
3173 (defconst verilog-directive-nest-re
3174 (concat "\\(`else\\>\\)\\|"
3175 "\\(`endif\\>\\)\\|"
3177 "\\(`ifdef\\>\\)\\|"
3178 "\\(`ifndef\\>\\)"))
3179 (defun verilog-set-auto-endcomments (indent-str kill-existing-comment)
3180 "Add ending comment with given INDENT-STR.
3181 With KILL-EXISTING-COMMENT, remove what was there before.
3182 Insert `// case: 7 ' or `// NAME ' on this line if appropriate.
3183 Insert `// case expr ' if this line ends a case block.
3184 Insert `// ifdef FOO ' if this line ends code conditional on FOO.
3185 Insert `// NAME ' if this line ends a function, task, module,
3186 primitive or interface named NAME."
3189 (; Comment close preprocessor directives
3191 (looking-at "\\(`endif\\)\\|\\(`else\\)")
3192 (or kill-existing-comment
3193 (not (save-excursion
3195 (search-backward "//" (verilog-get-beg-of-line) t)))))
3198 (else (if (match-end 2) "!" " ")))
3200 (if kill-existing-comment
3201 (verilog-kill-existing-comment))
3202 (delete-horizontal-space)
3205 (while (and (/= nest 0)
3206 (verilog-re-search-backward verilog-directive-nest-re nil 'move))
3208 ((match-end 1) ; `else
3211 ((match-end 2) ; `endif
3212 (setq nest (1+ nest)))
3213 ((match-end 3) ; `if
3214 (setq nest (1- nest)))
3215 ((match-end 4) ; `ifdef
3216 (setq nest (1- nest)))
3217 ((match-end 5) ; `ifndef
3218 (setq nest (1- nest)))))
3225 (skip-chars-forward "^ \t")
3226 (verilog-forward-syntactic-ws)
3229 (skip-chars-forward "a-zA-Z0-9_")
3232 (if (> (count-lines (point) b) verilog-minimum-comment-distance)
3233 (insert (concat " // " else m " " (buffer-substring b e))))
3235 (insert " // unmatched `else or `endif")
3238 (; Comment close case/class/function/task/module and named block
3239 (and (looking-at "\\<end")
3240 (or kill-existing-comment
3241 (not (save-excursion
3243 (search-backward "//" (verilog-get-beg-of-line) t)))))
3244 (let ((type (car indent-str)))
3245 (unless (eq type 'declaration)
3246 (unless (looking-at (concat "\\(" verilog-end-block-ordered-re "\\)[ \t]*:")) ;; ignore named ends
3247 (if (looking-at verilog-end-block-ordered-re)
3249 (;- This is a case block; search back for the start of this case
3250 (match-end 1) ;; of verilog-end-block-ordered-re
3253 (str "UNMATCHED!!"))
3255 (verilog-leap-to-head)
3257 ((looking-at "\\<randcase\\>")
3258 (setq str "randcase")
3261 (goto-char (match-end 1))
3264 (setq s (match-beginning 1))
3265 (setq f (progn (end-of-line)
3267 (setq str (buffer-substring s f)))
3269 (setq str (concat (buffer-substring (match-beginning 1) (match-end 1))
3271 (verilog-get-expr))))))
3273 (if kill-existing-comment
3274 (verilog-kill-existing-comment))
3275 (delete-horizontal-space)
3276 (insert (concat " // " str ))
3277 (if err (ding 't))))
3279 (;- This is a begin..end block
3280 (match-end 2) ;; of verilog-end-block-ordered-re
3281 (let ((str " // UNMATCHED !!")
3287 (verilog-leap-to-head)
3288 (setq there (point))
3289 (if (not (match-end 0))
3293 (if kill-existing-comment
3294 (verilog-kill-existing-comment))
3295 (delete-horizontal-space)
3299 (save-excursion (verilog-beg-of-defun) (point)))
3302 (;-- handle named block differently
3303 (looking-at verilog-named-block-re)
3304 (search-forward ":")
3305 (setq there (point))
3306 (setq str (verilog-get-expr))
3308 (setq str (concat " // block: " str )))
3310 ((verilog-in-case-region-p) ;-- handle case item differently
3312 (setq str (verilog-backward-case-item lim))
3313 (setq there (point))
3315 (setq str (concat " // case: " str )))
3317 (;- try to find "reason" for this begin
3321 (verilog-backward-token)
3322 (verilog-beg-of-statement-1)
3326 ((looking-at verilog-endcomment-reason-re)
3327 (setq there (match-end 0))
3329 (buffer-substring (match-beginning 0) (match-end 0)) " "))
3335 (if (and (verilog-continued-line)
3336 (looking-at "\\<repeat\\>\\|\\<wait\\>\\|\\<always\\>"))
3338 (goto-char (match-end 0))
3339 (setq there (point))
3342 (buffer-substring (match-beginning 0) (match-end 0)) " "
3343 (verilog-get-expr))))
3349 ( reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<if\\>\\)"))
3351 (while (verilog-re-search-backward reg nil 'move)
3353 ((match-end 1) ; begin
3354 (setq nest (1- nest)))
3355 ((match-end 2) ; end
3356 (setq nest (1+ nest)))
3360 (goto-char (match-end 0))
3361 (setq there (point))
3363 (setq str (verilog-get-expr))
3364 (setq str (concat " // else: !if" str ))
3365 (throw 'skip 1)))))))))
3371 (reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<if\\>\\)"))
3373 (while (verilog-re-search-backward reg nil 'move)
3375 ((match-end 1) ; begin
3376 (setq nest (1- nest)))
3377 ((match-end 2) ; end
3378 (setq nest (1+ nest)))
3382 (goto-char (match-end 0))
3383 (setq there (point))
3385 (setq str (verilog-get-expr))
3386 (setq str (concat " // else: !if" str ))
3387 (throw 'skip 1)))))))))
3389 (;- task/function/initial et cetera
3392 (goto-char (match-end 0))
3393 (setq there (point))
3395 (setq str (verilog-get-expr))
3396 (setq str (concat " // " cntx str )))
3399 (setq str " // auto-endcomment confused "))))
3402 (verilog-in-case-region-p) ;-- handle case item differently
3404 (setq there (point))
3406 (setq str (verilog-backward-case-item lim))))
3408 (setq str (concat " // case: " str )))
3410 ((verilog-in-fork-region-p)
3412 (setq str " // fork branch" ))
3414 ((looking-at "\\<end\\>")
3417 (verilog-forward-syntactic-ws)
3419 (setq str (verilog-get-expr))
3420 (setq str (concat " // " cntx str )))
3425 (if kill-existing-comment
3426 (verilog-kill-existing-comment))
3427 (delete-horizontal-space)
3429 (> (count-lines here there) verilog-minimum-comment-distance))
3433 (;- this is endclass, which can be nested
3434 (match-end 11) ;; of verilog-end-block-ordered-re
3437 (reg "\\<\\(class\\)\\|\\(endclass\\)\\|\\(package\\|primitive\\|\\(macro\\)?module\\)\\>")
3441 (while (verilog-re-search-backward reg nil 'move)
3443 ((match-end 3) ; endclass
3445 (setq string "unmatched endclass")
3448 ((match-end 2) ; endclass
3449 (setq nest (1+ nest)))
3451 ((match-end 1) ; class
3452 (setq nest (1- nest))
3455 (goto-char (match-end 0))
3458 (skip-chars-forward "^ \t")
3459 (verilog-forward-ws&directives)
3462 (skip-chars-forward "a-zA-Z0-9_")
3464 (setq string (buffer-substring b e)))
3468 (insert (concat " // " string ))))
3470 (;- this is end{function,generate,task,module,primitive,table,generate}
3471 ;- which can not be nested.
3473 (let (string reg (width nil))
3475 (if kill-existing-comment
3477 (verilog-kill-existing-comment)))
3478 (delete-horizontal-space)
3481 ((match-end 5) ;; of verilog-end-block-ordered-re
3482 (setq reg "\\(\\<function\\>\\)\\|\\(\\<\\(endfunction\\|task\\|\\(macro\\)?module\\|primitive\\)\\>\\)")
3483 (setq width "\\(\\s-*\\(\\[[^]]*\\]\\)\\|\\(real\\(time\\)?\\)\\|\\(integer\\)\\|\\(time\\)\\)?"))
3484 ((match-end 6) ;; of verilog-end-block-ordered-re
3485 (setq reg "\\(\\<task\\>\\)\\|\\(\\<\\(endtask\\|function\\|\\(macro\\)?module\\|primitive\\)\\>\\)"))
3486 ((match-end 7) ;; of verilog-end-block-ordered-re
3487 (setq reg "\\(\\<\\(macro\\)?module\\>\\)\\|\\<endmodule\\>"))
3488 ((match-end 8) ;; of verilog-end-block-ordered-re
3489 (setq reg "\\(\\<primitive\\>\\)\\|\\(\\<\\(endprimitive\\|package\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
3490 ((match-end 9) ;; of verilog-end-block-ordered-re
3491 (setq reg "\\(\\<interface\\>\\)\\|\\(\\<\\(endinterface\\|package\\|primitive\\|\\(macro\\)?module\\)\\>\\)"))
3492 ((match-end 10) ;; of verilog-end-block-ordered-re
3493 (setq reg "\\(\\<package\\>\\)\\|\\(\\<\\(endpackage\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
3494 ((match-end 11) ;; of verilog-end-block-ordered-re
3495 (setq reg "\\(\\<class\\>\\)\\|\\(\\<\\(endclass\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
3496 ((match-end 12) ;; of verilog-end-block-ordered-re
3497 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<\\(endcovergroup\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
3498 ((match-end 13) ;; of verilog-end-block-ordered-re
3499 (setq reg "\\(\\<program\\>\\)\\|\\(\\<\\(endprogram\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
3500 ((match-end 14) ;; of verilog-end-block-ordered-re
3501 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<\\(endsequence\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
3502 ((match-end 15) ;; of verilog-end-block-ordered-re
3503 (setq reg "\\(\\<clocking\\>\\)\\|\\<endclocking\\>"))
3505 (t (error "Problem in verilog-set-auto-endcomments")))
3508 (verilog-re-search-backward reg nil 'move)
3512 (skip-chars-forward "^ \t")
3513 (verilog-forward-ws&directives)
3514 (if (and width (looking-at width))
3516 (goto-char (match-end 0))
3517 (verilog-forward-ws&directives)))
3520 (skip-chars-forward "a-zA-Z0-9_")
3522 (setq string (buffer-substring b e)))
3525 (setq string "unmatched end(function|task|module|primitive|interface|package|class|clocking)")))))
3527 (insert (concat " // " string )))
3530 (defun verilog-get-expr()
3531 "Grab expression at point, e.g, case ( a | b & (c ^d))."
3533 (verilog-forward-syntactic-ws)
3534 (skip-chars-forward " \t")
3540 (verilog-forward-syntactic-ws)
3541 (if (looking-at "(")
3544 (while (and (/= par 0)
3545 (verilog-re-search-forward "\\((\\)\\|\\()\\)" nil 'move))
3548 (setq par (1+ par)))
3550 (setq par (1- par)))))))
3554 (while (and (/= par 0)
3555 (verilog-re-search-forward "\\((\\)\\|\\()\\)" nil 'move))
3558 (setq par (1+ par)))
3560 (setq par (1- par)))))
3564 (while (and (/= par 0)
3565 (verilog-re-search-forward "\\(\\[\\)\\|\\(\\]\\)" nil 'move))
3568 (setq par (1+ par)))
3570 (setq par (1- par)))))
3571 (verilog-forward-syntactic-ws)
3572 (skip-chars-forward "^ \t\n\f")
3574 ((looking-at "/[/\\*]")
3577 (skip-chars-forward "^: \t\n\f")
3579 (str (buffer-substring b e)))
3580 (if (setq e (string-match "[ \t]*\\(\\(\n\\)\\|\\(//\\)\\|\\(/\\*\\)\\)" str))
3581 (setq str (concat (substring str 0 e) "...")))
3584 (defun verilog-expand-vector ()
3585 "Take a signal vector on the current line and expand it to multiple lines.
3586 Useful for creating tri's and other expanded fields."
3588 (verilog-expand-vector-internal "[" "]"))
3590 (defun verilog-expand-vector-internal (bra ket)
3591 "Given BRA, the start brace and KET, the end brace, expand one line into many lines."
3594 (let ((signal-string (buffer-substring (point)
3596 (end-of-line) (point)))))
3600 "\\([0-9]*\\)\\(:[0-9]*\\|\\)\\(::[0-9---]*\\|\\)"
3602 "\\(.*\\)$") signal-string)
3603 (let* ((sig-head (match-string 1 signal-string))
3604 (vec-start (string-to-number (match-string 2 signal-string)))
3605 (vec-end (if (= (match-beginning 3) (match-end 3))
3608 (substring signal-string (1+ (match-beginning 3))
3611 (if (= (match-beginning 4) (match-end 4))
3614 (substring signal-string (+ 2 (match-beginning 4))
3616 (sig-tail (match-string 5 signal-string))
3621 (let ((tmp vec-start))
3622 (setq vec-start vec-end
3624 vec-range (- vec-range))))
3625 (if (< vec-end vec-start)
3626 (while (<= vec-end vec-start)
3627 (setq vec (append vec (list vec-start)))
3628 (setq vec-start (- vec-start vec-range)))
3629 (while (<= vec-start vec-end)
3630 (setq vec (append vec (list vec-start)))
3631 (setq vec-start (+ vec-start vec-range))))
3633 ;; Delete current line
3634 (delete-region (point) (progn (forward-line 0) (point)))
3638 (insert (concat sig-head bra
3639 (int-to-string (car vec)) ket sig-tail "\n"))
3640 (setq vec (cdr vec)))
3645 (defun verilog-strip-comments ()
3646 "Strip all comments from the Verilog code."
3648 (goto-char (point-min))
3649 (while (re-search-forward "//" nil t)
3650 (if (verilog-within-string)
3651 (re-search-forward "\"" nil t)
3652 (if (verilog-in-star-comment-p)
3653 (re-search-forward "\*/" nil t)
3654 (let ((bpt (- (point) 2)))
3656 (delete-region bpt (point))))))
3658 (goto-char (point-min))
3659 (while (re-search-forward "/\\*" nil t)
3660 (if (verilog-within-string)
3661 (re-search-forward "\"" nil t)
3662 (let ((bpt (- (point) 2)))
3663 (re-search-forward "\\*/")
3664 (delete-region bpt (point))))))
3666 (defun verilog-one-line ()
3667 "Convert structural Verilog instances to occupy one line."
3669 (goto-char (point-min))
3670 (while (re-search-forward "\\([^;]\\)[ \t]*\n[ \t]*" nil t)
3671 (replace-match "\\1 " nil nil)))
3673 (defun verilog-linter-name ()
3674 "Return name of linter, either surelint or verilint."
3675 (let ((compile-word1 (verilog-string-replace-matches "\\s .*$" "" nil nil
3677 (lint-word1 (verilog-string-replace-matches "\\s .*$" "" nil nil
3679 (cond ((equal compile-word1 "surelint") `surelint)
3680 ((equal compile-word1 "verilint") `verilint)
3681 ((equal lint-word1 "surelint") `surelint)
3682 ((equal lint-word1 "verilint") `verilint)
3683 (t `surelint)))) ;; back compatibility
3685 (defun verilog-lint-off ()
3686 "Convert a Verilog linter warning line into a disable statement.
3688 pci_bfm_null.v, line 46: Unused input: pci_rst_
3689 becomes a comment for the appropriate tool.
3691 The first word of the `compile-command' or `verilog-linter'
3692 variables is used to determine which product is being used.
3694 See \\[verilog-surelint-off] and \\[verilog-verilint-off]."
3696 (let ((linter (verilog-linter-name)))
3697 (cond ((equal linter `surelint)
3698 (verilog-surelint-off))
3699 ((equal linter `verilint)
3700 (verilog-verilint-off))
3701 (t (error "Linter name not set")))))
3703 (defvar compilation-last-buffer)
3705 (defun verilog-surelint-off ()
3706 "Convert a SureLint warning line into a disable statement.
3707 Run from Verilog source window; assumes there is a *compile* buffer
3708 with point set appropriately.
3711 WARNING [STD-UDDONX]: xx.v, line 8: output out is never assigned.
3713 // surefire lint_line_off UDDONX"
3715 (let ((buff (if (boundp 'next-error-last-buffer)
3716 next-error-last-buffer
3717 compilation-last-buffer)))
3718 (when (buffer-live-p buff)
3719 ;; FIXME with-current-buffer?
3721 (switch-to-buffer buff)
3724 (looking-at "\\(INFO\\|WARNING\\|ERROR\\) \\[[^-]+-\\([^]]+\\)\\]: \\([^,]+\\), line \\([0-9]+\\): \\(.*\\)$")
3725 (let* ((code (match-string 2))
3726 (file (match-string 3))
3727 (line (match-string 4))
3728 (buffer (get-file-buffer file))
3733 (and (file-exists-p file)
3734 (find-file-noselect file)))
3736 (let* ((pop-up-windows t))
3737 (let ((name (expand-file-name
3739 (format "Find this error in: (default %s) "
3742 (if (file-directory-p name)
3743 (setq name (expand-file-name filename name)))
3745 (and (file-exists-p name)
3746 (find-file-noselect name))))))))
3747 (switch-to-buffer buffer)
3748 (goto-line (string-to-number line))
3752 ((verilog-in-slash-comment-p)
3753 (re-search-backward "//")
3755 ((looking-at "// surefire lint_off_line ")
3756 (goto-char (match-end 0))
3757 (let ((lim (save-excursion (end-of-line) (point))))
3758 (if (re-search-forward code lim 'move)
3760 (insert (concat " " code)))))
3763 ((verilog-in-star-comment-p)
3764 (re-search-backward "/\*")
3765 (insert (format " // surefire lint_off_line %6s" code )))
3767 (insert (format " // surefire lint_off_line %6s" code ))
3770 (defun verilog-verilint-off ()
3771 "Convert a Verilint warning line into a disable statement.
3774 (W240) pci_bfm_null.v, line 46: Unused input: pci_rst_
3776 //Verilint 240 off // WARNING: Unused input"
3780 (when (looking-at "\\(.*\\)([WE]\\([0-9A-Z]+\\)).*,\\s +line\\s +[0-9]+:\\s +\\([^:\n]+\\):?.*$")
3781 (replace-match (format
3782 ;; %3s makes numbers 1-999 line up nicely
3783 "\\1//Verilint %3s off // WARNING: \\3"
3786 (verilog-indent-line))))
3788 (defun verilog-auto-save-compile ()
3789 "Update automatics with \\[verilog-auto], save the buffer, and compile."
3791 (verilog-auto) ; Always do it for safety
3793 (compile compile-command))
3801 (defmacro verilog-batch-error-wrapper (&rest body)
3802 "Execute BODY and add error prefix to any errors found.
3803 This lets programs calling batch mode to easily extract error messages."
3804 `(condition-case err
3807 (error "%%Error: %s%s" (error-message-string err)
3808 (if (featurep 'xemacs) "\n" ""))))) ;; XEmacs forgets to add a newline
3810 (defun verilog-batch-execute-func (funref)
3811 "Internal processing of a batch command, running FUNREF on all command arguments."
3812 (verilog-batch-error-wrapper
3813 ;; General globals needed
3814 (setq make-backup-files nil)
3815 (setq-default make-backup-files nil)
3816 (setq enable-local-variables t)
3817 (setq enable-local-eval t)
3818 ;; Make sure any sub-files we read get proper mode
3819 (setq default-major-mode `verilog-mode)
3820 ;; Ditto files already read in
3822 (when (buffer-file-name buf)
3827 ;; Process the files
3828 (mapcar '(lambda (buf)
3829 (when (buffer-file-name buf)
3831 (if (not (file-exists-p (buffer-file-name buf)))
3833 (concat "File not found: " (buffer-file-name buf))))
3834 (message (concat "Processing " (buffer-file-name buf)))
3840 (defun verilog-batch-auto ()
3841 "For use with --batch, perform automatic expansions as a stand-alone tool.
3842 This sets up the appropriate Verilog mode environment, updates automatics
3843 with \\[verilog-auto] on all command-line files, and saves the buffers.
3844 For proper results, multiple filenames need to be passed on the command
3845 line in bottom-up order."
3846 (unless noninteractive
3847 (error "Use verilog-batch-auto only with --batch")) ;; Otherwise we'd mess up buffer modes
3848 (verilog-batch-execute-func `verilog-auto))
3850 (defun verilog-batch-delete-auto ()
3851 "For use with --batch, perform automatic deletion as a stand-alone tool.
3852 This sets up the appropriate Verilog mode environment, deletes automatics
3853 with \\[verilog-delete-auto] on all command-line files, and saves the buffers."
3854 (unless noninteractive
3855 (error "Use verilog-batch-delete-auto only with --batch")) ;; Otherwise we'd mess up buffer modes
3856 (verilog-batch-execute-func `verilog-delete-auto))
3858 (defun verilog-batch-inject-auto ()
3859 "For use with --batch, perform automatic injection as a stand-alone tool.
3860 This sets up the appropriate Verilog mode environment, injects new automatics
3861 with \\[verilog-inject-auto] on all command-line files, and saves the buffers.
3862 For proper results, multiple filenames need to be passed on the command
3863 line in bottom-up order."
3864 (unless noninteractive
3865 (error "Use verilog-batch-inject-auto only with --batch")) ;; Otherwise we'd mess up buffer modes
3866 (verilog-batch-execute-func `verilog-inject-auto))
3868 (defun verilog-batch-indent ()
3869 "For use with --batch, reindent an a entire file as a stand-alone tool.
3870 This sets up the appropriate Verilog mode environment, calls
3871 \\[verilog-indent-buffer] on all command-line files, and saves the buffers."
3872 (unless noninteractive
3873 (error "Use verilog-batch-indent only with --batch")) ;; Otherwise we'd mess up buffer modes
3874 (verilog-batch-execute-func `verilog-indent-buffer))
3880 (defconst verilog-indent-alist
3881 '((block . (+ ind verilog-indent-level))
3882 (case . (+ ind verilog-case-indent))
3883 (cparenexp . (+ ind verilog-indent-level))
3884 (cexp . (+ ind verilog-cexp-indent))
3885 (defun . verilog-indent-level-module)
3886 (declaration . verilog-indent-level-declaration)
3887 (directive . (verilog-calculate-indent-directive))
3888 (tf . verilog-indent-level)
3889 (behavioral . (+ verilog-indent-level-behavioral verilog-indent-level-module))
3892 (comment . (verilog-comment-indent))
3896 (defun verilog-continued-line-1 (lim)
3897 "Return true if this is a continued line.
3898 Set point to where line starts. Limit search to point LIM."
3899 (let ((continued 't))
3900 (if (eq 0 (forward-line -1))
3903 (verilog-backward-ws&directives lim)
3905 (setq continued nil)
3906 (setq continued (verilog-backward-token))))
3907 (setq continued nil))
3910 (defun verilog-calculate-indent ()
3911 "Calculate the indent of the current Verilog line.
3912 Examine previous lines. Once a line is found that is definitive as to the
3913 type of the current line, return that lines' indent level and its type.
3914 Return a list of two elements: (INDENT-TYPE INDENT-LEVEL)."
3916 (let* ((starting_position (point))
3918 (begin (looking-at "[ \t]*begin\\>"))
3919 (lim (save-excursion (verilog-re-search-backward "\\(\\<begin\\>\\)\\|\\(\\<module\\>\\)" nil t)))
3920 (type (catch 'nesting
3921 ;; Keep working backwards until we can figure out
3922 ;; what type of statement this is.
3923 ;; Basically we need to figure out
3924 ;; 1) if this is a continuation of the previous line;
3925 ;; 2) are we in a block scope (begin..end)
3927 ;; if we are in a comment, done.
3928 (if (verilog-in-star-comment-p)
3929 (throw 'nesting 'comment))
3931 ;; if we have a directive, done.
3932 (if (save-excursion (beginning-of-line) (looking-at verilog-directive-re-1))
3933 (throw 'nesting 'directive))
3935 ;; unless we are in the newfangled coverpoint or constraint blocks
3936 ;; if we are in a parenthesized list, and the user likes to indent these, return.
3938 verilog-indent-lists
3939 (not (verilog-in-coverage))
3942 (throw 'nesting 'block)))
3944 ;; See if we are continuing a previous line
3946 ;; trap out if we crawl off the top of the buffer
3947 (if (bobp) (throw 'nesting 'cpp))
3949 (if (verilog-continued-line-1 lim)
3952 (not (looking-at verilog-complete-reg))
3953 (verilog-continued-line-1 lim))
3954 (progn (goto-char sp)
3955 (throw 'nesting 'cexp))
3960 (not verilog-indent-begin-after-if)
3961 (looking-at verilog-no-indent-begin-re))
3964 (skip-chars-forward " \t")
3965 (throw 'nesting 'statement))
3967 (throw 'nesting 'cexp))))
3968 ;; not a continued line
3969 (goto-char starting_position))
3971 (if (looking-at "\\<else\\>")
3972 ;; search back for governing if, striding across begin..end pairs
3975 (while (verilog-re-search-backward verilog-ends-re nil 'move)
3977 ((match-end 1) ; else, we're in deep
3978 (setq elsec (1+ elsec)))
3980 (setq elsec (1- elsec))
3982 (if verilog-align-ifelse
3983 (throw 'nesting 'statement)
3984 (progn ;; back up to first word on this line
3986 (verilog-forward-syntactic-ws)
3987 (throw 'nesting 'statement)))))
3989 ; try to leap back to matching outward block by striding across
3990 ; indent level changing tokens then immediately
3991 ; previous line governs indentation.
3992 (let (( reg) (nest 1))
3993 ;; verilog-ends => else|if|end|join(_any|_none|)|endcase|endclass|endtable|endspecify|endfunction|endtask|endgenerate|endgroup
3995 ((match-end 3) ; end
3996 ;; Search back for matching begin
3997 (setq reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)" ))
3998 ((match-end 4) ; endcase
3999 ;; Search back for matching case
4000 (setq reg "\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" ))
4001 ((match-end 5) ; endfunction
4002 ;; Search back for matching function
4003 (setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" ))
4004 ((match-end 6) ; endtask
4005 ;; Search back for matching task
4006 (setq reg "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)" ))
4007 ((match-end 7) ; endspecify
4008 ;; Search back for matching specify
4009 (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
4010 ((match-end 8) ; endtable
4011 ;; Search back for matching table
4012 (setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" ))
4013 ((match-end 9) ; endgenerate
4014 ;; Search back for matching generate
4015 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
4016 ((match-end 10) ; joins
4017 ;; Search back for matching fork
4018 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|none\\)?\\>\\)" ))
4019 ((match-end 11) ; class
4020 ;; Search back for matching class
4021 (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
4022 ((match-end 12) ; covergroup
4023 ;; Search back for matching covergroup
4024 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" )))
4026 (while (verilog-re-search-backward reg nil 'move)
4028 ((match-end 1) ; begin
4029 (setq nest (1- nest))
4032 ((match-end 2) ; end
4033 (setq nest (1+ nest)))))
4035 (throw 'nesting (verilog-calc-1)))
4039 ;; Return type of block and indent level.
4042 (if (> par 0) ; Unclosed Parenthesis
4043 (list 'cparenexp par)
4046 (list type (verilog-case-indent-level)))
4047 ((eq type 'statement)
4048 (list type (current-column)))
4052 (list type (verilog-current-indent-level))))))))
4054 (defun verilog-wai ()
4055 "Show matching nesting block for debugging."
4058 (let ((nesting (verilog-calc-1)))
4059 (message "You are at nesting %s" nesting))))
4061 (defun verilog-calc-1 ()
4063 (while (verilog-re-search-backward (concat "\\({\\|}\\|" verilog-indent-re "\\)") nil 'move)
4065 ((equal (char-after) ?\{)
4066 (if (verilog-at-constraint-p)
4067 (throw 'nesting 'block)))
4068 ((equal (char-after) ?\})
4070 (let ((there (verilog-at-close-constraint-p)))
4071 (if there (goto-char there))))
4073 ((looking-at verilog-beg-block-re-ordered)
4075 ((match-end 2) ; *sigh* could be "unique case" or "priority casex"
4076 (let ((here (point)))
4077 (verilog-beg-of-statement)
4078 (if (looking-at verilog-extended-case-re)
4079 (throw 'nesting 'case)
4081 (throw 'nesting 'case))
4083 ((match-end 4) ; *sigh* could be "disable fork"
4084 (let ((here (point)))
4085 (verilog-beg-of-statement)
4086 (if (looking-at verilog-disable-fork-re)
4087 t ; is disable fork, this is a normal statement
4088 (progn ; or is fork, starts a new block
4090 (throw 'nesting 'block)))))
4093 ;; need to consider typedef struct here...
4094 ((looking-at "\\<class\\|struct\\|function\\|task\\|property\\>")
4095 ; *sigh* These words have an optional prefix:
4096 ; extern {virtual|protected}? function a();
4097 ; assert property (p_1);
4098 ; typedef class foo;
4099 ; and we don't want to confuse this with
4104 (let ((here (point)))
4106 (verilog-beg-of-statement)
4107 (if (= (point) here)
4108 (throw 'nesting 'block)))))
4109 (t (throw 'nesting 'block))))
4111 ((looking-at verilog-end-block-re)
4112 (verilog-leap-to-head)
4113 (if (verilog-in-case-region-p)
4115 (verilog-leap-to-case-head)
4116 (if (looking-at verilog-case-re)
4117 (throw 'nesting 'case)))))
4119 ((looking-at (if (verilog-in-generate-region-p)
4120 verilog-defun-level-not-generate-re
4121 verilog-defun-level-re))
4122 (throw 'nesting 'defun))
4124 ((looking-at verilog-cpp-level-re)
4125 (throw 'nesting 'cpp))
4128 (throw 'nesting 'cpp))))
4129 (throw 'nesting 'cpp)))
4131 (defun verilog-calculate-indent-directive ()
4132 "Return indentation level for directive.
4133 For speed, the searcher looks at the last directive, not the indent
4134 of the appropriate enclosing block."
4135 (let ((base -1) ;; Indent of the line that determines our indentation
4136 (ind 0)) ;; Relative offset caused by other directives (like `endif on same line as `else)
4137 ;; Start at current location, scan back for another directive
4141 (while (and (< base 0)
4142 (verilog-re-search-backward verilog-directive-re nil t))
4143 (cond ((save-excursion (skip-chars-backward " \t") (bolp))
4144 (setq base (current-indentation))))
4145 (cond ((and (looking-at verilog-directive-end) (< base 0)) ;; Only matters when not at BOL
4146 (setq ind (- ind verilog-indent-level-directive)))
4147 ((and (looking-at verilog-directive-middle) (>= base 0)) ;; Only matters when at BOL
4148 (setq ind (+ ind verilog-indent-level-directive)))
4149 ((looking-at verilog-directive-begin)
4150 (setq ind (+ ind verilog-indent-level-directive)))))
4151 ;; Adjust indent to starting indent of critical line
4152 (setq ind (max 0 (+ ind base))))
4156 (skip-chars-forward " \t")
4157 (cond ((or (looking-at verilog-directive-middle)
4158 (looking-at verilog-directive-end))
4159 (setq ind (max 0 (- ind verilog-indent-level-directive))))))
4162 (defun verilog-leap-to-case-head ()
4165 (verilog-re-search-backward "\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" nil 'move)
4168 (setq nest (1- nest)))
4170 (setq nest (1+ nest)))
4175 (defun verilog-leap-to-head ()
4176 "Move point to the head of this block.
4177 Jump from end to matching begin, from endcase to matching case, and so on."
4182 ((looking-at "\\<end\\>")
4183 ;; 1: Search back for matching begin
4184 (setq reg (concat "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|"
4185 "\\(\\<endcase\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" )))
4186 ((looking-at "\\<endcase\\>")
4187 ;; 2: Search back for matching case
4188 (setq reg "\\(\\<randcase\\>\\|\\<case[xz]?\\>\\)\\|\\(\\<endcase\\>\\)" ))
4189 ((looking-at "\\<join\\(_any\\|_none\\)?\\>")
4190 ;; 3: Search back for matching fork
4191 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" ))
4192 ((looking-at "\\<endclass\\>")
4193 ;; 4: Search back for matching class
4194 (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
4195 ((looking-at "\\<endtable\\>")
4196 ;; 5: Search back for matching table
4197 (setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" ))
4198 ((looking-at "\\<endspecify\\>")
4199 ;; 6: Search back for matching specify
4200 (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
4201 ((looking-at "\\<endfunction\\>")
4202 ;; 7: Search back for matching function
4203 (setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" ))
4204 ((looking-at "\\<endgenerate\\>")
4205 ;; 8: Search back for matching generate
4206 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
4207 ((looking-at "\\<endtask\\>")
4208 ;; 9: Search back for matching task
4209 (setq reg "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)" ))
4210 ((looking-at "\\<endgroup\\>")
4211 ;; 10: Search back for matching covergroup
4212 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" ))
4213 ((looking-at "\\<endproperty\\>")
4214 ;; 11: Search back for matching property
4215 (setq reg "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)" ))
4216 ((looking-at "\\<endinterface\\>")
4217 ;; 12: Search back for matching interface
4218 (setq reg "\\(\\<interface\\>\\)\\|\\(\\<endinterface\\>\\)" ))
4219 ((looking-at "\\<endsequence\\>")
4220 ;; 12: Search back for matching sequence
4221 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)" ))
4222 ((looking-at "\\<endclocking\\>")
4223 ;; 12: Search back for matching clocking
4224 (setq reg "\\(\\<clocking\\)\\|\\(\\<endclocking\\>\\)" )))
4228 (while (verilog-re-search-backward reg nil 'move)
4230 ((match-end 1) ; begin
4231 (setq nest (1- nest))
4233 ;; Now previous line describes syntax
4238 ((match-end 2) ; end
4239 (setq nest (1+ nest)))
4241 ;; endcase, jump to case
4243 (setq nest (1+ nest))
4245 (setq reg "\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" ))
4247 ;; join, jump to fork
4249 (setq nest (1+ nest))
4251 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" ))
4254 (defun verilog-continued-line ()
4255 "Return true if this is a continued line.
4256 Set point to where line starts."
4257 (let ((continued 't))
4258 (if (eq 0 (forward-line -1))
4261 (verilog-backward-ws&directives)
4263 (setq continued nil)
4264 (while (and continued
4266 (skip-chars-backward " \t")
4268 (setq continued (verilog-backward-token)))))
4269 (setq continued nil))
4272 (defun verilog-backward-token ()
4273 "Step backward token, returning true if we are now at an end of line token."
4275 (verilog-backward-syntactic-ws)
4279 (;-- Anything ending in a ; is complete
4280 (= (preceding-char) ?\;)
4282 (; If a "}" is prefixed by a ";", then this is a complete statement
4283 ; i.e.: constraint foo { a = b; }
4284 (= (preceding-char) ?\})
4287 (verilog-at-close-constraint-p)))
4288 (;-- constraint foo { a = b }
4289 ; is a complete statement. *sigh*
4290 (= (preceding-char) ?\{)
4293 (not (verilog-at-constraint-p))))
4294 (;-- Could be 'case (foo)' or 'always @(bar)' which is complete
4295 ; also could be simply '@(foo)'
4297 ; (b, ... which ISN'T complete
4298 ;;;; Do we need this???
4299 (= (preceding-char) ?\))
4302 (backward-up-list 1)
4303 (verilog-backward-syntactic-ws)
4304 (let ((back (point)))
4307 ((looking-at "\\<\\(always\\(_latch\\|_ff\\|_comb\\)?\\|case\\(\\|[xz]\\)\\|for\\(\\|each\\|ever\\)\\|i\\(f\\|nitial\\)\\|repeat\\|while\\)\\>")
4308 (not (looking-at "\\<randcase\\>\\|\\<case[xz]?\\>[^:]")))
4312 ((= (preceding-char) ?\@)
4315 (verilog-backward-token)
4316 (not (looking-at "\\<\\(always\\(_latch\\|_ff\\|_comb\\)?\\|initial\\|while\\)\\>"))))
4317 ((= (preceding-char) ?\#)
4321 (;-- any of begin|initial|while are complete statements; 'begin : foo' is also complete
4325 ((looking-at "\\<else\\>")
4327 ((looking-at verilog-behavioral-block-beg-re)
4329 ((looking-at verilog-indent-re)
4334 (verilog-backward-syntactic-ws)
4336 ((= (preceding-char) ?\:)
4338 (verilog-backward-syntactic-ws)
4340 (if (looking-at verilog-nameable-item-re )
4343 ((= (preceding-char) ?\#)
4346 ((= (preceding-char) ?\`)
4354 (defun verilog-backward-syntactic-ws (&optional bound)
4355 "Backward skip over syntactic whitespace for Emacs 19.
4356 Optional BOUND limits search."
4358 (let* ((bound (or bound (point-min))) (here bound) )
4359 (if (< bound (point))
4361 (narrow-to-region bound (point))
4362 (while (/= here (point))
4364 (verilog-skip-backward-comments))))))
4367 (defun verilog-forward-syntactic-ws (&optional bound)
4368 "Forward skip over syntactic whitespace for Emacs 19.
4369 Optional BOUND limits search."
4371 (let* ((bound (or bound (point-max)))
4373 (if (> bound (point))
4375 (narrow-to-region (point) bound)
4376 (while (/= here (point))
4378 (forward-comment (buffer-size))))))))
4380 (defun verilog-backward-ws&directives (&optional bound)
4381 "Backward skip over syntactic whitespace and compiler directives for Emacs 19.
4382 Optional BOUND limits search."
4384 (let* ((bound (or bound (point-min)))
4387 (if (< bound (point))
4389 (let ((state (save-excursion (verilog-syntax-ppss))))
4391 ((nth 7 state) ;; in // comment
4392 (verilog-re-search-backward "//" nil 'move)
4393 (skip-chars-backward "/"))
4394 ((nth 4 state) ;; in /* */ comment
4395 (verilog-re-search-backward "/\*" nil 'move))))
4396 (narrow-to-region bound (point))
4397 (while (/= here (point))
4399 (verilog-skip-backward-comments)
4404 ((verilog-within-translate-off)
4405 (verilog-back-to-start-translate-off (point-min)))
4406 ((looking-at verilog-directive-re-1)
4410 (if p (goto-char p))))))))
4412 (defun verilog-forward-ws&directives (&optional bound)
4413 "Forward skip over syntactic whitespace and compiler directives for Emacs 19.
4414 Optional BOUND limits search."
4416 (let* ((bound (or bound (point-max)))
4419 (if (> bound (point))
4421 (let ((state (save-excursion (verilog-syntax-ppss))))
4423 ((nth 7 state) ;; in // comment
4424 (verilog-re-search-forward "//" nil 'move))
4425 ((nth 4 state) ;; in /* */ comment
4426 (verilog-re-search-forward "/\*" nil 'move))))
4427 (narrow-to-region (point) bound)
4428 (while (/= here (point))
4431 (forward-comment (buffer-size))
4434 (if (looking-at verilog-directive-re-1)
4437 (beginning-of-line 2))))))))
4439 (defun verilog-in-comment-p ()
4440 "Return true if in a star or // comment."
4441 (let ((state (save-excursion (verilog-syntax-ppss))))
4442 (or (nth 4 state) (nth 7 state))))
4444 (defun verilog-in-star-comment-p ()
4445 "Return true if in a star comment."
4446 (let ((state (save-excursion (verilog-syntax-ppss))))
4448 (nth 4 state) ; t if in a comment of style a // or b /**/
4450 (nth 7 state) ; t if in a comment of style b /**/
4453 (defun verilog-in-slash-comment-p ()
4454 "Return true if in a slash comment."
4455 (let ((state (save-excursion (verilog-syntax-ppss))))
4458 (defun verilog-in-comment-or-string-p ()
4459 "Return true if in a string or comment."
4460 (let ((state (save-excursion (verilog-syntax-ppss))))
4461 (or (nth 3 state) (nth 4 state) (nth 7 state)))) ; Inside string or comment)
4463 (defun verilog-in-escaped-name-p ()
4464 "Return true if in an escaped name."
4467 (skip-chars-backward "^ \t\n\f")
4468 (if (equal (char-after (point) ) ?\\ )
4472 (defun verilog-in-paren ()
4473 "Return true if in a parenthetical expression."
4474 (let ((state (save-excursion (verilog-syntax-ppss))))
4475 (> (nth 0 state) 0 )))
4477 (defun verilog-in-coverage ()
4478 "Return true if in a constraint or coverpoint expression."
4481 (if (verilog-in-paren)
4483 (backward-up-list 1)
4484 (verilog-at-constraint-p)
4487 (defun verilog-at-close-constraint-p ()
4488 "If at the } that closes a constraint or covergroup, return true."
4490 (equal (char-after) ?\})
4494 (verilog-backward-ws&directives)
4495 (if (equal (char-before) ?\;)
4499 (defun verilog-at-constraint-p ()
4500 "If at the { of a constraint or coverpoint definition, return true, moving point to constraint."
4503 (equal (char-after) ?\{)
4505 (progn (backward-char 1)
4506 (verilog-backward-ws&directives)
4507 (equal (char-before) ?\;))))
4509 (verilog-re-search-backward "\\<constraint\\|coverpoint\\|cross\\>" nil 'move)
4513 (defun verilog-parenthesis-depth ()
4514 "Return non zero if in parenthetical-expression."
4515 (save-excursion (nth 1 (verilog-syntax-ppss))))
4518 (defun verilog-skip-forward-comment-or-string ()
4519 "Return true if in a string or comment."
4520 (let ((state (save-excursion (verilog-syntax-ppss))))
4522 ((nth 3 state) ;Inside string
4523 (search-forward "\"")
4525 ((nth 7 state) ;Inside // comment
4528 ((nth 4 state) ;Inside any comment (hence /**/)
4529 (search-forward "*/"))
4533 (defun verilog-skip-backward-comment-or-string ()
4534 "Return true if in a string or comment."
4535 (let ((state (save-excursion (verilog-syntax-ppss))))
4537 ((nth 3 state) ;Inside string
4538 (search-backward "\"")
4540 ((nth 7 state) ;Inside // comment
4541 (search-backward "//")
4542 (skip-chars-backward "/")
4544 ((nth 4 state) ;Inside /* */ comment
4545 (search-backward "/*")
4550 (defun verilog-skip-backward-comments ()
4551 "Return true if a comment was skipped."
4555 (let ((state (save-excursion (verilog-syntax-ppss))))
4557 ((nth 7 state) ;Inside // comment
4558 (search-backward "//")
4559 (skip-chars-backward "/")
4560 (skip-chars-backward " \t\n\f")
4562 ((nth 4 state) ;Inside /* */ comment
4563 (search-backward "/*")
4564 (skip-chars-backward " \t\n\f")
4567 (= (char-before) ?\/)
4568 (= (char-before (1- (point))) ?\*))
4569 (goto-char (- (point) 2))
4572 (skip-chars-backward " \t\n\f")
4575 (defun verilog-skip-forward-comment-p ()
4576 "If in comment, move to end and return true."
4579 (setq state (save-excursion (verilog-syntax-ppss)))
4583 ((nth 7 state) ;Inside // comment
4587 ((nth 4 state) ;Inside any comment
4592 (defun verilog-indent-line-relative ()
4593 "Cheap version of indent line.
4594 Only look at a few lines to determine indent level."
4598 (if (looking-at "^[ \t]*$")
4599 (cond ;- A blank line; No need to be too smart.
4601 (setq indent-str (list 'cpp 0)))
4602 ((verilog-continued-line)
4603 (let ((sp1 (point)))
4604 (if (verilog-continued-line)
4608 (list 'statement (verilog-current-indent-level))))
4610 (setq indent-str (list 'block (verilog-current-indent-level)))))
4613 (setq indent-str (verilog-calculate-indent))))
4614 (progn (skip-chars-forward " \t")
4615 (setq indent-str (verilog-calculate-indent))))
4616 (verilog-do-indent indent-str)))
4618 (defun verilog-indent-line ()
4619 "Indent for special part of code."
4620 (verilog-do-indent (verilog-calculate-indent)))
4622 (defun verilog-do-indent (indent-str)
4623 (let ((type (car indent-str))
4624 (ind (car (cdr indent-str))))
4626 (; handle continued exp
4628 (let ((here (point)))
4629 (verilog-backward-syntactic-ws)
4632 (= (preceding-char) ?\,)
4633 (= (preceding-char) ?\])
4635 (verilog-beg-of-statement-1)
4636 (looking-at verilog-declaration-re)))
4641 (verilog-beg-of-statement-1)
4643 (if (looking-at verilog-declaration-re)
4644 (progn ;; we have multiple words
4645 (goto-char (match-end 0))
4646 (skip-chars-forward " \t")
4648 ((and verilog-indent-declaration-macros
4649 (= (following-char) ?\`))
4653 (skip-chars-forward " \t")))
4654 ((= (following-char) ?\[)
4657 (backward-up-list -1)
4658 (skip-chars-forward " \t"))))
4662 (+ (current-column) verilog-cexp-indent))))))
4664 (indent-line-to val)))
4665 ((= (preceding-char) ?\) )
4667 (let ((val (eval (cdr (assoc type verilog-indent-alist)))))
4668 (indent-line-to val)))
4672 (verilog-beg-of-statement-1)
4673 (if (and (< (point) here)
4674 (verilog-re-search-forward "=[ \\t]*" here 'move))
4675 (setq val (current-column))
4676 (setq val (eval (cdr (assoc type verilog-indent-alist)))))
4678 (indent-line-to val))))))
4680 (; handle inside parenthetical expressions
4681 (eq type 'cparenexp)
4682 (let ((val (save-excursion
4683 (backward-up-list 1)
4685 (skip-chars-forward " \t")
4687 (indent-line-to val)
4688 (if (and (not (verilog-in-struct-region-p))
4689 (looking-at verilog-declaration-re))
4690 (verilog-indent-declaration ind))))
4692 (;-- Handle the ends
4694 (looking-at verilog-end-block-re )
4695 (verilog-at-close-constraint-p))
4696 (let ((val (if (eq type 'statement)
4697 (- ind verilog-indent-level)
4699 (indent-line-to val)))
4701 (;-- Case -- maybe line 'em up
4702 (and (eq type 'case) (not (looking-at "^[ \t]*$")))
4705 ((looking-at "\\<endcase\\>")
4706 (indent-line-to ind))
4708 (let ((val (eval (cdr (assoc type verilog-indent-alist)))))
4709 (indent-line-to val))))))
4712 (and (eq type 'defun)
4713 (looking-at verilog-zero-indent-re))
4720 (looking-at verilog-declaration-re))
4721 (verilog-indent-declaration ind))
4723 (;-- Everything else
4725 (let ((val (eval (cdr (assoc type verilog-indent-alist)))))
4726 (indent-line-to val))))
4728 (if (looking-at "[ \t]+$")
4729 (skip-chars-forward " \t"))
4730 indent-str ; Return indent data
4733 (defun verilog-current-indent-level ()
4734 "Return the indent-level of the current statement."
4738 (setq par-pos (verilog-parenthesis-depth))
4742 (setq par-pos (verilog-parenthesis-depth)))
4743 (skip-chars-forward " \t")
4746 (defun verilog-case-indent-level ()
4747 "Return the indent-level of the current statement.
4748 Do not count named blocks or case-statements."
4750 (skip-chars-forward " \t")
4752 ((looking-at verilog-named-block-re)
4754 ((and (not (looking-at verilog-case-re))
4755 (looking-at "^[^:;]+[ \t]*:"))
4756 (verilog-re-search-forward ":" nil t)
4757 (skip-chars-forward " \t")
4760 (current-column)))))
4762 (defun verilog-indent-comment ()
4763 "Indent current line as comment."
4766 ((verilog-in-star-comment-p)
4768 (re-search-backward "/\\*" nil t)
4769 (1+(current-column))))
4774 (re-search-backward "//" nil t)
4775 (current-column))))))
4776 (indent-line-to stcol)
4779 (defun verilog-more-comment ()
4780 "Make more comment lines like the previous."
4784 ((verilog-in-star-comment-p)
4787 (re-search-backward "/\\*" nil t)
4788 (1+(current-column))))
4793 (re-search-backward "//" nil t)
4794 (current-column))))))
4800 (skip-chars-forward " \t")
4804 (defun verilog-comment-indent (&optional arg)
4805 "Return the column number the line should be indented to.
4806 ARG is ignored, for `comment-indent-function' compatibility."
4808 ((verilog-in-star-comment-p)
4810 (re-search-backward "/\\*" nil t)
4811 (1+(current-column))))
4816 (re-search-backward "//" nil t)
4817 (current-column)))))
4821 (defun verilog-pretty-declarations (&optional quiet)
4822 "Line up declarations around point."
4826 (verilog-beg-of-statement-1)
4827 (looking-at verilog-declaration-re))
4828 (let* ((m1 (make-marker))
4831 ;; Start of declaration range
4834 (verilog-beg-of-statement-1)
4835 (while (looking-at verilog-declaration-re)
4838 (verilog-backward-syntactic-ws)
4840 (verilog-beg-of-statement-1)) ;Ack, need to grok `define
4842 ;; End of declaration range
4846 (verilog-end-of-statement)
4847 (setq e (point)) ;Might be on last line
4848 (verilog-forward-syntactic-ws)
4849 (while (looking-at verilog-declaration-re)
4851 (verilog-end-of-statement)
4853 (verilog-forward-syntactic-ws))
4855 (edpos (set-marker (make-marker) end))
4860 (verilog-do-indent (verilog-calculate-indent))
4861 (verilog-forward-ws&directives)
4865 (if (and (not quiet)
4866 (> (- end start) 100))
4867 (message "Lining up declarations..(please stand by)"))
4868 ;; Get the beginning of line indent first
4869 (while (progn (setq e (marker-position edpos))
4872 ( (save-excursion (skip-chars-backward " \t")
4874 (verilog-forward-ws&directives)
4875 (indent-line-to base-ind)
4876 (verilog-forward-ws&directives)
4877 (verilog-re-search-forward "[ \t\n\f]" e 'move))
4880 (verilog-re-search-forward "[ \t\n\f]" e 'move)))
4883 ;; Now find biggest prefix
4884 (setq ind (verilog-get-lineup-indent start edpos))
4885 ;; Now indent each line.
4887 (while (progn (setq e (marker-position edpos))
4888 (setq r (- e (point)))
4891 (unless quiet (message "%d" r))
4893 ((or (and verilog-indent-declaration-macros
4894 (looking-at verilog-declaration-re-1-macro))
4895 (looking-at verilog-declaration-re-1-no-macro))
4896 (let ((p (match-end 0)))
4898 (if (verilog-re-search-forward "[[#`]" p 'move)
4902 (goto-char (marker-position m1))
4908 ((verilog-continued-line-1 start)
4910 (indent-line-to ind))
4911 (t ; Must be comment or white space
4913 (verilog-forward-ws&directives)
4916 (unless quiet (message ""))))))
4918 (defun verilog-pretty-expr (&optional quiet myre)
4919 "Line up expressions around point, or optional regexp MYRE."
4920 (interactive "sRegular Expression: ((<|:)?=) ")
4922 (if (or (eq myre nil)
4923 (string-equal myre ""))
4924 (setq myre "\\(<\\|:\\)?="))
4925 (setq myre (concat "\\(^[^;#:<=>]*\\)\\(" myre "\\)"))
4926 (let ((rexp(concat "^\\s-*" verilog-complete-reg)))
4928 (if (and (not (looking-at rexp ))
4930 (let* ((here (point))
4936 (verilog-backward-syntactic-ws)
4938 (while (and (not (looking-at rexp ))
4943 (verilog-backward-syntactic-ws)
4945 ) ;Ack, need to grok `define
4951 (setq e (point)) ;Might be on last line
4952 (verilog-forward-syntactic-ws)
4954 (while (and (not (looking-at rexp ))
4958 (verilog-forward-syntactic-ws)
4962 (edpos (set-marker (make-marker) end))
4966 (verilog-do-indent (verilog-calculate-indent))
4967 (if (and (not quiet)
4968 (> (- end start) 100))
4969 (message "Lining up expressions..(please stand by)"))
4971 ;; Set indent to minimum throughout region
4972 (while (< (point) (marker-position edpos))
4974 (verilog-just-one-space myre)
4976 (verilog-forward-syntactic-ws)
4979 ;; Now find biggest prefix
4980 (setq ind (verilog-get-lineup-indent-2 myre start edpos))
4982 ;; Now indent each line.
4984 (while (progn (setq e (marker-position edpos))
4985 (setq r (- e (point)))
4988 (if (not quiet) (message "%d" r))
4991 (goto-char (match-end 1))
4992 (if (not (verilog-parenthesis-depth)) ;; ignore parenthsized exprs
4993 (if (eq (char-after) ?=)
4994 (indent-to (1+ ind)) ; line up the = of the <= with surrounding =
4997 ((verilog-continued-line-1 start)
4999 (indent-line-to ind))
5000 (t ; Must be comment or white space
5002 (verilog-forward-ws&directives)
5006 (unless quiet (message ""))
5009 (defun verilog-just-one-space (myre)
5010 "Remove extra spaces around regular expression MYRE."
5012 (if (and (not(looking-at verilog-complete-reg))
5014 (let ((p1 (match-end 1))
5018 (if (looking-at "\\s-") (just-one-space))
5021 (if (looking-at "\\s-") (just-one-space))
5024 (defun verilog-indent-declaration (baseind)
5025 "Indent current lines as declaration.
5026 Line up the variable names based on previous declaration's indentation.
5027 BASEIND is the base indent to offset everything."
5029 (let ((pos (point-marker))
5030 (lim (save-excursion
5031 ;; (verilog-re-search-backward verilog-declaration-opener nil 'move)
5032 (verilog-re-search-backward "\\(\\<begin\\>\\)\\|\\(\\<module\\>\\)\\|\\(\\<task\\>\\)" nil 'move)
5038 (+ baseind (eval (cdr (assoc 'declaration verilog-indent-alist)))))
5039 (indent-line-to val)
5041 ;; Use previous declaration (in this module) as template.
5042 (if (or (memq 'all verilog-auto-lineup)
5043 (memq 'declaration verilog-auto-lineup))
5044 (if (verilog-re-search-backward
5045 (or (and verilog-indent-declaration-macros
5046 verilog-declaration-re-1-macro)
5047 verilog-declaration-re-1-no-macro) lim t)
5049 (goto-char (match-end 0))
5050 (skip-chars-forward " \t")
5051 (setq ind (current-column))
5055 (eval (cdr (assoc 'declaration verilog-indent-alist)))))
5056 (indent-line-to val)
5057 (if (and verilog-indent-declaration-macros
5058 (looking-at verilog-declaration-re-2-macro))
5059 (let ((p (match-end 0)))
5061 (if (verilog-re-search-forward "[[#`]" p 'move)
5065 (goto-char (marker-position m1))
5068 (if (/= (current-column) ind)
5072 (if (looking-at verilog-declaration-re-2-no-macro)
5073 (let ((p (match-end 0)))
5075 (if (verilog-re-search-forward "[[`#]" p 'move)
5079 (goto-char (marker-position m1))
5082 (if (/= (current-column) ind)
5085 (indent-to ind))))))))))
5088 (defun verilog-get-lineup-indent (b edpos)
5089 "Return the indent level that will line up several lines within the region.
5090 Region is defined by B and EDPOS."
5094 ;; Get rightmost position
5095 (while (progn (setq e (marker-position edpos))
5097 (if (verilog-re-search-forward
5098 (or (and verilog-indent-declaration-macros
5099 verilog-declaration-re-1-macro)
5100 verilog-declaration-re-1-no-macro) e 'move)
5102 (goto-char (match-end 0))
5103 (verilog-backward-syntactic-ws)
5104 (if (> (current-column) ind)
5105 (setq ind (current-column)))
5106 (goto-char (match-end 0)))))
5109 ;; No lineup-string found
5112 (skip-chars-backward " \t")
5113 (1+ (current-column))))))
5115 (defun verilog-get-lineup-indent-2 (myre b edpos)
5116 "Return the indent level that will line up several lines within the region."
5120 ;; Get rightmost position
5121 (while (progn (setq e (marker-position edpos))
5123 (if (and (verilog-re-search-forward myre e 'move)
5124 (not (verilog-parenthesis-depth))) ;; skip parenthsized exprs
5126 (goto-char (match-beginning 2))
5127 (verilog-backward-syntactic-ws)
5128 (if (> (current-column) ind)
5129 (setq ind (current-column)))
5130 (goto-char (match-end 0)))
5134 ;; No lineup-string found
5137 (skip-chars-backward " \t")
5138 (1+ (current-column))))))
5140 (defun verilog-comment-depth (type val)
5141 "A useful mode debugging aide. TYPE and VAL are comments for insertion."
5149 (if (re-search-backward " /\\* \[#-\]# \[a-zA-Z\]+ \[0-9\]+ ## \\*/" b t)
5151 (replace-match " /* -# ## */")
5155 (insert " /* ## ## */"))))
5158 (format "%s %d" type val))))
5164 (defvar verilog-str nil)
5165 (defvar verilog-all nil)
5166 (defvar verilog-pred nil)
5167 (defvar verilog-buffer-to-use nil)
5168 (defvar verilog-flag nil)
5169 (defvar verilog-toggle-completions nil
5170 "*True means \\<verilog-mode-map>\\[verilog-complete-word] should try all possible completions one by one.
5171 Repeated use of \\[verilog-complete-word] will show you all of them.
5172 Normally, when there is more than one possible completion,
5173 it displays a list of all possible completions.")
5176 (defvar verilog-type-keywords
5178 "and" "buf" "bufif0" "bufif1" "cmos" "defparam" "inout" "input"
5179 "integer" "localparam" "logic" "mailbox" "nand" "nmos" "nor" "not" "notif0"
5180 "notif1" "or" "output" "parameter" "pmos" "pull0" "pull1" "pullup"
5181 "rcmos" "real" "realtime" "reg" "rnmos" "rpmos" "rtran" "rtranif0"
5182 "rtranif1" "semaphore" "time" "tran" "tranif0" "tranif1" "tri" "tri0" "tri1"
5183 "triand" "trior" "trireg" "wand" "wire" "wor" "xnor" "xor"
5185 "*Keywords for types used when completing a word in a declaration or parmlist.
5186 \(Eg. integer, real, reg...)")
5188 (defvar verilog-cpp-keywords
5189 '("module" "macromodule" "primitive" "timescale" "define" "ifdef" "ifndef" "else"
5191 "*Keywords to complete when at first word of a line in declarative scope.
5192 \(Eg. initial, always, begin, assign.)
5193 The procedures and variables defined within the Verilog program
5194 will be completed at runtime and should not be added to this list.")
5196 (defvar verilog-defun-keywords
5199 "always" "always_comb" "always_ff" "always_latch" "assign"
5200 "begin" "end" "generate" "endgenerate" "module" "endmodule"
5201 "specify" "endspecify" "function" "endfunction" "initial" "final"
5202 "task" "endtask" "primitive" "endprimitive"
5204 verilog-type-keywords)
5205 "*Keywords to complete when at first word of a line in declarative scope.
5206 \(Eg. initial, always, begin, assign.)
5207 The procedures and variables defined within the Verilog program
5208 will be completed at runtime and should not be added to this list.")
5210 (defvar verilog-block-keywords
5212 "begin" "break" "case" "continue" "else" "end" "endfunction"
5213 "endgenerate" "endinterface" "endpackage" "endspecify" "endtask"
5214 "for" "fork" "if" "join" "join_any" "join_none" "repeat" "return"
5216 "*Keywords to complete when at first word of a line in behavioral scope.
5217 \(Eg. begin, if, then, else, for, fork.)
5218 The procedures and variables defined within the Verilog program
5219 will be completed at runtime and should not be added to this list.")
5221 (defvar verilog-tf-keywords
5222 '("begin" "break" "fork" "join" "join_any" "join_none" "case" "end" "endtask" "endfunction" "if" "else" "for" "while" "repeat")
5223 "*Keywords to complete when at first word of a line in a task or function.
5224 \(Eg. begin, if, then, else, for, fork.)
5225 The procedures and variables defined within the Verilog program
5226 will be completed at runtime and should not be added to this list.")
5228 (defvar verilog-case-keywords
5229 '("begin" "fork" "join" "join_any" "join_none" "case" "end" "endcase" "if" "else" "for" "repeat")
5230 "*Keywords to complete when at first word of a line in case scope.
5231 \(Eg. begin, if, then, else, for, fork.)
5232 The procedures and variables defined within the Verilog program
5233 will be completed at runtime and should not be added to this list.")
5235 (defvar verilog-separator-keywords
5236 '("else" "then" "begin")
5237 "*Keywords to complete when NOT standing at the first word of a statement.
5239 Variables and function names defined within the Verilog program
5240 will be completed at runtime and should not be added to this list.")
5242 (defun verilog-string-diff (str1 str2)
5243 "Return index of first letter where STR1 and STR2 differs."
5247 (if (or (> (1+ diff) (length str1))
5248 (> (1+ diff) (length str2)))
5250 (or (equal (aref str1 diff) (aref str2 diff))
5252 (setq diff (1+ diff))))))
5254 ;; Calculate all possible completions for functions if argument is `function',
5255 ;; completions for procedures if argument is `procedure' or both functions and
5256 ;; procedures otherwise.
5258 (defun verilog-func-completion (type)
5259 "Build regular expression for module/task/function names.
5260 TYPE is 'module, 'tf for task or function, or t if unknown."
5261 (if (string= verilog-str "")
5262 (setq verilog-str "[a-zA-Z_]"))
5263 (let ((verilog-str (concat (cond
5264 ((eq type 'module) "\\<\\(module\\)\\s +")
5265 ((eq type 'tf) "\\<\\(task\\|function\\)\\s +")
5266 (t "\\<\\(task\\|function\\|module\\)\\s +"))
5267 "\\<\\(" verilog-str "[a-zA-Z0-9_.]*\\)\\>"))
5270 (if (not (looking-at verilog-defun-re))
5271 (verilog-re-search-backward verilog-defun-re nil t))
5274 ;; Search through all reachable functions
5275 (goto-char (point-min))
5276 (while (verilog-re-search-forward verilog-str (point-max) t)
5277 (progn (setq match (buffer-substring (match-beginning 2)
5279 (if (or (null verilog-pred)
5280 (funcall verilog-pred match))
5281 (setq verilog-all (cons match verilog-all)))))
5282 (if (match-beginning 0)
5283 (goto-char (match-beginning 0)))))
5285 (defun verilog-get-completion-decl (end)
5286 "Macro for searching through current declaration (var, type or const)
5287 for matches of `str' and adding the occurrence tp `all' through point END."
5288 (let ((re (or (and verilog-indent-declaration-macros
5289 verilog-declaration-re-2-macro)
5290 verilog-declaration-re-2-no-macro))
5293 (while (and (< (point) end)
5294 (verilog-re-search-forward re end t))
5295 ;; Traverse current line
5296 (setq decl-end (save-excursion (verilog-declaration-end)))
5297 (while (and (verilog-re-search-forward verilog-symbol-re decl-end t)
5298 (not (match-end 1)))
5299 (setq match (buffer-substring (match-beginning 0) (match-end 0)))
5300 (if (string-match (concat "\\<" verilog-str) match)
5301 (if (or (null verilog-pred)
5302 (funcall verilog-pred match))
5303 (setq verilog-all (cons match verilog-all)))))
5307 (defun verilog-type-completion ()
5308 "Calculate all possible completions for types."
5309 (let ((start (point))
5311 ;; Search for all reachable type declarations
5312 (while (or (verilog-beg-of-defun)
5313 (setq goon (not goon)))
5315 (if (and (< start (prog1 (save-excursion (verilog-end-of-defun)
5318 (verilog-re-search-forward
5319 "\\<type\\>\\|\\<\\(begin\\|function\\|procedure\\)\\>"
5321 (not (match-end 1)))
5322 ;; Check current type declaration
5323 (verilog-get-completion-decl start))))))
5325 (defun verilog-var-completion ()
5326 "Calculate all possible completions for variables (or constants)."
5327 (let ((start (point)))
5328 ;; Search for all reachable var declarations
5329 (verilog-beg-of-defun)
5331 ;; Check var declarations
5332 (verilog-get-completion-decl start))))
5334 (defun verilog-keyword-completion (keyword-list)
5335 "Give list of all possible completions of keywords in KEYWORD-LIST."
5336 (mapcar '(lambda (s)
5337 (if (string-match (concat "\\<" verilog-str) s)
5338 (if (or (null verilog-pred)
5339 (funcall verilog-pred s))
5340 (setq verilog-all (cons s verilog-all)))))
5344 (defun verilog-completion (verilog-str verilog-pred verilog-flag)
5345 "Function passed to `completing-read', `try-completion' or `all-completions'.
5346 Called to get completion on VERILOG-STR. If VERILOG-PRED is non-nil, it
5347 must be a function to be called for every match to check if this should
5348 really be a match. If VERILOG-FLAG is t, the function returns a list of
5349 all possible completions. If VERILOG-FLAG is nil it returns a string,
5350 the longest possible completion, or t if VERILOG-STR is an exact match.
5351 If VERILOG-FLAG is 'lambda, the function returns t if VERILOG-STR is an
5352 exact match, nil otherwise."
5354 (let ((verilog-all nil))
5355 ;; Set buffer to use for searching labels. This should be set
5356 ;; within functions which use verilog-completions
5357 (set-buffer verilog-buffer-to-use)
5359 ;; Determine what should be completed
5360 (let ((state (car (verilog-calculate-indent))))
5361 (cond ((eq state 'defun)
5362 (save-excursion (verilog-var-completion))
5363 (verilog-func-completion 'module)
5364 (verilog-keyword-completion verilog-defun-keywords))
5366 ((eq state 'behavioral)
5367 (save-excursion (verilog-var-completion))
5368 (verilog-func-completion 'module)
5369 (verilog-keyword-completion verilog-defun-keywords))
5372 (save-excursion (verilog-var-completion))
5373 (verilog-func-completion 'tf)
5374 (verilog-keyword-completion verilog-block-keywords))
5377 (save-excursion (verilog-var-completion))
5378 (verilog-func-completion 'tf)
5379 (verilog-keyword-completion verilog-case-keywords))
5382 (save-excursion (verilog-var-completion))
5383 (verilog-func-completion 'tf)
5384 (verilog-keyword-completion verilog-tf-keywords))
5387 (save-excursion (verilog-var-completion))
5388 (verilog-keyword-completion verilog-cpp-keywords))
5390 ((eq state 'cparenexp)
5391 (save-excursion (verilog-var-completion)))
5394 (save-excursion (verilog-var-completion))
5395 (verilog-func-completion 'both)
5396 (verilog-keyword-completion verilog-separator-keywords))))
5398 ;; Now we have built a list of all matches. Give response to caller
5399 (verilog-completion-response))))
5401 (defun verilog-completion-response ()
5402 (cond ((or (equal verilog-flag 'lambda) (null verilog-flag))
5403 ;; This was not called by all-completions
5404 (if (null verilog-all)
5405 ;; Return nil if there was no matching label
5407 ;; Get longest string common in the labels
5408 (let* ((elm (cdr verilog-all))
5409 (match (car verilog-all))
5410 (min (length match))
5412 (if (string= match verilog-str)
5413 ;; Return t if first match was an exact match
5415 (while (not (null elm))
5416 ;; Find longest common string
5417 (if (< (setq tmp (verilog-string-diff match (car elm))) min)
5420 (setq match (substring match 0 min))))
5421 ;; Terminate with match=t if this is an exact match
5422 (if (string= (car elm) verilog-str)
5426 (setq elm (cdr elm)))))
5427 ;; If this is a test just for exact match, return nil ot t
5428 (if (and (equal verilog-flag 'lambda) (not (equal match 't)))
5431 ;; If flag is t, this was called by all-completions. Return
5432 ;; list of all possible completions
5436 (defvar verilog-last-word-numb 0)
5437 (defvar verilog-last-word-shown nil)
5438 (defvar verilog-last-completions nil)
5440 (defun verilog-complete-word ()
5441 "Complete word at current point.
5442 \(See also `verilog-toggle-completions', `verilog-type-keywords',
5443 and `verilog-separator-keywords'.)"
5445 (let* ((b (save-excursion (skip-chars-backward "a-zA-Z0-9_") (point)))
5446 (e (save-excursion (skip-chars-forward "a-zA-Z0-9_") (point)))
5447 (verilog-str (buffer-substring b e))
5448 ;; The following variable is used in verilog-completion
5449 (verilog-buffer-to-use (current-buffer))
5450 (allcomp (if (and verilog-toggle-completions
5451 (string= verilog-last-word-shown verilog-str))
5452 verilog-last-completions
5453 (all-completions verilog-str 'verilog-completion)))
5454 (match (if verilog-toggle-completions
5456 verilog-str (mapcar '(lambda (elm)
5457 (cons elm 0)) allcomp)))))
5458 ;; Delete old string
5461 ;; Toggle-completions inserts whole labels
5462 (if verilog-toggle-completions
5464 ;; Update entry number in list
5465 (setq verilog-last-completions allcomp
5466 verilog-last-word-numb
5467 (if (>= verilog-last-word-numb (1- (length allcomp)))
5469 (1+ verilog-last-word-numb)))
5470 (setq verilog-last-word-shown (elt allcomp verilog-last-word-numb))
5471 ;; Display next match or same string if no match was found
5472 (if (not (null allcomp))
5473 (insert "" verilog-last-word-shown)
5474 (insert "" verilog-str)
5475 (message "(No match)")))
5476 ;; The other form of completion does not necessarily do that.
5478 ;; Insert match if found, or the original string if no match
5479 (if (or (null match) (equal match 't))
5480 (progn (insert "" verilog-str)
5481 (message "(No match)"))
5483 ;; Give message about current status of completion
5484 (cond ((equal match 't)
5485 (if (not (null (cdr allcomp)))
5486 (message "(Complete but not unique)")
5487 (message "(Sole completion)")))
5488 ;; Display buffer if the current completion didn't help
5489 ;; on completing the label.
5490 ((and (not (null (cdr allcomp))) (= (length verilog-str)
5492 (with-output-to-temp-buffer "*Completions*"
5493 (display-completion-list allcomp))
5494 ;; Wait for a key press. Then delete *Completion* window
5495 (momentary-string-display "" (point))
5496 (delete-window (get-buffer-window (get-buffer "*Completions*")))
5499 (defun verilog-show-completions ()
5500 "Show all possible completions at current point."
5502 (let* ((b (save-excursion (skip-chars-backward "a-zA-Z0-9_") (point)))
5503 (e (save-excursion (skip-chars-forward "a-zA-Z0-9_") (point)))
5504 (verilog-str (buffer-substring b e))
5505 ;; The following variable is used in verilog-completion
5506 (verilog-buffer-to-use (current-buffer))
5507 (allcomp (if (and verilog-toggle-completions
5508 (string= verilog-last-word-shown verilog-str))
5509 verilog-last-completions
5510 (all-completions verilog-str 'verilog-completion))))
5511 ;; Show possible completions in a temporary buffer.
5512 (with-output-to-temp-buffer "*Completions*"
5513 (display-completion-list allcomp))
5514 ;; Wait for a key press. Then delete *Completion* window
5515 (momentary-string-display "" (point))
5516 (delete-window (get-buffer-window (get-buffer "*Completions*")))))
5519 (defun verilog-get-default-symbol ()
5520 "Return symbol around current point as a string."
5522 (buffer-substring (progn
5523 (skip-chars-backward " \t")
5524 (skip-chars-backward "a-zA-Z0-9_")
5527 (skip-chars-forward "a-zA-Z0-9_")
5530 (defun verilog-build-defun-re (str &optional arg)
5531 "Return function/task/module starting with STR as regular expression.
5532 With optional second ARG non-nil, STR is the complete name of the instruction."
5534 (concat "^\\(function\\|task\\|module\\)[ \t]+\\(" str "\\)\\>")
5535 (concat "^\\(function\\|task\\|module\\)[ \t]+\\(" str "[a-zA-Z0-9_]*\\)\\>")))
5537 (defun verilog-comp-defun (verilog-str verilog-pred verilog-flag)
5538 "Function passed to `completing-read', `try-completion' or `all-completions'.
5539 Returns a completion on any function name based on VERILOG-STR prefix. If
5540 VERILOG-PRED is non-nil, it must be a function to be called for every match
5541 to check if this should really be a match. If VERILOG-FLAG is t, the
5542 function returns a list of all possible completions. If it is nil it
5543 returns a string, the longest possible completion, or t if VERILOG-STR is
5544 an exact match. If VERILOG-FLAG is 'lambda, the function returns t if
5545 VERILOG-STR is an exact match, nil otherwise."
5547 (let ((verilog-all nil)
5550 ;; Set buffer to use for searching labels. This should be set
5551 ;; within functions which use verilog-completions
5552 (set-buffer verilog-buffer-to-use)
5554 (let ((verilog-str verilog-str))
5555 ;; Build regular expression for functions
5556 (if (string= verilog-str "")
5557 (setq verilog-str (verilog-build-defun-re "[a-zA-Z_]"))
5558 (setq verilog-str (verilog-build-defun-re verilog-str)))
5559 (goto-char (point-min))
5561 ;; Build a list of all possible completions
5562 (while (verilog-re-search-forward verilog-str nil t)
5563 (setq match (buffer-substring (match-beginning 2) (match-end 2)))
5564 (if (or (null verilog-pred)
5565 (funcall verilog-pred match))
5566 (setq verilog-all (cons match verilog-all)))))
5568 ;; Now we have built a list of all matches. Give response to caller
5569 (verilog-completion-response))))
5571 (defun verilog-goto-defun ()
5572 "Move to specified Verilog module/task/function.
5573 The default is a name found in the buffer around point.
5574 If search fails, other files are checked based on
5575 `verilog-library-flags'."
5577 (let* ((default (verilog-get-default-symbol))
5578 ;; The following variable is used in verilog-comp-function
5579 (verilog-buffer-to-use (current-buffer))
5580 (label (if (not (string= default ""))
5581 ;; Do completion with default
5582 (completing-read (concat "Label: (default " default ") ")
5583 'verilog-comp-defun nil nil "")
5584 ;; There is no default value. Complete without it
5585 (completing-read "Label: "
5586 'verilog-comp-defun nil nil "")))
5588 ;; If there was no response on prompt, use default value
5589 (if (string= label "")
5590 (setq label default))
5591 ;; Goto right place in buffer if label is not an empty string
5592 (or (string= label "")
5595 (goto-char (point-min))
5597 (re-search-forward (verilog-build-defun-re label t) nil t)))
5600 (beginning-of-line))
5602 (verilog-goto-defun-file label))))
5604 ;; Eliminate compile warning
5605 (defvar occur-pos-list)
5607 (defun verilog-showscopes ()
5608 "List all scopes in this module."
5610 (let ((buffer (current-buffer))
5614 (prevpos (point-min))
5615 (final-context-start (make-marker))
5616 (regexp "\\(module\\s-+\\w+\\s-*(\\)\\|\\(\\w+\\s-+\\w+\\s-*(\\)"))
5617 (with-output-to-temp-buffer "*Occur*"
5619 (message (format "Searching for %s ..." regexp))
5620 ;; Find next match, but give up if prev match was at end of buffer.
5621 (while (and (not (= prevpos (point-max)))
5622 (verilog-re-search-forward regexp nil t))
5623 (goto-char (match-beginning 0))
5626 (setq linenum (+ linenum (count-lines prevpos (point)))))
5627 (setq prevpos (point))
5628 (goto-char (match-end 0))
5629 (let* ((start (save-excursion
5630 (goto-char (match-beginning 0))
5631 (forward-line (if (< nlines 0) nlines (- nlines)))
5633 (end (save-excursion
5634 (goto-char (match-end 0))
5636 (forward-line (1+ nlines))
5639 (tag (format "%3d" linenum))
5640 (empty (make-string (length tag) ?\ ))
5643 (setq tem (make-marker))
5644 (set-marker tem (point))
5645 (set-buffer standard-output)
5646 (setq occur-pos-list (cons tem occur-pos-list))
5647 (or first (zerop nlines)
5648 (insert "--------\n"))
5650 (insert-buffer-substring buffer start end)
5651 (backward-char (- end start))
5652 (setq tem (if (< nlines 0) (- nlines) nlines))
5656 (setq tem (1- tem)))
5657 (let ((this-linenum linenum))
5658 (set-marker final-context-start
5659 (+ (point) (- (match-end 0) (match-beginning 0))))
5660 (while (< (point) final-context-start)
5662 (setq tag (format "%3d" this-linenum)))
5663 (insert tag ?:)))))))
5664 (set-buffer-modified-p nil))))
5667 ;; Highlight helper functions
5668 (defconst verilog-directive-regexp "\\(translate\\|coverage\\|lint\\)_")
5669 (defun verilog-within-translate-off ()
5670 "Return point if within translate-off region, else nil."
5671 (and (save-excursion
5673 (concat "//\\s-*.*\\s-*" verilog-directive-regexp "\\(on\\|off\\)\\>")
5675 (equal "off" (match-string 2))
5678 (defun verilog-start-translate-off (limit)
5679 "Return point before translate-off directive if before LIMIT, else nil."
5680 (when (re-search-forward
5681 (concat "//\\s-*.*\\s-*" verilog-directive-regexp "off\\>")
5683 (match-beginning 0)))
5685 (defun verilog-back-to-start-translate-off (limit)
5686 "Return point before translate-off directive if before LIMIT, else nil."
5687 (when (re-search-backward
5688 (concat "//\\s-*.*\\s-*" verilog-directive-regexp "off\\>")
5690 (match-beginning 0)))
5692 (defun verilog-end-translate-off (limit)
5693 "Return point after translate-on directive if before LIMIT, else nil."
5695 (re-search-forward (concat
5696 "//\\s-*.*\\s-*" verilog-directive-regexp "on\\>") limit t))
5698 (defun verilog-match-translate-off (limit)
5699 "Match a translate-off block, setting `match-data' and returning t, else nil.
5700 Bound search by LIMIT."
5701 (when (< (point) limit)
5702 (let ((start (or (verilog-within-translate-off)
5703 (verilog-start-translate-off limit)))
5704 (case-fold-search t))
5706 (let ((end (or (verilog-end-translate-off limit) limit)))
5707 (set-match-data (list start end))
5708 (goto-char end))))))
5710 (defun verilog-font-lock-match-item (limit)
5711 "Match, and move over, any declaration item after point.
5712 Bound search by LIMIT. Adapted from
5713 `font-lock-match-c-style-declaration-item-and-skip-to-next'."
5716 (narrow-to-region (point-min) limit)
5718 (when (looking-at "\\s-*\\([a-zA-Z]\\w*\\)")
5720 (goto-char (match-end 1))
5721 ;; move to next item
5722 (if (looking-at "\\(\\s-*,\\)")
5723 (goto-char (match-end 1))
5728 ;; Added by Subbu Meiyappan for Header
5730 (defun verilog-header ()
5731 "Insert a standard Verilog file header."
5733 (let ((start (point)))
5735 //-----------------------------------------------------------------------------
5737 // Project : <project>
5738 //-----------------------------------------------------------------------------
5739 // File : <filename>
5740 // Author : <author>
5741 // Created : <credate>
5742 // Last modified : <moddate>
5743 //-----------------------------------------------------------------------------
5746 //-----------------------------------------------------------------------------
5747 // Copyright (c) <copydate> by <company> This model is the confidential and
5748 // proprietary property of <company> and the possession or use of this
5749 // file requires a written license from <company>.
5750 //------------------------------------------------------------------------------
5751 // Modification history :
5753 //-----------------------------------------------------------------------------
5757 (search-forward "<filename>")
5758 (replace-match (buffer-name) t t)
5759 (search-forward "<author>") (replace-match "" t t)
5760 (insert (user-full-name))
5761 (insert " <" (user-login-name) "@" (system-name) ">")
5762 (search-forward "<credate>") (replace-match "" t t)
5763 (verilog-insert-date)
5764 (search-forward "<moddate>") (replace-match "" t t)
5765 (verilog-insert-date)
5766 (search-forward "<copydate>") (replace-match "" t t)
5767 (verilog-insert-year)
5768 (search-forward "<modhist>") (replace-match "" t t)
5769 (verilog-insert-date)
5770 (insert " : created")
5773 (setq string (read-string "title: "))
5774 (search-forward "<title>")
5775 (replace-match string t t)
5776 (setq string (read-string "project: " verilog-project))
5777 (setq verilog-project string)
5778 (search-forward "<project>")
5779 (replace-match string t t)
5780 (setq string (read-string "Company: " verilog-company))
5781 (setq verilog-company string)
5782 (search-forward "<company>")
5783 (replace-match string t t)
5784 (search-forward "<company>")
5785 (replace-match string t t)
5786 (search-forward "<company>")
5787 (replace-match string t t)
5788 (search-backward "<description>")
5789 (replace-match "" t t))))
5791 ;; verilog-header Uses the verilog-insert-date function
5793 (defun verilog-insert-date ()
5794 "Insert date from the system."
5797 (setq timpos (point))
5798 (if verilog-date-scientific-format
5799 (shell-command "date \"+@%Y/%m/%d\"" t)
5800 (shell-command "date \"+@%d.%m.%Y\"" t))
5801 (search-forward "@")
5802 (delete-region timpos (point))
5806 (defun verilog-insert-year ()
5807 "Insert year from the system."
5810 (setq timpos (point))
5811 (shell-command "date \"+@%Y\"" t)
5812 (search-forward "@")
5813 (delete-region timpos (point))
5819 ;; Signal list parsing
5822 ;; Elements of a signal list
5823 (defsubst verilog-sig-name (sig)
5825 (defsubst verilog-sig-bits (sig)
5827 (defsubst verilog-sig-comment (sig)
5829 (defsubst verilog-sig-memory (sig)
5831 (defsubst verilog-sig-enum (sig)
5833 (defsubst verilog-sig-signed (sig)
5835 (defsubst verilog-sig-type (sig)
5837 (defsubst verilog-sig-multidim (sig)
5839 (defsubst verilog-sig-multidim-string (sig)
5840 (if (verilog-sig-multidim sig)
5841 (let ((str "") (args (verilog-sig-multidim sig)))
5843 (setq str (concat str (car args)))
5844 (setq args (cdr args)))
5846 (defsubst verilog-sig-width (sig)
5847 (verilog-make-width-expression (verilog-sig-bits sig)))
5849 (defsubst verilog-alw-get-inputs (sigs)
5851 (defsubst verilog-alw-get-outputs (sigs)
5853 (defsubst verilog-alw-get-uses-delayed (sigs)
5856 (defun verilog-signals-not-in (in-list not-list)
5857 "Return list of signals in IN-LIST that aren't also in NOT-LIST.
5858 Also remove any duplicates in IN-LIST.
5859 Signals must be in standard (base vector) form."
5862 (if (not (or (assoc (car (car in-list)) not-list)
5863 (assoc (car (car in-list)) out-list)))
5864 (setq out-list (cons (car in-list) out-list)))
5865 (setq in-list (cdr in-list)))
5866 (nreverse out-list)))
5867 ;;(verilog-signals-not-in '(("A" "") ("B" "") ("DEL" "[2:3]")) '(("DEL" "") ("EXT" "")))
5869 (defun verilog-signals-in (in-list other-list)
5870 "Return list of signals in IN-LIST that are also in OTHER-LIST.
5871 Signals must be in standard (base vector) form."
5874 (if (assoc (car (car in-list)) other-list)
5875 (setq out-list (cons (car in-list) out-list)))
5876 (setq in-list (cdr in-list)))
5877 (nreverse out-list)))
5878 ;;(verilog-signals-in '(("A" "") ("B" "") ("DEL" "[2:3]")) '(("DEL" "") ("EXT" "")))
5880 (defun verilog-signals-memory (in-list)
5881 "Return list of signals in IN-LIST that are memoried (multidimensional)."
5884 (if (nth 3 (car in-list))
5885 (setq out-list (cons (car in-list) out-list)))
5886 (setq in-list (cdr in-list)))
5888 ;;(verilog-signals-memory '(("A" nil nil "[3:0]")) '(("B" nil nil nil)))
5890 (defun verilog-signals-sort-compare (a b)
5891 "Compare signal A and B for sorting."
5892 (string< (car a) (car b)))
5894 (defun verilog-signals-not-params (in-list)
5895 "Return list of signals in IN-LIST that aren't parameters or numeric constants."
5898 (unless (boundp (intern (concat "vh-" (car (car in-list)))))
5899 (setq out-list (cons (car in-list) out-list)))
5900 (setq in-list (cdr in-list)))
5901 (nreverse out-list)))
5903 (defun verilog-signals-combine-bus (in-list)
5904 "Return a list of signals in IN-LIST, with busses combined.
5905 Duplicate signals are also removed. For example A[2] and A[1] become A[2:1]."
5908 sig highbit lowbit ; Temp information about current signal
5909 sv-name sv-highbit sv-lowbit ; Details about signal we are forming
5910 sv-comment sv-memory sv-enum sv-signed sv-type sv-multidim sv-busstring
5912 ;; Shove signals so duplicated signals will be adjacent
5913 (setq in-list (sort in-list `verilog-signals-sort-compare))
5915 (setq sig (car in-list))
5916 ;; No current signal; form from existing details
5918 (setq sv-name (verilog-sig-name sig)
5921 sv-comment (verilog-sig-comment sig)
5922 sv-memory (verilog-sig-memory sig)
5923 sv-enum (verilog-sig-enum sig)
5924 sv-signed (verilog-sig-signed sig)
5925 sv-type (verilog-sig-type sig)
5926 sv-multidim (verilog-sig-multidim sig)
5929 ;; Extract bus details
5930 (setq bus (verilog-sig-bits sig))
5932 (or (and (string-match "\\[\\([0-9]+\\):\\([0-9]+\\)\\]" bus)
5933 (setq highbit (string-to-number (match-string 1 bus))
5934 lowbit (string-to-number
5935 (match-string 2 bus))))
5936 (and (string-match "\\[\\([0-9]+\\)\\]" bus)
5937 (setq highbit (string-to-number (match-string 1 bus))
5939 ;; Combine bits in bus
5941 (setq sv-highbit (max highbit sv-highbit)
5942 sv-lowbit (min lowbit sv-lowbit))
5943 (setq sv-highbit highbit
5946 ;; String, probably something like `preproc:0
5947 (setq sv-busstring bus)))
5948 ;; Peek ahead to next signal
5949 (setq in-list (cdr in-list))
5950 (setq sig (car in-list))
5951 (cond ((and sig (equal sv-name (verilog-sig-name sig)))
5952 ;; Combine with this signal
5953 (when (and sv-busstring
5954 (not (equal sv-busstring (verilog-sig-bits sig))))
5955 (when nil ;; Debugging
5956 (message (concat "Warning, can't merge into single bus "
5958 ", the AUTOs may be wrong")))
5959 (setq buswarn ", Couldn't Merge"))
5960 (if (verilog-sig-comment sig) (setq combo ", ..."))
5961 (setq sv-memory (or sv-memory (verilog-sig-memory sig))
5962 sv-enum (or sv-enum (verilog-sig-enum sig))
5963 sv-signed (or sv-signed (verilog-sig-signed sig))
5964 sv-type (or sv-type (verilog-sig-type sig))
5965 sv-multidim (or sv-multidim (verilog-sig-multidim sig))))
5966 ;; Doesn't match next signal, add to queue, zero in prep for next
5967 ;; Note sig may also be nil for the last signal in the list
5974 (concat "[" (int-to-string sv-highbit) ":"
5975 (int-to-string sv-lowbit) "]")))
5976 (concat sv-comment combo buswarn)
5977 sv-memory sv-enum sv-signed sv-type sv-multidim)
5983 (defun verilog-sig-tieoff (sig &optional no-width)
5984 "Return tieoff expression for given SIG, with appropriate width.
5985 Ignore width if optional NO-WIDTH is set."
5986 (let* ((width (if no-width nil (verilog-sig-width sig))))
5988 (if (and verilog-active-low-regexp
5989 (string-match verilog-active-low-regexp (verilog-sig-name sig)))
5993 ((string-match "^[0-9]+$" width)
5994 (concat width (if (verilog-sig-signed sig) "'sh0" "'h0")))
5996 (concat "{" width "{1'b0}}"))))))
5999 ;; Port/Wire/Etc Reading
6002 (defun verilog-read-inst-backward-name ()
6003 "Internal. Move point back to beginning of inst-name."
6004 (verilog-backward-open-paren)
6007 (verilog-re-search-backward-quick "\\()\\|\\b[a-zA-Z0-9`_\$]\\|\\]\\)" nil nil) ; ] isn't word boundary
6008 (cond ((looking-at ")")
6009 (verilog-backward-open-paren))
6010 (t (setq done t)))))
6011 (while (looking-at "\\]")
6012 (verilog-backward-open-bracket)
6013 (verilog-re-search-backward-quick "\\(\\b[a-zA-Z0-9`_\$]\\|\\]\\)" nil nil))
6014 (skip-chars-backward "a-zA-Z0-9`_$"))
6016 (defun verilog-read-inst-module ()
6017 "Return module_name when point is inside instantiation."
6019 (verilog-read-inst-backward-name)
6020 ;; Skip over instantiation name
6021 (verilog-re-search-backward-quick "\\(\\b[a-zA-Z0-9`_\$]\\|)\\)" nil nil) ; ) isn't word boundary
6022 ;; Check for parameterized instantiations
6023 (when (looking-at ")")
6024 (verilog-backward-open-paren)
6025 (verilog-re-search-backward-quick "\\b[a-zA-Z0-9`_\$]" nil nil))
6026 (skip-chars-backward "a-zA-Z0-9'_$")
6027 (looking-at "[a-zA-Z0-9`_\$]+")
6028 ;; Important: don't use match string, this must work with Emacs 19 font-lock on
6029 (buffer-substring-no-properties (match-beginning 0) (match-end 0))))
6031 (defun verilog-read-inst-name ()
6032 "Return instance_name when point is inside instantiation."
6034 (verilog-read-inst-backward-name)
6035 (looking-at "[a-zA-Z0-9`_\$]+")
6036 ;; Important: don't use match string, this must work with Emacs 19 font-lock on
6037 (buffer-substring-no-properties (match-beginning 0) (match-end 0))))
6039 (defun verilog-read-module-name ()
6040 "Return module name when after its ( or ;."
6042 (re-search-backward "[(;]")
6043 (verilog-re-search-backward-quick "\\b[a-zA-Z0-9`_\$]" nil nil)
6044 (skip-chars-backward "a-zA-Z0-9`_$")
6045 (looking-at "[a-zA-Z0-9`_\$]+")
6046 ;; Important: don't use match string, this must work with Emacs 19 font-lock on
6047 (buffer-substring-no-properties (match-beginning 0) (match-end 0))))
6049 (defun verilog-read-auto-params (num-param &optional max-param)
6050 "Return parameter list inside auto.
6051 Optional NUM-PARAM and MAX-PARAM check for a specific number of parameters."
6054 ;; /*AUTOPUNT("parameter", "parameter")*/
6055 (search-backward "(")
6056 (while (looking-at "(?\\s *\"\\([^\"]*\\)\"\\s *,?")
6057 (setq olist (cons (match-string 1) olist))
6058 (goto-char (match-end 0))))
6059 (or (eq nil num-param)
6060 (<= num-param (length olist))
6061 (error "%s: Expected %d parameters" (verilog-point-text) num-param))
6062 (if (eq max-param nil) (setq max-param num-param))
6063 (or (eq nil max-param)
6064 (>= max-param (length olist))
6065 (error "%s: Expected <= %d parameters" (verilog-point-text) max-param))
6068 (defun verilog-read-decls ()
6069 "Compute signal declaration information for the current module at point.
6070 Return a array of [outputs inouts inputs wire reg assign const]."
6071 (let ((end-mod-point (or (verilog-get-end-of-defun t) (point-max)))
6072 (functask 0) (paren 0) (sig-paren 0)
6073 sigs-in sigs-out sigs-inout sigs-wire sigs-reg sigs-assign sigs-const sigs-gparam
6074 vec expect-signal keywd newsig rvalue enum io signed typedefed multidim)
6076 (verilog-beg-of-defun)
6077 (setq sigs-const (verilog-read-auto-constants (point) end-mod-point))
6078 (while (< (point) end-mod-point)
6079 ;;(if dbg (setq dbg (cons (format "Pt %s Vec %s Kwd'%s'\n" (point) vec keywd) dbg)))
6082 (if (looking-at "[^\n]*synopsys\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
6083 (setq enum (match-string 1)))
6084 (search-forward "\n"))
6085 ((looking-at "/\\*")
6087 (if (looking-at "[^*]*synopsys\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
6088 (setq enum (match-string 1)))
6089 (or (search-forward "*/")
6090 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
6091 ((looking-at "(\\*")
6093 (or (looking-at "\\s-*)") ; It's a "always @ (*)"
6094 (search-forward "*)")
6095 (error "%s: Unmatched (* *), at char %d" (verilog-point-text) (point))))
6096 ((eq ?\" (following-char))
6097 (or (re-search-forward "[^\\]\"" nil t) ;; don't forward-char first, since we look for a non backslash first
6098 (error "%s: Unmatched quotes, at char %d" (verilog-point-text) (point))))
6099 ((eq ?\; (following-char))
6100 (setq vec nil io nil expect-signal nil newsig nil paren 0 rvalue nil)
6102 ((eq ?= (following-char))
6103 (setq rvalue t newsig nil)
6105 ((and (or rvalue sig-paren)
6106 (cond ((and (eq ?, (following-char))
6107 (eq paren sig-paren))
6111 ;; ,'s can occur inside {} & funcs
6112 ((looking-at "[{(]")
6113 (setq paren (1+ paren))
6116 ((looking-at "[})]")
6117 (setq paren (1- paren))
6119 (when (< paren sig-paren)
6120 (setq expect-signal nil)) ; ) that ends variables inside v2k arg list
6122 ((looking-at "\\s-*\\(\\[[^]]+\\]\\)")
6123 (goto-char (match-end 0))
6124 (cond (newsig ; Memory, not just width. Patch last signal added's memory (nth 3)
6125 (setcar (cdr (cdr (cdr newsig))) (match-string 1)))
6126 (vec ;; Multidimensional
6127 (setq multidim (cons vec multidim))
6128 (setq vec (verilog-string-replace-matches
6129 "\\s-+" "" nil nil (match-string 1))))
6131 (setq vec (verilog-string-replace-matches
6132 "\\s-+" "" nil nil (match-string 1))))))
6133 ;; Normal or escaped identifier -- note we remember the \ if escaped
6134 ((looking-at "\\s-*\\([a-zA-Z0-9`_$]+\\|\\\\[^ \t\n\f]+\\)")
6135 (goto-char (match-end 0))
6136 (setq keywd (match-string 1))
6137 (when (string-match "^\\\\" keywd)
6138 (setq keywd (concat keywd " "))) ;; Escaped ID needs space at end
6139 (cond ((equal keywd "input")
6140 (setq vec nil enum nil rvalue nil newsig nil signed nil typedefed nil multidim nil sig-paren paren
6141 expect-signal 'sigs-in io t))
6142 ((equal keywd "output")
6143 (setq vec nil enum nil rvalue nil newsig nil signed nil typedefed nil multidim nil sig-paren paren
6144 expect-signal 'sigs-out io t))
6145 ((equal keywd "inout")
6146 (setq vec nil enum nil rvalue nil newsig nil signed nil typedefed nil multidim nil sig-paren paren
6147 expect-signal 'sigs-inout io t))
6148 ((or (equal keywd "wire")
6150 (equal keywd "tri0")
6151 (equal keywd "tri1"))
6152 (unless io (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren
6153 expect-signal 'sigs-wire)))
6154 ((or (equal keywd "reg")
6155 (equal keywd "trireg"))
6156 (unless io (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren
6157 expect-signal 'sigs-reg)))
6158 ((equal keywd "assign")
6159 (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren
6160 expect-signal 'sigs-assign))
6161 ((or (equal keywd "supply0")
6162 (equal keywd "supply1")
6163 (equal keywd "supply")
6164 (equal keywd "localparam")
6165 (equal keywd "genvar"))
6166 (unless io (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren
6167 expect-signal 'sigs-const)))
6168 ((or (equal keywd "parameter"))
6169 (unless io (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren
6170 expect-signal 'sigs-gparam)))
6171 ((equal keywd "signed")
6172 (setq signed "signed"))
6173 ((or (equal keywd "function")
6174 (equal keywd "task"))
6175 (setq functask (1+ functask)))
6176 ((or (equal keywd "endfunction")
6177 (equal keywd "endtask"))
6178 (setq functask (1- functask)))
6179 ((or (equal keywd "`ifdef")
6180 (equal keywd "`ifndef"))
6182 ((verilog-typedef-name-p keywd)
6183 (setq typedefed keywd))
6187 (eq paren sig-paren)
6188 (not (member keywd verilog-keywords)))
6189 ;; Add new signal to expect-signal's variable
6190 (setq newsig (list keywd vec nil nil enum signed typedefed multidim))
6191 (set expect-signal (cons newsig
6192 (symbol-value expect-signal))))))
6195 (skip-syntax-forward " "))
6197 (vector (nreverse sigs-out)
6198 (nreverse sigs-inout)
6200 (nreverse sigs-wire)
6202 (nreverse sigs-assign)
6203 (nreverse sigs-const)
6204 (nreverse sigs-gparam)))))
6207 ;; Prevent compile warnings; these are let's, not globals
6208 ;; Do not remove the eval-when-compile
6209 ;; - we want a error when we are debugging this code if they are refed.
6215 (defsubst verilog-modi-get-decls (modi)
6216 (verilog-modi-cache-results modi 'verilog-read-decls))
6218 (defsubst verilog-modi-get-sub-decls (modi)
6219 (verilog-modi-cache-results modi 'verilog-read-sub-decls))
6222 ;; Signal reading for given module
6223 ;; Note these all take modi's - as returned from the
6224 ;; verilog-modi-current function.
6225 (defsubst verilog-modi-get-outputs (modi)
6226 (aref (verilog-modi-get-decls modi) 0))
6227 (defsubst verilog-modi-get-inouts (modi)
6228 (aref (verilog-modi-get-decls modi) 1))
6229 (defsubst verilog-modi-get-inputs (modi)
6230 (aref (verilog-modi-get-decls modi) 2))
6231 (defsubst verilog-modi-get-wires (modi)
6232 (aref (verilog-modi-get-decls modi) 3))
6233 (defsubst verilog-modi-get-regs (modi)
6234 (aref (verilog-modi-get-decls modi) 4))
6235 (defsubst verilog-modi-get-assigns (modi)
6236 (aref (verilog-modi-get-decls modi) 5))
6237 (defsubst verilog-modi-get-consts (modi)
6238 (aref (verilog-modi-get-decls modi) 6))
6239 (defsubst verilog-modi-get-gparams (modi)
6240 (aref (verilog-modi-get-decls modi) 7))
6241 (defsubst verilog-modi-get-sub-outputs (modi)
6242 (aref (verilog-modi-get-sub-decls modi) 0))
6243 (defsubst verilog-modi-get-sub-inouts (modi)
6244 (aref (verilog-modi-get-sub-decls modi) 1))
6245 (defsubst verilog-modi-get-sub-inputs (modi)
6246 (aref (verilog-modi-get-sub-decls modi) 2))
6249 (defun verilog-read-sub-decls-sig (submodi comment port sig vec multidim)
6250 "For `verilog-read-sub-decls-line', add a signal."
6253 (setq port (verilog-symbol-detick-denumber port))
6254 (setq sig (verilog-symbol-detick-denumber sig))
6255 (if sig (setq sig (verilog-string-replace-matches "^[---+~!|&]+" "" nil nil sig)))
6256 (if vec (setq vec (verilog-symbol-detick-denumber vec)))
6257 (if multidim (setq multidim (mapcar `verilog-symbol-detick-denumber multidim)))
6258 (unless (or (not sig)
6259 (equal sig "")) ;; Ignore .foo(1'b1) assignments
6260 (cond ((setq portdata (assoc port (verilog-modi-get-inouts submodi)))
6261 (setq sigs-inout (cons (list sig vec (concat "To/From " comment) nil nil
6262 (verilog-sig-signed portdata)
6263 (verilog-sig-type portdata)
6266 ((setq portdata (assoc port (verilog-modi-get-outputs submodi)))
6267 (setq sigs-out (cons (list sig vec (concat "From " comment) nil nil
6268 (verilog-sig-signed portdata)
6269 (verilog-sig-type portdata)
6272 ((setq portdata (assoc port (verilog-modi-get-inputs submodi)))
6273 (setq sigs-in (cons (list sig vec (concat "To " comment) nil nil
6274 (verilog-sig-signed portdata)
6275 (verilog-sig-type portdata)
6278 ;; (t -- warning pin isn't defined.) ; Leave for lint tool
6281 (defun verilog-read-sub-decls-line (submodi comment)
6282 "For `verilog-read-sub-decls', read lines of port defs until none match anymore.
6283 Return the list of signals found, using submodi to look up each port."
6284 (let (done port sig vec multidim)
6289 (cond ((looking-at "\\s-*\\.\\s-*\\([a-zA-Z0-9`_$]*\\)\\s-*(\\s-*")
6290 (setq port (match-string 1))
6291 (goto-char (match-end 0)))
6292 ((looking-at "\\s-*\\.\\s-*\\(\\\\[^ \t\n\f]*\\)\\s-*(\\s-*")
6293 (setq port (concat (match-string 1) " ")) ;; escaped id's need trailing space
6294 (goto-char (match-end 0)))
6295 ((looking-at "\\s-*\\.[^(]*(")
6296 (setq port nil) ;; skip this line
6297 (goto-char (match-end 0)))
6299 (setq port nil done t))) ;; Unknown, ignore rest of line
6303 (cond ((looking-at "\\(\\\\[^ \t\n\f]*\\)\\s-*)")
6304 (setq sig (concat (match-string 1) " ") ;; escaped id's need trailing space
6306 ; We intentionally ignore (non-escaped) signals with .s in them
6307 ; this prevents AUTOWIRE etc from noticing hierarchical sigs.
6308 ((looking-at "\\([^[({).]*\\)\\s-*)")
6309 (setq sig (verilog-string-remove-spaces (match-string 1))
6311 ((looking-at "\\([^[({).]*\\)\\s-*\\(\\[[^]]+\\]\\)\\s-*)")
6312 (setq sig (verilog-string-remove-spaces (match-string 1))
6313 vec (match-string 2)))
6314 ((looking-at "\\([^[({).]*\\)\\s-*/\\*\\(\\[[^*]+\\]\\)\\*/\\s-*)")
6315 (setq sig (verilog-string-remove-spaces (match-string 1))
6317 (let ((parse (match-string 2)))
6318 (while (string-match "^\\(\\[[^]]+\\]\\)\\(.*\\)$" parse)
6319 (when vec (setq multidim (cons vec multidim)))
6320 (setq vec (match-string 1 parse))
6321 (setq parse (match-string 2 parse)))))
6322 ((looking-at "{\\(.*\\)}.*\\s-*)")
6323 (let ((mlst (split-string (match-string 1) ","))
6325 (while (setq mstr (pop mlst))
6326 ;;(unless noninteractive (message "sig: %s " mstr))
6328 ((string-match "\\(['`a-zA-Z0-9_$]+\\)\\s-*$" mstr)
6329 (setq sig (verilog-string-remove-spaces (match-string 1 mstr))
6331 ;;(unless noninteractive (message "concat sig1: %s %s" mstr (match-string 1 mstr)))
6333 ((string-match "\\([^[({).]+\\)\\s-*\\(\\[[^]]+\\]\\)\\s-*" mstr)
6334 (setq sig (verilog-string-remove-spaces (match-string 1 mstr))
6335 vec (match-string 2 mstr))
6336 ;;(unless noninteractive (message "concat sig2: '%s' '%s' '%s'" mstr (match-string 1 mstr) (match-string 2 mstr)))
6341 (verilog-read-sub-decls-sig submodi comment port sig vec multidim))))
6345 (verilog-read-sub-decls-sig submodi comment port sig vec multidim))
6347 (forward-line 1)))))
6349 (defun verilog-read-sub-decls ()
6350 "Internally parse signals going to modules under this module.
6351 Return a array of [ outputs inouts inputs ] signals for modules that are
6352 instantiated in this module. For example if declare A A (.B(SIG)) and SIG
6353 is a output, then SIG will be included in the list.
6355 This only works on instantiations created with /*AUTOINST*/ converted by
6356 \\[verilog-auto-inst]. Otherwise, it would have to read in the whole
6357 component library to determine connectivity of the design.
6359 One work around for this problem is to manually create // Inputs and //
6360 Outputs comments above subcell signals, for example:
6368 (let ((end-mod-point (verilog-get-end-of-defun t))
6369 st-point end-inst-point
6370 ;; below 3 modified by verilog-read-sub-decls-line
6371 sigs-out sigs-inout sigs-in)
6372 (verilog-beg-of-defun)
6373 (while (verilog-re-search-forward "\\(/\\*AUTOINST\\*/\\|\\.\\*\\)" end-mod-point t)
6375 (goto-char (match-beginning 0))
6376 (unless (verilog-inside-comment-p)
6377 ;; Attempt to snarf a comment
6378 (let* ((submod (verilog-read-inst-module))
6379 (inst (verilog-read-inst-name))
6380 (comment (concat inst " of " submod ".v")) submodi)
6381 (when (setq submodi (verilog-modi-lookup submod t))
6382 ;; This could have used a list created by verilog-auto-inst
6383 ;; However I want it to be runnable even on user's manually added signals
6384 (verilog-backward-open-paren)
6385 (setq end-inst-point (save-excursion (forward-sexp 1) (point))
6387 (while (re-search-forward "\\s *(?\\s *// Outputs" end-inst-point t)
6388 (verilog-read-sub-decls-line submodi comment)) ;; Modifies sigs-out
6389 (goto-char st-point)
6390 (while (re-search-forward "\\s *// Inouts" end-inst-point t)
6391 (verilog-read-sub-decls-line submodi comment)) ;; Modifies sigs-inout
6392 (goto-char st-point)
6393 (while (re-search-forward "\\s *// Inputs" end-inst-point t)
6394 (verilog-read-sub-decls-line submodi comment)) ;; Modifies sigs-in
6396 ;; Combine duplicate bits
6397 ;;(setq rr (vector sigs-out sigs-inout sigs-in))
6398 (vector (verilog-signals-combine-bus (nreverse sigs-out))
6399 (verilog-signals-combine-bus (nreverse sigs-inout))
6400 (verilog-signals-combine-bus (nreverse sigs-in))))))
6402 (defun verilog-read-inst-pins ()
6403 "Return an array of [ pins ] for the current instantiation at point.
6404 For example if declare A A (.B(SIG)) then B will be included in the list."
6406 (let ((end-mod-point (point)) ;; presume at /*AUTOINST*/ point
6408 (verilog-backward-open-paren)
6409 (while (re-search-forward "\\.\\([^(,) \t\n\f]*\\)\\s-*" end-mod-point t)
6410 (setq pin (match-string 1))
6411 (unless (verilog-inside-comment-p)
6412 (setq pins (cons (list pin) pins))
6413 (when (looking-at "(")
6417 (defun verilog-read-arg-pins ()
6418 "Return an array of [ pins ] for the current argument declaration at point."
6420 (let ((end-mod-point (point)) ;; presume at /*AUTOARG*/ point
6422 (verilog-backward-open-paren)
6423 (while (re-search-forward "\\([a-zA-Z0-9$_.%`]+\\)" end-mod-point t)
6424 (setq pin (match-string 1))
6425 (unless (verilog-inside-comment-p)
6426 (setq pins (cons (list pin) pins))))
6429 (defun verilog-read-auto-constants (beg end-mod-point)
6430 "Return a list of AUTO_CONSTANTs used in the region from BEG to END-MOD-POINT."
6433 (let (sig-list tpl-end-pt)
6435 (while (re-search-forward "\\<AUTO_CONSTANT" end-mod-point t)
6436 (if (not (looking-at "\\s *("))
6437 (error "%s: Missing () after AUTO_CONSTANT" (verilog-point-text)))
6438 (search-forward "(" end-mod-point)
6439 (setq tpl-end-pt (save-excursion
6441 (forward-sexp 1) ;; Moves to paren that closes argdecl's
6444 (while (re-search-forward "\\s-*\\([\"a-zA-Z0-9$_.%`]+\\)\\s-*,*" tpl-end-pt t)
6445 (setq sig-list (cons (list (match-string 1) nil nil) sig-list))))
6448 (defun verilog-read-auto-lisp (start end)
6449 "Look for and evaluate a AUTO_LISP between START and END."
6452 (while (re-search-forward "\\<AUTO_LISP(" end t)
6454 (let* ((beg-pt (prog1 (point)
6455 (forward-sexp 1))) ;; Closing paren
6457 (eval-region beg-pt end-pt nil)))))
6460 ;; Prevent compile warnings; these are let's, not globals
6461 ;; Do not remove the eval-when-compile
6462 ;; - we want a error when we are debugging this code if they are refed.
6467 (defvar uses-delayed)
6468 (defvar vector-skip-list))
6470 (defun verilog-read-always-signals-recurse
6471 (exit-keywd rvalue ignore-next)
6472 "Recursive routine for parentheses/bracket matching.
6473 EXIT-KEYWD is expression to stop at, nil if top level.
6474 RVALUE is true if at right hand side of equal.
6475 IGNORE-NEXT is true to ignore next token, fake from inside case statement."
6476 (let* ((semi-rvalue (equal "endcase" exit-keywd)) ;; true if after a ; we are looking for rvalue
6477 keywd last-keywd sig-tolk sig-last-tolk gotend got-sig got-rvalue end-else-check)
6478 ;;(if dbg (setq dbg (concat dbg (format "Recursion %S %S %S\n" exit-keywd rvalue ignore-next))))
6479 (while (not (or (eobp) gotend))
6482 (search-forward "\n"))
6483 ((looking-at "/\\*")
6484 (or (search-forward "*/")
6485 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
6486 ((looking-at "(\\*")
6487 (or (looking-at "(\\*\\s-*)") ; It's a "always @ (*)"
6488 (search-forward "*)")
6489 (error "%s: Unmatched (* *), at char %d" (verilog-point-text) (point))))
6490 (t (setq keywd (buffer-substring-no-properties
6492 (save-excursion (when (eq 0 (skip-chars-forward "a-zA-Z0-9$_.%`"))
6495 sig-last-tolk sig-tolk
6497 ;;(if dbg (setq dbg (concat dbg (format "\tPt=%S %S\trv=%S in=%S ee=%S\n" (point) keywd rvalue ignore-next end-else-check))))
6500 (or (re-search-forward "[^\\]\"" nil t)
6501 (error "%s: Unmatched quotes, at char %d" (verilog-point-text) (point))))
6502 ;; else at top level loop, keep parsing
6503 ((and end-else-check (equal keywd "else"))
6504 ;;(if dbg (setq dbg (concat dbg (format "\tif-check-else %s\n" keywd))))
6505 ;; no forward movement, want to see else in lower loop
6506 (setq end-else-check nil))
6507 ;; End at top level loop
6508 ((and end-else-check (looking-at "[^ \t\n\f]"))
6509 ;;(if dbg (setq dbg (concat dbg (format "\tif-check-else-other %s\n" keywd))))
6512 ((and exit-keywd (equal keywd exit-keywd))
6514 (forward-char (length keywd)))
6515 ;; Standard tokens...
6517 (setq ignore-next nil rvalue semi-rvalue)
6518 ;; Final statement at top level loop?
6519 (when (not exit-keywd)
6520 ;;(if dbg (setq dbg (concat dbg (format "\ttop-end-check %s\n" keywd))))
6521 (setq end-else-check t))
6524 (if (looking-at "'s?[hdxbo][0-9a-fA-F_xz? \t]*")
6525 (goto-char (match-end 0))
6527 ((equal keywd ":") ;; Case statement, begin/end label, x?y:z
6528 (cond ((equal "endcase" exit-keywd) ;; case x: y=z; statement next
6529 (setq ignore-next nil rvalue nil))
6530 ((equal "?" exit-keywd) ;; x?y:z rvalue
6532 (got-sig ;; label: statement
6533 (setq ignore-next nil rvalue semi-rvalue got-sig nil))
6534 ((not rvalue) ;; begin label
6535 (setq ignore-next t rvalue nil)))
6538 (if (eq (char-before) ?< )
6539 (setq uses-delayed 1))
6540 (setq ignore-next nil rvalue t)
6544 (verilog-read-always-signals-recurse ":" rvalue nil))
6547 (verilog-read-always-signals-recurse "]" t nil))
6550 (cond (sig-last-tolk ;; Function call; zap last signal
6551 (setq got-sig nil)))
6552 (cond ((equal last-keywd "for")
6553 (verilog-read-always-signals-recurse ";" nil nil)
6554 (verilog-read-always-signals-recurse ";" t nil)
6555 (verilog-read-always-signals-recurse ")" nil nil))
6556 (t (verilog-read-always-signals-recurse ")" t nil))))
6557 ((equal keywd "begin")
6558 (skip-syntax-forward "w_")
6559 (verilog-read-always-signals-recurse "end" nil nil)
6560 ;;(if dbg (setq dbg (concat dbg (format "\tgot-end %s\n" exit-keywd))))
6561 (setq ignore-next nil rvalue semi-rvalue)
6562 (if (not exit-keywd) (setq end-else-check t)))
6563 ((or (equal keywd "case")
6564 (equal keywd "casex")
6565 (equal keywd "casez"))
6566 (skip-syntax-forward "w_")
6567 (verilog-read-always-signals-recurse "endcase" t nil)
6568 (setq ignore-next nil rvalue semi-rvalue)
6569 (if (not exit-keywd) (setq gotend t))) ;; top level begin/end
6570 ((string-match "^[$`a-zA-Z_]" keywd) ;; not exactly word constituent
6571 (cond ((or (equal keywd "`ifdef")
6572 (equal keywd "`ifndef"))
6573 (setq ignore-next t))
6575 (member keywd verilog-keywords)
6576 (string-match "^\\$" keywd)) ;; PLI task
6577 (setq ignore-next nil))
6579 (setq keywd (verilog-symbol-detick-denumber keywd))
6581 (if got-rvalue (setq sigs-in (cons got-sig sigs-in))
6582 (setq sigs-out (cons got-sig sigs-out)))
6583 ;;(if dbg (setq dbg (concat dbg (format "\t\tgot-sig=%S rv=%S\n" got-sig got-rvalue))))
6585 (setq got-rvalue rvalue
6586 got-sig (if (or (not keywd)
6587 (assoc keywd (if got-rvalue sigs-in sigs-out)))
6588 nil (list keywd nil nil))
6590 (skip-chars-forward "a-zA-Z0-9$_.%`"))
6593 ;; End of non-comment token
6594 (setq last-keywd keywd)))
6595 (skip-syntax-forward " "))
6596 ;; Append the final pending signal
6598 (if got-rvalue (setq sigs-in (cons got-sig sigs-in))
6599 (setq sigs-out (cons got-sig sigs-out)))
6600 ;;(if dbg (setq dbg (concat dbg (format "\t\tgot-sig=%S rv=%S\n" got-sig got-rvalue))))
6602 ;;(if dbg (setq dbg (concat dbg (format "ENDRecursion %s\n" exit-keywd))))
6605 (defun verilog-read-always-signals ()
6606 "Parse always block at point and return list of (outputs inout inputs)."
6611 uses-delayed) ;; Found signal/rvalue; push if not function
6612 (search-forward ")")
6613 (verilog-read-always-signals-recurse nil nil nil)
6614 ;;(if dbg (save-excursion (set-buffer (get-buffer-create "*vl-dbg*")) (delete-region (point-min) (point-max)) (insert dbg) (setq dbg "")))
6615 ;; Return what was found
6616 (list sigs-out nil sigs-in uses-delayed))))
6618 (defun verilog-read-instants ()
6619 "Parse module at point and return list of ( ( file instance ) ... )."
6620 (verilog-beg-of-defun)
6621 (let* ((end-mod-point (verilog-get-end-of-defun t))
6623 (instants-list nil))
6625 (while (< (point) end-mod-point)
6626 ;; Stay at level 0, no comments
6628 (setq state (parse-partial-sexp (point) end-mod-point 0 t nil))
6629 (or (> (car state) 0) ; in parens
6630 (nth 5 state) ; comment
6634 (if (looking-at "^\\s-*\\([a-zA-Z0-9`_$]+\\)\\s-+\\([a-zA-Z0-9`_$]+\\)\\s-*(")
6635 ;;(if (looking-at "^\\(.+\\)$")
6636 (let ((module (match-string 1))
6637 (instant (match-string 2)))
6638 (if (not (member module verilog-keywords))
6639 (setq instants-list (cons (list module instant) instants-list)))))
6644 (defun verilog-read-auto-template (module)
6645 "Look for a auto_template for the instantiation of the given MODULE.
6646 If found returns the signal name connections. Return REGEXP and
6647 list of ( (signal_name connection_name)... )."
6650 (let ((tpl-regexp "\\([0-9]+\\)")
6653 tpl-sig-list tpl-wild-list tpl-end-pt rep)
6655 (re-search-backward (concat "^\\s-*/?\\*?\\s-*" module "\\s-+AUTO_TEMPLATE") nil t)
6657 (goto-char (point-min))
6658 (re-search-forward (concat "^\\s-*/?\\*?\\s-*" module "\\s-+AUTO_TEMPLATE") nil t)))
6659 (goto-char (match-end 0))
6661 ;; We reserve @"..." for future lisp expressions that evaluate once-per-AUTOINST
6662 (when (looking-at "\\s-*\"\\([^\"]*)\\)\"")
6663 (setq tpl-regexp (match-string 1))
6664 (goto-char (match-end 0)))
6665 (search-forward "(")
6666 ;; Parse lines in the template
6667 (when verilog-auto-inst-template-numbers
6669 (goto-char (point-min))
6670 (while (search-forward "AUTO_TEMPLATE" nil t)
6671 (setq templateno (1+ templateno)))))
6672 (setq tpl-end-pt (save-excursion
6674 (forward-sexp 1) ;; Moves to paren that closes argdecl's
6678 (while (< (point) tpl-end-pt)
6679 (cond ((looking-at "\\s-*\\.\\([a-zA-Z0-9`_$]+\\)\\s-*(\\(.*\\))\\s-*\\(,\\|)\\s-*;\\)")
6680 (setq tpl-sig-list (cons (list
6681 (match-string-no-properties 1)
6682 (match-string-no-properties 2)
6685 (goto-char (match-end 0)))
6688 ;; Regexp bug in XEmacs disallows ][ inside [], and wants + last
6689 "\\s-*\\.\\(\\([a-zA-Z0-9`_$+@^.*?|---]+\\|[][]\\|\\\\[()|]\\)+\\)\\s-*(\\(.*\\))\\s-*\\(,\\|)\\s-*;\\)")
6690 (setq rep (match-string-no-properties 3))
6691 (goto-char (match-end 0))
6695 (verilog-string-replace-matches "@" "\\\\([0-9]+\\\\)" nil nil
6701 ((looking-at "[ \t\f]+")
6702 (goto-char (match-end 0)))
6704 (setq lineno (1+ lineno))
6705 (goto-char (match-end 0)))
6707 (search-forward "\n"))
6708 ((looking-at "/\\*")
6710 (or (search-forward "*/")
6711 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
6713 (error "%s: AUTO_TEMPLATE parsing error: %s"
6714 (verilog-point-text)
6715 (progn (looking-at ".*$") (match-string 0))))))
6718 (list tpl-sig-list tpl-wild-list)))
6719 ;; If no template found
6720 (t (vector tpl-regexp nil))))))
6721 ;;(progn (find-file "auto-template.v") (verilog-read-auto-template "ptl_entry"))
6723 (defun verilog-set-define (defname defvalue &optional buffer enumname)
6724 "Set the definition DEFNAME to the DEFVALUE in the given BUFFER.
6725 Optionally associate it with the specified enumeration ENUMNAME."
6727 (set-buffer (or buffer (current-buffer)))
6728 (let ((mac (intern (concat "vh-" defname))))
6729 ;;(message "Define %s=%s" defname defvalue) (sleep-for 1)
6730 ;; Need to define to a constant if no value given
6731 (set (make-variable-buffer-local mac)
6732 (if (equal defvalue "") "1" defvalue)))
6734 (let ((enumvar (intern (concat "venum-" enumname))))
6735 ;;(message "Define %s=%s" defname defvalue) (sleep-for 1)
6736 (make-variable-buffer-local enumvar)
6737 (add-to-list enumvar defname)))))
6739 (defun verilog-read-defines (&optional filename recurse subcall)
6740 "Read `defines and parameters for the current file, or optional FILENAME.
6741 If the filename is provided, `verilog-library-flags' will be used to
6742 resolve it. If optional RECURSE is non-nil, recurse through `includes.
6744 Parameters must be simple assignments to constants, or have their own
6745 \"parameter\" label rather than a list of parameters. Thus:
6747 parameter X = 5, Y = 10; // Ok
6748 parameter X = {1'b1, 2'h2}; // Ok
6749 parameter X = {1'b1, 2'h2}, Y = 10; // Bad, make into 2 parameter lines
6751 Defines must be simple text substitutions, one on a line, starting
6752 at the beginning of the line. Any ifdefs or multiline comments around the
6755 Defines are stored inside Emacs variables using the name vh-{definename}.
6757 This function is useful for setting vh-* variables. The file variables
6758 feature can be used to set defines that `verilog-mode' can see; put at the
6759 *END* of your file something like:
6762 // vh-macro:\"macro_definition\"
6765 If macros are defined earlier in the same file and you want their values,
6766 you can read them automatically (provided `enable-local-eval' is on):
6769 // eval:(verilog-read-defines)
6770 // eval:(verilog-read-defines \"group_standard_includes.v\")
6773 Note these are only read when the file is first visited, you must use
6774 \\[find-alternate-file] RET to have these take effect after editing them!
6776 If you want to disable the \"Process `eval' or hook local variables\"
6777 warning message, you need to add to your .emacs file:
6779 (setq enable-local-eval t)"
6780 (let ((origbuf (current-buffer)))
6782 (unless subcall (verilog-getopt-flags))
6784 (let ((fns (verilog-library-filenames filename (buffer-file-name))))
6786 (set-buffer (find-file-noselect (car fns)))
6787 (error (concat (verilog-point-text)
6788 ": Can't find verilog-read-defines file: " filename)))))
6790 (goto-char (point-min))
6791 (while (re-search-forward "^\\s-*`include\\s-+\\([^ \t\n\f]+\\)" nil t)
6792 (let ((inc (verilog-string-replace-matches "\"" "" nil nil (match-string-no-properties 1))))
6793 (unless (verilog-inside-comment-p)
6794 (verilog-read-defines inc recurse t)))))
6796 ;; note we don't use verilog-re... it's faster this way, and that
6797 ;; function has problems when comments are at the end of the define
6798 (goto-char (point-min))
6799 (while (re-search-forward "^\\s-*`define\\s-+\\([a-zA-Z0-9_$]+\\)\\s-+\\(.*\\)$" nil t)
6800 (let ((defname (match-string-no-properties 1))
6801 (defvalue (match-string-no-properties 2)))
6802 (setq defvalue (verilog-string-replace-matches "\\s-*/[/*].*$" "" nil nil defvalue))
6803 (verilog-set-define defname defvalue origbuf)))
6804 ;; Hack: Read parameters
6805 (goto-char (point-min))
6806 (while (re-search-forward
6807 "^\\s-*\\(parameter\\|localparam\\)\\(\\(\\s-*\\[[^]]*\\]\\|\\)\\s-+\\([a-zA-Z0-9_$]+\\)\\s-*=\\s-*\\([^;,]*\\),?\\|\\)\\s-*" nil t)
6808 (let ((var (match-string-no-properties 4))
6809 (val (match-string-no-properties 5))
6811 ;; The primary way of getting defines is verilog-read-decls
6812 ;; However, that isn't called yet for included files, so we'll add another scheme
6813 (if (looking-at "[^\n]*synopsys\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
6814 (setq enumname (match-string-no-properties 1)))
6816 (verilog-set-define var val origbuf enumname))
6817 (forward-comment 999)
6818 (while (looking-at "\\s-*,?\\s-*\\([a-zA-Z0-9_$]+\\)\\s-*=\\s-*\\([^;,]*\\),?\\s-*")
6819 (verilog-set-define (match-string-no-properties 1) (match-string-no-properties 2) origbuf enumname)
6820 (goto-char (match-end 0))
6821 (forward-comment 999)))))))
6823 (defun verilog-read-includes ()
6824 "Read `includes for the current file.
6825 This will find all of the `includes which are at the beginning of lines,
6826 ignoring any ifdefs or multiline comments around them.
6827 `verilog-read-defines' is then performed on the current and each included
6830 It is often useful put at the *END* of your file something like:
6833 // eval:(verilog-read-defines)
6834 // eval:(verilog-read-includes)
6837 Note includes are only read when the file is first visited, you must use
6838 \\[find-alternate-file] RET to have these take effect after editing them!
6840 It is good to get in the habit of including all needed files in each .v
6841 file that needs it, rather than waiting for compile time. This will aid
6842 this process, Verilint, and readability. To prevent defining the same
6843 variable over and over when many modules are compiled together, put a test
6844 around the inside each include file:
6847 `ifdef _FOO_V // include if not already included
6850 ... contents of file
6852 ;;slow: (verilog-read-defines nil t))
6854 (verilog-getopt-flags)
6855 (goto-char (point-min))
6856 (while (re-search-forward "^\\s-*`include\\s-+\\([^ \t\n\f]+\\)" nil t)
6857 (let ((inc (verilog-string-replace-matches "\"" "" nil nil (match-string 1))))
6858 (verilog-read-defines inc nil t)))))
6860 (defun verilog-read-signals (&optional start end)
6861 "Return a simple list of all possible signals in the file.
6862 Bounded by optional region from START to END. Overly aggressive but fast.
6863 Some macros and such are also found and included. For dinotrace.el."
6864 (let (sigs-all keywd)
6865 (progn;save-excursion
6866 (goto-char (or start (point-min)))
6867 (setq end (or end (point-max)))
6868 (while (re-search-forward "[\"/a-zA-Z_.%`]" end t)
6872 (search-forward "\n"))
6873 ((looking-at "/\\*")
6874 (search-forward "*/"))
6875 ((looking-at "(\\*")
6876 (or (looking-at "(\\*\\s-*)") ; It's a "always @ (*)"
6877 (search-forward "*)")))
6878 ((eq ?\" (following-char))
6879 (re-search-forward "[^\\]\"")) ;; don't forward-char first, since we look for a non backslash first
6880 ((looking-at "\\s-*\\([a-zA-Z0-9$_.%`]+\\)")
6881 (goto-char (match-end 0))
6882 (setq keywd (match-string-no-properties 1))
6883 (or (member keywd verilog-keywords)
6884 (member keywd sigs-all)
6885 (setq sigs-all (cons keywd sigs-all))))
6886 (t (forward-char 1))))
6891 ;; Argument file parsing
6894 (defun verilog-getopt (arglist)
6895 "Parse -f, -v etc arguments in ARGLIST list or string."
6896 (unless (listp arglist) (setq arglist (list arglist)))
6897 (let ((space-args '())
6899 ;; Split on spaces, so users can pass whole command lines
6901 (setq arg (car arglist)
6902 arglist (cdr arglist))
6903 (while (string-match "^\\([^ \t\n\f]+\\)[ \t\n\f]*\\(.*$\\)" arg)
6904 (setq space-args (append space-args
6905 (list (match-string-no-properties 1 arg))))
6906 (setq arg (match-string 2 arg))))
6909 (setq arg (car space-args)
6910 space-args (cdr space-args))
6914 (setq next-param arg))
6916 (setq next-param arg))
6918 (setq next-param arg))
6919 ;; +libext+(ext1)+(ext2)...
6920 ((string-match "^\\+libext\\+\\(.*\\)" arg)
6921 (setq arg (match-string 1 arg))
6922 (while (string-match "\\([^+]+\\)\\+?\\(.*\\)" arg)
6923 (verilog-add-list-unique `verilog-library-extensions
6924 (match-string 1 arg))
6925 (setq arg (match-string 2 arg))))
6927 ((or (string-match "^-D\\([^+=]*\\)[+=]\\(.*\\)" arg) ;; -Ddefine=val
6928 (string-match "^-D\\([^+=]*\\)\\(\\)" arg) ;; -Ddefine
6929 (string-match "^\\+define\\([^+=]*\\)[+=]\\(.*\\)" arg) ;; +define+val
6930 (string-match "^\\+define\\([^+=]*\\)\\(\\)" arg)) ;; +define+define
6931 (verilog-set-define (match-string 1 arg) (match-string 2 arg)))
6933 ((or (string-match "^\\+incdir\\+\\(.*\\)" arg) ;; +incdir+dir
6934 (string-match "^-I\\(.*\\)" arg)) ;; -Idir
6935 (verilog-add-list-unique `verilog-library-directories
6936 (match-string 1 arg)))
6938 ((equal "+librescan" arg))
6939 ((string-match "^-U\\(.*\\)" arg)) ;; -Udefine
6940 ;; Second parameters
6941 ((equal next-param "-f")
6942 (setq next-param nil)
6943 (verilog-getopt-file arg))
6944 ((equal next-param "-v")
6945 (setq next-param nil)
6946 (verilog-add-list-unique `verilog-library-files arg))
6947 ((equal next-param "-y")
6948 (setq next-param nil)
6949 (verilog-add-list-unique `verilog-library-directories arg))
6951 ((string-match "^[^-+]" arg)
6952 (verilog-add-list-unique `verilog-library-files arg))
6953 ;; Default - ignore; no warning
6955 ;;(verilog-getopt (list "+libext+.a+.b" "+incdir+foodir" "+define+a+aval" "-f" "otherf" "-v" "library" "-y" "dir"))
6957 (defun verilog-getopt-file (filename)
6958 "Read Verilog options from the specified FILENAME."
6960 (let ((fns (verilog-library-filenames filename (buffer-file-name)))
6961 (orig-buffer (current-buffer))
6964 (set-buffer (find-file-noselect (car fns)))
6965 (error (concat (verilog-point-text)
6966 "Can't find verilog-getopt-file -f file: " filename)))
6967 (goto-char (point-min))
6969 (setq line (buffer-substring (point)
6970 (save-excursion (end-of-line) (point))))
6972 (when (string-match "//" line)
6973 (setq line (substring line 0 (match-beginning 0))))
6975 (set-buffer orig-buffer) ; Variables are buffer-local, so need right context.
6976 (verilog-getopt line))))))
6978 (defun verilog-getopt-flags ()
6979 "Convert `verilog-library-flags' into standard library variables."
6980 ;; If the flags are local, then all the outputs should be local also
6981 (when (local-variable-p `verilog-library-flags (current-buffer))
6982 (mapc 'make-local-variable '(verilog-library-extensions
6983 verilog-library-directories
6984 verilog-library-files
6985 verilog-library-flags)))
6986 ;; Allow user to customize
6987 (run-hooks 'verilog-before-getopt-flags-hook)
6988 ;; Process arguments
6989 (verilog-getopt verilog-library-flags)
6990 ;; Allow user to customize
6991 (run-hooks 'verilog-getopt-flags-hook))
6993 (defun verilog-add-list-unique (varref object)
6994 "Append to VARREF list the given OBJECT,
6995 unless it is already a member of the variable's list."
6996 (unless (member object (symbol-value varref))
6997 (set varref (append (symbol-value varref) (list object))))
6999 ;;(progn (setq l '()) (verilog-add-list-unique `l "a") (verilog-add-list-unique `l "a") l)
7003 ;; Module name lookup
7006 (defun verilog-module-inside-filename-p (module filename)
7007 "Return point if MODULE is specified inside FILENAME, else nil.
7008 Allows version control to check out the file if need be."
7009 (and (or (file-exists-p filename)
7010 (and (fboundp 'vc-backend)
7011 (vc-backend filename)))
7014 (set-buffer (find-file-noselect filename))
7015 (goto-char (point-min))
7017 ;; It may be tempting to look for verilog-defun-re, don't, it slows things down a lot!
7018 (verilog-re-search-forward-quick "\\<module\\>" nil t)
7019 (verilog-re-search-forward-quick "[(;]" nil t))
7020 (if (equal module (verilog-read-module-name))
7024 (defun verilog-is-number (symbol)
7025 "Return true if SYMBOL is number-like."
7026 (or (string-match "^[0-9 \t:]+$" symbol)
7027 (string-match "^[---]*[0-9]+$" symbol)
7028 (string-match "^[0-9 \t]+'s?[hdxbo][0-9a-fA-F_xz? \t]*$" symbol)))
7030 (defun verilog-symbol-detick (symbol wing-it)
7031 "Return an expanded SYMBOL name without any defines.
7032 If the variable vh-{symbol} is defined, return that value.
7033 If undefined, and WING-IT, return just SYMBOL without the tick, else nil."
7034 (while (and symbol (string-match "^`" symbol))
7035 (setq symbol (substring symbol 1))
7037 (if (boundp (intern (concat "vh-" symbol)))
7038 ;; Emacs has a bug where boundp on a buffer-local
7039 ;; variable in only one buffer returns t in another.
7040 ;; This can confuse, so check for nil.
7041 (let ((val (eval (intern (concat "vh-" symbol)))))
7043 (if wing-it symbol nil)
7045 (if wing-it symbol nil))))
7047 ;;(verilog-symbol-detick "`mod" nil)
7049 (defun verilog-symbol-detick-denumber (symbol)
7050 "Return SYMBOL with defines converted and any numbers dropped to nil."
7051 (when (string-match "^`" symbol)
7052 ;; This only will work if the define is a simple signal, not
7053 ;; something like a[b]. Sorry, it should be substituted into the parser
7055 (verilog-string-replace-matches
7056 "\[[^0-9: \t]+\]" "" nil nil
7057 (or (verilog-symbol-detick symbol nil)
7058 (if verilog-auto-sense-defines-constant
7061 (if (verilog-is-number symbol)
7065 (defun verilog-symbol-detick-text (text)
7066 "Return TEXT without any known defines.
7067 If the variable vh-{symbol} is defined, substitute that value."
7068 (let ((ok t) symbol val)
7069 (while (and ok (string-match "`\\([a-zA-Z0-9_]+\\)" text))
7070 (setq symbol (match-string 1 text))
7073 (boundp (intern (concat "vh-" symbol)))
7074 ;; Emacs has a bug where boundp on a buffer-local
7075 ;; variable in only one buffer returns t in another.
7076 ;; This can confuse, so check for nil.
7077 (setq val (eval (intern (concat "vh-" symbol)))))
7078 (setq text (replace-match val nil nil text)))
7079 (t (setq ok nil)))))
7081 ;;(progn (setq vh-mod "`foo" vh-foo "bar") (verilog-symbol-detick-text "bar `mod `undefed"))
7083 (defun verilog-expand-dirnames (&optional dirnames)
7084 "Return a list of existing directories given a list of wildcarded DIRNAMES.
7085 Or, just the existing dirnames themselves if there are no wildcards."
7087 (unless dirnames (error "`verilog-library-directories' should include at least '.'"))
7088 (setq dirnames (reverse dirnames)) ; not nreverse
7090 pattern dirfile dirfiles dirname root filename rest)
7092 (setq dirname (substitute-in-file-name (car dirnames))
7093 dirnames (cdr dirnames))
7094 (cond ((string-match (concat "^\\(\\|[/\\]*[^*?]*[/\\]\\)" ;; root
7095 "\\([^/\\]*[*?][^/\\]*\\)" ;; filename with *?
7098 (setq root (match-string 1 dirname)
7099 filename (match-string 2 dirname)
7100 rest (match-string 3 dirname)
7102 ;; now replace those * and ? with .+ and .
7103 ;; use ^ and /> to get only whole file names
7104 ;;verilog-string-replace-matches
7105 (setq pattern (verilog-string-replace-matches "[*]" ".+" nil nil pattern)
7106 pattern (verilog-string-replace-matches "[?]" "." nil nil pattern)
7108 ;; Unfortunately allows abc/*/rtl to match abc/rtl
7109 ;; because abc/.. shows up in dirfiles. Solutions welcome.
7110 dirfiles (if (file-directory-p root) ; Ignore version control external
7111 (directory-files root t pattern nil)))
7113 (setq dirfile (expand-file-name (concat (car dirfiles) rest))
7114 dirfiles (cdr dirfiles))
7115 (if (file-directory-p dirfile)
7116 (setq dirlist (cons dirfile dirlist)))))
7119 (if (file-directory-p dirname)
7120 (setq dirlist (cons dirname dirlist))))))
7122 ;;(verilog-expand-dirnames (list "." ".." "nonexist" "../*" "/home/wsnyder/*/v"))
7124 (defun verilog-library-filenames (filename current &optional check-ext)
7125 "Return a search path to find the given FILENAME name.
7126 Uses the CURRENT filename, `verilog-library-directories' and
7127 `verilog-library-extensions' variables to build the path.
7128 With optional CHECK-EXT also check `verilog-library-extensions'."
7129 (let ((ckdir (verilog-expand-dirnames verilog-library-directories))
7132 (let ((ckext (if check-ext verilog-library-extensions `(""))))
7134 (setq fn (expand-file-name
7135 (concat filename (car ckext))
7136 (expand-file-name (car ckdir) (file-name-directory current))))
7137 (if (file-exists-p fn)
7138 (setq outlist (cons fn outlist)))
7139 (setq ckext (cdr ckext))))
7140 (setq ckdir (cdr ckdir)))
7141 (nreverse outlist)))
7143 (defun verilog-module-filenames (module current)
7144 "Return a search path to find the given MODULE name.
7145 Uses the CURRENT filename, `verilog-library-extensions',
7146 `verilog-library-directories' and `verilog-library-files'
7147 variables to build the path."
7148 ;; Return search locations for it
7149 (append (list current) ; first, current buffer
7150 (verilog-library-filenames module current t)
7151 verilog-library-files)) ; finally, any libraries
7154 ;; Module Information
7156 ;; Many of these functions work on "modi" a module information structure
7157 ;; A modi is: [module-name-string file-name begin-point]
7159 (defvar verilog-cache-enabled t
7160 "If true, enable caching of signals, etc. Set to nil for debugging to make things SLOW!")
7162 (defvar verilog-modi-cache-list nil
7163 "Cache of ((Module Function) Buf-Tick Buf-Modtime Func-Returns)...
7164 For speeding up verilog-modi-get-* commands.
7167 (make-variable-buffer-local 'verilog-modi-cache-list)
7169 (defvar verilog-modi-cache-preserve-tick nil
7170 "Modification tick after which the cache is still considered valid.
7171 Use `verilog-preserve-cache' to set it.")
7172 (defvar verilog-modi-cache-preserve-buffer nil
7173 "Modification tick after which the cache is still considered valid.
7174 Use `verilog-preserve-cache' to set it.")
7176 (defun verilog-modi-current ()
7177 "Return the modi structure for the module currently at point."
7179 ;; read current module's name
7181 (verilog-re-search-backward-quick verilog-defun-re nil nil)
7182 (verilog-re-search-forward-quick "(" nil nil)
7183 (setq name (verilog-read-module-name))
7186 (vector name (or (buffer-file-name) (current-buffer)) pt)))
7188 (defvar verilog-modi-lookup-last-mod nil "Cache of last module looked up.")
7189 (defvar verilog-modi-lookup-last-modi nil "Cache of last modi returned.")
7190 (defvar verilog-modi-lookup-last-current nil "Cache of last `current-buffer' looked up.")
7191 (defvar verilog-modi-lookup-last-tick nil "Cache of last `buffer-modified-tick' looked up.")
7193 (defun verilog-modi-lookup (module allow-cache &optional ignore-error)
7194 "Find the file and point at which MODULE is defined.
7195 If ALLOW-CACHE is set, check and remember cache of previous lookups.
7196 Return modi if successful, else print message unless IGNORE-ERROR is true."
7197 (let* ((current (or (buffer-file-name) (current-buffer))))
7198 (cond ((and verilog-modi-lookup-last-modi
7199 verilog-cache-enabled
7201 (equal verilog-modi-lookup-last-mod module)
7202 (equal verilog-modi-lookup-last-current current)
7203 (equal verilog-modi-lookup-last-tick (buffer-modified-tick)))
7206 (t (let* ((realmod (verilog-symbol-detick module t))
7207 (orig-filenames (verilog-module-filenames realmod current))
7208 (filenames orig-filenames)
7210 (while (and filenames (not pt))
7211 (if (not (setq pt (verilog-module-inside-filename-p realmod (car filenames))))
7212 (setq filenames (cdr filenames))))
7213 (cond (pt (setq verilog-modi-lookup-last-modi
7214 (vector realmod (car filenames) pt)))
7215 (t (setq verilog-modi-lookup-last-modi nil)
7217 (error (concat (verilog-point-text)
7218 ": Can't locate " module " module definition"
7219 (if (not (equal module realmod))
7220 (concat " (Expanded macro to " realmod ")")
7222 "\n Check the verilog-library-directories variable."
7223 "\n I looked in (if not listed, doesn't exist):\n\t"
7224 (mapconcat 'concat orig-filenames "\n\t"))))))
7225 (setq verilog-modi-lookup-last-mod module
7226 verilog-modi-lookup-last-current current
7227 verilog-modi-lookup-last-tick (buffer-modified-tick)))))
7228 verilog-modi-lookup-last-modi))
7230 (defsubst verilog-modi-name (modi)
7232 (defsubst verilog-modi-file-or-buffer (modi)
7234 (defsubst verilog-modi-point (modi)
7237 (defun verilog-modi-filename (modi)
7238 "Filename of MODI, or name of buffer if it's never been saved."
7239 (if (bufferp (verilog-modi-file-or-buffer modi))
7240 (or (buffer-file-name (verilog-modi-file-or-buffer modi))
7241 (buffer-name (verilog-modi-file-or-buffer modi)))
7242 (verilog-modi-file-or-buffer modi)))
7244 (defun verilog-modi-goto (modi)
7245 "Move point/buffer to specified MODI."
7246 (or modi (error "Passed unfound modi to goto, check earlier"))
7247 (set-buffer (if (bufferp (verilog-modi-file-or-buffer modi))
7248 (verilog-modi-file-or-buffer modi)
7249 (find-file-noselect (verilog-modi-file-or-buffer modi))))
7250 (or (equal major-mode `verilog-mode) ;; Put into Verilog mode to get syntax
7252 (goto-char (verilog-modi-point modi)))
7254 (defun verilog-goto-defun-file (module)
7255 "Move point to the file at which a given MODULE is defined."
7256 (interactive "sGoto File for Module: ")
7257 (let* ((modi (verilog-modi-lookup module nil)))
7259 (verilog-modi-goto modi)
7260 (switch-to-buffer (current-buffer)))))
7262 (defun verilog-modi-cache-results (modi function)
7263 "Run on MODI the given FUNCTION. Locate the module in a file.
7264 Cache the output of function so next call may have faster access."
7265 (let (func-returns fass)
7267 (verilog-modi-goto modi)
7268 (if (and (setq fass (assoc (list (verilog-modi-name modi) function)
7269 verilog-modi-cache-list))
7270 ;; Destroy caching when incorrect; Modified or file changed
7271 (not (and verilog-cache-enabled
7272 (or (equal (buffer-modified-tick) (nth 1 fass))
7273 (and verilog-modi-cache-preserve-tick
7274 (<= verilog-modi-cache-preserve-tick (nth 1 fass))
7275 (equal verilog-modi-cache-preserve-buffer (current-buffer))))
7276 (equal (visited-file-modtime) (nth 2 fass)))))
7277 (setq verilog-modi-cache-list nil
7281 (setq func-returns (nth 3 fass)))
7284 ;; Clear then restore any hilighting to make Emacs 19 happy
7285 (let ((fontlocked (when (and (boundp 'font-lock-mode)
7287 (font-lock-mode nil)
7289 (setq func-returns (funcall function))
7290 (when fontlocked (font-lock-mode t)))
7291 ;; Cache for next time
7292 (setq verilog-modi-cache-list
7293 (cons (list (list (verilog-modi-name modi) function)
7294 (buffer-modified-tick)
7295 (visited-file-modtime)
7297 verilog-modi-cache-list)))))
7301 (defun verilog-modi-cache-add (modi function element sig-list)
7302 "Add function return results to the module cache.
7303 Update MODI's cache for given FUNCTION so that the return ELEMENT of that
7304 function now contains the additional SIG-LIST parameters."
7307 (verilog-modi-goto modi)
7308 (if (setq fass (assoc (list (verilog-modi-name modi) function)
7309 verilog-modi-cache-list))
7310 (let ((func-returns (nth 3 fass)))
7311 (aset func-returns element
7312 (append sig-list (aref func-returns element))))))))
7314 (defmacro verilog-preserve-cache (&rest body)
7315 "Execute the BODY forms, allowing cache preservation within BODY.
7316 This means that changes to the buffer will not result in the cache being
7317 flushed. If the changes affect the modsig state, they must call the
7318 modsig-cache-add-* function, else the results of later calls may be
7319 incorrect. Without this, changes are assumed to be adding/removing signals
7320 and invalidating the cache."
7321 `(let ((verilog-modi-cache-preserve-tick (buffer-modified-tick))
7322 (verilog-modi-cache-preserve-buffer (current-buffer)))
7326 (defun verilog-signals-matching-enum (in-list enum)
7327 "Return all signals in IN-LIST matching the given ENUM."
7330 (if (equal (verilog-sig-enum (car in-list)) enum)
7331 (setq out-list (cons (car in-list) out-list)))
7332 (setq in-list (cdr in-list)))
7334 (let* ((enumvar (intern (concat "venum-" enum)))
7335 (enumlist (and (boundp enumvar) (eval enumvar))))
7337 (add-to-list 'out-list (list (car enumlist)))
7338 (setq enumlist (cdr enumlist))))
7339 (nreverse out-list)))
7341 (defun verilog-signals-matching-regexp (in-list regexp)
7342 "Return all signals in IN-LIST matching the given REGEXP, if non-nil."
7347 (if (string-match regexp (verilog-sig-name (car in-list)))
7348 (setq out-list (cons (car in-list) out-list)))
7349 (setq in-list (cdr in-list)))
7350 (nreverse out-list))))
7352 (defun verilog-signals-not-matching-regexp (in-list regexp)
7353 "Return all signals in IN-LIST not matching the given REGEXP, if non-nil."
7358 (if (not (string-match regexp (verilog-sig-name (car in-list))))
7359 (setq out-list (cons (car in-list) out-list)))
7360 (setq in-list (cdr in-list)))
7361 (nreverse out-list))))
7364 (defun verilog-modi-get-signals (modi)
7366 (verilog-modi-get-outputs modi)
7367 (verilog-modi-get-inouts modi)
7368 (verilog-modi-get-inputs modi)
7369 (verilog-modi-get-wires modi)
7370 (verilog-modi-get-regs modi)
7371 (verilog-modi-get-assigns modi)
7372 (verilog-modi-get-consts modi)
7373 (verilog-modi-get-gparams modi)))
7375 (defun verilog-modi-get-ports (modi)
7377 (verilog-modi-get-outputs modi)
7378 (verilog-modi-get-inouts modi)
7379 (verilog-modi-get-inputs modi)))
7381 (defsubst verilog-modi-cache-add-outputs (modi sig-list)
7382 (verilog-modi-cache-add modi 'verilog-read-decls 0 sig-list))
7383 (defsubst verilog-modi-cache-add-inouts (modi sig-list)
7384 (verilog-modi-cache-add modi 'verilog-read-decls 1 sig-list))
7385 (defsubst verilog-modi-cache-add-inputs (modi sig-list)
7386 (verilog-modi-cache-add modi 'verilog-read-decls 2 sig-list))
7387 (defsubst verilog-modi-cache-add-wires (modi sig-list)
7388 (verilog-modi-cache-add modi 'verilog-read-decls 3 sig-list))
7389 (defsubst verilog-modi-cache-add-regs (modi sig-list)
7390 (verilog-modi-cache-add modi 'verilog-read-decls 4 sig-list))
7392 (defun verilog-signals-from-signame (signame-list)
7393 "Return signals in standard form from SIGNAME-LIST, a simple list of signal names."
7394 (mapcar (function (lambda (name) (list name nil nil)))
7398 ;; Auto creation utilities
7401 (defun verilog-auto-re-search-do (search-for func)
7402 "Search for the given auto text regexp SEARCH-FOR, and perform FUNC where it occurs."
7403 (goto-char (point-min))
7404 (while (verilog-re-search-forward search-for nil t)
7407 (defun verilog-auto-search-do (search-for func)
7408 "Search for the given auto text SEARCH-FOR, and perform FUNC where it occurs."
7409 (verilog-auto-re-search-do (regexp-quote search-for) func))
7411 (defun verilog-insert-one-definition (sig type indent-pt)
7412 "Print out a definition for SIG of the given TYPE,
7413 with appropriate INDENT-PT indentation."
7414 (indent-to indent-pt)
7416 (when (verilog-sig-signed sig)
7417 (insert " " (verilog-sig-signed sig)))
7418 (when (verilog-sig-multidim sig)
7419 (insert " " (verilog-sig-multidim-string sig)))
7420 (when (verilog-sig-bits sig)
7421 (insert " " (verilog-sig-bits sig)))
7422 (indent-to (max 24 (+ indent-pt 16)))
7423 (unless (= (char-syntax (preceding-char)) ?\ )
7424 (insert " ")) ; Need space between "]name" if indent-to did nothing
7425 (insert (verilog-sig-name sig)))
7427 (defun verilog-insert-definition (sigs direction indent-pt v2k &optional dont-sort)
7428 "Print out a definition for a list of SIGS of the given DIRECTION,
7429 with appropriate INDENT-PT indentation. If V2K, use Verilog 2001 I/O
7430 format. Sort unless DONT-SORT. DIRECTION is normally wire/reg/output."
7432 (setq sigs (sort (copy-alist sigs) `verilog-signals-sort-compare)))
7434 (let ((sig (car sigs)))
7435 (verilog-insert-one-definition
7437 ;; Want "type x" or "output type x", not "wire type x"
7438 (cond ((verilog-sig-type sig)
7440 (if (not (equal direction "wire"))
7441 (concat direction " "))
7442 (verilog-sig-type sig)))
7445 (insert (if v2k "," ";"))
7446 (if (or (not (verilog-sig-comment sig))
7447 (equal "" (verilog-sig-comment sig)))
7449 (indent-to (max 48 (+ indent-pt 40)))
7450 (insert (concat "// " (verilog-sig-comment sig) "\n")))
7451 (setq sigs (cdr sigs)))))
7454 (if (not (boundp 'indent-pt))
7455 (defvar indent-pt nil "Local used by insert-indent")))
7457 (defun verilog-insert-indent (&rest stuff)
7458 "Indent to position stored in local `indent-pt' variable, then insert STUFF.
7459 Presumes that any newlines end a list element."
7460 (let ((need-indent t))
7462 (if need-indent (indent-to indent-pt))
7463 (setq need-indent nil)
7464 (insert (car stuff))
7465 (setq need-indent (string-match "\n$" (car stuff))
7466 stuff (cdr stuff)))))
7467 ;;(let ((indent-pt 10)) (verilog-insert-indent "hello\n" "addon" "there\n"))
7469 (defun verilog-repair-open-comma ()
7470 "If backwards-from-point is other than a open parenthesis insert comma."
7472 (verilog-backward-syntactic-ws)
7473 (when (save-excursion
7475 (and (not (looking-at "[(,]"))
7477 (verilog-re-search-backward "[(`]" nil t)
7481 (defun verilog-repair-close-comma ()
7482 "If point is at a comma followed by a close parenthesis, fix it.
7483 This repairs those mis-inserted by a AUTOARG."
7484 ;; It would be much nicer if Verilog allowed extra commas like Perl does!
7486 (verilog-forward-close-paren)
7488 (verilog-backward-syntactic-ws)
7490 (when (looking-at ",")
7493 (defun verilog-get-list (start end)
7494 "Return the elements of a comma separated list between START and END."
7496 (let ((my-list (list))
7499 (while (< (point) end)
7500 (when (re-search-forward "\\([^,{]+\\)" end t)
7501 (setq my-string (verilog-string-remove-spaces (match-string 1)))
7502 (setq my-list (nconc my-list (list my-string) ))
7503 (goto-char (match-end 0))))
7506 (defun verilog-make-width-expression (range-exp)
7507 "Return an expression calculating the length of a range [x:y] in RANGE-EXP."
7509 (cond ((not range-exp)
7512 (if (string-match "^\\[\\(.*\\)\\]$" range-exp)
7513 (setq range-exp (match-string 1 range-exp)))
7514 (cond ((not range-exp)
7516 ((string-match "^\\s *\\([0-9]+\\)\\s *:\\s *\\([0-9]+\\)\\s *$"
7519 (1+ (abs (- (string-to-number (match-string 1 range-exp))
7520 (string-to-number (match-string 2 range-exp)))))))
7521 ((string-match "^\\(.*\\)\\s *:\\s *\\(.*\\)\\s *$" range-exp)
7522 (concat "(1+(" (match-string 1 range-exp) ")"
7523 (if (equal "0" (match-string 2 range-exp))
7524 "" ;; Don't bother with -(0)
7525 (concat "-(" (match-string 2 range-exp) ")"))
7528 ;;(verilog-make-width-expression "`A:`B")
7530 (defun verilog-typedef-name-p (variable-name)
7531 "Return true if the VARIABLE-NAME is a type definition."
7532 (when verilog-typedef-regexp
7533 (string-match verilog-typedef-regexp variable-name)))
7539 (defun verilog-delete-autos-lined ()
7540 "Delete autos that occupy multiple lines, between begin and end comments."
7544 (looking-at "\\s-*// Beginning")
7545 (search-forward "// End of automatic" nil t))
7548 (delete-region pt (point))
7551 (defun verilog-forward-close-paren ()
7552 "Find the close parenthesis that match the current point.
7553 Ignore other close parenthesis with matching open parens."
7556 (unless (verilog-re-search-forward-quick "[()]" nil t)
7557 (error "%s: Mismatching ()" (verilog-point-text)))
7558 (cond ((= (preceding-char) ?\( )
7559 (setq parens (1+ parens)))
7560 ((= (preceding-char) ?\) )
7561 (setq parens (1- parens)))))))
7563 (defun verilog-backward-open-paren ()
7564 "Find the open parenthesis that match the current point.
7565 Ignore other open parenthesis with matching close parens."
7568 (unless (verilog-re-search-backward-quick "[()]" nil t)
7569 (error "%s: Mismatching ()" (verilog-point-text)))
7570 (cond ((= (following-char) ?\) )
7571 (setq parens (1+ parens)))
7572 ((= (following-char) ?\( )
7573 (setq parens (1- parens)))))))
7575 (defun verilog-backward-open-bracket ()
7576 "Find the open bracket that match the current point.
7577 Ignore other open bracket with matching close bracket."
7580 (unless (verilog-re-search-backward-quick "[][]" nil t)
7581 (error "%s: Mismatching []" (verilog-point-text)))
7582 (cond ((= (following-char) ?\] )
7583 (setq parens (1+ parens)))
7584 ((= (following-char) ?\[ )
7585 (setq parens (1- parens)))))))
7587 (defun verilog-delete-to-paren ()
7588 "Delete the automatic inst/sense/arg created by autos.
7589 Deletion stops at the matching end parenthesis."
7590 (delete-region (point)
7592 (verilog-backward-open-paren)
7593 (forward-sexp 1) ;; Moves to paren that closes argdecl's
7597 (defun verilog-auto-star-safe ()
7598 "Return if a .* AUTOINST is safe to delete or expand.
7599 It was created by the AUTOS themselves, or by the user."
7600 (and verilog-auto-star-expand
7601 (looking-at "[ \t\n\f,]*\\([)]\\|// \\(Outputs\\|Inouts\\|Inputs\\)\\)")))
7603 (defun verilog-delete-auto-star-all ()
7604 "Delete a .* AUTOINST, if it is safe."
7605 (when (verilog-auto-star-safe)
7606 (verilog-delete-to-paren)))
7608 (defun verilog-delete-auto-star-implicit ()
7609 "Delete all .* implicit connections created by `verilog-auto-star'.
7610 This function will be called automatically at save unless
7611 `verilog-auto-star-save' is set, any non-templated expanded pins will be
7614 (let (paren-pt indent have-close-paren)
7616 (goto-char (point-min))
7617 ;; We need to match these even outside of comments.
7618 ;; For reasonable performance, we don't check if inside comments, sorry.
7619 (while (re-search-forward "// Implicit \\.\\*" nil t)
7620 (setq paren-pt (point))
7622 (setq have-close-paren
7624 (when (search-forward ");" paren-pt t)
7625 (setq indent (current-indentation))
7627 (delete-region (point) (+ 1 paren-pt)) ; Nuke line incl CR
7628 (when have-close-paren
7629 ;; Delete extra commentary
7633 (looking-at "\\s *//\\s *\\(Outputs\\|Inouts\\|Inputs\\)\n"))
7634 (delete-region (match-beginning 0) (match-end 0))))
7635 ;; If it is simple, we can put the ); on the same line as the last text
7636 (let ((rtn-pt (point)))
7638 (while (progn (backward-char 1)
7639 (looking-at "[ \t\n\f]")))
7640 (when (looking-at ",")
7641 (delete-region (+ 1 (point)) rtn-pt))))
7645 ;; Still need to kill final comma - always is one as we put one after the .*
7646 (re-search-backward ",")
7647 (delete-char 1))))))
7649 (defun verilog-delete-auto ()
7650 "Delete the automatic outputs, regs, and wires created by \\[verilog-auto].
7651 Use \\[verilog-auto] to re-insert the updated AUTOs.
7653 The hooks `verilog-before-delete-auto-hook' and `verilog-delete-auto-hook' are
7654 called before and after this function, respectively."
7657 (if (buffer-file-name)
7658 (find-file-noselect (buffer-file-name))) ;; To check we have latest version
7659 ;; Allow user to customize
7660 (run-hooks 'verilog-before-delete-auto-hook)
7662 ;; Remove those that have multi-line insertions, possibly with parameters
7663 (verilog-auto-re-search-do
7666 (verilog-regexp-words
7667 `("AUTOASCIIENUM" "AUTOCONCATCOMMENT" "AUTODEFINEVALUE"
7668 "AUTOINOUT" "AUTOINOUTMODULE" "AUTOINPUT" "AUTOOUTPUT"
7670 "AUTOREG" "AUTOREGINPUT" "AUTORESET" "AUTOTIEOFF"
7671 "AUTOUNUSED" "AUTOWIRE")))
7672 "\\(\\|([^)]*)\\|(\"[^\"]*\")\\)" ; Optional parens or quoted parameter
7674 'verilog-delete-autos-lined)
7675 ;; Remove those that are in parenthesis
7676 (verilog-auto-re-search-do
7679 (verilog-regexp-words
7680 `("AS" "AUTOARG" "AUTOCONCATWIDTH" "AUTOINST" "AUTOINSTPARAM"
7683 'verilog-delete-to-paren)
7684 ;; Do .* instantiations, but avoid removing any user pins by looking for our magic comments
7685 (verilog-auto-re-search-do "\\.\\*"
7686 'verilog-delete-auto-star-all)
7687 ;; Remove template comments ... anywhere in case was pasted after AUTOINST removed
7688 (goto-char (point-min))
7689 (while (re-search-forward "\\s-*// \\(Templated\\|Implicit \\.\\*\\)[ \tLT0-9]*$" nil t)
7693 (run-hooks 'verilog-delete-auto-hook)))
7699 (defun verilog-inject-auto ()
7700 "Examine legacy non-AUTO code and insert AUTOs in appropriate places.
7702 Any always @ blocks with sensitivity lists that match computed lists will
7703 be replaced with /*AS*/ comments.
7705 Any cells will get /*AUTOINST*/ added to the end of the pin list.
7706 Pins with have identical names will be deleted.
7708 Argument lists will not be deleted, /*AUTOARG*/ will only be inserted to
7709 support adding new ports. You may wish to delete older ports yourself.
7713 module ExampInject (i, o);
7724 Typing \\[verilog-inject-auto] will make this into:
7726 module ExampInject (i, o/*AUTOARG*/
7731 always @ (/*AS*/i or j)
7742 (defun verilog-inject-arg ()
7743 "Inject AUTOARG into new code. See `verilog-inject-auto'."
7744 ;; Presume one module per file.
7746 (goto-char (point-min))
7747 (while (verilog-re-search-forward-quick "\\<module\\>" nil t)
7748 (let ((endmodp (save-excursion
7749 (verilog-re-search-forward-quick "\\<endmodule\\>" nil t)
7751 ;; See if there's already a comment .. inside a comment so not verilog-re-search
7752 (when (not (re-search-forward "/\\*AUTOARG\\*/" endmodp t))
7753 (verilog-re-search-forward-quick ";" nil t)
7755 (verilog-backward-syntactic-ws)
7756 (backward-char 1) ; Moves to paren that closes argdecl's
7757 (when (looking-at ")")
7758 (insert "/*AUTOARG*/")))))))
7760 (defun verilog-inject-sense ()
7761 "Inject AUTOSENSE into new code. See `verilog-inject-auto'."
7763 (goto-char (point-min))
7764 (while (verilog-re-search-forward-quick "\\<always\\s *@\\s *(" nil t)
7765 (let ((start-pt (point))
7766 (modi (verilog-modi-current))
7771 (backward-char 1) ;; End )
7772 (when (not (verilog-re-search-backward "/\\*\\(AUTOSENSE\\|AS\\)\\*/" start-pt t))
7773 (setq pre-sigs (verilog-signals-from-signame
7774 (verilog-read-signals start-pt (point)))
7775 got-sigs (verilog-auto-sense-sigs modi nil))
7776 (when (not (or (verilog-signals-not-in pre-sigs got-sigs) ; Both are equal?
7777 (verilog-signals-not-in got-sigs pre-sigs)))
7778 (delete-region start-pt (point))
7779 (insert "/*AS*/")))))))
7781 (defun verilog-inject-inst ()
7782 "Inject AUTOINST into new code. See `verilog-inject-auto'."
7784 (goto-char (point-min))
7785 ;; It's hard to distinguish modules; we'll instead search for pins.
7786 (while (verilog-re-search-forward-quick "\\.\\s *[a-zA-Z0-9`_\$]+\\s *(\\s *[a-zA-Z0-9`_\$]+\\s *)" nil t)
7787 (verilog-backward-open-paren) ;; Inst start
7789 ((= (preceding-char) ?\#) ;; #(...) parameter section, not pin. Skip.
7791 (verilog-forward-close-paren)) ;; Parameters done
7794 (let ((indent-pt (+ (current-column)))
7795 (end-pt (save-excursion (verilog-forward-close-paren) (point))))
7796 (cond ((verilog-re-search-forward "\\(/\\*AUTOINST\\*/\\|\\.\\*\\)" end-pt t)
7797 (goto-char end-pt)) ;; Already there, continue search with next instance
7799 ;; Delete identical interconnect
7800 (let ((case-fold-search nil)) ;; So we don't convert upper-to-lower, etc
7801 (while (verilog-re-search-forward "\\.\\s *\\([a-zA-Z0-9`_\$]+\\)*\\s *(\\s *\\1\\s *)\\s *" end-pt t)
7802 (delete-region (match-beginning 0) (match-end 0))
7803 (setq end-pt (- end-pt (- (match-end 0) (match-beginning 0)))) ;; Keep it correct
7804 (while (or (looking-at "[ \t\n\f,]+")
7805 (looking-at "//[^\n]*"))
7806 (delete-region (match-beginning 0) (match-end 0))
7807 (setq end-pt (- end-pt (- (match-end 0) (match-beginning 0)))))))
7808 (verilog-forward-close-paren)
7810 ;; Not verilog-re-search, as we don't want to strip comments
7811 (while (re-search-backward "[ \t\n\f]+" (- (point) 1) t)
7812 (delete-region (match-beginning 0) (match-end 0)))
7814 (indent-to indent-pt)
7815 (insert "/*AUTOINST*/")))))))))
7821 (defun verilog-auto-save-check ()
7822 "On saving see if we need auto update."
7823 (cond ((not verilog-auto-save-policy)) ; disabled
7824 ((not (save-excursion
7826 (let ((case-fold-search nil))
7827 (goto-char (point-min))
7828 (re-search-forward "AUTO" nil t))))))
7829 ((eq verilog-auto-save-policy 'force)
7831 ((not (buffer-modified-p)))
7832 ((eq verilog-auto-update-tick (buffer-modified-tick))) ; up-to-date
7833 ((eq verilog-auto-save-policy 'detect)
7836 (when (yes-or-no-p "AUTO statements not recomputed, do it now? ")
7838 ;; Don't ask again if didn't update
7839 (set (make-local-variable 'verilog-auto-update-tick) (buffer-modified-tick))))
7840 (when (not verilog-auto-star-save)
7841 (verilog-delete-auto-star-implicit))
7842 nil) ;; Always return nil -- we don't write the file ourselves
7844 (defun verilog-auto-read-locals ()
7845 "Return file local variable segment at bottom of file."
7847 (goto-char (point-max))
7848 (if (re-search-backward "Local Variables:" nil t)
7849 (buffer-substring-no-properties (point) (point-max))
7852 (defun verilog-auto-reeval-locals (&optional force)
7853 "Read file local variable segment at bottom of file if it has changed.
7854 If FORCE, always reread it."
7855 (make-local-variable 'verilog-auto-last-file-locals)
7856 (let ((curlocal (verilog-auto-read-locals)))
7857 (when (or force (not (equal verilog-auto-last-file-locals curlocal)))
7858 (setq verilog-auto-last-file-locals curlocal)
7859 ;; Note this may cause this function to be recursively invoked.
7860 ;; The above when statement will prevent it from recursing forever.
7861 (hack-local-variables)
7868 (defun verilog-auto-arg-ports (sigs message indent-pt)
7869 "Print a list of ports for a AUTOINST.
7870 Takes SIGS list, adds MESSAGE to front and inserts each at INDENT-PT."
7873 (indent-to indent-pt)
7877 (indent-to indent-pt)
7879 (cond ((> (+ 2 (current-column) (length (verilog-sig-name (car sigs)))) fill-column)
7881 (indent-to indent-pt))
7883 (insert (verilog-sig-name (car sigs)) ",")
7884 (setq sigs (cdr sigs)
7887 (defun verilog-auto-arg ()
7888 "Expand AUTOARG statements.
7889 Replace the argument declarations at the beginning of the
7890 module with ones automatically derived from input and output
7891 statements. This can be dangerous if the module is instantiated
7892 using position-based connections, so use only name-based when
7893 instantiating the resulting module. Long lines are split based
7894 on the `fill-column', see \\[set-fill-column].
7897 Concatenation and outputting partial busses is not supported.
7899 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
7903 module ExampArg (/*AUTOARG*/);
7908 Typing \\[verilog-auto] will make this into:
7910 module ExampArg (/*AUTOARG*/
7920 Any ports declared between the ( and /*AUTOARG*/ are presumed to be
7921 predeclared and are not redeclared by AUTOARG. AUTOARG will make a
7922 conservative guess on adding a comma for the first signal, if you have
7923 any ifdefs or complicated expressions before the AUTOARG you will need
7924 to choose the comma yourself.
7926 Avoid declaring ports manually, as it makes code harder to maintain."
7928 (let ((modi (verilog-modi-current))
7929 (skip-pins (aref (verilog-read-arg-pins) 0)))
7930 (verilog-repair-open-comma)
7931 (verilog-auto-arg-ports (verilog-signals-not-in
7932 (verilog-modi-get-outputs modi)
7935 verilog-indent-level-declaration)
7936 (verilog-auto-arg-ports (verilog-signals-not-in
7937 (verilog-modi-get-inouts modi)
7940 verilog-indent-level-declaration)
7941 (verilog-auto-arg-ports (verilog-signals-not-in
7942 (verilog-modi-get-inputs modi)
7945 verilog-indent-level-declaration)
7946 (verilog-repair-close-comma)
7947 (unless (eq (char-before) ?/ )
7949 (indent-to verilog-indent-level-declaration))))
7951 (defun verilog-auto-inst-port-map (port-st)
7954 (defvar vl-cell-type nil "See `verilog-auto-inst'.") ; Prevent compile warning
7955 (defvar vl-cell-name nil "See `verilog-auto-inst'.") ; Prevent compile warning
7956 (defvar vl-name nil "See `verilog-auto-inst'.") ; Prevent compile warning
7957 (defvar vl-width nil "See `verilog-auto-inst'.") ; Prevent compile warning
7958 (defvar vl-dir nil "See `verilog-auto-inst'.") ; Prevent compile warning
7960 (defun verilog-auto-inst-port (port-st indent-pt tpl-list tpl-num for-star)
7961 "Print out a instantiation connection for this PORT-ST.
7962 Insert to INDENT-PT, use template TPL-LIST.
7963 @ are instantiation numbers, replaced with TPL-NUM.
7964 @\"(expression @)\" are evaluated, with @ as a variable.
7965 If FOR-STAR add comment it is a .* expansion."
7966 (let* ((port (verilog-sig-name port-st))
7967 (tpl-ass (or (assoc port (car tpl-list))
7968 (verilog-auto-inst-port-map port-st)))
7969 ;; vl-* are documented for user use
7970 (vl-name (verilog-sig-name port-st))
7971 (vl-width (verilog-sig-width port-st))
7972 (vl-bits (if (or verilog-auto-inst-vector
7973 (not (assoc port vector-skip-list))
7974 (not (equal (verilog-sig-bits port-st)
7975 (verilog-sig-bits (assoc port vector-skip-list)))))
7976 (or (verilog-sig-bits port-st) "")
7978 ;; Default if not found
7979 (tpl-net (if (verilog-sig-multidim port-st)
7980 (concat port "/*" (verilog-sig-multidim-string port-st)
7982 (concat port vl-bits)))
7983 (case-fold-search nil))
7985 (cond (tpl-ass ; Template of exact port name
7986 (setq tpl-net (nth 1 tpl-ass)))
7987 ((nth 1 tpl-list) ; Wildcards in template, search them
7988 (let ((wildcards (nth 1 tpl-list)))
7990 (when (string-match (nth 0 (car wildcards)) port)
7991 (setq tpl-ass (car wildcards) ; so allow @ parsing
7992 tpl-net (replace-match (nth 1 (car wildcards))
7994 (setq wildcards (cdr wildcards))))))
7995 ;; Parse Templated variable
7997 ;; Evaluate @"(lispcode)"
7998 (when (string-match "@\".*[^\\]\"" tpl-net)
7999 (while (string-match "@\"\\(\\([^\\\"]*\\(\\\\.\\)*\\)*\\)\"" tpl-net)
8002 (substring tpl-net 0 (match-beginning 0))
8004 (let* ((expr (match-string 1 tpl-net))
8007 (setq expr (verilog-string-replace-matches "\\\\\"" "\"" nil nil expr))
8008 (setq expr (verilog-string-replace-matches "@" tpl-num nil nil expr))
8009 (prin1 (eval (car (read-from-string expr)))
8010 (lambda (ch) ())))))
8011 (if (numberp value) (setq value (number-to-string value)))
8013 (substring tpl-net (match-end 0))))))
8014 ;; Replace @ and [] magic variables in final output
8015 (setq tpl-net (verilog-string-replace-matches "@" tpl-num nil nil tpl-net))
8016 (setq tpl-net (verilog-string-replace-matches "\\[\\]" vl-bits nil nil tpl-net)))
8017 (indent-to indent-pt)
8019 (indent-to verilog-auto-inst-column)
8020 (insert "(" tpl-net "),")
8022 (indent-to (+ (if (< verilog-auto-inst-column 48) 24 16)
8023 verilog-auto-inst-column))
8024 (insert " // Templated")
8025 (when verilog-auto-inst-template-numbers
8026 (insert " T" (int-to-string (nth 2 tpl-ass))
8027 " L" (int-to-string (nth 3 tpl-ass)))))
8029 (indent-to (+ (if (< verilog-auto-inst-column 48) 24 16)
8030 verilog-auto-inst-column))
8031 (insert " // Implicit .\*"))) ;For some reason the . or * must be escaped...
8033 ;;(verilog-auto-inst-port (list "foo" "[5:0]") 10 (list (list "foo" "a@\"(% (+ @ 1) 4)\"a")) "3")
8034 ;;(x "incom[@\"(+ (* 8 @) 7)\":@\"(* 8 @)\"]")
8035 ;;(x ".out (outgo[@\"(concat (+ (* 8 @) 7) \\\":\\\" ( * 8 @))\"]));")
8037 (defun verilog-auto-inst-first ()
8038 "Insert , etc before first ever port in this instant, as part of \\[verilog-auto-inst]."
8039 ;; Do we need a trailing comma?
8040 ;; There maybe a ifdef or something similar before us. What a mess. Thus
8041 ;; to avoid trouble we only insert on preceeding ) or *.
8042 ;; Insert first port on new line
8043 (insert "\n") ;; Must insert before search, so point will move forward if insert comma
8045 (verilog-re-search-backward "[^ \t\n\f]" nil nil)
8046 (when (looking-at ")\\|\\*") ;; Generally don't insert, unless we are fairly sure
8050 (defun verilog-auto-star ()
8051 "Expand SystemVerilog .* pins, as part of \\[verilog-auto].
8053 If `verilog-auto-star-expand' is set, .* pins are treated if they were
8054 AUTOINST statements, otherwise they are ignored. For safety, Verilog mode
8055 will also ignore any .* that are not last in your pin list (this prevents
8056 it from deleting pins following the .* when it expands the AUTOINST.)
8058 On writing your file, unless `verilog-auto-star-save' is set, any
8059 non-templated expanded pins will be removed. You may do this at any time
8060 with \\[verilog-delete-auto-star-implicit].
8062 If you are converting a module to use .* for the first time, you may wish
8063 to use \\[verilog-inject-auto] and then replace the created AUTOINST with .*.
8065 See `verilog-auto-inst' for examples, templates, and more information."
8066 (when (verilog-auto-star-safe)
8067 (verilog-auto-inst)))
8069 (defun verilog-auto-inst ()
8070 "Expand AUTOINST statements, as part of \\[verilog-auto].
8071 Replace the pin connections to an instantiation with ones
8072 automatically derived from the module header of the instantiated netlist.
8074 If `verilog-auto-star-expand' is set, also expand SystemVerilog .* ports,
8075 and delete them before saving unless `verilog-auto-star-save' is set.
8076 See `verilog-auto-star' for more information.
8079 Module names must be resolvable to filenames by adding a
8080 `verilog-library-extensions', and being found in the same directory, or
8081 by changing the variable `verilog-library-flags' or
8082 `verilog-library-directories'. Macros `modname are translated through the
8083 vh-{name} Emacs variable, if that is not found, it just ignores the `.
8085 In templates you must have one signal per line, ending in a ), or ));,
8086 and have proper () nesting, including a final ); to end the template.
8088 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
8090 SystemVerilog multidimensional input/output has only experimental support.
8092 For example, first take the submodule InstModule.v:
8094 module InstModule (o,i)
8097 wire [31:0] o = {32{i}};
8100 This is then used in a upper level module:
8102 module ExampInst (o,i)
8109 Typing \\[verilog-auto] will make this into:
8111 module ExampInst (o,i)
8122 Where the list of inputs and outputs came from the inst module.
8126 Unless you are instantiating a module multiple times, or the module is
8127 something trivial like an adder, DO NOT CHANGE SIGNAL NAMES ACROSS HIERARCHY.
8128 It just makes for unmaintainable code. To sanitize signal names, try
8129 vrename from http://www.veripool.com.
8131 When you need to violate this suggestion there are two ways to list
8132 exceptions, placing them before the AUTOINST, or using templates.
8134 Any ports defined before the /*AUTOINST*/ are not included in the list of
8135 automatics. This is similar to making a template as described below, but
8136 is restricted to simple connections just like you normally make. Also note
8137 that any signals before the AUTOINST will only be picked up by AUTOWIRE if
8138 you have the appropriate // Input or // Output comment, and exactly the
8139 same line formatting as AUTOINST itself uses.
8143 .i (my_i_dont_mess_with_it),
8151 For multiple instantiations based upon a single template, create a
8152 commented out template:
8154 /* InstModule AUTO_TEMPLATE (
8159 Templates go ABOVE the instantiation(s). When an instantiation is
8160 expanded `verilog-mode' simply searches up for the closest template.
8161 Thus you can have multiple templates for the same module, just alternate
8162 between the template for an instantiation and the instantiation itself.
8164 The module name must be the same as the name of the module in the
8165 instantiation name, and the code \"AUTO_TEMPLATE\" must be in these exact
8166 words and capitalized. Only signals that must be different for each
8167 instantiation need to be listed.
8169 Inside a template, a [] in a connection name (with nothing else inside
8170 the brackets) will be replaced by the same bus subscript as it is being
8171 connected to, or the [] will be removed if it is a single bit signal.
8172 Generally it is a good idea to do this for all connections in a template,
8173 as then they will work for any width signal, and with AUTOWIRE. See
8174 PTL_BUS becoming PTL_BUSNEW below.
8176 If you have a complicated template, set `verilog-auto-inst-template-numbers'
8177 to see which regexps are matching. Don't leave that mode set after
8178 debugging is completed though, it will result in lots of extra differences
8179 and merge conflicts.
8183 /* InstModule AUTO_TEMPLATE (
8184 .ptl_bus (ptl_busnew[]),
8187 InstModule ms2m (/*AUTOINST*/);
8189 Typing \\[verilog-auto] will make this into:
8191 InstModule ms2m (/*AUTOINST*/
8193 .NotInTemplate (NotInTemplate),
8194 .ptl_bus (ptl_busnew[3:0]), // Templated
8199 It is common to instantiate a cell multiple times, so templates make it
8200 trivial to substitute part of the cell name into the connection name.
8202 /* InstName AUTO_TEMPLATE <optional \"REGEXP\"> (
8204 .sig2 (sigy[@\"(% (+ 1 @) 4)\"]),
8208 If no regular expression is provided immediately after the AUTO_TEMPLATE
8209 keyword, then the @ character in any connection names will be replaced
8210 with the instantiation number; the first digits found in the cell's
8213 If a regular expression is provided, the @ character will be replaced
8214 with the first \(\) grouping that matches against the cell name. Using a
8215 regexp of \"\\([0-9]+\\)\" provides identical values for @ as when no
8216 regexp is provided. If you use multiple layers of parenthesis,
8217 \"test\\([^0-9]+\\)_\\([0-9]+\\)\" would replace @ with non-number
8218 characters after test and before _, whereas
8219 \"\\(test\\([a-z]+\\)_\\([0-9]+\\)\\)\" would replace @ with the entire
8224 /* InstModule AUTO_TEMPLATE (
8225 .ptl_mapvalidx (ptl_mapvalid[@]),
8226 .ptl_mapvalidp1x (ptl_mapvalid[@\"(% (+ 1 @) 4)\"]),
8229 InstModule ms2m (/*AUTOINST*/);
8231 Typing \\[verilog-auto] will make this into:
8233 InstModule ms2m (/*AUTOINST*/
8235 .ptl_mapvalidx (ptl_mapvalid[2]),
8236 .ptl_mapvalidp1x (ptl_mapvalid[3]));
8238 Note the @ character was replaced with the 2 from \"ms2m\".
8240 Alternatively, using a regular expression for @:
8242 /* InstModule AUTO_TEMPLATE \"_\\([a-z]+\\)\" (
8243 .ptl_mapvalidx (@_ptl_mapvalid),
8244 .ptl_mapvalidp1x (ptl_mapvalid_@),
8247 InstModule ms2_FOO (/*AUTOINST*/);
8248 InstModule ms2_BAR (/*AUTOINST*/);
8250 Typing \\[verilog-auto] will make this into:
8252 InstModule ms2_FOO (/*AUTOINST*/
8254 .ptl_mapvalidx (FOO_ptl_mapvalid),
8255 .ptl_mapvalidp1x (ptl_mapvalid_FOO));
8256 InstModule ms2_BAR (/*AUTOINST*/
8258 .ptl_mapvalidx (BAR_ptl_mapvalid),
8259 .ptl_mapvalidp1x (ptl_mapvalid_BAR));
8264 A template entry of the form
8266 .pci_req\\([0-9]+\\)_l (pci_req_jtag_[\\1]),
8268 will apply an Emacs style regular expression search for any port beginning
8269 in pci_req followed by numbers and ending in _l and connecting that to
8270 the pci_req_jtag_[] net, with the bus subscript coming from what matches
8271 inside the first set of \\( \\). Thus pci_req2_l becomes pci_req_jtag_[2].
8273 Since \\([0-9]+\\) is so common and ugly to read, a @ in the port name
8274 does the same thing. (Note a @ in the connection/replacement text is
8275 completely different -- still use \\1 there!) Thus this is the same as
8278 .pci_req@_l (pci_req_jtag_[\\1]),
8280 Here's another example to remove the _l, useful when naming conventions
8281 specify _ alone to mean active low. Note the use of [] to keep the bus
8284 .\\(.*\\)_l (\\1_[]),
8288 First any regular expression template is expanded.
8290 If the syntax @\"( ... )\" is found in a connection, the expression in
8291 quotes will be evaluated as a Lisp expression, with @ replaced by the
8292 instantiation number. The MAPVALIDP1X example above would put @+1 modulo
8293 4 into the brackets. Quote all double-quotes inside the expression with
8294 a leading backslash (\\\"). There are special variables defined that are
8295 useful in these Lisp functions:
8297 vl-name Name portion of the input/output port.
8298 vl-bits Bus bits portion of the input/output port ('[2:0]').
8299 vl-width Width of the input/output port ('3' for [2:0]).
8300 May be a (...) expression if bits isn't a constant.
8301 vl-dir Direction of the pin input/output/inout.
8302 vl-cell-type Module name/type of the cell ('InstModule').
8303 vl-cell-name Instance name of the cell ('instName').
8305 Normal Lisp variables may be used in expressions. See
8306 `verilog-read-defines' which can set vh-{definename} variables for use
8307 here. Also, any comments of the form:
8309 /*AUTO_LISP(setq foo 1)*/
8311 will evaluate any Lisp expression inside the parenthesis between the
8312 beginning of the buffer and the point of the AUTOINST. This allows
8313 functions to be defined or variables to be changed between instantiations.
8315 Note that when using lisp expressions errors may occur when @ is not a
8316 number; you may need to use the standard Emacs Lisp functions
8317 `number-to-string' and `string-to-number'.
8319 After the evaluation is completed, @ substitution and [] substitution
8324 (for-star (save-excursion (backward-char 2) (looking-at "\\.\\*")))
8325 (indent-pt (save-excursion (verilog-backward-open-paren)
8326 (1+ (current-column))))
8327 (verilog-auto-inst-column (max verilog-auto-inst-column
8328 (+ 16 (* 8 (/ (+ indent-pt 7) 8)))))
8329 (modi (verilog-modi-current))
8330 (vector-skip-list (unless verilog-auto-inst-vector
8331 (verilog-modi-get-signals modi)))
8332 submod submodi inst skip-pins tpl-list tpl-num did-first)
8333 ;; Find module name that is instantiated
8334 (setq submod (verilog-read-inst-module)
8335 inst (verilog-read-inst-name)
8338 skip-pins (aref (verilog-read-inst-pins) 0))
8340 ;; Parse any AUTO_LISP() before here
8341 (verilog-read-auto-lisp (point-min) pt)
8343 ;; Lookup position, etc of submodule
8344 ;; Note this may raise an error
8345 (when (setq submodi (verilog-modi-lookup submod t))
8346 ;; If there's a number in the instantiation, it may be a argument to the
8347 ;; automatic variable instantiation program.
8348 (let* ((tpl-info (verilog-read-auto-template submod))
8349 (tpl-regexp (aref tpl-info 0)))
8350 (setq tpl-num (if (string-match tpl-regexp inst)
8351 (match-string 1 inst)
8353 tpl-list (aref tpl-info 1)))
8354 ;; Find submodule's signals and dump
8355 (let ((sig-list (verilog-signals-not-in
8356 (verilog-modi-get-outputs submodi)
8360 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
8361 (indent-to indent-pt)
8362 ;; Note these are searched for in verilog-read-sub-decls.
8363 (insert "// Outputs\n")
8364 (mapc (lambda (port)
8365 (verilog-auto-inst-port port indent-pt
8366 tpl-list tpl-num for-star))
8368 (let ((sig-list (verilog-signals-not-in
8369 (verilog-modi-get-inouts submodi)
8373 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
8374 (indent-to indent-pt)
8375 (insert "// Inouts\n")
8376 (mapc (lambda (port)
8377 (verilog-auto-inst-port port indent-pt
8378 tpl-list tpl-num for-star))
8380 (let ((sig-list (verilog-signals-not-in
8381 (verilog-modi-get-inputs submodi)
8385 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
8386 (indent-to indent-pt)
8387 (insert "// Inputs\n")
8388 (mapc (lambda (port)
8389 (verilog-auto-inst-port port indent-pt
8390 tpl-list tpl-num for-star))
8395 (re-search-backward "," pt t)
8398 (search-forward "\n") ;; Added by inst-port
8399 (delete-backward-char 1)
8400 (if (search-forward ")" nil t) ;; From user, moved up a line
8401 (delete-backward-char 1))
8402 (if (search-forward ";" nil t) ;; Don't error if user had syntax error and forgot it
8403 (delete-backward-char 1)))))))))
8405 (defun verilog-auto-inst-param ()
8406 "Expand AUTOINSTPARAM statements, as part of \\[verilog-auto].
8407 Replace the parameter connections to an instantiation with ones
8408 automatically derived from the module header of the instantiated netlist.
8410 See \\[verilog-auto-inst] for limitations, and templates to customize the
8413 For example, first take the submodule InstModule.v:
8415 module InstModule (o,i)
8419 This is then used in a upper level module:
8421 module ExampInst (o,i)
8423 InstModule #(/*AUTOINSTPARAM*/)
8424 instName (/*AUTOINST*/);
8427 Typing \\[verilog-auto] will make this into:
8429 module ExampInst (o,i)
8432 InstModule #(/*AUTOINSTPARAM*/
8435 instName (/*AUTOINST*/);
8438 Where the list of parameter connections come from the inst module.
8442 You can customize the parameter connections using AUTO_TEMPLATEs,
8443 just as you would with \\[verilog-auto-inst]."
8447 (indent-pt (save-excursion (verilog-backward-open-paren)
8448 (1+ (current-column))))
8449 (verilog-auto-inst-column (max verilog-auto-inst-column
8450 (+ 16 (* 8 (/ (+ indent-pt 7) 8)))))
8451 (modi (verilog-modi-current))
8452 (vector-skip-list (unless verilog-auto-inst-vector
8453 (verilog-modi-get-signals modi)))
8454 submod submodi inst skip-pins tpl-list tpl-num did-first)
8455 ;; Find module name that is instantiated
8456 (setq submod (save-excursion
8457 ;; Get to the point where AUTOINST normally is to read the module
8458 (verilog-re-search-forward-quick "[(;]" nil nil)
8459 (verilog-read-inst-module))
8460 inst (save-excursion
8461 ;; Get to the point where AUTOINST normally is to read the module
8462 (verilog-re-search-forward-quick "[(;]" nil nil)
8463 (verilog-read-inst-name))
8466 skip-pins (aref (verilog-read-inst-pins) 0))
8468 ;; Parse any AUTO_LISP() before here
8469 (verilog-read-auto-lisp (point-min) pt)
8471 ;; Lookup position, etc of submodule
8472 ;; Note this may raise an error
8473 (when (setq submodi (verilog-modi-lookup submod t))
8474 ;; If there's a number in the instantiation, it may be a argument to the
8475 ;; automatic variable instantiation program.
8476 (let* ((tpl-info (verilog-read-auto-template submod))
8477 (tpl-regexp (aref tpl-info 0)))
8478 (setq tpl-num (if (string-match tpl-regexp inst)
8479 (match-string 1 inst)
8481 tpl-list (aref tpl-info 1)))
8482 ;; Find submodule's signals and dump
8483 (let ((sig-list (verilog-signals-not-in
8484 (verilog-modi-get-gparams submodi)
8486 (vl-dir "parameter"))
8488 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
8489 (indent-to indent-pt)
8490 ;; Note these are searched for in verilog-read-sub-decls.
8491 (insert "// Parameters\n")
8492 (mapc (lambda (port)
8493 (verilog-auto-inst-port port indent-pt
8494 tpl-list tpl-num nil))
8499 (re-search-backward "," pt t)
8502 (search-forward "\n") ;; Added by inst-port
8503 (delete-backward-char 1)
8504 (if (search-forward ")" nil t) ;; From user, moved up a line
8505 (delete-backward-char 1)))))))))
8507 (defun verilog-auto-reg ()
8508 "Expand AUTOREG statements, as part of \\[verilog-auto].
8509 Make reg statements for any output that isn't already declared,
8510 and isn't a wire output from a block.
8513 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
8515 This does NOT work on memories, declare those yourself.
8519 module ExampReg (o,i)
8526 Typing \\[verilog-auto] will make this into:
8528 module ExampReg (o,i)
8532 // Beginning of automatic regs (for this module's undeclared outputs)
8534 // End of automatics
8538 ;; Point must be at insertion point.
8539 (let* ((indent-pt (current-indentation))
8540 (modi (verilog-modi-current))
8541 (sig-list (verilog-signals-not-in
8542 (verilog-modi-get-outputs modi)
8543 (append (verilog-modi-get-wires modi)
8544 (verilog-modi-get-regs modi)
8545 (verilog-modi-get-assigns modi)
8546 (verilog-modi-get-consts modi)
8547 (verilog-modi-get-gparams modi)
8548 (verilog-modi-get-sub-outputs modi)
8549 (verilog-modi-get-sub-inouts modi)))))
8552 (verilog-insert-indent "// Beginning of automatic regs (for this module's undeclared outputs)\n")
8553 (verilog-insert-definition sig-list "reg" indent-pt nil)
8554 (verilog-modi-cache-add-regs modi sig-list)
8555 (verilog-insert-indent "// End of automatics\n")))))
8557 (defun verilog-auto-reg-input ()
8558 "Expand AUTOREGINPUT statements, as part of \\[verilog-auto].
8559 Make reg statements instantiation inputs that aren't already declared.
8560 This is useful for making a top level shell for testing the module that is
8564 This ONLY detects inputs of AUTOINSTants (see `verilog-read-sub-decls').
8566 This does NOT work on memories, declare those yourself.
8568 An example (see `verilog-auto-inst' for what else is going on here):
8570 module ExampRegInput (o,i)
8578 Typing \\[verilog-auto] will make this into:
8580 module ExampRegInput (o,i)
8584 // Beginning of automatic reg inputs (for undeclared ...
8585 reg [31:0] iv; // From inst of inst.v
8586 // End of automatics
8595 ;; Point must be at insertion point.
8596 (let* ((indent-pt (current-indentation))
8597 (modi (verilog-modi-current))
8598 (sig-list (verilog-signals-combine-bus
8599 (verilog-signals-not-in
8600 (append (verilog-modi-get-sub-inputs modi)
8601 (verilog-modi-get-sub-inouts modi))
8602 (verilog-modi-get-signals modi)))))
8605 (verilog-insert-indent "// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)\n")
8606 (verilog-insert-definition sig-list "reg" indent-pt nil)
8607 (verilog-modi-cache-add-regs modi sig-list)
8608 (verilog-insert-indent "// End of automatics\n")))))
8610 (defun verilog-auto-wire ()
8611 "Expand AUTOWIRE statements, as part of \\[verilog-auto].
8612 Make wire statements for instantiations outputs that aren't
8616 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls'),
8617 and all busses must have widths, such as those from AUTOINST, or using []
8620 This does NOT work on memories or SystemVerilog .name connections,
8621 declare those yourself.
8623 Verilog mode will add \"Couldn't Merge\" comments to signals it cannot
8624 determine how to bus together. This occurs when you have ports with
8625 non-numeric or non-sequential bus subscripts. If Verilog mode
8626 mis-guessed, you'll have to declare them yourself.
8628 An example (see `verilog-auto-inst' for what else is going on here):
8630 module ExampWire (o,i)
8638 Typing \\[verilog-auto] will make this into:
8640 module ExampWire (o,i)
8644 // Beginning of automatic wires
8645 wire [31:0] ov; // From inst of inst.v
8646 // End of automatics
8656 ;; Point must be at insertion point.
8657 (let* ((indent-pt (current-indentation))
8658 (modi (verilog-modi-current))
8659 (sig-list (verilog-signals-combine-bus
8660 (verilog-signals-not-in
8661 (append (verilog-modi-get-sub-outputs modi)
8662 (verilog-modi-get-sub-inouts modi))
8663 (verilog-modi-get-signals modi)))))
8666 (verilog-insert-indent "// Beginning of automatic wires (for undeclared instantiated-module outputs)\n")
8667 (verilog-insert-definition sig-list "wire" indent-pt nil)
8668 (verilog-modi-cache-add-wires modi sig-list)
8669 (verilog-insert-indent "// End of automatics\n")
8670 (when nil ;; Too slow on huge modules, plus makes everyone's module change
8673 (verilog-pretty-declarations quiet)
8675 (verilog-pretty-expr "//"))))))
8677 (defun verilog-auto-output (&optional with-params)
8678 "Expand AUTOOUTPUT statements, as part of \\[verilog-auto].
8679 Make output statements for any output signal from an /*AUTOINST*/ that
8680 isn't a input to another AUTOINST. This is useful for modules which
8681 only instantiate other modules.
8684 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
8686 If placed inside the parenthesis of a module declaration, it creates
8687 Verilog 2001 style, else uses Verilog 1995 style.
8689 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
8690 instantiation, all bets are off. (For example due to a AUTO_TEMPLATE).
8692 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
8694 Signals matching `verilog-auto-output-ignore-regexp' are not included.
8696 An example (see `verilog-auto-inst' for what else is going on here):
8698 module ExampOutput (ov,i)
8705 Typing \\[verilog-auto] will make this into:
8707 module ExampOutput (ov,i)
8710 // Beginning of automatic outputs (from unused autoinst outputs)
8711 output [31:0] ov; // From inst of inst.v
8712 // End of automatics
8721 You may also provide an optional regular expression, in which case only
8722 signals matching the regular expression will be included. For example the
8723 same expansion will result from only extracting outputs starting with ov:
8725 /*AUTOOUTPUT(\"^ov\")*/"
8727 ;; Point must be at insertion point.
8728 (let* ((indent-pt (current-indentation))
8729 (regexp (and with-params
8730 (nth 0 (verilog-read-auto-params 1))))
8731 (v2k (verilog-in-paren))
8732 (modi (verilog-modi-current))
8733 (sig-list (verilog-signals-not-in
8734 (verilog-modi-get-sub-outputs modi)
8735 (append (verilog-modi-get-outputs modi)
8736 (verilog-modi-get-inouts modi)
8737 (verilog-modi-get-sub-inputs modi)
8738 (verilog-modi-get-sub-inouts modi)))))
8740 (setq sig-list (verilog-signals-matching-regexp
8742 (setq sig-list (verilog-signals-not-matching-regexp
8743 sig-list verilog-auto-output-ignore-regexp))
8745 (when v2k (verilog-repair-open-comma))
8747 (verilog-insert-indent "// Beginning of automatic outputs (from unused autoinst outputs)\n")
8748 (verilog-insert-definition sig-list "output" indent-pt v2k)
8749 (verilog-modi-cache-add-outputs modi sig-list)
8750 (verilog-insert-indent "// End of automatics\n"))
8751 (when v2k (verilog-repair-close-comma)))))
8753 (defun verilog-auto-output-every ()
8754 "Expand AUTOOUTPUTEVERY statements, as part of \\[verilog-auto].
8755 Make output statements for any signals that aren't primary inputs or
8756 outputs already. This makes every signal in the design a output. This is
8757 useful to get Synopsys to preserve every signal in the design, since it
8758 won't optimize away the outputs.
8762 module ExampOutputEvery (o,i,tempa,tempb)
8771 Typing \\[verilog-auto] will make this into:
8773 module ExampOutputEvery (o,i,tempa,tempb)
8777 // Beginning of automatic outputs (every signal)
8780 // End of automatics
8786 ;;Point must be at insertion point
8787 (let* ((indent-pt (current-indentation))
8788 (v2k (verilog-in-paren))
8789 (modi (verilog-modi-current))
8790 (sig-list (verilog-signals-combine-bus
8791 (verilog-signals-not-in
8792 (verilog-modi-get-signals modi)
8793 (verilog-modi-get-ports modi)))))
8795 (when v2k (verilog-repair-open-comma))
8797 (verilog-insert-indent "// Beginning of automatic outputs (every signal)\n")
8798 (verilog-insert-definition sig-list "output" indent-pt v2k)
8799 (verilog-modi-cache-add-outputs modi sig-list)
8800 (verilog-insert-indent "// End of automatics\n"))
8801 (when v2k (verilog-repair-close-comma)))))
8803 (defun verilog-auto-input (&optional with-params)
8804 "Expand AUTOINPUT statements, as part of \\[verilog-auto].
8805 Make input statements for any input signal into an /*AUTOINST*/ that
8806 isn't declared elsewhere inside the module. This is useful for modules which
8807 only instantiate other modules.
8810 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
8812 If placed inside the parenthesis of a module declaration, it creates
8813 Verilog 2001 style, else uses Verilog 1995 style.
8815 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
8816 instantiation, all bets are off. (For example due to a AUTO_TEMPLATE).
8818 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
8820 Signals matching `verilog-auto-input-ignore-regexp' are not included.
8822 An example (see `verilog-auto-inst' for what else is going on here):
8824 module ExampInput (ov,i)
8831 Typing \\[verilog-auto] will make this into:
8833 module ExampInput (ov,i)
8836 // Beginning of automatic inputs (from unused autoinst inputs)
8837 input i; // From inst of inst.v
8838 // End of automatics
8847 You may also provide an optional regular expression, in which case only
8848 signals matching the regular expression will be included. For example the
8849 same expansion will result from only extracting inputs starting with i:
8851 /*AUTOINPUT(\"^i\")*/"
8853 (let* ((indent-pt (current-indentation))
8854 (regexp (and with-params
8855 (nth 0 (verilog-read-auto-params 1))))
8856 (v2k (verilog-in-paren))
8857 (modi (verilog-modi-current))
8858 (sig-list (verilog-signals-not-in
8859 (verilog-modi-get-sub-inputs modi)
8860 (append (verilog-modi-get-inputs modi)
8861 (verilog-modi-get-inouts modi)
8862 (verilog-modi-get-wires modi)
8863 (verilog-modi-get-regs modi)
8864 (verilog-modi-get-consts modi)
8865 (verilog-modi-get-gparams modi)
8866 (verilog-modi-get-sub-outputs modi)
8867 (verilog-modi-get-sub-inouts modi)))))
8869 (setq sig-list (verilog-signals-matching-regexp
8871 (setq sig-list (verilog-signals-not-matching-regexp
8872 sig-list verilog-auto-input-ignore-regexp))
8874 (when v2k (verilog-repair-open-comma))
8876 (verilog-insert-indent "// Beginning of automatic inputs (from unused autoinst inputs)\n")
8877 (verilog-insert-definition sig-list "input" indent-pt v2k)
8878 (verilog-modi-cache-add-inputs modi sig-list)
8879 (verilog-insert-indent "// End of automatics\n"))
8880 (when v2k (verilog-repair-close-comma)))))
8882 (defun verilog-auto-inout (&optional with-params)
8883 "Expand AUTOINOUT statements, as part of \\[verilog-auto].
8884 Make inout statements for any inout signal in an /*AUTOINST*/ that
8885 isn't declared elsewhere inside the module.
8888 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
8890 If placed inside the parenthesis of a module declaration, it creates
8891 Verilog 2001 style, else uses Verilog 1995 style.
8893 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
8894 instantiation, all bets are off. (For example due to a AUTO_TEMPLATE).
8896 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
8898 Signals matching `verilog-auto-inout-ignore-regexp' are not included.
8900 An example (see `verilog-auto-inst' for what else is going on here):
8902 module ExampInout (ov,i)
8909 Typing \\[verilog-auto] will make this into:
8911 module ExampInout (ov,i)
8914 // Beginning of automatic inouts (from unused autoinst inouts)
8915 inout [31:0] ov; // From inst of inst.v
8916 // End of automatics
8925 You may also provide an optional regular expression, in which case only
8926 signals matching the regular expression will be included. For example the
8927 same expansion will result from only extracting inouts starting with i:
8929 /*AUTOINOUT(\"^i\")*/"
8931 ;; Point must be at insertion point.
8932 (let* ((indent-pt (current-indentation))
8933 (regexp (and with-params
8934 (nth 0 (verilog-read-auto-params 1))))
8935 (v2k (verilog-in-paren))
8936 (modi (verilog-modi-current))
8937 (sig-list (verilog-signals-not-in
8938 (verilog-modi-get-sub-inouts modi)
8939 (append (verilog-modi-get-outputs modi)
8940 (verilog-modi-get-inouts modi)
8941 (verilog-modi-get-inputs modi)
8942 (verilog-modi-get-sub-inputs modi)
8943 (verilog-modi-get-sub-outputs modi)))))
8945 (setq sig-list (verilog-signals-matching-regexp
8947 (setq sig-list (verilog-signals-not-matching-regexp
8948 sig-list verilog-auto-inout-ignore-regexp))
8950 (when v2k (verilog-repair-open-comma))
8952 (verilog-insert-indent "// Beginning of automatic inouts (from unused autoinst inouts)\n")
8953 (verilog-insert-definition sig-list "inout" indent-pt v2k)
8954 (verilog-modi-cache-add-inouts modi sig-list)
8955 (verilog-insert-indent "// End of automatics\n"))
8956 (when v2k (verilog-repair-close-comma)))))
8958 (defun verilog-auto-inout-module ()
8959 "Expand AUTOINOUTMODULE statements, as part of \\[verilog-auto].
8960 Take input/output/inout statements from the specified module and insert
8961 into the current module. This is useful for making null templates and
8962 shell modules which need to have identical I/O with another module.
8963 Any I/O which are already defined in this module will not be redefined.
8966 If placed inside the parenthesis of a module declaration, it creates
8967 Verilog 2001 style, else uses Verilog 1995 style.
8969 Concatenation and outputting partial busses is not supported.
8971 Module names must be resolvable to filenames. See `verilog-auto-inst'.
8973 Signals are not inserted in the same order as in the original module,
8974 though they will appear to be in the same order to a AUTOINST
8975 instantiating either module.
8979 module ExampShell (/*AUTOARG*/)
8980 /*AUTOINOUTMODULE(\"ExampMain\")*/
8983 module ExampMain (i,o,io)
8989 Typing \\[verilog-auto] will make this into:
8991 module ExampShell (/*AUTOARG*/i,o,io)
8992 /*AUTOINOUTMODULE(\"ExampMain\")*/
8993 // Beginning of automatic in/out/inouts (from specific module)
8997 // End of automatics
9000 You may also provide an optional regular expression, in which case only
9001 signals matching the regular expression will be included. For example the
9002 same expansion will result from only extracting signals starting with i:
9004 /*AUTOINOUTMODULE(\"ExampMain\",\"^i\")*/"
9006 (let* ((params (verilog-read-auto-params 1 2))
9007 (submod (nth 0 params))
9008 (regexp (nth 1 params))
9010 ;; Lookup position, etc of co-module
9011 ;; Note this may raise an error
9012 (when (setq submodi (verilog-modi-lookup submod t))
9013 (let* ((indent-pt (current-indentation))
9014 (v2k (verilog-in-paren))
9015 (modi (verilog-modi-current))
9016 (sig-list-i (verilog-signals-not-in
9017 (verilog-modi-get-inputs submodi)
9018 (append (verilog-modi-get-inputs modi))))
9019 (sig-list-o (verilog-signals-not-in
9020 (verilog-modi-get-outputs submodi)
9021 (append (verilog-modi-get-outputs modi))))
9022 (sig-list-io (verilog-signals-not-in
9023 (verilog-modi-get-inouts submodi)
9024 (append (verilog-modi-get-inouts modi)))))
9027 (setq sig-list-i (verilog-signals-matching-regexp
9029 sig-list-o (verilog-signals-matching-regexp
9031 sig-list-io (verilog-signals-matching-regexp
9032 sig-list-io regexp)))
9033 (when v2k (verilog-repair-open-comma))
9034 (when (or sig-list-i sig-list-o sig-list-io)
9035 (verilog-insert-indent "// Beginning of automatic in/out/inouts (from specific module)\n")
9036 ;; Don't sort them so a upper AUTOINST will match the main module
9037 (verilog-insert-definition sig-list-o "output" indent-pt v2k t)
9038 (verilog-insert-definition sig-list-io "inout" indent-pt v2k t)
9039 (verilog-insert-definition sig-list-i "input" indent-pt v2k t)
9040 (verilog-modi-cache-add-inputs modi sig-list-i)
9041 (verilog-modi-cache-add-outputs modi sig-list-o)
9042 (verilog-modi-cache-add-inouts modi sig-list-io)
9043 (verilog-insert-indent "// End of automatics\n"))
9044 (when v2k (verilog-repair-close-comma)))))))
9046 (defun verilog-auto-sense-sigs (modi presense-sigs)
9047 "Return list of signals for current AUTOSENSE block."
9048 (let* ((sigss (verilog-read-always-signals))
9049 (sig-list (verilog-signals-not-params
9050 (verilog-signals-not-in (verilog-alw-get-inputs sigss)
9051 (append (and (not verilog-auto-sense-include-inputs)
9052 (verilog-alw-get-outputs sigss))
9053 (verilog-modi-get-consts modi)
9054 (verilog-modi-get-gparams modi)
9058 (defun verilog-auto-sense ()
9059 "Expand AUTOSENSE statements, as part of \\[verilog-auto].
9060 Replace the always (/*AUTOSENSE*/) sensitivity list (/*AS*/ for short)
9061 with one automatically derived from all inputs declared in the always
9062 statement. Signals that are generated within the same always block are NOT
9063 placed into the sensitivity list (see `verilog-auto-sense-include-inputs').
9064 Long lines are split based on the `fill-column', see \\[set-fill-column].
9067 Verilog does not allow memories (multidimensional arrays) in sensitivity
9068 lists. AUTOSENSE will thus exclude them, and add a /*memory or*/ comment.
9071 AUTOSENSE cannot always determine if a `define is a constant or a signal
9072 (it could be in a include file for example). If a `define or other signal
9073 is put into the AUTOSENSE list and is not desired, use the AUTO_CONSTANT
9074 declaration anywhere in the module (parenthesis are required):
9076 /* AUTO_CONSTANT ( `this_is_really_constant_dont_autosense_it ) */
9078 Better yet, use a parameter, which will be understood to be constant
9082 If AUTOSENSE makes a mistake, please report it. (First try putting
9083 a begin/end after your always!) As a workaround, if a signal that
9084 shouldn't be in the sensitivity list was, use the AUTO_CONSTANT above.
9085 If a signal should be in the sensitivity list wasn't, placing it before
9086 the /*AUTOSENSE*/ comment will prevent it from being deleted when the
9087 autos are updated (or added if it occurs there already).
9091 always @ (/*AS*/) begin
9092 /* AUTO_CONSTANT (`constant) */
9093 outin = ina | inb | `constant;
9097 Typing \\[verilog-auto] will make this into:
9099 always @ (/*AS*/ina or inb) begin
9100 /* AUTO_CONSTANT (`constant) */
9101 outin = ina | inb | `constant;
9105 Note in Verilog 2001, you can often get the same result from the new @*
9106 operator. (This was added to the language in part due to AUTOSENSE!)
9109 outin = ina | inb | `constant;
9114 (let* ((start-pt (save-excursion
9115 (verilog-re-search-backward "(" nil t)
9117 (indent-pt (save-excursion
9118 (or (and (goto-char start-pt) (1+ (current-column)))
9119 (current-indentation))))
9120 (modi (verilog-modi-current))
9121 (sig-memories (verilog-signals-memory
9123 (verilog-modi-get-regs modi)
9124 (verilog-modi-get-wires modi))))
9125 sig-list not-first presense-sigs)
9126 ;; Read signals in always, eliminate outputs from sense list
9127 (setq presense-sigs (verilog-signals-from-signame
9129 (verilog-read-signals start-pt (point)))))
9130 (setq sig-list (verilog-auto-sense-sigs modi presense-sigs))
9132 (let ((tlen (length sig-list)))
9133 (setq sig-list (verilog-signals-not-in sig-list sig-memories))
9134 (if (not (eq tlen (length sig-list))) (insert " /*memory or*/ "))))
9135 (if (and presense-sigs ;; Add a "or" if not "(.... or /*AUTOSENSE*/"
9136 (save-excursion (goto-char (point))
9137 (verilog-re-search-backward "[a-zA-Z0-9$_.%`]+" start-pt t)
9138 (verilog-re-search-backward "\\s-" start-pt t)
9139 (while (looking-at "\\s-`endif")
9140 (verilog-re-search-backward "[a-zA-Z0-9$_.%`]+" start-pt t)
9141 (verilog-re-search-backward "\\s-" start-pt t))
9142 (not (looking-at "\\s-or\\b"))))
9144 (setq sig-list (sort sig-list `verilog-signals-sort-compare))
9146 (cond ((> (+ 4 (current-column) (length (verilog-sig-name (car sig-list)))) fill-column) ;+4 for width of or
9148 (indent-to indent-pt)
9149 (if not-first (insert "or ")))
9150 (not-first (insert " or ")))
9151 (insert (verilog-sig-name (car sig-list)))
9152 (setq sig-list (cdr sig-list)
9155 (defun verilog-auto-reset ()
9156 "Expand AUTORESET statements, as part of \\[verilog-auto].
9157 Replace the /*AUTORESET*/ comment with code to initialize all
9158 registers set elsewhere in the always block.
9161 AUTORESET will not clear memories.
9163 AUTORESET uses <= if there are any <= in the block, else it uses =.
9165 /*AUTORESET*/ presumes that any signals mentioned between the previous
9166 begin/case/if statement and the AUTORESET comment are being reset manually
9167 and should not be automatically reset. This includes omitting any signals
9168 used on the right hand side of assignments.
9170 By default, AUTORESET will include the width of the signal in the autos,
9171 this is a recent change. To control this behavior, see
9172 `verilog-auto-reset-widths'.
9174 AUTORESET ties signals to deasserted, which is presumed to be zero.
9175 Signals that match `verilog-active-low-regexp' will be deasserted by tieing
9180 always @(posedge clk or negedge reset_l) begin
9192 Typing \\[verilog-auto] will make this into:
9194 always @(posedge core_clk or negedge reset_l) begin
9198 // Beginning of autoreset for uninitialized flops
9201 // End of automatics
9213 (let* ((indent-pt (current-indentation))
9214 (modi (verilog-modi-current))
9215 (all-list (verilog-modi-get-signals modi))
9216 sigss sig-list prereset-sigs assignment-str)
9217 ;; Read signals in always, eliminate outputs from reset list
9218 (setq prereset-sigs (verilog-signals-from-signame
9220 (verilog-read-signals
9222 (verilog-re-search-backward "\\(@\\|\\<begin\\>\\|\\<if\\>\\|\\<case\\>\\)" nil t)
9226 (verilog-re-search-backward "@" nil t)
9227 (setq sigss (verilog-read-always-signals)))
9228 (setq assignment-str (if (verilog-alw-get-uses-delayed sigss)
9229 (concat " <= " verilog-assignment-delay)
9231 (setq sig-list (verilog-signals-not-in (verilog-alw-get-outputs sigss)
9233 (setq sig-list (sort sig-list `verilog-signals-sort-compare))
9236 (indent-to indent-pt)
9237 (insert "// Beginning of autoreset for uninitialized flops\n");
9238 (indent-to indent-pt)
9240 (let ((sig (or (assoc (verilog-sig-name (car sig-list)) all-list) ;; As sig-list has no widths
9242 (insert (verilog-sig-name sig)
9244 (verilog-sig-tieoff sig (not verilog-auto-reset-widths))
9246 (indent-to indent-pt)
9247 (setq sig-list (cdr sig-list))))
9248 (insert "// End of automatics")))))
9250 (defun verilog-auto-tieoff ()
9251 "Expand AUTOTIEOFF statements, as part of \\[verilog-auto].
9252 Replace the /*AUTOTIEOFF*/ comment with code to wire-tie all unused output
9253 signals to deasserted.
9255 /*AUTOTIEOFF*/ is used to make stub modules; modules that have the same
9256 input/output list as another module, but no internals. Specifically, it
9257 finds all outputs in the module, and if that input is not otherwise declared
9258 as a register or wire, creates a tieoff.
9260 AUTORESET ties signals to deasserted, which is presumed to be zero.
9261 Signals that match `verilog-active-low-regexp' will be deasserted by tieing
9264 An example of making a stub for another module:
9266 module ExampStub (/*AUTOINST*/);
9267 /*AUTOINOUTMODULE(\"Foo\")*/
9269 // verilator lint_off UNUSED
9270 wire _unused_ok = &{1'b0,
9273 // verilator lint_on UNUSED
9276 Typing \\[verilog-auto] will make this into:
9278 module ExampStub (/*AUTOINST*/...);
9279 /*AUTOINOUTMODULE(\"Foo\")*/
9280 // Beginning of autotieoff
9282 // End of automatics
9285 // Beginning of autotieoff
9286 wire [2:0] foo = 3'b0;
9287 // End of automatics
9293 (let* ((indent-pt (current-indentation))
9294 (modi (verilog-modi-current))
9295 (sig-list (verilog-signals-not-in
9296 (verilog-modi-get-outputs modi)
9297 (append (verilog-modi-get-wires modi)
9298 (verilog-modi-get-regs modi)
9299 (verilog-modi-get-assigns modi)
9300 (verilog-modi-get-consts modi)
9301 (verilog-modi-get-gparams modi)
9302 (verilog-modi-get-sub-outputs modi)
9303 (verilog-modi-get-sub-inouts modi)))))
9306 (verilog-insert-indent "// Beginning of automatic tieoffs (for this module's unterminated outputs)\n")
9307 (setq sig-list (sort (copy-alist sig-list) `verilog-signals-sort-compare))
9308 (verilog-modi-cache-add-wires modi sig-list) ; Before we trash list
9310 (let ((sig (car sig-list)))
9311 (verilog-insert-one-definition sig "wire" indent-pt)
9312 (indent-to (max 48 (+ indent-pt 40)))
9313 (insert "= " (verilog-sig-tieoff sig)
9315 (setq sig-list (cdr sig-list))))
9316 (verilog-insert-indent "// End of automatics\n")))))
9318 (defun verilog-auto-unused ()
9319 "Expand AUTOUNUSED statements, as part of \\[verilog-auto].
9320 Replace the /*AUTOUNUSED*/ comment with a comma separated list of all unused
9321 input and inout signals.
9323 /*AUTOUNUSED*/ is used to make stub modules; modules that have the same
9324 input/output list as another module, but no internals. Specifically, it
9325 finds all inputs and inouts in the module, and if that input is not otherwise
9326 used, adds it to a comma separated list.
9328 The comma separated list is intended to be used to create a _unused_ok
9329 signal. Using the exact name \"_unused_ok\" for name of the temporary
9330 signal is recommended as it will insure maximum forward compatibility, it
9331 also makes lint warnings easy to understand; ignore any unused warnings
9332 with \"unused\" in the signal name.
9334 To reduce simulation time, the _unused_ok signal should be forced to a
9335 constant to prevent wiggling. The easiest thing to do is use a
9336 reduction-and with 1'b0 as shown.
9338 This way all unused signals are in one place, making it convenient to add
9339 your tool's specific pragmas around the assignment to disable any unused
9342 You can add signals you do not want included in AUTOUNUSED with
9343 `verilog-auto-unused-ignore-regexp'.
9345 An example of making a stub for another module:
9347 module ExampStub (/*AUTOINST*/);
9348 /*AUTOINOUTMODULE(\"Examp\")*/
9350 // verilator lint_off UNUSED
9351 wire _unused_ok = &{1'b0,
9354 // verilator lint_on UNUSED
9357 Typing \\[verilog-auto] will make this into:
9360 // verilator lint_off UNUSED
9361 wire _unused_ok = &{1'b0,
9363 // Beginning of automatics
9367 // End of automatics
9369 // verilator lint_on UNUSED
9374 (let* ((indent-pt (progn (search-backward "/*") (current-column)))
9375 (modi (verilog-modi-current))
9376 (sig-list (verilog-signals-not-in
9377 (append (verilog-modi-get-inputs modi)
9378 (verilog-modi-get-inouts modi))
9379 (append (verilog-modi-get-sub-inputs modi)
9380 (verilog-modi-get-sub-inouts modi)))))
9381 (setq sig-list (verilog-signals-not-matching-regexp
9382 sig-list verilog-auto-unused-ignore-regexp))
9385 (verilog-insert-indent "// Beginning of automatic unused inputs\n")
9386 (setq sig-list (sort (copy-alist sig-list) `verilog-signals-sort-compare))
9388 (let ((sig (car sig-list)))
9389 (indent-to indent-pt)
9390 (insert (verilog-sig-name sig) ",\n")
9391 (setq sig-list (cdr sig-list))))
9392 (verilog-insert-indent "// End of automatics\n")))))
9394 (defun verilog-enum-ascii (signm elim-regexp)
9395 "Convert an enum name SIGNM to an ascii string for insertion.
9396 Remove user provided prefix ELIM-REGEXP."
9397 (or elim-regexp (setq elim-regexp "_ DONT MATCH IT_"))
9398 (let ((case-fold-search t))
9399 ;; All upper becomes all lower for readability
9400 (downcase (verilog-string-replace-matches elim-regexp "" nil nil signm))))
9402 (defun verilog-auto-ascii-enum ()
9403 "Expand AUTOASCIIENUM statements, as part of \\[verilog-auto].
9404 Create a register to contain the ASCII decode of a enumerated signal type.
9405 This will allow trace viewers to show the ASCII name of states.
9407 First, parameters are built into a enumeration using the synopsys enum
9408 comment. The comment must be between the keyword and the symbol.
9409 \(Annoying, but that's what Synopsys's dc_shell FSM reader requires.)
9411 Next, registers which that enum applies to are also tagged with the same
9412 enum. Synopsys also suggests labeling state vectors, but `verilog-mode'
9415 Finally, a AUTOASCIIENUM command is used.
9417 The first parameter is the name of the signal to be decoded.
9419 The second parameter is the name to store the ASCII code into. For the
9420 signal foo, I suggest the name _foo__ascii, where the leading _ indicates
9421 a signal that is just for simulation, and the magic characters _ascii
9422 tell viewers like Dinotrace to display in ASCII format.
9424 The final optional parameter is a string which will be removed from the
9429 //== State enumeration
9430 parameter [2:0] // synopsys enum state_info
9434 //== State variables
9435 reg [2:0] /* synopsys enum state_info */
9436 state_r; /* synopsys state_vector state_r */
9437 reg [2:0] /* synopsys enum state_info */
9440 //== ASCII state decoding
9442 /*AUTOASCIIENUM(\"state_r\", \"state_ascii_r\", \"SM_\")*/
9444 Typing \\[verilog-auto] will make this into:
9446 ... same front matter ...
9448 /*AUTOASCIIENUM(\"state_r\", \"state_ascii_r\", \"SM_\")*/
9449 // Beginning of automatic ASCII enum decoding
9450 reg [39:0] state_ascii_r; // Decode of state_r
9451 always @(state_r) begin
9453 SM_IDLE: state_ascii_r = \"idle \";
9454 SM_SEND: state_ascii_r = \"send \";
9455 SM_WAIT1: state_ascii_r = \"wait1\";
9456 default: state_ascii_r = \"%Erro\";
9459 // End of automatics"
9461 (let* ((params (verilog-read-auto-params 2 3))
9462 (undecode-name (nth 0 params))
9463 (ascii-name (nth 1 params))
9464 (elim-regexp (nth 2 params))
9466 (indent-pt (current-indentation))
9467 (modi (verilog-modi-current))
9469 (sig-list-consts (append (verilog-modi-get-consts modi)
9470 (verilog-modi-get-gparams modi)))
9471 (sig-list-all (append (verilog-modi-get-regs modi)
9472 (verilog-modi-get-outputs modi)
9473 (verilog-modi-get-inouts modi)
9474 (verilog-modi-get-inputs modi)
9475 (verilog-modi-get-wires modi)))
9477 (undecode-sig (or (assoc undecode-name sig-list-all)
9478 (error "%s: Signal %s not found in design" (verilog-point-text) undecode-name)))
9479 (undecode-enum (or (verilog-sig-enum undecode-sig)
9480 (error "%s: Signal %s does not have a enum tag" (verilog-point-text) undecode-name)))
9482 (enum-sigs (or (verilog-signals-matching-enum sig-list-consts undecode-enum)
9483 (error "%s: No state definitions for %s" (verilog-point-text) undecode-enum)))
9488 ;; Find number of ascii chars needed
9489 (let ((tmp-sigs enum-sigs))
9491 (setq enum-chars (max enum-chars (length (verilog-sig-name (car tmp-sigs))))
9492 ascii-chars (max ascii-chars (length (verilog-enum-ascii
9493 (verilog-sig-name (car tmp-sigs))
9495 tmp-sigs (cdr tmp-sigs))))
9498 (verilog-insert-indent "// Beginning of automatic ASCII enum decoding\n")
9499 (let ((decode-sig-list (list (list ascii-name (format "[%d:0]" (- (* ascii-chars 8) 1))
9500 (concat "Decode of " undecode-name) nil nil))))
9501 (verilog-insert-definition decode-sig-list "reg" indent-pt nil)
9502 (verilog-modi-cache-add-regs modi decode-sig-list))
9504 (verilog-insert-indent "always @(" undecode-name ") begin\n")
9505 (setq indent-pt (+ indent-pt verilog-indent-level))
9506 (indent-to indent-pt)
9507 (insert "case ({" undecode-name "})\n")
9508 (setq indent-pt (+ indent-pt verilog-case-indent))
9510 (let ((tmp-sigs enum-sigs)
9511 (chrfmt (format "%%-%ds %s = \"%%-%ds\";\n" (1+ (max 8 enum-chars))
9512 ascii-name ascii-chars))
9513 (errname (substring "%Error" 0 (min 6 ascii-chars))))
9515 (verilog-insert-indent
9516 (format chrfmt (concat (verilog-sig-name (car tmp-sigs)) ":")
9517 (verilog-enum-ascii (verilog-sig-name (car tmp-sigs))
9519 (setq tmp-sigs (cdr tmp-sigs)))
9520 (verilog-insert-indent (format chrfmt "default:" errname)))
9522 (setq indent-pt (- indent-pt verilog-case-indent))
9523 (verilog-insert-indent "endcase\n")
9524 (setq indent-pt (- indent-pt verilog-indent-level))
9525 (verilog-insert-indent "end\n"
9526 "// End of automatics\n"))))
9528 (defun verilog-auto-templated-rel ()
9529 "Replace Templated relative line numbers with absolute line numbers.
9530 Internal use only. This hacks around the line numbers in AUTOINST Templates
9531 being different from the final output's line numbering."
9532 (let ((templateno 0) (template-line (list 0)))
9533 ;; Find line number each template is on
9534 (goto-char (point-min))
9535 (while (search-forward "AUTO_TEMPLATE" nil t)
9536 (setq templateno (1+ templateno))
9538 (cons (count-lines (point-min) (point)) template-line)))
9539 (setq template-line (nreverse template-line))
9540 ;; Replace T# L# with absolute line number
9541 (goto-char (point-min))
9542 (while (re-search-forward " Templated T\\([0-9]+\\) L\\([0-9]+\\)" nil t)
9544 (concat " Templated "
9545 (int-to-string (+ (nth (string-to-number (match-string 1))
9547 (string-to-number (match-string 2)))))
9555 (defun verilog-auto (&optional inject) ; Use verilog-inject-auto instead of passing a arg
9556 "Expand AUTO statements.
9557 Look for any /*AUTO...*/ commands in the code, as used in
9558 instantiations or argument headers. Update the list of signals
9559 following the /*AUTO...*/ command.
9561 Use \\[verilog-delete-auto] to remove the AUTOs.
9563 Use \\[verilog-inject-auto] to insert AUTOs for the first time.
9565 Use \\[verilog-faq] for a pointer to frequently asked questions.
9567 The hooks `verilog-before-auto-hook' and `verilog-auto-hook' are
9568 called before and after this function, respectively.
9571 module ModuleName (/*AUTOARG*/)
9576 InstMod instName #(/*AUTOINSTPARAM*/) (/*AUTOINST*/);
9578 You can also update the AUTOs from the shell using:
9579 emacs --batch <filenames.v> -f verilog-batch-auto
9580 Or fix indentation with:
9581 emacs --batch <filenames.v> -f verilog-batch-indent
9582 Likewise, you can delete or inject AUTOs with:
9583 emacs --batch <filenames.v> -f verilog-batch-delete-auto
9584 emacs --batch <filenames.v> -f verilog-batch-inject-auto
9586 Using \\[describe-function], see also:
9587 `verilog-auto-arg' for AUTOARG module instantiations
9588 `verilog-auto-ascii-enum' for AUTOASCIIENUM enumeration decoding
9589 `verilog-auto-inout-module' for AUTOINOUTMODULE copying i/o from elsewhere
9590 `verilog-auto-inout' for AUTOINOUT making hierarchy inouts
9591 `verilog-auto-input' for AUTOINPUT making hierarchy inputs
9592 `verilog-auto-inst' for AUTOINST instantiation pins
9593 `verilog-auto-star' for AUTOINST .* SystemVerilog pins
9594 `verilog-auto-inst-param' for AUTOINSTPARAM instantiation params
9595 `verilog-auto-output' for AUTOOUTPUT making hierarchy outputs
9596 `verilog-auto-output-every' for AUTOOUTPUTEVERY making all outputs
9597 `verilog-auto-reg' for AUTOREG registers
9598 `verilog-auto-reg-input' for AUTOREGINPUT instantiation registers
9599 `verilog-auto-reset' for AUTORESET flop resets
9600 `verilog-auto-sense' for AUTOSENSE always sensitivity lists
9601 `verilog-auto-tieoff' for AUTOTIEOFF output tieoffs
9602 `verilog-auto-unused' for AUTOUNUSED unused inputs/inouts
9603 `verilog-auto-wire' for AUTOWIRE instantiation wires
9605 `verilog-read-defines' for reading `define values
9606 `verilog-read-includes' for reading `includes
9608 If you have bugs with these autos, try contacting the AUTOAUTHOR
9609 Wilson Snyder (wsnyder@wsnyder.org), and/or see http://www.veripool.com."
9611 (unless noninteractive (message "Updating AUTOs..."))
9612 (if (fboundp 'dinotrace-unannotate-all)
9613 (dinotrace-unannotate-all))
9614 (let ((oldbuf (if (not (buffer-modified-p))
9616 ;; Before version 20, match-string with font-lock returns a
9617 ;; vector that is not equal to the string. IE if on "input"
9618 ;; nil==(equal "input" (progn (looking-at "input") (match-string 0)))
9619 (fontlocked (when (and (boundp 'font-lock-mode)
9621 (font-lock-mode nil)
9625 ;; If we're not in verilog-mode, change syntax table so parsing works right
9626 (unless (eq major-mode `verilog-mode) (verilog-mode))
9627 ;; Allow user to customize
9628 (run-hooks 'verilog-before-auto-hook)
9629 ;; Try to save the user from needing to revert-file to reread file local-variables
9630 (verilog-auto-reeval-locals)
9631 (verilog-read-auto-lisp (point-min) (point-max))
9632 (verilog-getopt-flags)
9633 ;; These two may seem obvious to do always, but on large includes it can be way too slow
9634 (when verilog-auto-read-includes
9635 (verilog-read-includes)
9636 (verilog-read-defines nil nil t))
9637 ;; This particular ordering is important
9638 ;; INST: Lower modules correct, no internal dependencies, FIRST
9639 (verilog-preserve-cache
9640 ;; Clear existing autos else we'll be screwed by existing ones
9641 (verilog-delete-auto)
9642 ;; Injection if appropriate
9644 (verilog-inject-inst)
9645 (verilog-inject-sense)
9646 (verilog-inject-arg))
9648 (verilog-auto-search-do "/*AUTOINSTPARAM*/" 'verilog-auto-inst-param)
9649 (verilog-auto-search-do "/*AUTOINST*/" 'verilog-auto-inst)
9650 (verilog-auto-search-do ".*" 'verilog-auto-star)
9651 ;; Doesn't matter when done, but combine it with a common changer
9652 (verilog-auto-re-search-do "/\\*\\(AUTOSENSE\\|AS\\)\\*/" 'verilog-auto-sense)
9653 (verilog-auto-re-search-do "/\\*AUTORESET\\*/" 'verilog-auto-reset)
9654 ;; Must be done before autoin/out as creates a reg
9655 (verilog-auto-re-search-do "/\\*AUTOASCIIENUM([^)]*)\\*/" 'verilog-auto-ascii-enum)
9657 ;; first in/outs from other files
9658 (verilog-auto-re-search-do "/\\*AUTOINOUTMODULE([^)]*)\\*/" 'verilog-auto-inout-module)
9659 ;; next in/outs which need previous sucked inputs first
9660 (verilog-auto-re-search-do "/\\*AUTOOUTPUT\\((\"[^\"]*\")\\)\\*/"
9661 '(lambda () (verilog-auto-output t)))
9662 (verilog-auto-re-search-do "/\\*AUTOOUTPUT\\*/" 'verilog-auto-output)
9663 (verilog-auto-re-search-do "/\\*AUTOINPUT\\((\"[^\"]*\")\\)\\*/"
9664 '(lambda () (verilog-auto-input t)))
9665 (verilog-auto-re-search-do "/\\*AUTOINPUT\\*/" 'verilog-auto-input)
9666 (verilog-auto-re-search-do "/\\*AUTOINOUT\\((\"[^\"]*\")\\)\\*/"
9667 '(lambda () (verilog-auto-inout t)))
9668 (verilog-auto-re-search-do "/\\*AUTOINOUT\\*/" 'verilog-auto-inout)
9669 ;; Then tie off those in/outs
9670 (verilog-auto-search-do "/*AUTOTIEOFF*/" 'verilog-auto-tieoff)
9671 ;; Wires/regs must be after inputs/outputs
9672 (verilog-auto-search-do "/*AUTOWIRE*/" 'verilog-auto-wire)
9673 (verilog-auto-search-do "/*AUTOREG*/" 'verilog-auto-reg)
9674 (verilog-auto-search-do "/*AUTOREGINPUT*/" 'verilog-auto-reg-input)
9675 ;; outputevery needs AUTOOUTPUTs done first
9676 (verilog-auto-search-do "/*AUTOOUTPUTEVERY*/" 'verilog-auto-output-every)
9677 ;; After we've created all new variables
9678 (verilog-auto-search-do "/*AUTOUNUSED*/" 'verilog-auto-unused)
9679 ;; Must be after all inputs outputs are generated
9680 (verilog-auto-search-do "/*AUTOARG*/" 'verilog-auto-arg)
9681 ;; Fix line numbers (comments only)
9682 (verilog-auto-templated-rel))
9684 (run-hooks 'verilog-auto-hook)
9686 (set (make-local-variable 'verilog-auto-update-tick) (buffer-modified-tick))
9688 ;; If end result is same as when started, clear modified flag
9689 (cond ((and oldbuf (equal oldbuf (buffer-string)))
9690 (set-buffer-modified-p nil)
9691 (unless noninteractive (message "Updating AUTOs...done (no changes)")))
9692 (t (unless noninteractive (message "Updating AUTOs...done")))))
9695 ;; Restore font-lock
9696 (when fontlocked (font-lock-mode t))))))
9700 ;; Skeleton based code insertion
9702 (defvar verilog-template-map
9703 (let ((map (make-sparse-keymap)))
9704 (define-key map "a" 'verilog-sk-always)
9705 (define-key map "b" 'verilog-sk-begin)
9706 (define-key map "c" 'verilog-sk-case)
9707 (define-key map "f" 'verilog-sk-for)
9708 (define-key map "g" 'verilog-sk-generate)
9709 (define-key map "h" 'verilog-sk-header)
9710 (define-key map "i" 'verilog-sk-initial)
9711 (define-key map "j" 'verilog-sk-fork)
9712 (define-key map "m" 'verilog-sk-module)
9713 (define-key map "p" 'verilog-sk-primitive)
9714 (define-key map "r" 'verilog-sk-repeat)
9715 (define-key map "s" 'verilog-sk-specify)
9716 (define-key map "t" 'verilog-sk-task)
9717 (define-key map "w" 'verilog-sk-while)
9718 (define-key map "x" 'verilog-sk-casex)
9719 (define-key map "z" 'verilog-sk-casez)
9720 (define-key map "?" 'verilog-sk-if)
9721 (define-key map ":" 'verilog-sk-else-if)
9722 (define-key map "/" 'verilog-sk-comment)
9723 (define-key map "A" 'verilog-sk-assign)
9724 (define-key map "F" 'verilog-sk-function)
9725 (define-key map "I" 'verilog-sk-input)
9726 (define-key map "O" 'verilog-sk-output)
9727 (define-key map "S" 'verilog-sk-state-machine)
9728 (define-key map "=" 'verilog-sk-inout)
9729 (define-key map "W" 'verilog-sk-wire)
9730 (define-key map "R" 'verilog-sk-reg)
9731 (define-key map "D" 'verilog-sk-define-signal)
9733 "Keymap used in Verilog mode for smart template operations.")
9737 ;; Place the templates into Verilog Mode. They may be inserted under any key.
9738 ;; C-c C-t will be the default. If you use templates a lot, you
9739 ;; may want to consider moving the binding to another key in your .emacs
9742 ;(define-key verilog-mode-map "\C-ct" verilog-template-map)
9743 (define-key verilog-mode-map "\C-c\C-t" verilog-template-map)
9745 ;;; ---- statement skeletons ------------------------------------------
9747 (define-skeleton verilog-sk-prompt-condition
9748 "Prompt for the loop condition."
9749 "[condition]: " str )
9751 (define-skeleton verilog-sk-prompt-init
9752 "Prompt for the loop init statement."
9753 "[initial statement]: " str )
9755 (define-skeleton verilog-sk-prompt-inc
9756 "Prompt for the loop increment statement."
9757 "[increment statement]: " str )
9759 (define-skeleton verilog-sk-prompt-name
9760 "Prompt for the name of something."
9763 (define-skeleton verilog-sk-prompt-clock
9764 "Prompt for the name of something."
9765 "name and edge of clock(s): " str)
9767 (defvar verilog-sk-reset nil)
9768 (defun verilog-sk-prompt-reset ()
9769 "Prompt for the name of a state machine reset."
9770 (setq verilog-sk-reset (read-string "name of reset: " "rst")))
9773 (define-skeleton verilog-sk-prompt-state-selector
9774 "Prompt for the name of a state machine selector."
9775 "name of selector (eg {a,b,c,d}): " str )
9777 (define-skeleton verilog-sk-prompt-output
9778 "Prompt for the name of something."
9781 (define-skeleton verilog-sk-prompt-msb
9782 "Prompt for least significant bit specification."
9783 "msb:" str & ?: & '(verilog-sk-prompt-lsb) | -1 )
9785 (define-skeleton verilog-sk-prompt-lsb
9786 "Prompt for least significant bit specification."
9789 (defvar verilog-sk-p nil)
9790 (define-skeleton verilog-sk-prompt-width
9791 "Prompt for a width specification."
9794 (setq verilog-sk-p (point))
9795 (verilog-sk-prompt-msb)
9796 (if (> (point) verilog-sk-p) "] " " ")))
9798 (defun verilog-sk-header ()
9799 "Insert a descriptive header at the top of the file."
9802 (goto-char (point-min))
9803 (verilog-sk-header-tmpl)))
9805 (define-skeleton verilog-sk-header-tmpl
9806 "Insert a comment block containing the module title, author, etc."
9808 "// -*- Mode: Verilog -*-"
9809 "\n// Filename : " (buffer-name)
9810 "\n// Description : " str
9811 "\n// Author : " (user-full-name)
9812 "\n// Created On : " (current-time-string)
9813 "\n// Last Modified By: ."
9814 "\n// Last Modified On: ."
9815 "\n// Update Count : 0"
9816 "\n// Status : Unknown, Use with caution!"
9819 (define-skeleton verilog-sk-module
9820 "Insert a module definition."
9822 > "module " '(verilog-sk-prompt-name) " (/*AUTOARG*/ ) ;" \n
9824 > (- verilog-indent-level-behavioral) "endmodule" (progn (electric-verilog-terminate-line) nil))
9826 (define-skeleton verilog-sk-primitive
9827 "Insert a task definition."
9829 > "primitive " '(verilog-sk-prompt-name) " ( " '(verilog-sk-prompt-output) ("input:" ", " str ) " );"\n
9831 > (- verilog-indent-level-behavioral) "endprimitive" (progn (electric-verilog-terminate-line) nil))
9833 (define-skeleton verilog-sk-task
9834 "Insert a task definition."
9836 > "task " '(verilog-sk-prompt-name) & ?; \n
9840 > (- verilog-indent-level-behavioral) "end" \n
9841 > (- verilog-indent-level-behavioral) "endtask" (progn (electric-verilog-terminate-line) nil))
9843 (define-skeleton verilog-sk-function
9844 "Insert a function definition."
9846 > "function [" '(verilog-sk-prompt-width) | -1 '(verilog-sk-prompt-name) ?; \n
9850 > (- verilog-indent-level-behavioral) "end" \n
9851 > (- verilog-indent-level-behavioral) "endfunction" (progn (electric-verilog-terminate-line) nil))
9853 (define-skeleton verilog-sk-always
9854 "Insert always block. Uses the minibuffer to prompt
9855 for sensitivity list."
9857 > "always @ ( /*AUTOSENSE*/ ) begin\n"
9859 > (- verilog-indent-level-behavioral) "end" \n >
9862 (define-skeleton verilog-sk-initial
9863 "Insert an initial block."
9867 > (- verilog-indent-level-behavioral) "end" \n > )
9869 (define-skeleton verilog-sk-specify
9870 "Insert specify block. "
9874 > (- verilog-indent-level-behavioral) "endspecify" \n > )
9876 (define-skeleton verilog-sk-generate
9877 "Insert generate block. "
9881 > (- verilog-indent-level-behavioral) "endgenerate" \n > )
9883 (define-skeleton verilog-sk-begin
9884 "Insert begin end block. Uses the minibuffer to prompt for name."
9886 > "begin" '(verilog-sk-prompt-name) \n
9888 > (- verilog-indent-level-behavioral) "end"
9891 (define-skeleton verilog-sk-fork
9892 "Insert a fork join block."
9897 > (- verilog-indent-level-behavioral) "end" \n
9900 > (- verilog-indent-level-behavioral) "end" \n
9901 > (- verilog-indent-level-behavioral) "join" \n
9905 (define-skeleton verilog-sk-case
9906 "Build skeleton case statement, prompting for the selector expression,
9907 and the case items."
9908 "[selector expression]: "
9909 > "case (" str ") " \n
9910 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n )
9911 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil))
9913 (define-skeleton verilog-sk-casex
9914 "Build skeleton casex statement, prompting for the selector expression,
9915 and the case items."
9916 "[selector expression]: "
9917 > "casex (" str ") " \n
9918 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n )
9919 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil))
9921 (define-skeleton verilog-sk-casez
9922 "Build skeleton casez statement, prompting for the selector expression,
9923 and the case items."
9924 "[selector expression]: "
9925 > "casez (" str ") " \n
9926 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n )
9927 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil))
9929 (define-skeleton verilog-sk-if
9930 "Insert a skeleton if statement."
9931 > "if (" '(verilog-sk-prompt-condition) & ")" " begin" \n
9933 > (- verilog-indent-level-behavioral) "end " \n )
9935 (define-skeleton verilog-sk-else-if
9936 "Insert a skeleton else if statement."
9937 > (verilog-indent-line) "else if ("
9938 (progn (setq verilog-sk-p (point)) nil) '(verilog-sk-prompt-condition) (if (> (point) verilog-sk-p) ") " -1 ) & " begin" \n
9940 > "end" (progn (electric-verilog-terminate-line) nil))
9942 (define-skeleton verilog-sk-datadef
9943 "Common routine to get data definition."
9945 '(verilog-sk-prompt-width) | -1 ("name (RET to end):" str ", ") -2 ";" \n)
9947 (define-skeleton verilog-sk-input
9948 "Insert an input definition."
9950 > "input [" '(verilog-sk-datadef))
9952 (define-skeleton verilog-sk-output
9953 "Insert an output definition."
9955 > "output [" '(verilog-sk-datadef))
9957 (define-skeleton verilog-sk-inout
9958 "Insert an inout definition."
9960 > "inout [" '(verilog-sk-datadef))
9962 (defvar verilog-sk-signal nil)
9963 (define-skeleton verilog-sk-def-reg
9964 "Insert a reg definition."
9966 > "reg [" '(verilog-sk-prompt-width) | -1 verilog-sk-signal ";" \n (verilog-pretty-declarations) )
9968 (defun verilog-sk-define-signal ()
9969 "Insert a definition of signal under point at top of module."
9971 (let* ((sig-re "[a-zA-Z0-9_]*")
9972 (v1 (buffer-substring
9974 (skip-chars-backward sig-re)
9977 (skip-chars-forward sig-re)
9979 (if (not (member v1 verilog-keywords))
9981 (setq verilog-sk-signal v1)
9982 (verilog-beg-of-defun)
9983 (verilog-end-of-statement)
9984 (verilog-forward-syntactic-ws)
9985 (verilog-sk-def-reg)
9986 (message "signal at point is %s" v1))
9987 (message "object at point (%s) is a keyword" v1))))
9989 (define-skeleton verilog-sk-wire
9990 "Insert a wire definition."
9992 > "wire [" '(verilog-sk-datadef))
9994 (define-skeleton verilog-sk-reg
9995 "Insert a reg definition."
9997 > "reg [" '(verilog-sk-datadef))
9999 (define-skeleton verilog-sk-assign
10000 "Insert a skeleton assign statement."
10002 > "assign " '(verilog-sk-prompt-name) " = " _ ";" \n)
10004 (define-skeleton verilog-sk-while
10005 "Insert a skeleton while loop statement."
10007 > "while (" '(verilog-sk-prompt-condition) ") begin" \n
10009 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil))
10011 (define-skeleton verilog-sk-repeat
10012 "Insert a skeleton repeat loop statement."
10014 > "repeat (" '(verilog-sk-prompt-condition) ") begin" \n
10016 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil))
10018 (define-skeleton verilog-sk-for
10019 "Insert a skeleton while loop statement."
10022 '(verilog-sk-prompt-init) "; "
10023 '(verilog-sk-prompt-condition) "; "
10024 '(verilog-sk-prompt-inc)
10027 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil))
10029 (define-skeleton verilog-sk-comment
10030 "Inserts three comment lines, making a display comment."
10036 (define-skeleton verilog-sk-state-machine
10037 "Insert a state machine definition."
10038 "Name of state variable: "
10039 '(setq input "state")
10040 > "// State registers for " str | -23 \n
10041 '(setq verilog-sk-state str)
10042 > "reg [" '(verilog-sk-prompt-width) | -1 verilog-sk-state ", next_" verilog-sk-state ?; \n
10045 > "// State FF for " verilog-sk-state \n
10046 > "always @ ( " (read-string "clock:" "posedge clk") " or " (verilog-sk-prompt-reset) " ) begin" \n
10047 > "if ( " verilog-sk-reset " ) " verilog-sk-state " = 0; else" \n
10048 > verilog-sk-state " = next_" verilog-sk-state ?; \n
10049 > (- verilog-indent-level-behavioral) "end" (progn (electric-verilog-terminate-line) nil)
10051 > "// Next State Logic for " verilog-sk-state \n
10052 > "always @ ( /*AUTOSENSE*/ ) begin\n"
10053 > "case (" '(verilog-sk-prompt-state-selector) ") " \n
10054 > ("case selector: " str ": begin" \n > "next_" verilog-sk-state " = " _ ";" \n > (- verilog-indent-level-behavioral) "end" \n )
10055 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil)
10056 > (- verilog-indent-level-behavioral) "end" (progn (electric-verilog-terminate-line) nil))
10060 ;; Include file loading with mouse/return event
10062 ;; idea & first impl.: M. Rouat (eldo-mode.el)
10063 ;; second (emacs/xemacs) impl.: G. Van der Plas (spice-mode.el)
10065 (if (featurep 'xemacs)
10067 (require 'lucid)) ;; what else can we do ??
10069 (defconst verilog-include-file-regexp
10070 "^`include\\s-+\"\\([^\n\"]*\\)\""
10071 "Regexp that matches the include file.")
10073 (defvar verilog-mode-mouse-map
10074 (let ((map (make-sparse-keymap))) ; as described in info pages, make a map
10075 (set-keymap-parent map verilog-mode-map)
10076 ;; mouse button bindings
10077 (define-key map "\r" 'verilog-load-file-at-point)
10078 (if (featurep 'xemacs)
10079 (define-key map 'button2 'verilog-load-file-at-mouse);ffap-at-mouse ?
10080 (define-key map [mouse-2] 'verilog-load-file-at-mouse))
10081 (if (featurep 'xemacs)
10082 (define-key map 'Sh-button2 'mouse-yank) ; you wanna paste don't you ?
10083 (define-key map [S-mouse-2] 'mouse-yank-at-click))
10085 "Map containing mouse bindings for `verilog-mode'.")
10088 (defun verilog-colorize-include-files (beg end old-len)
10089 "This function colorizes included files when the mouse passes over them.
10090 Clicking on the middle-mouse button loads them in a buffer (as in dired)."
10095 (setq end-point (verilog-get-end-of-line))
10097 (beginning-of-line) ; scan entire line !
10098 ;; delete overlays existing on this line
10099 (let ((overlays (overlays-in (point) end-point)))
10102 (overlay-get (car overlays) 'detachable)
10103 (overlay-get (car overlays) 'verilog-include-file))
10104 (delete-overlay (car overlays)))
10105 (setq overlays (cdr overlays)))) ; let
10106 ;; make new ones, could reuse deleted one ?
10107 (while (search-forward-regexp verilog-include-file-regexp end-point t)
10109 (goto-char (match-beginning 1))
10110 (setq ov (make-overlay (match-beginning 1) (match-end 1)))
10111 (overlay-put ov 'start-closed 't)
10112 (overlay-put ov 'end-closed 't)
10113 (overlay-put ov 'evaporate 't)
10114 (overlay-put ov 'verilog-include-file 't)
10115 (overlay-put ov 'mouse-face 'highlight)
10116 (overlay-put ov 'local-map verilog-mode-mouse-map)))))))
10119 (defun verilog-colorize-include-files-buffer ()
10120 "Colorize an include file."
10123 (let ((overlays (overlays-in (point-min) (point-max))))
10126 (overlay-get (car overlays) 'detachable)
10127 (overlay-get (car overlays) 'verilog-include-file))
10128 (delete-overlay (car overlays)))
10129 (setq overlays (cdr overlays)))) ; let
10131 (verilog-colorize-include-files (point-min) (point-max) nil))
10133 ;; ffap-at-mouse isn't useful for Verilog mode. It uses library paths.
10134 ;; so define this function to do more or less the same as ffap-at-mouse
10135 ;; but first resolve filename...
10136 (defun verilog-load-file-at-mouse (event)
10137 "Load file under button 2 click's EVENT.
10138 Files are checked based on `verilog-library-directories'."
10140 (save-excursion ;; implement a Verilog specific ffap-at-mouse
10141 (mouse-set-point event)
10142 (beginning-of-line)
10143 (if (looking-at verilog-include-file-regexp)
10144 (if (and (car (verilog-library-filenames
10145 (match-string 1) (buffer-file-name)))
10146 (file-readable-p (car (verilog-library-filenames
10147 (match-string 1) (buffer-file-name)))))
10148 (find-file (car (verilog-library-filenames
10149 (match-string 1) (buffer-file-name))))
10152 "File '%s' isn't readable, use shift-mouse2 to paste in this field"
10153 (match-string 1)))))))
10155 ;; ffap isn't useable for Verilog mode. It uses library paths.
10156 ;; so define this function to do more or less the same as ffap
10157 ;; but first resolve filename...
10158 (defun verilog-load-file-at-point ()
10159 "Load file under point.
10160 Files are checked based on `verilog-library-directories'."
10162 (save-excursion ;; implement a Verilog specific ffap
10163 (beginning-of-line)
10164 (if (looking-at verilog-include-file-regexp)
10166 (car (verilog-library-filenames
10167 (match-string 1) (buffer-file-name)))
10168 (file-readable-p (car (verilog-library-filenames
10169 (match-string 1) (buffer-file-name)))))
10170 (find-file (car (verilog-library-filenames
10171 (match-string 1) (buffer-file-name))))))))
10178 (defun verilog-faq ()
10179 "Tell the user their current version, and where to get the FAQ etc."
10181 (with-output-to-temp-buffer "*verilog-mode help*"
10182 (princ (format "You are using verilog-mode %s\n" verilog-mode-version))
10184 (princ "For new releases, see http://www.verilog.com\n")
10186 (princ "For frequently asked questions, see http://www.veripool.com/verilog-mode-faq.html\n")
10188 (princ "To submit a bug, use M-x verilog-submit-bug-report\n")
10191 (autoload 'reporter-submit-bug-report "reporter")
10192 (defvar reporter-prompt-for-summary-p)
10194 (defun verilog-submit-bug-report ()
10195 "Submit via mail a bug report on verilog-mode.el."
10197 (let ((reporter-prompt-for-summary-p t))
10198 (reporter-submit-bug-report
10200 (concat "verilog-mode v" verilog-mode-version)
10202 verilog-align-ifelse
10203 verilog-auto-endcomments
10205 verilog-auto-indent-on-newline
10206 verilog-auto-inst-vector
10207 verilog-auto-inst-template-numbers
10208 verilog-auto-lineup
10209 verilog-auto-newline
10210 verilog-auto-save-policy
10211 verilog-auto-sense-defines-constant
10212 verilog-auto-sense-include-inputs
10213 verilog-before-auto-hook
10214 verilog-case-indent
10215 verilog-cexp-indent
10218 verilog-highlight-translate-off
10219 verilog-indent-begin-after-if
10220 verilog-indent-declaration-macros
10221 verilog-indent-level
10222 verilog-indent-level-behavioral
10223 verilog-indent-level-declaration
10224 verilog-indent-level-directive
10225 verilog-indent-level-module
10226 verilog-indent-lists
10227 verilog-library-flags
10228 verilog-library-directories
10229 verilog-library-extensions
10230 verilog-library-files
10232 verilog-minimum-comment-distance
10235 verilog-tab-always-indent
10236 verilog-tab-to-comment
10241 I want to report a bug. I've read the `Bugs' section of `Info' on
10242 Emacs, so I know how to make a clear and unambiguous report. To get
10243 to that Info section, I typed
10245 M-x info RET m " invocation-name " RET m bugs RET
10247 Before I go further, I want to say that Verilog mode has changed my life.
10248 I save so much time, my files are colored nicely, my co workers respect
10249 my coding ability... until now. I'd really appreciate anything you
10250 could do to help me out with this minor deficiency in the product.
10252 If you have bugs with the AUTO functions, please CC the AUTOAUTHOR Wilson
10253 Snyder (wsnyder@wsnyder.org) and/or see http://www.veripool.com.
10254 You may also want to look at the Verilog-Mode FAQ, see
10255 http://www.veripool.com/verilog-mode-faq.html.
10257 To reproduce the bug, start a fresh Emacs via " invocation-name "
10258 -no-init-file -no-site-file'. In a new buffer, in Verilog mode, type
10259 the code included below.
10261 Given those lines, I expected [[Fill in here]] to happen;
10262 but instead, [[Fill in here]] happens!.
10264 == The code: =="))))
10266 (provide 'verilog-mode)
10268 ;; Local Variables:
10269 ;; checkdoc-permit-comma-termination-flag:t
10270 ;; checkdoc-force-docstrings-flag:nil
10273 ;; arch-tag: 87923725-57b3-41b5-9494-be21118c6a6f
10274 ;;; verilog-mode.el ends here