1 ;; verilog-mode.el --- major mode for editing verilog source in Emacs
3 ;; Copyright (C) 1996-2012 Free Software Foundation, Inc.
5 ;; Author: Michael McNamara (mac@verilog.com),
6 ;; Wilson Snyder (wsnyder@wsnyder.org)
7 ;; Please see our web sites:
8 ;; http://www.verilog.com
9 ;; http://www.veripool.org
11 ;; Keywords: languages
13 ;; Yoni Rabkin <yoni@rabkins.net> contacted the maintainer of this
14 ;; file on 19/3/2008, and the maintainer agreed that when a bug is
15 ;; filed in the Emacs bug reporting system against this file, a copy
16 ;; of the bug report be sent to the maintainer's email address.
18 ;; This code supports Emacs 21.1 and later
19 ;; And XEmacs 21.1 and later
20 ;; Please do not make changes that break Emacs 21. Thanks!
24 ;; This file is part of GNU Emacs.
26 ;; GNU Emacs is free software: you can redistribute it and/or modify
27 ;; it under the terms of the GNU General Public License as published by
28 ;; the Free Software Foundation, either version 3 of the License, or
29 ;; (at your option) any later version.
31 ;; GNU Emacs is distributed in the hope that it will be useful,
32 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
33 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
34 ;; GNU General Public License for more details.
36 ;; You should have received a copy of the GNU General Public License
37 ;; along with GNU Emacs. If not, see <http://www.gnu.org/licenses/>.
41 ;; This mode borrows heavily from the Pascal-mode and the cc-mode of Emacs
46 ;; A major mode for editing Verilog HDL source code. When you have
47 ;; entered Verilog mode, you may get more info by pressing C-h m. You
48 ;; may also get online help describing various functions by: C-h f
49 ;; <Name of function you want described>
51 ;; KNOWN BUGS / BUG REPORTS
52 ;; =======================
54 ;; Verilog is a rapidly evolving language, and hence this mode is
55 ;; under continuous development. Hence this is beta code, and likely
56 ;; has bugs. Please report any issues to the issue tracker at
57 ;; http://www.veripool.org/verilog-mode
58 ;; Please use verilog-submit-bug-report to submit a report; type C-c
59 ;; C-b to invoke this and as a result I will have a much easier time
60 ;; of reproducing the bug you find, and hence fixing it.
62 ;; INSTALLING THE MODE
63 ;; ===================
65 ;; An older version of this mode may be already installed as a part of
66 ;; your environment, and one method of updating would be to update
67 ;; your Emacs environment. Sometimes this is difficult for local
68 ;; political/control reasons, and hence you can always install a
69 ;; private copy (or even a shared copy) which overrides the system
72 ;; You can get step by step help in installing this file by going to
73 ;; <http://www.verilog.com/emacs_install.html>
75 ;; The short list of installation instructions are: To set up
76 ;; automatic Verilog mode, put this file in your load path, and put
77 ;; the following in code (please un comment it first!) in your
78 ;; .emacs, or in your site's site-load.el
80 ; (autoload 'verilog-mode "verilog-mode" "Verilog mode" t )
81 ; (add-to-list 'auto-mode-alist '("\\.[ds]?vh?\\'" . verilog-mode))
83 ;; Be sure to examine at the help for verilog-auto, and the other
84 ;; verilog-auto-* functions for some major coding time savers.
86 ;; If you want to customize Verilog mode to fit your needs better,
87 ;; you may add the below lines (the values of the variables presented
88 ;; here are the defaults). Note also that if you use an Emacs that
89 ;; supports custom, it's probably better to use the custom menu to
90 ;; edit these. If working as a member of a large team these settings
91 ;; should be common across all users (in a site-start file), or set
92 ;; in Local Variables in every file. Otherwise, different people's
93 ;; AUTO expansion may result different whitespace changes.
95 ; ;; Enable syntax highlighting of **all** languages
96 ; (global-font-lock-mode t)
98 ; ;; User customization for Verilog mode
99 ; (setq verilog-indent-level 3
100 ; verilog-indent-level-module 3
101 ; verilog-indent-level-declaration 3
102 ; verilog-indent-level-behavioral 3
103 ; verilog-indent-level-directive 1
104 ; verilog-case-indent 2
105 ; verilog-auto-newline t
106 ; verilog-auto-indent-on-newline t
107 ; verilog-tab-always-indent t
108 ; verilog-auto-endcomments t
109 ; verilog-minimum-comment-distance 40
110 ; verilog-indent-begin-after-if t
111 ; verilog-auto-lineup 'declarations
112 ; verilog-highlight-p1800-keywords nil
113 ; verilog-linter "my_lint_shell_command"
120 ;; See commit history at http://www.veripool.org/verilog-mode.html
121 ;; (This section is required to appease checkdoc.)
125 ;; This variable will always hold the version number of the mode
126 (defconst verilog-mode-version
"725"
127 "Version of this Verilog mode.")
128 (defconst verilog-mode-release-date
"2011-11-27-GNU"
129 "Release date of this Verilog mode.")
130 (defconst verilog-mode-release-emacs t
131 "If non-nil, this version of Verilog mode was released with Emacs itself.")
133 (defun verilog-version ()
134 "Inform caller of the version of this file."
136 (message "Using verilog-mode version %s" verilog-mode-version
))
138 ;; Insure we have certain packages, and deal with it if we don't
139 ;; Be sure to note which Emacs flavor and version added each feature.
141 ;; Provide stuff if we are XEmacs
142 (when (featurep 'xemacs
)
147 (require 'regexp-opt
)
149 ;; Bug in 19.28 through 19.30 skeleton.el, not provided.
156 (defmacro when
(cond &rest body
)
157 (list 'if cond
(cons 'progn body
))))
160 (if (fboundp 'unless
)
162 (defmacro unless
(cond &rest body
)
163 (cons 'if
(cons cond
(cons nil body
)))))
166 (if (fboundp 'store-match-data
)
168 (defmacro store-match-data
(&rest args
) nil
))
171 (if (fboundp 'char-before
)
173 (defmacro char-before
(&rest body
)
174 (char-after (1- (point)))))
179 (defsubst point-at-bol
(&optional N
)
180 (save-excursion (beginning-of-line N
) (point))))
185 (defsubst point-at-eol
(&optional N
)
186 (save-excursion (end-of-line N
) (point))))
192 (if (fboundp 'match-string-no-properties
)
194 (defsubst match-string-no-properties
(num &optional string
)
195 "Return string of text matched by last search, without text properties.
196 NUM specifies which parenthesized expression in the last regexp.
197 Value is nil if NUMth pair didn't match, or there were less than NUM pairs.
198 Zero means the entire text matched by the whole regexp or whole string.
199 STRING should be given if the last search was by `string-match' on STRING."
200 (if (match-beginning num
)
204 (match-beginning num
) (match-end num
))))
205 (set-text-properties 0 (length result
) nil result
)
207 (buffer-substring-no-properties (match-beginning num
)
212 (if (and (featurep 'custom
) (fboundp 'custom-declare-variable
))
213 nil
;; We've got what we needed
214 ;; We have the old custom-library, hack around it!
215 (defmacro defgroup
(&rest args
) nil
)
216 (defmacro customize
(&rest args
)
218 "Sorry, Customize is not available with this version of Emacs"))
219 (defmacro defcustom
(var value doc
&rest args
)
220 `(defvar ,var
,value
,doc
))
222 (if (fboundp 'defface
)
224 (defmacro defface
(var values doc
&rest args
)
228 (if (and (featurep 'custom
) (fboundp 'customize-group
))
229 nil
;; We've got what we needed
230 ;; We have an intermediate custom-library, hack around it!
231 (defmacro customize-group
(var &rest args
)
235 (unless (boundp 'inhibit-point-motion-hooks
)
236 (defvar inhibit-point-motion-hooks nil
))
237 (unless (boundp 'deactivate-mark
)
238 (defvar deactivate-mark nil
))
241 ;; OK, do this stuff if we are NOT XEmacs:
242 (unless (featurep 'xemacs
)
243 (unless (fboundp 'region-active-p
)
244 (defmacro region-active-p
()
245 `(and transient-mark-mode mark-active
))))
248 ;; Provide a regular expression optimization routine, using regexp-opt
249 ;; if provided by the user's elisp libraries
251 ;; The below were disabled when GNU Emacs 22 was released;
252 ;; perhaps some still need to be there to support Emacs 21.
253 (if (featurep 'xemacs
)
254 (if (fboundp 'regexp-opt
)
255 ;; regexp-opt is defined, does it take 3 or 2 arguments?
256 (if (fboundp 'function-max-args
)
257 (let ((args (function-max-args `regexp-opt
)))
259 ((eq args
3) ;; It takes 3
260 (condition-case nil
; Hide this defun from emacses
261 ;with just a two input regexp
262 (defun verilog-regexp-opt (a b
)
263 "Deal with differing number of required arguments for `regexp-opt'.
264 Call 'regexp-opt' on A and B."
268 ((eq args
2) ;; It takes 2
269 (defun verilog-regexp-opt (a b
)
270 "Call 'regexp-opt' on A and B."
274 ;; We can't tell; assume it takes 2
275 (defun verilog-regexp-opt (a b
)
276 "Call 'regexp-opt' on A and B."
279 ;; There is no regexp-opt, provide our own
280 (defun verilog-regexp-opt (strings &optional paren shy
)
281 (let ((open (if paren
"\\(" "")) (close (if paren
"\\)" "")))
282 (concat open
(mapconcat 'regexp-quote strings
"\\|") close
)))
285 (defalias 'verilog-regexp-opt
'regexp-opt
)))
288 ;; Both xemacs and emacs
290 (require 'diff
) ;; diff-command and diff-switches
293 (require 'compile
) ;; compilation-error-regexp-alist-alist
296 (unless (fboundp 'buffer-chars-modified-tick
) ;; Emacs 22 added
297 (defmacro buffer-chars-modified-tick
() (buffer-modified-tick)))
299 ;; Added in Emacs 24.1
301 (unless (fboundp 'prog-mode
)
302 (define-derived-mode prog-mode fundamental-mode
"Prog"))
306 (defun verilog-regexp-words (a)
307 "Call 'regexp-opt' with word delimiters for the words A."
308 (concat "\\<" (verilog-regexp-opt a t
) "\\>")))
309 (defun verilog-regexp-words (a)
310 "Call 'regexp-opt' with word delimiters for the words A."
311 ;; The FAQ references this function, so user LISP sometimes calls it
312 (concat "\\<" (verilog-regexp-opt a t
) "\\>"))
314 (defun verilog-easy-menu-filter (menu)
315 "Filter `easy-menu-define' MENU to support new features."
316 (cond ((not (featurep 'xemacs
))
317 menu
) ;; GNU Emacs - passthru
318 ;; XEmacs doesn't support :help. Strip it.
319 ;; Recursively filter the a submenu
321 (mapcar 'verilog-easy-menu-filter menu
))
322 ;; Look for [:help "blah"] and remove
324 (let ((i 0) (out []))
325 (while (< i
(length menu
))
326 (if (equal `:help
(aref menu i
))
328 (setq out
(vconcat out
(vector (aref menu i
)))
331 (t menu
))) ;; Default - ok
332 ;;(verilog-easy-menu-filter
333 ;; `("Verilog" ("MA" ["SAA" nil :help "Help SAA"] ["SAB" nil :help "Help SAA"])
334 ;; "----" ["MB" nil :help "Help MB"]))
336 (defun verilog-define-abbrev (table name expansion
&optional hook
)
337 "Filter `define-abbrev' TABLE NAME EXPANSION and call HOOK.
338 Provides SYSTEM-FLAG in newer Emacs."
340 (define-abbrev table name expansion hook
0 t
)
342 (define-abbrev table name expansion hook
))))
344 (defun verilog-customize ()
345 "Customize variables and other settings used by Verilog-Mode."
347 (customize-group 'verilog-mode
))
349 (defun verilog-font-customize ()
350 "Customize fonts used by Verilog-Mode."
352 (if (fboundp 'customize-apropos
)
353 (customize-apropos "font-lock-*" 'faces
)))
355 (defun verilog-booleanp (value)
356 "Return t if VALUE is boolean.
357 This implements GNU Emacs 22.1's `booleanp' function in earlier Emacs.
358 This function may be removed when Emacs 21 is no longer supported."
359 (or (equal value t
) (equal value nil
)))
361 (defun verilog-insert-last-command-event ()
362 "Insert the `last-command-event'."
363 (insert (if (featurep 'xemacs
)
364 ;; XEmacs 21.5 doesn't like last-command-event
366 ;; And GNU Emacs 22 has obsoleted last-command-char
367 last-command-event
)))
369 (defvar verilog-no-change-functions nil
370 "True if `after-change-functions' is disabled.
371 Use of `syntax-ppss' may break, as ppss's cache may get corrupted.")
373 (defvar verilog-in-hooks nil
374 "True when within a `verilog-run-hooks' block.")
376 (defmacro verilog-run-hooks
(&rest hooks
)
377 "Run each hook in HOOKS using `run-hooks'.
378 Set `verilog-in-hooks' during this time, to assist AUTO caches."
379 `(let ((verilog-in-hooks t
))
380 (run-hooks ,@hooks
)))
382 (defun verilog-syntax-ppss (&optional pos
)
383 (when verilog-no-change-functions
385 (verilog-scan-cache-flush)
386 ;; else don't let the AUTO code itself get away with flushing the cache,
387 ;; as that'll make things very slow
389 (error "%s: Internal problem; use of syntax-ppss when cache may be corrupt"
390 (verilog-point-text))))
391 (if (fboundp 'syntax-ppss
)
393 (parse-partial-sexp (point-min) (or pos
(point)))))
395 (defgroup verilog-mode nil
396 "Facilitates easy editing of Verilog source text."
400 ; (defgroup verilog-mode-fonts nil
401 ; "Facilitates easy customization fonts used in Verilog source text"
402 ; :link '(customize-apropos "font-lock-*" 'faces)
403 ; :group 'verilog-mode)
405 (defgroup verilog-mode-indent nil
406 "Customize indentation and highlighting of Verilog source text."
407 :group
'verilog-mode
)
409 (defgroup verilog-mode-actions nil
410 "Customize actions on Verilog source text."
411 :group
'verilog-mode
)
413 (defgroup verilog-mode-auto nil
414 "Customize AUTO actions when expanding Verilog source text."
415 :group
'verilog-mode
)
417 (defvar verilog-debug nil
418 "If set, enable debug messages for `verilog-mode' internals.")
420 (defcustom verilog-linter
421 "echo 'No verilog-linter set, see \"M-x describe-variable verilog-linter\"'"
422 "*Unix program and arguments to call to run a lint checker on Verilog source.
423 Depending on the `verilog-set-compile-command', this may be invoked when
424 you type \\[compile]. When the compile completes, \\[next-error] will take
425 you to the next lint error."
427 :group
'verilog-mode-actions
)
428 ;; We don't mark it safe, as it's used as a shell command
430 (defcustom verilog-coverage
431 "echo 'No verilog-coverage set, see \"M-x describe-variable verilog-coverage\"'"
432 "*Program and arguments to use to annotate for coverage Verilog source.
433 Depending on the `verilog-set-compile-command', this may be invoked when
434 you type \\[compile]. When the compile completes, \\[next-error] will take
435 you to the next lint error."
437 :group
'verilog-mode-actions
)
438 ;; We don't mark it safe, as it's used as a shell command
440 (defcustom verilog-simulator
441 "echo 'No verilog-simulator set, see \"M-x describe-variable verilog-simulator\"'"
442 "*Program and arguments to use to interpret Verilog source.
443 Depending on the `verilog-set-compile-command', this may be invoked when
444 you type \\[compile]. When the compile completes, \\[next-error] will take
445 you to the next lint error."
447 :group
'verilog-mode-actions
)
448 ;; We don't mark it safe, as it's used as a shell command
450 (defcustom verilog-compiler
451 "echo 'No verilog-compiler set, see \"M-x describe-variable verilog-compiler\"'"
452 "*Program and arguments to use to compile Verilog source.
453 Depending on the `verilog-set-compile-command', this may be invoked when
454 you type \\[compile]. When the compile completes, \\[next-error] will take
455 you to the next lint error."
457 :group
'verilog-mode-actions
)
458 ;; We don't mark it safe, as it's used as a shell command
460 (defcustom verilog-preprocessor
461 ;; Very few tools give preprocessed output, so we'll default to Verilog-Perl
462 "vppreproc __FLAGS__ __FILE__"
463 "*Program and arguments to use to preprocess Verilog source.
464 This is invoked with `verilog-preprocess', and depending on the
465 `verilog-set-compile-command', may also be invoked when you type
466 \\[compile]. When the compile completes, \\[next-error] will
467 take you to the next lint error."
469 :group
'verilog-mode-actions
)
470 ;; We don't mark it safe, as it's used as a shell command
472 (defvar verilog-preprocess-history nil
473 "History for `verilog-preprocess'.")
475 (defvar verilog-tool
'verilog-linter
476 "Which tool to use for building compiler-command.
477 Either nil, `verilog-linter, `verilog-compiler,
478 `verilog-coverage, `verilog-preprocessor, or `verilog-simulator.
479 Alternatively use the \"Choose Compilation Action\" menu. See
480 `verilog-set-compile-command' for more information.")
482 (defcustom verilog-highlight-translate-off nil
483 "*Non-nil means background-highlight code excluded from translation.
484 That is, all code between \"// synopsys translate_off\" and
485 \"// synopsys translate_on\" is highlighted using a different background color
486 \(face `verilog-font-lock-translate-off-face').
488 Note: This will slow down on-the-fly fontification (and thus editing).
490 Note: Activate the new setting in a Verilog buffer by re-fontifying it (menu
491 entry \"Fontify Buffer\"). XEmacs: turn off and on font locking."
493 :group
'verilog-mode-indent
)
494 ;; Note we don't use :safe, as that would break on Emacsen before 22.0.
495 (put 'verilog-highlight-translate-off
'safe-local-variable
'verilog-booleanp
)
497 (defcustom verilog-auto-lineup
'declarations
498 "*Type of statements to lineup across multiple lines.
499 If 'all' is selected, then all line ups described below are done.
501 If 'declaration', then just declarations are lined up with any
502 preceding declarations, taking into account widths and the like,
503 so or example the code:
510 If 'assignment', then assignments are lined up with any preceding
511 assignments, so for example the code
512 a_long_variable <= b + c;
515 a_long_variable <= b + c;
518 In order to speed up editing, large blocks of statements are lined up
519 only when a \\[verilog-pretty-expr] is typed; and large blocks of declarations
520 are lineup only when \\[verilog-pretty-declarations] is typed."
522 :type
'(radio (const :tag
"Line up Assignments and Declarations" all
)
523 (const :tag
"Line up Assignment statements" assignments
)
524 (const :tag
"Line up Declarations" declarations
)
525 (function :tag
"Other"))
526 :group
'verilog-mode-indent
)
528 (defcustom verilog-indent-level
3
529 "*Indentation of Verilog statements with respect to containing block."
530 :group
'verilog-mode-indent
532 (put 'verilog-indent-level
'safe-local-variable
'integerp
)
534 (defcustom verilog-indent-level-module
3
535 "*Indentation of Module level Verilog statements (eg always, initial).
536 Set to 0 to get initial and always statements lined up on the left side of
538 :group
'verilog-mode-indent
540 (put 'verilog-indent-level-module
'safe-local-variable
'integerp
)
542 (defcustom verilog-indent-level-declaration
3
543 "*Indentation of declarations with respect to containing block.
544 Set to 0 to get them list right under containing block."
545 :group
'verilog-mode-indent
547 (put 'verilog-indent-level-declaration
'safe-local-variable
'integerp
)
549 (defcustom verilog-indent-declaration-macros nil
550 "*How to treat macro expansions in a declaration.
555 If non nil, treat as:
559 :group
'verilog-mode-indent
561 (put 'verilog-indent-declaration-macros
'safe-local-variable
'verilog-booleanp
)
563 (defcustom verilog-indent-lists t
564 "*How to treat indenting items in a list.
565 If t (the default), indent as:
566 always @( posedge a or
570 always @( posedge a or
572 :group
'verilog-mode-indent
574 (put 'verilog-indent-lists
'safe-local-variable
'verilog-booleanp
)
576 (defcustom verilog-indent-level-behavioral
3
577 "*Absolute indentation of first begin in a task or function block.
578 Set to 0 to get such code to start at the left side of the screen."
579 :group
'verilog-mode-indent
581 (put 'verilog-indent-level-behavioral
'safe-local-variable
'integerp
)
583 (defcustom verilog-indent-level-directive
1
584 "*Indentation to add to each level of `ifdef declarations.
585 Set to 0 to have all directives start at the left side of the screen."
586 :group
'verilog-mode-indent
588 (put 'verilog-indent-level-directive
'safe-local-variable
'integerp
)
590 (defcustom verilog-cexp-indent
2
591 "*Indentation of Verilog statements split across lines."
592 :group
'verilog-mode-indent
594 (put 'verilog-cexp-indent
'safe-local-variable
'integerp
)
596 (defcustom verilog-case-indent
2
597 "*Indentation for case statements."
598 :group
'verilog-mode-indent
600 (put 'verilog-case-indent
'safe-local-variable
'integerp
)
602 (defcustom verilog-auto-newline t
603 "*True means automatically newline after semicolons."
604 :group
'verilog-mode-indent
606 (put 'verilog-auto-newline
'safe-local-variable
'verilog-booleanp
)
608 (defcustom verilog-auto-indent-on-newline t
609 "*True means automatically indent line after newline."
610 :group
'verilog-mode-indent
612 (put 'verilog-auto-indent-on-newline
'safe-local-variable
'verilog-booleanp
)
614 (defcustom verilog-tab-always-indent t
615 "*True means TAB should always re-indent the current line.
616 A nil value means TAB will only reindent when at the beginning of the line."
617 :group
'verilog-mode-indent
619 (put 'verilog-tab-always-indent
'safe-local-variable
'verilog-booleanp
)
621 (defcustom verilog-tab-to-comment nil
622 "*True means TAB moves to the right hand column in preparation for a comment."
623 :group
'verilog-mode-actions
625 (put 'verilog-tab-to-comment
'safe-local-variable
'verilog-booleanp
)
627 (defcustom verilog-indent-begin-after-if t
628 "*If true, indent begin statements following if, else, while, for and repeat.
629 Otherwise, line them up."
630 :group
'verilog-mode-indent
632 (put 'verilog-indent-begin-after-if
'safe-local-variable
'verilog-booleanp
)
635 (defcustom verilog-align-ifelse nil
636 "*If true, align `else' under matching `if'.
637 Otherwise else is lined up with first character on line holding matching if."
638 :group
'verilog-mode-indent
640 (put 'verilog-align-ifelse
'safe-local-variable
'verilog-booleanp
)
642 (defcustom verilog-minimum-comment-distance
10
643 "*Minimum distance (in lines) between begin and end required before a comment.
644 Setting this variable to zero results in every end acquiring a comment; the
645 default avoids too many redundant comments in tight quarters."
646 :group
'verilog-mode-indent
648 (put 'verilog-minimum-comment-distance
'safe-local-variable
'integerp
)
650 (defcustom verilog-highlight-p1800-keywords nil
651 "*True means highlight words newly reserved by IEEE-1800.
652 These will appear in `verilog-font-lock-p1800-face' in order to gently
653 suggest changing where these words are used as variables to something else.
654 A nil value means highlight these words as appropriate for the SystemVerilog
655 IEEE-1800 standard. Note that changing this will require restarting Emacs
656 to see the effect as font color choices are cached by Emacs."
657 :group
'verilog-mode-indent
659 (put 'verilog-highlight-p1800-keywords
'safe-local-variable
'verilog-booleanp
)
661 (defcustom verilog-highlight-grouping-keywords nil
662 "*True means highlight grouping keywords 'begin' and 'end' more dramatically.
663 If false, these words are in the `font-lock-type-face'; if True then they are in
664 `verilog-font-lock-ams-face'. Some find that special highlighting on these
665 grouping constructs allow the structure of the code to be understood at a glance."
666 :group
'verilog-mode-indent
668 (put 'verilog-highlight-grouping-keywords
'safe-local-variable
'verilog-booleanp
)
670 (defcustom verilog-highlight-modules nil
671 "*True means highlight module statements for `verilog-load-file-at-point'.
672 When true, mousing over module names will allow jumping to the
673 module definition. If false, this is not supported. Setting
674 this is experimental, and may lead to bad performance."
675 :group
'verilog-mode-indent
677 (put 'verilog-highlight-modules
'safe-local-variable
'verilog-booleanp
)
679 (defcustom verilog-highlight-includes t
680 "*True means highlight module statements for `verilog-load-file-at-point'.
681 When true, mousing over include file names will allow jumping to the
682 file referenced. If false, this is not supported."
683 :group
'verilog-mode-indent
685 (put 'verilog-highlight-includes
'safe-local-variable
'verilog-booleanp
)
687 (defcustom verilog-auto-declare-nettype nil
688 "*Non-nil specifies the data type to use with `verilog-auto-input' etc.
689 Set this to \"wire\" if the Verilog code uses \"`default_nettype
690 none\". Note using `default_nettype none isn't recommended practice; this
691 mode is experimental."
693 :group
'verilog-mode-actions
695 (put 'verilog-auto-declare-nettype
'safe-local-variable
`stringp
)
697 (defcustom verilog-auto-wire-type nil
698 "*Non-nil specifies the data type to use with `verilog-auto-wire' etc.
699 Set this to \"logic\" for SystemVerilog code, or use `verilog-auto-logic'."
701 :group
'verilog-mode-actions
703 (put 'verilog-auto-wire-type
'safe-local-variable
`stringp
)
705 (defcustom verilog-auto-endcomments t
706 "*True means insert a comment /* ... */ after 'end's.
707 The name of the function or case will be set between the braces."
708 :group
'verilog-mode-actions
710 (put 'verilog-auto-endcomments
'safe-local-variable
'verilog-booleanp
)
712 (defcustom verilog-auto-delete-trailing-whitespace nil
713 "*True means to `delete-trailing-whitespace' in `verilog-auto'."
715 :group
'verilog-mode-actions
717 (put 'verilog-auto-delete-trailing-whitespace
'safe-local-variable
'verilog-booleanp
)
719 (defcustom verilog-auto-ignore-concat nil
720 "*True means ignore signals in {...} concatenations for AUTOWIRE etc.
721 This will exclude signals referenced as pin connections in {...}
722 from AUTOWIRE, AUTOOUTPUT and friends. This flag should be set
723 for backward compatibility only and not set in new designs; it
724 may be removed in future versions."
725 :group
'verilog-mode-actions
727 (put 'verilog-auto-ignore-concat
'safe-local-variable
'verilog-booleanp
)
729 (defcustom verilog-auto-read-includes nil
730 "*True means to automatically read includes before AUTOs.
731 This will do a `verilog-read-defines' and `verilog-read-includes' before
732 each AUTO expansion. This makes it easier to embed defines and includes,
733 but can result in very slow reading times if there are many or large
735 :group
'verilog-mode-actions
737 (put 'verilog-auto-read-includes
'safe-local-variable
'verilog-booleanp
)
739 (defcustom verilog-auto-save-policy nil
740 "*Non-nil indicates action to take when saving a Verilog buffer with AUTOs.
741 A value of `force' will always do a \\[verilog-auto] automatically if
742 needed on every save. A value of `detect' will do \\[verilog-auto]
743 automatically when it thinks necessary. A value of `ask' will query the
744 user when it thinks updating is needed.
746 You should not rely on the 'ask or 'detect policies, they are safeguards
747 only. They do not detect when AUTOINSTs need to be updated because a
748 sub-module's port list has changed."
749 :group
'verilog-mode-actions
750 :type
'(choice (const nil
) (const ask
) (const detect
) (const force
)))
752 (defcustom verilog-auto-star-expand t
753 "*Non-nil indicates to expand a SystemVerilog .* instance ports.
754 They will be expanded in the same way as if there was a AUTOINST in the
755 instantiation. See also `verilog-auto-star' and `verilog-auto-star-save'."
756 :group
'verilog-mode-actions
758 (put 'verilog-auto-star-expand
'safe-local-variable
'verilog-booleanp
)
760 (defcustom verilog-auto-star-save nil
761 "*Non-nil indicates to save to disk SystemVerilog .* instance expansions.
762 A nil value indicates direct connections will be removed before saving.
763 Only meaningful to those created due to `verilog-auto-star-expand' being set.
765 Instead of setting this, you may want to use /*AUTOINST*/, which will
767 :group
'verilog-mode-actions
769 (put 'verilog-auto-star-save
'safe-local-variable
'verilog-booleanp
)
771 (defvar verilog-auto-update-tick nil
772 "Modification tick at which autos were last performed.")
774 (defvar verilog-auto-last-file-locals nil
775 "Text from file-local-variables during last evaluation.")
777 (defvar verilog-diff-function
'verilog-diff-report
778 "*Function to run when `verilog-diff-auto' detects differences.
779 Function takes three arguments, the original buffer, the
780 difference buffer, and the point in original buffer with the
785 (defvar verilog-error-regexp-added nil
)
787 (defvar verilog-error-regexp-emacs-alist
790 "\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 3)
792 "([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\(line[ \t]+\\)?\\([0-9]+\\):.*$" 1 3)
794 ".*\\*[WE],[0-9A-Z]+\\(\[[0-9A-Z_,]+\]\\)? (\\([^ \t,]+\\),\\([0-9]+\\)" 2 3)
796 "[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 1 2)
798 "\\(WARNING\\|ERROR\\|INFO\\)[^:]*: \\([^,]+\\),\\s-+\\(line \\)?\\([0-9]+\\):" 2 4 )
801 \\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\
802 :\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 2 5)
804 "\\(Error\\|Warning\\).*in file (\\([^ \t]+\\) at line *\\([0-9]+\\))" 2 3)
806 "\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 2 3)
808 "Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 2)
810 "\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 2 3)
812 "syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 1 2)
814 "%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 3 4)
816 "^In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\(Warning\\|Error\\|Failure\\)[^\n]*" 1 2)
818 "List of regexps for Verilog compilers.
819 See `compilation-error-regexp-alist' for the formatting. For Emacs 22+.")
821 (defvar verilog-error-regexp-xemacs-alist
822 ;; Emacs form is '((v-tool "re" 1 2) ...)
823 ;; XEmacs form is '(verilog ("re" 1 2) ...)
824 ;; So we can just map from Emacs to XEmacs
825 (cons 'verilog
(mapcar 'cdr verilog-error-regexp-emacs-alist
))
826 "List of regexps for Verilog compilers.
827 See `compilation-error-regexp-alist-alist' for the formatting. For XEmacs.")
829 (defvar verilog-error-font-lock-keywords
832 ("\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 bold t
)
833 ("\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 bold t
)
835 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\(line[ \t]+\\)?\\([0-9]+\\):.*$" 1 bold t
)
836 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\(line[ \t]+\\)?\\([0-9]+\\):.*$" 3 bold t
)
837 ;; verilog-IES (nc-verilog)
838 (".*\\*[WE],[0-9A-Z]+\\(\[[0-9A-Z_,]+\]\\)? (\\([^ \t,]+\\),\\([0-9]+\\)|" 2 bold t
)
839 (".*\\*[WE],[0-9A-Z]+\\(\[[0-9A-Z_,]+\]\\)? (\\([^ \t,]+\\),\\([0-9]+\\)|" 3 bold t
)
840 ;; verilog-surefire-1
841 ("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 1 bold t
)
842 ("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 2 bold t
)
843 ;; verilog-surefire-2
844 ("\\(WARNING\\|ERROR\\|INFO\\): \\([^,]+\\), line \\([0-9]+\\):" 2 bold t
)
845 ("\\(WARNING\\|ERROR\\|INFO\\): \\([^,]+\\), line \\([0-9]+\\):" 3 bold t
)
848 \\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\
849 :\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 bold t
)
851 \\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\
852 :\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 bold t
)
854 ("\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 2 bold t
)
855 ("\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 3 bold t
)
857 ("Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 bold t
)
858 ("Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 bold t
)
860 ("\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 2 bold t
)
861 ("\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 3 bold t
)
863 ("syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 1 bold t
)
864 ("syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 2 bold t
)
866 (".*%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 3 bold t
)
867 (".*%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 4 bold t
)
869 ("^In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\(Warning\\|Error\\|Failure\\)[^\n]*" 1 bold t
)
870 ("^In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\(Warning\\|Error\\|Failure\\)[^\n]*" 2 bold t
)
872 "*Keywords to also highlight in Verilog *compilation* buffers.
873 Only used in XEmacs; GNU Emacs uses `verilog-error-regexp-emacs-alist'.")
875 (defcustom verilog-library-flags
'("")
876 "*List of standard Verilog arguments to use for /*AUTOINST*/.
877 These arguments are used to find files for `verilog-auto', and match
878 the flags accepted by a standard Verilog-XL simulator.
880 -f filename Reads more `verilog-library-flags' from the filename.
881 +incdir+dir Adds the directory to `verilog-library-directories'.
882 -Idir Adds the directory to `verilog-library-directories'.
883 -y dir Adds the directory to `verilog-library-directories'.
884 +libext+.v Adds the extensions to `verilog-library-extensions'.
885 -v filename Adds the filename to `verilog-library-files'.
887 filename Adds the filename to `verilog-library-files'.
888 This is not recommended, -v is a better choice.
890 You might want these defined in each file; put at the *END* of your file
894 // verilog-library-flags:(\"-y dir -y otherdir\")
897 Verilog-mode attempts to detect changes to this local variable, but they
898 are only insured to be correct when the file is first visited. Thus if you
899 have problems, use \\[find-alternate-file] RET to have these take effect.
901 See also the variables mentioned above."
902 :group
'verilog-mode-auto
903 :type
'(repeat string
))
904 (put 'verilog-library-flags
'safe-local-variable
'listp
)
906 (defcustom verilog-library-directories
'(".")
907 "*List of directories when looking for files for /*AUTOINST*/.
908 The directory may be relative to the current file, or absolute.
909 Environment variables are also expanded in the directory names.
910 Having at least the current directory is a good idea.
912 You might want these defined in each file; put at the *END* of your file
916 // verilog-library-directories:(\".\" \"subdir\" \"subdir2\")
919 Verilog-mode attempts to detect changes to this local variable, but they
920 are only insured to be correct when the file is first visited. Thus if you
921 have problems, use \\[find-alternate-file] RET to have these take effect.
923 See also `verilog-library-flags', `verilog-library-files'
924 and `verilog-library-extensions'."
925 :group
'verilog-mode-auto
926 :type
'(repeat file
))
927 (put 'verilog-library-directories
'safe-local-variable
'listp
)
929 (defcustom verilog-library-files
'()
930 "*List of files to search for modules.
931 AUTOINST will use this when it needs to resolve a module name.
932 This is a complete path, usually to a technology file with many standard
935 You might want these defined in each file; put at the *END* of your file
939 // verilog-library-files:(\"/some/path/technology.v\" \"/some/path/tech2.v\")
942 Verilog-mode attempts to detect changes to this local variable, but they
943 are only insured to be correct when the file is first visited. Thus if you
944 have problems, use \\[find-alternate-file] RET to have these take effect.
946 See also `verilog-library-flags', `verilog-library-directories'."
947 :group
'verilog-mode-auto
948 :type
'(repeat directory
))
949 (put 'verilog-library-files
'safe-local-variable
'listp
)
951 (defcustom verilog-library-extensions
'(".v" ".sv")
952 "*List of extensions to use when looking for files for /*AUTOINST*/.
953 See also `verilog-library-flags', `verilog-library-directories'."
954 :type
'(repeat string
)
955 :group
'verilog-mode-auto
)
956 (put 'verilog-library-extensions
'safe-local-variable
'listp
)
958 (defcustom verilog-active-low-regexp nil
959 "*If set, treat signals matching this regexp as active low.
960 This is used for AUTORESET and AUTOTIEOFF. For proper behavior,
961 you will probably also need `verilog-auto-reset-widths' set."
962 :group
'verilog-mode-auto
964 (put 'verilog-active-low-regexp
'safe-local-variable
'stringp
)
966 (defcustom verilog-auto-sense-include-inputs nil
967 "*If true, AUTOSENSE should include all inputs.
968 If nil, only inputs that are NOT output signals in the same block are
970 :group
'verilog-mode-auto
972 (put 'verilog-auto-sense-include-inputs
'safe-local-variable
'verilog-booleanp
)
974 (defcustom verilog-auto-sense-defines-constant nil
975 "*If true, AUTOSENSE should assume all defines represent constants.
976 When true, the defines will not be included in sensitivity lists. To
977 maintain compatibility with other sites, this should be set at the bottom
978 of each Verilog file that requires it, rather than being set globally."
979 :group
'verilog-mode-auto
981 (put 'verilog-auto-sense-defines-constant
'safe-local-variable
'verilog-booleanp
)
983 (defcustom verilog-auto-reset-blocking-in-non t
984 "*If true, AUTORESET will reset those signals which were
985 assigned with blocking assignments (=) even in a block with
986 non-blocking assignments (<=).
988 If nil, all blocking assigned signals are ignored when any
989 non-blocking assignment is in the AUTORESET block. This allows
990 blocking assignments to be used for temporary values and not have
991 those temporaries reset. See example in `verilog-auto-reset'."
994 :group
'verilog-mode-auto
)
995 (put 'verilog-auto-reset-blocking-in-non
'safe-local-variable
'verilog-booleanp
)
997 (defcustom verilog-auto-reset-widths t
998 "*If true, AUTORESET should determine the width of signals.
999 This is then used to set the width of the zero (32'h0 for example). This
1000 is required by some lint tools that aren't smart enough to ignore widths of
1001 the constant zero. This may result in ugly code when parameters determine
1002 the MSB or LSB of a signal inside an AUTORESET."
1004 :group
'verilog-mode-auto
)
1005 (put 'verilog-auto-reset-widths
'safe-local-variable
'verilog-booleanp
)
1007 (defcustom verilog-assignment-delay
""
1008 "*Text used for delays in delayed assignments. Add a trailing space if set."
1009 :group
'verilog-mode-auto
1011 (put 'verilog-assignment-delay
'safe-local-variable
'stringp
)
1013 (defcustom verilog-auto-arg-sort nil
1014 "*If set, AUTOARG signal names will be sorted, not in declaration order.
1015 Declaration order is advantageous with order based instantiations
1016 and is the default for backward compatibility. Sorted order
1017 reduces changes when declarations are moved around in a file, and
1018 it's bad practice to rely on order based instantiations anyhow.
1020 See also `verilog-auto-inst-sort'."
1021 :group
'verilog-mode-auto
1023 (put 'verilog-auto-arg-sort
'safe-local-variable
'verilog-booleanp
)
1025 (defcustom verilog-auto-inst-dot-name nil
1026 "*If true, when creating ports with AUTOINST, use .name syntax.
1027 This will use \".port\" instead of \".port(port)\" when possible.
1028 This is only legal in SystemVerilog files, and will confuse older
1029 simulators. Setting `verilog-auto-inst-vector' to nil may also
1030 be desirable to increase how often .name will be used."
1031 :group
'verilog-mode-auto
1033 (put 'verilog-auto-inst-dot-name
'safe-local-variable
'verilog-booleanp
)
1035 (defcustom verilog-auto-inst-param-value nil
1036 "*If set, AUTOINST will replace parameters with the parameter value.
1037 If nil, leave parameters as symbolic names.
1039 Parameters must be in Verilog 2001 format #(...), and if a parameter is not
1040 listed as such there (as when the default value is acceptable), it will not
1041 be replaced, and will remain symbolic.
1043 For example, imagine a submodule uses parameters to declare the size of its
1044 inputs. This is then used by a upper module:
1046 module InstModule (o,i);
1048 input [WIDTH-1:0] i;
1058 Note even though PARAM=10, the AUTOINST has left the parameter as a
1059 symbolic name. If `verilog-auto-inst-param-value' is set, this will
1068 :group
'verilog-mode-auto
1070 (put 'verilog-auto-inst-param-value
'safe-local-variable
'verilog-booleanp
)
1072 (defcustom verilog-auto-inst-sort nil
1073 "*If set, AUTOINST signal names will be sorted, not in declaration order.
1074 Also affects AUTOINSTPARAM. Declaration order is the default for
1075 backward compatibility, and as some teams prefer signals that are
1076 declared together to remain together. Sorted order reduces
1077 changes when declarations are moved around in a file.
1079 See also `verilog-auto-arg-sort'."
1081 :group
'verilog-mode-auto
1083 (put 'verilog-auto-inst-sort
'safe-local-variable
'verilog-booleanp
)
1085 (defcustom verilog-auto-inst-vector t
1086 "*If true, when creating default ports with AUTOINST, use bus subscripts.
1087 If nil, skip the subscript when it matches the entire bus as declared in
1088 the module (AUTOWIRE signals always are subscripted, you must manually
1089 declare the wire to have the subscripts removed.) Setting this to nil may
1090 speed up some simulators, but is less general and harder to read, so avoid."
1091 :group
'verilog-mode-auto
1093 (put 'verilog-auto-inst-vector
'safe-local-variable
'verilog-booleanp
)
1095 (defcustom verilog-auto-inst-template-numbers nil
1096 "*If true, when creating templated ports with AUTOINST, add a comment.
1098 If t, the comment will add the line number of the template that
1099 was used for that port declaration. This setting is suggested
1100 only for debugging use, as regular use may cause a large numbers
1103 If 'lhs', the comment will show the left hand side of the
1104 AUTO_TEMPLATE rule that is matched. This is less precise than
1105 numbering (t) when multiple rules have the same pin name, but
1106 won't merge conflict."
1107 :group
'verilog-mode-auto
1108 :type
'(choice (const nil
) (const t
) (const lhs
)))
1109 (put 'verilog-auto-inst-template-numbers
'safe-local-variable
1110 '(lambda (x) (memq x
'(nil t lhs
))))
1112 (defcustom verilog-auto-inst-column
40
1113 "*Indent-to column number for net name part of AUTOINST created pin."
1114 :group
'verilog-mode-indent
1116 (put 'verilog-auto-inst-column
'safe-local-variable
'integerp
)
1118 (defcustom verilog-auto-input-ignore-regexp nil
1119 "*If set, when creating AUTOINPUT list, ignore signals matching this regexp.
1120 See the \\[verilog-faq] for examples on using this."
1121 :group
'verilog-mode-auto
1123 (put 'verilog-auto-input-ignore-regexp
'safe-local-variable
'stringp
)
1125 (defcustom verilog-auto-inout-ignore-regexp nil
1126 "*If set, when creating AUTOINOUT list, ignore signals matching this regexp.
1127 See the \\[verilog-faq] for examples on using this."
1128 :group
'verilog-mode-auto
1130 (put 'verilog-auto-inout-ignore-regexp
'safe-local-variable
'stringp
)
1132 (defcustom verilog-auto-output-ignore-regexp nil
1133 "*If set, when creating AUTOOUTPUT list, ignore signals matching this regexp.
1134 See the \\[verilog-faq] for examples on using this."
1135 :group
'verilog-mode-auto
1137 (put 'verilog-auto-output-ignore-regexp
'safe-local-variable
'stringp
)
1139 (defcustom verilog-auto-tieoff-declaration
"wire"
1140 "*Data type used for the declaration for AUTOTIEOFF. If \"wire\" then
1141 create a wire, if \"assign\" create an assignment, else the data type for
1144 :group
'verilog-mode-auto
1146 (put 'verilog-auto-tieoff-declaration
'safe-local-variable
'stringp
)
1148 (defcustom verilog-auto-tieoff-ignore-regexp nil
1149 "*If set, when creating AUTOTIEOFF list, ignore signals matching this regexp.
1150 See the \\[verilog-faq] for examples on using this."
1151 :group
'verilog-mode-auto
1153 (put 'verilog-auto-tieoff-ignore-regexp
'safe-local-variable
'stringp
)
1155 (defcustom verilog-auto-unused-ignore-regexp nil
1156 "*If set, when creating AUTOUNUSED list, ignore signals matching this regexp.
1157 See the \\[verilog-faq] for examples on using this."
1158 :group
'verilog-mode-auto
1160 (put 'verilog-auto-unused-ignore-regexp
'safe-local-variable
'stringp
)
1162 (defcustom verilog-typedef-regexp nil
1163 "*If non-nil, regular expression that matches Verilog-2001 typedef names.
1164 For example, \"_t$\" matches typedefs named with _t, as in the C language."
1165 :group
'verilog-mode-auto
1167 (put 'verilog-typedef-regexp
'safe-local-variable
'stringp
)
1169 (defcustom verilog-mode-hook
'verilog-set-compile-command
1170 "*Hook run after Verilog mode is loaded."
1172 :group
'verilog-mode
)
1174 (defcustom verilog-auto-hook nil
1175 "*Hook run after `verilog-mode' updates AUTOs."
1176 :group
'verilog-mode-auto
1179 (defcustom verilog-before-auto-hook nil
1180 "*Hook run before `verilog-mode' updates AUTOs."
1181 :group
'verilog-mode-auto
1184 (defcustom verilog-delete-auto-hook nil
1185 "*Hook run after `verilog-mode' deletes AUTOs."
1186 :group
'verilog-mode-auto
1189 (defcustom verilog-before-delete-auto-hook nil
1190 "*Hook run before `verilog-mode' deletes AUTOs."
1191 :group
'verilog-mode-auto
1194 (defcustom verilog-getopt-flags-hook nil
1195 "*Hook run after `verilog-getopt-flags' determines the Verilog option lists."
1196 :group
'verilog-mode-auto
1199 (defcustom verilog-before-getopt-flags-hook nil
1200 "*Hook run before `verilog-getopt-flags' determines the Verilog option lists."
1201 :group
'verilog-mode-auto
1204 (defvar verilog-imenu-generic-expression
1205 '((nil "^\\s-*\\(\\(m\\(odule\\|acromodule\\)\\)\\|primitive\\)\\s-+\\([a-zA-Z0-9_.:]+\\)" 4)
1206 ("*Vars*" "^\\s-*\\(reg\\|wire\\)\\s-+\\(\\|\\[[^]]+\\]\\s-+\\)\\([A-Za-z0-9_]+\\)" 3))
1207 "Imenu expression for Verilog mode. See `imenu-generic-expression'.")
1210 ;; provide a verilog-header function.
1211 ;; Customization variables:
1213 (defvar verilog-date-scientific-format nil
1214 "*If non-nil, dates are written in scientific format (e.g. 1997/09/17).
1215 If nil, in European format (e.g. 17.09.1997). The brain-dead American
1216 format (e.g. 09/17/1997) is not supported.")
1218 (defvar verilog-company nil
1219 "*Default name of Company for Verilog header.
1220 If set will become buffer local.")
1221 (make-variable-buffer-local 'verilog-company
)
1223 (defvar verilog-project nil
1224 "*Default name of Project for Verilog header.
1225 If set will become buffer local.")
1226 (make-variable-buffer-local 'verilog-project
)
1228 (defvar verilog-mode-map
1229 (let ((map (make-sparse-keymap)))
1230 (define-key map
";" 'electric-verilog-semi
)
1231 (define-key map
[(control 59)] 'electric-verilog-semi-with-comment
)
1232 (define-key map
":" 'electric-verilog-colon
)
1233 ;;(define-key map "=" 'electric-verilog-equal)
1234 (define-key map
"\`" 'electric-verilog-tick
)
1235 (define-key map
"\t" 'electric-verilog-tab
)
1236 (define-key map
"\r" 'electric-verilog-terminate-line
)
1237 ;; backspace/delete key bindings
1238 (define-key map
[backspace] 'backward-delete-char-untabify)
1239 (unless (boundp 'delete-key-deletes-forward) ; XEmacs variable
1240 (define-key map [delete] 'delete-char)
1241 (define-key map [(meta delete)] 'kill-word))
1242 (define-key map "\M-\C-b" 'electric-verilog-backward-sexp)
1243 (define-key map "\M-\C-f" 'electric-verilog-forward-sexp)
1244 (define-key map "\M-\r" `electric-verilog-terminate-and-indent)
1245 (define-key map "\M-\t" 'verilog-complete-word)
1246 (define-key map "\M-?" 'verilog-show-completions)
1247 ;; Note \C-c and letter are reserved for users
1248 (define-key map "\C-c\`" 'verilog-lint-off)
1249 (define-key map "\C-c\*" 'verilog-delete-auto-star-implicit)
1250 (define-key map "\C-c\?" 'verilog-diff-auto)
1251 (define-key map "\C-c\C-r" 'verilog-label-be)
1252 (define-key map "\C-c\C-i" 'verilog-pretty-declarations)
1253 (define-key map "\C-c=" 'verilog-pretty-expr)
1254 (define-key map "\C-c\C-b" 'verilog-submit-bug-report)
1255 (define-key map "\M-*" 'verilog-star-comment)
1256 (define-key map "\C-c\C-c" 'verilog-comment-region)
1257 (define-key map "\C-c\C-u" 'verilog-uncomment-region)
1258 (when (featurep 'xemacs)
1259 (define-key map [(meta control h)] 'verilog-mark-defun)
1260 (define-key map "\M-\C-a" 'verilog-beg-of-defun)
1261 (define-key map "\M-\C-e" 'verilog-end-of-defun))
1262 (define-key map "\C-c\C-d" 'verilog-goto-defun)
1263 (define-key map "\C-c\C-k" 'verilog-delete-auto)
1264 (define-key map "\C-c\C-a" 'verilog-auto)
1265 (define-key map "\C-c\C-s" 'verilog-auto-save-compile)
1266 (define-key map "\C-c\C-p" 'verilog-preprocess)
1267 (define-key map "\C-c\C-z" 'verilog-inject-auto)
1268 (define-key map "\C-c\C-e" 'verilog-expand-vector)
1269 (define-key map "\C-c\C-h" 'verilog-header)
1271 "Keymap used in Verilog mode.")
1275 verilog-menu verilog-mode-map "Menu for Verilog mode"
1276 (verilog-easy-menu-filter
1278 ("Choose Compilation Action"
1281 (setq verilog-tool nil)
1282 (verilog-set-compile-command))
1284 :selected (equal verilog-tool nil)
1285 :help "When invoking compilation, use compile-command"]
1288 (setq verilog-tool 'verilog-linter)
1289 (verilog-set-compile-command))
1291 :selected (equal verilog-tool `verilog-linter)
1292 :help "When invoking compilation, use lint checker"]
1295 (setq verilog-tool 'verilog-coverage)
1296 (verilog-set-compile-command))
1298 :selected (equal verilog-tool `verilog-coverage)
1299 :help "When invoking compilation, annotate for coverage"]
1302 (setq verilog-tool 'verilog-simulator)
1303 (verilog-set-compile-command))
1305 :selected (equal verilog-tool `verilog-simulator)
1306 :help "When invoking compilation, interpret Verilog source"]
1309 (setq verilog-tool 'verilog-compiler)
1310 (verilog-set-compile-command))
1312 :selected (equal verilog-tool `verilog-compiler)
1313 :help "When invoking compilation, compile Verilog source"]
1316 (setq verilog-tool 'verilog-preprocessor)
1317 (verilog-set-compile-command))
1319 :selected (equal verilog-tool `verilog-preprocessor)
1320 :help "When invoking compilation, preprocess Verilog source, see also `verilog-preprocess'"]
1323 ["Beginning of function" verilog-beg-of-defun
1325 :help "Move backward to the beginning of the current function or procedure"]
1326 ["End of function" verilog-end-of-defun
1328 :help "Move forward to the end of the current function or procedure"]
1329 ["Mark function" verilog-mark-defun
1331 :help "Mark the current Verilog function or procedure"]
1332 ["Goto function/module" verilog-goto-defun
1333 :help "Move to specified Verilog module/task/function"]
1334 ["Move to beginning of block" electric-verilog-backward-sexp
1335 :help "Move backward over one balanced expression"]
1336 ["Move to end of block" electric-verilog-forward-sexp
1337 :help "Move forward over one balanced expression"]
1340 ["Comment Region" verilog-comment-region
1341 :help "Put marked area into a comment"]
1342 ["UnComment Region" verilog-uncomment-region
1343 :help "Uncomment an area commented with Comment Region"]
1344 ["Multi-line comment insert" verilog-star-comment
1345 :help "Insert Verilog /* */ comment at point"]
1346 ["Lint error to comment" verilog-lint-off
1347 :help "Convert a Verilog linter warning line into a disable statement"]
1351 :help "Perform compilation-action (above) on the current buffer"]
1352 ["AUTO, Save, Compile" verilog-auto-save-compile
1353 :help "Recompute AUTOs, save buffer, and compile"]
1354 ["Next Compile Error" next-error
1355 :help "Visit next compilation error message and corresponding source code"]
1356 ["Ignore Lint Warning at point" verilog-lint-off
1357 :help "Convert a Verilog linter warning line into a disable statement"]
1359 ["Line up declarations around point" verilog-pretty-declarations
1360 :help "Line up declarations around point"]
1361 ["Line up equations around point" verilog-pretty-expr
1362 :help "Line up expressions around point"]
1363 ["Redo/insert comments on every end" verilog-label-be
1364 :help "Label matching begin ... end statements"]
1365 ["Expand [x:y] vector line" verilog-expand-vector
1366 :help "Take a signal vector on the current line and expand it to multiple lines"]
1367 ["Insert begin-end block" verilog-insert-block
1368 :help "Insert begin ... end"]
1369 ["Complete word" verilog-complete-word
1370 :help "Complete word at point"]
1372 ["Recompute AUTOs" verilog-auto
1373 :help "Expand AUTO meta-comment statements"]
1374 ["Kill AUTOs" verilog-delete-auto
1375 :help "Remove AUTO expansions"]
1376 ["Diff AUTOs" verilog-diff-auto
1377 :help "Show differences in AUTO expansions"]
1378 ["Inject AUTOs" verilog-inject-auto
1379 :help "Inject AUTOs into legacy non-AUTO buffer"]
1381 ["AUTO General" (describe-function 'verilog-auto)
1382 :help "Help introduction on AUTOs"]
1383 ["AUTO Library Flags" (describe-variable 'verilog-library-flags)
1384 :help "Help on verilog-library-flags"]
1385 ["AUTO Library Path" (describe-variable 'verilog-library-directories)
1386 :help "Help on verilog-library-directories"]
1387 ["AUTO Library Files" (describe-variable 'verilog-library-files)
1388 :help "Help on verilog-library-files"]
1389 ["AUTO Library Extensions" (describe-variable 'verilog-library-extensions)
1390 :help "Help on verilog-library-extensions"]
1391 ["AUTO `define Reading" (describe-function 'verilog-read-defines)
1392 :help "Help on reading `defines"]
1393 ["AUTO `include Reading" (describe-function 'verilog-read-includes)
1394 :help "Help on parsing `includes"]
1395 ["AUTOARG" (describe-function 'verilog-auto-arg)
1396 :help "Help on AUTOARG - declaring module port list"]
1397 ["AUTOASCIIENUM" (describe-function 'verilog-auto-ascii-enum)
1398 :help "Help on AUTOASCIIENUM - creating ASCII for enumerations"]
1399 ["AUTOINOUTCOMP" (describe-function 'verilog-auto-inout-comp)
1400 :help "Help on AUTOINOUTCOMP - copying complemented i/o from another file"]
1401 ["AUTOINOUTIN" (describe-function 'verilog-auto-inout-in)
1402 :help "Help on AUTOINOUTCOMP - copying i/o from another file as all inputs"]
1403 ["AUTOINOUTMODULE" (describe-function 'verilog-auto-inout-module)
1404 :help "Help on AUTOINOUTMODULE - copying i/o from another file"]
1405 ["AUTOINSERTLISP" (describe-function 'verilog-auto-insert-lisp)
1406 :help "Help on AUTOINSERTLISP - insert text from a lisp function"]
1407 ["AUTOINOUT" (describe-function 'verilog-auto-inout)
1408 :help "Help on AUTOINOUT - adding inouts from cells"]
1409 ["AUTOINPUT" (describe-function 'verilog-auto-input)
1410 :help "Help on AUTOINPUT - adding inputs from cells"]
1411 ["AUTOINST" (describe-function 'verilog-auto-inst)
1412 :help "Help on AUTOINST - adding pins for cells"]
1413 ["AUTOINST (.*)" (describe-function 'verilog-auto-star)
1414 :help "Help on expanding Verilog-2001 .* pins"]
1415 ["AUTOINSTPARAM" (describe-function 'verilog-auto-inst-param)
1416 :help "Help on AUTOINSTPARAM - adding parameter pins to cells"]
1417 ["AUTOLOGIC" (describe-function 'verilog-auto-logic)
1418 :help "Help on AUTOLOGIC - declaring logic signals"]
1419 ["AUTOOUTPUT" (describe-function 'verilog-auto-output)
1420 :help "Help on AUTOOUTPUT - adding outputs from cells"]
1421 ["AUTOOUTPUTEVERY" (describe-function 'verilog-auto-output-every)
1422 :help "Help on AUTOOUTPUTEVERY - adding outputs of all signals"]
1423 ["AUTOREG" (describe-function 'verilog-auto-reg)
1424 :help "Help on AUTOREG - declaring registers for non-wires"]
1425 ["AUTOREGINPUT" (describe-function 'verilog-auto-reg-input)
1426 :help "Help on AUTOREGINPUT - declaring inputs for non-wires"]
1427 ["AUTORESET" (describe-function 'verilog-auto-reset)
1428 :help "Help on AUTORESET - resetting always blocks"]
1429 ["AUTOSENSE" (describe-function 'verilog-auto-sense)
1430 :help "Help on AUTOSENSE - sensitivity lists for always blocks"]
1431 ["AUTOTIEOFF" (describe-function 'verilog-auto-tieoff)
1432 :help "Help on AUTOTIEOFF - tying off unused outputs"]
1433 ["AUTOUNUSED" (describe-function 'verilog-auto-unused)
1434 :help "Help on AUTOUNUSED - terminating unused inputs"]
1435 ["AUTOWIRE" (describe-function 'verilog-auto-wire)
1436 :help "Help on AUTOWIRE - declaring wires for cells"]
1439 ["Submit bug report" verilog-submit-bug-report
1440 :help "Submit via mail a bug report on verilog-mode.el"]
1441 ["Version and FAQ" verilog-faq
1442 :help "Show the current version, and where to get the FAQ etc"]
1443 ["Customize Verilog Mode..." verilog-customize
1444 :help "Customize variables and other settings used by Verilog-Mode"]
1445 ["Customize Verilog Fonts & Colors" verilog-font-customize
1446 :help "Customize fonts used by Verilog-Mode."])))
1449 verilog-stmt-menu verilog-mode-map "Menu for statement templates in Verilog."
1450 (verilog-easy-menu-filter
1452 ["Header" verilog-sk-header
1453 :help "Insert a header block at the top of file"]
1454 ["Comment" verilog-sk-comment
1455 :help "Insert a comment block"]
1457 ["Module" verilog-sk-module
1458 :help "Insert a module .. (/*AUTOARG*/);.. endmodule block"]
1459 ["OVM Class" verilog-sk-ovm-class
1460 :help "Insert an OVM class block"]
1461 ["UVM Class" verilog-sk-uvm-class
1462 :help "Insert an UVM class block"]
1463 ["Primitive" verilog-sk-primitive
1464 :help "Insert a primitive .. (.. );.. endprimitive block"]
1466 ["Input" verilog-sk-input
1467 :help "Insert an input declaration"]
1468 ["Output" verilog-sk-output
1469 :help "Insert an output declaration"]
1470 ["Inout" verilog-sk-inout
1471 :help "Insert an inout declaration"]
1472 ["Wire" verilog-sk-wire
1473 :help "Insert a wire declaration"]
1474 ["Reg" verilog-sk-reg
1475 :help "Insert a register declaration"]
1476 ["Define thing under point as a register" verilog-sk-define-signal
1477 :help "Define signal under point as a register at the top of the module"]
1479 ["Initial" verilog-sk-initial
1480 :help "Insert an initial begin .. end block"]
1481 ["Always" verilog-sk-always
1482 :help "Insert an always @(AS) begin .. end block"]
1483 ["Function" verilog-sk-function
1484 :help "Insert a function .. begin .. end endfunction block"]
1485 ["Task" verilog-sk-task
1486 :help "Insert a task .. begin .. end endtask block"]
1487 ["Specify" verilog-sk-specify
1488 :help "Insert a specify .. endspecify block"]
1489 ["Generate" verilog-sk-generate
1490 :help "Insert a generate .. endgenerate block"]
1492 ["Begin" verilog-sk-begin
1493 :help "Insert a begin .. end block"]
1495 :help "Insert an if (..) begin .. end block"]
1496 ["(if) else" verilog-sk-else-if
1497 :help "Insert an else if (..) begin .. end block"]
1498 ["For" verilog-sk-for
1499 :help "Insert a for (...) begin .. end block"]
1500 ["While" verilog-sk-while
1501 :help "Insert a while (...) begin .. end block"]
1502 ["Fork" verilog-sk-fork
1503 :help "Insert a fork begin .. end .. join block"]
1504 ["Repeat" verilog-sk-repeat
1505 :help "Insert a repeat (..) begin .. end block"]
1506 ["Case" verilog-sk-case
1507 :help "Insert a case block, prompting for details"]
1508 ["Casex" verilog-sk-casex
1509 :help "Insert a casex (...) item: begin.. end endcase block"]
1510 ["Casez" verilog-sk-casez
1511 :help "Insert a casez (...) item: begin.. end endcase block"])))
1513 (defvar verilog-mode-abbrev-table nil
1514 "Abbrev table in use in Verilog-mode buffers.")
1516 (define-abbrev-table 'verilog-mode-abbrev-table ())
1517 (verilog-define-abbrev verilog-mode-abbrev-table "class" "" 'verilog-sk-ovm-class)
1518 (verilog-define-abbrev verilog-mode-abbrev-table "always" "" 'verilog-sk-always)
1519 (verilog-define-abbrev verilog-mode-abbrev-table "begin" nil `verilog-sk-begin)
1520 (verilog-define-abbrev verilog-mode-abbrev-table "case" "" `verilog-sk-case)
1521 (verilog-define-abbrev verilog-mode-abbrev-table "for" "" `verilog-sk-for)
1522 (verilog-define-abbrev verilog-mode-abbrev-table "generate" "" `verilog-sk-generate)
1523 (verilog-define-abbrev verilog-mode-abbrev-table "initial" "" `verilog-sk-initial)
1524 (verilog-define-abbrev verilog-mode-abbrev-table "fork" "" `verilog-sk-fork)
1525 (verilog-define-abbrev verilog-mode-abbrev-table "module" "" `verilog-sk-module)
1526 (verilog-define-abbrev verilog-mode-abbrev-table "primitive" "" `verilog-sk-primitive)
1527 (verilog-define-abbrev verilog-mode-abbrev-table "repeat" "" `verilog-sk-repeat)
1528 (verilog-define-abbrev verilog-mode-abbrev-table "specify" "" `verilog-sk-specify)
1529 (verilog-define-abbrev verilog-mode-abbrev-table "task" "" `verilog-sk-task)
1530 (verilog-define-abbrev verilog-mode-abbrev-table "while" "" `verilog-sk-while)
1531 (verilog-define-abbrev verilog-mode-abbrev-table "casex" "" `verilog-sk-casex)
1532 (verilog-define-abbrev verilog-mode-abbrev-table "casez" "" `verilog-sk-casez)
1533 (verilog-define-abbrev verilog-mode-abbrev-table "if" "" `verilog-sk-if)
1534 (verilog-define-abbrev verilog-mode-abbrev-table "else if" "" `verilog-sk-else-if)
1535 (verilog-define-abbrev verilog-mode-abbrev-table "assign" "" `verilog-sk-assign)
1536 (verilog-define-abbrev verilog-mode-abbrev-table "function" "" `verilog-sk-function)
1537 (verilog-define-abbrev verilog-mode-abbrev-table "input" "" `verilog-sk-input)
1538 (verilog-define-abbrev verilog-mode-abbrev-table "output" "" `verilog-sk-output)
1539 (verilog-define-abbrev verilog-mode-abbrev-table "inout" "" `verilog-sk-inout)
1540 (verilog-define-abbrev verilog-mode-abbrev-table "wire" "" `verilog-sk-wire)
1541 (verilog-define-abbrev verilog-mode-abbrev-table "reg" "" `verilog-sk-reg)
1547 (defsubst verilog-within-string ()
1548 (nth 3 (parse-partial-sexp (point-at-bol) (point))))
1550 (defsubst verilog-string-replace-matches (from-string to-string fixedcase literal string)
1551 "Replace occurrences of FROM-STRING with TO-STRING.
1552 FIXEDCASE and LITERAL as in `replace-match`. STRING is what to replace.
1553 The case (verilog-string-replace-matches \"o\" \"oo\" nil nil \"foobar\")
1554 will break, as the o's continuously replace. xa -> x works ok though."
1555 ;; Hopefully soon to a emacs built-in
1556 ;; Also note \ in the replacement prevent multiple replacements; IE
1557 ;; (verilog-string-replace-matches "@" "\\\\([0-9]+\\\\)" nil nil "wire@_@")
1558 ;; Gives "wire\([0-9]+\)_@" not "wire\([0-9]+\)_\([0-9]+\)"
1560 (while (string-match from-string string start)
1561 (setq string (replace-match to-string fixedcase literal string)
1562 start (min (length string) (+ (match-beginning 0) (length to-string)))))
1565 (defsubst verilog-string-remove-spaces (string)
1566 "Remove spaces surrounding STRING."
1568 (setq string (verilog-string-replace-matches "^\\s-+" "" nil nil string))
1569 (setq string (verilog-string-replace-matches "\\s-+$" "" nil nil string))
1572 (defsubst verilog-re-search-forward (REGEXP BOUND NOERROR)
1573 ; checkdoc-params: (REGEXP BOUND NOERROR)
1574 "Like `re-search-forward', but skips over match in comments or strings."
1575 (let ((mdata '(nil nil))) ;; So match-end will return nil if no matches found
1577 (re-search-forward REGEXP BOUND NOERROR)
1578 (setq mdata (match-data))
1579 (and (verilog-skip-forward-comment-or-string)
1581 (setq mdata '(nil nil))
1585 (store-match-data mdata)
1588 (defsubst verilog-re-search-backward (REGEXP BOUND NOERROR)
1589 ; checkdoc-params: (REGEXP BOUND NOERROR)
1590 "Like `re-search-backward', but skips over match in comments or strings."
1591 (let ((mdata '(nil nil))) ;; So match-end will return nil if no matches found
1593 (re-search-backward REGEXP BOUND NOERROR)
1594 (setq mdata (match-data))
1595 (and (verilog-skip-backward-comment-or-string)
1597 (setq mdata '(nil nil))
1601 (store-match-data mdata)
1604 (defsubst verilog-re-search-forward-quick (regexp bound noerror)
1605 "Like `verilog-re-search-forward', including use of REGEXP BOUND and NOERROR,
1606 but trashes match data and is faster for REGEXP that doesn't match often.
1607 This uses `verilog-scan' and text properties to ignore comments,
1608 so there may be a large up front penalty for the first search."
1610 (while (and (not pt)
1611 (re-search-forward regexp bound noerror))
1612 (if (verilog-inside-comment-or-string-p)
1613 (re-search-forward "[/\"\n]" nil t) ;; Only way a comment or quote can end
1614 (setq pt (match-end 0))))
1617 (defsubst verilog-re-search-backward-quick (regexp bound noerror)
1618 ; checkdoc-params: (REGEXP BOUND NOERROR)
1619 "Like `verilog-re-search-backward', including use of REGEXP BOUND and NOERROR,
1620 but trashes match data and is faster for REGEXP that doesn't match often.
1621 This uses `verilog-scan' and text properties to ignore comments,
1622 so there may be a large up front penalty for the first search."
1624 (while (and (not pt)
1625 (re-search-backward regexp bound noerror))
1626 (if (verilog-inside-comment-or-string-p)
1627 (re-search-backward "[/\"]" nil t) ;; Only way a comment or quote can begin
1628 (setq pt (match-beginning 0))))
1631 (defsubst verilog-re-search-forward-substr (substr regexp bound noerror)
1632 "Like `re-search-forward', but first search for SUBSTR constant.
1633 Then searched for the normal REGEXP (which contains SUBSTR), with given
1634 BOUND and NOERROR. The REGEXP must fit within a single line.
1635 This speeds up complicated regexp matches."
1636 ;; Problem with overlap: search-forward BAR then FOOBARBAZ won't match.
1637 ;; thus require matches to be on one line, and use beginning-of-line.
1639 (while (and (not done)
1640 (search-forward substr bound noerror))
1643 (setq done (re-search-forward regexp (point-at-eol) noerror)))
1644 (unless (and (<= (match-beginning 0) (point))
1645 (>= (match-end 0) (point)))
1647 (when done (goto-char done))
1649 ;;(verilog-re-search-forward-substr "-end" "get-end-of" nil t) ;;-end (test bait)
1651 (defsubst verilog-re-search-backward-substr (substr regexp bound noerror)
1652 "Like `re-search-backward', but first search for SUBSTR constant.
1653 Then searched for the normal REGEXP (which contains SUBSTR), with given
1654 BOUND and NOERROR. The REGEXP must fit within a single line.
1655 This speeds up complicated regexp matches."
1656 ;; Problem with overlap: search-backward BAR then FOOBARBAZ won't match.
1657 ;; thus require matches to be on one line, and use beginning-of-line.
1659 (while (and (not done)
1660 (search-backward substr bound noerror))
1663 (setq done (re-search-backward regexp (point-at-bol) noerror)))
1664 (unless (and (<= (match-beginning 0) (point))
1665 (>= (match-end 0) (point)))
1667 (when done (goto-char done))
1669 ;;(verilog-re-search-backward-substr "-end" "get-end-of" nil t) ;;-end (test bait)
1671 (defun verilog-delete-trailing-whitespace ()
1672 "Delete trailing spaces or tabs, but not newlines nor linefeeds."
1673 ;; Similar to `delete-trailing-whitespace' but that's not present in XEmacs
1675 (goto-char (point-min))
1676 (while (re-search-forward "[ \t]+$" nil t) ;; Not syntactic WS as no formfeed
1677 (replace-match "" nil nil))))
1679 (defvar compile-command)
1681 ;; compilation program
1682 (defun verilog-set-compile-command ()
1683 "Function to compute shell command to compile Verilog.
1685 This reads `verilog-tool' and sets `compile-command'. This specifies the
1686 program that executes when you type \\[compile] or
1687 \\[verilog-auto-save-compile].
1689 By default `verilog-tool' uses a Makefile if one exists in the
1690 current directory. If not, it is set to the `verilog-linter',
1691 `verilog-compiler', `verilog-coverage', `verilog-preprocessor',
1692 or `verilog-simulator' variables, as selected with the Verilog ->
1693 \"Choose Compilation Action\" menu.
1695 You should set `verilog-tool' or the other variables to the path and
1696 arguments for your Verilog simulator. For example:
1699 \"(cd /tmp; surecov %s)\".
1701 In the former case, the path to the current buffer is concat'ed to the
1702 value of `verilog-tool'; in the later, the path to the current buffer is
1703 substituted for the %s.
1705 Where __FLAGS__ appears in the string `verilog-current-flags'
1706 will be substituted.
1708 Where __FILE__ appears in the string, the variable
1709 `buffer-file-name' of the current buffer, without the directory
1710 portion, will be substituted."
1713 ((or (file-exists-p "makefile") ;If there is a makefile, use it
1714 (file-exists-p "Makefile"))
1715 (set (make-local-variable 'compile-command) "make "))
1717 (set (make-local-variable 'compile-command)
1719 (if (string-match "%s" (eval verilog-tool))
1720 (format (eval verilog-tool) (or buffer-file-name ""))
1721 (concat (eval verilog-tool) " " (or buffer-file-name "")))
1723 (verilog-modify-compile-command))
1725 (defun verilog-expand-command (command)
1726 "Replace meta-information in COMMAND and return it.
1727 Where __FLAGS__ appears in the string `verilog-current-flags'
1728 will be substituted. Where __FILE__ appears in the string, the
1729 current buffer's file-name, without the directory portion, will
1731 (setq command (verilog-string-replace-matches
1732 ;; Note \\b only works if under verilog syntax table
1733 "\\b__FLAGS__\\b" (verilog-current-flags)
1735 (setq command (verilog-string-replace-matches
1736 "\\b__FILE__\\b" (file-name-nondirectory
1737 (or (buffer-file-name) ""))
1741 (defun verilog-modify-compile-command ()
1742 "Update `compile-command' using `verilog-expand-command'."
1744 (stringp compile-command)
1745 (string-match "\\b\\(__FLAGS__\\|__FILE__\\)\\b" compile-command))
1746 (set (make-local-variable 'compile-command)
1747 (verilog-expand-command compile-command))))
1749 (if (featurep 'xemacs)
1750 ;; Following code only gets called from compilation-mode-hook on XEmacs to add error handling.
1751 (defun verilog-error-regexp-add-xemacs ()
1752 "Teach XEmacs about verilog errors.
1753 Called by `compilation-mode-hook'. This allows \\[next-error] to
1756 (if (boundp 'compilation-error-regexp-systems-alist)
1758 (not (equal compilation-error-regexp-systems-list 'all))
1759 (not (member compilation-error-regexp-systems-list 'verilog)))
1760 (push 'verilog compilation-error-regexp-systems-list)))
1761 (if (boundp 'compilation-error-regexp-alist-alist)
1762 (if (not (assoc 'verilog compilation-error-regexp-alist-alist))
1763 (setcdr compilation-error-regexp-alist-alist
1764 (cons verilog-error-regexp-xemacs-alist
1765 (cdr compilation-error-regexp-alist-alist)))))
1766 (if (boundp 'compilation-font-lock-keywords)
1768 (set (make-local-variable 'compilation-font-lock-keywords)
1769 verilog-error-font-lock-keywords)
1770 (font-lock-set-defaults)))
1771 ;; Need to re-run compilation-error-regexp builder
1772 (if (fboundp 'compilation-build-compilation-error-regexp-alist)
1773 (compilation-build-compilation-error-regexp-alist))
1776 ;; Following code only gets called from compilation-mode-hook on Emacs to add error handling.
1777 (defun verilog-error-regexp-add-emacs ()
1778 "Tell Emacs compile that we are Verilog.
1779 Called by `compilation-mode-hook'. This allows \\[next-error] to
1782 (if (boundp 'compilation-error-regexp-alist-alist)
1784 (if (not (assoc 'verilog-xl-1 compilation-error-regexp-alist-alist))
1787 (push (car item) compilation-error-regexp-alist)
1788 (push item compilation-error-regexp-alist-alist)
1790 verilog-error-regexp-emacs-alist)))))
1792 (if (featurep 'xemacs) (add-hook 'compilation-mode-hook 'verilog-error-regexp-add-xemacs))
1793 (if (featurep 'emacs) (add-hook 'compilation-mode-hook 'verilog-error-regexp-add-emacs))
1795 (defconst verilog-directive-re
1797 (verilog-regexp-words
1799 "`case" "`default" "`define" "`else" "`elsif" "`endfor" "`endif"
1800 "`endprotect" "`endswitch" "`endwhile" "`for" "`format" "`if" "`ifdef"
1801 "`ifndef" "`include" "`let" "`protect" "`switch" "`timescale"
1802 "`time_scale" "`undef" "`while" ))))
1804 (defconst verilog-directive-re-1
1805 (concat "[ \t]*" verilog-directive-re))
1807 (defconst verilog-directive-begin
1808 "\\<`\\(for\\|i\\(f\\|fdef\\|fndef\\)\\|switch\\|while\\)\\>")
1810 (defconst verilog-directive-middle
1811 "\\<`\\(else\\|elsif\\|default\\|case\\)\\>")
1813 (defconst verilog-directive-end
1814 "`\\(endfor\\|endif\\|endswitch\\|endwhile\\)\\>")
1816 (defconst verilog-ovm-begin-re
1820 "`ovm_component_utils_begin"
1821 "`ovm_component_param_utils_begin"
1822 "`ovm_field_utils_begin"
1823 "`ovm_object_utils_begin"
1824 "`ovm_object_param_utils_begin"
1825 "`ovm_sequence_utils_begin"
1826 "`ovm_sequencer_utils_begin"
1829 (defconst verilog-ovm-end-re
1833 "`ovm_component_utils_end"
1834 "`ovm_field_utils_end"
1835 "`ovm_object_utils_end"
1836 "`ovm_sequence_utils_end"
1837 "`ovm_sequencer_utils_end"
1840 (defconst verilog-uvm-begin-re
1844 "`uvm_component_utils_begin"
1845 "`uvm_component_param_utils_begin"
1846 "`uvm_field_utils_begin"
1847 "`uvm_object_utils_begin"
1848 "`uvm_object_param_utils_begin"
1849 "`uvm_sequence_utils_begin"
1850 "`uvm_sequencer_utils_begin"
1853 (defconst verilog-uvm-end-re
1857 "`uvm_component_utils_end"
1858 "`uvm_field_utils_end"
1859 "`uvm_object_utils_end"
1860 "`uvm_sequence_utils_end"
1861 "`uvm_sequencer_utils_end"
1864 (defconst verilog-vmm-begin-re
1868 "`vmm_data_member_begin"
1869 "`vmm_env_member_begin"
1870 "`vmm_scenario_member_begin"
1871 "`vmm_subenv_member_begin"
1872 "`vmm_xactor_member_begin"
1875 (defconst verilog-vmm-end-re
1879 "`vmm_data_member_end"
1880 "`vmm_env_member_end"
1881 "`vmm_scenario_member_end"
1882 "`vmm_subenv_member_end"
1883 "`vmm_xactor_member_end"
1886 (defconst verilog-vmm-statement-re
1890 ;; "`vmm_xactor_member_enum_array"
1891 "`vmm_\\(data\\|env\\|scenario\\|subenv\\|xactor\\)_member_\\(scalar\\|string\\|enum\\|vmm_data\\|channel\\|xactor\\|subenv\\|user_defined\\)\\(_array\\)?"
1892 ;; "`vmm_xactor_member_scalar_array"
1893 ;; "`vmm_xactor_member_scalar"
1896 (defconst verilog-ovm-statement-re
1905 "`ovm_analysis_imp_decl"
1906 "`ovm_blocking_get_imp_decl"
1907 "`ovm_blocking_get_peek_imp_decl"
1908 "`ovm_blocking_master_imp_decl"
1909 "`ovm_blocking_peek_imp_decl"
1910 "`ovm_blocking_put_imp_decl"
1911 "`ovm_blocking_slave_imp_decl"
1912 "`ovm_blocking_transport_imp_decl"
1913 "`ovm_component_registry"
1914 "`ovm_component_registry_param"
1915 "`ovm_component_utils"
1918 "`ovm_declare_sequence_lib"
1925 "`ovm_field_aa_int_byte"
1926 "`ovm_field_aa_int_byte_unsigned"
1927 "`ovm_field_aa_int_int"
1928 "`ovm_field_aa_int_int_unsigned"
1929 "`ovm_field_aa_int_integer"
1930 "`ovm_field_aa_int_integer_unsigned"
1931 "`ovm_field_aa_int_key"
1932 "`ovm_field_aa_int_longint"
1933 "`ovm_field_aa_int_longint_unsigned"
1934 "`ovm_field_aa_int_shortint"
1935 "`ovm_field_aa_int_shortint_unsigned"
1936 "`ovm_field_aa_int_string"
1937 "`ovm_field_aa_object_int"
1938 "`ovm_field_aa_object_string"
1939 "`ovm_field_aa_string_int"
1940 "`ovm_field_aa_string_string"
1941 "`ovm_field_array_int"
1942 "`ovm_field_array_object"
1943 "`ovm_field_array_string"
1948 "`ovm_field_queue_int"
1949 "`ovm_field_queue_object"
1950 "`ovm_field_queue_string"
1951 "`ovm_field_sarray_int"
1956 "`ovm_get_peek_imp_decl"
1963 "`ovm_master_imp_decl"
1965 "`ovm_non_blocking_transport_imp_decl"
1966 "`ovm_nonblocking_get_imp_decl"
1967 "`ovm_nonblocking_get_peek_imp_decl"
1968 "`ovm_nonblocking_master_imp_decl"
1969 "`ovm_nonblocking_peek_imp_decl"
1970 "`ovm_nonblocking_put_imp_decl"
1971 "`ovm_nonblocking_slave_imp_decl"
1972 "`ovm_object_registry"
1973 "`ovm_object_registry_param"
1975 "`ovm_peek_imp_decl"
1976 "`ovm_phase_func_decl"
1977 "`ovm_phase_task_decl"
1978 "`ovm_print_aa_int_object"
1979 "`ovm_print_aa_string_int"
1980 "`ovm_print_aa_string_object"
1981 "`ovm_print_aa_string_string"
1982 "`ovm_print_array_int"
1983 "`ovm_print_array_object"
1984 "`ovm_print_array_string"
1985 "`ovm_print_object_queue"
1986 "`ovm_print_queue_int"
1987 "`ovm_print_string_queue"
1990 "`ovm_rand_send_with"
1992 "`ovm_sequence_utils"
1993 "`ovm_slave_imp_decl"
1994 "`ovm_transport_imp_decl"
1995 "`ovm_update_sequence_lib"
1996 "`ovm_update_sequence_lib_and_item"
1999 "`static_message") nil )))
2001 (defconst verilog-uvm-statement-re
2006 "`uvm_analysis_imp_decl"
2007 "`uvm_blocking_get_imp_decl"
2008 "`uvm_blocking_get_peek_imp_decl"
2009 "`uvm_blocking_master_imp_decl"
2010 "`uvm_blocking_peek_imp_decl"
2011 "`uvm_blocking_put_imp_decl"
2012 "`uvm_blocking_slave_imp_decl"
2013 "`uvm_blocking_transport_imp_decl"
2014 "`uvm_component_param_utils"
2015 "`uvm_component_registry"
2016 "`uvm_component_registry_param"
2017 "`uvm_component_utils"
2020 "`uvm_create_seq" ;; Undocumented in 1.1
2021 "`uvm_declare_p_sequencer"
2022 "`uvm_declare_sequence_lib" ;; Deprecated in 1.1
2025 "`uvm_do_callbacks_exit_on"
2026 "`uvm_do_obj_callbacks"
2027 "`uvm_do_obj_callbacks_exit_on"
2030 "`uvm_do_on_pri_with"
2034 "`uvm_do_seq" ;; Undocumented in 1.1
2035 "`uvm_do_seq_with" ;; Undocumented in 1.1
2038 "`uvm_error_context"
2040 "`uvm_fatal_context"
2041 "`uvm_field_aa_int_byte"
2042 "`uvm_field_aa_int_byte_unsigned"
2043 "`uvm_field_aa_int_enum"
2044 "`uvm_field_aa_int_int"
2045 "`uvm_field_aa_int_int_unsigned"
2046 "`uvm_field_aa_int_integer"
2047 "`uvm_field_aa_int_integer_unsigned"
2048 "`uvm_field_aa_int_key"
2049 "`uvm_field_aa_int_longint"
2050 "`uvm_field_aa_int_longint_unsigned"
2051 "`uvm_field_aa_int_shortint"
2052 "`uvm_field_aa_int_shortint_unsigned"
2053 "`uvm_field_aa_int_string"
2054 "`uvm_field_aa_object_int"
2055 "`uvm_field_aa_object_string"
2056 "`uvm_field_aa_string_int"
2057 "`uvm_field_aa_string_string"
2058 "`uvm_field_array_enum"
2059 "`uvm_field_array_int"
2060 "`uvm_field_array_object"
2061 "`uvm_field_array_string"
2066 "`uvm_field_queue_enum"
2067 "`uvm_field_queue_int"
2068 "`uvm_field_queue_object"
2069 "`uvm_field_queue_string"
2071 "`uvm_field_sarray_enum"
2072 "`uvm_field_sarray_int"
2073 "`uvm_field_sarray_object"
2074 "`uvm_field_sarray_string"
2077 "`uvm_file" ;; Undocumented in 1.1, use `__FILE__
2079 "`uvm_get_peek_imp_decl"
2082 "`uvm_line" ;; Undocumented in 1.1, use `__LINE__
2083 "`uvm_master_imp_decl"
2084 "`uvm_non_blocking_transport_imp_decl" ;; Deprecated in 1.1
2085 "`uvm_nonblocking_get_imp_decl"
2086 "`uvm_nonblocking_get_peek_imp_decl"
2087 "`uvm_nonblocking_master_imp_decl"
2088 "`uvm_nonblocking_peek_imp_decl"
2089 "`uvm_nonblocking_put_imp_decl"
2090 "`uvm_nonblocking_slave_imp_decl"
2091 "`uvm_nonblocking_transport_imp_decl"
2092 "`uvm_object_param_utils"
2093 "`uvm_object_registry"
2094 "`uvm_object_registry_param" ;; Undocumented in 1.1
2108 "`uvm_peek_imp_decl"
2111 "`uvm_rand_send_pri"
2112 "`uvm_rand_send_pri_with"
2113 "`uvm_rand_send_with"
2114 "`uvm_record_attribute"
2119 "`uvm_sequence_utils" ;; Deprecated in 1.1
2120 "`uvm_set_super_type"
2121 "`uvm_slave_imp_decl"
2122 "`uvm_transport_imp_decl"
2124 "`uvm_unpack_arrayN"
2130 "`uvm_unpack_queueN"
2132 "`uvm_unpack_sarray"
2133 "`uvm_unpack_sarrayN"
2134 "`uvm_unpack_string"
2135 "`uvm_update_sequence_lib" ;; Deprecated in 1.1
2136 "`uvm_update_sequence_lib_and_item" ;; Deprecated in 1.1
2138 "`uvm_warning_context") nil )))
2142 ;; Regular expressions used to calculate indent, etc.
2144 (defconst verilog-symbol-re "\\<[a-zA-Z_][a-zA-Z_0-9.]*\\>")
2151 (defconst verilog-assignment-operator-re
2155 ;; blocking assignment_operator
2156 "=" "+=" "-=" "*=" "/=" "%=" "&=" "|=" "^=" "<<=" ">>=" "<<<=" ">>>="
2157 ;; non blocking assignment operator
2160 "==" "!=" "===" "!===" "<=" ">=" "==\?" "!=\?"
2165 ;; Is this a legal verilog operator?
2169 (defconst verilog-assignment-operation-re
2171 ; "\\(^\\s-*[A-Za-z0-9_]+\\(\\[\\([A-Za-z0-9_]+\\)\\]\\)*\\s-*\\)"
2172 ; "\\(^\\s-*[^=<>+-*/%&|^:\\s-]+[^=<>+-*/%&|^\n]*?\\)"
2173 "\\(^.*?\\)" "\\B" verilog-assignment-operator-re "\\B" ))
2175 (defconst verilog-label-re (concat verilog-symbol-re "\\s-*:\\s-*"))
2176 (defconst verilog-property-re
2177 (concat "\\(" verilog-label-re "\\)?"
2178 "\\(\\(assert\\|assume\\|cover\\)\\>\\s-+\\<property\\>\\)\\|\\(assert\\)"))
2179 ;; "\\(assert\\|assume\\|cover\\)\\s-+property\\>"
2181 (defconst verilog-no-indent-begin-re
2182 "\\<\\(if\\|else\\|while\\|for\\|repeat\\|always\\|always_comb\\|always_ff\\|always_latch\\)\\>")
2184 (defconst verilog-ends-re
2185 ;; Parenthesis indicate type of keyword found
2187 "\\(\\<else\\>\\)\\|" ; 1
2188 "\\(\\<if\\>\\)\\|" ; 2
2189 "\\(\\<assert\\>\\)\\|" ; 3
2190 "\\(\\<end\\>\\)\\|" ; 3.1
2191 "\\(\\<endcase\\>\\)\\|" ; 4
2192 "\\(\\<endfunction\\>\\)\\|" ; 5
2193 "\\(\\<endtask\\>\\)\\|" ; 6
2194 "\\(\\<endspecify\\>\\)\\|" ; 7
2195 "\\(\\<endtable\\>\\)\\|" ; 8
2196 "\\(\\<endgenerate\\>\\)\\|" ; 9
2197 "\\(\\<join\\(_any\\|_none\\)?\\>\\)\\|" ; 10
2198 "\\(\\<endclass\\>\\)\\|" ; 11
2199 "\\(\\<endgroup\\>\\)\\|" ; 12
2201 "\\(\\<`vmm_data_member_end\\>\\)\\|"
2202 "\\(\\<`vmm_env_member_end\\>\\)\\|"
2203 "\\(\\<`vmm_scenario_member_end\\>\\)\\|"
2204 "\\(\\<`vmm_subenv_member_end\\>\\)\\|"
2205 "\\(\\<`vmm_xactor_member_end\\>\\)\\|"
2207 "\\(\\<`ovm_component_utils_end\\>\\)\\|"
2208 "\\(\\<`ovm_field_utils_end\\>\\)\\|"
2209 "\\(\\<`ovm_object_utils_end\\>\\)\\|"
2210 "\\(\\<`ovm_sequence_utils_end\\>\\)\\|"
2211 "\\(\\<`ovm_sequencer_utils_end\\>\\)"
2213 "\\(\\<`uvm_component_utils_end\\>\\)\\|"
2214 "\\(\\<`uvm_field_utils_end\\>\\)\\|"
2215 "\\(\\<`uvm_object_utils_end\\>\\)\\|"
2216 "\\(\\<`uvm_sequence_utils_end\\>\\)\\|"
2217 "\\(\\<`uvm_sequencer_utils_end\\>\\)"
2220 (defconst verilog-auto-end-comment-lines-re
2221 ;; Matches to names in this list cause auto-end-commenting
2223 verilog-directive-re "\\)\\|\\("
2225 (verilog-regexp-words
2253 ;;; NOTE: verilog-leap-to-head expects that verilog-end-block-re and
2254 ;;; verilog-end-block-ordered-re matches exactly the same strings.
2255 (defconst verilog-end-block-ordered-re
2256 ;; Parenthesis indicate type of keyword found
2257 (concat "\\(\\<endcase\\>\\)\\|" ; 1
2258 "\\(\\<end\\>\\)\\|" ; 2
2259 "\\(\\<end" ; 3, but not used
2260 "\\(" ; 4, but not used
2261 "\\(function\\)\\|" ; 5
2263 "\\(module\\)\\|" ; 7
2264 "\\(primitive\\)\\|" ; 8
2265 "\\(interface\\)\\|" ; 9
2266 "\\(package\\)\\|" ; 10
2267 "\\(class\\)\\|" ; 11
2268 "\\(group\\)\\|" ; 12
2269 "\\(program\\)\\|" ; 13
2270 "\\(sequence\\)\\|" ; 14
2271 "\\(clocking\\)\\|" ; 15
2273 (defconst verilog-end-block-re
2275 (verilog-regexp-words
2277 `("end" ;; closes begin
2278 "endcase" ;; closes any of case, casex casez or randcase
2279 "join" "join_any" "join_none" ;; closes fork
2294 "`ovm_component_utils_end"
2295 "`ovm_field_utils_end"
2296 "`ovm_object_utils_end"
2297 "`ovm_sequence_utils_end"
2298 "`ovm_sequencer_utils_end"
2300 "`uvm_component_utils_end"
2301 "`uvm_field_utils_end"
2302 "`uvm_object_utils_end"
2303 "`uvm_sequence_utils_end"
2304 "`uvm_sequencer_utils_end"
2306 "`vmm_data_member_end"
2307 "`vmm_env_member_end"
2308 "`vmm_scenario_member_end"
2309 "`vmm_subenv_member_end"
2310 "`vmm_xactor_member_end"
2314 (defconst verilog-endcomment-reason-re
2315 ;; Parenthesis indicate type of keyword found
2317 "\\(\\<begin\\>\\)\\|" ; 1
2318 "\\(\\<else\\>\\)\\|" ; 2
2319 "\\(\\<end\\>\\s-+\\<else\\>\\)\\|" ; 3
2320 "\\(\\<always_comb\\>\\(\[ \t\]*@\\)?\\)\\|" ; 4
2321 "\\(\\<always_ff\\>\\(\[ \t\]*@\\)?\\)\\|" ; 5
2322 "\\(\\<always_latch\\>\\(\[ \t\]*@\\)?\\)\\|" ; 6
2323 "\\(\\<fork\\>\\)\\|" ; 7
2324 "\\(\\<always\\>\\(\[ \t\]*@\\)?\\)\\|"
2326 verilog-property-re "\\|"
2327 "\\(\\(" verilog-label-re "\\)?\\<assert\\>\\)\\|"
2328 "\\(\\<clocking\\>\\)\\|"
2329 "\\(\\<task\\>\\)\\|"
2330 "\\(\\<function\\>\\)\\|"
2331 "\\(\\<initial\\>\\)\\|"
2332 "\\(\\<interface\\>\\)\\|"
2333 "\\(\\<package\\>\\)\\|"
2334 "\\(\\<final\\>\\)\\|"
2336 "\\(\\<while\\>\\)\\|"
2337 "\\(\\<for\\(ever\\|each\\)?\\>\\)\\|"
2338 "\\(\\<repeat\\>\\)\\|\\(\\<wait\\>\\)\\|"
2341 (defconst verilog-named-block-re "begin[ \t]*:")
2343 ;; These words begin a block which can occur inside a module which should be indented,
2344 ;; and closed with the respective word from the end-block list
2346 (defconst verilog-beg-block-re
2348 (verilog-regexp-words
2350 "case" "casex" "casez" "randcase"
2360 "`ovm_component_utils_begin"
2361 "`ovm_component_param_utils_begin"
2362 "`ovm_field_utils_begin"
2363 "`ovm_object_utils_begin"
2364 "`ovm_object_param_utils_begin"
2365 "`ovm_sequence_utils_begin"
2366 "`ovm_sequencer_utils_begin"
2368 "`uvm_component_utils_begin"
2369 "`uvm_component_param_utils_begin"
2370 "`uvm_field_utils_begin"
2371 "`uvm_object_utils_begin"
2372 "`uvm_object_param_utils_begin"
2373 "`uvm_sequence_utils_begin"
2374 "`uvm_sequencer_utils_begin"
2376 "`vmm_data_member_begin"
2377 "`vmm_env_member_begin"
2378 "`vmm_scenario_member_begin"
2379 "`vmm_subenv_member_begin"
2380 "`vmm_xactor_member_begin"
2382 ;; These are the same words, in a specific order in the regular
2383 ;; expression so that matching will work nicely for
2384 ;; verilog-forward-sexp and verilog-calc-indent
2385 (defconst verilog-beg-block-re-ordered
2386 ( concat "\\(\\<begin\\>\\)" ;1
2387 "\\|\\(\\<randcase\\>\\|\\(\\<unique\\s-+\\|priority\\s-+\\)?case[xz]?\\>\\)" ; 2,3
2388 "\\|\\(\\(\\<disable\\>\\s-+\\|\\<wait\\>\\s-+\\)?fork\\>\\)" ;4,5
2389 "\\|\\(\\<class\\>\\)" ;6
2390 "\\|\\(\\<table\\>\\)" ;7
2391 "\\|\\(\\<specify\\>\\)" ;8
2392 "\\|\\(\\<function\\>\\)" ;9
2393 "\\|\\(\\(\\(\\<virtual\\>\\s-+\\)\\|\\(\\<protected\\>\\s-+\\)\\)*\\<function\\>\\)" ;10
2394 "\\|\\(\\<task\\>\\)" ;14
2395 "\\|\\(\\(\\(\\<virtual\\>\\s-+\\)\\|\\(\\<protected\\>\\s-+\\)\\)*\\<task\\>\\)" ;15
2396 "\\|\\(\\<generate\\>\\)" ;18
2397 "\\|\\(\\<covergroup\\>\\)" ;16 20
2398 "\\|\\(\\(\\(\\<cover\\>\\s-+\\)\\|\\(\\<assert\\>\\s-+\\)\\)*\\<property\\>\\)" ;17 21
2399 "\\|\\(\\<\\(rand\\)?sequence\\>\\)" ;21 25
2400 "\\|\\(\\<clocking\\>\\)" ;22 27
2401 "\\|\\(\\<`[ou]vm_[a-z_]+_begin\\>\\)" ;28
2402 "\\|\\(\\<`vmm_[a-z_]+_member_begin\\>\\)"
2407 (defconst verilog-end-block-ordered-rry
2408 [ "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<endcase\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)"
2409 "\\(\\<randcase\\>\\|\\<case[xz]?\\>\\)\\|\\(\\<endcase\\>\\)"
2410 "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)"
2411 "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)"
2412 "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)"
2413 "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)"
2414 "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)"
2415 "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)"
2416 "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)"
2417 "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)"
2418 "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)"
2419 "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)"
2420 "\\(\\<clocking\\>\\)\\|\\(\\<endclocking\\>\\)"
2423 (defconst verilog-nameable-item-re
2425 (verilog-regexp-words
2428 "join" "join_any" "join_none"
2445 (defconst verilog-declaration-opener
2447 (verilog-regexp-words
2448 `("module" "begin" "task" "function"))))
2450 (defconst verilog-declaration-prefix-re
2452 (verilog-regexp-words
2455 "inout" "input" "output" "ref"
2457 "const" "static" "protected" "local"
2459 "localparam" "parameter" "var"
2463 (defconst verilog-declaration-core-re
2465 (verilog-regexp-words
2467 ;; port direction (by themselves)
2468 "inout" "input" "output"
2469 ;; integer_atom_type
2470 "byte" "shortint" "int" "longint" "integer" "time"
2471 ;; integer_vector_type
2474 "shortreal" "real" "realtime"
2476 "supply0" "supply1" "tri" "triand" "trior" "trireg" "tri0" "tri1" "uwire" "wire" "wand" "wor"
2478 "string" "event" "chandle" "virtual" "enum" "genvar"
2481 "mailbox" "semaphore"
2483 (defconst verilog-declaration-re
2484 (concat "\\(" verilog-declaration-prefix-re "\\s-*\\)?" verilog-declaration-core-re))
2485 (defconst verilog-range-re "\\(\\[[^]]*\\]\\s-*\\)+")
2486 (defconst verilog-optional-signed-re "\\s-*\\(signed\\)?")
2487 (defconst verilog-optional-signed-range-re
2489 "\\s-*\\(\\<\\(reg\\|wire\\)\\>\\s-*\\)?\\(\\<signed\\>\\s-*\\)?\\(" verilog-range-re "\\)?"))
2490 (defconst verilog-macroexp-re "`\\sw+")
2492 (defconst verilog-delay-re "#\\s-*\\(\\([0-9_]+\\('s?[hdxbo][0-9a-fA-F_xz]+\\)?\\)\\|\\(([^()]*)\\)\\|\\(\\sw+\\)\\)")
2493 (defconst verilog-declaration-re-2-no-macro
2494 (concat "\\s-*" verilog-declaration-re
2495 "\\s-*\\(\\(" verilog-optional-signed-range-re "\\)\\|\\(" verilog-delay-re "\\)"
2497 (defconst verilog-declaration-re-2-macro
2498 (concat "\\s-*" verilog-declaration-re
2499 "\\s-*\\(\\(" verilog-optional-signed-range-re "\\)\\|\\(" verilog-delay-re "\\)"
2500 "\\|\\(" verilog-macroexp-re "\\)"
2502 (defconst verilog-declaration-re-1-macro
2503 (concat "^" verilog-declaration-re-2-macro))
2505 (defconst verilog-declaration-re-1-no-macro (concat "^" verilog-declaration-re-2-no-macro))
2507 (defconst verilog-defun-re
2508 (eval-when-compile (verilog-regexp-words `("macromodule" "module" "class" "program" "interface" "package" "primitive" "config"))))
2509 (defconst verilog-end-defun-re
2510 (eval-when-compile (verilog-regexp-words `("endmodule" "endclass" "endprogram" "endinterface" "endpackage" "endprimitive" "endconfig"))))
2511 (defconst verilog-zero-indent-re
2512 (concat verilog-defun-re "\\|" verilog-end-defun-re))
2513 (defconst verilog-inst-comment-re
2514 (eval-when-compile (verilog-regexp-words `("Outputs" "Inouts" "Inputs" "Interfaces" "Interfaced"))))
2516 (defconst verilog-behavioral-block-beg-re
2517 (eval-when-compile (verilog-regexp-words `("initial" "final" "always" "always_comb" "always_latch" "always_ff"
2518 "function" "task"))))
2519 (defconst verilog-coverpoint-re "\\w+\\s*:\\s*\\(coverpoint\\|cross\\constraint\\)" )
2520 (defconst verilog-indent-re
2522 (verilog-regexp-words
2525 "always" "always_latch" "always_ff" "always_comb"
2527 ; "unique" "priority"
2528 "case" "casex" "casez" "randcase" "endcase"
2530 "clocking" "endclocking"
2531 "config" "endconfig"
2532 "covergroup" "endgroup"
2533 "fork" "join" "join_any" "join_none"
2534 "function" "endfunction"
2536 "generate" "endgenerate"
2538 "interface" "endinterface"
2539 "module" "macromodule" "endmodule"
2540 "package" "endpackage"
2541 "primitive" "endprimitive"
2542 "program" "endprogram"
2543 "property" "endproperty"
2544 "sequence" "randsequence" "endsequence"
2545 "specify" "endspecify"
2552 "`if" "`ifdef" "`ifndef" "`else" "`elsif" "`endif"
2553 "`while" "`endwhile"
2558 "`protect" "`endprotect"
2559 "`switch" "`endswitch"
2563 "`ovm_component_utils_begin"
2564 "`ovm_component_param_utils_begin"
2565 "`ovm_field_utils_begin"
2566 "`ovm_object_utils_begin"
2567 "`ovm_object_param_utils_begin"
2568 "`ovm_sequence_utils_begin"
2569 "`ovm_sequencer_utils_begin"
2571 "`ovm_component_utils_end"
2572 "`ovm_field_utils_end"
2573 "`ovm_object_utils_end"
2574 "`ovm_sequence_utils_end"
2575 "`ovm_sequencer_utils_end"
2577 "`uvm_component_utils_begin"
2578 "`uvm_component_param_utils_begin"
2579 "`uvm_field_utils_begin"
2580 "`uvm_object_utils_begin"
2581 "`uvm_object_param_utils_begin"
2582 "`uvm_sequence_utils_begin"
2583 "`uvm_sequencer_utils_begin"
2585 "`uvm_component_utils_end" ;; Typo in spec, it's not uvm_component_end
2586 "`uvm_field_utils_end"
2587 "`uvm_object_utils_end"
2588 "`uvm_sequence_utils_end"
2589 "`uvm_sequencer_utils_end"
2591 "`vmm_data_member_begin"
2592 "`vmm_env_member_begin"
2593 "`vmm_scenario_member_begin"
2594 "`vmm_subenv_member_begin"
2595 "`vmm_xactor_member_begin"
2597 "`vmm_data_member_end"
2598 "`vmm_env_member_end"
2599 "`vmm_scenario_member_end"
2600 "`vmm_subenv_member_end"
2601 "`vmm_xactor_member_end"
2604 (defconst verilog-defun-level-not-generate-re
2606 (verilog-regexp-words
2607 `( "module" "macromodule" "primitive" "class" "program"
2608 "interface" "package" "config"))))
2610 (defconst verilog-defun-level-re
2612 (verilog-regexp-words
2614 `( "module" "macromodule" "primitive" "class" "program"
2615 "interface" "package" "config")
2616 `( "initial" "final" "always" "always_comb" "always_ff"
2617 "always_latch" "endtask" "endfunction" )))))
2619 (defconst verilog-defun-level-generate-only-re
2621 (verilog-regexp-words
2622 `( "initial" "final" "always" "always_comb" "always_ff"
2623 "always_latch" "endtask" "endfunction" ))))
2625 (defconst verilog-cpp-level-re
2627 (verilog-regexp-words
2629 "endmodule" "endprimitive" "endinterface" "endpackage" "endprogram" "endclass"
2631 (defconst verilog-disable-fork-re "\\(disable\\|wait\\)\\s-+fork\\>")
2632 (defconst verilog-extended-case-re "\\(unique\\s-+\\|priority\\s-+\\)?case[xz]?")
2633 (defconst verilog-extended-complete-re
2634 (concat "\\(\\<extern\\s-+\\|\\<\\(\\<pure\\>\\s-+\\)?virtual\\s-+\\|\\<protected\\s-+\\)*\\(\\<function\\>\\|\\<task\\>\\)"
2635 "\\|\\(\\<typedef\\>\\s-+\\)*\\(\\<struct\\>\\|\\<union\\>\\|\\<class\\>\\)"
2636 "\\|\\(\\<import\\>\\s-+\\)?\"DPI-C\"\\s-+\\(function\\>\\|task\\>\\)"
2637 "\\|" verilog-extended-case-re ))
2638 (defconst verilog-basic-complete-re
2640 (verilog-regexp-words
2642 "always" "assign" "always_latch" "always_ff" "always_comb" "constraint"
2643 "import" "initial" "final" "module" "macromodule" "repeat" "randcase" "while"
2644 "if" "for" "forever" "foreach" "else" "parameter" "do" "localparam" "assert"
2646 (defconst verilog-complete-reg
2648 verilog-extended-complete-re
2650 verilog-basic-complete-re))
2652 (defconst verilog-end-statement-re
2653 (concat "\\(" verilog-beg-block-re "\\)\\|\\("
2654 verilog-end-block-re "\\)"))
2656 (defconst verilog-endcase-re
2657 (concat verilog-extended-case-re "\\|"
2662 (defconst verilog-exclude-str-start "/* -----\\/----- EXCLUDED -----\\/-----"
2663 "String used to mark beginning of excluded text.")
2664 (defconst verilog-exclude-str-end " -----/\\----- EXCLUDED -----/\\----- */"
2665 "String used to mark end of excluded text.")
2666 (defconst verilog-preprocessor-re
2668 (verilog-regexp-words
2670 "`define" "`include" "`ifdef" "`ifndef" "`if" "`endif" "`else"
2673 (defconst verilog-keywords
2674 '( "`case" "`default" "`define" "`else" "`endfor" "`endif"
2675 "`endprotect" "`endswitch" "`endwhile" "`for" "`format" "`if" "`ifdef"
2676 "`ifndef" "`include" "`let" "`protect" "`switch" "`timescale"
2677 "`time_scale" "`undef" "`while"
2679 "after" "alias" "always" "always_comb" "always_ff" "always_latch" "and"
2680 "assert" "assign" "assume" "automatic" "before" "begin" "bind"
2681 "bins" "binsof" "bit" "break" "buf" "bufif0" "bufif1" "byte"
2682 "case" "casex" "casez" "cell" "chandle" "class" "clocking" "cmos"
2683 "config" "const" "constraint" "context" "continue" "cover"
2684 "covergroup" "coverpoint" "cross" "deassign" "default" "defparam"
2685 "design" "disable" "dist" "do" "edge" "else" "end" "endcase"
2686 "endclass" "endclocking" "endconfig" "endfunction" "endgenerate"
2687 "endgroup" "endinterface" "endmodule" "endpackage" "endprimitive"
2688 "endprogram" "endproperty" "endspecify" "endsequence" "endtable"
2689 "endtask" "enum" "event" "expect" "export" "extends" "extern"
2690 "final" "first_match" "for" "force" "foreach" "forever" "fork"
2691 "forkjoin" "function" "generate" "genvar" "highz0" "highz1" "if"
2692 "iff" "ifnone" "ignore_bins" "illegal_bins" "import" "incdir"
2693 "include" "initial" "inout" "input" "inside" "instance" "int"
2694 "integer" "interface" "intersect" "join" "join_any" "join_none"
2695 "large" "liblist" "library" "local" "localparam" "logic"
2696 "longint" "macromodule" "mailbox" "matches" "medium" "modport" "module"
2697 "nand" "negedge" "new" "nmos" "nor" "noshowcancelled" "not"
2698 "notif0" "notif1" "null" "or" "output" "package" "packed"
2699 "parameter" "pmos" "posedge" "primitive" "priority" "program"
2700 "property" "protected" "pull0" "pull1" "pulldown" "pullup"
2701 "pulsestyle_onevent" "pulsestyle_ondetect" "pure" "rand" "randc"
2702 "randcase" "randsequence" "rcmos" "real" "realtime" "ref" "reg"
2703 "release" "repeat" "return" "rnmos" "rpmos" "rtran" "rtranif0"
2704 "rtranif1" "scalared" "semaphore" "sequence" "shortint" "shortreal"
2705 "showcancelled" "signed" "small" "solve" "specify" "specparam"
2706 "static" "string" "strong0" "strong1" "struct" "super" "supply0"
2707 "supply1" "table" "tagged" "task" "this" "throughout" "time"
2708 "timeprecision" "timeunit" "tran" "tranif0" "tranif1" "tri"
2709 "tri0" "tri1" "triand" "trior" "trireg" "type" "typedef" "union"
2710 "unique" "unsigned" "use" "uwire" "var" "vectored" "virtual" "void"
2711 "wait" "wait_order" "wand" "weak0" "weak1" "while" "wildcard"
2712 "wire" "with" "within" "wor" "xnor" "xor"
2714 "accept_on" "checker" "endchecker" "eventually" "global" "implies"
2715 "let" "nexttime" "reject_on" "restrict" "s_always" "s_eventually"
2716 "s_nexttime" "s_until" "s_until_with" "strong" "sync_accept_on"
2717 "sync_reject_on" "unique0" "until" "until_with" "untyped" "weak"
2719 "List of Verilog keywords.")
2721 (defconst verilog-comment-start-regexp "//\\|/\\*"
2722 "Dual comment value for `comment-start-regexp'.")
2724 (defvar verilog-mode-syntax-table
2725 (let ((table (make-syntax-table)))
2726 ;; Populate the syntax TABLE.
2727 (modify-syntax-entry ?\\ "\\" table)
2728 (modify-syntax-entry ?+ "." table)
2729 (modify-syntax-entry ?- "." table)
2730 (modify-syntax-entry ?= "." table)
2731 (modify-syntax-entry ?% "." table)
2732 (modify-syntax-entry ?< "." table)
2733 (modify-syntax-entry ?> "." table)
2734 (modify-syntax-entry ?& "." table)
2735 (modify-syntax-entry ?| "." table)
2736 (modify-syntax-entry ?` "w" table)
2737 (modify-syntax-entry ?_ "w" table)
2738 (modify-syntax-entry ?\' "." table)
2740 ;; Set up TABLE to handle block and line style comments.
2741 (if (featurep 'xemacs)
2743 ;; XEmacs (formerly Lucid) has the best implementation
2744 (modify-syntax-entry ?/ ". 1456" table)
2745 (modify-syntax-entry ?* ". 23" table)
2746 (modify-syntax-entry ?\n "> b" table))
2747 ;; Emacs does things differently, but we can work with it
2748 (modify-syntax-entry ?/ ". 124b" table)
2749 (modify-syntax-entry ?* ". 23" table)
2750 (modify-syntax-entry ?\n "> b" table))
2752 "Syntax table used in Verilog mode buffers.")
2754 (defvar verilog-font-lock-keywords nil
2755 "Default highlighting for Verilog mode.")
2757 (defvar verilog-font-lock-keywords-1 nil
2758 "Subdued level highlighting for Verilog mode.")
2760 (defvar verilog-font-lock-keywords-2 nil
2761 "Medium level highlighting for Verilog mode.
2762 See also `verilog-font-lock-extra-types'.")
2764 (defvar verilog-font-lock-keywords-3 nil
2765 "Gaudy level highlighting for Verilog mode.
2766 See also `verilog-font-lock-extra-types'.")
2767 (defvar verilog-font-lock-translate-off-face
2768 'verilog-font-lock-translate-off-face
2769 "Font to use for translated off regions.")
2770 (defface verilog-font-lock-translate-off-face
2773 (:background "gray90" :italic t ))
2776 (:background "gray10" :italic t ))
2777 (((class grayscale) (background light))
2778 (:foreground "DimGray" :italic t))
2779 (((class grayscale) (background dark))
2780 (:foreground "LightGray" :italic t))
2782 "Font lock mode face used to background highlight translate-off regions."
2783 :group 'font-lock-highlighting-faces)
2785 (defvar verilog-font-lock-p1800-face
2786 'verilog-font-lock-p1800-face
2787 "Font to use for p1800 keywords.")
2788 (defface verilog-font-lock-p1800-face
2791 (:foreground "DarkOrange3" :bold t ))
2794 (:foreground "orange1" :bold t ))
2796 "Font lock mode face used to highlight P1800 keywords."
2797 :group 'font-lock-highlighting-faces)
2799 (defvar verilog-font-lock-ams-face
2800 'verilog-font-lock-ams-face
2801 "Font to use for Analog/Mixed Signal keywords.")
2802 (defface verilog-font-lock-ams-face
2805 (:foreground "Purple" :bold t ))
2808 (:foreground "orange1" :bold t ))
2810 "Font lock mode face used to highlight AMS keywords."
2811 :group 'font-lock-highlighting-faces)
2813 (defvar verilog-font-grouping-keywords-face
2814 'verilog-font-lock-grouping-keywords-face
2815 "Font to use for Verilog Grouping Keywords (such as begin..end).")
2816 (defface verilog-font-lock-grouping-keywords-face
2819 (:foreground "red4" :bold t ))
2822 (:foreground "red4" :bold t ))
2824 "Font lock mode face used to highlight verilog grouping keywords."
2825 :group 'font-lock-highlighting-faces)
2827 (let* ((verilog-type-font-keywords
2831 "and" "bit" "buf" "bufif0" "bufif1" "cmos" "defparam"
2832 "event" "genvar" "inout" "input" "integer" "localparam"
2833 "logic" "mailbox" "nand" "nmos" "not" "notif0" "notif1" "or"
2834 "output" "parameter" "pmos" "pull0" "pull1" "pulldown" "pullup"
2835 "rcmos" "real" "realtime" "reg" "rnmos" "rpmos" "rtran"
2836 "rtranif0" "rtranif1" "semaphore" "signed" "struct" "supply"
2837 "supply0" "supply1" "time" "tran" "tranif0" "tranif1"
2838 "tri" "tri0" "tri1" "triand" "trior" "trireg" "typedef"
2839 "uwire" "vectored" "wand" "wire" "wor" "xnor" "xor"
2842 (verilog-pragma-keywords
2845 '("surefire" "synopsys" "rtl_synthesis" "verilint" "leda" "0in") nil
2848 (verilog-1800-2005-keywords
2851 '("alias" "assert" "assume" "automatic" "before" "bind"
2852 "bins" "binsof" "break" "byte" "cell" "chandle" "class"
2853 "clocking" "config" "const" "constraint" "context" "continue"
2854 "cover" "covergroup" "coverpoint" "cross" "deassign" "design"
2855 "dist" "do" "edge" "endclass" "endclocking" "endconfig"
2856 "endgroup" "endprogram" "endproperty" "endsequence" "enum"
2857 "expect" "export" "extends" "extern" "first_match" "foreach"
2858 "forkjoin" "genvar" "highz0" "highz1" "ifnone" "ignore_bins"
2859 "illegal_bins" "import" "incdir" "include" "inside" "instance"
2860 "int" "intersect" "large" "liblist" "library" "local" "longint"
2861 "matches" "medium" "modport" "new" "noshowcancelled" "null"
2862 "packed" "program" "property" "protected" "pull0" "pull1"
2863 "pulsestyle_onevent" "pulsestyle_ondetect" "pure" "rand" "randc"
2864 "randcase" "randsequence" "ref" "release" "return" "scalared"
2865 "sequence" "shortint" "shortreal" "showcancelled" "small" "solve"
2866 "specparam" "static" "string" "strong0" "strong1" "struct"
2867 "super" "tagged" "this" "throughout" "timeprecision" "timeunit"
2868 "type" "union" "unsigned" "use" "var" "virtual" "void"
2869 "wait_order" "weak0" "weak1" "wildcard" "with" "within"
2872 (verilog-1800-2009-keywords
2875 '("accept_on" "checker" "endchecker" "eventually" "global"
2876 "implies" "let" "nexttime" "reject_on" "restrict" "s_always"
2877 "s_eventually" "s_nexttime" "s_until" "s_until_with" "strong"
2878 "sync_accept_on" "sync_reject_on" "unique0" "until"
2879 "until_with" "untyped" "weak" ) nil )))
2881 (verilog-ams-keywords
2884 '("above" "abs" "absdelay" "acos" "acosh" "ac_stim"
2885 "aliasparam" "analog" "analysis" "asin" "asinh" "atan" "atan2" "atanh"
2886 "branch" "ceil" "connectmodule" "connectrules" "cos" "cosh" "ddt"
2887 "ddx" "discipline" "driver_update" "enddiscipline" "endconnectrules"
2888 "endnature" "endparamset" "exclude" "exp" "final_step" "flicker_noise"
2889 "floor" "flow" "from" "ground" "hypot" "idt" "idtmod" "inf"
2890 "initial_step" "laplace_nd" "laplace_np" "laplace_zd" "laplace_zp"
2891 "last_crossing" "limexp" "ln" "log" "max" "min" "nature"
2892 "net_resolution" "noise_table" "paramset" "potential" "pow" "sin"
2893 "sinh" "slew" "sqrt" "tan" "tanh" "timer" "transition" "white_noise"
2894 "wreal" "zi_nd" "zi_np" "zi_zd" ) nil )))
2896 (verilog-font-keywords
2900 "assign" "case" "casex" "casez" "randcase" "deassign"
2901 "default" "disable" "else" "endcase" "endfunction"
2902 "endgenerate" "endinterface" "endmodule" "endprimitive"
2903 "endspecify" "endtable" "endtask" "final" "for" "force" "return" "break"
2904 "continue" "forever" "fork" "function" "generate" "if" "iff" "initial"
2905 "interface" "join" "join_any" "join_none" "macromodule" "module" "negedge"
2906 "package" "endpackage" "always" "always_comb" "always_ff"
2907 "always_latch" "posedge" "primitive" "priority" "release"
2908 "repeat" "specify" "table" "task" "unique" "wait" "while"
2909 "class" "program" "endclass" "endprogram"
2912 (verilog-font-grouping-keywords
2915 '( "begin" "end" ) nil ))))
2917 (setq verilog-font-lock-keywords
2919 ;; Fontify all builtin keywords
2920 (concat "\\<\\(" verilog-font-keywords "\\|"
2921 ;; And user/system tasks and functions
2922 "\\$[a-zA-Z][a-zA-Z0-9_\\$]*"
2924 ;; Fontify all types
2925 (if verilog-highlight-grouping-keywords
2926 (cons (concat "\\<\\(" verilog-font-grouping-keywords "\\)\\>")
2927 'verilog-font-lock-ams-face)
2928 (cons (concat "\\<\\(" verilog-font-grouping-keywords "\\)\\>")
2929 'font-lock-type-face))
2930 (cons (concat "\\<\\(" verilog-type-font-keywords "\\)\\>")
2931 'font-lock-type-face)
2932 ;; Fontify IEEE-1800-2005 keywords appropriately
2933 (if verilog-highlight-p1800-keywords
2934 (cons (concat "\\<\\(" verilog-1800-2005-keywords "\\)\\>")
2935 'verilog-font-lock-p1800-face)
2936 (cons (concat "\\<\\(" verilog-1800-2005-keywords "\\)\\>")
2937 'font-lock-type-face))
2938 ;; Fontify IEEE-1800-2009 keywords appropriately
2939 (if verilog-highlight-p1800-keywords
2940 (cons (concat "\\<\\(" verilog-1800-2009-keywords "\\)\\>")
2941 'verilog-font-lock-p1800-face)
2942 (cons (concat "\\<\\(" verilog-1800-2009-keywords "\\)\\>")
2943 'font-lock-type-face))
2944 ;; Fontify Verilog-AMS keywords
2945 (cons (concat "\\<\\(" verilog-ams-keywords "\\)\\>")
2946 'verilog-font-lock-ams-face)))
2948 (setq verilog-font-lock-keywords-1
2949 (append verilog-font-lock-keywords
2951 ;; Fontify module definitions
2953 "\\<\\(\\(macro\\)?module\\|primitive\\|class\\|program\\|interface\\|package\\|task\\)\\>\\s-*\\(\\sw+\\)"
2954 '(1 font-lock-keyword-face)
2955 '(3 font-lock-function-name-face 'prepend))
2956 ;; Fontify function definitions
2958 (concat "\\<function\\>\\s-+\\(integer\\|real\\(time\\)?\\|time\\)\\s-+\\(\\sw+\\)" )
2959 '(1 font-lock-keyword-face)
2960 '(3 font-lock-constant-face prepend))
2961 '("\\<function\\>\\s-+\\(\\[[^]]+\\]\\)\\s-+\\(\\sw+\\)"
2962 (1 font-lock-keyword-face)
2963 (2 font-lock-constant-face append))
2964 '("\\<function\\>\\s-+\\(\\sw+\\)"
2965 1 'font-lock-constant-face append))))
2967 (setq verilog-font-lock-keywords-2
2968 (append verilog-font-lock-keywords-1
2971 (concat "\\(//\\s-*" verilog-pragma-keywords "\\s-.*\\)")
2972 ;; Fontify escaped names
2973 '("\\(\\\\\\S-*\\s-\\)" 0 font-lock-function-name-face)
2974 ;; Fontify macro definitions/ uses
2975 '("`\\s-*[A-Za-z][A-Za-z0-9_]*" 0 (if (boundp 'font-lock-preprocessor-face)
2976 'font-lock-preprocessor-face
2977 'font-lock-type-face))
2978 ;; Fontify delays/numbers
2979 '("\\(@\\)\\|\\(#\\s-*\\(\\(\[0-9_.\]+\\('s?[hdxbo][0-9a-fA-F_xz]*\\)?\\)\\|\\(([^()]+)\\|\\sw+\\)\\)\\)"
2980 0 font-lock-type-face append)
2981 ;; Fontify instantiation names
2982 '("\\([A-Za-z][A-Za-z0-9_]*\\)\\s-*(" 1 font-lock-function-name-face)
2985 (setq verilog-font-lock-keywords-3
2986 (append verilog-font-lock-keywords-2
2987 (when verilog-highlight-translate-off
2989 ;; Fontify things in translate off regions
2990 '(verilog-match-translate-off
2991 (0 'verilog-font-lock-translate-off-face prepend))
2995 ;; Buffer state preservation
2997 (defmacro verilog-save-buffer-state (&rest body)
2998 "Execute BODY forms, saving state around insignificant change.
2999 Changes in text properties like `face' or `syntax-table' are
3000 considered insignificant. This macro allows text properties to
3001 be changed, even in a read-only buffer.
3003 A change is considered significant if it affects the buffer text
3004 in any way that isn't completely restored again. Any
3005 user-visible changes to the buffer must not be within a
3006 `verilog-save-buffer-state'."
3007 ;; From c-save-buffer-state
3008 `(let* ((modified (buffer-modified-p))
3009 (buffer-undo-list t)
3010 (inhibit-read-only t)
3011 (inhibit-point-motion-hooks t)
3012 (verilog-no-change-functions t)
3013 before-change-functions
3014 after-change-functions
3016 buffer-file-name ; Prevent primitives checking
3017 buffer-file-truename) ; for file modification
3022 (set-buffer-modified-p nil)))))
3024 (defmacro verilog-save-no-change-functions (&rest body)
3025 "Execute BODY forms, disabling all change hooks in BODY.
3026 For insignificant changes, see instead `verilog-save-buffer-state'."
3027 `(let* ((inhibit-point-motion-hooks t)
3028 (verilog-no-change-functions t)
3029 before-change-functions
3030 after-change-functions)
3034 ;; Comment detection and caching
3036 (defvar verilog-scan-cache-preserving nil
3037 "If set, the specified buffer's comment properties are static.
3038 Buffer changes will be ignored. See `verilog-inside-comment-or-string-p'
3039 and `verilog-scan'.")
3041 (defvar verilog-scan-cache-tick nil
3042 "Modification tick at which `verilog-scan' was last completed.")
3043 (make-variable-buffer-local 'verilog-scan-cache-tick)
3045 (defun verilog-scan-cache-flush ()
3046 "Flush the `verilog-scan' cache."
3047 (setq verilog-scan-cache-tick nil))
3049 (defun verilog-scan-cache-ok-p ()
3050 "Return t iff the scan cache is up to date."
3051 (or (and verilog-scan-cache-preserving
3052 (eq verilog-scan-cache-preserving (current-buffer))
3053 verilog-scan-cache-tick)
3054 (equal verilog-scan-cache-tick (buffer-chars-modified-tick))))
3056 (defmacro verilog-save-scan-cache (&rest body)
3057 "Execute the BODY forms, allowing scan cache preservation within BODY.
3058 This requires that insertions must use `verilog-insert'."
3059 ;; If the buffer is out of date, trash it, as we'll not check later the tick
3060 ;; Note this must work properly if there's multiple layers of calls
3061 ;; to verilog-save-scan-cache even with differing ticks.
3063 (unless (verilog-scan-cache-ok-p) ;; Must be before let
3064 (setq verilog-scan-cache-tick nil))
3065 (let* ((verilog-scan-cache-preserving (current-buffer)))
3068 (defun verilog-scan-region (beg end)
3069 "Parse between BEG and END for `verilog-inside-comment-or-string-p'.
3070 This creates v-cmts properties where comments are in force."
3071 ;; Why properties and not overlays? Overlays have much slower non O(1)
3073 ;; This function is warm - called on every verilog-insert
3076 (verilog-save-buffer-state
3079 (while (< (point) end)
3080 (cond ((looking-at "//")
3082 (or (search-forward "\n" end t)
3084 ;; "1+": The leading // or /* itself isn't considered as
3085 ;; being "inside" the comment, so that a (search-backward)
3086 ;; that lands at the start of the // won't mis-indicate
3087 ;; it's inside a comment. Also otherwise it would be
3088 ;; hard to find a commented out /*AS*/ vs one that isn't
3089 (put-text-property (1+ pt) (point) 'v-cmts t))
3090 ((looking-at "/\\*")
3092 (or (search-forward "*/" end t)
3093 ;; No error - let later code indicate it so we can
3094 ;; use inside functions on-the-fly
3095 ;;(error "%s: Unmatched /* */, at char %d"
3096 ;; (verilog-point-text) (point))
3098 (put-text-property (1+ pt) (point) 'v-cmts t))
3101 (or (re-search-forward "[^\\]\"" end t) ;; don't forward-char first, since we look for a non backslash first
3102 ;; No error - let later code indicate it so we can
3104 (put-text-property (1+ pt) (point) 'v-cmts t))
3107 (if (re-search-forward "[/\"]" end t)
3109 (goto-char end))))))))))
3111 (defun verilog-scan ()
3112 "Parse the buffer, marking all comments with properties.
3113 Also assumes any text inserted since `verilog-scan-cache-tick'
3114 either is ok to parse as a non-comment, or `verilog-insert' was used."
3115 ;; See also `verilog-scan-debug' and `verilog-scan-and-debug'
3116 (unless (verilog-scan-cache-ok-p)
3118 (verilog-save-buffer-state
3120 (message "Scanning %s cache=%s cachetick=%S tick=%S" (current-buffer)
3121 verilog-scan-cache-preserving verilog-scan-cache-tick
3122 (buffer-chars-modified-tick)))
3123 (remove-text-properties (point-min) (point-max) '(v-cmts nil))
3124 (verilog-scan-region (point-min) (point-max))
3125 (setq verilog-scan-cache-tick (buffer-chars-modified-tick))
3126 (when verilog-debug (message "Scanning... done"))))))
3128 (defun verilog-scan-debug ()
3129 "For debugging, show with display face results of `verilog-scan'."
3131 ;;(if dbg (setq dbg (concat dbg (format "verilog-scan-debug\n"))))
3133 (goto-char (point-min))
3134 (remove-text-properties (point-min) (point-max) '(face nil))
3136 (cond ((get-text-property (point) 'v-cmts)
3137 (put-text-property (point) (1+ (point)) `face 'underline)
3138 ;;(if dbg (setq dbg (concat dbg (format " v-cmts at %S\n" (point)))))
3141 (goto-char (or (next-property-change (point)) (point-max))))))))
3143 (defun verilog-scan-and-debug ()
3144 "For debugging, run `verilog-scan' and `verilog-scan-debug'."
3145 (let (verilog-scan-cache-preserving
3146 verilog-scan-cache-tick)
3147 (goto-char (point-min))
3149 (verilog-scan-debug)))
3151 (defun verilog-inside-comment-or-string-p (&optional pos)
3152 "Check if optional point POS is inside a comment.
3153 This may require a slow pre-parse of the buffer with `verilog-scan'
3154 to establish comment properties on all text."
3155 ;; This function is very hot
3158 (and (>= pos (point-min))
3159 (get-text-property pos 'v-cmts))
3160 (get-text-property (point) 'v-cmts)))
3162 (defun verilog-insert (&rest stuff)
3163 "Insert STUFF arguments, tracking for `verilog-inside-comment-or-string-p'.
3164 Any insert that includes a comment must have the entire commente
3165 inserted using a single call to `verilog-insert'."
3168 (insert (car stuff))
3169 (setq stuff (cdr stuff)))
3170 (verilog-scan-region pt (point))))
3174 (defun verilog-declaration-end ()
3175 (search-forward ";"))
3177 (defun verilog-point-text (&optional pointnum)
3178 "Return text describing where POINTNUM or current point is (for errors).
3179 Use filename, if current buffer being edited shorten to just buffer name."
3180 (concat (or (and (equal (window-buffer (selected-window)) (current-buffer))
3184 ":" (int-to-string (1+ (count-lines (point-min) (or pointnum (point)))))))
3186 (defun electric-verilog-backward-sexp ()
3187 "Move backward over one balanced expression."
3189 ;; before that see if we are in a comment
3190 (verilog-backward-sexp))
3192 (defun electric-verilog-forward-sexp ()
3193 "Move forward over one balanced expression."
3195 ;; before that see if we are in a comment
3196 (verilog-forward-sexp))
3198 ;;;used by hs-minor-mode
3199 (defun verilog-forward-sexp-function (arg)
3201 (verilog-backward-sexp)
3202 (verilog-forward-sexp)))
3205 (defun verilog-backward-sexp ()
3210 (if (not (looking-at "\\<"))
3213 ((verilog-skip-backward-comment-or-string))
3214 ((looking-at "\\<else\\>")
3216 verilog-end-block-re
3217 "\\|\\(\\<else\\>\\)"
3218 "\\|\\(\\<if\\>\\)"))
3219 (while (and (not found)
3220 (verilog-re-search-backward reg nil 'move))
3222 ((match-end 1) ; matched verilog-end-block-re
3223 ; try to leap back to matching outward block by striding across
3224 ; indent level changing tokens then immediately
3225 ; previous line governs indentation.
3226 (verilog-leap-to-head))
3227 ((match-end 2) ; else, we're in deep
3228 (setq elsec (1+ elsec)))
3229 ((match-end 3) ; found it
3230 (setq elsec (1- elsec))
3232 ;; Now previous line describes syntax
3233 (setq found 't))))))
3234 ((looking-at verilog-end-block-re)
3235 (verilog-leap-to-head))
3236 ((looking-at "\\(endmodule\\>\\)\\|\\(\\<endprimitive\\>\\)\\|\\(\\<endclass\\>\\)\\|\\(\\<endprogram\\>\\)\\|\\(\\<endinterface\\>\\)\\|\\(\\<endpackage\\>\\)")
3239 (verilog-re-search-backward "\\<\\(macro\\)?module\\>" nil 'move))
3241 (verilog-re-search-backward "\\<primitive\\>" nil 'move))
3243 (verilog-re-search-backward "\\<class\\>" nil 'move))
3245 (verilog-re-search-backward "\\<program\\>" nil 'move))
3247 (verilog-re-search-backward "\\<interface\\>" nil 'move))
3249 (verilog-re-search-backward "\\<package\\>" nil 'move))
3252 (backward-sexp 1))))
3257 (defun verilog-forward-sexp ()
3262 (if (not (looking-at "\\<"))
3265 ((verilog-skip-forward-comment-or-string)
3266 (verilog-forward-syntactic-ws))
3267 ((looking-at verilog-beg-block-re-ordered)
3270 ;; Search forward for matching end
3271 (setq reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)" ))
3273 ;; Search forward for matching endcase
3274 (setq reg "\\(\\<randcase\\>\\|\\(\\<unique\\>\\s-+\\|\\<priority\\>\\s-+\\)?\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" )
3275 (setq md 3) ;; ender is third item in regexp
3278 ;; might be "disable fork" or "wait fork"
3282 (looking-at verilog-disable-fork-re)
3283 (and (looking-at "fork")
3285 (setq here (point)) ;; sometimes a fork is just a fork
3287 (looking-at verilog-disable-fork-re))))
3288 (progn ;; it is a disable fork; ignore it
3289 (goto-char (match-end 0))
3292 (progn ;; it is a nice simple fork
3293 (goto-char here) ;; return from looking for "disable fork"
3294 ;; Search forward for matching join
3295 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" )))))
3297 ;; Search forward for matching endclass
3298 (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
3301 ;; Search forward for matching endtable
3302 (setq reg "\\<endtable\\>" )
3305 ;; Search forward for matching endspecify
3306 (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
3308 ;; Search forward for matching endfunction
3309 (setq reg "\\<endfunction\\>" )
3312 ;; Search forward for matching endfunction
3313 (setq reg "\\<endfunction\\>" )
3316 ;; Search forward for matching endtask
3317 (setq reg "\\<endtask\\>" )
3320 ;; Search forward for matching endtask
3321 (setq reg "\\<endtask\\>" )
3324 ;; Search forward for matching endgenerate
3325 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
3327 ;; Search forward for matching endgroup
3328 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" ))
3330 ;; Search forward for matching endproperty
3331 (setq reg "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)" ))
3333 ;; Search forward for matching endsequence
3334 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)" )
3335 (setq md 3)) ; 3 to get to endsequence in the reg above
3337 ;; Search forward for matching endclocking
3338 (setq reg "\\(\\<clocking\\>\\)\\|\\(\\<endclocking\\>\\)" )))
3345 (while (verilog-re-search-forward reg nil 'move)
3347 ((match-end md) ; a closer in regular expression, so we are climbing out
3348 (setq depth (1- depth))
3349 (if (= 0 depth) ; we are out!
3351 ((match-end 1) ; an opener in the r-e, so we are in deeper now
3352 (setq here (point)) ; remember where we started
3353 (goto-char (match-beginning 1))
3356 (looking-at verilog-disable-fork-re)
3357 (and (looking-at "fork")
3360 (looking-at verilog-disable-fork-re))))
3361 (progn ;; it is a disable fork; another false alarm
3362 (goto-char (match-end 0)))
3363 (progn ;; it is a simple fork (or has nothing to do with fork)
3365 (setq depth (1+ depth))))))))))
3366 (if (verilog-re-search-forward reg nil 'move)
3367 (throw 'skip 1))))))
3369 ((looking-at (concat
3370 "\\(\\<\\(macro\\)?module\\>\\)\\|"
3371 "\\(\\<primitive\\>\\)\\|"
3372 "\\(\\<class\\>\\)\\|"
3373 "\\(\\<program\\>\\)\\|"
3374 "\\(\\<interface\\>\\)\\|"
3375 "\\(\\<package\\>\\)"))
3378 (verilog-re-search-forward "\\<endmodule\\>" nil 'move))
3380 (verilog-re-search-forward "\\<endprimitive\\>" nil 'move))
3382 (verilog-re-search-forward "\\<endclass\\>" nil 'move))
3384 (verilog-re-search-forward "\\<endprogram\\>" nil 'move))
3386 (verilog-re-search-forward "\\<endinterface\\>" nil 'move))
3388 (verilog-re-search-forward "\\<endpackage\\>" nil 'move))
3391 (if (= (following-char) ?\) )
3393 (forward-sexp 1)))))
3396 (if (= (following-char) ?\) )
3398 (forward-sexp 1))))))
3400 (defun verilog-declaration-beg ()
3401 (verilog-re-search-backward verilog-declaration-re (bobp) t))
3407 (defvar verilog-which-tool 1)
3409 (define-derived-mode verilog-mode prog-mode "Verilog"
3410 "Major mode for editing Verilog code.
3411 \\<verilog-mode-map>
3412 See \\[describe-function] verilog-auto (\\[verilog-auto]) for details on how
3413 AUTOs can improve coding efficiency.
3415 Use \\[verilog-faq] for a pointer to frequently asked questions.
3417 NEWLINE, TAB indents for Verilog code.
3418 Delete converts tabs to spaces as it moves back.
3420 Supports highlighting.
3422 Turning on Verilog mode calls the value of the variable `verilog-mode-hook'
3423 with no args, if that value is non-nil.
3425 Variables controlling indentation/edit style:
3427 variable `verilog-indent-level' (default 3)
3428 Indentation of Verilog statements with respect to containing block.
3429 `verilog-indent-level-module' (default 3)
3430 Absolute indentation of Module level Verilog statements.
3431 Set to 0 to get initial and always statements lined up
3432 on the left side of your screen.
3433 `verilog-indent-level-declaration' (default 3)
3434 Indentation of declarations with respect to containing block.
3435 Set to 0 to get them list right under containing block.
3436 `verilog-indent-level-behavioral' (default 3)
3437 Indentation of first begin in a task or function block
3438 Set to 0 to get such code to lined up underneath the task or
3440 `verilog-indent-level-directive' (default 1)
3441 Indentation of `ifdef/`endif blocks.
3442 `verilog-cexp-indent' (default 1)
3443 Indentation of Verilog statements broken across lines i.e.:
3446 `verilog-case-indent' (default 2)
3447 Indentation for case statements.
3448 `verilog-auto-newline' (default nil)
3449 Non-nil means automatically newline after semicolons and the punctuation
3451 `verilog-auto-indent-on-newline' (default t)
3452 Non-nil means automatically indent line after newline.
3453 `verilog-tab-always-indent' (default t)
3454 Non-nil means TAB in Verilog mode should always reindent the current line,
3455 regardless of where in the line point is when the TAB command is used.
3456 `verilog-indent-begin-after-if' (default t)
3457 Non-nil means to indent begin statements following a preceding
3458 if, else, while, for and repeat statements, if any. Otherwise,
3459 the begin is lined up with the preceding token. If t, you get:
3461 begin // amount of indent based on `verilog-cexp-indent'
3465 `verilog-auto-endcomments' (default t)
3466 Non-nil means a comment /* ... */ is set after the ends which ends
3467 cases, tasks, functions and modules.
3468 The type and name of the object will be set between the braces.
3469 `verilog-minimum-comment-distance' (default 10)
3470 Minimum distance (in lines) between begin and end required before a comment
3471 will be inserted. Setting this variable to zero results in every
3472 end acquiring a comment; the default avoids too many redundant
3473 comments in tight quarters.
3474 `verilog-auto-lineup' (default 'declarations)
3475 List of contexts where auto lineup of code should be done.
3477 Variables controlling other actions:
3479 `verilog-linter' (default surelint)
3480 Unix program to call to run the lint checker. This is the default
3481 command for \\[compile-command] and \\[verilog-auto-save-compile].
3483 See \\[customize] for the complete list of variables.
3485 AUTO expansion functions are, in part:
3487 \\[verilog-auto] Expand AUTO statements.
3488 \\[verilog-delete-auto] Remove the AUTOs.
3489 \\[verilog-inject-auto] Insert AUTOs for the first time.
3491 Some other functions are:
3493 \\[verilog-complete-word] Complete word with appropriate possibilities.
3494 \\[verilog-mark-defun] Mark function.
3495 \\[verilog-beg-of-defun] Move to beginning of current function.
3496 \\[verilog-end-of-defun] Move to end of current function.
3497 \\[verilog-label-be] Label matching begin ... end, fork ... join, etc statements.
3499 \\[verilog-comment-region] Put marked area in a comment.
3500 \\[verilog-uncomment-region] Uncomment an area commented with \\[verilog-comment-region].
3501 \\[verilog-insert-block] Insert begin ... end.
3502 \\[verilog-star-comment] Insert /* ... */.
3504 \\[verilog-sk-always] Insert an always @(AS) begin .. end block.
3505 \\[verilog-sk-begin] Insert a begin .. end block.
3506 \\[verilog-sk-case] Insert a case block, prompting for details.
3507 \\[verilog-sk-for] Insert a for (...) begin .. end block, prompting for details.
3508 \\[verilog-sk-generate] Insert a generate .. endgenerate block.
3509 \\[verilog-sk-header] Insert a header block at the top of file.
3510 \\[verilog-sk-initial] Insert an initial begin .. end block.
3511 \\[verilog-sk-fork] Insert a fork begin .. end .. join block.
3512 \\[verilog-sk-module] Insert a module .. (/*AUTOARG*/);.. endmodule block.
3513 \\[verilog-sk-ovm-class] Insert an OVM Class block.
3514 \\[verilog-sk-uvm-class] Insert an UVM Class block.
3515 \\[verilog-sk-primitive] Insert a primitive .. (.. );.. endprimitive block.
3516 \\[verilog-sk-repeat] Insert a repeat (..) begin .. end block.
3517 \\[verilog-sk-specify] Insert a specify .. endspecify block.
3518 \\[verilog-sk-task] Insert a task .. begin .. end endtask block.
3519 \\[verilog-sk-while] Insert a while (...) begin .. end block, prompting for details.
3520 \\[verilog-sk-casex] Insert a casex (...) item: begin.. end endcase block, prompting for details.
3521 \\[verilog-sk-casez] Insert a casez (...) item: begin.. end endcase block, prompting for details.
3522 \\[verilog-sk-if] Insert an if (..) begin .. end block.
3523 \\[verilog-sk-else-if] Insert an else if (..) begin .. end block.
3524 \\[verilog-sk-comment] Insert a comment block.
3525 \\[verilog-sk-assign] Insert an assign .. = ..; statement.
3526 \\[verilog-sk-function] Insert a function .. begin .. end endfunction block.
3527 \\[verilog-sk-input] Insert an input declaration, prompting for details.
3528 \\[verilog-sk-output] Insert an output declaration, prompting for details.
3529 \\[verilog-sk-state-machine] Insert a state machine definition, prompting for details.
3530 \\[verilog-sk-inout] Insert an inout declaration, prompting for details.
3531 \\[verilog-sk-wire] Insert a wire declaration, prompting for details.
3532 \\[verilog-sk-reg] Insert a register declaration, prompting for details.
3533 \\[verilog-sk-define-signal] Define signal under point as a register at the top of the module.
3535 All key bindings can be seen in a Verilog-buffer with \\[describe-bindings].
3536 Key bindings specific to `verilog-mode-map' are:
3538 \\{verilog-mode-map}"
3539 :abbrev-table verilog-mode-abbrev-table
3540 (set (make-local-variable 'beginning-of-defun-function)
3541 'verilog-beg-of-defun)
3542 (set (make-local-variable 'end-of-defun-function)
3543 'verilog-end-of-defun)
3544 (set-syntax-table verilog-mode-syntax-table)
3545 (set (make-local-variable 'indent-line-function)
3546 #'verilog-indent-line-relative)
3547 (setq comment-indent-function 'verilog-comment-indent)
3548 (set (make-local-variable 'parse-sexp-ignore-comments) nil)
3549 (set (make-local-variable 'comment-start) "// ")
3550 (set (make-local-variable 'comment-end) "")
3551 (set (make-local-variable 'comment-start-skip) "/\\*+ *\\|// *")
3552 (set (make-local-variable 'comment-multi-line) nil)
3553 ;; Set up for compilation
3554 (setq verilog-which-tool 1)
3555 (setq verilog-tool 'verilog-linter)
3556 (verilog-set-compile-command)
3557 (when (boundp 'hack-local-variables-hook) ;; Also modify any file-local-variables
3558 (add-hook 'hack-local-variables-hook 'verilog-modify-compile-command t))
3561 (when (featurep 'xemacs)
3562 (easy-menu-add verilog-stmt-menu)
3563 (easy-menu-add verilog-menu)
3564 (setq mode-popup-menu (cons "Verilog Mode" verilog-stmt-menu)))
3566 ;; Stuff for GNU Emacs
3567 (set (make-local-variable 'font-lock-defaults)
3568 `((verilog-font-lock-keywords verilog-font-lock-keywords-1
3569 verilog-font-lock-keywords-2
3570 verilog-font-lock-keywords-3)
3572 ,(if (functionp 'syntax-ppss)
3573 ;; verilog-beg-of-defun uses syntax-ppss, and syntax-ppss uses
3574 ;; font-lock-beginning-of-syntax-function, so
3575 ;; font-lock-beginning-of-syntax-function, can't use
3576 ;; verilog-beg-of-defun.
3578 'verilog-beg-of-defun)))
3579 ;;------------------------------------------------------------
3580 ;; now hook in 'verilog-highlight-include-files (eldo-mode.el&spice-mode.el)
3581 ;; all buffer local:
3582 (unless noninteractive ;; Else can't see the result, and change hooks are slow
3583 (when (featurep 'xemacs)
3584 (make-local-hook 'font-lock-mode-hook)
3585 (make-local-hook 'font-lock-after-fontify-buffer-hook); doesn't exist in Emacs
3586 (make-local-hook 'after-change-functions))
3587 (add-hook 'font-lock-mode-hook 'verilog-highlight-buffer t t)
3588 (add-hook 'font-lock-after-fontify-buffer-hook 'verilog-highlight-buffer t t) ; not in Emacs
3589 (add-hook 'after-change-functions 'verilog-highlight-region t t))
3591 ;; Tell imenu how to handle Verilog.
3592 (set (make-local-variable 'imenu-generic-expression)
3593 verilog-imenu-generic-expression)
3594 ;; Tell which-func-modes that imenu knows about verilog
3595 (when (boundp 'which-func-modes)
3596 (add-to-list 'which-func-modes 'verilog-mode))
3598 (when (boundp 'hs-special-modes-alist)
3599 (unless (assq 'verilog-mode hs-special-modes-alist)
3600 (setq hs-special-modes-alist
3601 (cons '(verilog-mode-mode "\\<begin\\>" "\\<end\\>" nil
3602 verilog-forward-sexp-function)
3603 hs-special-modes-alist))))
3606 (add-hook 'write-contents-hooks 'verilog-auto-save-check nil 'local)
3607 ;; verilog-mode-hook call added by define-derived-mode
3612 ;; Electric functions
3614 (defun electric-verilog-terminate-line (&optional arg)
3615 "Terminate line and indent next line.
3616 With optional ARG, remove existing end of line comments."
3618 ;; before that see if we are in a comment
3619 (let ((state (save-excursion (verilog-syntax-ppss))))
3621 ((nth 7 state) ; Inside // comment
3624 (delete-horizontal-space)
3629 (beginning-of-line)))
3630 (verilog-indent-line))
3631 ((nth 4 state) ; Inside any comment (hence /**/)
3633 (verilog-more-comment))
3635 ;; First, check if current line should be indented
3637 (delete-horizontal-space)
3639 (skip-chars-forward " \t")
3640 (if (looking-at verilog-auto-end-comment-lines-re)
3641 (let ((indent-str (verilog-indent-line)))
3642 ;; Maybe we should set some endcomments
3643 (if verilog-auto-endcomments
3644 (verilog-set-auto-endcomments indent-str arg))
3646 (delete-horizontal-space)
3653 (delete-horizontal-space)
3655 ;; see if we should line up assignments
3657 (if (or (eq 'all verilog-auto-lineup)
3658 (eq 'assignments verilog-auto-lineup))
3659 (verilog-pretty-expr t "\\(<\\|:\\)?=" ))
3663 (if verilog-auto-indent-on-newline
3664 (verilog-indent-line)))
3668 (defun electric-verilog-terminate-and-indent ()
3669 "Insert a newline and indent for the next statement."
3671 (electric-verilog-terminate-line 1))
3673 (defun electric-verilog-semi ()
3674 "Insert `;' character and reindent the line."
3676 (verilog-insert-last-command-event)
3678 (if (or (verilog-in-comment-or-string-p)
3679 (verilog-in-escaped-name-p))
3683 (verilog-forward-ws&directives)
3684 (verilog-indent-line))
3685 (if (and verilog-auto-newline
3686 (not (verilog-parenthesis-depth)))
3687 (electric-verilog-terminate-line))))
3689 (defun electric-verilog-semi-with-comment ()
3690 "Insert `;' character, reindent the line and indent for comment."
3695 (verilog-indent-line))
3696 (indent-for-comment))
3698 (defun electric-verilog-colon ()
3699 "Insert `:' and do all indentations except line indent on this line."
3701 (verilog-insert-last-command-event)
3702 ;; Do nothing if within string.
3704 (verilog-within-string)
3705 (not (verilog-in-case-region-p)))
3709 (lim (progn (verilog-beg-of-statement) (point))))
3711 (verilog-backward-case-item lim)
3712 (verilog-indent-line)))
3713 ;; (let ((verilog-tab-always-indent nil))
3714 ;; (verilog-indent-line))
3717 ;;(defun electric-verilog-equal ()
3718 ;; "Insert `=', and do indentation if within block."
3720 ;; (verilog-insert-last-command-event)
3721 ;; Could auto line up expressions, but not yet
3722 ;; (if (eq (car (verilog-calculate-indent)) 'block)
3723 ;; (let ((verilog-tab-always-indent nil))
3724 ;; (verilog-indent-command)))
3727 (defun electric-verilog-tick ()
3728 "Insert back-tick, and indent to column 0 if this is a CPP directive."
3730 (verilog-insert-last-command-event)
3732 (if (verilog-in-directive-p)
3733 (verilog-indent-line))))
3735 (defun electric-verilog-tab ()
3736 "Function called when TAB is pressed in Verilog mode."
3738 ;; If verilog-tab-always-indent, indent the beginning of the line.
3740 ;; The region is active, indent it.
3741 ((and (region-active-p)
3742 (not (eq (region-beginning) (region-end))))
3743 (indent-region (region-beginning) (region-end) nil))
3744 ((or verilog-tab-always-indent
3746 (skip-chars-backward " \t")
3748 (let* ((oldpnt (point))
3752 (skip-chars-forward " \t")
3753 (verilog-indent-line)
3754 (back-to-indentation)
3756 (if (< (point) boi-point)
3757 (back-to-indentation)
3758 (cond ((not verilog-tab-to-comment))
3762 (indent-for-comment)
3763 (when (and (eolp) (= oldpnt (point)))
3764 ; kill existing comment
3766 (re-search-forward comment-start-skip oldpnt 'move)
3767 (goto-char (match-beginning 0))
3768 (skip-chars-backward " \t")
3769 (kill-region (point) oldpnt)))))))
3770 (t (progn (insert "\t")))))
3775 ;; Interactive functions
3778 (defun verilog-indent-buffer ()
3779 "Indent-region the entire buffer as Verilog code.
3780 To call this from the command line, see \\[verilog-batch-indent]."
3783 (indent-region (point-min) (point-max) nil))
3785 (defun verilog-insert-block ()
3786 "Insert Verilog begin ... end; block in the code with right indentation."
3788 (verilog-indent-line)
3790 (electric-verilog-terminate-line)
3792 (electric-verilog-terminate-line)
3795 (verilog-indent-line)))
3797 (defun verilog-star-comment ()
3798 "Insert Verilog star comment at point."
3800 (verilog-indent-line)
3808 (defun verilog-insert-1 (fmt max)
3809 "Use format string FMT to insert integers 0 to MAX - 1.
3810 Inserts one integer per line, at the current column. Stops early
3811 if it reaches the end of the buffer."
3812 (let ((col (current-column))
3816 (insert (format fmt n))
3818 ;; Note that this function does not bother to check for lines
3819 ;; shorter than col.
3823 (move-to-column col))))))
3825 (defun verilog-insert-indices (max)
3826 "Insert a set of indices into a rectangle.
3827 The upper left corner is defined by point. Indices begin with 0
3828 and extend to the MAX - 1. If no prefix arg is given, the user
3829 is prompted for a value. The indices are surrounded by square
3830 brackets \[]. For example, the following code with the point
3831 located after the first 'a' gives:
3837 a = b ==> insert-indices ==> a[ 4] = b
3843 (interactive "NMAX: ")
3844 (verilog-insert-1 "[%3d]" max))
3846 (defun verilog-generate-numbers (max)
3847 "Insert a set of generated numbers into a rectangle.
3848 The upper left corner is defined by point. The numbers are padded to three
3849 digits, starting with 000 and extending to (MAX - 1). If no prefix argument
3850 is supplied, then the user is prompted for the MAX number. Consider the
3851 following code fragment:
3857 buf buf ==> generate-numbers ==> buf buf004
3863 (interactive "NMAX: ")
3864 (verilog-insert-1 "%3.3d" max))
3866 (defun verilog-mark-defun ()
3867 "Mark the current Verilog function (or procedure).
3868 This puts the mark at the end, and point at the beginning."
3870 (if (featurep 'xemacs)
3873 (verilog-end-of-defun)
3875 (verilog-beg-of-defun)
3876 (if (fboundp 'zmacs-activate-region)
3877 (zmacs-activate-region)))
3880 (defun verilog-comment-region (start end)
3881 ; checkdoc-params: (start end)
3882 "Put the region into a Verilog comment.
3883 The comments that are in this area are \"deformed\":
3884 `*)' becomes `!(*' and `}' becomes `!{'.
3885 These deformed comments are returned to normal if you use
3886 \\[verilog-uncomment-region] to undo the commenting.
3888 The commented area starts with `verilog-exclude-str-start', and ends with
3889 `verilog-exclude-str-end'. But if you change these variables,
3890 \\[verilog-uncomment-region] won't recognize the comments."
3893 ;; Insert start and endcomments
3895 (if (and (save-excursion (skip-chars-forward " \t") (eolp))
3896 (not (save-excursion (skip-chars-backward " \t") (bolp))))
3898 (beginning-of-line))
3899 (insert verilog-exclude-str-end)
3904 (insert verilog-exclude-str-start)
3906 ;; Replace end-comments within commented area
3909 (while (re-search-backward "\\*/" start t)
3910 (replace-match "*-/" t t)))
3912 (let ((s+1 (1+ start)))
3913 (while (re-search-backward "/\\*" s+1 t)
3914 (replace-match "/-*" t t))))))
3916 (defun verilog-uncomment-region ()
3917 "Uncomment a commented area; change deformed comments back to normal.
3918 This command does nothing if the pointer is not in a commented
3919 area. See also `verilog-comment-region'."
3922 (let ((start (point))
3924 ;; Find the boundaries of the comment
3926 (setq start (progn (search-backward verilog-exclude-str-start nil t)
3928 (setq end (progn (search-forward verilog-exclude-str-end nil t)
3930 ;; Check if we're really inside a comment
3931 (if (or (equal start (point)) (<= end (point)))
3932 (message "Not standing within commented area.")
3934 ;; Remove endcomment
3937 (let ((pos (point)))
3939 (delete-region pos (1+ (point))))
3940 ;; Change comments back to normal
3942 (while (re-search-backward "\\*-/" start t)
3943 (replace-match "*/" t t)))
3945 (while (re-search-backward "/-\\*" start t)
3946 (replace-match "/*" t t)))
3947 ;; Remove start comment
3950 (let ((pos (point)))
3952 (delete-region pos (1+ (point)))))))))
3954 (defun verilog-beg-of-defun ()
3955 "Move backward to the beginning of the current function or procedure."
3957 (verilog-re-search-backward verilog-defun-re nil 'move))
3959 (defun verilog-beg-of-defun-quick ()
3960 "Move backward to the beginning of the current function or procedure.
3961 Uses `verilog-scan' cache."
3963 (verilog-re-search-backward-quick verilog-defun-re nil 'move))
3965 (defun verilog-end-of-defun ()
3966 "Move forward to the end of the current function or procedure."
3968 (verilog-re-search-forward verilog-end-defun-re nil 'move))
3970 (defun verilog-get-beg-of-defun (&optional warn)
3972 (cond ((verilog-re-search-forward-quick verilog-defun-re nil t)
3975 (error "%s: Can't find module beginning" (verilog-point-text))
3977 (defun verilog-get-end-of-defun (&optional warn)
3979 (cond ((verilog-re-search-forward-quick verilog-end-defun-re nil t)
3982 (error "%s: Can't find endmodule" (verilog-point-text))
3985 (defun verilog-label-be (&optional arg)
3986 "Label matching begin ... end, fork ... join and case ... endcase statements.
3987 With ARG, first kill any existing labels."
3992 (verilog-beg-of-defun)
3995 (verilog-end-of-defun)
3997 (goto-char (marker-position b))
3999 (message "Relabeling module..."))
4001 (> (marker-position e) (point))
4002 (verilog-re-search-forward
4004 "\\<end\\(\\(function\\)\\|\\(task\\)\\|\\(module\\)\\|\\(primitive\\)\\|\\(interface\\)\\|\\(package\\)\\|\\(case\\)\\)?\\>"
4005 "\\|\\(`endif\\)\\|\\(`else\\)")
4007 (goto-char (match-beginning 0))
4008 (let ((indent-str (verilog-indent-line)))
4009 (verilog-set-auto-endcomments indent-str 't)
4011 (delete-horizontal-space))
4013 (if (= 9 (% cnt 10))
4014 (message "%d..." cnt)))
4019 (message "%d lines auto commented" cnt))))
4021 (defun verilog-beg-of-statement ()
4022 "Move backward to beginning of statement."
4024 ;; Move back token by token until we see the end
4025 ;; of some earlier line.
4028 ;; If the current point does not begin a new
4029 ;; statement, as in the character ahead of us is a ';', or SOF
4030 ;; or the string after us unambiguously starts a statement,
4031 ;; or the token before us unambiguously ends a statement,
4032 ;; then move back a token and test again.
4034 ;; stop if beginning of buffer
4036 ;; stop if we find a ;
4037 (= (preceding-char) ?\;)
4038 ;; stop if we see a named coverpoint
4039 (looking-at "\\w+\\W*:\\W*\\(coverpoint\\|cross\\|constraint\\)")
4040 ;; keep going if we are in the middle of a word
4041 (not (or (looking-at "\\<") (forward-word -1)))
4042 ;; stop if we see an assertion (perhaps labeled)
4044 (looking-at "\\(\\<\\(assert\\|assume\\|cover\\)\\>\\s-+\\<property\\>\\)\\|\\(\\<assert\\>\\)")
4048 (verilog-backward-token)
4049 (if (looking-at verilog-label-re)
4052 ;; stop if we see a complete reg, perhaps an extended one
4054 (looking-at verilog-complete-reg)
4056 (while (and (looking-at verilog-extended-complete-re)
4057 (progn (setq p (point))
4058 (verilog-backward-token)
4061 ;; stop if we see a complete reg (previous found extended ones)
4062 (looking-at verilog-basic-complete-re)
4063 ;; stop if previous token is an ender
4065 (verilog-backward-token)
4067 (looking-at verilog-end-block-re)
4068 (looking-at verilog-preprocessor-re))))) ;; end of test
4069 (verilog-backward-syntactic-ws)
4070 (verilog-backward-token))
4071 ;; Now point is where the previous line ended.
4072 (verilog-forward-syntactic-ws)))
4074 (defun verilog-beg-of-statement-1 ()
4075 "Move backward to beginning of statement."
4077 (if (verilog-in-comment-p)
4078 (verilog-backward-syntactic-ws))
4081 (while (not (looking-at verilog-complete-reg))
4083 (verilog-backward-syntactic-ws)
4085 (= (preceding-char) ?\;)
4087 (verilog-backward-token)
4088 (looking-at verilog-ends-re)))
4092 (verilog-backward-token))))
4093 (verilog-forward-syntactic-ws)))
4096 ; (not (looking-at verilog-complete-reg))
4098 ; (not (= (preceding-char) ?\;)))
4099 ; (verilog-backward-token)
4100 ; (verilog-backward-syntactic-ws)
4101 ; (setq pt (point)))
4103 ; ;(verilog-forward-syntactic-ws)
4105 (defun verilog-end-of-statement ()
4106 "Move forward to end of current statement."
4110 ((verilog-in-directive-p)
4114 ((looking-at verilog-beg-block-re)
4115 (verilog-forward-sexp))
4117 ((equal (char-after) ?\})
4120 ;; Skip to end of statement
4121 ((condition-case nil
4126 (verilog-skip-forward-comment-or-string)
4129 (cond ((looking-at "[ \t]*;")
4130 (skip-chars-forward "^;")
4132 (throw 'found (point)))
4135 (looking-at verilog-beg-block-re))
4136 (goto-char (match-beginning 0))
4138 ((looking-at "[ \t]*)")
4139 (throw 'found (point)))
4141 (throw 'found (point)))
4147 ;; Skip a whole block
4150 (verilog-re-search-forward verilog-end-statement-re nil 'move)
4151 (setq nest (if (match-end 1)
4155 (throw 'found (point)))
4157 (throw 'found (verilog-end-of-statement))))))
4160 (defun verilog-in-case-region-p ()
4161 "Return true if in a case region.
4162 More specifically, point @ in the line foo : @ begin"
4166 (progn (verilog-forward-syntactic-ws)
4167 (looking-at "\\<begin\\>"))
4168 (progn (verilog-backward-syntactic-ws)
4169 (= (preceding-char) ?\:)))
4173 (verilog-re-search-backward
4174 (concat "\\(\\<module\\>\\)\\|\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|"
4175 "\\(\\<endcase\\>\\)\\>")
4179 (setq nest (1+ nest)))
4183 (setq nest (1- nest)))
4185 (throw 'found (= nest 0)))))))
4188 (defun verilog-backward-up-list (arg)
4189 "Like `backward-up-list', but deal with comments."
4190 (let ((parse-sexp-ignore-comments t))
4191 (backward-up-list arg)))
4193 (defun verilog-forward-sexp-cmt (arg)
4194 "Call `forward-sexp', inside comments."
4195 (let ((parse-sexp-ignore-comments nil))
4196 (forward-sexp arg)))
4198 (defun verilog-forward-sexp-ign-cmt (arg)
4199 "Call `forward-sexp', ignoring comments."
4200 (let ((parse-sexp-ignore-comments t))
4201 (forward-sexp arg)))
4203 (defun verilog-in-struct-region-p ()
4204 "Return true if in a struct region.
4205 More specifically, in a list after a struct|union keyword."
4208 (let* ((state (verilog-syntax-ppss))
4209 (depth (nth 0 state)))
4211 (progn (verilog-backward-up-list depth)
4212 (verilog-beg-of-statement)
4213 (looking-at "\\<typedef\\>?\\s-*\\<struct\\|union\\>"))))))
4215 (defun verilog-in-generate-region-p ()
4216 "Return true if in a generate region.
4217 More specifically, after a generate and before an endgenerate."
4224 (verilog-re-search-backward
4225 "\\<\\(module\\)\\|\\(generate\\)\\|\\(endgenerate\\)\\>" nil 'move)
4227 ((match-end 1) ; module - we have crawled out
4229 ((match-end 2) ; generate
4230 (setq nest (1- nest)))
4231 ((match-end 3) ; endgenerate
4232 (setq nest (1+ nest))))))))
4233 (= nest 0) )) ; return nest
4235 (defun verilog-in-fork-region-p ()
4236 "Return true if between a fork and join."
4238 (let ((lim (save-excursion (verilog-beg-of-defun) (point)))
4243 (verilog-re-search-backward "\\<\\(fork\\)\\|\\(join\\(_any\\|_none\\)?\\)\\>" lim 'move)
4245 ((match-end 1) ; fork
4246 (setq nest (1- nest)))
4247 ((match-end 2) ; join
4248 (setq nest (1+ nest)))))))
4249 (= nest 0) )) ; return nest
4251 (defun verilog-backward-case-item (lim)
4252 "Skip backward to nearest enclosing case item.
4253 Limit search to point LIM."
4259 (verilog-re-search-backward verilog-endcomment-reason-re
4262 ;; Try to find the real :
4263 (if (save-excursion (search-backward ":" lim1 t))
4269 (verilog-re-search-backward "\\(\\[\\)\\|\\(\\]\\)\\|\\(:\\)"
4273 (setq colon (1+ colon))
4275 (error "%s: unbalanced [" (verilog-point-text))))
4277 (setq colon (1- colon)))
4280 (setq colon (1+ colon)))))
4281 ;; Skip back to beginning of case item
4282 (skip-chars-backward "\t ")
4283 (verilog-skip-backward-comment-or-string)
4288 (verilog-re-search-backward
4289 "\\<\\(case[zx]?\\)\\>\\|;\\|\\<end\\>" nil 'move)
4293 (goto-char (match-end 1))
4294 (verilog-forward-ws&directives)
4295 (if (looking-at "(")
4298 (verilog-forward-ws&directives)))
4301 (goto-char (match-end 0))
4302 (verilog-forward-ws&directives)
4304 (error "Malformed case item"))))
4305 (setq str (buffer-substring b e))
4309 "[ \t]*\\(\\(\n\\)\\|\\(//\\)\\|\\(/\\*\\)\\)" str))
4310 (setq str (concat (substring str 0 e) "...")))
4319 (defun verilog-kill-existing-comment ()
4320 "Kill auto comment on this line."
4328 (search-forward "//" e t))))
4330 (delete-region (- b 2) e)))))
4332 (defconst verilog-directive-nest-re
4333 (concat "\\(`else\\>\\)\\|"
4334 "\\(`endif\\>\\)\\|"
4336 "\\(`ifdef\\>\\)\\|"
4337 "\\(`ifndef\\>\\)\\|"
4339 (defun verilog-set-auto-endcomments (indent-str kill-existing-comment)
4340 "Add ending comment with given INDENT-STR.
4341 With KILL-EXISTING-COMMENT, remove what was there before.
4342 Insert `// case: 7 ' or `// NAME ' on this line if appropriate.
4343 Insert `// case expr ' if this line ends a case block.
4344 Insert `// ifdef FOO ' if this line ends code conditional on FOO.
4345 Insert `// NAME ' if this line ends a function, task, module,
4346 primitive or interface named NAME."
4349 (; Comment close preprocessor directives
4351 (looking-at "\\(`endif\\)\\|\\(`else\\)")
4352 (or kill-existing-comment
4353 (not (save-excursion
4355 (search-backward "//" (point-at-bol) t)))))
4358 (else (if (match-end 2) "!" " ")))
4360 (if kill-existing-comment
4361 (verilog-kill-existing-comment))
4362 (delete-horizontal-space)
4365 (while (and (/= nest 0)
4366 (verilog-re-search-backward verilog-directive-nest-re nil 'move))
4368 ((match-end 1) ; `else
4371 ((match-end 2) ; `endif
4372 (setq nest (1+ nest)))
4373 ((match-end 3) ; `if
4374 (setq nest (1- nest)))
4375 ((match-end 4) ; `ifdef
4376 (setq nest (1- nest)))
4377 ((match-end 5) ; `ifndef
4378 (setq nest (1- nest)))
4379 ((match-end 6) ; `elsif
4390 (skip-chars-forward "^ \t")
4391 (verilog-forward-syntactic-ws)
4394 (skip-chars-forward "a-zA-Z0-9_")
4397 (if (> (count-lines (point) b) verilog-minimum-comment-distance)
4398 (insert (concat " // " else m " " (buffer-substring b e))))
4400 (insert " // unmatched `else, `elsif or `endif")
4403 (; Comment close case/class/function/task/module and named block
4404 (and (looking-at "\\<end")
4405 (or kill-existing-comment
4406 (not (save-excursion
4408 (search-backward "//" (point-at-bol) t)))))
4409 (let ((type (car indent-str)))
4410 (unless (eq type 'declaration)
4411 (unless (looking-at (concat "\\(" verilog-end-block-ordered-re "\\)[ \t]*:")) ;; ignore named ends
4412 (if (looking-at verilog-end-block-ordered-re)
4414 (;- This is a case block; search back for the start of this case
4415 (match-end 1) ;; of verilog-end-block-ordered-re
4418 (str "UNMATCHED!!"))
4420 (verilog-leap-to-head)
4422 ((looking-at "\\<randcase\\>")
4423 (setq str "randcase")
4425 ((looking-at "\\(\\(unique\\s-+\\|priority\\s-+\\)?case[xz]?\\)")
4426 (goto-char (match-end 0))
4427 (setq str (concat (match-string 0) " " (verilog-get-expr)))
4431 (if kill-existing-comment
4432 (verilog-kill-existing-comment))
4433 (delete-horizontal-space)
4434 (insert (concat " // " str ))
4435 (if err (ding 't))))
4437 (;- This is a begin..end block
4438 (match-end 2) ;; of verilog-end-block-ordered-re
4439 (let ((str " // UNMATCHED !!")
4445 (verilog-leap-to-head)
4446 (setq there (point))
4447 (if (not (match-end 0))
4451 (if kill-existing-comment
4452 (verilog-kill-existing-comment))
4453 (delete-horizontal-space)
4457 (save-excursion (verilog-beg-of-defun) (point)))
4460 (;-- handle named block differently
4461 (looking-at verilog-named-block-re)
4462 (search-forward ":")
4463 (setq there (point))
4464 (setq str (verilog-get-expr))
4466 (setq str (concat " // block: " str )))
4468 ((verilog-in-case-region-p) ;-- handle case item differently
4470 (setq str (verilog-backward-case-item lim))
4471 (setq there (point))
4473 (setq str (concat " // case: " str )))
4475 (;- try to find "reason" for this begin
4479 ;; (verilog-backward-token)
4480 (verilog-beg-of-statement)
4484 ((looking-at verilog-endcomment-reason-re)
4485 (setq there (match-end 0))
4486 (setq cntx (concat (match-string 0) " "))
4492 (if (and (verilog-continued-line)
4493 (looking-at "\\<repeat\\>\\|\\<wait\\>\\|\\<always\\>"))
4495 (goto-char (match-end 0))
4496 (setq there (point))
4498 (concat " // " (match-string 0) " " (verilog-get-expr))))
4504 ( reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<if\\>\\)\\|\\(assert\\)"))
4506 (while (verilog-re-search-backward reg nil 'move)
4508 ((match-end 1) ; begin
4509 (setq nest (1- nest)))
4510 ((match-end 2) ; end
4511 (setq nest (1+ nest)))
4515 (goto-char (match-end 0))
4516 (setq there (point))
4518 (setq str (verilog-get-expr))
4519 (setq str (concat " // else: !if" str ))
4524 (goto-char (match-end 0))
4525 (setq there (point))
4527 (setq str (verilog-get-expr))
4528 (setq str (concat " // else: !assert " str ))
4529 (throw 'skip 1)))))))))
4534 (reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<if\\>\\)\\|\\(assert\\)"))
4536 (while (verilog-re-search-backward reg nil 'move)
4538 ((match-end 1) ; begin
4539 (setq nest (1- nest)))
4540 ((match-end 2) ; end
4541 (setq nest (1+ nest)))
4545 (goto-char (match-end 0))
4546 (setq there (point))
4548 (setq str (verilog-get-expr))
4549 (setq str (concat " // else: !if" str ))
4554 (goto-char (match-end 0))
4555 (setq there (point))
4557 (setq str (verilog-get-expr))
4558 (setq str (concat " // else: !assert " str ))
4559 (throw 'skip 1)))))))))
4561 (; always_comb, always_ff, always_latch
4562 (or (match-end 4) (match-end 5) (match-end 6))
4563 (goto-char (match-end 0))
4564 (setq there (point))
4566 (setq str (concat " // " cntx )))
4568 (;- task/function/initial et cetera
4571 (goto-char (match-end 0))
4572 (setq there (point))
4574 (setq str (concat " // " cntx (verilog-get-expr))))
4577 (setq str " // auto-endcomment confused "))))
4580 (verilog-in-case-region-p) ;-- handle case item differently
4582 (setq there (point))
4584 (setq str (verilog-backward-case-item lim))))
4586 (setq str (concat " // case: " str )))
4588 ((verilog-in-fork-region-p)
4590 (setq str " // fork branch" ))
4592 ((looking-at "\\<end\\>")
4595 (verilog-forward-syntactic-ws)
4597 (setq str (verilog-get-expr))
4598 (setq str (concat " // " cntx str )))
4603 (if kill-existing-comment
4604 (verilog-kill-existing-comment))
4605 (delete-horizontal-space)
4607 (> (count-lines here there) verilog-minimum-comment-distance))
4611 (;- this is endclass, which can be nested
4612 (match-end 11) ;; of verilog-end-block-ordered-re
4615 (reg "\\<\\(class\\)\\|\\(endclass\\)\\|\\(package\\|primitive\\|\\(macro\\)?module\\)\\>")
4619 (while (verilog-re-search-backward reg nil 'move)
4621 ((match-end 3) ; endclass
4623 (setq string "unmatched endclass")
4626 ((match-end 2) ; endclass
4627 (setq nest (1+ nest)))
4629 ((match-end 1) ; class
4630 (setq nest (1- nest))
4633 (goto-char (match-end 0))
4636 (skip-chars-forward "^ \t")
4637 (verilog-forward-ws&directives)
4640 (skip-chars-forward "a-zA-Z0-9_")
4642 (setq string (buffer-substring b e)))
4646 (insert (concat " // " string ))))
4648 (;- this is end{function,generate,task,module,primitive,table,generate}
4649 ;- which can not be nested.
4651 (let (string reg (name-re nil))
4653 (if kill-existing-comment
4655 (verilog-kill-existing-comment)))
4656 (delete-horizontal-space)
4659 ((match-end 5) ;; of verilog-end-block-ordered-re
4660 (setq reg "\\(\\<function\\>\\)\\|\\(\\<\\(endfunction\\|task\\|\\(macro\\)?module\\|primitive\\)\\>\\)")
4661 (setq name-re "\\w+\\s-*(")
4663 ((match-end 6) ;; of verilog-end-block-ordered-re
4664 (setq reg "\\(\\<task\\>\\)\\|\\(\\<\\(endtask\\|function\\|\\(macro\\)?module\\|primitive\\)\\>\\)"))
4665 ((match-end 7) ;; of verilog-end-block-ordered-re
4666 (setq reg "\\(\\<\\(macro\\)?module\\>\\)\\|\\<endmodule\\>"))
4667 ((match-end 8) ;; of verilog-end-block-ordered-re
4668 (setq reg "\\(\\<primitive\\>\\)\\|\\(\\<\\(endprimitive\\|package\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4669 ((match-end 9) ;; of verilog-end-block-ordered-re
4670 (setq reg "\\(\\<interface\\>\\)\\|\\(\\<\\(endinterface\\|package\\|primitive\\|\\(macro\\)?module\\)\\>\\)"))
4671 ((match-end 10) ;; of verilog-end-block-ordered-re
4672 (setq reg "\\(\\<package\\>\\)\\|\\(\\<\\(endpackage\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4673 ((match-end 11) ;; of verilog-end-block-ordered-re
4674 (setq reg "\\(\\<class\\>\\)\\|\\(\\<\\(endclass\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4675 ((match-end 12) ;; of verilog-end-block-ordered-re
4676 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<\\(endcovergroup\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4677 ((match-end 13) ;; of verilog-end-block-ordered-re
4678 (setq reg "\\(\\<program\\>\\)\\|\\(\\<\\(endprogram\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4679 ((match-end 14) ;; of verilog-end-block-ordered-re
4680 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<\\(endsequence\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4681 ((match-end 15) ;; of verilog-end-block-ordered-re
4682 (setq reg "\\(\\<clocking\\>\\)\\|\\<endclocking\\>"))
4684 (t (error "Problem in verilog-set-auto-endcomments")))
4687 (verilog-re-search-backward reg nil 'move)
4691 (skip-chars-forward "^ \t")
4692 (verilog-forward-ws&directives)
4693 (if (looking-at "static\\|automatic")
4695 (goto-char (match-end 0))
4696 (verilog-forward-ws&directives)))
4697 (if (and name-re (verilog-re-search-forward name-re nil 'move))
4699 (goto-char (match-beginning 0))
4700 (verilog-forward-ws&directives)))
4703 (skip-chars-forward "a-zA-Z0-9_")
4705 (setq string (buffer-substring b e)))
4708 (setq string "unmatched end(function|task|module|primitive|interface|package|class|clocking)")))))
4710 (insert (concat " // " string )))
4713 (defun verilog-get-expr()
4714 "Grab expression at point, e.g, case ( a | b & (c ^d))."
4716 (verilog-forward-syntactic-ws)
4717 (skip-chars-forward " \t")
4723 (verilog-forward-syntactic-ws)
4724 (if (looking-at "(")
4727 (while (and (/= par 0)
4728 (verilog-re-search-forward "\\((\\)\\|\\()\\)" nil 'move))
4731 (setq par (1+ par)))
4733 (setq par (1- par)))))))
4737 (while (and (/= par 0)
4738 (verilog-re-search-forward "\\((\\)\\|\\()\\)" nil 'move))
4741 (setq par (1+ par)))
4743 (setq par (1- par)))))
4747 (while (and (/= par 0)
4748 (verilog-re-search-forward "\\(\\[\\)\\|\\(\\]\\)" nil 'move))
4751 (setq par (1+ par)))
4753 (setq par (1- par)))))
4754 (verilog-forward-syntactic-ws)
4755 (skip-chars-forward "^ \t\n\f")
4757 ((looking-at "/[/\\*]")
4760 (skip-chars-forward "^: \t\n\f")
4762 (str (buffer-substring b e)))
4763 (if (setq e (string-match "[ \t]*\\(\\(\n\\)\\|\\(//\\)\\|\\(/\\*\\)\\)" str))
4764 (setq str (concat (substring str 0 e) "...")))
4767 (defun verilog-expand-vector ()
4768 "Take a signal vector on the current line and expand it to multiple lines.
4769 Useful for creating tri's and other expanded fields."
4771 (verilog-expand-vector-internal "[" "]"))
4773 (defun verilog-expand-vector-internal (bra ket)
4774 "Given BRA, the start brace and KET, the end brace, expand one line into many lines."
4777 (let ((signal-string (buffer-substring (point)
4779 (end-of-line) (point)))))
4783 "\\([0-9]*\\)\\(:[0-9]*\\|\\)\\(::[0-9---]*\\|\\)"
4785 "\\(.*\\)$") signal-string)
4786 (let* ((sig-head (match-string 1 signal-string))
4787 (vec-start (string-to-number (match-string 2 signal-string)))
4788 (vec-end (if (= (match-beginning 3) (match-end 3))
4791 (substring signal-string (1+ (match-beginning 3))
4794 (if (= (match-beginning 4) (match-end 4))
4797 (substring signal-string (+ 2 (match-beginning 4))
4799 (sig-tail (match-string 5 signal-string))
4804 (let ((tmp vec-start))
4805 (setq vec-start vec-end
4807 vec-range (- vec-range))))
4808 (if (< vec-end vec-start)
4809 (while (<= vec-end vec-start)
4810 (setq vec (append vec (list vec-start)))
4811 (setq vec-start (- vec-start vec-range)))
4812 (while (<= vec-start vec-end)
4813 (setq vec (append vec (list vec-start)))
4814 (setq vec-start (+ vec-start vec-range))))
4816 ;; Delete current line
4817 (delete-region (point) (progn (forward-line 0) (point)))
4821 (insert (concat sig-head bra
4822 (int-to-string (car vec)) ket sig-tail "\n"))
4823 (setq vec (cdr vec)))
4828 (defun verilog-strip-comments ()
4829 "Strip all comments from the Verilog code."
4831 (goto-char (point-min))
4832 (while (re-search-forward "//" nil t)
4833 (if (verilog-within-string)
4834 (re-search-forward "\"" nil t)
4835 (if (verilog-in-star-comment-p)
4836 (re-search-forward "\*/" nil t)
4837 (let ((bpt (- (point) 2)))
4839 (delete-region bpt (point))))))
4841 (goto-char (point-min))
4842 (while (re-search-forward "/\\*" nil t)
4843 (if (verilog-within-string)
4844 (re-search-forward "\"" nil t)
4845 (let ((bpt (- (point) 2)))
4846 (re-search-forward "\\*/")
4847 (delete-region bpt (point))))))
4849 (defun verilog-one-line ()
4850 "Convert structural Verilog instances to occupy one line."
4852 (goto-char (point-min))
4853 (while (re-search-forward "\\([^;]\\)[ \t]*\n[ \t]*" nil t)
4854 (replace-match "\\1 " nil nil)))
4856 (defun verilog-linter-name ()
4857 "Return name of linter, either surelint or verilint."
4858 (let ((compile-word1 (verilog-string-replace-matches "\\s .*$" "" nil nil
4860 (lint-word1 (verilog-string-replace-matches "\\s .*$" "" nil nil
4862 (cond ((equal compile-word1 "surelint") `surelint)
4863 ((equal compile-word1 "verilint") `verilint)
4864 ((equal lint-word1 "surelint") `surelint)
4865 ((equal lint-word1 "verilint") `verilint)
4866 (t `surelint)))) ;; back compatibility
4868 (defun verilog-lint-off ()
4869 "Convert a Verilog linter warning line into a disable statement.
4871 pci_bfm_null.v, line 46: Unused input: pci_rst_
4872 becomes a comment for the appropriate tool.
4874 The first word of the `compile-command' or `verilog-linter'
4875 variables is used to determine which product is being used.
4877 See \\[verilog-surelint-off] and \\[verilog-verilint-off]."
4879 (let ((linter (verilog-linter-name)))
4880 (cond ((equal linter `surelint)
4881 (verilog-surelint-off))
4882 ((equal linter `verilint)
4883 (verilog-verilint-off))
4884 (t (error "Linter name not set")))))
4886 (defvar compilation-last-buffer)
4887 (defvar next-error-last-buffer)
4889 (defun verilog-surelint-off ()
4890 "Convert a SureLint warning line into a disable statement.
4891 Run from Verilog source window; assumes there is a *compile* buffer
4892 with point set appropriately.
4895 WARNING [STD-UDDONX]: xx.v, line 8: output out is never assigned.
4897 // surefire lint_line_off UDDONX"
4899 (let ((buff (if (boundp 'next-error-last-buffer)
4900 next-error-last-buffer
4901 compilation-last-buffer)))
4902 (when (buffer-live-p buff)
4904 (switch-to-buffer buff)
4907 (looking-at "\\(INFO\\|WARNING\\|ERROR\\) \\[[^-]+-\\([^]]+\\)\\]: \\([^,]+\\), line \\([0-9]+\\): \\(.*\\)$")
4908 (let* ((code (match-string 2))
4909 (file (match-string 3))
4910 (line (match-string 4))
4911 (buffer (get-file-buffer file))
4916 (and (file-exists-p file)
4917 (find-file-noselect file)))
4919 (let* ((pop-up-windows t))
4920 (let ((name (expand-file-name
4922 (format "Find this error in: (default %s) "
4925 (if (file-directory-p name)
4926 (setq name (expand-file-name filename name)))
4928 (and (file-exists-p name)
4929 (find-file-noselect name))))))))
4930 (switch-to-buffer buffer)
4931 (goto-char (point-min))
4932 (forward-line (- (string-to-number line)))
4936 ((verilog-in-slash-comment-p)
4937 (re-search-backward "//")
4939 ((looking-at "// surefire lint_off_line ")
4940 (goto-char (match-end 0))
4941 (let ((lim (point-at-eol)))
4942 (if (re-search-forward code lim 'move)
4944 (insert (concat " " code)))))
4947 ((verilog-in-star-comment-p)
4948 (re-search-backward "/\*")
4949 (insert (format " // surefire lint_off_line %6s" code )))
4951 (insert (format " // surefire lint_off_line %6s" code ))
4954 (defun verilog-verilint-off ()
4955 "Convert a Verilint warning line into a disable statement.
4958 (W240) pci_bfm_null.v, line 46: Unused input: pci_rst_
4960 //Verilint 240 off // WARNING: Unused input"
4964 (when (looking-at "\\(.*\\)([WE]\\([0-9A-Z]+\\)).*,\\s +line\\s +[0-9]+:\\s +\\([^:\n]+\\):?.*$")
4965 (replace-match (format
4966 ;; %3s makes numbers 1-999 line up nicely
4967 "\\1//Verilint %3s off // WARNING: \\3"
4970 (verilog-indent-line))))
4972 (defun verilog-auto-save-compile ()
4973 "Update automatics with \\[verilog-auto], save the buffer, and compile."
4975 (verilog-auto) ; Always do it for safety
4977 (compile compile-command))
4979 (defun verilog-preprocess (&optional command filename)
4980 "Preprocess the buffer, similar to `compile', but leave output in Verilog-Mode.
4981 Takes optional COMMAND or defaults to `verilog-preprocessor', and
4982 FILENAME or defaults to `buffer-file-name`."
4985 (let ((default (verilog-expand-command verilog-preprocessor)))
4986 (set (make-local-variable `verilog-preprocessor)
4987 (read-from-minibuffer "Run Preprocessor (like this): "
4989 'verilog-preprocess-history default)))))
4990 (unless command (setq command (verilog-expand-command verilog-preprocessor)))
4991 (let* ((fontlocked (and (boundp 'font-lock-mode) font-lock-mode))
4992 (dir (file-name-directory (or filename buffer-file-name)))
4993 (file (file-name-nondirectory (or filename buffer-file-name)))
4994 (cmd (concat "cd " dir "; " command " " file)))
4995 (with-output-to-temp-buffer "*Verilog-Preprocessed*"
4996 (with-current-buffer (get-buffer "*Verilog-Preprocessed*")
4997 (insert (concat "// " cmd "\n"))
4998 (shell-command cmd "*Verilog-Preprocessed*")
5000 ;; Without this force, it takes a few idle seconds
5001 ;; to get the color, which is very jarring
5002 (when fontlocked (font-lock-fontify-buffer))))))
5009 (defmacro verilog-batch-error-wrapper (&rest body)
5010 "Execute BODY and add error prefix to any errors found.
5011 This lets programs calling batch mode to easily extract error messages."
5012 `(condition-case err
5015 (error "%%Error: %s%s" (error-message-string err)
5016 (if (featurep 'xemacs) "\n" ""))))) ;; XEmacs forgets to add a newline
5018 (defun verilog-batch-execute-func (funref &optional no-save)
5019 "Internal processing of a batch command, running FUNREF on all command arguments.
5020 Save the result unless optional NO-SAVE is t."
5021 (verilog-batch-error-wrapper
5022 ;; Setting global variables like that is *VERY NASTY* !!! --Stef
5023 ;; However, this function is called only when Emacs is being used as
5024 ;; a standalone language instead of as an editor, so we'll live.
5026 ;; General globals needed
5027 (setq make-backup-files nil)
5028 (setq-default make-backup-files nil)
5029 (setq enable-local-variables t)
5030 (setq enable-local-eval t)
5031 ;; Make sure any sub-files we read get proper mode
5032 (setq-default major-mode 'verilog-mode)
5033 ;; Ditto files already read in
5035 (when (buffer-file-name buf)
5036 (with-current-buffer buf
5039 ;; Process the files
5040 (mapcar (lambda (buf)
5041 (when (buffer-file-name buf)
5043 (if (not (file-exists-p (buffer-file-name buf)))
5045 (concat "File not found: " (buffer-file-name buf))))
5046 (message (concat "Processing " (buffer-file-name buf)))
5049 (unless no-save (save-buffer)))))
5052 (defun verilog-batch-auto ()
5053 "For use with --batch, perform automatic expansions as a stand-alone tool.
5054 This sets up the appropriate Verilog mode environment, updates automatics
5055 with \\[verilog-auto] on all command-line files, and saves the buffers.
5056 For proper results, multiple filenames need to be passed on the command
5057 line in bottom-up order."
5058 (unless noninteractive
5059 (error "Use verilog-batch-auto only with --batch")) ;; Otherwise we'd mess up buffer modes
5060 (verilog-batch-execute-func `verilog-auto))
5062 (defun verilog-batch-delete-auto ()
5063 "For use with --batch, perform automatic deletion as a stand-alone tool.
5064 This sets up the appropriate Verilog mode environment, deletes automatics
5065 with \\[verilog-delete-auto] on all command-line files, and saves the buffers."
5066 (unless noninteractive
5067 (error "Use verilog-batch-delete-auto only with --batch")) ;; Otherwise we'd mess up buffer modes
5068 (verilog-batch-execute-func `verilog-delete-auto))
5070 (defun verilog-batch-diff-auto ()
5071 "For use with --batch, perform automatic differences as a stand-alone tool.
5072 This sets up the appropriate Verilog mode environment, expand automatics
5073 with \\[verilog-diff-auto] on all command-line files, and reports an error
5074 if any differences are observed. This is appropriate for adding to regressions
5075 to insure automatics are always properly maintained."
5076 (unless noninteractive
5077 (error "Use verilog-batch-diff-auto only with --batch")) ;; Otherwise we'd mess up buffer modes
5078 (verilog-batch-execute-func `verilog-diff-auto t))
5080 (defun verilog-batch-inject-auto ()
5081 "For use with --batch, perform automatic injection as a stand-alone tool.
5082 This sets up the appropriate Verilog mode environment, injects new automatics
5083 with \\[verilog-inject-auto] on all command-line files, and saves the buffers.
5084 For proper results, multiple filenames need to be passed on the command
5085 line in bottom-up order."
5086 (unless noninteractive
5087 (error "Use verilog-batch-inject-auto only with --batch")) ;; Otherwise we'd mess up buffer modes
5088 (verilog-batch-execute-func `verilog-inject-auto))
5090 (defun verilog-batch-indent ()
5091 "For use with --batch, reindent an a entire file as a stand-alone tool.
5092 This sets up the appropriate Verilog mode environment, calls
5093 \\[verilog-indent-buffer] on all command-line files, and saves the buffers."
5094 (unless noninteractive
5095 (error "Use verilog-batch-indent only with --batch")) ;; Otherwise we'd mess up buffer modes
5096 (verilog-batch-execute-func `verilog-indent-buffer))
5102 (defconst verilog-indent-alist
5103 '((block . (+ ind verilog-indent-level))
5104 (case . (+ ind verilog-case-indent))
5105 (cparenexp . (+ ind verilog-indent-level))
5106 (cexp . (+ ind verilog-cexp-indent))
5107 (defun . verilog-indent-level-module)
5108 (declaration . verilog-indent-level-declaration)
5109 (directive . (verilog-calculate-indent-directive))
5110 (tf . verilog-indent-level)
5111 (behavioral . (+ verilog-indent-level-behavioral verilog-indent-level-module))
5114 (comment . (verilog-comment-indent))
5118 (defun verilog-continued-line-1 (lim)
5119 "Return true if this is a continued line.
5120 Set point to where line starts. Limit search to point LIM."
5121 (let ((continued 't))
5122 (if (eq 0 (forward-line -1))
5125 (verilog-backward-ws&directives lim)
5127 (setq continued nil)
5128 (setq continued (verilog-backward-token))))
5129 (setq continued nil))
5132 (defun verilog-calculate-indent ()
5133 "Calculate the indent of the current Verilog line.
5134 Examine previous lines. Once a line is found that is definitive as to the
5135 type of the current line, return that lines' indent level and its type.
5136 Return a list of two elements: (INDENT-TYPE INDENT-LEVEL)."
5138 (let* ((starting_position (point))
5140 (begin (looking-at "[ \t]*begin\\>"))
5141 (lim (save-excursion (verilog-re-search-backward "\\(\\<begin\\>\\)\\|\\(\\<module\\>\\)" nil t)))
5142 (type (catch 'nesting
5143 ;; Keep working backwards until we can figure out
5144 ;; what type of statement this is.
5145 ;; Basically we need to figure out
5146 ;; 1) if this is a continuation of the previous line;
5147 ;; 2) are we in a block scope (begin..end)
5149 ;; if we are in a comment, done.
5150 (if (verilog-in-star-comment-p)
5151 (throw 'nesting 'comment))
5153 ;; if we have a directive, done.
5154 (if (save-excursion (beginning-of-line)
5155 (and (looking-at verilog-directive-re-1)
5156 (not (or (looking-at "[ \t]*`[ou]vm_")
5157 (looking-at "[ \t]*`vmm_")))))
5158 (throw 'nesting 'directive))
5159 ;; indent structs as if there were module level
5160 (if (verilog-in-struct-p)
5161 (throw 'nesting 'block))
5163 ;; if we are in a parenthesized list, and the user likes to indent these, return.
5164 ;; unless we are in the newfangled coverpoint or constraint blocks
5166 verilog-indent-lists
5168 (not (verilog-in-coverage-p))
5171 (throw 'nesting 'block)))
5173 ;; See if we are continuing a previous line
5175 ;; trap out if we crawl off the top of the buffer
5176 (if (bobp) (throw 'nesting 'cpp))
5178 (if (verilog-continued-line-1 lim)
5181 (not (looking-at verilog-complete-reg))
5182 (verilog-continued-line-1 lim))
5183 (progn (goto-char sp)
5184 (throw 'nesting 'cexp))
5189 (not verilog-indent-begin-after-if)
5190 (looking-at verilog-no-indent-begin-re))
5193 (skip-chars-forward " \t")
5194 (throw 'nesting 'statement))
5196 (throw 'nesting 'cexp))))
5197 ;; not a continued line
5198 (goto-char starting_position))
5200 (if (looking-at "\\<else\\>")
5201 ;; search back for governing if, striding across begin..end pairs
5204 (while (verilog-re-search-backward verilog-ends-re nil 'move)
5206 ((match-end 1) ; else, we're in deep
5207 (setq elsec (1+ elsec)))
5209 (setq elsec (1- elsec))
5211 (if verilog-align-ifelse
5212 (throw 'nesting 'statement)
5213 (progn ;; back up to first word on this line
5215 (verilog-forward-syntactic-ws)
5216 (throw 'nesting 'statement)))))
5217 ((match-end 3) ; assert block
5218 (setq elsec (1- elsec))
5219 (verilog-beg-of-statement) ;; doesn't get to beginning
5220 (if (looking-at verilog-property-re)
5221 (throw 'nesting 'statement) ; We don't need an endproperty for these
5222 (throw 'nesting 'block) ;We still need a endproperty
5225 ; try to leap back to matching outward block by striding across
5226 ; indent level changing tokens then immediately
5227 ; previous line governs indentation.
5228 (let (( reg) (nest 1))
5229 ;; verilog-ends => else|if|end|join(_any|_none|)|endcase|endclass|endtable|endspecify|endfunction|endtask|endgenerate|endgroup
5231 ((match-end 4) ; end
5232 ;; Search back for matching begin
5233 (setq reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)" ))
5234 ((match-end 5) ; endcase
5235 ;; Search back for matching case
5236 (setq reg "\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" ))
5237 ((match-end 6) ; endfunction
5238 ;; Search back for matching function
5239 (setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" ))
5240 ((match-end 7) ; endtask
5241 ;; Search back for matching task
5242 (setq reg "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)" ))
5243 ((match-end 8) ; endspecify
5244 ;; Search back for matching specify
5245 (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
5246 ((match-end 9) ; endtable
5247 ;; Search back for matching table
5248 (setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" ))
5249 ((match-end 10) ; endgenerate
5250 ;; Search back for matching generate
5251 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
5252 ((match-end 11) ; joins
5253 ;; Search back for matching fork
5254 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|none\\)?\\>\\)" ))
5255 ((match-end 12) ; class
5256 ;; Search back for matching class
5257 (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
5258 ((match-end 13) ; covergroup
5259 ;; Search back for matching covergroup
5260 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" )))
5262 (while (verilog-re-search-backward reg nil 'move)
5264 ((match-end 1) ; begin
5265 (setq nest (1- nest))
5268 ((match-end 2) ; end
5269 (setq nest (1+ nest)))))
5271 (throw 'nesting (verilog-calc-1)))
5275 ;; Return type of block and indent level.
5278 (if (> par 0) ; Unclosed Parenthesis
5279 (list 'cparenexp par)
5282 (list type (verilog-case-indent-level)))
5283 ((eq type 'statement)
5284 (list type (current-column)))
5288 (list type (verilog-current-indent-level))))))))
5290 (defun verilog-wai ()
5291 "Show matching nesting block for debugging."
5294 (let* ((type (verilog-calc-1))
5296 ;; Return type of block and indent level.
5300 verilog-indent-lists
5301 (not(or (verilog-in-coverage-p)
5302 (verilog-in-struct-p)))
5307 (setq depth (verilog-case-indent-level)))
5308 ((eq type 'statement)
5309 (setq depth (current-column)))
5313 (setq depth (verilog-current-indent-level)))))
5314 (message "You are at nesting %s depth %d" type depth))))
5316 (defun verilog-calc-1 ()
5318 (let ((re (concat "\\({\\|}\\|" verilog-indent-re "\\)")))
5319 (while (verilog-re-search-backward re nil 'move)
5322 ((equal (char-after) ?\{)
5323 (if (verilog-at-constraint-p)
5324 (throw 'nesting 'block)))
5326 ((equal (char-after) ?\})
5327 (let ((there (verilog-at-close-constraint-p)))
5328 (if there ;; we are at the } that closes a constraint. Find the { that opens it
5332 (verilog-beg-of-statement)))))
5334 ((looking-at verilog-beg-block-re-ordered)
5336 ((match-end 2) ; *sigh* could be "unique case" or "priority casex"
5337 (let ((here (point)))
5338 (verilog-beg-of-statement)
5339 (if (looking-at verilog-extended-case-re)
5340 (throw 'nesting 'case)
5342 (throw 'nesting 'case))
5344 ((match-end 4) ; *sigh* could be "disable fork"
5345 (let ((here (point)))
5346 (verilog-beg-of-statement)
5347 (if (looking-at verilog-disable-fork-re)
5348 t ; this is a normal statement
5349 (progn ; or is fork, starts a new block
5351 (throw 'nesting 'block)))))
5353 ((match-end 27) ; *sigh* might be a clocking declaration
5354 (let ((here (point)))
5355 (if (verilog-in-paren)
5356 t ; this is a normal statement
5357 (progn ; or is fork, starts a new block
5359 (throw 'nesting 'block)))))
5361 ;; need to consider typedef struct here...
5362 ((looking-at "\\<class\\|struct\\|function\\|task\\>")
5363 ; *sigh* These words have an optional prefix:
5364 ; extern {virtual|protected}? function a();
5365 ; typedef class foo;
5366 ; and we don't want to confuse this with
5371 (verilog-beg-of-statement)
5372 (if (looking-at verilog-beg-block-re-ordered)
5373 (throw 'nesting 'block)
5374 (throw 'nesting 'defun)))
5376 ((looking-at "\\<property\\>")
5378 ; {assert|assume|cover} property (); are complete
5379 ; and could also be labeled: - foo: assert property
5381 ; property ID () ... needs end_property
5382 (verilog-beg-of-statement)
5383 (if (looking-at verilog-property-re)
5384 (throw 'continue 'statement) ; We don't need an endproperty for these
5385 (throw 'nesting 'block) ;We still need a endproperty
5388 (t (throw 'nesting 'block))))
5390 ((looking-at verilog-end-block-re)
5391 (verilog-leap-to-head)
5392 (if (verilog-in-case-region-p)
5394 (verilog-leap-to-case-head)
5395 (if (looking-at verilog-extended-case-re)
5396 (throw 'nesting 'case)))))
5398 ((looking-at verilog-defun-level-re)
5399 (if (looking-at verilog-defun-level-generate-only-re)
5400 (if (verilog-in-generate-region-p)
5401 (throw 'continue 'foo) ; always block in a generate - keep looking
5402 (throw 'nesting 'defun))
5403 (throw 'nesting 'defun)))
5405 ((looking-at verilog-cpp-level-re)
5406 (throw 'nesting 'cpp))
5409 (throw 'nesting 'cpp)))))
5411 (throw 'nesting 'cpp))))
5413 (defun verilog-calculate-indent-directive ()
5414 "Return indentation level for directive.
5415 For speed, the searcher looks at the last directive, not the indent
5416 of the appropriate enclosing block."
5417 (let ((base -1) ;; Indent of the line that determines our indentation
5418 (ind 0)) ;; Relative offset caused by other directives (like `endif on same line as `else)
5419 ;; Start at current location, scan back for another directive
5423 (while (and (< base 0)
5424 (verilog-re-search-backward verilog-directive-re nil t))
5425 (cond ((save-excursion (skip-chars-backward " \t") (bolp))
5426 (setq base (current-indentation))))
5427 (cond ((and (looking-at verilog-directive-end) (< base 0)) ;; Only matters when not at BOL
5428 (setq ind (- ind verilog-indent-level-directive)))
5429 ((and (looking-at verilog-directive-middle) (>= base 0)) ;; Only matters when at BOL
5430 (setq ind (+ ind verilog-indent-level-directive)))
5431 ((looking-at verilog-directive-begin)
5432 (setq ind (+ ind verilog-indent-level-directive)))))
5433 ;; Adjust indent to starting indent of critical line
5434 (setq ind (max 0 (+ ind base))))
5438 (skip-chars-forward " \t")
5439 (cond ((or (looking-at verilog-directive-middle)
5440 (looking-at verilog-directive-end))
5441 (setq ind (max 0 (- ind verilog-indent-level-directive))))))
5444 (defun verilog-leap-to-case-head ()
5447 (verilog-re-search-backward
5449 "\\(\\<randcase\\>\\|\\(\\<unique\\s-+\\|priority\\s-+\\)?\\<case[xz]?\\>\\)"
5450 "\\|\\(\\<endcase\\>\\)" )
5454 (let ((here (point)))
5455 (verilog-beg-of-statement)
5456 (unless (looking-at verilog-extended-case-re)
5458 (setq nest (1- nest)))
5460 (setq nest (1+ nest)))
5465 (defun verilog-leap-to-head ()
5466 "Move point to the head of this block.
5467 Jump from end to matching begin, from endcase to matching case, and so on."
5473 ((looking-at "\\<end\\>")
5474 ;; 1: Search back for matching begin
5475 (setq reg (concat "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|"
5476 "\\(\\<endcase\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" )))
5477 ((looking-at "\\<endtask\\>")
5478 ;; 2: Search back for matching task
5479 (setq reg "\\(\\<task\\>\\)\\|\\(\\(\\(\\<virtual\\>\\s-+\\)\\|\\(\\<protected\\>\\s-+\\)\\)+\\<task\\>\\)")
5481 ((looking-at "\\<endcase\\>")
5483 (verilog-leap-to-case-head) )
5484 (setq reg nil) ; to force skip
5487 ((looking-at "\\<join\\(_any\\|_none\\)?\\>")
5488 ;; 4: Search back for matching fork
5489 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" ))
5490 ((looking-at "\\<endclass\\>")
5491 ;; 5: Search back for matching class
5492 (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
5493 ((looking-at "\\<endtable\\>")
5494 ;; 6: Search back for matching table
5495 (setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" ))
5496 ((looking-at "\\<endspecify\\>")
5497 ;; 7: Search back for matching specify
5498 (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
5499 ((looking-at "\\<endfunction\\>")
5500 ;; 8: Search back for matching function
5501 (setq reg "\\(\\<function\\>\\)\\|\\(\\(\\(\\<virtual\\>\\s-+\\)\\|\\(\\<protected\\>\\s-+\\)\\)+\\<function\\>\\)")
5503 ;;(setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" ))
5504 ((looking-at "\\<endgenerate\\>")
5505 ;; 8: Search back for matching generate
5506 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
5507 ((looking-at "\\<endgroup\\>")
5508 ;; 10: Search back for matching covergroup
5509 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" ))
5510 ((looking-at "\\<endproperty\\>")
5511 ;; 11: Search back for matching property
5512 (setq reg "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)" ))
5513 ((looking-at verilog-uvm-end-re)
5514 ;; 12: Search back for matching sequence
5515 (setq reg (concat "\\(" verilog-uvm-begin-re "\\|" verilog-uvm-end-re "\\)")))
5516 ((looking-at verilog-ovm-end-re)
5517 ;; 12: Search back for matching sequence
5518 (setq reg (concat "\\(" verilog-ovm-begin-re "\\|" verilog-ovm-end-re "\\)")))
5519 ((looking-at verilog-vmm-end-re)
5520 ;; 12: Search back for matching sequence
5521 (setq reg (concat "\\(" verilog-vmm-begin-re "\\|" verilog-vmm-end-re "\\)")))
5522 ((looking-at "\\<endinterface\\>")
5523 ;; 12: Search back for matching interface
5524 (setq reg "\\(\\<interface\\>\\)\\|\\(\\<endinterface\\>\\)" ))
5525 ((looking-at "\\<endsequence\\>")
5526 ;; 12: Search back for matching sequence
5527 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)" ))
5528 ((looking-at "\\<endclocking\\>")
5529 ;; 12: Search back for matching clocking
5530 (setq reg "\\(\\<clocking\\)\\|\\(\\<endclocking\\>\\)" )))
5533 (if (eq nesting 'yes)
5535 (while (verilog-re-search-backward reg nil 'move)
5537 ((match-end 1) ; begin
5538 (if (looking-at "fork")
5539 (let ((here (point)))
5540 (verilog-beg-of-statement)
5541 (unless (looking-at verilog-disable-fork-re)
5543 (setq nest (1- nest))))
5544 (setq nest (1- nest)))
5546 ;; Now previous line describes syntax
5551 ((match-end 2) ; end
5552 (setq nest (1+ nest)))
5554 ;; endcase, jump to case
5556 (setq nest (1+ nest))
5558 (setq reg "\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" ))
5560 ;; join, jump to fork
5562 (setq nest (1+ nest))
5564 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" ))
5568 (verilog-re-search-backward reg nil 'move)
5569 (match-end 1)) ; task -> could be virtual and/or protected
5571 (verilog-beg-of-statement)
5573 (throw 'skip 1)))))))
5575 (defun verilog-continued-line ()
5576 "Return true if this is a continued line.
5577 Set point to where line starts."
5578 (let ((continued 't))
5579 (if (eq 0 (forward-line -1))
5582 (verilog-backward-ws&directives)
5584 (setq continued nil)
5585 (while (and continued
5587 (skip-chars-backward " \t")
5589 (setq continued (verilog-backward-token)))))
5590 (setq continued nil))
5593 (defun verilog-backward-token ()
5594 "Step backward token, returning true if this is a continued line."
5596 (verilog-backward-syntactic-ws)
5600 (;-- Anything ending in a ; is complete
5601 (= (preceding-char) ?\;)
5603 (; If a "}" is prefixed by a ";", then this is a complete statement
5604 ; i.e.: constraint foo { a = b; }
5605 (= (preceding-char) ?\})
5608 (not(verilog-at-close-constraint-p))))
5609 (;-- constraint foo { a = b }
5610 ; is a complete statement. *sigh*
5611 (= (preceding-char) ?\{)
5614 (not (verilog-at-constraint-p))))
5616 (= (preceding-char) ?\")
5618 (verilog-skip-backward-comment-or-string)
5622 (= (preceding-char) ?\])
5624 (verilog-backward-open-bracket)
5627 (;-- Could be 'case (foo)' or 'always @(bar)' which is complete
5628 ; also could be simply '@(foo)'
5630 ; (b, ... which ISN'T complete
5631 ;;;; Do we need this???
5632 (= (preceding-char) ?\))
5635 (verilog-backward-up-list 1)
5636 (verilog-backward-syntactic-ws)
5637 (let ((back (point)))
5641 ((looking-at "\\<\\(always\\(_latch\\|_ff\\|_comb\\)?\\|case\\(\\|[xz]\\)\\|for\\(\\|each\\|ever\\)\\|i\\(f\\|nitial\\)\\|repeat\\|while\\)\\>")
5642 (not (looking-at "\\<randcase\\>\\|\\<case[xz]?\\>[^:]")))
5643 ((looking-at verilog-uvm-statement-re)
5645 ((looking-at verilog-uvm-begin-re)
5647 ((looking-at verilog-uvm-end-re)
5649 ((looking-at verilog-ovm-statement-re)
5651 ((looking-at verilog-ovm-begin-re)
5653 ((looking-at verilog-ovm-end-re)
5655 ;; JBA find VMM macros
5656 ((looking-at verilog-vmm-statement-re)
5658 ((looking-at verilog-vmm-begin-re)
5660 ((looking-at verilog-vmm-end-re)
5662 ;; JBA trying to catch macro lines with no ; at end
5663 ((looking-at "\\<`")
5668 ((= (preceding-char) ?\@)
5671 (verilog-backward-token)
5672 (not (looking-at "\\<\\(always\\(_latch\\|_ff\\|_comb\\)?\\|initial\\|while\\)\\>"))))
5673 ((= (preceding-char) ?\#)
5677 (;-- any of begin|initial|while are complete statements; 'begin : foo' is also complete
5680 (while (= (preceding-char) ?\_)
5683 ((looking-at "\\<else\\>")
5685 ((looking-at verilog-behavioral-block-beg-re)
5687 ((looking-at verilog-indent-re)
5692 (verilog-backward-syntactic-ws)
5694 ((= (preceding-char) ?\:)
5696 (verilog-backward-syntactic-ws)
5698 (if (looking-at verilog-nameable-item-re )
5701 ((= (preceding-char) ?\#)
5704 ((= (preceding-char) ?\`)
5712 (defun verilog-backward-syntactic-ws ()
5713 "Move backwards putting point after first non-whitespace non-comment."
5714 (verilog-skip-backward-comments)
5715 (forward-comment (- (buffer-size))))
5717 (defun verilog-backward-syntactic-ws-quick ()
5718 "As with `verilog-backward-syntactic-ws' but uses `verilog-scan' cache."
5719 (while (cond ((bobp)
5721 ((> (skip-syntax-backward " ") 0)
5723 ((eq (preceding-char) ?\n) ;; \n's terminate // so aren't space syntax
5726 ((or (verilog-inside-comment-or-string-p (1- (point)))
5727 (verilog-inside-comment-or-string-p (point)))
5728 (re-search-backward "[/\"]" nil t) ;; Only way a comment or quote can begin
5731 (defun verilog-forward-syntactic-ws ()
5732 (verilog-skip-forward-comment-p)
5733 (forward-comment (buffer-size)))
5735 (defun verilog-backward-ws&directives (&optional bound)
5736 "Backward skip over syntactic whitespace and compiler directives for Emacs 19.
5737 Optional BOUND limits search."
5739 (let* ((bound (or bound (point-min)))
5742 (if (< bound (point))
5744 (let ((state (save-excursion (verilog-syntax-ppss))))
5746 ((nth 7 state) ;; in // comment
5747 (verilog-re-search-backward "//" nil 'move)
5748 (skip-chars-backward "/"))
5749 ((nth 4 state) ;; in /* */ comment
5750 (verilog-re-search-backward "/\*" nil 'move))))
5751 (narrow-to-region bound (point))
5752 (while (/= here (point))
5754 (verilog-skip-backward-comments)
5759 ((and verilog-highlight-translate-off
5760 (verilog-within-translate-off))
5761 (verilog-back-to-start-translate-off (point-min)))
5762 ((looking-at verilog-directive-re-1)
5766 (if p (goto-char p))))))))
5768 (defun verilog-forward-ws&directives (&optional bound)
5769 "Forward skip over syntactic whitespace and compiler directives for Emacs 19.
5770 Optional BOUND limits search."
5772 (let* ((bound (or bound (point-max)))
5775 (if (> bound (point))
5777 (let ((state (save-excursion (verilog-syntax-ppss))))
5779 ((nth 7 state) ;; in // comment
5782 (skip-chars-forward " \t\n\f")
5784 ((nth 4 state) ;; in /* */ comment
5785 (verilog-re-search-forward "\*\/\\s-*" nil 'move))))
5786 (narrow-to-region (point) bound)
5787 (while (/= here (point))
5790 (forward-comment (buffer-size))
5791 (and (looking-at "\\s-*(\\*.*\\*)\\s-*") ;; Attribute
5792 (goto-char (match-end 0)))
5795 (if (looking-at verilog-directive-re-1)
5798 (beginning-of-line 2))))))))
5800 (defun verilog-in-comment-p ()
5801 "Return true if in a star or // comment."
5802 (let ((state (save-excursion (verilog-syntax-ppss))))
5803 (or (nth 4 state) (nth 7 state))))
5805 (defun verilog-in-star-comment-p ()
5806 "Return true if in a star comment."
5807 (let ((state (save-excursion (verilog-syntax-ppss))))
5809 (nth 4 state) ; t if in a comment of style a // or b /**/
5811 (nth 7 state) ; t if in a comment of style b /**/
5814 (defun verilog-in-slash-comment-p ()
5815 "Return true if in a slash comment."
5816 (let ((state (save-excursion (verilog-syntax-ppss))))
5819 (defun verilog-in-comment-or-string-p ()
5820 "Return true if in a string or comment."
5821 (let ((state (save-excursion (verilog-syntax-ppss))))
5822 (or (nth 3 state) (nth 4 state) (nth 7 state)))) ; Inside string or comment)
5824 (defun verilog-in-attribute-p ()
5825 "Return true if point is in an attribute (* [] attribute *)."
5828 (verilog-re-search-backward "\\((\\*\\)\\|\\(\\*)\\)" nil 'move)
5829 (numberp (match-beginning 1)))))
5831 (defun verilog-in-parameter-p ()
5832 "Return true if point is in a parameter assignment #( p1=1, p2=5)."
5835 (verilog-re-search-backward "\\(#(\\)\\|\\()\\)" nil 'move)
5836 (numberp (match-beginning 1)))))
5838 (defun verilog-in-escaped-name-p ()
5839 "Return true if in an escaped name."
5842 (skip-chars-backward "^ \t\n\f")
5843 (if (equal (char-after (point) ) ?\\ )
5846 (defun verilog-in-directive-p ()
5847 "Return true if in a directive."
5850 (looking-at verilog-directive-re-1)))
5852 (defun verilog-in-parenthesis-p ()
5853 "Return true if in a ( ) expression (but not { } or [ ])."
5856 (verilog-re-search-backward "\\((\\)\\|\\()\\)" nil 'move)
5857 (numberp (match-beginning 1)))))
5859 (defun verilog-in-paren ()
5860 "Return true if in a parenthetical expression.
5861 May cache result using `verilog-syntax-ppss'."
5862 (let ((state (save-excursion (verilog-syntax-ppss))))
5863 (> (nth 0 state) 0 )))
5865 (defun verilog-in-paren-quick ()
5866 "Return true if in a parenthetical expression.
5867 Always starts from point-min, to allow inserts with hooks disabled."
5868 ;; The -quick refers to its use alongside the other -quick functions,
5869 ;; not that it's likely to be faster than verilog-in-paren.
5870 (let ((state (save-excursion (parse-partial-sexp (point-min) (point)))))
5871 (> (nth 0 state) 0 )))
5873 (defun verilog-in-struct-p ()
5874 "Return true if in a struct declaration."
5877 (if (verilog-in-paren)
5879 (verilog-backward-up-list 1)
5880 (verilog-at-struct-p)
5884 (defun verilog-in-coverage-p ()
5885 "Return true if in a constraint or coverpoint expression."
5888 (if (verilog-in-paren)
5890 (verilog-backward-up-list 1)
5891 (verilog-at-constraint-p)
5894 (defun verilog-at-close-constraint-p ()
5895 "If at the } that closes a constraint or covergroup, return true."
5897 (equal (char-after) ?\})
5901 (verilog-backward-ws&directives)
5902 (if (equal (char-before) ?\;)
5906 (defun verilog-at-constraint-p ()
5907 "If at the { of a constraint or coverpoint definition, return true, moving point to constraint."
5910 (equal (char-after) ?\{)
5912 (progn (backward-char 1)
5913 (verilog-backward-ws&directives)
5914 (equal (char-before) ?\;))))
5916 (verilog-re-search-backward "\\<constraint\\|coverpoint\\|cross\\>" nil 'move)
5920 (defun verilog-at-struct-p ()
5921 "If at the { of a struct, return true, moving point to struct."
5923 (if (and (equal (char-after) ?\{)
5924 (verilog-backward-token))
5925 (looking-at "\\<struct\\|union\\|packed\\|\\(un\\)?signed\\>")
5928 (defun verilog-parenthesis-depth ()
5929 "Return non zero if in parenthetical-expression."
5930 (save-excursion (nth 1 (verilog-syntax-ppss))))
5933 (defun verilog-skip-forward-comment-or-string ()
5934 "Return true if in a string or comment."
5935 (let ((state (save-excursion (verilog-syntax-ppss))))
5937 ((nth 3 state) ;Inside string
5938 (search-forward "\"")
5940 ((nth 7 state) ;Inside // comment
5943 ((nth 4 state) ;Inside any comment (hence /**/)
5944 (search-forward "*/"))
5948 (defun verilog-skip-backward-comment-or-string ()
5949 "Return true if in a string or comment."
5950 (let ((state (save-excursion (verilog-syntax-ppss))))
5952 ((nth 3 state) ;Inside string
5953 (search-backward "\"")
5955 ((nth 7 state) ;Inside // comment
5956 (search-backward "//")
5957 (skip-chars-backward "/")
5959 ((nth 4 state) ;Inside /* */ comment
5960 (search-backward "/*")
5965 (defun verilog-skip-backward-comments ()
5966 "Return true if a comment was skipped."
5970 (let ((state (save-excursion (verilog-syntax-ppss))))
5972 ((nth 7 state) ;Inside // comment
5973 (search-backward "//")
5974 (skip-chars-backward "/")
5975 (skip-chars-backward " \t\n\f")
5977 ((nth 4 state) ;Inside /* */ comment
5978 (search-backward "/*")
5979 (skip-chars-backward " \t\n\f")
5982 (= (char-before) ?\/)
5983 (= (char-before (1- (point))) ?\*))
5984 (goto-char (- (point) 2))
5985 t) ;; Let nth 4 state handle the rest
5987 (= (char-before) ?\))
5988 (= (char-before (1- (point))) ?\*))
5989 (goto-char (- (point) 2))
5990 (if (search-backward "(*" nil t)
5992 (skip-chars-backward " \t\n\f")
5995 (goto-char (+ (point) 2))
5998 (/= (skip-chars-backward " \t\n\f") 0))))))))
6000 (defun verilog-skip-forward-comment-p ()
6001 "If in comment, move to end and return true."
6003 (state (save-excursion (verilog-syntax-ppss)))
6005 ((nth 3 state) ;Inside string
6007 ((nth 7 state) ;Inside // comment
6011 ((nth 4 state) ;Inside /* comment
6012 (search-forward "*/")
6014 ((verilog-in-attribute-p) ;Inside (* attribute
6015 (search-forward "*)" nil t)
6018 (skip-chars-forward " \t\n\f")
6021 ((looking-at "\\/\\*")
6024 (goto-char (match-end 0))
6025 (if (search-forward "*/" nil t)
6027 (skip-chars-forward " \t\n\f")
6032 ((looking-at "(\\*")
6035 (goto-char (match-end 0))
6036 (if (search-forward "*)" nil t)
6038 (skip-chars-forward " \t\n\f")
6046 (defun verilog-indent-line-relative ()
6047 "Cheap version of indent line.
6048 Only look at a few lines to determine indent level."
6052 (if (looking-at "^[ \t]*$")
6053 (cond ;- A blank line; No need to be too smart.
6055 (setq indent-str (list 'cpp 0)))
6056 ((verilog-continued-line)
6057 (let ((sp1 (point)))
6058 (if (verilog-continued-line)
6062 (list 'statement (verilog-current-indent-level))))
6064 (setq indent-str (list 'block (verilog-current-indent-level)))))
6067 (setq indent-str (verilog-calculate-indent))))
6068 (progn (skip-chars-forward " \t")
6069 (setq indent-str (verilog-calculate-indent))))
6070 (verilog-do-indent indent-str)))
6072 (defun verilog-indent-line ()
6073 "Indent for special part of code."
6074 (verilog-do-indent (verilog-calculate-indent)))
6076 (defun verilog-do-indent (indent-str)
6077 (let ((type (car indent-str))
6078 (ind (car (cdr indent-str))))
6080 (; handle continued exp
6082 (let ((here (point)))
6083 (verilog-backward-syntactic-ws)
6086 (= (preceding-char) ?\,)
6087 (= (preceding-char) ?\])
6089 (verilog-beg-of-statement-1)
6090 (looking-at verilog-declaration-re)))
6095 (verilog-beg-of-statement-1)
6097 (if (looking-at verilog-declaration-re)
6098 (progn ;; we have multiple words
6099 (goto-char (match-end 0))
6100 (skip-chars-forward " \t")
6102 ((and verilog-indent-declaration-macros
6103 (= (following-char) ?\`))
6107 (skip-chars-forward " \t")))
6108 ((= (following-char) ?\[)
6111 (verilog-backward-up-list -1)
6112 (skip-chars-forward " \t"))))
6116 (+ (current-column) verilog-cexp-indent))))))
6118 (indent-line-to val)
6119 (if (and (not verilog-indent-lists)
6121 (verilog-pretty-declarations))
6123 ((= (preceding-char) ?\) )
6125 (let ((val (eval (cdr (assoc type verilog-indent-alist)))))
6126 (indent-line-to val)))
6130 (verilog-beg-of-statement-1)
6131 (if (and (< (point) here)
6132 (verilog-re-search-forward "=[ \\t]*" here 'move))
6133 (setq val (current-column))
6134 (setq val (eval (cdr (assoc type verilog-indent-alist)))))
6136 (indent-line-to val))))))
6138 (; handle inside parenthetical expressions
6139 (eq type 'cparenexp)
6141 (val (save-excursion
6142 (verilog-backward-up-list 1)
6144 (if verilog-indent-lists
6145 (skip-chars-forward " \t")
6146 (verilog-forward-syntactic-ws))
6150 (decl (save-excursion
6152 (verilog-forward-syntactic-ws)
6154 (looking-at verilog-declaration-re))))
6155 (indent-line-to val)
6157 (verilog-pretty-declarations))))
6159 (;-- Handle the ends
6161 (looking-at verilog-end-block-re )
6162 (verilog-at-close-constraint-p))
6163 (let ((val (if (eq type 'statement)
6164 (- ind verilog-indent-level)
6166 (indent-line-to val)))
6168 (;-- Case -- maybe line 'em up
6169 (and (eq type 'case) (not (looking-at "^[ \t]*$")))
6172 ((looking-at "\\<endcase\\>")
6173 (indent-line-to ind))
6175 (let ((val (eval (cdr (assoc type verilog-indent-alist)))))
6176 (indent-line-to val))))))
6179 (and (eq type 'defun)
6180 (looking-at verilog-zero-indent-re))
6187 (looking-at verilog-declaration-re))
6188 (verilog-indent-declaration ind))
6190 (;-- Everything else
6192 (let ((val (eval (cdr (assoc type verilog-indent-alist)))))
6193 (indent-line-to val))))
6195 (if (looking-at "[ \t]+$")
6196 (skip-chars-forward " \t"))
6197 indent-str ; Return indent data
6200 (defun verilog-current-indent-level ()
6201 "Return the indent-level of the current statement."
6205 (setq par-pos (verilog-parenthesis-depth))
6209 (setq par-pos (verilog-parenthesis-depth)))
6210 (skip-chars-forward " \t")
6213 (defun verilog-case-indent-level ()
6214 "Return the indent-level of the current statement.
6215 Do not count named blocks or case-statements."
6217 (skip-chars-forward " \t")
6219 ((looking-at verilog-named-block-re)
6221 ((and (not (looking-at verilog-extended-case-re))
6222 (looking-at "^[^:;]+[ \t]*:"))
6223 (verilog-re-search-forward ":" nil t)
6224 (skip-chars-forward " \t")
6227 (current-column)))))
6229 (defun verilog-indent-comment ()
6230 "Indent current line as comment."
6233 ((verilog-in-star-comment-p)
6235 (re-search-backward "/\\*" nil t)
6236 (1+(current-column))))
6241 (re-search-backward "//" nil t)
6242 (current-column))))))
6243 (indent-line-to stcol)
6246 (defun verilog-more-comment ()
6247 "Make more comment lines like the previous."
6251 ((verilog-in-star-comment-p)
6254 (re-search-backward "/\\*" nil t)
6255 (1+(current-column))))
6260 (re-search-backward "//" nil t)
6261 (current-column))))))
6267 (skip-chars-forward " \t")
6271 (defun verilog-comment-indent (&optional arg)
6272 "Return the column number the line should be indented to.
6273 ARG is ignored, for `comment-indent-function' compatibility."
6275 ((verilog-in-star-comment-p)
6277 (re-search-backward "/\\*" nil t)
6278 (1+(current-column))))
6283 (re-search-backward "//" nil t)
6284 (current-column)))))
6288 (defun verilog-pretty-declarations (&optional quiet)
6289 "Line up declarations around point.
6290 Be verbose about progress unless optional QUIET set."
6292 (let* ((m1 (make-marker))
6306 ; (verilog-beg-of-statement-1)
6308 (verilog-forward-syntactic-ws)
6309 (and (not (verilog-in-directive-p)) ;; could have `define input foo
6310 (looking-at verilog-declaration-re)))
6312 (if (verilog-parenthesis-depth)
6313 ;; in an argument list or parameter block
6314 (setq el (verilog-backward-up-list -1)
6317 (verilog-backward-up-list 1)
6318 (forward-line) ;; ignore ( input foo,
6319 (verilog-re-search-forward verilog-declaration-re el 'move)
6320 (goto-char (match-beginning 0))
6321 (skip-chars-backward " \t")
6323 startpos (set-marker (make-marker) start)
6326 (verilog-backward-up-list -1)
6328 (verilog-backward-syntactic-ws)
6330 endpos (set-marker (make-marker) end)
6334 (skip-chars-forward " \t")
6337 ;; in a declaration block (not in argument list)
6340 (verilog-beg-of-statement-1)
6341 (while (and (looking-at verilog-declaration-re)
6343 (skip-chars-backward " \t")
6346 (verilog-backward-syntactic-ws)
6348 (verilog-beg-of-statement-1))
6350 startpos (set-marker (make-marker) start)
6353 (verilog-end-of-statement)
6354 (setq e (point)) ;Might be on last line
6355 (verilog-forward-syntactic-ws)
6356 (while (looking-at verilog-declaration-re)
6357 (verilog-end-of-statement)
6359 (verilog-forward-syntactic-ws))
6361 endpos (set-marker (make-marker) end)
6364 (verilog-do-indent (verilog-calculate-indent))
6365 (verilog-forward-ws&directives)
6367 ;; OK, start and end are set
6368 (goto-char (marker-position startpos))
6369 (if (and (not quiet)
6370 (> (- end start) 100))
6371 (message "Lining up declarations..(please stand by)"))
6372 ;; Get the beginning of line indent first
6373 (while (progn (setq e (marker-position endpos))
6376 ((save-excursion (skip-chars-backward " \t")
6378 (verilog-forward-ws&directives)
6379 (indent-line-to base-ind)
6380 (verilog-forward-ws&directives)
6382 (verilog-re-search-forward "[ \t\n\f]" e 'move)))
6385 (verilog-re-search-forward "[ \t\n\f]" e 'move)))
6388 ;; Now find biggest prefix
6389 (setq ind (verilog-get-lineup-indent (marker-position startpos) endpos))
6390 ;; Now indent each line.
6391 (goto-char (marker-position startpos))
6392 (while (progn (setq e (marker-position endpos))
6393 (setq r (- e (point)))
6396 (unless quiet (message "%d" r))
6397 ;;(verilog-do-indent (verilog-calculate-indent)))
6398 (verilog-forward-ws&directives)
6400 ((or (and verilog-indent-declaration-macros
6401 (looking-at verilog-declaration-re-2-macro))
6402 (looking-at verilog-declaration-re-2-no-macro))
6403 (let ((p (match-end 0)))
6405 (if (verilog-re-search-forward "[[#`]" p 'move)
6409 (goto-char (marker-position m1))
6415 ((verilog-continued-line-1 (marker-position startpos))
6417 (indent-line-to ind))
6418 ((verilog-in-struct-p)
6419 ;; could have a declaration of a user defined item
6421 (verilog-end-of-statement))
6422 (t ; Must be comment or white space
6424 (verilog-forward-ws&directives)
6427 (unless quiet (message "")))))))
6429 (defun verilog-pretty-expr (&optional quiet myre)
6430 "Line up expressions around point, optionally QUIET with regexp MYRE ignored."
6432 (if (not (verilog-in-comment-or-string-p))
6434 (let ((rexp (concat "^\\s-*" verilog-complete-reg)))
6436 (if (and (not (looking-at rexp ))
6437 (looking-at verilog-assignment-operation-re)
6439 (goto-char (match-end 2))
6440 (and (not (verilog-in-attribute-p))
6441 (not (verilog-in-parameter-p))
6442 (not (verilog-in-comment-or-string-p)))))
6443 (let* ((here (point))
6449 (verilog-backward-syntactic-ws)
6451 (while (and (not (looking-at rexp ))
6452 (looking-at verilog-assignment-operation-re)
6456 (verilog-backward-syntactic-ws)
6458 ) ;Ack, need to grok `define
6464 (setq e (point)) ;Might be on last line
6465 (verilog-forward-syntactic-ws)
6468 (not (looking-at rexp ))
6469 (looking-at verilog-assignment-operation-re)
6472 (not (eq e (point)))))
6474 (verilog-forward-syntactic-ws)
6478 (endpos (set-marker (make-marker) end))
6482 (verilog-do-indent (verilog-calculate-indent))
6483 (if (and (not quiet)
6484 (> (- end start) 100))
6485 (message "Lining up expressions..(please stand by)"))
6487 ;; Set indent to minimum throughout region
6488 (while (< (point) (marker-position endpos))
6490 (verilog-just-one-space verilog-assignment-operation-re)
6492 (verilog-do-indent (verilog-calculate-indent))
6494 (verilog-forward-syntactic-ws)
6497 ;; Now find biggest prefix
6498 (setq ind (verilog-get-lineup-indent-2 verilog-assignment-operation-re start endpos))
6500 ;; Now indent each line.
6502 (while (progn (setq e (marker-position endpos))
6503 (setq r (- e (point)))
6506 (if (not quiet) (message "%d" r))
6508 ((looking-at verilog-assignment-operation-re)
6509 (goto-char (match-beginning 2))
6510 (if (not (or (verilog-in-parenthesis-p) ;; leave attributes and comparisons alone
6511 (verilog-in-coverage-p)))
6512 (if (eq (char-after) ?=)
6513 (indent-to (1+ ind)) ; line up the = of the <= with surrounding =
6517 ((verilog-continued-line-1 start)
6519 (indent-line-to ind))
6520 (t ; Must be comment or white space
6522 (verilog-forward-ws&directives)
6526 (unless quiet (message ""))
6529 (defun verilog-just-one-space (myre)
6530 "Remove extra spaces around regular expression MYRE."
6532 (if (and (not(looking-at verilog-complete-reg))
6534 (let ((p1 (match-end 1))
6540 (just-one-space)))))
6542 (defun verilog-indent-declaration (baseind)
6543 "Indent current lines as declaration.
6544 Line up the variable names based on previous declaration's indentation.
6545 BASEIND is the base indent to offset everything."
6547 (let ((pos (point-marker))
6548 (lim (save-excursion
6549 ;; (verilog-re-search-backward verilog-declaration-opener nil 'move)
6550 (verilog-re-search-backward "\\(\\<begin\\>\\)\\|\\(\\<module\\>\\)\\|\\(\\<task\\>\\)" nil 'move)
6556 (+ baseind (eval (cdr (assoc 'declaration verilog-indent-alist)))))
6557 (indent-line-to val)
6559 ;; Use previous declaration (in this module) as template.
6560 (if (or (eq 'all verilog-auto-lineup)
6561 (eq 'declarations verilog-auto-lineup))
6562 (if (verilog-re-search-backward
6563 (or (and verilog-indent-declaration-macros
6564 verilog-declaration-re-1-macro)
6565 verilog-declaration-re-1-no-macro) lim t)
6567 (goto-char (match-end 0))
6568 (skip-chars-forward " \t")
6569 (setq ind (current-column))
6573 (eval (cdr (assoc 'declaration verilog-indent-alist)))))
6574 (indent-line-to val)
6575 (if (and verilog-indent-declaration-macros
6576 (looking-at verilog-declaration-re-2-macro))
6577 (let ((p (match-end 0)))
6579 (if (verilog-re-search-forward "[[#`]" p 'move)
6583 (goto-char (marker-position m1))
6586 (if (/= (current-column) ind)
6590 (if (looking-at verilog-declaration-re-2-no-macro)
6591 (let ((p (match-end 0)))
6593 (if (verilog-re-search-forward "[[`#]" p 'move)
6597 (goto-char (marker-position m1))
6600 (if (/= (current-column) ind)
6603 (indent-to ind))))))))))
6606 (defun verilog-get-lineup-indent (b edpos)
6607 "Return the indent level that will line up several lines within the region.
6608 Region is defined by B and EDPOS."
6612 ;; Get rightmost position
6613 (while (progn (setq e (marker-position edpos))
6615 (if (verilog-re-search-forward
6616 (or (and verilog-indent-declaration-macros
6617 verilog-declaration-re-1-macro)
6618 verilog-declaration-re-1-no-macro) e 'move)
6620 (goto-char (match-end 0))
6621 (verilog-backward-syntactic-ws)
6622 (if (> (current-column) ind)
6623 (setq ind (current-column)))
6624 (goto-char (match-end 0)))))
6627 ;; No lineup-string found
6630 (verilog-backward-syntactic-ws)
6631 ;;(skip-chars-backward " \t")
6632 (1+ (current-column))))))
6634 (defun verilog-get-lineup-indent-2 (myre b edpos)
6635 "Return the indent level that will line up several lines within the region."
6639 ;; Get rightmost position
6640 (while (progn (setq e (marker-position edpos))
6642 (if (and (verilog-re-search-forward myre e 'move)
6643 (not (verilog-in-attribute-p))) ;; skip attribute exprs
6645 (goto-char (match-beginning 2))
6646 (verilog-backward-syntactic-ws)
6647 (if (> (current-column) ind)
6648 (setq ind (current-column)))
6649 (goto-char (match-end 0)))
6653 ;; No lineup-string found
6656 (skip-chars-backward " \t")
6657 (1+ (current-column))))))
6659 (defun verilog-comment-depth (type val)
6660 "A useful mode debugging aide. TYPE and VAL are comments for insertion."
6668 (if (re-search-backward " /\\* \[#-\]# \[a-zA-Z\]+ \[0-9\]+ ## \\*/" b t)
6670 (replace-match " /* -# ## */")
6674 (insert " /* ## ## */"))))
6677 (format "%s %d" type val))))
6683 (defvar verilog-str nil)
6684 (defvar verilog-all nil)
6685 (defvar verilog-pred nil)
6686 (defvar verilog-buffer-to-use nil)
6687 (defvar verilog-flag nil)
6688 (defvar verilog-toggle-completions nil
6689 "*True means \\<verilog-mode-map>\\[verilog-complete-word] should try all possible completions one by one.
6690 Repeated use of \\[verilog-complete-word] will show you all of them.
6691 Normally, when there is more than one possible completion,
6692 it displays a list of all possible completions.")
6695 (defvar verilog-type-keywords
6697 "and" "buf" "bufif0" "bufif1" "cmos" "defparam" "inout" "input"
6698 "integer" "localparam" "logic" "mailbox" "nand" "nmos" "nor" "not" "notif0"
6699 "notif1" "or" "output" "parameter" "pmos" "pull0" "pull1" "pulldown" "pullup"
6700 "rcmos" "real" "realtime" "reg" "rnmos" "rpmos" "rtran" "rtranif0"
6701 "rtranif1" "semaphore" "time" "tran" "tranif0" "tranif1" "tri" "tri0" "tri1"
6702 "triand" "trior" "trireg" "wand" "wire" "wor" "xnor" "xor"
6704 "*Keywords for types used when completing a word in a declaration or parmlist.
6705 \(integer, real, reg...)")
6707 (defvar verilog-cpp-keywords
6708 '("module" "macromodule" "primitive" "timescale" "define" "ifdef" "ifndef" "else"
6710 "*Keywords to complete when at first word of a line in declarative scope.
6711 \(initial, always, begin, assign...)
6712 The procedures and variables defined within the Verilog program
6713 will be completed at runtime and should not be added to this list.")
6715 (defvar verilog-defun-keywords
6718 "always" "always_comb" "always_ff" "always_latch" "assign"
6719 "begin" "end" "generate" "endgenerate" "module" "endmodule"
6720 "specify" "endspecify" "function" "endfunction" "initial" "final"
6721 "task" "endtask" "primitive" "endprimitive"
6723 verilog-type-keywords)
6724 "*Keywords to complete when at first word of a line in declarative scope.
6725 \(initial, always, begin, assign...)
6726 The procedures and variables defined within the Verilog program
6727 will be completed at runtime and should not be added to this list.")
6729 (defvar verilog-block-keywords
6731 "begin" "break" "case" "continue" "else" "end" "endfunction"
6732 "endgenerate" "endinterface" "endpackage" "endspecify" "endtask"
6733 "for" "fork" "if" "join" "join_any" "join_none" "repeat" "return"
6735 "*Keywords to complete when at first word of a line in behavioral scope.
6736 \(begin, if, then, else, for, fork...)
6737 The procedures and variables defined within the Verilog program
6738 will be completed at runtime and should not be added to this list.")
6740 (defvar verilog-tf-keywords
6741 '("begin" "break" "fork" "join" "join_any" "join_none" "case" "end" "endtask" "endfunction" "if" "else" "for" "while" "repeat")
6742 "*Keywords to complete when at first word of a line in a task or function.
6743 \(begin, if, then, else, for, fork.)
6744 The procedures and variables defined within the Verilog program
6745 will be completed at runtime and should not be added to this list.")
6747 (defvar verilog-case-keywords
6748 '("begin" "fork" "join" "join_any" "join_none" "case" "end" "endcase" "if" "else" "for" "repeat")
6749 "*Keywords to complete when at first word of a line in case scope.
6750 \(begin, if, then, else, for, fork...)
6751 The procedures and variables defined within the Verilog program
6752 will be completed at runtime and should not be added to this list.")
6754 (defvar verilog-separator-keywords
6755 '("else" "then" "begin")
6756 "*Keywords to complete when NOT standing at the first word of a statement.
6757 \(else, then, begin...)
6758 Variables and function names defined within the Verilog program
6759 will be completed at runtime and should not be added to this list.")
6761 (defvar verilog-gate-ios
6762 ;; All these have an implied {"input"...} at the end
6776 ("pulldown" "output")
6781 ("rtran" "inout" "inout")
6782 ("rtranif0" "inout" "inout")
6783 ("rtranif1" "inout" "inout")
6784 ("tran" "inout" "inout")
6785 ("tranif0" "inout" "inout")
6786 ("tranif1" "inout" "inout")
6789 "*Map of direction for each positional argument to each gate primitive.")
6791 (defvar verilog-gate-keywords (mapcar `car verilog-gate-ios)
6792 "*Keywords for gate primitives.")
6794 (defun verilog-string-diff (str1 str2)
6795 "Return index of first letter where STR1 and STR2 differs."
6799 (if (or (> (1+ diff) (length str1))
6800 (> (1+ diff) (length str2)))
6802 (or (equal (aref str1 diff) (aref str2 diff))
6804 (setq diff (1+ diff))))))
6806 ;; Calculate all possible completions for functions if argument is `function',
6807 ;; completions for procedures if argument is `procedure' or both functions and
6808 ;; procedures otherwise.
6810 (defun verilog-func-completion (type)
6811 "Build regular expression for module/task/function names.
6812 TYPE is 'module, 'tf for task or function, or t if unknown."
6813 (if (string= verilog-str "")
6814 (setq verilog-str "[a-zA-Z_]"))
6815 (let ((verilog-str (concat (cond
6816 ((eq type 'module) "\\<\\(module\\)\\s +")
6817 ((eq type 'tf) "\\<\\(task\\|function\\)\\s +")
6818 (t "\\<\\(task\\|function\\|module\\)\\s +"))
6819 "\\<\\(" verilog-str "[a-zA-Z0-9_.]*\\)\\>"))
6822 (if (not (looking-at verilog-defun-re))
6823 (verilog-re-search-backward verilog-defun-re nil t))
6826 ;; Search through all reachable functions
6827 (goto-char (point-min))
6828 (while (verilog-re-search-forward verilog-str (point-max) t)
6829 (progn (setq match (buffer-substring (match-beginning 2)
6831 (if (or (null verilog-pred)
6832 (funcall verilog-pred match))
6833 (setq verilog-all (cons match verilog-all)))))
6834 (if (match-beginning 0)
6835 (goto-char (match-beginning 0)))))
6837 (defun verilog-get-completion-decl (end)
6838 "Macro for searching through current declaration (var, type or const)
6839 for matches of `str' and adding the occurrence tp `all' through point END."
6840 (let ((re (or (and verilog-indent-declaration-macros
6841 verilog-declaration-re-2-macro)
6842 verilog-declaration-re-2-no-macro))
6845 (while (and (< (point) end)
6846 (verilog-re-search-forward re end t))
6847 ;; Traverse current line
6848 (setq decl-end (save-excursion (verilog-declaration-end)))
6849 (while (and (verilog-re-search-forward verilog-symbol-re decl-end t)
6850 (not (match-end 1)))
6851 (setq match (buffer-substring (match-beginning 0) (match-end 0)))
6852 (if (string-match (concat "\\<" verilog-str) match)
6853 (if (or (null verilog-pred)
6854 (funcall verilog-pred match))
6855 (setq verilog-all (cons match verilog-all)))))
6859 (defun verilog-type-completion ()
6860 "Calculate all possible completions for types."
6861 (let ((start (point))
6863 ;; Search for all reachable type declarations
6864 (while (or (verilog-beg-of-defun)
6865 (setq goon (not goon)))
6867 (if (and (< start (prog1 (save-excursion (verilog-end-of-defun)
6870 (verilog-re-search-forward
6871 "\\<type\\>\\|\\<\\(begin\\|function\\|procedure\\)\\>"
6873 (not (match-end 1)))
6874 ;; Check current type declaration
6875 (verilog-get-completion-decl start))))))
6877 (defun verilog-var-completion ()
6878 "Calculate all possible completions for variables (or constants)."
6879 (let ((start (point)))
6880 ;; Search for all reachable var declarations
6881 (verilog-beg-of-defun)
6883 ;; Check var declarations
6884 (verilog-get-completion-decl start))))
6886 (defun verilog-keyword-completion (keyword-list)
6887 "Give list of all possible completions of keywords in KEYWORD-LIST."
6889 (if (string-match (concat "\\<" verilog-str) s)
6890 (if (or (null verilog-pred)
6891 (funcall verilog-pred s))
6892 (setq verilog-all (cons s verilog-all)))))
6896 (defun verilog-completion (verilog-str verilog-pred verilog-flag)
6897 "Function passed to `completing-read', `try-completion' or `all-completions'.
6898 Called to get completion on VERILOG-STR. If VERILOG-PRED is non-nil, it
6899 must be a function to be called for every match to check if this should
6900 really be a match. If VERILOG-FLAG is t, the function returns a list of
6901 all possible completions. If VERILOG-FLAG is nil it returns a string,
6902 the longest possible completion, or t if VERILOG-STR is an exact match.
6903 If VERILOG-FLAG is 'lambda, the function returns t if VERILOG-STR is an
6904 exact match, nil otherwise."
6906 (let ((verilog-all nil))
6907 ;; Set buffer to use for searching labels. This should be set
6908 ;; within functions which use verilog-completions
6909 (set-buffer verilog-buffer-to-use)
6911 ;; Determine what should be completed
6912 (let ((state (car (verilog-calculate-indent))))
6913 (cond ((eq state 'defun)
6914 (save-excursion (verilog-var-completion))
6915 (verilog-func-completion 'module)
6916 (verilog-keyword-completion verilog-defun-keywords))
6918 ((eq state 'behavioral)
6919 (save-excursion (verilog-var-completion))
6920 (verilog-func-completion 'module)
6921 (verilog-keyword-completion verilog-defun-keywords))
6924 (save-excursion (verilog-var-completion))
6925 (verilog-func-completion 'tf)
6926 (verilog-keyword-completion verilog-block-keywords))
6929 (save-excursion (verilog-var-completion))
6930 (verilog-func-completion 'tf)
6931 (verilog-keyword-completion verilog-case-keywords))
6934 (save-excursion (verilog-var-completion))
6935 (verilog-func-completion 'tf)
6936 (verilog-keyword-completion verilog-tf-keywords))
6939 (save-excursion (verilog-var-completion))
6940 (verilog-keyword-completion verilog-cpp-keywords))
6942 ((eq state 'cparenexp)
6943 (save-excursion (verilog-var-completion)))
6946 (save-excursion (verilog-var-completion))
6947 (verilog-func-completion 'both)
6948 (verilog-keyword-completion verilog-separator-keywords))))
6950 ;; Now we have built a list of all matches. Give response to caller
6951 (verilog-completion-response))))
6953 (defun verilog-completion-response ()
6954 (cond ((or (equal verilog-flag 'lambda) (null verilog-flag))
6955 ;; This was not called by all-completions
6956 (if (null verilog-all)
6957 ;; Return nil if there was no matching label
6959 ;; Get longest string common in the labels
6960 (let* ((elm (cdr verilog-all))
6961 (match (car verilog-all))
6962 (min (length match))
6964 (if (string= match verilog-str)
6965 ;; Return t if first match was an exact match
6967 (while (not (null elm))
6968 ;; Find longest common string
6969 (if (< (setq tmp (verilog-string-diff match (car elm))) min)
6972 (setq match (substring match 0 min))))
6973 ;; Terminate with match=t if this is an exact match
6974 (if (string= (car elm) verilog-str)
6978 (setq elm (cdr elm)))))
6979 ;; If this is a test just for exact match, return nil ot t
6980 (if (and (equal verilog-flag 'lambda) (not (equal match 't)))
6983 ;; If flag is t, this was called by all-completions. Return
6984 ;; list of all possible completions
6988 (defvar verilog-last-word-numb 0)
6989 (defvar verilog-last-word-shown nil)
6990 (defvar verilog-last-completions nil)
6992 (defun verilog-complete-word ()
6993 "Complete word at current point.
6994 \(See also `verilog-toggle-completions', `verilog-type-keywords',
6995 and `verilog-separator-keywords'.)"
6997 (let* ((b (save-excursion (skip-chars-backward "a-zA-Z0-9_") (point)))
6998 (e (save-excursion (skip-chars-forward "a-zA-Z0-9_") (point)))
6999 (verilog-str (buffer-substring b e))
7000 ;; The following variable is used in verilog-completion
7001 (verilog-buffer-to-use (current-buffer))
7002 (allcomp (if (and verilog-toggle-completions
7003 (string= verilog-last-word-shown verilog-str))
7004 verilog-last-completions
7005 (all-completions verilog-str 'verilog-completion)))
7006 (match (if verilog-toggle-completions
7008 verilog-str (mapcar (lambda (elm)
7009 (cons elm 0)) allcomp)))))
7010 ;; Delete old string
7013 ;; Toggle-completions inserts whole labels
7014 (if verilog-toggle-completions
7016 ;; Update entry number in list
7017 (setq verilog-last-completions allcomp
7018 verilog-last-word-numb
7019 (if (>= verilog-last-word-numb (1- (length allcomp)))
7021 (1+ verilog-last-word-numb)))
7022 (setq verilog-last-word-shown (elt allcomp verilog-last-word-numb))
7023 ;; Display next match or same string if no match was found
7024 (if (not (null allcomp))
7025 (insert "" verilog-last-word-shown)
7026 (insert "" verilog-str)
7027 (message "(No match)")))
7028 ;; The other form of completion does not necessarily do that.
7030 ;; Insert match if found, or the original string if no match
7031 (if (or (null match) (equal match 't))
7032 (progn (insert "" verilog-str)
7033 (message "(No match)"))
7035 ;; Give message about current status of completion
7036 (cond ((equal match 't)
7037 (if (not (null (cdr allcomp)))
7038 (message "(Complete but not unique)")
7039 (message "(Sole completion)")))
7040 ;; Display buffer if the current completion didn't help
7041 ;; on completing the label.
7042 ((and (not (null (cdr allcomp))) (= (length verilog-str)
7044 (with-output-to-temp-buffer "*Completions*"
7045 (display-completion-list allcomp))
7046 ;; Wait for a key press. Then delete *Completion* window
7047 (momentary-string-display "" (point))
7048 (delete-window (get-buffer-window (get-buffer "*Completions*")))
7051 (defun verilog-show-completions ()
7052 "Show all possible completions at current point."
7054 (let* ((b (save-excursion (skip-chars-backward "a-zA-Z0-9_") (point)))
7055 (e (save-excursion (skip-chars-forward "a-zA-Z0-9_") (point)))
7056 (verilog-str (buffer-substring b e))
7057 ;; The following variable is used in verilog-completion
7058 (verilog-buffer-to-use (current-buffer))
7059 (allcomp (if (and verilog-toggle-completions
7060 (string= verilog-last-word-shown verilog-str))
7061 verilog-last-completions
7062 (all-completions verilog-str 'verilog-completion))))
7063 ;; Show possible completions in a temporary buffer.
7064 (with-output-to-temp-buffer "*Completions*"
7065 (display-completion-list allcomp))
7066 ;; Wait for a key press. Then delete *Completion* window
7067 (momentary-string-display "" (point))
7068 (delete-window (get-buffer-window (get-buffer "*Completions*")))))
7071 (defun verilog-get-default-symbol ()
7072 "Return symbol around current point as a string."
7074 (buffer-substring (progn
7075 (skip-chars-backward " \t")
7076 (skip-chars-backward "a-zA-Z0-9_")
7079 (skip-chars-forward "a-zA-Z0-9_")
7082 (defun verilog-build-defun-re (str &optional arg)
7083 "Return function/task/module starting with STR as regular expression.
7084 With optional second ARG non-nil, STR is the complete name of the instruction."
7086 (concat "^\\(function\\|task\\|module\\)[ \t]+\\(" str "\\)\\>")
7087 (concat "^\\(function\\|task\\|module\\)[ \t]+\\(" str "[a-zA-Z0-9_]*\\)\\>")))
7089 (defun verilog-comp-defun (verilog-str verilog-pred verilog-flag)
7090 "Function passed to `completing-read', `try-completion' or `all-completions'.
7091 Returns a completion on any function name based on VERILOG-STR prefix. If
7092 VERILOG-PRED is non-nil, it must be a function to be called for every match
7093 to check if this should really be a match. If VERILOG-FLAG is t, the
7094 function returns a list of all possible completions. If it is nil it
7095 returns a string, the longest possible completion, or t if VERILOG-STR is
7096 an exact match. If VERILOG-FLAG is 'lambda, the function returns t if
7097 VERILOG-STR is an exact match, nil otherwise."
7099 (let ((verilog-all nil)
7102 ;; Set buffer to use for searching labels. This should be set
7103 ;; within functions which use verilog-completions
7104 (set-buffer verilog-buffer-to-use)
7106 (let ((verilog-str verilog-str))
7107 ;; Build regular expression for functions
7108 (if (string= verilog-str "")
7109 (setq verilog-str (verilog-build-defun-re "[a-zA-Z_]"))
7110 (setq verilog-str (verilog-build-defun-re verilog-str)))
7111 (goto-char (point-min))
7113 ;; Build a list of all possible completions
7114 (while (verilog-re-search-forward verilog-str nil t)
7115 (setq match (buffer-substring (match-beginning 2) (match-end 2)))
7116 (if (or (null verilog-pred)
7117 (funcall verilog-pred match))
7118 (setq verilog-all (cons match verilog-all)))))
7120 ;; Now we have built a list of all matches. Give response to caller
7121 (verilog-completion-response))))
7123 (defun verilog-goto-defun ()
7124 "Move to specified Verilog module/interface/task/function.
7125 The default is a name found in the buffer around point.
7126 If search fails, other files are checked based on
7127 `verilog-library-flags'."
7129 (let* ((default (verilog-get-default-symbol))
7130 ;; The following variable is used in verilog-comp-function
7131 (verilog-buffer-to-use (current-buffer))
7132 (label (if (not (string= default ""))
7133 ;; Do completion with default
7134 (completing-read (concat "Goto-Label: (default "
7136 'verilog-comp-defun nil nil "")
7137 ;; There is no default value. Complete without it
7138 (completing-read "Goto-Label: "
7139 'verilog-comp-defun nil nil "")))
7141 ;; Make sure library paths are correct, in case need to resolve module
7142 (verilog-auto-reeval-locals)
7143 (verilog-getopt-flags)
7144 ;; If there was no response on prompt, use default value
7145 (if (string= label "")
7146 (setq label default))
7147 ;; Goto right place in buffer if label is not an empty string
7148 (or (string= label "")
7151 (goto-char (point-min))
7153 (re-search-forward (verilog-build-defun-re label t) nil t)))
7156 (beginning-of-line))
7158 (verilog-goto-defun-file label))))
7160 ;; Eliminate compile warning
7161 (defvar occur-pos-list)
7163 (defun verilog-showscopes ()
7164 "List all scopes in this module."
7166 (let ((buffer (current-buffer))
7170 (prevpos (point-min))
7171 (final-context-start (make-marker))
7172 (regexp "\\(module\\s-+\\w+\\s-*(\\)\\|\\(\\w+\\s-+\\w+\\s-*(\\)"))
7173 (with-output-to-temp-buffer "*Occur*"
7175 (message (format "Searching for %s ..." regexp))
7176 ;; Find next match, but give up if prev match was at end of buffer.
7177 (while (and (not (= prevpos (point-max)))
7178 (verilog-re-search-forward regexp nil t))
7179 (goto-char (match-beginning 0))
7182 (setq linenum (+ linenum (count-lines prevpos (point)))))
7183 (setq prevpos (point))
7184 (goto-char (match-end 0))
7185 (let* ((start (save-excursion
7186 (goto-char (match-beginning 0))
7187 (forward-line (if (< nlines 0) nlines (- nlines)))
7189 (end (save-excursion
7190 (goto-char (match-end 0))
7192 (forward-line (1+ nlines))
7195 (tag (format "%3d" linenum))
7196 (empty (make-string (length tag) ?\ ))
7199 (setq tem (make-marker))
7200 (set-marker tem (point))
7201 (set-buffer standard-output)
7202 (setq occur-pos-list (cons tem occur-pos-list))
7203 (or first (zerop nlines)
7204 (insert "--------\n"))
7206 (insert-buffer-substring buffer start end)
7207 (backward-char (- end start))
7208 (setq tem (if (< nlines 0) (- nlines) nlines))
7212 (setq tem (1- tem)))
7213 (let ((this-linenum linenum))
7214 (set-marker final-context-start
7215 (+ (point) (- (match-end 0) (match-beginning 0))))
7216 (while (< (point) final-context-start)
7218 (setq tag (format "%3d" this-linenum)))
7219 (insert tag ?:)))))))
7220 (set-buffer-modified-p nil))))
7223 ;; Highlight helper functions
7224 (defconst verilog-directive-regexp "\\(translate\\|coverage\\|lint\\)_")
7225 (defun verilog-within-translate-off ()
7226 "Return point if within translate-off region, else nil."
7227 (and (save-excursion
7229 (concat "//\\s-*.*\\s-*" verilog-directive-regexp "\\(on\\|off\\)\\>")
7231 (equal "off" (match-string 2))
7234 (defun verilog-start-translate-off (limit)
7235 "Return point before translate-off directive if before LIMIT, else nil."
7236 (when (re-search-forward
7237 (concat "//\\s-*.*\\s-*" verilog-directive-regexp "off\\>")
7239 (match-beginning 0)))
7241 (defun verilog-back-to-start-translate-off (limit)
7242 "Return point before translate-off directive if before LIMIT, else nil."
7243 (when (re-search-backward
7244 (concat "//\\s-*.*\\s-*" verilog-directive-regexp "off\\>")
7246 (match-beginning 0)))
7248 (defun verilog-end-translate-off (limit)
7249 "Return point after translate-on directive if before LIMIT, else nil."
7251 (re-search-forward (concat
7252 "//\\s-*.*\\s-*" verilog-directive-regexp "on\\>") limit t))
7254 (defun verilog-match-translate-off (limit)
7255 "Match a translate-off block, setting `match-data' and returning t, else nil.
7256 Bound search by LIMIT."
7257 (when (< (point) limit)
7258 (let ((start (or (verilog-within-translate-off)
7259 (verilog-start-translate-off limit)))
7260 (case-fold-search t))
7262 (let ((end (or (verilog-end-translate-off limit) limit)))
7263 (set-match-data (list start end))
7264 (goto-char end))))))
7266 (defun verilog-font-lock-match-item (limit)
7267 "Match, and move over, any declaration item after point.
7268 Bound search by LIMIT. Adapted from
7269 `font-lock-match-c-style-declaration-item-and-skip-to-next'."
7272 (narrow-to-region (point-min) limit)
7274 (when (looking-at "\\s-*\\([a-zA-Z]\\w*\\)")
7276 (goto-char (match-end 1))
7277 ;; move to next item
7278 (if (looking-at "\\(\\s-*,\\)")
7279 (goto-char (match-end 1))
7284 ;; Added by Subbu Meiyappan for Header
7286 (defun verilog-header ()
7287 "Insert a standard Verilog file header.
7288 See also `verilog-sk-header' for an alternative format."
7290 (let ((start (point)))
7292 //-----------------------------------------------------------------------------
7294 // Project : <project>
7295 //-----------------------------------------------------------------------------
7296 // File : <filename>
7297 // Author : <author>
7298 // Created : <credate>
7299 // Last modified : <moddate>
7300 //-----------------------------------------------------------------------------
7303 //-----------------------------------------------------------------------------
7304 // Copyright (c) <copydate> by <company> This model is the confidential and
7305 // proprietary property of <company> and the possession or use of this
7306 // file requires a written license from <company>.
7307 //------------------------------------------------------------------------------
7308 // Modification history :
7310 //-----------------------------------------------------------------------------
7314 (search-forward "<filename>")
7315 (replace-match (buffer-name) t t)
7316 (search-forward "<author>") (replace-match "" t t)
7317 (insert (user-full-name))
7318 (insert " <" (user-login-name) "@" (system-name) ">")
7319 (search-forward "<credate>") (replace-match "" t t)
7320 (verilog-insert-date)
7321 (search-forward "<moddate>") (replace-match "" t t)
7322 (verilog-insert-date)
7323 (search-forward "<copydate>") (replace-match "" t t)
7324 (verilog-insert-year)
7325 (search-forward "<modhist>") (replace-match "" t t)
7326 (verilog-insert-date)
7327 (insert " : created")
7330 (setq string (read-string "title: "))
7331 (search-forward "<title>")
7332 (replace-match string t t)
7333 (setq string (read-string "project: " verilog-project))
7334 (setq verilog-project string)
7335 (search-forward "<project>")
7336 (replace-match string t t)
7337 (setq string (read-string "Company: " verilog-company))
7338 (setq verilog-company string)
7339 (search-forward "<company>")
7340 (replace-match string t t)
7341 (search-forward "<company>")
7342 (replace-match string t t)
7343 (search-forward "<company>")
7344 (replace-match string t t)
7345 (search-backward "<description>")
7346 (replace-match "" t t))))
7348 ;; verilog-header Uses the verilog-insert-date function
7350 (defun verilog-insert-date ()
7351 "Insert date from the system."
7353 (if verilog-date-scientific-format
7354 (insert (format-time-string "%Y/%m/%d"))
7355 (insert (format-time-string "%d.%m.%Y"))))
7357 (defun verilog-insert-year ()
7358 "Insert year from the system."
7360 (insert (format-time-string "%Y")))
7364 ;; Signal list parsing
7367 ;; Elements of a signal list
7368 (defsubst verilog-sig-new (name bits comment mem enum signed type multidim modport)
7369 (list name bits comment mem enum signed type multidim modport))
7370 (defsubst verilog-sig-name (sig)
7372 (defsubst verilog-sig-bits (sig)
7374 (defsubst verilog-sig-comment (sig)
7376 (defsubst verilog-sig-memory (sig)
7378 (defsubst verilog-sig-enum (sig)
7380 (defsubst verilog-sig-signed (sig)
7382 (defsubst verilog-sig-type (sig)
7384 (defsubst verilog-sig-multidim (sig)
7386 (defsubst verilog-sig-multidim-string (sig)
7387 (if (verilog-sig-multidim sig)
7388 (let ((str "") (args (verilog-sig-multidim sig)))
7390 (setq str (concat str (car args)))
7391 (setq args (cdr args)))
7393 (defsubst verilog-sig-modport (sig)
7395 (defsubst verilog-sig-width (sig)
7396 (verilog-make-width-expression (verilog-sig-bits sig)))
7398 (defsubst verilog-alw-new (outputs-del outputs-imm temps inputs)
7399 (list outputs-del outputs-imm temps inputs))
7400 (defsubst verilog-alw-get-outputs-delayed (sigs)
7402 (defsubst verilog-alw-get-outputs-immediate (sigs)
7404 (defsubst verilog-alw-get-temps (sigs)
7406 (defsubst verilog-alw-get-inputs (sigs)
7408 (defsubst verilog-alw-get-uses-delayed (sigs)
7411 (defsubst verilog-modi-new (name fob pt type)
7412 (vector name fob pt type))
7413 (defsubst verilog-modi-name (modi)
7415 (defsubst verilog-modi-file-or-buffer (modi)
7417 (defsubst verilog-modi-get-point (modi)
7419 (defsubst verilog-modi-get-type (modi) ;; "module" or "interface"
7421 (defsubst verilog-modi-get-decls (modi)
7422 (verilog-modi-cache-results modi 'verilog-read-decls))
7423 (defsubst verilog-modi-get-sub-decls (modi)
7424 (verilog-modi-cache-results modi 'verilog-read-sub-decls))
7426 ;; Signal reading for given module
7427 ;; Note these all take modi's - as returned from verilog-modi-current
7428 (defsubst verilog-decls-new (out inout in vars unuseds assigns consts gparams interfaces)
7429 (vector out inout in vars unuseds assigns consts gparams interfaces))
7430 (defsubst verilog-decls-get-outputs (decls)
7432 (defsubst verilog-decls-get-inouts (decls)
7434 (defsubst verilog-decls-get-inputs (decls)
7436 (defsubst verilog-decls-get-vars (decls)
7438 ;;(defsubst verilog-decls-get-unused (decls)
7440 (defsubst verilog-decls-get-assigns (decls)
7442 (defsubst verilog-decls-get-consts (decls)
7444 (defsubst verilog-decls-get-gparams (decls)
7446 (defsubst verilog-decls-get-interfaces (decls)
7449 (defsubst verilog-subdecls-new (out inout in intf intfd)
7450 (vector out inout in intf intfd))
7451 (defsubst verilog-subdecls-get-outputs (subdecls)
7453 (defsubst verilog-subdecls-get-inouts (subdecls)
7455 (defsubst verilog-subdecls-get-inputs (subdecls)
7457 (defsubst verilog-subdecls-get-interfaces (subdecls)
7459 (defsubst verilog-subdecls-get-interfaced (subdecls)
7462 (defun verilog-signals-not-in (in-list not-list)
7463 "Return list of signals in IN-LIST that aren't also in NOT-LIST.
7464 Also remove any duplicates in IN-LIST.
7465 Signals must be in standard (base vector) form."
7466 ;; This function is hot, so implemented as O(1)
7467 (cond ((eval-when-compile (fboundp 'make-hash-table))
7468 (let ((ht (make-hash-table :test 'equal :rehash-size 4.0))
7471 (puthash (car (car not-list)) t ht)
7472 (setq not-list (cdr not-list)))
7474 (when (not (gethash (car (car in-list)) ht))
7475 (setq out-list (cons (car in-list) out-list))
7476 (puthash (car (car in-list)) t ht))
7477 (setq in-list (cdr in-list)))
7478 (nreverse out-list)))
7479 ;; Slower Fallback if no hash tables (pre Emacs 21.1/XEmacs 21.4)
7483 (if (not (or (assoc (car (car in-list)) not-list)
7484 (assoc (car (car in-list)) out-list)))
7485 (setq out-list (cons (car in-list) out-list)))
7486 (setq in-list (cdr in-list)))
7487 (nreverse out-list)))))
7488 ;;(verilog-signals-not-in '(("A" "") ("B" "") ("DEL" "[2:3]")) '(("DEL" "") ("EXT" "")))
7490 (defun verilog-signals-memory (in-list)
7491 "Return list of signals in IN-LIST that are memorized (multidimensional)."
7494 (if (nth 3 (car in-list))
7495 (setq out-list (cons (car in-list) out-list)))
7496 (setq in-list (cdr in-list)))
7498 ;;(verilog-signals-memory '(("A" nil nil "[3:0]")) '(("B" nil nil nil)))
7500 (defun verilog-signals-sort-compare (a b)
7501 "Compare signal A and B for sorting."
7502 (string< (car a) (car b)))
7504 (defun verilog-signals-not-params (in-list)
7505 "Return list of signals in IN-LIST that aren't parameters or numeric constants."
7508 (unless (boundp (intern (concat "vh-" (car (car in-list)))))
7509 (setq out-list (cons (car in-list) out-list)))
7510 (setq in-list (cdr in-list)))
7511 (nreverse out-list)))
7513 (defun verilog-signals-combine-bus (in-list)
7514 "Return a list of signals in IN-LIST, with buses combined.
7515 Duplicate signals are also removed. For example A[2] and A[1] become A[2:1]."
7518 sig highbit lowbit ; Temp information about current signal
7519 sv-name sv-highbit sv-lowbit ; Details about signal we are forming
7520 sv-comment sv-memory sv-enum sv-signed sv-type sv-multidim sv-busstring
7523 ;; Shove signals so duplicated signals will be adjacent
7524 (setq in-list (sort in-list `verilog-signals-sort-compare))
7526 (setq sig (car in-list))
7527 ;; No current signal; form from existing details
7529 (setq sv-name (verilog-sig-name sig)
7532 sv-comment (verilog-sig-comment sig)
7533 sv-memory (verilog-sig-memory sig)
7534 sv-enum (verilog-sig-enum sig)
7535 sv-signed (verilog-sig-signed sig)
7536 sv-type (verilog-sig-type sig)
7537 sv-multidim (verilog-sig-multidim sig)
7538 sv-modport (verilog-sig-modport sig)
7541 ;; Extract bus details
7542 (setq bus (verilog-sig-bits sig))
7543 (setq bus (and bus (verilog-simplify-range-expression bus)))
7545 (or (and (string-match "\\[\\([0-9]+\\):\\([0-9]+\\)\\]" bus)
7546 (setq highbit (string-to-number (match-string 1 bus))
7547 lowbit (string-to-number
7548 (match-string 2 bus))))
7549 (and (string-match "\\[\\([0-9]+\\)\\]" bus)
7550 (setq highbit (string-to-number (match-string 1 bus))
7552 ;; Combine bits in bus
7554 (setq sv-highbit (max highbit sv-highbit)
7555 sv-lowbit (min lowbit sv-lowbit))
7556 (setq sv-highbit highbit
7559 ;; String, probably something like `preproc:0
7560 (setq sv-busstring bus)))
7561 ;; Peek ahead to next signal
7562 (setq in-list (cdr in-list))
7563 (setq sig (car in-list))
7564 (cond ((and sig (equal sv-name (verilog-sig-name sig)))
7565 ;; Combine with this signal
7566 (when (and sv-busstring
7567 (not (equal sv-busstring (verilog-sig-bits sig))))
7568 (when nil ;; Debugging
7569 (message (concat "Warning, can't merge into single bus "
7571 ", the AUTOs may be wrong")))
7572 (setq buswarn ", Couldn't Merge"))
7573 (if (verilog-sig-comment sig) (setq combo ", ..."))
7574 (setq sv-memory (or sv-memory (verilog-sig-memory sig))
7575 sv-enum (or sv-enum (verilog-sig-enum sig))
7576 sv-signed (or sv-signed (verilog-sig-signed sig))
7577 sv-type (or sv-type (verilog-sig-type sig))
7578 sv-multidim (or sv-multidim (verilog-sig-multidim sig))
7579 sv-modport (or sv-modport (verilog-sig-modport sig))))
7580 ;; Doesn't match next signal, add to queue, zero in prep for next
7581 ;; Note sig may also be nil for the last signal in the list
7584 (cons (verilog-sig-new
7588 (concat "[" (int-to-string sv-highbit) ":"
7589 (int-to-string sv-lowbit) "]")))
7590 (concat sv-comment combo buswarn)
7591 sv-memory sv-enum sv-signed sv-type sv-multidim sv-modport)
7597 (defun verilog-sig-tieoff (sig &optional no-width)
7598 "Return tieoff expression for given SIG, with appropriate width.
7599 Ignore width if optional NO-WIDTH is set."
7600 (let* ((width (if no-width nil (verilog-sig-width sig))))
7602 (if (and verilog-active-low-regexp
7603 (string-match verilog-active-low-regexp (verilog-sig-name sig)))
7607 ((string-match "^[0-9]+$" width)
7608 (concat width (if (verilog-sig-signed sig) "'sh0" "'h0")))
7610 (concat "{" width "{1'b0}}"))))))
7613 ;; Port/Wire/Etc Reading
7616 (defun verilog-read-inst-backward-name ()
7617 "Internal. Move point back to beginning of inst-name."
7618 (verilog-backward-open-paren)
7621 (verilog-re-search-backward-quick "\\()\\|\\b[a-zA-Z0-9`_\$]\\|\\]\\)" nil nil) ; ] isn't word boundary
7622 (cond ((looking-at ")")
7623 (verilog-backward-open-paren))
7624 (t (setq done t)))))
7625 (while (looking-at "\\]")
7626 (verilog-backward-open-bracket)
7627 (verilog-re-search-backward-quick "\\(\\b[a-zA-Z0-9`_\$]\\|\\]\\)" nil nil))
7628 (skip-chars-backward "a-zA-Z0-9`_$"))
7630 (defun verilog-read-inst-module-matcher ()
7631 "Set match data 0 with module_name when point is inside instantiation."
7632 (verilog-read-inst-backward-name)
7633 ;; Skip over instantiation name
7634 (verilog-re-search-backward-quick "\\(\\b[a-zA-Z0-9`_\$]\\|)\\)" nil nil) ; ) isn't word boundary
7635 ;; Check for parameterized instantiations
7636 (when (looking-at ")")
7637 (verilog-backward-open-paren)
7638 (verilog-re-search-backward-quick "\\b[a-zA-Z0-9`_\$]" nil nil))
7639 (skip-chars-backward "a-zA-Z0-9'_$")
7640 (looking-at "[a-zA-Z0-9`_\$]+")
7641 ;; Important: don't use match string, this must work with Emacs 19 font-lock on
7642 (buffer-substring-no-properties (match-beginning 0) (match-end 0))
7643 ;; Caller assumes match-beginning/match-end is still set
7646 (defun verilog-read-inst-module ()
7647 "Return module_name when point is inside instantiation."
7649 (verilog-read-inst-module-matcher)))
7651 (defun verilog-read-inst-name ()
7652 "Return instance_name when point is inside instantiation."
7654 (verilog-read-inst-backward-name)
7655 (looking-at "[a-zA-Z0-9`_\$]+")
7656 ;; Important: don't use match string, this must work with Emacs 19 font-lock on
7657 (buffer-substring-no-properties (match-beginning 0) (match-end 0))))
7659 (defun verilog-read-module-name ()
7660 "Return module name when after its ( or ;."
7662 (re-search-backward "[(;]")
7663 ;; Due to "module x import y (" we must search for declaration begin
7664 (verilog-re-search-backward-quick verilog-defun-re nil nil)
7665 (goto-char (match-end 0))
7666 (verilog-re-search-forward-quick "\\b[a-zA-Z0-9`_\$]+" nil nil)
7667 ;; Important: don't use match string, this must work with Emacs 19 font-lock on
7668 (verilog-symbol-detick
7669 (buffer-substring-no-properties (match-beginning 0) (match-end 0)) t)))
7671 (defun verilog-read-inst-param-value ()
7672 "Return list of parameters and values when point is inside instantiation."
7674 (verilog-read-inst-backward-name)
7675 ;; Skip over instantiation name
7676 (verilog-re-search-backward-quick "\\(\\b[a-zA-Z0-9`_\$]\\|)\\)" nil nil) ; ) isn't word boundary
7677 ;; If there are parameterized instantiations
7678 (when (looking-at ")")
7679 (let ((end-pt (point))
7681 param-name paren-beg-pt param-value)
7682 (verilog-backward-open-paren)
7683 (while (verilog-re-search-forward-quick "\\." end-pt t)
7684 (verilog-re-search-forward-quick "\\([a-zA-Z0-9`_\$]\\)" nil nil)
7685 (skip-chars-backward "a-zA-Z0-9'_$")
7686 (looking-at "[a-zA-Z0-9`_\$]+")
7687 (setq param-name (buffer-substring-no-properties
7688 (match-beginning 0) (match-end 0)))
7689 (verilog-re-search-forward-quick "(" nil nil)
7690 (setq paren-beg-pt (point))
7691 (verilog-forward-close-paren)
7692 (setq param-value (verilog-string-remove-spaces
7693 (buffer-substring-no-properties
7694 paren-beg-pt (1- (point)))))
7695 (setq params (cons (list param-name param-value) params)))
7698 (defun verilog-read-auto-params (num-param &optional max-param)
7699 "Return parameter list inside auto.
7700 Optional NUM-PARAM and MAX-PARAM check for a specific number of parameters."
7703 ;; /*AUTOPUNT("parameter", "parameter")*/
7704 (search-backward "(")
7705 (while (looking-at "(?\\s *\"\\([^\"]*\\)\"\\s *,?")
7706 (setq olist (cons (match-string 1) olist))
7707 (goto-char (match-end 0))))
7708 (or (eq nil num-param)
7709 (<= num-param (length olist))
7710 (error "%s: Expected %d parameters" (verilog-point-text) num-param))
7711 (if (eq max-param nil) (setq max-param num-param))
7712 (or (eq nil max-param)
7713 (>= max-param (length olist))
7714 (error "%s: Expected <= %d parameters" (verilog-point-text) max-param))
7717 (defun verilog-read-decls ()
7718 "Compute signal declaration information for the current module at point.
7719 Return a array of [outputs inouts inputs wire reg assign const]."
7720 (let ((end-mod-point (or (verilog-get-end-of-defun t) (point-max)))
7721 (functask 0) (paren 0) (sig-paren 0) (v2kargs-ok t)
7723 sigs-in sigs-out sigs-inout sigs-var sigs-assign sigs-const
7724 sigs-gparam sigs-intf
7725 vec expect-signal keywd newsig rvalue enum io signed typedefed multidim
7728 (verilog-beg-of-defun-quick)
7729 (setq sigs-const (verilog-read-auto-constants (point) end-mod-point))
7730 (while (< (point) end-mod-point)
7731 ;;(if dbg (setq dbg (concat dbg (format "Pt %s Vec %s C%c Kwd'%s'\n" (point) vec (following-char) keywd))))
7734 (if (looking-at "[^\n]*synopsys\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
7735 (setq enum (match-string 1)))
7736 (search-forward "\n"))
7737 ((looking-at "/\\*")
7739 (if (looking-at "[^\n]*synopsys\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
7740 (setq enum (match-string 1)))
7741 (or (search-forward "*/")
7742 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
7743 ((looking-at "(\\*")
7744 ;; To advance past either "(*)" or "(* ... *)" don't forward past first *
7746 (or (search-forward "*)")
7747 (error "%s: Unmatched (* *), at char %d" (verilog-point-text) (point))))
7748 ((eq ?\" (following-char))
7749 (or (re-search-forward "[^\\]\"" nil t) ;; don't forward-char first, since we look for a non backslash first
7750 (error "%s: Unmatched quotes, at char %d" (verilog-point-text) (point))))
7751 ((eq ?\; (following-char))
7752 (setq vec nil io nil expect-signal nil newsig nil paren 0 rvalue nil
7753 v2kargs-ok nil in-modport nil ign-prop nil)
7755 ((eq ?= (following-char))
7756 (setq rvalue t newsig nil)
7758 ((and (eq ?, (following-char))
7759 (eq paren sig-paren))
7762 ;; ,'s can occur inside {} & funcs
7763 ((looking-at "[{(]")
7764 (setq paren (1+ paren))
7766 ((looking-at "[})]")
7767 (setq paren (1- paren))
7769 (when (< paren sig-paren)
7770 (setq expect-signal nil))) ; ) that ends variables inside v2k arg list
7771 ((looking-at "\\s-*\\(\\[[^]]+\\]\\)")
7772 (goto-char (match-end 0))
7773 (cond (newsig ; Memory, not just width. Patch last signal added's memory (nth 3)
7774 (setcar (cdr (cdr (cdr newsig)))
7775 (if (verilog-sig-memory newsig)
7776 (concat (verilog-sig-memory newsig) (match-string 1))
7778 (vec ;; Multidimensional
7779 (setq multidim (cons vec multidim))
7780 (setq vec (verilog-string-replace-matches
7781 "\\s-+" "" nil nil (match-string 1))))
7783 (setq vec (verilog-string-replace-matches
7784 "\\s-+" "" nil nil (match-string 1))))))
7785 ;; Normal or escaped identifier -- note we remember the \ if escaped
7786 ((looking-at "\\s-*\\([a-zA-Z0-9`_$]+\\|\\\\[^ \t\n\f]+\\)")
7787 (goto-char (match-end 0))
7788 (setq keywd (match-string 1))
7789 (when (string-match "^\\\\" (match-string 1))
7790 (setq keywd (concat keywd " "))) ;; Escaped ID needs space at end
7791 ;; Add any :: package names to same identifier
7792 (while (looking-at "\\s-*::\\s-*\\([a-zA-Z0-9`_$]+\\|\\\\[^ \t\n\f]+\\)")
7793 (goto-char (match-end 0))
7794 (setq keywd (concat keywd "::" (match-string 1)))
7795 (when (string-match "^\\\\" (match-string 1))
7796 (setq keywd (concat keywd " ")))) ;; Escaped ID needs space at end
7797 (cond ((equal keywd "input")
7798 (setq vec nil enum nil rvalue nil newsig nil signed nil typedefed nil multidim nil sig-paren paren
7799 expect-signal 'sigs-in io t modport nil))
7800 ((equal keywd "output")
7801 (setq vec nil enum nil rvalue nil newsig nil signed nil typedefed nil multidim nil sig-paren paren
7802 expect-signal 'sigs-out io t modport nil))
7803 ((equal keywd "inout")
7804 (setq vec nil enum nil rvalue nil newsig nil signed nil typedefed nil multidim nil sig-paren paren
7805 expect-signal 'sigs-inout io t modport nil))
7806 ((equal keywd "parameter")
7807 (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren
7808 expect-signal 'sigs-gparam io t modport nil))
7809 ((member keywd '("wire"
7810 "tri" "tri0" "tri1" "triand" "trior" "wand" "wor"
7812 "byte" "shortint" "int" "longint" "integer" "time"
7814 "shortreal" "real" "realtime"
7815 "string" "event" "chandle"))
7816 (unless io (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren
7817 expect-signal 'sigs-var modport nil)))
7818 ((equal keywd "assign")
7819 (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren
7820 expect-signal 'sigs-assign modport nil))
7821 ((member keywd '("supply0" "supply1" "supply"
7822 "localparam" "genvar"))
7823 (unless io (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren
7824 expect-signal 'sigs-const modport nil)))
7825 ((member keywd '("signed" "unsigned"))
7826 (setq signed keywd))
7827 ((member keywd '("assert" "assume" "cover" "expect" "restrict"))
7829 ((member keywd '("class" "clocking" "covergroup" "function"
7830 "property" "randsequence" "sequence" "task"))
7832 (setq functask (1+ functask))))
7833 ((member keywd '("endclass" "endclocking" "endgroup" "endfunction"
7834 "endproperty" "endsequence" "endtask"))
7835 (setq functask (1- functask)))
7836 ((equal keywd "modport")
7837 (setq in-modport t))
7838 ;; Ifdef? Ignore name of define
7839 ((member keywd '("`ifdef" "`ifndef" "`elsif"))
7842 ((verilog-typedef-name-p keywd)
7843 (setq typedefed keywd))
7844 ;; Interface with optional modport in v2k arglist?
7845 ;; Skip over parsing modport, and take the interface name as the type
7849 (looking-at "\\s-*\\(\\.\\(\\s-*[a-zA-Z`_$][a-zA-Z0-9`_$]*\\)\\|\\)\\s-*[a-zA-Z`_$][a-zA-Z0-9`_$]*"))
7850 (when (match-end 2) (goto-char (match-end 2)))
7851 (setq vec nil enum nil rvalue nil newsig nil signed nil typedefed keywd multidim nil sig-paren paren
7852 expect-signal 'sigs-intf io t modport (match-string 2)))
7853 ;; Ignore dotted LHS assignments: "assign foo.bar = z;"
7854 ((looking-at "\\s-*\\.")
7855 (goto-char (match-end 0))
7857 (setq expect-signal nil)))
7858 ;; New signal, maybe?
7863 (not (member keywd verilog-keywords)))
7864 ;; Add new signal to expect-signal's variable
7865 (setq newsig (verilog-sig-new keywd vec nil nil enum signed typedefed multidim modport))
7866 (set expect-signal (cons newsig
7867 (symbol-value expect-signal))))))
7870 (skip-syntax-forward " "))
7872 (verilog-decls-new (nreverse sigs-out)
7873 (nreverse sigs-inout)
7877 (nreverse sigs-assign)
7878 (nreverse sigs-const)
7879 (nreverse sigs-gparam)
7880 (nreverse sigs-intf)))))
7882 (defvar verilog-read-sub-decls-in-interfaced nil
7883 "For `verilog-read-sub-decls', process next signal as under interfaced block.")
7885 (defvar verilog-read-sub-decls-gate-ios nil
7886 "For `verilog-read-sub-decls', gate IO pins remaining, nil if non-primitive.")
7889 ;; Prevent compile warnings; these are let's, not globals
7890 ;; Do not remove the eval-when-compile
7891 ;; - we want a error when we are debugging this code if they are refed.
7896 (defvar sigs-intfd))
7898 (defun verilog-read-sub-decls-sig (submoddecls comment port sig vec multidim)
7899 "For `verilog-read-sub-decls-line', add a signal."
7900 ;; sig eq t to indicate .name syntax
7901 ;;(message "vrsds: %s(%S)" port sig)
7902 (let ((dotname (eq sig t))
7905 (setq port (verilog-symbol-detick-denumber port))
7906 (setq sig (if dotname port (verilog-symbol-detick-denumber sig)))
7907 (if vec (setq vec (verilog-symbol-detick-denumber vec)))
7908 (if multidim (setq multidim (mapcar `verilog-symbol-detick-denumber multidim)))
7909 (unless (or (not sig)
7910 (equal sig "")) ;; Ignore .foo(1'b1) assignments
7911 (cond ((or (setq portdata (assoc port (verilog-decls-get-inouts submoddecls)))
7912 (equal "inout" verilog-read-sub-decls-gate-ios))
7914 (cons (verilog-sig-new
7916 (if dotname (verilog-sig-bits portdata) vec)
7917 (concat "To/From " comment)
7918 (verilog-sig-memory portdata)
7920 (verilog-sig-signed portdata)
7921 (verilog-sig-type portdata)
7924 ((or (setq portdata (assoc port (verilog-decls-get-outputs submoddecls)))
7925 (equal "output" verilog-read-sub-decls-gate-ios))
7927 (cons (verilog-sig-new
7929 (if dotname (verilog-sig-bits portdata) vec)
7930 (concat "From " comment)
7931 (verilog-sig-memory portdata)
7933 (verilog-sig-signed portdata)
7934 (verilog-sig-type portdata)
7937 ((or (setq portdata (assoc port (verilog-decls-get-inputs submoddecls)))
7938 (equal "input" verilog-read-sub-decls-gate-ios))
7940 (cons (verilog-sig-new
7942 (if dotname (verilog-sig-bits portdata) vec)
7943 (concat "To " comment)
7944 (verilog-sig-memory portdata)
7946 (verilog-sig-signed portdata)
7947 (verilog-sig-type portdata)
7950 ((setq portdata (assoc port (verilog-decls-get-interfaces submoddecls)))
7952 (cons (verilog-sig-new
7954 (if dotname (verilog-sig-bits portdata) vec)
7955 (concat "To/From " comment)
7956 (verilog-sig-memory portdata)
7958 (verilog-sig-signed portdata)
7959 (verilog-sig-type portdata)
7962 ((setq portdata (and verilog-read-sub-decls-in-interfaced
7963 (assoc port (verilog-decls-get-vars submoddecls))))
7965 (cons (verilog-sig-new
7967 (if dotname (verilog-sig-bits portdata) vec)
7968 (concat "To/From " comment)
7969 (verilog-sig-memory portdata)
7971 (verilog-sig-signed portdata)
7972 (verilog-sig-type portdata)
7975 ;; (t -- warning pin isn't defined.) ; Leave for lint tool
7978 (defun verilog-read-sub-decls-expr (submoddecls comment port expr)
7979 "For `verilog-read-sub-decls-line', parse a subexpression and add signals."
7980 ;;(message "vrsde: '%s'" expr)
7981 ;; Replace special /*[....]*/ comments inserted by verilog-auto-inst-port
7982 (setq expr (verilog-string-replace-matches "/\\*\\(\\[[^*]+\\]\\)\\*/" "\\1" nil nil expr))
7983 ;; Remove front operators
7984 (setq expr (verilog-string-replace-matches "^\\s-*[---+~!|&]+\\s-*" "" nil nil expr))
7987 ;; {..., a, b} requires us to recurse on a,b
7988 ;; To support {#{},{#{a,b}} we'll just split everything on [{},]
7989 ((string-match "^\\s-*{\\(.*\\)}\\s-*$" expr)
7990 (unless verilog-auto-ignore-concat
7991 (let ((mlst (split-string (match-string 1 expr) "[{},]"))
7993 (while (setq mstr (pop mlst))
7994 (verilog-read-sub-decls-expr submoddecls comment port mstr)))))
7996 (let (sig vec multidim)
7997 ;; Remove leading reduction operators, etc
7998 (setq expr (verilog-string-replace-matches "^\\s-*[---+~!|&]+\\s-*" "" nil nil expr))
7999 ;;(message "vrsde-ptop: '%s'" expr)
8000 (cond ;; Find \signal. Final space is part of escaped signal name
8001 ((string-match "^\\s-*\\(\\\\[^ \t\n\f]+\\s-\\)" expr)
8002 ;;(message "vrsde-s: '%s'" (match-string 1 expr))
8003 (setq sig (match-string 1 expr)
8004 expr (substring expr (match-end 0))))
8006 ((string-match "^\\s-*\\([a-zA-Z_][a-zA-Z_0-9]*\\)" expr)
8007 ;;(message "vrsde-s: '%s'" (match-string 1 expr))
8008 (setq sig (verilog-string-remove-spaces (match-string 1 expr))
8009 expr (substring expr (match-end 0)))))
8010 ;; Find [vector] or [multi][multi][multi][vector]
8011 (while (string-match "^\\s-*\\(\\[[^]]+\\]\\)" expr)
8012 ;;(message "vrsde-v: '%s'" (match-string 1 expr))
8013 (when vec (setq multidim (cons vec multidim)))
8014 (setq vec (match-string 1 expr)
8015 expr (substring expr (match-end 0))))
8016 ;; If found signal, and nothing unrecognized, add the signal
8017 ;;(message "vrsde-rem: '%s'" expr)
8018 (when (and sig (string-match "^\\s-*$" expr))
8019 (verilog-read-sub-decls-sig submoddecls comment port sig vec multidim))))))
8021 (defun verilog-read-sub-decls-line (submoddecls comment)
8022 "For `verilog-read-sub-decls', read lines of port defs until none match.
8023 Inserts the list of signals found, using submodi to look up each port."
8029 (cond ((looking-at "\\s-*\\.\\s-*\\([a-zA-Z0-9`_$]*\\)\\s-*(\\s-*")
8030 (setq port (match-string 1))
8031 (goto-char (match-end 0)))
8033 ((looking-at "\\s-*\\.\\s-*\\(\\\\[^ \t\n\f]*\\)\\s-*(\\s-*")
8034 (setq port (concat (match-string 1) " ")) ;; escaped id's need trailing space
8035 (goto-char (match-end 0)))
8037 ((looking-at "\\s-*\\.\\s-*\\([a-zA-Z0-9`_$]*\\)\\s-*[,)/]")
8038 (verilog-read-sub-decls-sig
8039 submoddecls comment (match-string 1) t ; sig==t for .name
8040 nil nil) ; vec multidim
8043 ((looking-at "\\s-*\\.\\s-*\\(\\\\[^ \t\n\f]*\\)\\s-*[,)/]")
8044 (verilog-read-sub-decls-sig
8045 submoddecls comment (concat (match-string 1) " ") t ; sig==t for .name
8046 nil nil) ; vec multidim
8049 ((looking-at "\\s-*\\.[^(]*(")
8050 (setq port nil) ;; skip this line
8051 (goto-char (match-end 0)))
8053 (setq port nil done t))) ;; Unknown, ignore rest of line
8054 ;; Get signal name. Point is at the first-non-space after (
8055 ;; We intentionally ignore (non-escaped) signals with .s in them
8056 ;; this prevents AUTOWIRE etc from noticing hierarchical sigs.
8058 (cond ((looking-at "\\([a-zA-Z_][a-zA-Z_0-9]*\\)\\s-*)")
8059 (verilog-read-sub-decls-sig
8060 submoddecls comment port
8061 (verilog-string-remove-spaces (match-string 1)) ; sig
8062 nil nil)) ; vec multidim
8064 ((looking-at "\\([a-zA-Z_][a-zA-Z_0-9]*\\)\\s-*\\(\\[[^]]+\\]\\)\\s-*)")
8065 (verilog-read-sub-decls-sig
8066 submoddecls comment port
8067 (verilog-string-remove-spaces (match-string 1)) ; sig
8068 (match-string 2) nil)) ; vec multidim
8069 ;; Fastpath was above looking-at's.
8070 ;; For something more complicated invoke a parser
8071 ((looking-at "[^)]+")
8072 (verilog-read-sub-decls-expr
8073 submoddecls comment port
8075 (point) (1- (progn (search-backward "(") ; start at (
8076 (verilog-forward-sexp-ign-cmt 1)
8077 (point)))))))) ; expr
8079 (forward-line 1)))))
8081 (defun verilog-read-sub-decls-gate (submoddecls comment submod end-inst-point)
8082 "For `verilog-read-sub-decls', read lines of UDP gate decl until none match.
8083 Inserts the list of signals found."
8085 (let ((iolist (cdr (assoc submod verilog-gate-ios))))
8086 (while (< (point) end-inst-point)
8087 ;; Get primitive's signal name, as will never have port, and no trailing )
8088 (cond ((looking-at "//")
8089 (search-forward "\n"))
8090 ((looking-at "/\\*")
8091 (or (search-forward "*/")
8092 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
8093 ((looking-at "(\\*")
8094 ;; To advance past either "(*)" or "(* ... *)" don't forward past first *
8096 (or (search-forward "*)")
8097 (error "%s: Unmatched (* *), at char %d" (verilog-point-text) (point))))
8098 ;; On pins, parse and advance to next pin
8099 ;; Looking at pin, but *not* an // Output comment, or ) to end the inst
8100 ((looking-at "\\s-*[a-zA-Z0-9`_$({}\\\\][^,]*")
8101 (goto-char (match-end 0))
8102 (setq verilog-read-sub-decls-gate-ios (or (car iolist) "input")
8103 iolist (cdr iolist))
8104 (verilog-read-sub-decls-expr
8105 submoddecls comment "primitive_port"
8109 (skip-syntax-forward " ")))))))
8111 (defun verilog-read-sub-decls ()
8112 "Internally parse signals going to modules under this module.
8113 Return a array of [ outputs inouts inputs ] signals for modules that are
8114 instantiated in this module. For example if declare A A (.B(SIG)) and SIG
8115 is a output, then SIG will be included in the list.
8117 This only works on instantiations created with /*AUTOINST*/ converted by
8118 \\[verilog-auto-inst]. Otherwise, it would have to read in the whole
8119 component library to determine connectivity of the design.
8121 One work around for this problem is to manually create // Inputs and //
8122 Outputs comments above subcell signals, for example:
8130 (let ((end-mod-point (verilog-get-end-of-defun t))
8131 st-point end-inst-point
8132 ;; below 3 modified by verilog-read-sub-decls-line
8133 sigs-out sigs-inout sigs-in sigs-intf sigs-intfd)
8134 (verilog-beg-of-defun-quick)
8135 (while (verilog-re-search-forward-quick "\\(/\\*AUTOINST\\*/\\|\\.\\*\\)" end-mod-point t)
8137 (goto-char (match-beginning 0))
8138 (unless (verilog-inside-comment-or-string-p)
8139 ;; Attempt to snarf a comment
8140 (let* ((submod (verilog-read-inst-module))
8141 (inst (verilog-read-inst-name))
8142 (subprim (member submod verilog-gate-keywords))
8143 (comment (concat inst " of " submod ".v"))
8144 submodi submoddecls)
8147 (setq submodi `primitive
8148 submoddecls (verilog-decls-new nil nil nil nil nil nil nil nil nil)
8149 comment (concat inst " of " submod))
8150 (verilog-backward-open-paren)
8151 (setq end-inst-point (save-excursion (verilog-forward-sexp-ign-cmt 1)
8155 (verilog-read-sub-decls-gate submoddecls comment submod end-inst-point))
8158 (when (setq submodi (verilog-modi-lookup submod t))
8159 (setq submoddecls (verilog-modi-get-decls submodi)
8160 verilog-read-sub-decls-gate-ios nil)
8161 (verilog-backward-open-paren)
8162 (setq end-inst-point (save-excursion (verilog-forward-sexp-ign-cmt 1)
8165 ;; This could have used a list created by verilog-auto-inst
8166 ;; However I want it to be runnable even on user's manually added signals
8167 (let ((verilog-read-sub-decls-in-interfaced t))
8168 (while (re-search-forward "\\s *(?\\s *// Interfaced" end-inst-point t)
8169 (verilog-read-sub-decls-line submoddecls comment))) ;; Modifies sigs-ifd
8170 (goto-char st-point)
8171 (while (re-search-forward "\\s *(?\\s *// Interfaces" end-inst-point t)
8172 (verilog-read-sub-decls-line submoddecls comment)) ;; Modifies sigs-out
8173 (goto-char st-point)
8174 (while (re-search-forward "\\s *(?\\s *// Outputs" end-inst-point t)
8175 (verilog-read-sub-decls-line submoddecls comment)) ;; Modifies sigs-out
8176 (goto-char st-point)
8177 (while (re-search-forward "\\s *(?\\s *// Inouts" end-inst-point t)
8178 (verilog-read-sub-decls-line submoddecls comment)) ;; Modifies sigs-inout
8179 (goto-char st-point)
8180 (while (re-search-forward "\\s *(?\\s *// Inputs" end-inst-point t)
8181 (verilog-read-sub-decls-line submoddecls comment)) ;; Modifies sigs-in
8183 ;; Combine duplicate bits
8184 ;;(setq rr (vector sigs-out sigs-inout sigs-in))
8185 (verilog-subdecls-new
8186 (verilog-signals-combine-bus (nreverse sigs-out))
8187 (verilog-signals-combine-bus (nreverse sigs-inout))
8188 (verilog-signals-combine-bus (nreverse sigs-in))
8189 (verilog-signals-combine-bus (nreverse sigs-intf))
8190 (verilog-signals-combine-bus (nreverse sigs-intfd))))))
8192 (defun verilog-read-inst-pins ()
8193 "Return an array of [ pins ] for the current instantiation at point.
8194 For example if declare A A (.B(SIG)) then B will be included in the list."
8196 (let ((end-mod-point (point)) ;; presume at /*AUTOINST*/ point
8198 (verilog-backward-open-paren)
8199 (while (re-search-forward "\\.\\([^(,) \t\n\f]*\\)\\s-*" end-mod-point t)
8200 (setq pin (match-string 1))
8201 (unless (verilog-inside-comment-or-string-p)
8202 (setq pins (cons (list pin) pins))
8203 (when (looking-at "(")
8204 (verilog-forward-sexp-ign-cmt 1))))
8207 (defun verilog-read-arg-pins ()
8208 "Return an array of [ pins ] for the current argument declaration at point."
8210 (let ((end-mod-point (point)) ;; presume at /*AUTOARG*/ point
8212 (verilog-backward-open-paren)
8213 (while (re-search-forward "\\([a-zA-Z0-9$_.%`]+\\)" end-mod-point t)
8214 (setq pin (match-string 1))
8215 (unless (verilog-inside-comment-or-string-p)
8216 (setq pins (cons (list pin) pins))))
8219 (defun verilog-read-auto-constants (beg end-mod-point)
8220 "Return a list of AUTO_CONSTANTs used in the region from BEG to END-MOD-POINT."
8223 (let (sig-list tpl-end-pt)
8225 (while (re-search-forward "\\<AUTO_CONSTANT" end-mod-point t)
8226 (if (not (looking-at "\\s *("))
8227 (error "%s: Missing () after AUTO_CONSTANT" (verilog-point-text)))
8228 (search-forward "(" end-mod-point)
8229 (setq tpl-end-pt (save-excursion
8231 (verilog-forward-sexp-cmt 1) ;; Moves to paren that closes argdecl's
8234 (while (re-search-forward "\\s-*\\([\"a-zA-Z0-9$_.%`]+\\)\\s-*,*" tpl-end-pt t)
8235 (setq sig-list (cons (list (match-string 1) nil nil) sig-list))))
8238 (defvar verilog-cache-has-lisp nil "True if any AUTO_LISP in buffer.")
8239 (make-variable-buffer-local 'verilog-cache-has-lisp)
8241 (defun verilog-read-auto-lisp-present ()
8242 "Set `verilog-cache-has-lisp' if any AUTO_LISP in this buffer."
8244 (goto-char (point-min))
8245 (setq verilog-cache-has-lisp (re-search-forward "\\<AUTO_LISP(" nil t))))
8247 (defun verilog-read-auto-lisp (start end)
8248 "Look for and evaluate a AUTO_LISP between START and END.
8249 Must call `verilog-read-auto-lisp-present' before this function."
8250 ;; This function is expensive for large buffers, so we cache if any AUTO_LISP exists
8251 (when verilog-cache-has-lisp
8254 (while (re-search-forward "\\<AUTO_LISP(" end t)
8256 (let* ((beg-pt (prog1 (point)
8257 (verilog-forward-sexp-cmt 1))) ;; Closing paren
8259 (eval-region beg-pt end-pt nil))))))
8262 ;; Prevent compile warnings; these are let's, not globals
8263 ;; Do not remove the eval-when-compile
8264 ;; - we want a error when we are debugging this code if they are refed.
8268 (defvar sigs-out-unk)
8270 (defvar vector-skip-list))
8272 (defun verilog-read-always-signals-recurse
8273 (exit-keywd rvalue temp-next)
8274 "Recursive routine for parentheses/bracket matching.
8275 EXIT-KEYWD is expression to stop at, nil if top level.
8276 RVALUE is true if at right hand side of equal.
8277 IGNORE-NEXT is true to ignore next token, fake from inside case statement."
8278 (let* ((semi-rvalue (equal "endcase" exit-keywd)) ;; true if after a ; we are looking for rvalue
8279 keywd last-keywd sig-tolk sig-last-tolk gotend got-sig got-list end-else-check
8281 ;;(if dbg (setq dbg (concat dbg (format "Recursion %S %S %S\n" exit-keywd rvalue temp-next))))
8282 (while (not (or (eobp) gotend))
8285 (search-forward "\n"))
8286 ((looking-at "/\\*")
8287 (or (search-forward "*/")
8288 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
8289 ((looking-at "(\\*")
8290 ;; To advance past either "(*)" or "(* ... *)" don't forward past first *
8292 (or (search-forward "*)")
8293 (error "%s: Unmatched (* *), at char %d" (verilog-point-text) (point))))
8294 (t (setq keywd (buffer-substring-no-properties
8296 (save-excursion (when (eq 0 (skip-chars-forward "a-zA-Z0-9$_.%`"))
8299 sig-last-tolk sig-tolk
8301 ;;(if dbg (setq dbg (concat dbg (format "\tPt=%S %S\trv=%S in=%S ee=%S gs=%S\n" (point) keywd rvalue ignore-next end-else-check got-sig))))
8304 (or (re-search-forward "[^\\]\"" nil t)
8305 (error "%s: Unmatched quotes, at char %d" (verilog-point-text) (point))))
8306 ;; else at top level loop, keep parsing
8307 ((and end-else-check (equal keywd "else"))
8308 ;;(if dbg (setq dbg (concat dbg (format "\tif-check-else %s\n" keywd))))
8309 ;; no forward movement, want to see else in lower loop
8310 (setq end-else-check nil))
8311 ;; End at top level loop
8312 ((and end-else-check (looking-at "[^ \t\n\f]"))
8313 ;;(if dbg (setq dbg (concat dbg (format "\tif-check-else-other %s\n" keywd))))
8316 ((and exit-keywd (equal keywd exit-keywd))
8318 (forward-char (length keywd)))
8319 ;; Standard tokens...
8321 (setq ignore-next nil rvalue semi-rvalue)
8322 ;; Final statement at top level loop?
8323 (when (not exit-keywd)
8324 ;;(if dbg (setq dbg (concat dbg (format "\ttop-end-check %s\n" keywd))))
8325 (setq end-else-check t))
8328 (if (looking-at "'[sS]?[hdxboHDXBO]?[ \t]*[0-9a-fA-F_xzXZ?]+")
8329 (goto-char (match-end 0))
8331 ((equal keywd ":") ;; Case statement, begin/end label, x?y:z
8332 (cond ((equal "endcase" exit-keywd) ;; case x: y=z; statement next
8333 (setq ignore-next nil rvalue nil))
8334 ((equal "?" exit-keywd) ;; x?y:z rvalue
8336 ((equal "]" exit-keywd) ;; [x:y] rvalue
8338 (got-sig ;; label: statement
8339 (setq ignore-next nil rvalue semi-rvalue got-sig nil))
8340 ((not rvalue) ;; begin label
8341 (setq ignore-next t rvalue nil)))
8345 ;;(if dbg (setq dbg (concat dbg (format "\t\tequal got-sig=%S got-list=%s\n" got-sig got-list))))
8346 (set got-list (cons got-sig (symbol-value got-list)))
8349 (if (eq (char-before) ?< )
8350 (setq sigs-out-d (append sigs-out-d sigs-out-unk)
8352 (setq sigs-out-i (append sigs-out-i sigs-out-unk)
8354 (setq ignore-next nil rvalue t)
8358 (verilog-read-always-signals-recurse ":" rvalue nil))
8361 (verilog-read-always-signals-recurse "]" t nil))
8364 (cond (sig-last-tolk ;; Function call; zap last signal
8365 (setq got-sig nil)))
8366 (cond ((equal last-keywd "for")
8367 ;; temp-next: Variables on LHS are lvalues, but generally we want
8368 ;; to ignore them, assuming they are loop increments
8369 (verilog-read-always-signals-recurse ";" nil t)
8370 (verilog-read-always-signals-recurse ";" t nil)
8371 (verilog-read-always-signals-recurse ")" nil nil))
8372 (t (verilog-read-always-signals-recurse ")" t nil))))
8373 ((equal keywd "begin")
8374 (skip-syntax-forward "w_")
8375 (verilog-read-always-signals-recurse "end" nil nil)
8376 ;;(if dbg (setq dbg (concat dbg (format "\tgot-end %s\n" exit-keywd))))
8377 (setq ignore-next nil rvalue semi-rvalue)
8378 (if (not exit-keywd) (setq end-else-check t)))
8379 ((member keywd '("case" "casex" "casez"))
8380 (skip-syntax-forward "w_")
8381 (verilog-read-always-signals-recurse "endcase" t nil)
8382 (setq ignore-next nil rvalue semi-rvalue)
8383 (if (not exit-keywd) (setq gotend t))) ;; top level begin/end
8384 ((string-match "^[$`a-zA-Z_]" keywd) ;; not exactly word constituent
8385 (cond ((member keywd '("`ifdef" "`ifndef" "`elsif"))
8386 (setq ignore-next t))
8388 (member keywd verilog-keywords)
8389 (string-match "^\\$" keywd)) ;; PLI task
8390 (setq ignore-next nil))
8392 (setq keywd (verilog-symbol-detick-denumber keywd))
8394 (set got-list (cons got-sig (symbol-value got-list)))
8395 ;;(if dbg (setq dbg (concat dbg (format "\t\tgot-sig=%S got-list=%S\n" got-sig got-list))))
8397 (setq got-list (cond (temp-next 'sigs-temp)
8400 got-sig (if (or (not keywd)
8401 (assoc keywd (symbol-value got-list)))
8402 nil (list keywd nil nil))
8405 (skip-chars-forward "a-zA-Z0-9$_.%`"))
8408 ;; End of non-comment token
8409 (setq last-keywd keywd)))
8410 (skip-syntax-forward " "))
8411 ;; Append the final pending signal
8413 ;;(if dbg (setq dbg (concat dbg (format "\t\tfinal got-sig=%S got-list=%s\n" got-sig got-list))))
8414 (set got-list (cons got-sig (symbol-value got-list)))
8416 ;;(if dbg (setq dbg (concat dbg (format "ENDRecursion %s\n" exit-keywd))))
8419 (defun verilog-read-always-signals ()
8420 "Parse always block at point and return list of (outputs inout inputs)."
8423 sigs-out-d sigs-out-i sigs-out-unk sigs-temp sigs-in)
8424 (search-forward ")")
8425 (verilog-read-always-signals-recurse nil nil nil)
8426 (setq sigs-out-i (append sigs-out-i sigs-out-unk)
8428 ;;(if dbg (with-current-buffer (get-buffer-create "*vl-dbg*")) (delete-region (point-min) (point-max)) (insert dbg) (setq dbg ""))
8429 ;; Return what was found
8430 (verilog-alw-new sigs-out-d sigs-out-i sigs-temp sigs-in))))
8432 (defun verilog-read-instants ()
8433 "Parse module at point and return list of ( ( file instance ) ... )."
8434 (verilog-beg-of-defun-quick)
8435 (let* ((end-mod-point (verilog-get-end-of-defun t))
8437 (instants-list nil))
8439 (while (< (point) end-mod-point)
8440 ;; Stay at level 0, no comments
8442 (setq state (parse-partial-sexp (point) end-mod-point 0 t nil))
8443 (or (> (car state) 0) ; in parens
8444 (nth 5 state) ; comment
8448 (if (looking-at "^\\s-*\\([a-zA-Z0-9`_$]+\\)\\s-+\\([a-zA-Z0-9`_$]+\\)\\s-*(")
8449 ;;(if (looking-at "^\\(.+\\)$")
8450 (let ((module (match-string 1))
8451 (instant (match-string 2)))
8452 (if (not (member module verilog-keywords))
8453 (setq instants-list (cons (list module instant) instants-list)))))
8458 (defun verilog-read-auto-template (module)
8459 "Look for a auto_template for the instantiation of the given MODULE.
8460 If found returns the signal name connections. Return REGEXP and
8461 list of ( (signal_name connection_name)... )."
8464 (let ((tpl-regexp "\\([0-9]+\\)")
8465 (lineno -1) ; -1 to offset for the AUTO_TEMPLATE's newline
8468 tpl-sig-list tpl-wild-list tpl-end-pt rep)
8469 ;; Note this search is expensive, as we hunt from mod-begin to point
8470 ;; for every instantiation. Likewise in verilog-read-auto-lisp.
8471 ;; So, we look first for an exact string rather than a slow regexp.
8472 ;; Someday we may keep a cache of every template, but this would also
8473 ;; need to record the relative position of each AUTOINST, as multiple
8474 ;; templates exist for each module, and we're inserting lines.
8476 (verilog-re-search-backward-substr
8478 (concat "^\\s-*/?\\*?\\s-*" module "\\s-+AUTO_TEMPLATE") nil t)
8479 ;; Also try forward of this AUTOINST
8480 ;; This is for historical support; this isn't speced as working
8483 (verilog-re-search-forward-substr
8485 (concat "^\\s-*/?\\*?\\s-*" module "\\s-+AUTO_TEMPLATE") nil t)))
8486 (goto-char (match-end 0))
8488 ;; We reserve @"..." for future lisp expressions that evaluate
8489 ;; once-per-AUTOINST
8490 (when (looking-at "\\s-*\"\\([^\"]*\\)\"")
8491 (setq tpl-regexp (match-string 1))
8492 (goto-char (match-end 0)))
8493 (search-forward "(")
8494 ;; Parse lines in the template
8495 (when verilog-auto-inst-template-numbers
8497 (let ((pre-pt (point)))
8498 (goto-char (point-min))
8499 (while (search-forward "AUTO_TEMPLATE" pre-pt t)
8500 (setq templateno (1+ templateno)))
8501 (while (< (point) pre-pt)
8503 (setq lineno (1+ lineno))))))
8504 (setq tpl-end-pt (save-excursion
8506 (verilog-forward-sexp-cmt 1) ;; Moves to paren that closes argdecl's
8510 (while (< (point) tpl-end-pt)
8511 (cond ((looking-at "\\s-*\\.\\([a-zA-Z0-9`_$]+\\)\\s-*(\\(.*\\))\\s-*\\(,\\|)\\s-*;\\)")
8514 (match-string-no-properties 1)
8515 (match-string-no-properties 2)
8518 (goto-char (match-end 0)))
8521 ;; Regexp bug in XEmacs disallows ][ inside [], and wants + last
8522 "\\s-*\\.\\(\\([a-zA-Z0-9`_$+@^.*?|---]+\\|[][]\\|\\\\[()|]\\)+\\)\\s-*(\\(.*\\))\\s-*\\(,\\|)\\s-*;\\)")
8523 (setq rep (match-string-no-properties 3))
8524 (goto-char (match-end 0))
8528 (verilog-string-replace-matches "@" "\\\\([0-9]+\\\\)" nil nil
8534 ((looking-at "[ \t\f]+")
8535 (goto-char (match-end 0)))
8537 (setq lineno (1+ lineno))
8538 (goto-char (match-end 0)))
8540 (search-forward "\n")
8541 (setq lineno (1+ lineno)))
8542 ((looking-at "/\\*")
8544 (or (search-forward "*/")
8545 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
8547 (error "%s: AUTO_TEMPLATE parsing error: %s"
8548 (verilog-point-text)
8549 (progn (looking-at ".*$") (match-string 0))))))
8552 (list tpl-sig-list tpl-wild-list)))
8553 ;; If no template found
8554 (t (vector tpl-regexp nil))))))
8555 ;;(progn (find-file "auto-template.v") (verilog-read-auto-template "ptl_entry"))
8557 (defun verilog-set-define (defname defvalue &optional buffer enumname)
8558 "Set the definition DEFNAME to the DEFVALUE in the given BUFFER.
8559 Optionally associate it with the specified enumeration ENUMNAME."
8560 (with-current-buffer (or buffer (current-buffer))
8561 (let ((mac (intern (concat "vh-" defname))))
8562 ;;(message "Define %s=%s" defname defvalue) (sleep-for 1)
8563 ;; Need to define to a constant if no value given
8564 (set (make-local-variable mac)
8565 (if (equal defvalue "") "1" defvalue)))
8567 (let ((enumvar (intern (concat "venum-" enumname))))
8568 ;;(message "Define %s=%s" defname defvalue) (sleep-for 1)
8569 (unless (boundp enumvar) (set enumvar nil))
8570 (add-to-list (make-local-variable enumvar) defname)))))
8572 (defun verilog-read-defines (&optional filename recurse subcall)
8573 "Read `defines and parameters for the current file, or optional FILENAME.
8574 If the filename is provided, `verilog-library-flags' will be used to
8575 resolve it. If optional RECURSE is non-nil, recurse through `includes.
8577 Parameters must be simple assignments to constants, or have their own
8578 \"parameter\" label rather than a list of parameters. Thus:
8580 parameter X = 5, Y = 10; // Ok
8581 parameter X = {1'b1, 2'h2}; // Ok
8582 parameter X = {1'b1, 2'h2}, Y = 10; // Bad, make into 2 parameter lines
8584 Defines must be simple text substitutions, one on a line, starting
8585 at the beginning of the line. Any ifdefs or multiline comments around the
8588 Defines are stored inside Emacs variables using the name vh-{definename}.
8590 This function is useful for setting vh-* variables. The file variables
8591 feature can be used to set defines that `verilog-mode' can see; put at the
8592 *END* of your file something like:
8595 // vh-macro:\"macro_definition\"
8598 If macros are defined earlier in the same file and you want their values,
8599 you can read them automatically (provided `enable-local-eval' is on):
8602 // eval:(verilog-read-defines)
8603 // eval:(verilog-read-defines \"group_standard_includes.v\")
8606 Note these are only read when the file is first visited, you must use
8607 \\[find-alternate-file] RET to have these take effect after editing them!
8609 If you want to disable the \"Process `eval' or hook local variables\"
8610 warning message, you need to add to your .emacs file:
8612 (setq enable-local-eval t)"
8613 (let ((origbuf (current-buffer)))
8615 (unless subcall (verilog-getopt-flags))
8617 (let ((fns (verilog-library-filenames filename (buffer-file-name))))
8619 (set-buffer (find-file-noselect (car fns)))
8620 (error (concat (verilog-point-text)
8621 ": Can't find verilog-read-defines file: " filename)))))
8623 (goto-char (point-min))
8624 (while (re-search-forward "^\\s-*`include\\s-+\\([^ \t\n\f]+\\)" nil t)
8625 (let ((inc (verilog-string-replace-matches
8626 "\"" "" nil nil (match-string-no-properties 1))))
8627 (unless (verilog-inside-comment-or-string-p)
8628 (verilog-read-defines inc recurse t)))))
8630 ;; note we don't use verilog-re... it's faster this way, and that
8631 ;; function has problems when comments are at the end of the define
8632 (goto-char (point-min))
8633 (while (re-search-forward "^\\s-*`define\\s-+\\([a-zA-Z0-9_$]+\\)\\s-+\\(.*\\)$" nil t)
8634 (let ((defname (match-string-no-properties 1))
8635 (defvalue (match-string-no-properties 2)))
8636 (setq defvalue (verilog-string-replace-matches "\\s-*/[/*].*$" "" nil nil defvalue))
8637 (verilog-set-define defname defvalue origbuf)))
8638 ;; Hack: Read parameters
8639 (goto-char (point-min))
8640 (while (re-search-forward
8641 "^\\s-*\\(parameter\\|localparam\\)\\(\\s-*\\[[^]]*\\]\\)?\\s-*" nil t)
8643 ;; The primary way of getting defines is verilog-read-decls
8644 ;; However, that isn't called yet for included files, so we'll add another scheme
8645 (if (looking-at "[^\n]*synopsys\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
8646 (setq enumname (match-string-no-properties 1)))
8647 (forward-comment 999)
8648 (while (looking-at (concat "\\s-*,?\\s-*\\(?:/[/*].*?$\\)?\\s-*\\([a-zA-Z0-9_$]+\\)"
8649 "\\s-*=\\s-*\\([^;,]*\\),?\\s-*\\(/[/*].*?$\\)?\\s-*"))
8650 (verilog-set-define (match-string-no-properties 1)
8651 (match-string-no-properties 2) origbuf enumname)
8652 (goto-char (match-end 0))
8653 (forward-comment 999)))))))
8655 (defun verilog-read-includes ()
8656 "Read `includes for the current file.
8657 This will find all of the `includes which are at the beginning of lines,
8658 ignoring any ifdefs or multiline comments around them.
8659 `verilog-read-defines' is then performed on the current and each included
8662 It is often useful put at the *END* of your file something like:
8665 // eval:(verilog-read-defines)
8666 // eval:(verilog-read-includes)
8669 Note includes are only read when the file is first visited, you must use
8670 \\[find-alternate-file] RET to have these take effect after editing them!
8672 It is good to get in the habit of including all needed files in each .v
8673 file that needs it, rather than waiting for compile time. This will aid
8674 this process, Verilint, and readability. To prevent defining the same
8675 variable over and over when many modules are compiled together, put a test
8676 around the inside each include file:
8679 `ifdef _FOO_V // include if not already included
8682 ... contents of file
8684 ;;slow: (verilog-read-defines nil t))
8686 (verilog-getopt-flags)
8687 (goto-char (point-min))
8688 (while (re-search-forward "^\\s-*`include\\s-+\\([^ \t\n\f]+\\)" nil t)
8689 (let ((inc (verilog-string-replace-matches "\"" "" nil nil (match-string 1))))
8690 (verilog-read-defines inc nil t)))))
8692 (defun verilog-read-signals (&optional start end)
8693 "Return a simple list of all possible signals in the file.
8694 Bounded by optional region from START to END. Overly aggressive but fast.
8695 Some macros and such are also found and included. For dinotrace.el."
8696 (let (sigs-all keywd)
8697 (progn;save-excursion
8698 (goto-char (or start (point-min)))
8699 (setq end (or end (point-max)))
8700 (while (re-search-forward "[\"/a-zA-Z_.%`]" end t)
8704 (search-forward "\n"))
8705 ((looking-at "/\\*")
8706 (search-forward "*/"))
8707 ((looking-at "(\\*")
8708 (or (looking-at "(\\*\\s-*)") ; It's a "always @ (*)"
8709 (search-forward "*)")))
8710 ((eq ?\" (following-char))
8711 (re-search-forward "[^\\]\"")) ;; don't forward-char first, since we look for a non backslash first
8712 ((looking-at "\\s-*\\([a-zA-Z0-9$_.%`]+\\)")
8713 (goto-char (match-end 0))
8714 (setq keywd (match-string-no-properties 1))
8715 (or (member keywd verilog-keywords)
8716 (member keywd sigs-all)
8717 (setq sigs-all (cons keywd sigs-all))))
8718 (t (forward-char 1))))
8723 ;; Argument file parsing
8726 (defun verilog-getopt (arglist)
8727 "Parse -f, -v etc arguments in ARGLIST list or string."
8728 (unless (listp arglist) (setq arglist (list arglist)))
8729 (let ((space-args '())
8731 ;; Split on spaces, so users can pass whole command lines
8733 (setq arg (car arglist)
8734 arglist (cdr arglist))
8735 (while (string-match "^\\([^ \t\n\f]+\\)[ \t\n\f]*\\(.*$\\)" arg)
8736 (setq space-args (append space-args
8737 (list (match-string-no-properties 1 arg))))
8738 (setq arg (match-string 2 arg))))
8741 (setq arg (car space-args)
8742 space-args (cdr space-args))
8746 (setq next-param arg))
8748 (setq next-param arg))
8750 (setq next-param arg))
8751 ;; +libext+(ext1)+(ext2)...
8752 ((string-match "^\\+libext\\+\\(.*\\)" arg)
8753 (setq arg (match-string 1 arg))
8754 (while (string-match "\\([^+]+\\)\\+?\\(.*\\)" arg)
8755 (verilog-add-list-unique `verilog-library-extensions
8756 (match-string 1 arg))
8757 (setq arg (match-string 2 arg))))
8759 ((or (string-match "^-D\\([^+=]*\\)[+=]\\(.*\\)" arg) ;; -Ddefine=val
8760 (string-match "^-D\\([^+=]*\\)\\(\\)" arg) ;; -Ddefine
8761 (string-match "^\\+define\\([^+=]*\\)[+=]\\(.*\\)" arg) ;; +define+val
8762 (string-match "^\\+define\\([^+=]*\\)\\(\\)" arg)) ;; +define+define
8763 (verilog-set-define (match-string 1 arg) (match-string 2 arg)))
8765 ((or (string-match "^\\+incdir\\+\\(.*\\)" arg) ;; +incdir+dir
8766 (string-match "^-I\\(.*\\)" arg)) ;; -Idir
8767 (verilog-add-list-unique `verilog-library-directories
8768 (match-string 1 (substitute-in-file-name arg))))
8770 ((equal "+librescan" arg))
8771 ((string-match "^-U\\(.*\\)" arg)) ;; -Udefine
8772 ;; Second parameters
8773 ((equal next-param "-f")
8774 (setq next-param nil)
8775 (verilog-getopt-file (substitute-in-file-name arg)))
8776 ((equal next-param "-v")
8777 (setq next-param nil)
8778 (verilog-add-list-unique `verilog-library-files
8779 (substitute-in-file-name arg)))
8780 ((equal next-param "-y")
8781 (setq next-param nil)
8782 (verilog-add-list-unique `verilog-library-directories
8783 (substitute-in-file-name arg)))
8785 ((string-match "^[^-+]" arg)
8786 (verilog-add-list-unique `verilog-library-files
8787 (substitute-in-file-name arg)))
8788 ;; Default - ignore; no warning
8790 ;;(verilog-getopt (list "+libext+.a+.b" "+incdir+foodir" "+define+a+aval" "-f" "otherf" "-v" "library" "-y" "dir"))
8792 (defun verilog-getopt-file (filename)
8793 "Read Verilog options from the specified FILENAME."
8795 (let ((fns (verilog-library-filenames filename (buffer-file-name)))
8796 (orig-buffer (current-buffer))
8799 (set-buffer (find-file-noselect (car fns)))
8800 (error (concat (verilog-point-text)
8801 ": Can't find verilog-getopt-file -f file: " filename)))
8802 (goto-char (point-min))
8804 (setq line (buffer-substring (point) (point-at-eol)))
8806 (when (string-match "//" line)
8807 (setq line (substring line 0 (match-beginning 0))))
8808 (with-current-buffer orig-buffer ; Variables are buffer-local, so need right context.
8809 (verilog-getopt line))))))
8811 (defun verilog-getopt-flags ()
8812 "Convert `verilog-library-flags' into standard library variables."
8813 ;; If the flags are local, then all the outputs should be local also
8814 (when (local-variable-p `verilog-library-flags (current-buffer))
8815 (mapc 'make-local-variable '(verilog-library-extensions
8816 verilog-library-directories
8817 verilog-library-files
8818 verilog-library-flags)))
8819 ;; Allow user to customize
8820 (verilog-run-hooks 'verilog-before-getopt-flags-hook)
8821 ;; Process arguments
8822 (verilog-getopt verilog-library-flags)
8823 ;; Allow user to customize
8824 (verilog-run-hooks 'verilog-getopt-flags-hook))
8826 (defun verilog-add-list-unique (varref object)
8827 "Append to VARREF list the given OBJECT,
8828 unless it is already a member of the variable's list."
8829 (unless (member object (symbol-value varref))
8830 (set varref (append (symbol-value varref) (list object))))
8832 ;;(progn (setq l '()) (verilog-add-list-unique `l "a") (verilog-add-list-unique `l "a") l)
8834 (defun verilog-current-flags ()
8835 "Convert `verilog-library-flags' and similar variables to command line.
8836 Used for __FLAGS__ in `verilog-expand-command'."
8837 (let ((cmd (mapconcat `concat verilog-library-flags " ")))
8838 (when (equal cmd "")
8840 "+libext+" (mapconcat `concat verilog-library-extensions "+")
8841 (mapconcat (lambda (i) (concat " -y " i " +incdir+" i))
8842 verilog-library-directories "")
8843 (mapconcat (lambda (i) (concat " -v " i))
8844 verilog-library-files ""))))
8846 ;;(verilog-current-flags)
8850 ;; Cached directory support
8853 (defvar verilog-dir-cache-preserving nil
8854 "If set, the directory cache is enabled, and file system changes are ignored.
8855 See `verilog-dir-exists-p' and `verilog-dir-files'.")
8857 ;; If adding new cached variable, add also to verilog-preserve-dir-cache
8858 (defvar verilog-dir-cache-list nil
8859 "Alist of (((Cwd Dirname) Results)...) for caching `verilog-dir-files'.")
8860 (defvar verilog-dir-cache-lib-filenames nil
8861 "Cached data for `verilog-library-filenames'.")
8863 (defmacro verilog-preserve-dir-cache (&rest body)
8864 "Execute the BODY forms, allowing directory cache preservation within BODY.
8865 This means that changes inside BODY made to the file system will not be
8866 seen by the `verilog-dir-files' and related functions."
8867 `(let ((verilog-dir-cache-preserving (current-buffer))
8868 verilog-dir-cache-list
8869 verilog-dir-cache-lib-filenames)
8872 (defun verilog-dir-files (dirname)
8873 "Return all filenames in the DIRNAME directory.
8874 Relative paths depend on the `default-directory'.
8875 Results are cached if inside `verilog-preserve-dir-cache'."
8876 (unless verilog-dir-cache-preserving
8877 (setq verilog-dir-cache-list nil)) ;; Cache disabled
8878 ;; We don't use expand-file-name on the dirname to make key, as it's slow
8879 (let* ((cache-key (list dirname default-directory))
8880 (fass (assoc cache-key verilog-dir-cache-list))
8882 (cond (fass ;; Return data from cache hit
8885 (setq exp-dirname (expand-file-name dirname)
8886 data (and (file-directory-p exp-dirname)
8887 (directory-files exp-dirname nil nil nil)))
8888 ;; Note we also encache nil for non-existing dirs.
8889 (setq verilog-dir-cache-list (cons (list cache-key data)
8890 verilog-dir-cache-list))
8892 ;; Miss-and-hit test:
8893 ;;(verilog-preserve-dir-cache (prin1 (verilog-dir-files "."))
8894 ;; (prin1 (verilog-dir-files ".")) nil)
8896 (defun verilog-dir-file-exists-p (filename)
8897 "Return true if FILENAME exists.
8898 Like `file-exists-p' but results are cached if inside
8899 `verilog-preserve-dir-cache'."
8900 (let* ((dirname (file-name-directory filename))
8901 ;; Correct for file-name-nondirectory returning same if no slash.
8902 (dirnamed (if (or (not dirname) (equal dirname filename))
8903 default-directory dirname))
8904 (flist (verilog-dir-files dirnamed)))
8906 (member (file-name-nondirectory filename) flist)
8908 ;;(verilog-dir-file-exists-p "verilog-mode.el")
8909 ;;(verilog-dir-file-exists-p "../verilog-mode/verilog-mode.el")
8913 ;; Module name lookup
8916 (defun verilog-module-inside-filename-p (module filename)
8917 "Return modi if MODULE is specified inside FILENAME, else nil.
8918 Allows version control to check out the file if need be."
8919 (and (or (file-exists-p filename)
8920 (and (fboundp 'vc-backend)
8921 (vc-backend filename)))
8923 (with-current-buffer (find-file-noselect filename)
8925 (goto-char (point-min))
8927 ;; It may be tempting to look for verilog-defun-re,
8928 ;; don't, it slows things down a lot!
8929 (verilog-re-search-forward-quick "\\<\\(module\\|interface\\|program\\)\\>" nil t)
8930 (setq type (match-string-no-properties 0))
8931 (verilog-re-search-forward-quick "[(;]" nil t))
8932 (if (equal module (verilog-read-module-name))
8933 (setq modi (verilog-modi-new module filename (point) type))))
8936 (defun verilog-is-number (symbol)
8937 "Return true if SYMBOL is number-like."
8938 (or (string-match "^[0-9 \t:]+$" symbol)
8939 (string-match "^[---]*[0-9]+$" symbol)
8940 (string-match "^[0-9 \t]+'s?[hdxbo][0-9a-fA-F_xz? \t]*$" symbol)))
8942 (defun verilog-symbol-detick (symbol wing-it)
8943 "Return an expanded SYMBOL name without any defines.
8944 If the variable vh-{symbol} is defined, return that value.
8945 If undefined, and WING-IT, return just SYMBOL without the tick, else nil."
8946 (while (and symbol (string-match "^`" symbol))
8947 (setq symbol (substring symbol 1))
8949 (if (boundp (intern (concat "vh-" symbol)))
8950 ;; Emacs has a bug where boundp on a buffer-local
8951 ;; variable in only one buffer returns t in another.
8952 ;; This can confuse, so check for nil.
8953 (let ((val (eval (intern (concat "vh-" symbol)))))
8955 (if wing-it symbol nil)
8957 (if wing-it symbol nil))))
8959 ;;(verilog-symbol-detick "`mod" nil)
8961 (defun verilog-symbol-detick-denumber (symbol)
8962 "Return SYMBOL with defines converted and any numbers dropped to nil."
8963 (when (string-match "^`" symbol)
8964 ;; This only will work if the define is a simple signal, not
8965 ;; something like a[b]. Sorry, it should be substituted into the parser
8967 (verilog-string-replace-matches
8968 "\[[^0-9: \t]+\]" "" nil nil
8969 (or (verilog-symbol-detick symbol nil)
8970 (if verilog-auto-sense-defines-constant
8973 (if (verilog-is-number symbol)
8977 (defun verilog-symbol-detick-text (text)
8978 "Return TEXT without any known defines.
8979 If the variable vh-{symbol} is defined, substitute that value."
8980 (let ((ok t) symbol val)
8981 (while (and ok (string-match "`\\([a-zA-Z0-9_]+\\)" text))
8982 (setq symbol (match-string 1 text))
8985 (boundp (intern (concat "vh-" symbol)))
8986 ;; Emacs has a bug where boundp on a buffer-local
8987 ;; variable in only one buffer returns t in another.
8988 ;; This can confuse, so check for nil.
8989 (setq val (eval (intern (concat "vh-" symbol)))))
8990 (setq text (replace-match val nil nil text)))
8991 (t (setq ok nil)))))
8993 ;;(progn (setq vh-mod "`foo" vh-foo "bar") (verilog-symbol-detick-text "bar `mod `undefed"))
8995 (defun verilog-expand-dirnames (&optional dirnames)
8996 "Return a list of existing directories given a list of wildcarded DIRNAMES.
8997 Or, just the existing dirnames themselves if there are no wildcards."
8998 ;; Note this function is performance critical.
8999 ;; Do not call anything that requires disk access that cannot be cached.
9001 (unless dirnames (error "`verilog-library-directories' should include at least '.'"))
9002 (setq dirnames (reverse dirnames)) ; not nreverse
9004 pattern dirfile dirfiles dirname root filename rest basefile)
9006 (setq dirname (substitute-in-file-name (car dirnames))
9007 dirnames (cdr dirnames))
9008 (cond ((string-match (concat "^\\(\\|[/\\]*[^*?]*[/\\]\\)" ;; root
9009 "\\([^/\\]*[*?][^/\\]*\\)" ;; filename with *?
9012 (setq root (match-string 1 dirname)
9013 filename (match-string 2 dirname)
9014 rest (match-string 3 dirname)
9016 ;; now replace those * and ? with .+ and .
9017 ;; use ^ and /> to get only whole file names
9018 (setq pattern (verilog-string-replace-matches "[*]" ".+" nil nil pattern)
9019 pattern (verilog-string-replace-matches "[?]" "." nil nil pattern)
9020 pattern (concat "^" pattern "$")
9021 dirfiles (verilog-dir-files root))
9023 (setq basefile (car dirfiles)
9024 dirfile (expand-file-name (concat root basefile rest))
9025 dirfiles (cdr dirfiles))
9026 (if (and (string-match pattern basefile)
9027 ;; Don't allow abc/*/rtl to match abc/rtl via ..
9028 (not (equal basefile "."))
9029 (not (equal basefile ".."))
9030 (file-directory-p dirfile))
9031 (setq dirlist (cons dirfile dirlist)))))
9034 (if (file-directory-p dirname)
9035 (setq dirlist (cons dirname dirlist))))))
9037 ;;(verilog-expand-dirnames (list "." ".." "nonexist" "../*" "/home/wsnyder/*/v"))
9039 (defun verilog-library-filenames (filename &optional current check-ext)
9040 "Return a search path to find the given FILENAME or module name.
9041 Uses the optional CURRENT filename or buffer-file-name, plus
9042 `verilog-library-directories' and `verilog-library-extensions'
9043 variables to build the path. With optional CHECK-EXT also check
9044 `verilog-library-extensions'."
9045 (unless current (setq current (buffer-file-name)))
9046 (unless verilog-dir-cache-preserving
9047 (setq verilog-dir-cache-lib-filenames nil))
9048 (let* ((cache-key (list filename current check-ext))
9049 (fass (assoc cache-key verilog-dir-cache-lib-filenames))
9050 chkdirs chkdir chkexts fn outlist)
9051 (cond (fass ;; Return data from cache hit
9054 ;; Note this expand can't be easily cached, as we need to
9055 ;; pick up buffer-local variables for newly read sub-module files
9056 (setq chkdirs (verilog-expand-dirnames verilog-library-directories))
9058 (setq chkdir (expand-file-name (car chkdirs)
9059 (file-name-directory current))
9060 chkexts (if check-ext verilog-library-extensions `("")))
9062 (setq fn (expand-file-name (concat filename (car chkexts))
9064 ;;(message "Check for %s" fn)
9065 (if (verilog-dir-file-exists-p fn)
9066 (setq outlist (cons (expand-file-name
9067 fn (file-name-directory current))
9069 (setq chkexts (cdr chkexts)))
9070 (setq chkdirs (cdr chkdirs)))
9071 (setq outlist (nreverse outlist))
9072 (setq verilog-dir-cache-lib-filenames
9073 (cons (list cache-key outlist)
9074 verilog-dir-cache-lib-filenames))
9077 (defun verilog-module-filenames (module current)
9078 "Return a search path to find the given MODULE name.
9079 Uses the CURRENT filename, `verilog-library-extensions',
9080 `verilog-library-directories' and `verilog-library-files'
9081 variables to build the path."
9082 ;; Return search locations for it
9083 (append (list current) ; first, current buffer
9084 (verilog-library-filenames module current t)
9085 verilog-library-files)) ; finally, any libraries
9088 ;; Module Information
9090 ;; Many of these functions work on "modi" a module information structure
9091 ;; A modi is: [module-name-string file-name begin-point]
9093 (defvar verilog-cache-enabled t
9094 "If true, enable caching of signals, etc. Set to nil for debugging to make things SLOW!")
9096 (defvar verilog-modi-cache-list nil
9097 "Cache of ((Module Function) Buf-Tick Buf-Modtime Func-Returns)...
9098 For speeding up verilog-modi-get-* commands.
9100 (make-variable-buffer-local 'verilog-modi-cache-list)
9102 (defvar verilog-modi-cache-preserve-tick nil
9103 "Modification tick after which the cache is still considered valid.
9104 Use `verilog-preserve-modi-cache' to set it.")
9105 (defvar verilog-modi-cache-preserve-buffer nil
9106 "Modification tick after which the cache is still considered valid.
9107 Use `verilog-preserve-modi-cache' to set it.")
9108 (defvar verilog-modi-cache-current-enable nil
9109 "If true, allow caching `verilog-modi-current', set by let().")
9110 (defvar verilog-modi-cache-current nil
9111 "Currently active `verilog-modi-current', if any, set by let().")
9112 (defvar verilog-modi-cache-current-max nil
9113 "Current endmodule point for `verilog-modi-cache-current', if any.")
9115 (defun verilog-modi-current ()
9116 "Return the modi structure for the module currently at point, possibly cached."
9117 (cond ((and verilog-modi-cache-current
9118 (>= (point) (verilog-modi-get-point verilog-modi-cache-current))
9119 (<= (point) verilog-modi-cache-current-max))
9120 ;; Slow assertion, for debugging the cache:
9121 ;;(or (equal verilog-modi-cache-current (verilog-modi-current-get)) (debug))
9122 verilog-modi-cache-current)
9123 (verilog-modi-cache-current-enable
9124 (setq verilog-modi-cache-current (verilog-modi-current-get)
9125 verilog-modi-cache-current-max
9126 ;; The cache expires when we pass "endmodule" as then the
9127 ;; current modi may change to the next module
9128 ;; This relies on the AUTOs generally inserting, not deleting text
9130 (verilog-re-search-forward-quick verilog-end-defun-re nil nil)))
9131 verilog-modi-cache-current)
9133 (verilog-modi-current-get))))
9135 (defun verilog-modi-current-get ()
9136 "Return the modi structure for the module currently at point."
9137 (let* (name type pt)
9138 ;; read current module's name
9140 (verilog-re-search-backward-quick verilog-defun-re nil nil)
9141 (setq type (match-string-no-properties 0))
9142 (verilog-re-search-forward-quick "(" nil nil)
9143 (setq name (verilog-read-module-name))
9145 ;; return modi - note this vector built two places
9146 (verilog-modi-new name (or (buffer-file-name) (current-buffer)) pt type)))
9148 (defvar verilog-modi-lookup-cache nil "Hash of (modulename modi).")
9149 (make-variable-buffer-local 'verilog-modi-lookup-cache)
9150 (defvar verilog-modi-lookup-last-current nil "Cache of `current-buffer' at last lookup.")
9151 (defvar verilog-modi-lookup-last-tick nil "Cache of `buffer-chars-modified-tick' at last lookup.")
9153 (defun verilog-modi-lookup (module allow-cache &optional ignore-error)
9154 "Find the file and point at which MODULE is defined.
9155 If ALLOW-CACHE is set, check and remember cache of previous lookups.
9156 Return modi if successful, else print message unless IGNORE-ERROR is true."
9157 (let* ((current (or (buffer-file-name) (current-buffer)))
9160 ;;(message "verilog-modi-lookup: %s" module)
9161 (cond ((and verilog-modi-lookup-cache
9162 verilog-cache-enabled
9164 (setq modi (gethash module verilog-modi-lookup-cache))
9165 (equal verilog-modi-lookup-last-current current)
9166 ;; Iff hit is in current buffer, then tick must match
9167 (or (equal verilog-modi-lookup-last-tick (buffer-chars-modified-tick))
9168 (not (equal current (verilog-modi-file-or-buffer modi)))))
9169 ;;(message "verilog-modi-lookup: HIT %S" modi)
9172 (t (let* ((realmod (verilog-symbol-detick module t))
9173 (orig-filenames (verilog-module-filenames realmod current))
9174 (filenames orig-filenames)
9176 (while (and filenames (not mif))
9177 (if (not (setq mif (verilog-module-inside-filename-p realmod (car filenames))))
9178 (setq filenames (cdr filenames))))
9179 ;; mif has correct form to become later elements of modi
9180 (cond (mif (setq modi mif))
9183 (error (concat (verilog-point-text)
9184 ": Can't locate " module " module definition"
9185 (if (not (equal module realmod))
9186 (concat " (Expanded macro to " realmod ")")
9188 "\n Check the verilog-library-directories variable."
9189 "\n I looked in (if not listed, doesn't exist):\n\t"
9190 (mapconcat 'concat orig-filenames "\n\t"))))))
9191 (when (eval-when-compile (fboundp 'make-hash-table))
9192 (unless verilog-modi-lookup-cache
9193 (setq verilog-modi-lookup-cache
9194 (make-hash-table :test 'equal :rehash-size 4.0)))
9195 (puthash module modi verilog-modi-lookup-cache))
9196 (setq verilog-modi-lookup-last-current current
9197 verilog-modi-lookup-last-tick (buffer-chars-modified-tick)))))
9200 (defun verilog-modi-filename (modi)
9201 "Filename of MODI, or name of buffer if it's never been saved."
9202 (if (bufferp (verilog-modi-file-or-buffer modi))
9203 (or (buffer-file-name (verilog-modi-file-or-buffer modi))
9204 (buffer-name (verilog-modi-file-or-buffer modi)))
9205 (verilog-modi-file-or-buffer modi)))
9207 (defun verilog-modi-goto (modi)
9208 "Move point/buffer to specified MODI."
9209 (or modi (error "Passed unfound modi to goto, check earlier"))
9210 (set-buffer (if (bufferp (verilog-modi-file-or-buffer modi))
9211 (verilog-modi-file-or-buffer modi)
9212 (find-file-noselect (verilog-modi-file-or-buffer modi))))
9213 (or (equal major-mode `verilog-mode) ;; Put into Verilog mode to get syntax
9215 (goto-char (verilog-modi-get-point modi)))
9217 (defun verilog-goto-defun-file (module)
9218 "Move point to the file at which a given MODULE is defined."
9219 (interactive "sGoto File for Module: ")
9220 (let* ((modi (verilog-modi-lookup module nil)))
9222 (verilog-modi-goto modi)
9223 (switch-to-buffer (current-buffer)))))
9225 (defun verilog-modi-cache-results (modi function)
9226 "Run on MODI the given FUNCTION. Locate the module in a file.
9227 Cache the output of function so next call may have faster access."
9229 (save-excursion ;; Cache is buffer-local so can't avoid this.
9230 (verilog-modi-goto modi)
9231 (if (and (setq fass (assoc (list modi function)
9232 verilog-modi-cache-list))
9233 ;; Destroy caching when incorrect; Modified or file changed
9234 (not (and verilog-cache-enabled
9235 (or (equal (buffer-chars-modified-tick) (nth 1 fass))
9236 (and verilog-modi-cache-preserve-tick
9237 (<= verilog-modi-cache-preserve-tick (nth 1 fass))
9238 (equal verilog-modi-cache-preserve-buffer (current-buffer))))
9239 (equal (visited-file-modtime) (nth 2 fass)))))
9240 (setq verilog-modi-cache-list nil
9243 ;; Return data from cache hit
9247 ;; Clear then restore any highlighting to make emacs19 happy
9248 (let ((fontlocked (when (and (boundp 'font-lock-mode)
9253 (setq func-returns (funcall function))
9254 (when fontlocked (font-lock-mode t))
9255 ;; Cache for next time
9256 (setq verilog-modi-cache-list
9257 (cons (list (list modi function)
9258 (buffer-chars-modified-tick)
9259 (visited-file-modtime)
9261 verilog-modi-cache-list))
9264 (defun verilog-modi-cache-add (modi function element sig-list)
9265 "Add function return results to the module cache.
9266 Update MODI's cache for given FUNCTION so that the return ELEMENT of that
9267 function now contains the additional SIG-LIST parameters."
9270 (verilog-modi-goto modi)
9271 (if (setq fass (assoc (list modi function)
9272 verilog-modi-cache-list))
9273 (let ((func-returns (nth 3 fass)))
9274 (aset func-returns element
9275 (append sig-list (aref func-returns element))))))))
9277 (defmacro verilog-preserve-modi-cache (&rest body)
9278 "Execute the BODY forms, allowing cache preservation within BODY.
9279 This means that changes to the buffer will not result in the cache being
9280 flushed. If the changes affect the modsig state, they must call the
9281 modsig-cache-add-* function, else the results of later calls may be
9282 incorrect. Without this, changes are assumed to be adding/removing signals
9283 and invalidating the cache."
9284 `(let ((verilog-modi-cache-preserve-tick (buffer-chars-modified-tick))
9285 (verilog-modi-cache-preserve-buffer (current-buffer)))
9289 (defun verilog-signals-matching-enum (in-list enum)
9290 "Return all signals in IN-LIST matching the given ENUM."
9293 (if (equal (verilog-sig-enum (car in-list)) enum)
9294 (setq out-list (cons (car in-list) out-list)))
9295 (setq in-list (cdr in-list)))
9297 (let* ((enumvar (intern (concat "venum-" enum)))
9298 (enumlist (and (boundp enumvar) (eval enumvar))))
9300 (add-to-list 'out-list (list (car enumlist)))
9301 (setq enumlist (cdr enumlist))))
9302 (nreverse out-list)))
9304 (defun verilog-signals-matching-regexp (in-list regexp)
9305 "Return all signals in IN-LIST matching the given REGEXP, if non-nil."
9306 (if (or (not regexp) (equal regexp ""))
9310 (if (string-match regexp (verilog-sig-name (car in-list)))
9311 (setq out-list (cons (car in-list) out-list)))
9312 (setq in-list (cdr in-list)))
9313 (nreverse out-list))))
9315 (defun verilog-signals-not-matching-regexp (in-list regexp)
9316 "Return all signals in IN-LIST not matching the given REGEXP, if non-nil."
9317 (if (or (not regexp) (equal regexp ""))
9321 (if (not (string-match regexp (verilog-sig-name (car in-list))))
9322 (setq out-list (cons (car in-list) out-list)))
9323 (setq in-list (cdr in-list)))
9324 (nreverse out-list))))
9326 (defun verilog-signals-matching-dir-re (in-list decl-type regexp)
9327 "Return all signals in IN-LIST matching the given DECL-TYPE and REGEXP,
9329 (if (or (not regexp) (equal regexp ""))
9331 (let (out-list to-match)
9333 ;; Note verilog-insert-one-definition matches on this order
9334 (setq to-match (concat
9336 " " (verilog-sig-signed (car in-list))
9337 " " (verilog-sig-multidim (car in-list))
9338 (verilog-sig-bits (car in-list))))
9339 (if (string-match regexp to-match)
9340 (setq out-list (cons (car in-list) out-list)))
9341 (setq in-list (cdr in-list)))
9342 (nreverse out-list))))
9345 (defun verilog-decls-get-signals (decls)
9346 "Return all declared signals, excluding 'assign' statements."
9348 (verilog-decls-get-outputs decls)
9349 (verilog-decls-get-inouts decls)
9350 (verilog-decls-get-inputs decls)
9351 (verilog-decls-get-vars decls)
9352 (verilog-decls-get-consts decls)
9353 (verilog-decls-get-gparams decls)))
9355 (defun verilog-decls-get-ports (decls)
9357 (verilog-decls-get-outputs decls)
9358 (verilog-decls-get-inouts decls)
9359 (verilog-decls-get-inputs decls)))
9361 (defsubst verilog-modi-cache-add-outputs (modi sig-list)
9362 (verilog-modi-cache-add modi 'verilog-read-decls 0 sig-list))
9363 (defsubst verilog-modi-cache-add-inouts (modi sig-list)
9364 (verilog-modi-cache-add modi 'verilog-read-decls 1 sig-list))
9365 (defsubst verilog-modi-cache-add-inputs (modi sig-list)
9366 (verilog-modi-cache-add modi 'verilog-read-decls 2 sig-list))
9367 (defsubst verilog-modi-cache-add-vars (modi sig-list)
9368 (verilog-modi-cache-add modi 'verilog-read-decls 3 sig-list))
9370 (defun verilog-signals-from-signame (signame-list)
9371 "Return signals in standard form from SIGNAME-LIST, a simple list of signal names."
9372 (mapcar (function (lambda (name) (list name nil nil)))
9376 ;; Auto creation utilities
9379 (defun verilog-auto-re-search-do (search-for func)
9380 "Search for the given auto text regexp SEARCH-FOR, and perform FUNC where it occurs."
9381 (goto-char (point-min))
9382 (while (verilog-re-search-forward-quick search-for nil t)
9385 (defun verilog-insert-one-definition (sig type indent-pt)
9386 "Print out a definition for SIG of the given TYPE,
9387 with appropriate INDENT-PT indentation."
9388 (indent-to indent-pt)
9389 ;; Note verilog-signals-matching-dir-re matches on this order
9391 (when (verilog-sig-modport sig)
9392 (insert "." (verilog-sig-modport sig)))
9393 (when (verilog-sig-signed sig)
9394 (insert " " (verilog-sig-signed sig)))
9395 (when (verilog-sig-multidim sig)
9396 (insert " " (verilog-sig-multidim-string sig)))
9397 (when (verilog-sig-bits sig)
9398 (insert " " (verilog-sig-bits sig)))
9399 (indent-to (max 24 (+ indent-pt 16)))
9400 (unless (= (char-syntax (preceding-char)) ?\ )
9401 (insert " ")) ; Need space between "]name" if indent-to did nothing
9402 (insert (verilog-sig-name sig))
9403 (when (verilog-sig-memory sig)
9404 (insert " " (verilog-sig-memory sig))))
9406 (defun verilog-insert-definition (modi sigs direction indent-pt v2k &optional dont-sort)
9407 "Print out a definition for MODI's list of SIGS of the given DIRECTION,
9408 with appropriate INDENT-PT indentation. If V2K, use Verilog 2001 I/O
9409 format. Sort unless DONT-SORT. DIRECTION is normally wire/reg/output.
9410 When MODI is non-null, also add to modi-cache, for tracking."
9412 (cond ((equal direction "wire")
9413 (verilog-modi-cache-add-vars modi sigs))
9414 ((equal direction "reg")
9415 (verilog-modi-cache-add-vars modi sigs))
9416 ((equal direction "output")
9417 (verilog-modi-cache-add-outputs modi sigs)
9418 (when verilog-auto-declare-nettype
9419 (verilog-modi-cache-add-vars modi sigs)))
9420 ((equal direction "input")
9421 (verilog-modi-cache-add-inputs modi sigs)
9422 (when verilog-auto-declare-nettype
9423 (verilog-modi-cache-add-vars modi sigs)))
9424 ((equal direction "inout")
9425 (verilog-modi-cache-add-inouts modi sigs)
9426 (when verilog-auto-declare-nettype
9427 (verilog-modi-cache-add-vars modi sigs)))
9428 ((equal direction "interface"))
9430 (error "Unsupported verilog-insert-definition direction: %s" direction))))
9432 (setq sigs (sort (copy-alist sigs) `verilog-signals-sort-compare)))
9434 (let ((sig (car sigs)))
9435 (verilog-insert-one-definition
9437 ;; Want "type x" or "output type x", not "wire type x"
9438 (cond ((or (verilog-sig-type sig)
9439 verilog-auto-wire-type)
9441 (when (member direction '("input" "output" "inout"))
9442 (concat direction " "))
9443 (or (verilog-sig-type sig)
9444 verilog-auto-wire-type)))
9445 ((and verilog-auto-declare-nettype
9446 (member direction '("input" "output" "inout")))
9447 (concat direction " " verilog-auto-declare-nettype))
9451 (insert (if v2k "," ";"))
9452 (if (or (not (verilog-sig-comment sig))
9453 (equal "" (verilog-sig-comment sig)))
9455 (indent-to (max 48 (+ indent-pt 40)))
9456 (verilog-insert "// " (verilog-sig-comment sig) "\n"))
9457 (setq sigs (cdr sigs)))))
9460 (if (not (boundp 'indent-pt))
9461 (defvar indent-pt nil "Local used by insert-indent")))
9463 (defun verilog-insert-indent (&rest stuff)
9464 "Indent to position stored in local `indent-pt' variable, then insert STUFF.
9465 Presumes that any newlines end a list element."
9466 (let ((need-indent t))
9468 (if need-indent (indent-to indent-pt))
9469 (setq need-indent nil)
9470 (verilog-insert (car stuff))
9471 (setq need-indent (string-match "\n$" (car stuff))
9472 stuff (cdr stuff)))))
9473 ;;(let ((indent-pt 10)) (verilog-insert-indent "hello\n" "addon" "there\n"))
9475 (defun verilog-repair-open-comma ()
9476 "Insert comma if previous argument is other than a open parenthesis or endif."
9477 ;; We can't just search backward for ) as it might be inside another expression.
9478 ;; Also want "`ifdef X input foo `endif" to just leave things to the human to deal with
9480 (verilog-backward-syntactic-ws-quick)
9481 (when (and (not (save-excursion ;; Not beginning (, or existing ,
9483 (looking-at "[(,]")))
9484 (not (save-excursion ;; Not `endif, or user define
9486 (skip-chars-backward "[a-zA-Z0-9_`]")
9490 (defun verilog-repair-close-comma ()
9491 "If point is at a comma followed by a close parenthesis, fix it.
9492 This repairs those mis-inserted by a AUTOARG."
9493 ;; It would be much nicer if Verilog allowed extra commas like Perl does!
9495 (verilog-forward-close-paren)
9497 (verilog-backward-syntactic-ws-quick)
9499 (when (looking-at ",")
9502 (defun verilog-get-list (start end)
9503 "Return the elements of a comma separated list between START and END."
9505 (let ((my-list (list))
9508 (while (< (point) end)
9509 (when (re-search-forward "\\([^,{]+\\)" end t)
9510 (setq my-string (verilog-string-remove-spaces (match-string 1)))
9511 (setq my-list (nconc my-list (list my-string) ))
9512 (goto-char (match-end 0))))
9515 (defun verilog-make-width-expression (range-exp)
9516 "Return an expression calculating the length of a range [x:y] in RANGE-EXP."
9518 (cond ((not range-exp)
9521 (if (string-match "^\\[\\(.*\\)\\]$" range-exp)
9522 (setq range-exp (match-string 1 range-exp)))
9523 (cond ((not range-exp)
9525 ;; [#:#] We can compute a numeric result
9526 ((string-match "^\\s *\\([0-9]+\\)\\s *:\\s *\\([0-9]+\\)\\s *$"
9529 (1+ (abs (- (string-to-number (match-string 1 range-exp))
9530 (string-to-number (match-string 2 range-exp)))))))
9531 ;; [PARAM-1:0] can just return PARAM
9532 ((string-match "^\\s *\\([a-zA-Z_][a-zA-Z0-9_]*\\)\\s *-\\s *1\\s *:\\s *0\\s *$" range-exp)
9533 (match-string 1 range-exp))
9534 ;; [arbitrary] need math
9535 ((string-match "^\\(.*\\)\\s *:\\s *\\(.*\\)\\s *$" range-exp)
9536 (concat "(1+(" (match-string 1 range-exp) ")"
9537 (if (equal "0" (match-string 2 range-exp))
9538 "" ;; Don't bother with -(0)
9539 (concat "-(" (match-string 2 range-exp) ")"))
9542 ;;(verilog-make-width-expression "`A:`B")
9544 (defun verilog-simplify-range-expression (expr)
9545 "Return a simplified range expression with constants eliminated from EXPR."
9546 ;; Note this is always called with brackets; ie [z] or [z:z]
9547 (if (not (string-match "[---+*()]" expr))
9548 expr ;; short-circuit
9551 (while (not (equal last-pass out))
9552 (setq last-pass out)
9553 ;; Prefix regexp needs beginning of match, or some symbol of
9554 ;; lesser or equal precedence. We assume the [:]'s exist in expr.
9556 (while (string-match
9557 (concat "\\([[({:*+-]\\)" ; - must be last
9558 "(\\<\\([0-9A-Za-z_]+\\))"
9561 (setq out (replace-match "\\1\\2\\3" nil nil out)))
9562 ;; For precedence do * before +/-
9563 (while (string-match
9564 (concat "\\([[({:*+-]\\)"
9565 "\\([0-9]+\\)\\s *\\([*]\\)\\s *\\([0-9]+\\)"
9568 (setq out (replace-match
9569 (concat (match-string 1 out)
9570 (int-to-string (* (string-to-number (match-string 2 out))
9571 (string-to-number (match-string 4 out))))
9572 (match-string 5 out))
9574 (while (string-match
9575 (concat "\\([[({:+-]\\)" ; No * here as higher prec
9576 "\\([0-9]+\\)\\s *\\([---+]\\)\\s *\\([0-9]+\\)"
9579 (let ((pre (match-string 1 out))
9580 (lhs (string-to-number (match-string 2 out)))
9581 (rhs (string-to-number (match-string 4 out)))
9582 (post (match-string 5 out))
9584 (when (equal pre "-")
9586 (setq val (if (equal (match-string 3 out) "-")
9590 (concat (if (and (equal pre "-")
9592 "" ;; Not "--20" but just "-20"
9598 ;;(verilog-simplify-range-expression "[1:3]") ;; 1
9599 ;;(verilog-simplify-range-expression "[(1):3]") ;; 1
9600 ;;(verilog-simplify-range-expression "[(((16)+1)+1+(1+1))]") ;;20
9601 ;;(verilog-simplify-range-expression "[(2*3+6*7)]") ;; 48
9602 ;;(verilog-simplify-range-expression "[(FOO*4-1*2)]") ;; FOO*4-2
9603 ;;(verilog-simplify-range-expression "[(FOO*4+1-1)]") ;; FOO*4+0
9604 ;;(verilog-simplify-range-expression "[(func(BAR))]") ;; func(BAR)
9605 ;;(verilog-simplify-range-expression "[FOO-1+1-1+1]") ;; FOO-0
9607 (defun verilog-typedef-name-p (variable-name)
9608 "Return true if the VARIABLE-NAME is a type definition."
9609 (when verilog-typedef-regexp
9610 (string-match verilog-typedef-regexp variable-name)))
9616 (defun verilog-delete-autos-lined ()
9617 "Delete autos that occupy multiple lines, between begin and end comments."
9618 ;; The newline must not have a comment property, so we must
9619 ;; delete the end auto's newline, not the first newline
9623 (looking-at "\\s-*// Beginning")
9624 (search-forward "// End of automatic" nil t))
9628 (delete-region pt (point)))))
9630 (defun verilog-delete-empty-auto-pair ()
9631 "Delete begin/end auto pair at point, if empty."
9633 (when (looking-at (concat "\\s-*// Beginning of automatic.*\n"
9634 "\\s-*// End of automatics\n"))
9635 (delete-region (point) (save-excursion (forward-line 2) (point)))))
9637 (defun verilog-forward-close-paren ()
9638 "Find the close parenthesis that match the current point.
9639 Ignore other close parenthesis with matching open parens."
9642 (unless (verilog-re-search-forward-quick "[()]" nil t)
9643 (error "%s: Mismatching ()" (verilog-point-text)))
9644 (cond ((= (preceding-char) ?\( )
9645 (setq parens (1+ parens)))
9646 ((= (preceding-char) ?\) )
9647 (setq parens (1- parens)))))))
9649 (defun verilog-backward-open-paren ()
9650 "Find the open parenthesis that match the current point.
9651 Ignore other open parenthesis with matching close parens."
9654 (unless (verilog-re-search-backward-quick "[()]" nil t)
9655 (error "%s: Mismatching ()" (verilog-point-text)))
9656 (cond ((= (following-char) ?\) )
9657 (setq parens (1+ parens)))
9658 ((= (following-char) ?\( )
9659 (setq parens (1- parens)))))))
9661 (defun verilog-backward-open-bracket ()
9662 "Find the open bracket that match the current point.
9663 Ignore other open bracket with matching close bracket."
9666 (unless (verilog-re-search-backward-quick "[][]" nil t)
9667 (error "%s: Mismatching []" (verilog-point-text)))
9668 (cond ((= (following-char) ?\] )
9669 (setq parens (1+ parens)))
9670 ((= (following-char) ?\[ )
9671 (setq parens (1- parens)))))))
9673 (defun verilog-delete-to-paren ()
9674 "Delete the automatic inst/sense/arg created by autos.
9675 Deletion stops at the matching end parenthesis, outside comments."
9676 (delete-region (point)
9678 (verilog-backward-open-paren)
9679 (verilog-forward-sexp-ign-cmt 1) ;; Moves to paren that closes argdecl's
9683 (defun verilog-auto-star-safe ()
9684 "Return if a .* AUTOINST is safe to delete or expand.
9685 It was created by the AUTOS themselves, or by the user."
9686 (and verilog-auto-star-expand
9688 (concat "[ \t\n\f,]*\\([)]\\|// " verilog-inst-comment-re "\\)"))))
9690 (defun verilog-delete-auto-star-all ()
9691 "Delete a .* AUTOINST, if it is safe."
9692 (when (verilog-auto-star-safe)
9693 (verilog-delete-to-paren)))
9695 (defun verilog-delete-auto-star-implicit ()
9696 "Delete all .* implicit connections created by `verilog-auto-star'.
9697 This function will be called automatically at save unless
9698 `verilog-auto-star-save' is set, any non-templated expanded pins will be
9701 (let (paren-pt indent have-close-paren)
9703 (goto-char (point-min))
9704 ;; We need to match these even outside of comments.
9705 ;; For reasonable performance, we don't check if inside comments, sorry.
9706 (while (re-search-forward "// Implicit \\.\\*" nil t)
9707 (setq paren-pt (point))
9709 (setq have-close-paren
9711 (when (search-forward ");" paren-pt t)
9712 (setq indent (current-indentation))
9714 (delete-region (point) (+ 1 paren-pt)) ; Nuke line incl CR
9715 (when have-close-paren
9716 ;; Delete extra commentary
9720 (looking-at (concat "\\s *//\\s *" verilog-inst-comment-re "\n")))
9721 (delete-region (match-beginning 0) (match-end 0))))
9722 ;; If it is simple, we can put the ); on the same line as the last text
9723 (let ((rtn-pt (point)))
9725 (while (progn (backward-char 1)
9726 (looking-at "[ \t\n\f]")))
9727 (when (looking-at ",")
9728 (delete-region (+ 1 (point)) rtn-pt))))
9732 ;; Still need to kill final comma - always is one as we put one after the .*
9733 (re-search-backward ",")
9734 (delete-char 1))))))
9736 (defun verilog-delete-auto ()
9737 "Delete the automatic outputs, regs, and wires created by \\[verilog-auto].
9738 Use \\[verilog-auto] to re-insert the updated AUTOs.
9740 The hooks `verilog-before-delete-auto-hook' and `verilog-delete-auto-hook' are
9741 called before and after this function, respectively."
9744 (if (buffer-file-name)
9745 (find-file-noselect (buffer-file-name))) ;; To check we have latest version
9746 (verilog-save-no-change-functions
9747 (verilog-save-scan-cache
9748 ;; Allow user to customize
9749 (verilog-run-hooks 'verilog-before-delete-auto-hook)
9751 ;; Remove those that have multi-line insertions, possibly with parameters
9752 ;; We allow anything beginning with AUTO, so that users can add their own
9754 (verilog-auto-re-search-do
9755 (concat "/\\*AUTO[A-Za-z0-9_]+"
9756 ;; Optional parens or quoted parameter or .* for (((...)))
9757 "\\(\\|([^)]*)\\|(\"[^\"]*\")\\).*?"
9759 'verilog-delete-autos-lined)
9760 ;; Remove those that are in parenthesis
9761 (verilog-auto-re-search-do
9764 (verilog-regexp-words
9765 `("AS" "AUTOARG" "AUTOCONCATWIDTH" "AUTOINST" "AUTOINSTPARAM"
9768 'verilog-delete-to-paren)
9769 ;; Do .* instantiations, but avoid removing any user pins by looking for our magic comments
9770 (verilog-auto-re-search-do "\\.\\*"
9771 'verilog-delete-auto-star-all)
9772 ;; Remove template comments ... anywhere in case was pasted after AUTOINST removed
9773 (goto-char (point-min))
9774 (while (re-search-forward "\\s-*// \\(Templated\\|Implicit \\.\\*\\)\\([ \tLT0-9]*\\| LHS: .*\\)?$" nil t)
9778 (verilog-run-hooks 'verilog-delete-auto-hook)))))
9784 (defun verilog-inject-auto ()
9785 "Examine legacy non-AUTO code and insert AUTOs in appropriate places.
9787 Any always @ blocks with sensitivity lists that match computed lists will
9788 be replaced with /*AS*/ comments.
9790 Any cells will get /*AUTOINST*/ added to the end of the pin list.
9791 Pins with have identical names will be deleted.
9793 Argument lists will not be deleted, /*AUTOARG*/ will only be inserted to
9794 support adding new ports. You may wish to delete older ports yourself.
9798 module ExampInject (i, o);
9809 Typing \\[verilog-inject-auto] will make this into:
9811 module ExampInject (i, o/*AUTOARG*/
9816 always @ (/*AS*/i or j)
9827 (defun verilog-inject-arg ()
9828 "Inject AUTOARG into new code. See `verilog-inject-auto'."
9829 ;; Presume one module per file.
9831 (goto-char (point-min))
9832 (while (verilog-re-search-forward-quick "\\<module\\>" nil t)
9833 (let ((endmodp (save-excursion
9834 (verilog-re-search-forward-quick "\\<endmodule\\>" nil t)
9836 ;; See if there's already a comment .. inside a comment so not verilog-re-search
9837 (when (not (re-search-forward "/\\*AUTOARG\\*/" endmodp t))
9838 (verilog-re-search-forward-quick ";" nil t)
9840 (verilog-backward-syntactic-ws-quick)
9841 (backward-char 1) ; Moves to paren that closes argdecl's
9842 (when (looking-at ")")
9843 (verilog-insert "/*AUTOARG*/")))))))
9845 (defun verilog-inject-sense ()
9846 "Inject AUTOSENSE into new code. See `verilog-inject-auto'."
9848 (goto-char (point-min))
9849 (while (verilog-re-search-forward-quick "\\<always\\s *@\\s *(" nil t)
9850 (let* ((start-pt (point))
9851 (modi (verilog-modi-current))
9852 (moddecls (verilog-modi-get-decls modi))
9856 (verilog-forward-sexp-ign-cmt 1)
9857 (backward-char 1) ;; End )
9858 (when (not (verilog-re-search-backward-quick "/\\*\\(AUTOSENSE\\|AS\\)\\*/" start-pt t))
9859 (setq pre-sigs (verilog-signals-from-signame
9860 (verilog-read-signals start-pt (point)))
9861 got-sigs (verilog-auto-sense-sigs moddecls nil))
9862 (when (not (or (verilog-signals-not-in pre-sigs got-sigs) ; Both are equal?
9863 (verilog-signals-not-in got-sigs pre-sigs)))
9864 (delete-region start-pt (point))
9865 (verilog-insert "/*AS*/")))))))
9867 (defun verilog-inject-inst ()
9868 "Inject AUTOINST into new code. See `verilog-inject-auto'."
9870 (goto-char (point-min))
9871 ;; It's hard to distinguish modules; we'll instead search for pins.
9872 (while (verilog-re-search-forward-quick "\\.\\s *[a-zA-Z0-9`_\$]+\\s *(\\s *[a-zA-Z0-9`_\$]+\\s *)" nil t)
9873 (verilog-backward-open-paren) ;; Inst start
9875 ((= (preceding-char) ?\#) ;; #(...) parameter section, not pin. Skip.
9877 (verilog-forward-close-paren)) ;; Parameters done
9880 (let ((indent-pt (+ (current-column)))
9881 (end-pt (save-excursion (verilog-forward-close-paren) (point))))
9882 (cond ((verilog-re-search-forward-quick "\\(/\\*AUTOINST\\*/\\|\\.\\*\\)" end-pt t)
9883 (goto-char end-pt)) ;; Already there, continue search with next instance
9885 ;; Delete identical interconnect
9886 (let ((case-fold-search nil)) ;; So we don't convert upper-to-lower, etc
9887 (while (verilog-re-search-forward-quick "\\.\\s *\\([a-zA-Z0-9`_\$]+\\)*\\s *(\\s *\\1\\s *)\\s *" end-pt t)
9888 (delete-region (match-beginning 0) (match-end 0))
9889 (setq end-pt (- end-pt (- (match-end 0) (match-beginning 0)))) ;; Keep it correct
9890 (while (or (looking-at "[ \t\n\f,]+")
9891 (looking-at "//[^\n]*"))
9892 (delete-region (match-beginning 0) (match-end 0))
9893 (setq end-pt (- end-pt (- (match-end 0) (match-beginning 0)))))))
9894 (verilog-forward-close-paren)
9896 ;; Not verilog-re-search, as we don't want to strip comments
9897 (while (re-search-backward "[ \t\n\f]+" (- (point) 1) t)
9898 (delete-region (match-beginning 0) (match-end 0)))
9899 (verilog-insert "\n")
9900 (verilog-insert-indent "/*AUTOINST*/")))))))))
9906 (defun verilog-diff-buffers-p (b1 b2 &optional whitespace)
9907 "Return nil if buffers B1 and B2 have same contents.
9908 Else, return point in B1 that first mismatches.
9909 If optional WHITESPACE true, ignore whitespace."
9911 (let* ((case-fold-search nil) ;; compare-buffer-substrings cares
9912 (p1 (with-current-buffer b1 (goto-char (point-min))))
9913 (p2 (with-current-buffer b2 (goto-char (point-min))))
9914 (maxp1 (with-current-buffer b1 (point-max)))
9915 (maxp2 (with-current-buffer b2 (point-max)))
9918 (while (not (and (eq p1 op1) (eq p2 op2)))
9919 ;; If both windows have whitespace optionally skip over it.
9921 ;; skip-syntax-* doesn't count \n
9922 (with-current-buffer b1
9924 (skip-chars-forward " \t\n\r\f\v")
9926 (with-current-buffer b2
9928 (skip-chars-forward " \t\n\r\f\v")
9930 (setq size (min (- maxp1 p1) (- maxp2 p2)))
9931 (setq progress (compare-buffer-substrings b2 p2 (+ size p2)
9933 (setq progress (if (zerop progress) size (1- (abs progress))))
9936 p2 (+ p2 progress)))
9938 (if (and (eq p1 maxp1) (eq p2 maxp2))
9941 (defun verilog-diff-file-with-buffer (f1 b2 &optional whitespace show)
9942 "View the differences between file F1 and buffer B2.
9943 This requires the external program `diff-command' to be in your `exec-path',
9944 and uses `diff-switches' in which you may want to have \"-u\" flag.
9945 Ignores WHITESPACE if t, and writes output to stdout if SHOW."
9946 ;; Similar to `diff-buffer-with-file' but works on XEmacs, and doesn't
9947 ;; call `diff' as `diff' has different calling semantics on different
9948 ;; versions of Emacs.
9949 (if (not (file-exists-p f1))
9950 (message "Buffer %s has no associated file on disc" (buffer-name b2))
9951 (with-temp-buffer "*Verilog-Diff*"
9952 (let ((outbuf (current-buffer))
9953 (f2 (make-temp-file "vm-diff-auto-")))
9956 (with-current-buffer b2
9959 (write-region (point-min) (point-max) f2 nil 'nomessage)))
9960 (call-process diff-command nil outbuf t
9961 diff-switches ;; User may want -u in diff-switches
9962 (if whitespace "-b" "")
9964 ;; Print out results. Alternatively we could have call-processed
9965 ;; ourself, but this way we can reuse diff switches
9967 (with-current-buffer outbuf (message "%s" (buffer-string))))))
9969 (when (file-exists-p f2)
9970 (delete-file f2))))))
9972 (defun verilog-diff-report (b1 b2 diffpt)
9973 "Report differences detected with `verilog-diff-auto'.
9974 Differences are between buffers B1 and B2, starting at point
9975 DIFFPT. This function is called via `verilog-diff-function'."
9976 (let ((name1 (with-current-buffer b1 (buffer-file-name))))
9977 (message "%%Warning: %s:%d: Difference in AUTO expansion found"
9978 name1 (with-current-buffer b1 (1+ (count-lines (point-min) (point)))))
9979 (cond (noninteractive
9980 (verilog-diff-file-with-buffer name1 b2 t t))
9982 (ediff-buffers b1 b2)))))
9984 (defun verilog-diff-auto ()
9985 "Expand AUTOs in a temporary buffer and indicate any changes.
9986 Whitespace differences are ignored to determine identicalness, but
9987 once a difference is detected, whitespace differences may be shown.
9989 To call this from the command line, see \\[verilog-batch-diff-auto].
9991 The action on differences is selected with
9992 `verilog-diff-function'. The default is `verilog-diff-report'
9993 which will report an error and run `ediff' in interactive mode,
9994 or `diff' in batch mode."
9996 (let ((b1 (current-buffer)) b2 diffpt
9997 (name1 (buffer-file-name))
9998 (newname "*Verilog-Diff*"))
10000 (when (get-buffer newname)
10001 (kill-buffer newname))
10002 (setq b2 (let (buffer-file-name) ;; Else clone is upset
10003 (clone-buffer newname)))
10004 (with-current-buffer b2
10005 ;; auto requires the filename, but can't have same filename in two
10006 ;; buffers; so override both b1 and b2's names
10007 (let ((buffer-file-name name1))
10010 (with-current-buffer b1 (setq buffer-file-name nil))
10012 (when (not verilog-auto-star-save)
10013 (verilog-delete-auto-star-implicit)))
10014 ;; Restore name if unwind
10015 (with-current-buffer b1 (setq buffer-file-name name1)))))
10017 (setq diffpt (verilog-diff-buffers-p b1 b2 t))
10018 (cond ((not diffpt)
10019 (unless noninteractive (message "AUTO expansion identical"))
10020 (kill-buffer newname)) ;; Nice to cleanup after oneself
10022 (funcall verilog-diff-function b1 b2 diffpt)))
10023 ;; Return result of compare
10031 (defun verilog-auto-save-check ()
10032 "On saving see if we need auto update."
10033 (cond ((not verilog-auto-save-policy)) ; disabled
10034 ((not (save-excursion
10036 (let ((case-fold-search nil))
10037 (goto-char (point-min))
10038 (re-search-forward "AUTO" nil t))))))
10039 ((eq verilog-auto-save-policy 'force)
10041 ((not (buffer-modified-p)))
10042 ((eq verilog-auto-update-tick (buffer-chars-modified-tick))) ; up-to-date
10043 ((eq verilog-auto-save-policy 'detect)
10046 (when (yes-or-no-p "AUTO statements not recomputed, do it now? ")
10048 ;; Don't ask again if didn't update
10049 (set (make-local-variable 'verilog-auto-update-tick) (buffer-chars-modified-tick))))
10050 (when (not verilog-auto-star-save)
10051 (verilog-delete-auto-star-implicit))
10052 nil) ;; Always return nil -- we don't write the file ourselves
10054 (defun verilog-auto-read-locals ()
10055 "Return file local variable segment at bottom of file."
10057 (goto-char (point-max))
10058 (if (re-search-backward "Local Variables:" nil t)
10059 (buffer-substring-no-properties (point) (point-max))
10062 (defun verilog-auto-reeval-locals (&optional force)
10063 "Read file local variable segment at bottom of file if it has changed.
10064 If FORCE, always reread it."
10065 (let ((curlocal (verilog-auto-read-locals)))
10066 (when (or force (not (equal verilog-auto-last-file-locals curlocal)))
10067 (set (make-local-variable 'verilog-auto-last-file-locals) curlocal)
10068 ;; Note this may cause this function to be recursively invoked,
10069 ;; because hack-local-variables may call (verilog-mode)
10070 ;; The above when statement will prevent it from recursing forever.
10071 (hack-local-variables)
10078 (defun verilog-auto-arg-ports (sigs message indent-pt)
10079 "Print a list of ports for a AUTOINST.
10080 Takes SIGS list, adds MESSAGE to front and inserts each at INDENT-PT."
10082 (when verilog-auto-arg-sort
10083 (setq sigs (sort (copy-alist sigs) `verilog-signals-sort-compare)))
10085 (indent-to indent-pt)
10089 (indent-to indent-pt)
10091 (cond ((> (+ 2 (current-column) (length (verilog-sig-name (car sigs)))) fill-column)
10093 (indent-to indent-pt))
10094 (t (insert space)))
10095 (insert (verilog-sig-name (car sigs)) ",")
10096 (setq sigs (cdr sigs)
10099 (defun verilog-auto-arg ()
10100 "Expand AUTOARG statements.
10101 Replace the argument declarations at the beginning of the
10102 module with ones automatically derived from input and output
10103 statements. This can be dangerous if the module is instantiated
10104 using position-based connections, so use only name-based when
10105 instantiating the resulting module. Long lines are split based
10106 on the `fill-column', see \\[set-fill-column].
10109 Concatenation and outputting partial buses is not supported.
10111 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
10115 module ExampArg (/*AUTOARG*/);
10120 Typing \\[verilog-auto] will make this into:
10122 module ExampArg (/*AUTOARG*/
10132 The argument declarations may be printed in declaration order to best suit
10133 order based instantiations, or alphabetically, based on the
10134 `verilog-auto-arg-sort' variable.
10136 Any ports declared between the ( and /*AUTOARG*/ are presumed to be
10137 predeclared and are not redeclared by AUTOARG. AUTOARG will make a
10138 conservative guess on adding a comma for the first signal, if you have
10139 any ifdefs or complicated expressions before the AUTOARG you will need
10140 to choose the comma yourself.
10142 Avoid declaring ports manually, as it makes code harder to maintain."
10144 (let* ((modi (verilog-modi-current))
10145 (moddecls (verilog-modi-get-decls modi))
10146 (skip-pins (aref (verilog-read-arg-pins) 0)))
10147 (verilog-repair-open-comma)
10148 (verilog-auto-arg-ports (verilog-signals-not-in
10149 (verilog-decls-get-outputs moddecls)
10152 verilog-indent-level-declaration)
10153 (verilog-auto-arg-ports (verilog-signals-not-in
10154 (verilog-decls-get-inouts moddecls)
10157 verilog-indent-level-declaration)
10158 (verilog-auto-arg-ports (verilog-signals-not-in
10159 (verilog-decls-get-inputs moddecls)
10162 verilog-indent-level-declaration)
10163 (verilog-repair-close-comma)
10164 (unless (eq (char-before) ?/ )
10166 (indent-to verilog-indent-level-declaration))))
10168 (defun verilog-auto-inst-port-map (port-st)
10171 (defvar vl-cell-type nil "See `verilog-auto-inst'.") ; Prevent compile warning
10172 (defvar vl-cell-name nil "See `verilog-auto-inst'.") ; Prevent compile warning
10173 (defvar vl-modport nil "See `verilog-auto-inst'.") ; Prevent compile warning
10174 (defvar vl-name nil "See `verilog-auto-inst'.") ; Prevent compile warning
10175 (defvar vl-width nil "See `verilog-auto-inst'.") ; Prevent compile warning
10176 (defvar vl-dir nil "See `verilog-auto-inst'.") ; Prevent compile warning
10177 (defvar vl-bits nil "See `verilog-auto-inst'.") ; Prevent compile warning
10178 (defvar vl-mbits nil "See `verilog-auto-inst'.") ; Prevent compile warning
10180 (defun verilog-auto-inst-port (port-st indent-pt tpl-list tpl-num for-star par-values)
10181 "Print out a instantiation connection for this PORT-ST.
10182 Insert to INDENT-PT, use template TPL-LIST.
10183 @ are instantiation numbers, replaced with TPL-NUM.
10184 @\"(expression @)\" are evaluated, with @ as a variable.
10185 If FOR-STAR add comment it is a .* expansion.
10186 If PAR-VALUES replace final strings with these parameter values."
10187 (let* ((port (verilog-sig-name port-st))
10188 (tpl-ass (or (assoc port (car tpl-list))
10189 (verilog-auto-inst-port-map port-st)))
10190 ;; vl-* are documented for user use
10191 (vl-name (verilog-sig-name port-st))
10192 (vl-width (verilog-sig-width port-st))
10193 (vl-modport (verilog-sig-modport port-st))
10194 (vl-mbits (if (verilog-sig-multidim port-st)
10195 (verilog-sig-multidim-string port-st) ""))
10196 (vl-bits (if (or verilog-auto-inst-vector
10197 (not (assoc port vector-skip-list))
10198 (not (equal (verilog-sig-bits port-st)
10199 (verilog-sig-bits (assoc port vector-skip-list)))))
10200 (or (verilog-sig-bits port-st) "")
10202 (case-fold-search nil)
10203 (check-values par-values)
10205 ;; Replace parameters in bit-width
10206 (when (and check-values
10207 (not (equal vl-bits "")))
10208 (while check-values
10209 (setq vl-bits (verilog-string-replace-matches
10210 (concat "\\<" (nth 0 (car check-values)) "\\>")
10211 (concat "(" (nth 1 (car check-values)) ")")
10213 vl-mbits (verilog-string-replace-matches
10214 (concat "\\<" (nth 0 (car check-values)) "\\>")
10215 (concat "(" (nth 1 (car check-values)) ")")
10217 check-values (cdr check-values)))
10218 (setq vl-bits (verilog-simplify-range-expression vl-bits)
10219 vl-mbits (verilog-simplify-range-expression vl-mbits)
10220 vl-width (verilog-make-width-expression vl-bits))) ; Not in the loop for speed
10221 ;; Default net value if not found
10222 (setq tpl-net (concat port
10223 (if vl-modport (concat "." vl-modport) "")
10224 (if (verilog-sig-multidim port-st)
10225 (concat "/*" vl-mbits vl-bits "*/")
10226 (concat vl-bits))))
10228 (cond (tpl-ass ; Template of exact port name
10229 (setq tpl-net (nth 1 tpl-ass)))
10230 ((nth 1 tpl-list) ; Wildcards in template, search them
10231 (let ((wildcards (nth 1 tpl-list)))
10233 (when (string-match (nth 0 (car wildcards)) port)
10234 (setq tpl-ass (car wildcards) ; so allow @ parsing
10235 tpl-net (replace-match (nth 1 (car wildcards))
10237 (setq wildcards (cdr wildcards))))))
10238 ;; Parse Templated variable
10240 ;; Evaluate @"(lispcode)"
10241 (when (string-match "@\".*[^\\]\"" tpl-net)
10242 (while (string-match "@\"\\(\\([^\\\"]*\\(\\\\.\\)*\\)*\\)\"" tpl-net)
10245 (substring tpl-net 0 (match-beginning 0))
10247 (let* ((expr (match-string 1 tpl-net))
10250 (setq expr (verilog-string-replace-matches "\\\\\"" "\"" nil nil expr))
10251 (setq expr (verilog-string-replace-matches "@" tpl-num nil nil expr))
10252 (prin1 (eval (car (read-from-string expr)))
10253 (lambda (ch) ())))))
10254 (if (numberp value) (setq value (number-to-string value)))
10256 (substring tpl-net (match-end 0))))))
10257 ;; Replace @ and [] magic variables in final output
10258 (setq tpl-net (verilog-string-replace-matches "@" tpl-num nil nil tpl-net))
10259 (setq tpl-net (verilog-string-replace-matches "\\[\\]" vl-bits nil nil tpl-net)))
10261 (indent-to indent-pt)
10263 (unless (and verilog-auto-inst-dot-name
10264 (equal port tpl-net))
10265 (indent-to verilog-auto-inst-column)
10266 (insert "(" tpl-net ")"))
10269 (indent-to (+ (if (< verilog-auto-inst-column 48) 24 16)
10270 verilog-auto-inst-column))
10271 ;; verilog-insert requires the complete comment in one call - including the newline
10272 (cond ((equal verilog-auto-inst-template-numbers `lhs)
10273 (verilog-insert " // Templated"
10274 " LHS: " (nth 0 tpl-ass)
10276 (verilog-auto-inst-template-numbers
10277 (verilog-insert " // Templated"
10278 " T" (int-to-string (nth 2 tpl-ass))
10279 " L" (int-to-string (nth 3 tpl-ass))
10282 (verilog-insert " // Templated\n"))))
10284 (indent-to (+ (if (< verilog-auto-inst-column 48) 24 16)
10285 verilog-auto-inst-column))
10286 (verilog-insert " // Implicit .\*\n")) ;For some reason the . or * must be escaped...
10289 ;;(verilog-auto-inst-port (list "foo" "[5:0]") 10 (list (list "foo" "a@\"(% (+ @ 1) 4)\"a")) "3")
10290 ;;(x "incom[@\"(+ (* 8 @) 7)\":@\"(* 8 @)\"]")
10291 ;;(x ".out (outgo[@\"(concat (+ (* 8 @) 7) \\\":\\\" ( * 8 @))\"]));")
10293 (defun verilog-auto-inst-port-list (sig-list indent-pt tpl-list tpl-num for-star par-values)
10294 "For `verilog-auto-inst' print a list of ports using `verilog-auto-inst-port'."
10295 (when verilog-auto-inst-sort
10296 (setq sig-list (sort (copy-alist sig-list) `verilog-signals-sort-compare)))
10297 (mapc (lambda (port)
10298 (verilog-auto-inst-port port indent-pt
10299 tpl-list tpl-num for-star par-values))
10302 (defun verilog-auto-inst-first ()
10303 "Insert , etc before first ever port in this instant, as part of \\[verilog-auto-inst]."
10304 ;; Do we need a trailing comma?
10305 ;; There maybe a ifdef or something similar before us. What a mess. Thus
10306 ;; to avoid trouble we only insert on preceding ) or *.
10307 ;; Insert first port on new line
10308 (insert "\n") ;; Must insert before search, so point will move forward if insert comma
10310 (verilog-re-search-backward-quick "[^ \t\n\f]" nil nil)
10311 (when (looking-at ")\\|\\*") ;; Generally don't insert, unless we are fairly sure
10315 (defun verilog-auto-star ()
10316 "Expand SystemVerilog .* pins, as part of \\[verilog-auto].
10318 If `verilog-auto-star-expand' is set, .* pins are treated if they were
10319 AUTOINST statements, otherwise they are ignored. For safety, Verilog mode
10320 will also ignore any .* that are not last in your pin list (this prevents
10321 it from deleting pins following the .* when it expands the AUTOINST.)
10323 On writing your file, unless `verilog-auto-star-save' is set, any
10324 non-templated expanded pins will be removed. You may do this at any time
10325 with \\[verilog-delete-auto-star-implicit].
10327 If you are converting a module to use .* for the first time, you may wish
10328 to use \\[verilog-inject-auto] and then replace the created AUTOINST with .*.
10330 See `verilog-auto-inst' for examples, templates, and more information."
10331 (when (verilog-auto-star-safe)
10332 (verilog-auto-inst)))
10334 (defun verilog-auto-inst ()
10335 "Expand AUTOINST statements, as part of \\[verilog-auto].
10336 Replace the pin connections to an instantiation or interface
10337 declaration with ones automatically derived from the module or
10338 interface header of the instantiated item.
10340 If `verilog-auto-star-expand' is set, also expand SystemVerilog .* ports,
10341 and delete them before saving unless `verilog-auto-star-save' is set.
10342 See `verilog-auto-star' for more information.
10344 The pins are printed in declaration order or alphabetically,
10345 based on the `verilog-auto-inst-sort' variable.
10348 Module names must be resolvable to filenames by adding a
10349 `verilog-library-extensions', and being found in the same directory, or
10350 by changing the variable `verilog-library-flags' or
10351 `verilog-library-directories'. Macros `modname are translated through the
10352 vh-{name} Emacs variable, if that is not found, it just ignores the `.
10354 In templates you must have one signal per line, ending in a ), or ));,
10355 and have proper () nesting, including a final ); to end the template.
10357 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
10359 SystemVerilog multidimensional input/output has only experimental support.
10361 SystemVerilog .name syntax is used if `verilog-auto-inst-dot-name' is set.
10363 Parameters referenced by the instantiation will remain symbolic, unless
10364 `verilog-auto-inst-param-value' is set.
10366 Gate primitives (and/or) may have AUTOINST for the purpose of
10367 AUTOWIRE declarations, etc. Gates are the only case when
10368 position based connections are passed.
10370 For example, first take the submodule InstModule.v:
10372 module InstModule (o,i);
10375 wire [31:0] o = {32{i}};
10378 This is then used in a upper level module:
10380 module ExampInst (o,i);
10383 InstModule instName
10387 Typing \\[verilog-auto] will make this into:
10389 module ExampInst (o,i);
10392 InstModule instName
10400 Where the list of inputs and outputs came from the inst module.
10404 Unless you are instantiating a module multiple times, or the module is
10405 something trivial like an adder, DO NOT CHANGE SIGNAL NAMES ACROSS HIERARCHY.
10406 It just makes for unmaintainable code. To sanitize signal names, try
10407 vrename from URL `http://www.veripool.org'.
10409 When you need to violate this suggestion there are two ways to list
10410 exceptions, placing them before the AUTOINST, or using templates.
10412 Any ports defined before the /*AUTOINST*/ are not included in the list of
10413 automatics. This is similar to making a template as described below, but
10414 is restricted to simple connections just like you normally make. Also note
10415 that any signals before the AUTOINST will only be picked up by AUTOWIRE if
10416 you have the appropriate // Input or // Output comment, and exactly the
10417 same line formatting as AUTOINST itself uses.
10419 InstModule instName
10421 .i (my_i_dont_mess_with_it),
10429 For multiple instantiations based upon a single template, create a
10430 commented out template:
10432 /* InstModule AUTO_TEMPLATE (
10437 Templates go ABOVE the instantiation(s). When an instantiation is
10438 expanded `verilog-mode' simply searches up for the closest template.
10439 Thus you can have multiple templates for the same module, just alternate
10440 between the template for an instantiation and the instantiation itself.
10442 The module name must be the same as the name of the module in the
10443 instantiation name, and the code \"AUTO_TEMPLATE\" must be in these exact
10444 words and capitalized. Only signals that must be different for each
10445 instantiation need to be listed.
10447 Inside a template, a [] in a connection name (with nothing else inside
10448 the brackets) will be replaced by the same bus subscript as it is being
10449 connected to, or the [] will be removed if it is a single bit signal.
10450 Generally it is a good idea to do this for all connections in a template,
10451 as then they will work for any width signal, and with AUTOWIRE. See
10452 PTL_BUS becoming PTL_BUSNEW below.
10454 If you have a complicated template, set `verilog-auto-inst-template-numbers'
10455 to see which regexps are matching. Don't leave that mode set after
10456 debugging is completed though, it will result in lots of extra differences
10457 and merge conflicts.
10461 /* InstModule AUTO_TEMPLATE (
10462 .ptl_bus (ptl_busnew[]),
10465 InstModule ms2m (/*AUTOINST*/);
10467 Typing \\[verilog-auto] will make this into:
10469 InstModule ms2m (/*AUTOINST*/
10471 .NotInTemplate (NotInTemplate),
10472 .ptl_bus (ptl_busnew[3:0]), // Templated
10476 Multiple Module Templates:
10478 The same template lines can be applied to multiple modules with
10479 the syntax as follows:
10481 /* InstModuleA AUTO_TEMPLATE
10482 InstModuleB AUTO_TEMPLATE
10483 InstModuleC AUTO_TEMPLATE
10484 InstModuleD AUTO_TEMPLATE (
10485 .ptl_bus (ptl_busnew[]),
10489 Note there is only one AUTO_TEMPLATE opening parenthesis.
10493 It is common to instantiate a cell multiple times, so templates make it
10494 trivial to substitute part of the cell name into the connection name.
10496 /* InstName AUTO_TEMPLATE <optional \"REGEXP\"> (
10498 .sig2 (sigy[@\"(% (+ 1 @) 4)\"]),
10502 If no regular expression is provided immediately after the AUTO_TEMPLATE
10503 keyword, then the @ character in any connection names will be replaced
10504 with the instantiation number; the first digits found in the cell's
10505 instantiation name.
10507 If a regular expression is provided, the @ character will be replaced
10508 with the first \(\) grouping that matches against the cell name. Using a
10509 regexp of \"\\([0-9]+\\)\" provides identical values for @ as when no
10510 regexp is provided. If you use multiple layers of parenthesis,
10511 \"test\\([^0-9]+\\)_\\([0-9]+\\)\" would replace @ with non-number
10512 characters after test and before _, whereas
10513 \"\\(test\\([a-z]+\\)_\\([0-9]+\\)\\)\" would replace @ with the entire
10518 /* InstModule AUTO_TEMPLATE (
10519 .ptl_mapvalidx (ptl_mapvalid[@]),
10520 .ptl_mapvalidp1x (ptl_mapvalid[@\"(% (+ 1 @) 4)\"]),
10523 InstModule ms2m (/*AUTOINST*/);
10525 Typing \\[verilog-auto] will make this into:
10527 InstModule ms2m (/*AUTOINST*/
10529 .ptl_mapvalidx (ptl_mapvalid[2]),
10530 .ptl_mapvalidp1x (ptl_mapvalid[3]));
10532 Note the @ character was replaced with the 2 from \"ms2m\".
10534 Alternatively, using a regular expression for @:
10536 /* InstModule AUTO_TEMPLATE \"_\\([a-z]+\\)\" (
10537 .ptl_mapvalidx (@_ptl_mapvalid),
10538 .ptl_mapvalidp1x (ptl_mapvalid_@),
10541 InstModule ms2_FOO (/*AUTOINST*/);
10542 InstModule ms2_BAR (/*AUTOINST*/);
10544 Typing \\[verilog-auto] will make this into:
10546 InstModule ms2_FOO (/*AUTOINST*/
10548 .ptl_mapvalidx (FOO_ptl_mapvalid),
10549 .ptl_mapvalidp1x (ptl_mapvalid_FOO));
10550 InstModule ms2_BAR (/*AUTOINST*/
10552 .ptl_mapvalidx (BAR_ptl_mapvalid),
10553 .ptl_mapvalidp1x (ptl_mapvalid_BAR));
10558 A template entry of the form
10560 .pci_req\\([0-9]+\\)_l (pci_req_jtag_[\\1]),
10562 will apply an Emacs style regular expression search for any port beginning
10563 in pci_req followed by numbers and ending in _l and connecting that to
10564 the pci_req_jtag_[] net, with the bus subscript coming from what matches
10565 inside the first set of \\( \\). Thus pci_req2_l becomes pci_req_jtag_[2].
10567 Since \\([0-9]+\\) is so common and ugly to read, a @ in the port name
10568 does the same thing. (Note a @ in the connection/replacement text is
10569 completely different -- still use \\1 there!) Thus this is the same as
10570 the above template:
10572 .pci_req@_l (pci_req_jtag_[\\1]),
10574 Here's another example to remove the _l, useful when naming conventions
10575 specify _ alone to mean active low. Note the use of [] to keep the bus
10578 .\\(.*\\)_l (\\1_[]),
10582 First any regular expression template is expanded.
10584 If the syntax @\"( ... )\" is found in a connection, the expression in
10585 quotes will be evaluated as a Lisp expression, with @ replaced by the
10586 instantiation number. The MAPVALIDP1X example above would put @+1 modulo
10587 4 into the brackets. Quote all double-quotes inside the expression with
10588 a leading backslash (\\\"...\\\"); or if the Lisp template is also a
10589 regexp template backslash the backslash quote (\\\\\"...\\\\\").
10591 There are special variables defined that are useful in these
10594 vl-name Name portion of the input/output port.
10595 vl-bits Bus bits portion of the input/output port ('[2:0]').
10596 vl-mbits Multidimensional array bits for port ('[2:0][3:0]').
10597 vl-width Width of the input/output port ('3' for [2:0]).
10598 May be a (...) expression if bits isn't a constant.
10599 vl-dir Direction of the pin input/output/inout/interface.
10600 vl-modport The modport, if an interface with a modport.
10601 vl-cell-type Module name/type of the cell ('InstModule').
10602 vl-cell-name Instance name of the cell ('instName').
10604 Normal Lisp variables may be used in expressions. See
10605 `verilog-read-defines' which can set vh-{definename} variables for use
10606 here. Also, any comments of the form:
10608 /*AUTO_LISP(setq foo 1)*/
10610 will evaluate any Lisp expression inside the parenthesis between the
10611 beginning of the buffer and the point of the AUTOINST. This allows
10612 functions to be defined or variables to be changed between instantiations.
10613 (See also `verilog-auto-insert-lisp' if you want the output from your
10614 lisp function to be inserted.)
10616 Note that when using lisp expressions errors may occur when @ is not a
10617 number; you may need to use the standard Emacs Lisp functions
10618 `number-to-string' and `string-to-number'.
10620 After the evaluation is completed, @ substitution and [] substitution
10623 For more information see the \\[verilog-faq] and forums at URL
10624 `http://www.veripool.org'."
10627 (let* ((pt (point))
10628 (for-star (save-excursion (backward-char 2) (looking-at "\\.\\*")))
10629 (indent-pt (save-excursion (verilog-backward-open-paren)
10630 (1+ (current-column))))
10631 (verilog-auto-inst-column (max verilog-auto-inst-column
10632 (+ 16 (* 8 (/ (+ indent-pt 7) 8)))))
10633 (modi (verilog-modi-current))
10634 (moddecls (verilog-modi-get-decls modi))
10635 (vector-skip-list (unless verilog-auto-inst-vector
10636 (verilog-decls-get-signals moddecls)))
10637 submod submodi submoddecls
10638 inst skip-pins tpl-list tpl-num did-first par-values)
10640 ;; Find module name that is instantiated
10641 (setq submod (verilog-read-inst-module)
10642 inst (verilog-read-inst-name)
10643 vl-cell-type submod
10645 skip-pins (aref (verilog-read-inst-pins) 0))
10647 ;; Parse any AUTO_LISP() before here
10648 (verilog-read-auto-lisp (point-min) pt)
10650 ;; Read parameters (after AUTO_LISP)
10651 (setq par-values (and verilog-auto-inst-param-value
10652 (verilog-read-inst-param-value)))
10654 ;; Lookup position, etc of submodule
10655 ;; Note this may raise an error
10656 (when (and (not (member submod verilog-gate-keywords))
10657 (setq submodi (verilog-modi-lookup submod t)))
10658 (setq submoddecls (verilog-modi-get-decls submodi))
10659 ;; If there's a number in the instantiation, it may be a argument to the
10660 ;; automatic variable instantiation program.
10661 (let* ((tpl-info (verilog-read-auto-template submod))
10662 (tpl-regexp (aref tpl-info 0)))
10663 (setq tpl-num (if (string-match tpl-regexp inst)
10664 (match-string 1 inst)
10666 tpl-list (aref tpl-info 1)))
10667 ;; Find submodule's signals and dump
10668 (let ((sig-list (and (equal (verilog-modi-get-type submodi) "interface")
10669 (verilog-signals-not-in
10670 (verilog-decls-get-vars submoddecls)
10672 (vl-dir "interfaced"))
10674 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
10675 ;; Note these are searched for in verilog-read-sub-decls.
10676 (verilog-insert-indent "// Interfaced\n")
10677 (verilog-auto-inst-port-list sig-list indent-pt
10678 tpl-list tpl-num for-star par-values)))
10679 (let ((sig-list (verilog-signals-not-in
10680 (verilog-decls-get-interfaces submoddecls)
10682 (vl-dir "interface"))
10684 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
10685 ;; Note these are searched for in verilog-read-sub-decls.
10686 (verilog-insert-indent "// Interfaces\n")
10687 (verilog-auto-inst-port-list sig-list indent-pt
10688 tpl-list tpl-num for-star par-values)))
10689 (let ((sig-list (verilog-signals-not-in
10690 (verilog-decls-get-outputs submoddecls)
10694 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
10695 (verilog-insert-indent "// Outputs\n")
10696 (verilog-auto-inst-port-list sig-list indent-pt
10697 tpl-list tpl-num for-star par-values)))
10698 (let ((sig-list (verilog-signals-not-in
10699 (verilog-decls-get-inouts submoddecls)
10703 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
10704 (verilog-insert-indent "// Inouts\n")
10705 (verilog-auto-inst-port-list sig-list indent-pt
10706 tpl-list tpl-num for-star par-values)))
10707 (let ((sig-list (verilog-signals-not-in
10708 (verilog-decls-get-inputs submoddecls)
10712 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
10713 (verilog-insert-indent "// Inputs\n")
10714 (verilog-auto-inst-port-list sig-list indent-pt
10715 tpl-list tpl-num for-star par-values)))
10719 (re-search-backward "," pt t)
10722 (search-forward "\n") ;; Added by inst-port
10724 (if (search-forward ")" nil t) ;; From user, moved up a line
10726 (if (search-forward ";" nil t) ;; Don't error if user had syntax error and forgot it
10727 (delete-char -1)))))))))
10729 (defun verilog-auto-inst-param ()
10730 "Expand AUTOINSTPARAM statements, as part of \\[verilog-auto].
10731 Replace the parameter connections to an instantiation with ones
10732 automatically derived from the module header of the instantiated netlist.
10734 See \\[verilog-auto-inst] for limitations, and templates to customize the
10737 For example, first take the submodule InstModule.v:
10739 module InstModule (o,i);
10743 This is then used in a upper level module:
10745 module ExampInst (o,i);
10747 InstModule #(/*AUTOINSTPARAM*/)
10748 instName (/*AUTOINST*/);
10751 Typing \\[verilog-auto] will make this into:
10753 module ExampInst (o,i);
10756 InstModule #(/*AUTOINSTPARAM*/
10759 instName (/*AUTOINST*/);
10762 Where the list of parameter connections come from the inst module.
10766 You can customize the parameter connections using AUTO_TEMPLATEs,
10767 just as you would with \\[verilog-auto-inst]."
10770 (let* ((pt (point))
10771 (indent-pt (save-excursion (verilog-backward-open-paren)
10772 (1+ (current-column))))
10773 (verilog-auto-inst-column (max verilog-auto-inst-column
10774 (+ 16 (* 8 (/ (+ indent-pt 7) 8)))))
10775 (modi (verilog-modi-current))
10776 (moddecls (verilog-modi-get-decls modi))
10777 (vector-skip-list (unless verilog-auto-inst-vector
10778 (verilog-decls-get-signals moddecls)))
10779 submod submodi submoddecls
10780 inst skip-pins tpl-list tpl-num did-first)
10781 ;; Find module name that is instantiated
10782 (setq submod (save-excursion
10783 ;; Get to the point where AUTOINST normally is to read the module
10784 (verilog-re-search-forward-quick "[(;]" nil nil)
10785 (verilog-read-inst-module))
10786 inst (save-excursion
10787 ;; Get to the point where AUTOINST normally is to read the module
10788 (verilog-re-search-forward-quick "[(;]" nil nil)
10789 (verilog-read-inst-name))
10790 vl-cell-type submod
10792 skip-pins (aref (verilog-read-inst-pins) 0))
10794 ;; Parse any AUTO_LISP() before here
10795 (verilog-read-auto-lisp (point-min) pt)
10797 ;; Lookup position, etc of submodule
10798 ;; Note this may raise an error
10799 (when (setq submodi (verilog-modi-lookup submod t))
10800 (setq submoddecls (verilog-modi-get-decls submodi))
10801 ;; If there's a number in the instantiation, it may be a argument to the
10802 ;; automatic variable instantiation program.
10803 (let* ((tpl-info (verilog-read-auto-template submod))
10804 (tpl-regexp (aref tpl-info 0)))
10805 (setq tpl-num (if (string-match tpl-regexp inst)
10806 (match-string 1 inst)
10808 tpl-list (aref tpl-info 1)))
10809 ;; Find submodule's signals and dump
10810 (let ((sig-list (verilog-signals-not-in
10811 (verilog-decls-get-gparams submoddecls)
10813 (vl-dir "parameter"))
10815 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
10816 ;; Note these are searched for in verilog-read-sub-decls.
10817 (verilog-insert-indent "// Parameters\n")
10818 (verilog-auto-inst-port-list sig-list indent-pt
10819 tpl-list tpl-num nil nil)))
10823 (re-search-backward "," pt t)
10826 (search-forward "\n") ;; Added by inst-port
10828 (if (search-forward ")" nil t) ;; From user, moved up a line
10829 (delete-char -1)))))))))
10831 (defun verilog-auto-reg ()
10832 "Expand AUTOREG statements, as part of \\[verilog-auto].
10833 Make reg statements for any output that isn't already declared,
10834 and isn't a wire output from a block. `verilog-auto-wire-type'
10835 may be used to change the datatype of the declarations.
10838 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
10840 This does NOT work on memories, declare those yourself.
10844 module ExampReg (o,i);
10851 Typing \\[verilog-auto] will make this into:
10853 module ExampReg (o,i);
10857 // Beginning of automatic regs (for this module's undeclared outputs)
10859 // End of automatics
10863 ;; Point must be at insertion point.
10864 (let* ((indent-pt (current-indentation))
10865 (modi (verilog-modi-current))
10866 (moddecls (verilog-modi-get-decls modi))
10867 (modsubdecls (verilog-modi-get-sub-decls modi))
10868 (sig-list (verilog-signals-not-in
10869 (verilog-decls-get-outputs moddecls)
10870 (append (verilog-decls-get-vars moddecls)
10871 (verilog-decls-get-assigns moddecls)
10872 (verilog-decls-get-consts moddecls)
10873 (verilog-decls-get-gparams moddecls)
10874 (verilog-subdecls-get-interfaced modsubdecls)
10875 (verilog-subdecls-get-outputs modsubdecls)
10876 (verilog-subdecls-get-inouts modsubdecls)))))
10879 (verilog-insert-indent "// Beginning of automatic regs (for this module's undeclared outputs)\n")
10880 (verilog-insert-definition modi sig-list "reg" indent-pt nil)
10881 (verilog-insert-indent "// End of automatics\n")))))
10883 (defun verilog-auto-reg-input ()
10884 "Expand AUTOREGINPUT statements, as part of \\[verilog-auto].
10885 Make reg statements instantiation inputs that aren't already declared.
10886 This is useful for making a top level shell for testing the module that is
10887 to be instantiated.
10890 This ONLY detects inputs of AUTOINSTants (see `verilog-read-sub-decls').
10892 This does NOT work on memories, declare those yourself.
10894 An example (see `verilog-auto-inst' for what else is going on here):
10896 module ExampRegInput (o,i);
10900 InstModule instName
10904 Typing \\[verilog-auto] will make this into:
10906 module ExampRegInput (o,i);
10910 // Beginning of automatic reg inputs (for undeclared ...
10911 reg [31:0] iv; // From inst of inst.v
10912 // End of automatics
10913 InstModule instName
10921 ;; Point must be at insertion point.
10922 (let* ((indent-pt (current-indentation))
10923 (modi (verilog-modi-current))
10924 (moddecls (verilog-modi-get-decls modi))
10925 (modsubdecls (verilog-modi-get-sub-decls modi))
10926 (sig-list (verilog-signals-combine-bus
10927 (verilog-signals-not-in
10928 (append (verilog-subdecls-get-inputs modsubdecls)
10929 (verilog-subdecls-get-inouts modsubdecls))
10930 (append (verilog-decls-get-signals moddecls)
10931 (verilog-decls-get-assigns moddecls))))))
10934 (verilog-insert-indent "// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)\n")
10935 (verilog-insert-definition modi sig-list "reg" indent-pt nil)
10936 (verilog-insert-indent "// End of automatics\n")))))
10938 (defun verilog-auto-logic ()
10939 "Expand AUTOLOGIC statements, as part of \\[verilog-auto].
10940 Make wire statements using the SystemVerilog logic keyword.
10941 This is currently equivalent to:
10945 with the below at the bottom of the file
10947 // Local Variables:
10948 // verilog-auto-logic-type:\"logic\"
10951 In the future AUTOLOGIC may declare additional identifiers,
10952 while AUTOWIRE will not."
10954 (unless verilog-auto-wire-type
10955 (set (make-local-variable 'verilog-auto-wire-type)
10957 (verilog-auto-wire)))
10959 (defun verilog-auto-wire ()
10960 "Expand AUTOWIRE statements, as part of \\[verilog-auto].
10961 Make wire statements for instantiations outputs that aren't
10962 already declared. `verilog-auto-wire-type' may be used to change
10963 the datatype of the declarations.
10966 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls'),
10967 and all buses must have widths, such as those from AUTOINST, or using []
10970 This does NOT work on memories or SystemVerilog .name connections,
10971 declare those yourself.
10973 Verilog mode will add \"Couldn't Merge\" comments to signals it cannot
10974 determine how to bus together. This occurs when you have ports with
10975 non-numeric or non-sequential bus subscripts. If Verilog mode
10976 mis-guessed, you'll have to declare them yourself.
10978 An example (see `verilog-auto-inst' for what else is going on here):
10980 module ExampWire (o,i);
10984 InstModule instName
10988 Typing \\[verilog-auto] will make this into:
10990 module ExampWire (o,i);
10994 // Beginning of automatic wires
10995 wire [31:0] ov; // From inst of inst.v
10996 // End of automatics
10997 InstModule instName
11006 ;; Point must be at insertion point.
11007 (let* ((indent-pt (current-indentation))
11008 (modi (verilog-modi-current))
11009 (moddecls (verilog-modi-get-decls modi))
11010 (modsubdecls (verilog-modi-get-sub-decls modi))
11011 (sig-list (verilog-signals-combine-bus
11012 (verilog-signals-not-in
11013 (append (verilog-subdecls-get-outputs modsubdecls)
11014 (verilog-subdecls-get-inouts modsubdecls))
11015 (verilog-decls-get-signals moddecls)))))
11018 (verilog-insert-indent "// Beginning of automatic wires (for undeclared instantiated-module outputs)\n")
11019 (verilog-insert-definition modi sig-list "wire" indent-pt nil)
11020 (verilog-insert-indent "// End of automatics\n")
11021 ;; We used to optionally call verilog-pretty-declarations and
11022 ;; verilog-pretty-expr here, but it's too slow on huge modules,
11023 ;; plus makes everyone's module change. Finally those call
11024 ;; syntax-ppss which is broken when change hooks are disabled.
11027 (defun verilog-auto-output (&optional with-params)
11028 "Expand AUTOOUTPUT statements, as part of \\[verilog-auto].
11029 Make output statements for any output signal from an /*AUTOINST*/ that
11030 isn't a input to another AUTOINST. This is useful for modules which
11031 only instantiate other modules.
11034 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
11036 If placed inside the parenthesis of a module declaration, it creates
11037 Verilog 2001 style, else uses Verilog 1995 style.
11039 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
11040 instantiation, all bets are off. (For example due to a AUTO_TEMPLATE).
11042 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
11044 Signals matching `verilog-auto-output-ignore-regexp' are not included.
11046 An example (see `verilog-auto-inst' for what else is going on here):
11048 module ExampOutput (ov,i);
11051 InstModule instName
11055 Typing \\[verilog-auto] will make this into:
11057 module ExampOutput (ov,i);
11060 // Beginning of automatic outputs (from unused autoinst outputs)
11061 output [31:0] ov; // From inst of inst.v
11062 // End of automatics
11063 InstModule instName
11071 You may also provide an optional regular expression, in which case only
11072 signals matching the regular expression will be included. For example the
11073 same expansion will result from only extracting outputs starting with ov:
11075 /*AUTOOUTPUT(\"^ov\")*/"
11077 ;; Point must be at insertion point.
11078 (let* ((indent-pt (current-indentation))
11079 (regexp (and with-params
11080 (nth 0 (verilog-read-auto-params 1))))
11081 (v2k (verilog-in-paren-quick))
11082 (modi (verilog-modi-current))
11083 (moddecls (verilog-modi-get-decls modi))
11084 (modsubdecls (verilog-modi-get-sub-decls modi))
11085 (sig-list (verilog-signals-not-in
11086 (verilog-subdecls-get-outputs modsubdecls)
11087 (append (verilog-decls-get-outputs moddecls)
11088 (verilog-decls-get-inouts moddecls)
11089 (verilog-subdecls-get-inputs modsubdecls)
11090 (verilog-subdecls-get-inouts modsubdecls)))))
11092 (setq sig-list (verilog-signals-matching-regexp
11094 (setq sig-list (verilog-signals-not-matching-regexp
11095 sig-list verilog-auto-output-ignore-regexp))
11097 (when v2k (verilog-repair-open-comma))
11099 (verilog-insert-indent "// Beginning of automatic outputs (from unused autoinst outputs)\n")
11100 (verilog-insert-definition modi sig-list "output" indent-pt v2k)
11101 (verilog-insert-indent "// End of automatics\n"))
11102 (when v2k (verilog-repair-close-comma)))))
11104 (defun verilog-auto-output-every ()
11105 "Expand AUTOOUTPUTEVERY statements, as part of \\[verilog-auto].
11106 Make output statements for any signals that aren't primary inputs or
11107 outputs already. This makes every signal in the design a output. This is
11108 useful to get Synopsys to preserve every signal in the design, since it
11109 won't optimize away the outputs.
11113 module ExampOutputEvery (o,i,tempa,tempb);
11116 /*AUTOOUTPUTEVERY*/
11118 wire tempb = tempa;
11122 Typing \\[verilog-auto] will make this into:
11124 module ExampOutputEvery (o,i,tempa,tempb);
11127 /*AUTOOUTPUTEVERY*/
11128 // Beginning of automatic outputs (every signal)
11131 // End of automatics
11133 wire tempb = tempa;
11137 ;;Point must be at insertion point
11138 (let* ((indent-pt (current-indentation))
11139 (v2k (verilog-in-paren-quick))
11140 (modi (verilog-modi-current))
11141 (moddecls (verilog-modi-get-decls modi))
11142 (sig-list (verilog-signals-combine-bus
11143 (verilog-signals-not-in
11144 (verilog-decls-get-signals moddecls)
11145 (verilog-decls-get-ports moddecls)))))
11147 (when v2k (verilog-repair-open-comma))
11149 (verilog-insert-indent "// Beginning of automatic outputs (every signal)\n")
11150 (verilog-insert-definition modi sig-list "output" indent-pt v2k)
11151 (verilog-insert-indent "// End of automatics\n"))
11152 (when v2k (verilog-repair-close-comma)))))
11154 (defun verilog-auto-input (&optional with-params)
11155 "Expand AUTOINPUT statements, as part of \\[verilog-auto].
11156 Make input statements for any input signal into an /*AUTOINST*/ that
11157 isn't declared elsewhere inside the module. This is useful for modules which
11158 only instantiate other modules.
11161 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
11163 If placed inside the parenthesis of a module declaration, it creates
11164 Verilog 2001 style, else uses Verilog 1995 style.
11166 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
11167 instantiation, all bets are off. (For example due to a AUTO_TEMPLATE).
11169 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
11171 Signals matching `verilog-auto-input-ignore-regexp' are not included.
11173 An example (see `verilog-auto-inst' for what else is going on here):
11175 module ExampInput (ov,i);
11178 InstModule instName
11182 Typing \\[verilog-auto] will make this into:
11184 module ExampInput (ov,i);
11187 // Beginning of automatic inputs (from unused autoinst inputs)
11188 input i; // From inst of inst.v
11189 // End of automatics
11190 InstModule instName
11198 You may also provide an optional regular expression, in which case only
11199 signals matching the regular expression will be included. For example the
11200 same expansion will result from only extracting inputs starting with i:
11202 /*AUTOINPUT(\"^i\")*/"
11204 (let* ((indent-pt (current-indentation))
11205 (regexp (and with-params
11206 (nth 0 (verilog-read-auto-params 1))))
11207 (v2k (verilog-in-paren-quick))
11208 (modi (verilog-modi-current))
11209 (moddecls (verilog-modi-get-decls modi))
11210 (modsubdecls (verilog-modi-get-sub-decls modi))
11211 (sig-list (verilog-signals-not-in
11212 (verilog-subdecls-get-inputs modsubdecls)
11213 (append (verilog-decls-get-inputs moddecls)
11214 (verilog-decls-get-inouts moddecls)
11215 (verilog-decls-get-vars moddecls)
11216 (verilog-decls-get-consts moddecls)
11217 (verilog-decls-get-gparams moddecls)
11218 (verilog-subdecls-get-interfaced modsubdecls)
11219 (verilog-subdecls-get-outputs modsubdecls)
11220 (verilog-subdecls-get-inouts modsubdecls)))))
11222 (setq sig-list (verilog-signals-matching-regexp
11224 (setq sig-list (verilog-signals-not-matching-regexp
11225 sig-list verilog-auto-input-ignore-regexp))
11227 (when v2k (verilog-repair-open-comma))
11229 (verilog-insert-indent "// Beginning of automatic inputs (from unused autoinst inputs)\n")
11230 (verilog-insert-definition modi sig-list "input" indent-pt v2k)
11231 (verilog-insert-indent "// End of automatics\n"))
11232 (when v2k (verilog-repair-close-comma)))))
11234 (defun verilog-auto-inout (&optional with-params)
11235 "Expand AUTOINOUT statements, as part of \\[verilog-auto].
11236 Make inout statements for any inout signal in an /*AUTOINST*/ that
11237 isn't declared elsewhere inside the module.
11240 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
11242 If placed inside the parenthesis of a module declaration, it creates
11243 Verilog 2001 style, else uses Verilog 1995 style.
11245 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
11246 instantiation, all bets are off. (For example due to a AUTO_TEMPLATE).
11248 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
11250 Signals matching `verilog-auto-inout-ignore-regexp' are not included.
11252 An example (see `verilog-auto-inst' for what else is going on here):
11254 module ExampInout (ov,i);
11257 InstModule instName
11261 Typing \\[verilog-auto] will make this into:
11263 module ExampInout (ov,i);
11266 // Beginning of automatic inouts (from unused autoinst inouts)
11267 inout [31:0] ov; // From inst of inst.v
11268 // End of automatics
11269 InstModule instName
11277 You may also provide an optional regular expression, in which case only
11278 signals matching the regular expression will be included. For example the
11279 same expansion will result from only extracting inouts starting with i:
11281 /*AUTOINOUT(\"^i\")*/"
11283 ;; Point must be at insertion point.
11284 (let* ((indent-pt (current-indentation))
11285 (regexp (and with-params
11286 (nth 0 (verilog-read-auto-params 1))))
11287 (v2k (verilog-in-paren-quick))
11288 (modi (verilog-modi-current))
11289 (moddecls (verilog-modi-get-decls modi))
11290 (modsubdecls (verilog-modi-get-sub-decls modi))
11291 (sig-list (verilog-signals-not-in
11292 (verilog-subdecls-get-inouts modsubdecls)
11293 (append (verilog-decls-get-outputs moddecls)
11294 (verilog-decls-get-inouts moddecls)
11295 (verilog-decls-get-inputs moddecls)
11296 (verilog-subdecls-get-inputs modsubdecls)
11297 (verilog-subdecls-get-outputs modsubdecls)))))
11299 (setq sig-list (verilog-signals-matching-regexp
11301 (setq sig-list (verilog-signals-not-matching-regexp
11302 sig-list verilog-auto-inout-ignore-regexp))
11304 (when v2k (verilog-repair-open-comma))
11306 (verilog-insert-indent "// Beginning of automatic inouts (from unused autoinst inouts)\n")
11307 (verilog-insert-definition modi sig-list "inout" indent-pt v2k)
11308 (verilog-insert-indent "// End of automatics\n"))
11309 (when v2k (verilog-repair-close-comma)))))
11311 (defun verilog-auto-inout-module (&optional complement all-in)
11312 "Expand AUTOINOUTMODULE statements, as part of \\[verilog-auto].
11313 Take input/output/inout statements from the specified module and insert
11314 into the current module. This is useful for making null templates and
11315 shell modules which need to have identical I/O with another module.
11316 Any I/O which are already defined in this module will not be redefined.
11317 For the complement of this function, see `verilog-auto-inout-comp',
11318 and to make monitors with all inputs, see `verilog-auto-inout-in'.
11321 If placed inside the parenthesis of a module declaration, it creates
11322 Verilog 2001 style, else uses Verilog 1995 style.
11324 Concatenation and outputting partial buses is not supported.
11326 Module names must be resolvable to filenames. See `verilog-auto-inst'.
11328 Signals are not inserted in the same order as in the original module,
11329 though they will appear to be in the same order to a AUTOINST
11330 instantiating either module.
11334 module ExampShell (/*AUTOARG*/);
11335 /*AUTOINOUTMODULE(\"ExampMain\")*/
11338 module ExampMain (i,o,io);
11344 Typing \\[verilog-auto] will make this into:
11346 module ExampShell (/*AUTOARG*/i,o,io);
11347 /*AUTOINOUTMODULE(\"ExampMain\")*/
11348 // Beginning of automatic in/out/inouts (from specific module)
11352 // End of automatics
11355 You may also provide an optional regular expression, in which case only
11356 signals matching the regular expression will be included. For example the
11357 same expansion will result from only extracting signals starting with i:
11359 /*AUTOINOUTMODULE(\"ExampMain\",\"^i\")*/
11361 You may also provide an optional second regular expression, in
11362 which case only signals which have that pin direction and data
11363 type will be included. This matches against everything before
11364 the signal name in the declaration, for example against
11365 \"input\" (single bit), \"output logic\" (direction and type) or
11366 \"output [1:0]\" (direction and implicit type). You also
11367 probably want to skip spaces in your regexp.
11369 For example, the below will result in matching the output \"o\"
11370 against the previous example's module:
11372 /*AUTOINOUTMODULE(\"ExampMain\",\"\",\"^output.*\")*/"
11374 (let* ((params (verilog-read-auto-params 1 3))
11375 (submod (nth 0 params))
11376 (regexp (nth 1 params))
11377 (direction-re (nth 2 params))
11379 ;; Lookup position, etc of co-module
11380 ;; Note this may raise an error
11381 (when (setq submodi (verilog-modi-lookup submod t))
11382 (let* ((indent-pt (current-indentation))
11383 (v2k (verilog-in-paren-quick))
11384 (modi (verilog-modi-current))
11385 (moddecls (verilog-modi-get-decls modi))
11386 (submoddecls (verilog-modi-get-decls submodi))
11387 (sig-list-i (verilog-signals-not-in
11390 (verilog-decls-get-inputs submoddecls)
11391 (verilog-decls-get-inouts submoddecls)
11392 (verilog-decls-get-outputs submoddecls)))
11394 (verilog-decls-get-outputs submoddecls))
11395 (t (verilog-decls-get-inputs submoddecls)))
11396 (append (verilog-decls-get-inputs moddecls))))
11397 (sig-list-o (verilog-signals-not-in
11400 (verilog-decls-get-inputs submoddecls))
11401 (t (verilog-decls-get-outputs submoddecls)))
11402 (append (verilog-decls-get-outputs moddecls))))
11403 (sig-list-io (verilog-signals-not-in
11405 (t (verilog-decls-get-inouts submoddecls)))
11406 (append (verilog-decls-get-inouts moddecls))))
11407 (sig-list-if (verilog-signals-not-in
11408 (verilog-decls-get-interfaces submoddecls)
11409 (append (verilog-decls-get-interfaces moddecls)))))
11411 (setq sig-list-i (verilog-signals-matching-dir-re
11412 (verilog-signals-matching-regexp sig-list-i regexp)
11413 "input" direction-re)
11414 sig-list-o (verilog-signals-matching-dir-re
11415 (verilog-signals-matching-regexp sig-list-o regexp)
11416 "output" direction-re)
11417 sig-list-io (verilog-signals-matching-dir-re
11418 (verilog-signals-matching-regexp sig-list-io regexp)
11419 "inout" direction-re)
11420 sig-list-if (verilog-signals-matching-dir-re
11421 (verilog-signals-matching-regexp sig-list-if regexp)
11422 "interface" direction-re))
11423 (when v2k (verilog-repair-open-comma))
11424 (when (or sig-list-i sig-list-o sig-list-io)
11425 (verilog-insert-indent "// Beginning of automatic in/out/inouts (from specific module)\n")
11426 ;; Don't sort them so a upper AUTOINST will match the main module
11427 (verilog-insert-definition modi sig-list-o "output" indent-pt v2k t)
11428 (verilog-insert-definition modi sig-list-io "inout" indent-pt v2k t)
11429 (verilog-insert-definition modi sig-list-i "input" indent-pt v2k t)
11430 (verilog-insert-definition modi sig-list-if "interface" indent-pt v2k t)
11431 (verilog-insert-indent "// End of automatics\n"))
11432 (when v2k (verilog-repair-close-comma)))))))
11434 (defun verilog-auto-inout-comp ()
11435 "Expand AUTOINOUTCOMP statements, as part of \\[verilog-auto].
11436 Take input/output/inout statements from the specified module and
11437 insert the inverse into the current module (inputs become outputs
11438 and vice-versa.) This is useful for making test and stimulus
11439 modules which need to have complementing I/O with another module.
11440 Any I/O which are already defined in this module will not be
11441 redefined. For the complement of this function, see
11442 `verilog-auto-inout-module'.
11445 If placed inside the parenthesis of a module declaration, it creates
11446 Verilog 2001 style, else uses Verilog 1995 style.
11448 Concatenation and outputting partial buses is not supported.
11450 Module names must be resolvable to filenames. See `verilog-auto-inst'.
11452 Signals are not inserted in the same order as in the original module,
11453 though they will appear to be in the same order to a AUTOINST
11454 instantiating either module.
11458 module ExampShell (/*AUTOARG*/);
11459 /*AUTOINOUTCOMP(\"ExampMain\")*/
11462 module ExampMain (i,o,io);
11468 Typing \\[verilog-auto] will make this into:
11470 module ExampShell (/*AUTOARG*/i,o,io);
11471 /*AUTOINOUTCOMP(\"ExampMain\")*/
11472 // Beginning of automatic in/out/inouts (from specific module)
11476 // End of automatics
11479 You may also provide an optional regular expression, in which case only
11480 signals matching the regular expression will be included. For example the
11481 same expansion will result from only extracting signals starting with i:
11483 /*AUTOINOUTCOMP(\"ExampMain\",\"^i\")*/"
11484 (verilog-auto-inout-module t nil))
11486 (defun verilog-auto-inout-in ()
11487 "Expand AUTOINOUTIN statements, as part of \\[verilog-auto].
11488 Take input/output/inout statements from the specified module and
11489 insert them as all inputs into the current module. This is
11490 useful for making monitor modules which need to see all signals
11491 as inputs based on another module. Any I/O which are already
11492 defined in this module will not be redefined. See also
11493 `verilog-auto-inout-module'.
11496 If placed inside the parenthesis of a module declaration, it creates
11497 Verilog 2001 style, else uses Verilog 1995 style.
11499 Concatenation and outputting partial buses is not supported.
11501 Module names must be resolvable to filenames. See `verilog-auto-inst'.
11503 Signals are not inserted in the same order as in the original module,
11504 though they will appear to be in the same order to a AUTOINST
11505 instantiating either module.
11509 module ExampShell (/*AUTOARG*/);
11510 /*AUTOINOUTIN(\"ExampMain\")*/
11513 module ExampMain (i,o,io);
11519 Typing \\[verilog-auto] will make this into:
11521 module ExampShell (/*AUTOARG*/i,o,io);
11522 /*AUTOINOUTIN(\"ExampMain\")*/
11523 // Beginning of automatic in/out/inouts (from specific module)
11527 // End of automatics
11530 You may also provide an optional regular expression, in which case only
11531 signals matching the regular expression will be included. For example the
11532 same expansion will result from only extracting signals starting with i:
11534 /*AUTOINOUTCOMP(\"ExampMain\",\"^i\")*/"
11535 (verilog-auto-inout-module nil t))
11537 (defun verilog-auto-insert-lisp ()
11538 "Expand AUTOINSERTLISP statements, as part of \\[verilog-auto].
11539 The Lisp code provided is called, and the Lisp code calls
11540 `insert` to insert text into the current file beginning on the
11541 line after the AUTOINSERTLISP.
11543 See also AUTO_LISP, which takes a Lisp expression and evaluates
11544 it during `verilog-auto-inst' but does not insert any text.
11548 module ExampInsertLisp;
11549 /*AUTOINSERTLISP(my-verilog-insert-hello \"world\")*/
11552 // For this example we declare the function in the
11553 // module's file itself. Often you'd define it instead
11554 // in a site-start.el or .emacs file.
11558 (defun my-verilog-insert-hello (who)
11559 (insert (concat \"initial $write(\\\"hello \" who \"\\\");\\n\")))
11563 Typing \\[verilog-auto] will call my-verilog-insert-hello and
11564 expand the above into:
11566 // Beginning of automatic insert lisp
11567 initial $write(\"hello world\");
11568 // End of automatics
11570 You can also call an external program and insert the returned
11573 /*AUTOINSERTLISP(insert (shell-command-to-string \"echo //hello\"))*/
11574 // Beginning of automatic insert lisp
11576 // End of automatics"
11578 ;; Point is at end of /*AUTO...*/
11579 (let* ((indent-pt (current-indentation))
11580 (cmd-end-pt (save-excursion (search-backward ")")
11582 (point))) ;; Closing paren
11583 (cmd-beg-pt (save-excursion (goto-char cmd-end-pt)
11584 (backward-sexp 1) ;; Inside comment
11585 (point))) ;; Beginning paren
11586 (cmd (buffer-substring-no-properties cmd-beg-pt cmd-end-pt)))
11588 ;; Some commands don't move point (like insert-file) so we always
11589 ;; add the begin/end comments, then delete it if not needed
11590 (verilog-insert-indent "// Beginning of automatic insert lisp\n")
11591 (verilog-insert-indent "// End of automatics\n")
11595 (setq verilog-scan-cache-tick nil) ;; Clear cache; inserted unknown text
11596 (verilog-delete-empty-auto-pair))))
11598 (defun verilog-auto-sense-sigs (moddecls presense-sigs)
11599 "Return list of signals for current AUTOSENSE block."
11600 (let* ((sigss (verilog-read-always-signals))
11601 (sig-list (verilog-signals-not-params
11602 (verilog-signals-not-in (verilog-alw-get-inputs sigss)
11603 (append (and (not verilog-auto-sense-include-inputs)
11604 (verilog-alw-get-outputs-delayed sigss))
11605 (and (not verilog-auto-sense-include-inputs)
11606 (verilog-alw-get-outputs-immediate sigss))
11607 (verilog-alw-get-temps sigss)
11608 (verilog-decls-get-consts moddecls)
11609 (verilog-decls-get-gparams moddecls)
11613 (defun verilog-auto-sense ()
11614 "Expand AUTOSENSE statements, as part of \\[verilog-auto].
11615 Replace the always (/*AUTOSENSE*/) sensitivity list (/*AS*/ for short)
11616 with one automatically derived from all inputs declared in the always
11617 statement. Signals that are generated within the same always block are NOT
11618 placed into the sensitivity list (see `verilog-auto-sense-include-inputs').
11619 Long lines are split based on the `fill-column', see \\[set-fill-column].
11622 Verilog does not allow memories (multidimensional arrays) in sensitivity
11623 lists. AUTOSENSE will thus exclude them, and add a /*memory or*/ comment.
11626 AUTOSENSE cannot always determine if a `define is a constant or a signal
11627 (it could be in a include file for example). If a `define or other signal
11628 is put into the AUTOSENSE list and is not desired, use the AUTO_CONSTANT
11629 declaration anywhere in the module (parenthesis are required):
11631 /* AUTO_CONSTANT ( `this_is_really_constant_dont_autosense_it ) */
11633 Better yet, use a parameter, which will be understood to be constant
11637 If AUTOSENSE makes a mistake, please report it. (First try putting
11638 a begin/end after your always!) As a workaround, if a signal that
11639 shouldn't be in the sensitivity list was, use the AUTO_CONSTANT above.
11640 If a signal should be in the sensitivity list wasn't, placing it before
11641 the /*AUTOSENSE*/ comment will prevent it from being deleted when the
11642 autos are updated (or added if it occurs there already).
11646 always @ (/*AS*/) begin
11647 /* AUTO_CONSTANT (`constant) */
11648 outin = ina | inb | `constant;
11652 Typing \\[verilog-auto] will make this into:
11654 always @ (/*AS*/ina or inb) begin
11655 /* AUTO_CONSTANT (`constant) */
11656 outin = ina | inb | `constant;
11660 Note in Verilog 2001, you can often get the same result from the new @*
11661 operator. (This was added to the language in part due to AUTOSENSE!)
11664 outin = ina | inb | `constant;
11669 (let* ((start-pt (save-excursion
11670 (verilog-re-search-backward-quick "(" nil t)
11672 (indent-pt (save-excursion
11673 (or (and (goto-char start-pt) (1+ (current-column)))
11674 (current-indentation))))
11675 (modi (verilog-modi-current))
11676 (moddecls (verilog-modi-get-decls modi))
11677 (sig-memories (verilog-signals-memory
11678 (verilog-decls-get-vars moddecls)))
11679 sig-list not-first presense-sigs)
11680 ;; Read signals in always, eliminate outputs from sense list
11681 (setq presense-sigs (verilog-signals-from-signame
11683 (verilog-read-signals start-pt (point)))))
11684 (setq sig-list (verilog-auto-sense-sigs moddecls presense-sigs))
11686 (let ((tlen (length sig-list)))
11687 (setq sig-list (verilog-signals-not-in sig-list sig-memories))
11688 (if (not (eq tlen (length sig-list))) (verilog-insert " /*memory or*/ "))))
11689 (if (and presense-sigs ;; Add a "or" if not "(.... or /*AUTOSENSE*/"
11690 (save-excursion (goto-char (point))
11691 (verilog-re-search-backward-quick "[a-zA-Z0-9$_.%`]+" start-pt t)
11692 (verilog-re-search-backward-quick "\\s-" start-pt t)
11693 (while (looking-at "\\s-`endif")
11694 (verilog-re-search-backward-quick "[a-zA-Z0-9$_.%`]+" start-pt t)
11695 (verilog-re-search-backward-quick "\\s-" start-pt t))
11696 (not (looking-at "\\s-or\\b"))))
11697 (setq not-first t))
11698 (setq sig-list (sort sig-list `verilog-signals-sort-compare))
11700 (cond ((> (+ 4 (current-column) (length (verilog-sig-name (car sig-list)))) fill-column) ;+4 for width of or
11702 (indent-to indent-pt)
11703 (if not-first (insert "or ")))
11704 (not-first (insert " or ")))
11705 (insert (verilog-sig-name (car sig-list)))
11706 (setq sig-list (cdr sig-list)
11709 (defun verilog-auto-reset ()
11710 "Expand AUTORESET statements, as part of \\[verilog-auto].
11711 Replace the /*AUTORESET*/ comment with code to initialize all
11712 registers set elsewhere in the always block.
11715 AUTORESET will not clear memories.
11717 AUTORESET uses <= if the signal has a <= assignment in the block,
11720 If <= is used, all = assigned variables are ignored if
11721 `verilog-auto-reset-blocking-in-non' is nil; they are presumed
11724 /*AUTORESET*/ presumes that any signals mentioned between the previous
11725 begin/case/if statement and the AUTORESET comment are being reset manually
11726 and should not be automatically reset. This includes omitting any signals
11727 used on the right hand side of assignments.
11729 By default, AUTORESET will include the width of the signal in the autos,
11730 this is a recent change. To control this behavior, see
11731 `verilog-auto-reset-widths'.
11733 AUTORESET ties signals to deasserted, which is presumed to be zero.
11734 Signals that match `verilog-active-low-regexp' will be deasserted by tying
11739 always @(posedge clk or negedge reset_l) begin
11740 if (!reset_l) begin
11751 Typing \\[verilog-auto] will make this into:
11753 always @(posedge core_clk or negedge reset_l) begin
11754 if (!reset_l) begin
11757 // Beginning of autoreset for uninitialized flops
11759 b = 0; // if `verilog-auto-reset-blocking-in-non' true
11760 // End of automatics
11772 (let* ((indent-pt (current-indentation))
11773 (modi (verilog-modi-current))
11774 (moddecls (verilog-modi-get-decls modi))
11775 (all-list (verilog-decls-get-signals moddecls))
11776 sigss sig-list dly-list prereset-sigs)
11777 ;; Read signals in always, eliminate outputs from reset list
11778 (setq prereset-sigs (verilog-signals-from-signame
11780 (verilog-read-signals
11782 (verilog-re-search-backward-quick "\\(@\\|\\<begin\\>\\|\\<if\\>\\|\\<case\\>\\)" nil t)
11786 (verilog-re-search-backward-quick "@" nil t)
11787 (setq sigss (verilog-read-always-signals)))
11788 (setq dly-list (verilog-alw-get-outputs-delayed sigss))
11789 (setq sig-list (verilog-signals-not-in (append
11790 (verilog-alw-get-outputs-delayed sigss)
11791 (when (or (not (verilog-alw-get-uses-delayed sigss))
11792 verilog-auto-reset-blocking-in-non)
11793 (verilog-alw-get-outputs-immediate sigss)))
11795 (verilog-alw-get-temps sigss)
11797 (setq sig-list (sort sig-list `verilog-signals-sort-compare))
11800 (verilog-insert-indent "// Beginning of autoreset for uninitialized flops\n");
11802 (let ((sig (or (assoc (verilog-sig-name (car sig-list)) all-list) ;; As sig-list has no widths
11804 (indent-to indent-pt)
11805 (insert (verilog-sig-name sig)
11806 (if (assoc (verilog-sig-name sig) dly-list)
11807 (concat " <= " verilog-assignment-delay)
11809 (verilog-sig-tieoff sig (not verilog-auto-reset-widths))
11811 (setq sig-list (cdr sig-list))))
11812 (verilog-insert-indent "// End of automatics")))))
11814 (defun verilog-auto-tieoff ()
11815 "Expand AUTOTIEOFF statements, as part of \\[verilog-auto].
11816 Replace the /*AUTOTIEOFF*/ comment with code to wire-tie all unused output
11817 signals to deasserted.
11819 /*AUTOTIEOFF*/ is used to make stub modules; modules that have the same
11820 input/output list as another module, but no internals. Specifically, it
11821 finds all outputs in the module, and if that input is not otherwise declared
11822 as a register or wire, creates a tieoff.
11824 AUTORESET ties signals to deasserted, which is presumed to be zero.
11825 Signals that match `verilog-active-low-regexp' will be deasserted by tying
11828 You can add signals you do not want included in AUTOTIEOFF with
11829 `verilog-auto-tieoff-ignore-regexp'.
11831 `verilog-auto-wire-type' may be used to change the datatype of
11834 An example of making a stub for another module:
11836 module ExampStub (/*AUTOINST*/);
11837 /*AUTOINOUTMODULE(\"Foo\")*/
11839 // verilator lint_off UNUSED
11840 wire _unused_ok = &{1'b0,
11843 // verilator lint_on UNUSED
11846 Typing \\[verilog-auto] will make this into:
11848 module ExampStub (/*AUTOINST*/...);
11849 /*AUTOINOUTMODULE(\"Foo\")*/
11850 // Beginning of autotieoff
11852 // End of automatics
11855 // Beginning of autotieoff
11856 wire [2:0] foo = 3'b0;
11857 // End of automatics
11863 (let* ((indent-pt (current-indentation))
11864 (modi (verilog-modi-current))
11865 (moddecls (verilog-modi-get-decls modi))
11866 (modsubdecls (verilog-modi-get-sub-decls modi))
11867 (sig-list (verilog-signals-not-in
11868 (verilog-decls-get-outputs moddecls)
11869 (append (verilog-decls-get-vars moddecls)
11870 (verilog-decls-get-assigns moddecls)
11871 (verilog-decls-get-consts moddecls)
11872 (verilog-decls-get-gparams moddecls)
11873 (verilog-subdecls-get-interfaced modsubdecls)
11874 (verilog-subdecls-get-outputs modsubdecls)
11875 (verilog-subdecls-get-inouts modsubdecls)))))
11876 (setq sig-list (verilog-signals-not-matching-regexp
11877 sig-list verilog-auto-tieoff-ignore-regexp))
11880 (verilog-insert-indent "// Beginning of automatic tieoffs (for this module's unterminated outputs)\n")
11881 (setq sig-list (sort (copy-alist sig-list) `verilog-signals-sort-compare))
11882 (verilog-modi-cache-add-vars modi sig-list) ; Before we trash list
11884 (let ((sig (car sig-list)))
11885 (cond ((equal verilog-auto-tieoff-declaration "assign")
11886 (indent-to indent-pt)
11887 (insert "assign " (verilog-sig-name sig)))
11889 (verilog-insert-one-definition sig verilog-auto-tieoff-declaration indent-pt)))
11890 (indent-to (max 48 (+ indent-pt 40)))
11891 (insert "= " (verilog-sig-tieoff sig)
11893 (setq sig-list (cdr sig-list))))
11894 (verilog-insert-indent "// End of automatics\n")))))
11896 (defun verilog-auto-unused ()
11897 "Expand AUTOUNUSED statements, as part of \\[verilog-auto].
11898 Replace the /*AUTOUNUSED*/ comment with a comma separated list of all unused
11899 input and inout signals.
11901 /*AUTOUNUSED*/ is used to make stub modules; modules that have the same
11902 input/output list as another module, but no internals. Specifically, it
11903 finds all inputs and inouts in the module, and if that input is not otherwise
11904 used, adds it to a comma separated list.
11906 The comma separated list is intended to be used to create a _unused_ok
11907 signal. Using the exact name \"_unused_ok\" for name of the temporary
11908 signal is recommended as it will insure maximum forward compatibility, it
11909 also makes lint warnings easy to understand; ignore any unused warnings
11910 with \"unused\" in the signal name.
11912 To reduce simulation time, the _unused_ok signal should be forced to a
11913 constant to prevent wiggling. The easiest thing to do is use a
11914 reduction-and with 1'b0 as shown.
11916 This way all unused signals are in one place, making it convenient to add
11917 your tool's specific pragmas around the assignment to disable any unused
11920 You can add signals you do not want included in AUTOUNUSED with
11921 `verilog-auto-unused-ignore-regexp'.
11923 An example of making a stub for another module:
11925 module ExampStub (/*AUTOINST*/);
11926 /*AUTOINOUTMODULE(\"Examp\")*/
11928 // verilator lint_off UNUSED
11929 wire _unused_ok = &{1'b0,
11932 // verilator lint_on UNUSED
11935 Typing \\[verilog-auto] will make this into:
11938 // verilator lint_off UNUSED
11939 wire _unused_ok = &{1'b0,
11941 // Beginning of automatics
11945 // End of automatics
11947 // verilator lint_on UNUSED
11952 (let* ((indent-pt (progn (search-backward "/*") (current-column)))
11953 (modi (verilog-modi-current))
11954 (moddecls (verilog-modi-get-decls modi))
11955 (modsubdecls (verilog-modi-get-sub-decls modi))
11956 (sig-list (verilog-signals-not-in
11957 (append (verilog-decls-get-inputs moddecls)
11958 (verilog-decls-get-inouts moddecls))
11959 (append (verilog-subdecls-get-inputs modsubdecls)
11960 (verilog-subdecls-get-inouts modsubdecls)))))
11961 (setq sig-list (verilog-signals-not-matching-regexp
11962 sig-list verilog-auto-unused-ignore-regexp))
11965 (verilog-insert-indent "// Beginning of automatic unused inputs\n")
11966 (setq sig-list (sort (copy-alist sig-list) `verilog-signals-sort-compare))
11968 (let ((sig (car sig-list)))
11969 (indent-to indent-pt)
11970 (insert (verilog-sig-name sig) ",\n")
11971 (setq sig-list (cdr sig-list))))
11972 (verilog-insert-indent "// End of automatics\n")))))
11974 (defun verilog-enum-ascii (signm elim-regexp)
11975 "Convert an enum name SIGNM to an ascii string for insertion.
11976 Remove user provided prefix ELIM-REGEXP."
11977 (or elim-regexp (setq elim-regexp "_ DONT MATCH IT_"))
11978 (let ((case-fold-search t))
11979 ;; All upper becomes all lower for readability
11980 (downcase (verilog-string-replace-matches elim-regexp "" nil nil signm))))
11982 (defun verilog-auto-ascii-enum ()
11983 "Expand AUTOASCIIENUM statements, as part of \\[verilog-auto].
11984 Create a register to contain the ASCII decode of a enumerated signal type.
11985 This will allow trace viewers to show the ASCII name of states.
11987 First, parameters are built into a enumeration using the synopsys enum
11988 comment. The comment must be between the keyword and the symbol.
11989 \(Annoying, but that's what Synopsys's dc_shell FSM reader requires.)
11991 Next, registers which that enum applies to are also tagged with the same
11994 Finally, a AUTOASCIIENUM command is used.
11996 The first parameter is the name of the signal to be decoded.
11998 The second parameter is the name to store the ASCII code into. For the
11999 signal foo, I suggest the name _foo__ascii, where the leading _ indicates
12000 a signal that is just for simulation, and the magic characters _ascii
12001 tell viewers like Dinotrace to display in ASCII format.
12003 The third optional parameter is a string which will be removed
12004 from the state names. It defaults to "" which removes nothing.
12006 The fourth optional parameter is \"onehot\" to force one-hot
12007 decoding. If unspecified, if and only if the first parameter
12008 width is 2^(number of states in enum) and does NOT match the
12009 width of the enum, the signal is assumed to be a one hot
12010 decode. Otherwise, it's a normal encoded state vector.
12012 `verilog-auto-wire-type' may be used to change the datatype of
12017 //== State enumeration
12018 parameter [2:0] // synopsys enum state_info
12022 //== State variables
12023 reg [2:0] /* synopsys enum state_info */
12024 state_r; /* synopsys state_vector state_r */
12025 reg [2:0] /* synopsys enum state_info */
12028 /*AUTOASCIIENUM(\"state_r\", \"state_ascii_r\", \"SM_\")*/
12030 Typing \\[verilog-auto] will make this into:
12032 ... same front matter ...
12034 /*AUTOASCIIENUM(\"state_r\", \"state_ascii_r\", \"SM_\")*/
12035 // Beginning of automatic ASCII enum decoding
12036 reg [39:0] state_ascii_r; // Decode of state_r
12037 always @(state_r) begin
12039 SM_IDLE: state_ascii_r = \"idle \";
12040 SM_SEND: state_ascii_r = \"send \";
12041 SM_WAIT1: state_ascii_r = \"wait1\";
12042 default: state_ascii_r = \"%Erro\";
12045 // End of automatics"
12047 (let* ((params (verilog-read-auto-params 2 4))
12048 (undecode-name (nth 0 params))
12049 (ascii-name (nth 1 params))
12050 (elim-regexp (and (nth 2 params)
12051 (not (equal (nth 2 params) ""))
12053 (one-hot-flag (nth 3 params))
12055 (indent-pt (current-indentation))
12056 (modi (verilog-modi-current))
12057 (moddecls (verilog-modi-get-decls modi))
12059 (sig-list-consts (append (verilog-decls-get-consts moddecls)
12060 (verilog-decls-get-gparams moddecls)))
12061 (sig-list-all (append (verilog-decls-get-vars moddecls)
12062 (verilog-decls-get-outputs moddecls)
12063 (verilog-decls-get-inouts moddecls)
12064 (verilog-decls-get-inputs moddecls)))
12066 (undecode-sig (or (assoc undecode-name sig-list-all)
12067 (error "%s: Signal %s not found in design" (verilog-point-text) undecode-name)))
12068 (undecode-enum (or (verilog-sig-enum undecode-sig)
12069 (error "%s: Signal %s does not have a enum tag" (verilog-point-text) undecode-name)))
12071 (enum-sigs (verilog-signals-not-in
12072 (or (verilog-signals-matching-enum sig-list-consts undecode-enum)
12073 (error "%s: No state definitions for %s" (verilog-point-text) undecode-enum))
12077 (string-match "onehot" (or one-hot-flag ""))
12078 (and ;; width(enum) != width(sig)
12079 (or (not (verilog-sig-bits (car enum-sigs)))
12080 (not (equal (verilog-sig-width (car enum-sigs))
12081 (verilog-sig-width undecode-sig))))
12082 ;; count(enums) == width(sig)
12083 (equal (number-to-string (length enum-sigs))
12084 (verilog-sig-width undecode-sig)))))
12088 ;; Find number of ascii chars needed
12089 (let ((tmp-sigs enum-sigs))
12091 (setq enum-chars (max enum-chars (length (verilog-sig-name (car tmp-sigs))))
12092 ascii-chars (max ascii-chars (length (verilog-enum-ascii
12093 (verilog-sig-name (car tmp-sigs))
12095 tmp-sigs (cdr tmp-sigs))))
12098 (verilog-insert-indent "// Beginning of automatic ASCII enum decoding\n")
12099 (let ((decode-sig-list (list (list ascii-name (format "[%d:0]" (- (* ascii-chars 8) 1))
12100 (concat "Decode of " undecode-name) nil nil))))
12101 (verilog-insert-definition modi decode-sig-list "reg" indent-pt nil))
12103 (verilog-insert-indent "always @(" undecode-name ") begin\n")
12104 (setq indent-pt (+ indent-pt verilog-indent-level))
12105 (verilog-insert-indent "case ({" undecode-name "})\n")
12106 (setq indent-pt (+ indent-pt verilog-case-indent))
12108 (let ((tmp-sigs enum-sigs)
12109 (chrfmt (format "%%-%ds %s = \"%%-%ds\";\n"
12110 (+ (if one-hot 9 1) (max 8 enum-chars))
12111 ascii-name ascii-chars))
12112 (errname (substring "%Error" 0 (min 6 ascii-chars))))
12114 (verilog-insert-indent
12117 (concat (if one-hot "(")
12118 ;; Use enum-sigs length as that's numeric
12119 ;; verilog-sig-width undecode-sig might not be.
12120 (if one-hot (number-to-string (length enum-sigs)))
12121 ;; We use a shift instead of var[index]
12122 ;; so that a non-one hot value will show as error.
12123 (if one-hot "'b1<<")
12124 (verilog-sig-name (car tmp-sigs))
12125 (if one-hot ")") ":")
12126 (verilog-enum-ascii (verilog-sig-name (car tmp-sigs))
12128 (setq tmp-sigs (cdr tmp-sigs)))
12129 (verilog-insert-indent (format chrfmt "default:" errname)))
12131 (setq indent-pt (- indent-pt verilog-case-indent))
12132 (verilog-insert-indent "endcase\n")
12133 (setq indent-pt (- indent-pt verilog-indent-level))
12134 (verilog-insert-indent "end\n"
12135 "// End of automatics\n"))))
12137 (defun verilog-auto-templated-rel ()
12138 "Replace Templated relative line numbers with absolute line numbers.
12139 Internal use only. This hacks around the line numbers in AUTOINST Templates
12140 being different from the final output's line numbering."
12141 (let ((templateno 0) (template-line (list 0)) (buf-line 1))
12142 ;; Find line number each template is on
12143 ;; Count lines as we go, as otherwise it's O(n^2) to use count-lines
12144 (goto-char (point-min))
12145 (while (not (eobp))
12146 (when (looking-at ".*AUTO_TEMPLATE")
12147 (setq templateno (1+ templateno))
12148 (setq template-line (cons buf-line template-line)))
12149 (setq buf-line (1+ buf-line))
12151 (setq template-line (nreverse template-line))
12152 ;; Replace T# L# with absolute line number
12153 (goto-char (point-min))
12154 (while (re-search-forward " Templated T\\([0-9]+\\) L\\([0-9]+\\)" nil t)
12156 (concat " Templated "
12157 (int-to-string (+ (nth (string-to-number (match-string 1))
12159 (string-to-number (match-string 2)))))
12167 (defun verilog-auto (&optional inject) ; Use verilog-inject-auto instead of passing a arg
12168 "Expand AUTO statements.
12169 Look for any /*AUTO...*/ commands in the code, as used in
12170 instantiations or argument headers. Update the list of signals
12171 following the /*AUTO...*/ command.
12173 Use \\[verilog-delete-auto] to remove the AUTOs.
12175 Use \\[verilog-diff-auto] to see differences in AUTO expansion.
12177 Use \\[verilog-inject-auto] to insert AUTOs for the first time.
12179 Use \\[verilog-faq] for a pointer to frequently asked questions.
12181 The hooks `verilog-before-auto-hook' and `verilog-auto-hook' are
12182 called before and after this function, respectively.
12185 module ModuleName (/*AUTOARG*/);
12190 InstMod instName #(/*AUTOINSTPARAM*/) (/*AUTOINST*/);
12192 You can also update the AUTOs from the shell using:
12193 emacs --batch <filenames.v> -f verilog-batch-auto
12194 Or fix indentation with:
12195 emacs --batch <filenames.v> -f verilog-batch-indent
12196 Likewise, you can delete or inject AUTOs with:
12197 emacs --batch <filenames.v> -f verilog-batch-delete-auto
12198 emacs --batch <filenames.v> -f verilog-batch-inject-auto
12199 Or check if AUTOs have the same expansion
12200 emacs --batch <filenames.v> -f verilog-batch-diff-auto
12202 Using \\[describe-function], see also:
12203 `verilog-auto-arg' for AUTOARG module instantiations
12204 `verilog-auto-ascii-enum' for AUTOASCIIENUM enumeration decoding
12205 `verilog-auto-inout-comp' for AUTOINOUTCOMP copy complemented i/o
12206 `verilog-auto-inout-in' for AUTOINOUTIN inputs for all i/o
12207 `verilog-auto-inout-module' for AUTOINOUTMODULE copying i/o from elsewhere
12208 `verilog-auto-inout' for AUTOINOUT making hierarchy inouts
12209 `verilog-auto-input' for AUTOINPUT making hierarchy inputs
12210 `verilog-auto-insert-lisp' for AUTOINSERTLISP insert code from lisp function
12211 `verilog-auto-inst' for AUTOINST instantiation pins
12212 `verilog-auto-star' for AUTOINST .* SystemVerilog pins
12213 `verilog-auto-inst-param' for AUTOINSTPARAM instantiation params
12214 `verilog-auto-logic' for AUTOLOGIC declaring logic signals
12215 `verilog-auto-output' for AUTOOUTPUT making hierarchy outputs
12216 `verilog-auto-output-every' for AUTOOUTPUTEVERY making all outputs
12217 `verilog-auto-reg' for AUTOREG registers
12218 `verilog-auto-reg-input' for AUTOREGINPUT instantiation registers
12219 `verilog-auto-reset' for AUTORESET flop resets
12220 `verilog-auto-sense' for AUTOSENSE always sensitivity lists
12221 `verilog-auto-tieoff' for AUTOTIEOFF output tieoffs
12222 `verilog-auto-unused' for AUTOUNUSED unused inputs/inouts
12223 `verilog-auto-wire' for AUTOWIRE instantiation wires
12225 `verilog-read-defines' for reading `define values
12226 `verilog-read-includes' for reading `includes
12228 If you have bugs with these autos, please file an issue at
12229 URL `http://www.veripool.org/verilog-mode' or contact the AUTOAUTHOR
12230 Wilson Snyder (wsnyder@wsnyder.org)."
12232 (unless noninteractive (message "Updating AUTOs..."))
12233 (if (fboundp 'dinotrace-unannotate-all)
12234 (dinotrace-unannotate-all))
12235 (let ((oldbuf (if (not (buffer-modified-p))
12237 ;; Before version 20, match-string with font-lock returns a
12238 ;; vector that is not equal to the string. IE if on "input"
12239 ;; nil==(equal "input" (progn (looking-at "input") (match-string 0)))
12240 (fontlocked (when (and (boundp 'font-lock-mode)
12244 ;; Cache directories; we don't write new files, so can't change
12245 (verilog-dir-cache-preserving t)
12246 ;; Cache current module
12247 (verilog-modi-cache-current-enable t)
12248 (verilog-modi-cache-current-max (point-min)) ; IE it's invalid
12249 verilog-modi-cache-current)
12251 ;; Disable change hooks for speed
12252 ;; This let can't be part of above let; must restore
12253 ;; after-change-functions before font-lock resumes
12254 (verilog-save-no-change-functions
12255 (verilog-save-scan-cache
12257 ;; Wipe cache; otherwise if we AUTOed a block above this one,
12258 ;; we'll misremember we have generated IOs, confusing AUTOOUTPUT
12259 (setq verilog-modi-cache-list nil)
12260 ;; If we're not in verilog-mode, change syntax table so parsing works right
12261 (unless (eq major-mode `verilog-mode) (verilog-mode))
12262 ;; Allow user to customize
12263 (verilog-run-hooks 'verilog-before-auto-hook)
12264 ;; Try to save the user from needing to revert-file to reread file local-variables
12265 (verilog-auto-reeval-locals)
12266 (verilog-read-auto-lisp-present)
12267 (verilog-read-auto-lisp (point-min) (point-max))
12268 (verilog-getopt-flags)
12269 ;; From here on out, we can cache anything we read from disk
12270 (verilog-preserve-dir-cache
12271 ;; These two may seem obvious to do always, but on large includes it can be way too slow
12272 (when verilog-auto-read-includes
12273 (verilog-read-includes)
12274 (verilog-read-defines nil nil t))
12275 ;; This particular ordering is important
12276 ;; INST: Lower modules correct, no internal dependencies, FIRST
12277 (verilog-preserve-modi-cache
12278 ;; Clear existing autos else we'll be screwed by existing ones
12279 (verilog-delete-auto)
12280 ;; Injection if appropriate
12282 (verilog-inject-inst)
12283 (verilog-inject-sense)
12284 (verilog-inject-arg))
12286 ;; Do user inserts first, so their code can insert AUTOs
12287 ;; We may provide a AUTOINSERTLISPLAST if another cleanup pass is needed
12288 (verilog-auto-re-search-do "/\\*AUTOINSERTLISP(.*?)\\*/"
12289 'verilog-auto-insert-lisp)
12290 ;; Expand instances before need the signals the instances input/output
12291 (verilog-auto-re-search-do "/\\*AUTOINSTPARAM\\*/" 'verilog-auto-inst-param)
12292 (verilog-auto-re-search-do "/\\*AUTOINST\\*/" 'verilog-auto-inst)
12293 (verilog-auto-re-search-do "\\.\\*" 'verilog-auto-star)
12294 ;; Doesn't matter when done, but combine it with a common changer
12295 (verilog-auto-re-search-do "/\\*\\(AUTOSENSE\\|AS\\)\\*/" 'verilog-auto-sense)
12296 (verilog-auto-re-search-do "/\\*AUTORESET\\*/" 'verilog-auto-reset)
12297 ;; Must be done before autoin/out as creates a reg
12298 (verilog-auto-re-search-do "/\\*AUTOASCIIENUM([^)]*)\\*/" 'verilog-auto-ascii-enum)
12300 ;; first in/outs from other files
12301 (verilog-auto-re-search-do "/\\*AUTOINOUTMODULE([^)]*)\\*/" 'verilog-auto-inout-module)
12302 (verilog-auto-re-search-do "/\\*AUTOINOUTCOMP([^)]*)\\*/" 'verilog-auto-inout-comp)
12303 (verilog-auto-re-search-do "/\\*AUTOINOUTIN([^)]*)\\*/" 'verilog-auto-inout-in)
12304 ;; next in/outs which need previous sucked inputs first
12305 (verilog-auto-re-search-do "/\\*AUTOOUTPUT\\((\"[^\"]*\")\\)\\*/"
12306 (lambda () (verilog-auto-output t)))
12307 (verilog-auto-re-search-do "/\\*AUTOOUTPUT\\*/" 'verilog-auto-output)
12308 (verilog-auto-re-search-do "/\\*AUTOINPUT\\((\"[^\"]*\")\\)\\*/"
12309 (lambda () (verilog-auto-input t)))
12310 (verilog-auto-re-search-do "/\\*AUTOINPUT\\*/" 'verilog-auto-input)
12311 (verilog-auto-re-search-do "/\\*AUTOINOUT\\((\"[^\"]*\")\\)\\*/"
12312 (lambda () (verilog-auto-inout t)))
12313 (verilog-auto-re-search-do "/\\*AUTOINOUT\\*/" 'verilog-auto-inout)
12314 ;; Then tie off those in/outs
12315 (verilog-auto-re-search-do "/\\*AUTOTIEOFF\\*/" 'verilog-auto-tieoff)
12316 ;; Wires/regs must be after inputs/outputs
12317 (verilog-auto-re-search-do "/\\*AUTOLOGIC\\*/" 'verilog-auto-logic)
12318 (verilog-auto-re-search-do "/\\*AUTOWIRE\\*/" 'verilog-auto-wire)
12319 (verilog-auto-re-search-do "/\\*AUTOREG\\*/" 'verilog-auto-reg)
12320 (verilog-auto-re-search-do "/\\*AUTOREGINPUT\\*/" 'verilog-auto-reg-input)
12321 ;; outputevery needs AUTOOUTPUTs done first
12322 (verilog-auto-re-search-do "/\\*AUTOOUTPUTEVERY\\*/" 'verilog-auto-output-every)
12323 ;; After we've created all new variables
12324 (verilog-auto-re-search-do "/\\*AUTOUNUSED\\*/" 'verilog-auto-unused)
12325 ;; Must be after all inputs outputs are generated
12326 (verilog-auto-re-search-do "/\\*AUTOARG\\*/" 'verilog-auto-arg)
12327 ;; Fix line numbers (comments only)
12328 (when verilog-auto-inst-template-numbers
12329 (verilog-auto-templated-rel))))
12331 (verilog-run-hooks 'verilog-auto-hook)
12333 (when verilog-auto-delete-trailing-whitespace
12334 (verilog-delete-trailing-whitespace))
12336 (set (make-local-variable 'verilog-auto-update-tick) (buffer-chars-modified-tick))
12338 ;; If end result is same as when started, clear modified flag
12339 (cond ((and oldbuf (equal oldbuf (buffer-string)))
12340 (set-buffer-modified-p nil)
12341 (unless noninteractive (message "Updating AUTOs...done (no changes)")))
12342 (t (unless noninteractive (message "Updating AUTOs...done"))))
12343 ;; End of after-change protection
12347 ;; Restore font-lock
12348 (when fontlocked (font-lock-mode t))))))
12352 ;; Skeleton based code insertion
12354 (defvar verilog-template-map
12355 (let ((map (make-sparse-keymap)))
12356 (define-key map "a" 'verilog-sk-always)
12357 (define-key map "b" 'verilog-sk-begin)
12358 (define-key map "c" 'verilog-sk-case)
12359 (define-key map "f" 'verilog-sk-for)
12360 (define-key map "g" 'verilog-sk-generate)
12361 (define-key map "h" 'verilog-sk-header)
12362 (define-key map "i" 'verilog-sk-initial)
12363 (define-key map "j" 'verilog-sk-fork)
12364 (define-key map "m" 'verilog-sk-module)
12365 (define-key map "o" 'verilog-sk-ovm-class)
12366 (define-key map "p" 'verilog-sk-primitive)
12367 (define-key map "r" 'verilog-sk-repeat)
12368 (define-key map "s" 'verilog-sk-specify)
12369 (define-key map "t" 'verilog-sk-task)
12370 (define-key map "u" 'verilog-sk-uvm-class)
12371 (define-key map "w" 'verilog-sk-while)
12372 (define-key map "x" 'verilog-sk-casex)
12373 (define-key map "z" 'verilog-sk-casez)
12374 (define-key map "?" 'verilog-sk-if)
12375 (define-key map ":" 'verilog-sk-else-if)
12376 (define-key map "/" 'verilog-sk-comment)
12377 (define-key map "A" 'verilog-sk-assign)
12378 (define-key map "F" 'verilog-sk-function)
12379 (define-key map "I" 'verilog-sk-input)
12380 (define-key map "O" 'verilog-sk-output)
12381 (define-key map "S" 'verilog-sk-state-machine)
12382 (define-key map "=" 'verilog-sk-inout)
12383 (define-key map "W" 'verilog-sk-wire)
12384 (define-key map "R" 'verilog-sk-reg)
12385 (define-key map "D" 'verilog-sk-define-signal)
12387 "Keymap used in Verilog mode for smart template operations.")
12391 ;; Place the templates into Verilog Mode. They may be inserted under any key.
12392 ;; C-c C-t will be the default. If you use templates a lot, you
12393 ;; may want to consider moving the binding to another key in your .emacs
12396 ;; Note \C-c and letter are reserved for users
12397 (define-key verilog-mode-map "\C-c\C-t" verilog-template-map)
12399 ;;; ---- statement skeletons ------------------------------------------
12401 (define-skeleton verilog-sk-prompt-condition
12402 "Prompt for the loop condition."
12403 "[condition]: " str )
12405 (define-skeleton verilog-sk-prompt-init
12406 "Prompt for the loop init statement."
12407 "[initial statement]: " str )
12409 (define-skeleton verilog-sk-prompt-inc
12410 "Prompt for the loop increment statement."
12411 "[increment statement]: " str )
12413 (define-skeleton verilog-sk-prompt-name
12414 "Prompt for the name of something."
12417 (define-skeleton verilog-sk-prompt-clock
12418 "Prompt for the name of something."
12419 "name and edge of clock(s): " str)
12421 (defvar verilog-sk-reset nil)
12422 (defun verilog-sk-prompt-reset ()
12423 "Prompt for the name of a state machine reset."
12424 (setq verilog-sk-reset (read-string "name of reset: " "rst")))
12427 (define-skeleton verilog-sk-prompt-state-selector
12428 "Prompt for the name of a state machine selector."
12429 "name of selector (eg {a,b,c,d}): " str )
12431 (define-skeleton verilog-sk-prompt-output
12432 "Prompt for the name of something."
12435 (define-skeleton verilog-sk-prompt-msb
12436 "Prompt for most significant bit specification."
12437 "msb:" str & ?: & '(verilog-sk-prompt-lsb) | -1 )
12439 (define-skeleton verilog-sk-prompt-lsb
12440 "Prompt for least significant bit specification."
12443 (defvar verilog-sk-p nil)
12444 (define-skeleton verilog-sk-prompt-width
12445 "Prompt for a width specification."
12448 (setq verilog-sk-p (point))
12449 (verilog-sk-prompt-msb)
12450 (if (> (point) verilog-sk-p) "] " " ")))
12452 (defun verilog-sk-header ()
12453 "Insert a descriptive header at the top of the file.
12454 See also `verilog-header' for an alternative format."
12457 (goto-char (point-min))
12458 (verilog-sk-header-tmpl)))
12460 (define-skeleton verilog-sk-header-tmpl
12461 "Insert a comment block containing the module title, author, etc."
12463 "// -*- Mode: Verilog -*-"
12464 "\n// Filename : " (buffer-name)
12465 "\n// Description : " str
12466 "\n// Author : " (user-full-name)
12467 "\n// Created On : " (current-time-string)
12468 "\n// Last Modified By: " (user-full-name)
12469 "\n// Last Modified On: " (current-time-string)
12470 "\n// Update Count : 0"
12471 "\n// Status : Unknown, Use with caution!"
12474 (define-skeleton verilog-sk-module
12475 "Insert a module definition."
12477 > "module " '(verilog-sk-prompt-name) " (/*AUTOARG*/ ) ;" \n
12479 > (- verilog-indent-level-behavioral) "endmodule" (progn (electric-verilog-terminate-line) nil))
12481 ;;; ------------------------------------------------------------------------
12482 ;;; Define a default OVM class, with macros and new()
12483 ;;; ------------------------------------------------------------------------
12485 (define-skeleton verilog-sk-ovm-class
12486 "Insert a class definition"
12488 > "class " (setq name (skeleton-read "Name: ")) " extends " (skeleton-read "Extends: ") ";" \n
12490 > "`ovm_object_utils_begin(" name ")" \n
12491 > (- verilog-indent-level) " `ovm_object_utils_end" \n
12493 > "function new(name=\"" name "\");" \n
12494 > "super.new(name);" \n
12495 > (- verilog-indent-level) "endfunction" \n
12497 > "endclass" (progn (electric-verilog-terminate-line) nil))
12499 (define-skeleton verilog-sk-uvm-class
12500 "Insert a class definition"
12502 > "class " (setq name (skeleton-read "Name: ")) " extends " (skeleton-read "Extends: ") ";" \n
12504 > "`uvm_object_utils_begin(" name ")" \n
12505 > (- verilog-indent-level) " `uvm_object_utils_end" \n
12507 > "function new(name=\"" name "\");" \n
12508 > "super.new(name);" \n
12509 > (- verilog-indent-level) "endfunction" \n
12511 > "endclass" (progn (electric-verilog-terminate-line) nil))
12513 (define-skeleton verilog-sk-primitive
12514 "Insert a task definition."
12516 > "primitive " '(verilog-sk-prompt-name) " ( " '(verilog-sk-prompt-output) ("input:" ", " str ) " );"\n
12518 > (- verilog-indent-level-behavioral) "endprimitive" (progn (electric-verilog-terminate-line) nil))
12520 (define-skeleton verilog-sk-task
12521 "Insert a task definition."
12523 > "task " '(verilog-sk-prompt-name) & ?; \n
12527 > (- verilog-indent-level-behavioral) "end" \n
12528 > (- verilog-indent-level-behavioral) "endtask" (progn (electric-verilog-terminate-line) nil))
12530 (define-skeleton verilog-sk-function
12531 "Insert a function definition."
12533 > "function [" '(verilog-sk-prompt-width) | -1 '(verilog-sk-prompt-name) ?; \n
12537 > (- verilog-indent-level-behavioral) "end" \n
12538 > (- verilog-indent-level-behavioral) "endfunction" (progn (electric-verilog-terminate-line) nil))
12540 (define-skeleton verilog-sk-always
12541 "Insert always block. Uses the minibuffer to prompt
12542 for sensitivity list."
12544 > "always @ ( /*AUTOSENSE*/ ) begin\n"
12546 > (- verilog-indent-level-behavioral) "end" \n >
12549 (define-skeleton verilog-sk-initial
12550 "Insert an initial block."
12552 > "initial begin\n"
12554 > (- verilog-indent-level-behavioral) "end" \n > )
12556 (define-skeleton verilog-sk-specify
12557 "Insert specify block. "
12561 > (- verilog-indent-level-behavioral) "endspecify" \n > )
12563 (define-skeleton verilog-sk-generate
12564 "Insert generate block. "
12568 > (- verilog-indent-level-behavioral) "endgenerate" \n > )
12570 (define-skeleton verilog-sk-begin
12571 "Insert begin end block. Uses the minibuffer to prompt for name."
12573 > "begin" '(verilog-sk-prompt-name) \n
12575 > (- verilog-indent-level-behavioral) "end"
12578 (define-skeleton verilog-sk-fork
12579 "Insert a fork join block."
12584 > (- verilog-indent-level-behavioral) "end" \n
12587 > (- verilog-indent-level-behavioral) "end" \n
12588 > (- verilog-indent-level-behavioral) "join" \n
12592 (define-skeleton verilog-sk-case
12593 "Build skeleton case statement, prompting for the selector expression,
12594 and the case items."
12595 "[selector expression]: "
12596 > "case (" str ") " \n
12597 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n > )
12598 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil))
12600 (define-skeleton verilog-sk-casex
12601 "Build skeleton casex statement, prompting for the selector expression,
12602 and the case items."
12603 "[selector expression]: "
12604 > "casex (" str ") " \n
12605 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n > )
12606 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil))
12608 (define-skeleton verilog-sk-casez
12609 "Build skeleton casez statement, prompting for the selector expression,
12610 and the case items."
12611 "[selector expression]: "
12612 > "casez (" str ") " \n
12613 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n > )
12614 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil))
12616 (define-skeleton verilog-sk-if
12617 "Insert a skeleton if statement."
12618 > "if (" '(verilog-sk-prompt-condition) & ")" " begin" \n
12620 > (- verilog-indent-level-behavioral) "end " \n )
12622 (define-skeleton verilog-sk-else-if
12623 "Insert a skeleton else if statement."
12624 > (verilog-indent-line) "else if ("
12625 (progn (setq verilog-sk-p (point)) nil) '(verilog-sk-prompt-condition) (if (> (point) verilog-sk-p) ") " -1 ) & " begin" \n
12627 > "end" (progn (electric-verilog-terminate-line) nil))
12629 (define-skeleton verilog-sk-datadef
12630 "Common routine to get data definition."
12632 '(verilog-sk-prompt-width) | -1 ("name (RET to end):" str ", ") -2 ";" \n)
12634 (define-skeleton verilog-sk-input
12635 "Insert an input definition."
12637 > "input [" '(verilog-sk-datadef))
12639 (define-skeleton verilog-sk-output
12640 "Insert an output definition."
12642 > "output [" '(verilog-sk-datadef))
12644 (define-skeleton verilog-sk-inout
12645 "Insert an inout definition."
12647 > "inout [" '(verilog-sk-datadef))
12649 (defvar verilog-sk-signal nil)
12650 (define-skeleton verilog-sk-def-reg
12651 "Insert a reg definition."
12653 > "reg [" '(verilog-sk-prompt-width) | -1 verilog-sk-signal ";" \n (verilog-pretty-declarations) )
12655 (defun verilog-sk-define-signal ()
12656 "Insert a definition of signal under point at top of module."
12658 (let* ((sig-re "[a-zA-Z0-9_]*")
12659 (v1 (buffer-substring
12661 (skip-chars-backward sig-re)
12664 (skip-chars-forward sig-re)
12666 (if (not (member v1 verilog-keywords))
12668 (setq verilog-sk-signal v1)
12669 (verilog-beg-of-defun)
12670 (verilog-end-of-statement)
12671 (verilog-forward-syntactic-ws)
12672 (verilog-sk-def-reg)
12673 (message "signal at point is %s" v1))
12674 (message "object at point (%s) is a keyword" v1))))
12676 (define-skeleton verilog-sk-wire
12677 "Insert a wire definition."
12679 > "wire [" '(verilog-sk-datadef))
12681 (define-skeleton verilog-sk-reg
12682 "Insert a reg definition."
12684 > "reg [" '(verilog-sk-datadef))
12686 (define-skeleton verilog-sk-assign
12687 "Insert a skeleton assign statement."
12689 > "assign " '(verilog-sk-prompt-name) " = " _ ";" \n)
12691 (define-skeleton verilog-sk-while
12692 "Insert a skeleton while loop statement."
12694 > "while (" '(verilog-sk-prompt-condition) ") begin" \n
12696 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil))
12698 (define-skeleton verilog-sk-repeat
12699 "Insert a skeleton repeat loop statement."
12701 > "repeat (" '(verilog-sk-prompt-condition) ") begin" \n
12703 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil))
12705 (define-skeleton verilog-sk-for
12706 "Insert a skeleton while loop statement."
12709 '(verilog-sk-prompt-init) "; "
12710 '(verilog-sk-prompt-condition) "; "
12711 '(verilog-sk-prompt-inc)
12714 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil))
12716 (define-skeleton verilog-sk-comment
12717 "Inserts three comment lines, making a display comment."
12723 (define-skeleton verilog-sk-state-machine
12724 "Insert a state machine definition."
12725 "Name of state variable: "
12726 '(setq input "state")
12727 > "// State registers for " str | -23 \n
12728 '(setq verilog-sk-state str)
12729 > "reg [" '(verilog-sk-prompt-width) | -1 verilog-sk-state ", next_" verilog-sk-state ?; \n
12732 > "// State FF for " verilog-sk-state \n
12733 > "always @ ( " (read-string "clock:" "posedge clk") " or " (verilog-sk-prompt-reset) " ) begin" \n
12734 > "if ( " verilog-sk-reset " ) " verilog-sk-state " = 0; else" \n
12735 > verilog-sk-state " = next_" verilog-sk-state ?; \n
12736 > (- verilog-indent-level-behavioral) "end" (progn (electric-verilog-terminate-line) nil)
12738 > "// Next State Logic for " verilog-sk-state \n
12739 > "always @ ( /*AUTOSENSE*/ ) begin\n"
12740 > "case (" '(verilog-sk-prompt-state-selector) ") " \n
12741 > ("case selector: " str ": begin" \n > "next_" verilog-sk-state " = " _ ";" \n > (- verilog-indent-level-behavioral) "end" \n )
12742 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil)
12743 > (- verilog-indent-level-behavioral) "end" (progn (electric-verilog-terminate-line) nil))
12747 ;; Include file loading with mouse/return event
12749 ;; idea & first impl.: M. Rouat (eldo-mode.el)
12750 ;; second (emacs/xemacs) impl.: G. Van der Plas (spice-mode.el)
12752 (if (featurep 'xemacs)
12753 (require 'overlay))
12755 (defconst verilog-include-file-regexp
12756 "^`include\\s-+\"\\([^\n\"]*\\)\""
12757 "Regexp that matches the include file.")
12759 (defvar verilog-mode-mouse-map
12760 (let ((map (make-sparse-keymap))) ; as described in info pages, make a map
12761 (set-keymap-parent map verilog-mode-map)
12762 ;; mouse button bindings
12763 (define-key map "\r" 'verilog-load-file-at-point)
12764 (if (featurep 'xemacs)
12765 (define-key map 'button2 'verilog-load-file-at-mouse);ffap-at-mouse ?
12766 (define-key map [mouse-2] 'verilog-load-file-at-mouse))
12767 (if (featurep 'xemacs)
12768 (define-key map 'Sh-button2 'mouse-yank) ; you wanna paste don't you ?
12769 (define-key map [S-mouse-2] 'mouse-yank-at-click))
12771 "Map containing mouse bindings for `verilog-mode'.")
12774 (defun verilog-highlight-region (beg end old-len)
12775 "Colorize included files and modules in the (changed?) region.
12776 Clicking on the middle-mouse button loads them in a buffer (as in dired)."
12777 (when (or verilog-highlight-includes
12778 verilog-highlight-modules)
12780 (save-match-data ;; A query-replace may call this function - do not disturb
12781 (verilog-save-buffer-state
12782 (verilog-save-scan-cache
12785 (setq end-point (point-at-eol))
12787 (beginning-of-line) ; scan entire line
12788 ;; delete overlays existing on this line
12789 (let ((overlays (overlays-in (point) end-point)))
12792 (overlay-get (car overlays) 'detachable)
12793 (or (overlay-get (car overlays) 'verilog-include-file)
12794 (overlay-get (car overlays) 'verilog-inst-module)))
12795 (delete-overlay (car overlays)))
12796 (setq overlays (cdr overlays))))
12798 ;; make new include overlays
12799 (when verilog-highlight-includes
12800 (while (search-forward-regexp verilog-include-file-regexp end-point t)
12801 (goto-char (match-beginning 1))
12802 (let ((ov (make-overlay (match-beginning 1) (match-end 1))))
12803 (overlay-put ov 'start-closed 't)
12804 (overlay-put ov 'end-closed 't)
12805 (overlay-put ov 'evaporate 't)
12806 (overlay-put ov 'verilog-include-file 't)
12807 (overlay-put ov 'mouse-face 'highlight)
12808 (overlay-put ov 'local-map verilog-mode-mouse-map))))
12810 ;; make new module overlays
12812 ;; This scanner is syntax-fragile, so don't get bent
12813 (when verilog-highlight-modules
12814 (condition-case nil
12815 (while (verilog-re-search-forward-quick "\\(/\\*AUTOINST\\*/\\|\\.\\*\\)" end-point t)
12817 (goto-char (match-beginning 0))
12818 (unless (verilog-inside-comment-or-string-p)
12819 (verilog-read-inst-module-matcher) ;; sets match 0
12820 (let* ((ov (make-overlay (match-beginning 0) (match-end 0))))
12821 (overlay-put ov 'start-closed 't)
12822 (overlay-put ov 'end-closed 't)
12823 (overlay-put ov 'evaporate 't)
12824 (overlay-put ov 'verilog-inst-module 't)
12825 (overlay-put ov 'mouse-face 'highlight)
12826 (overlay-put ov 'local-map verilog-mode-mouse-map)))))
12829 ;; Future highlights:
12830 ;; variables - make an Occur buffer of where referenced
12831 ;; pins - make an Occur buffer of the sig in the declaration module
12834 (defun verilog-highlight-buffer ()
12835 "Colorize included files and modules across the whole buffer."
12836 ;; Invoked via verilog-mode calling font-lock then `font-lock-mode-hook'
12838 ;; delete and remake overlays
12839 (verilog-highlight-region (point-min) (point-max) nil))
12841 ;; Deprecated, but was interactive, so we'll keep it around
12842 (defalias 'verilog-colorize-include-files-buffer 'verilog-highlight-buffer)
12844 ;; ffap-at-mouse isn't useful for Verilog mode. It uses library paths.
12845 ;; so define this function to do more or less the same as ffap-at-mouse
12846 ;; but first resolve filename...
12847 (defun verilog-load-file-at-mouse (event)
12848 "Load file under button 2 click's EVENT.
12849 Files are checked based on `verilog-library-flags'."
12851 (save-excursion ;; implement a Verilog specific ffap-at-mouse
12852 (mouse-set-point event)
12853 (verilog-load-file-at-point t)))
12855 ;; ffap isn't usable for Verilog mode. It uses library paths.
12856 ;; so define this function to do more or less the same as ffap
12857 ;; but first resolve filename...
12858 (defun verilog-load-file-at-point (&optional warn)
12859 "Load file under point.
12860 If WARN, throw warning if not found.
12861 Files are checked based on `verilog-library-flags'."
12863 (save-excursion ;; implement a Verilog specific ffap
12864 (let ((overlays (overlays-in (point) (point)))
12866 (while (and overlays (not hit))
12867 (when (overlay-get (car overlays) 'verilog-inst-module)
12868 (verilog-goto-defun-file (buffer-substring
12869 (overlay-start (car overlays))
12870 (overlay-end (car overlays))))
12872 (setq overlays (cdr overlays)))
12874 (beginning-of-line)
12875 (when (and (not hit)
12876 (looking-at verilog-include-file-regexp))
12877 (if (and (car (verilog-library-filenames
12878 (match-string 1) (buffer-file-name)))
12879 (file-readable-p (car (verilog-library-filenames
12880 (match-string 1) (buffer-file-name)))))
12881 (find-file (car (verilog-library-filenames
12882 (match-string 1) (buffer-file-name))))
12885 "File '%s' isn't readable, use shift-mouse2 to paste in this field"
12886 (match-string 1))))))))
12892 (defun verilog-faq ()
12893 "Tell the user their current version, and where to get the FAQ etc."
12895 (with-output-to-temp-buffer "*verilog-mode help*"
12896 (princ (format "You are using verilog-mode %s\n" verilog-mode-version))
12898 (princ "For new releases, see http://www.verilog.com\n")
12900 (princ "For frequently asked questions, see http://www.veripool.org/verilog-mode-faq.html\n")
12902 (princ "To submit a bug, use M-x verilog-submit-bug-report\n")
12905 (autoload 'reporter-submit-bug-report "reporter")
12906 (defvar reporter-prompt-for-summary-p)
12908 (defun verilog-submit-bug-report ()
12909 "Submit via mail a bug report on verilog-mode.el."
12911 (let ((reporter-prompt-for-summary-p t))
12912 (reporter-submit-bug-report
12913 "mac@verilog.com, wsnyder@wsnyder.org"
12914 (concat "verilog-mode v" verilog-mode-version)
12916 verilog-active-low-regexp
12917 verilog-align-ifelse
12918 verilog-assignment-delay
12919 verilog-auto-arg-sort
12920 verilog-auto-endcomments
12922 verilog-auto-ignore-concat
12923 verilog-auto-indent-on-newline
12924 verilog-auto-inout-ignore-regexp
12925 verilog-auto-input-ignore-regexp
12926 verilog-auto-inst-column
12927 verilog-auto-inst-dot-name
12928 verilog-auto-inst-param-value
12929 verilog-auto-inst-template-numbers
12930 verilog-auto-inst-vector
12931 verilog-auto-lineup
12932 verilog-auto-newline
12933 verilog-auto-output-ignore-regexp
12934 verilog-auto-read-includes
12935 verilog-auto-reset-widths
12936 verilog-auto-save-policy
12937 verilog-auto-sense-defines-constant
12938 verilog-auto-sense-include-inputs
12939 verilog-auto-star-expand
12940 verilog-auto-star-save
12941 verilog-auto-unused-ignore-regexp
12942 verilog-before-auto-hook
12943 verilog-before-delete-auto-hook
12944 verilog-before-getopt-flags-hook
12945 verilog-case-indent
12946 verilog-cexp-indent
12949 verilog-delete-auto-hook
12950 verilog-getopt-flags-hook
12951 verilog-highlight-grouping-keywords
12952 verilog-highlight-p1800-keywords
12953 verilog-highlight-translate-off
12954 verilog-indent-begin-after-if
12955 verilog-indent-declaration-macros
12956 verilog-indent-level
12957 verilog-indent-level-behavioral
12958 verilog-indent-level-declaration
12959 verilog-indent-level-directive
12960 verilog-indent-level-module
12961 verilog-indent-lists
12962 verilog-library-directories
12963 verilog-library-extensions
12964 verilog-library-files
12965 verilog-library-flags
12967 verilog-minimum-comment-distance
12969 verilog-preprocessor
12971 verilog-tab-always-indent
12972 verilog-tab-to-comment
12973 verilog-typedef-regexp
12978 I want to report a bug.
12980 Before I go further, I want to say that Verilog mode has changed my life.
12981 I save so much time, my files are colored nicely, my co workers respect
12982 my coding ability... until now. I'd really appreciate anything you
12983 could do to help me out with this minor deficiency in the product.
12985 I've taken a look at the Verilog-Mode FAQ at
12986 http://www.veripool.org/verilog-mode-faq.html.
12988 And, I've considered filing the bug on the issue tracker at
12989 http://www.veripool.org/verilog-mode-bugs
12990 since I realize that public bugs are easier for you to track,
12991 and for others to search, but would prefer to email.
12993 So, to reproduce the bug, start a fresh Emacs via " invocation-name "
12994 -no-init-file -no-site-file'. In a new buffer, in Verilog mode, type
12995 the code included below.
12997 Given those lines, I expected [[Fill in here]] to happen;
12998 but instead, [[Fill in here]] happens!.
13000 == The code: =="))))
13002 (provide 'verilog-mode)
13004 ;; Local Variables:
13005 ;; checkdoc-permit-comma-termination-flag:t
13006 ;; checkdoc-force-docstrings-flag:nil
13009 ;;; verilog-mode.el ends here