1 ;; verilog-mode.el --- major mode for editing verilog source in Emacs
3 ;; Copyright (C) 1996-2012 Free Software Foundation, Inc.
5 ;; Author: Michael McNamara (mac@verilog.com),
6 ;; Wilson Snyder (wsnyder@wsnyder.org)
7 ;; Please see our web sites:
8 ;; http://www.verilog.com
9 ;; http://www.veripool.org
11 ;; Keywords: languages
13 ;; Yoni Rabkin <yoni@rabkins.net> contacted the maintainer of this
14 ;; file on 19/3/2008, and the maintainer agreed that when a bug is
15 ;; filed in the Emacs bug reporting system against this file, a copy
16 ;; of the bug report be sent to the maintainer's email address.
18 ;; This code supports Emacs 21.1 and later
19 ;; And XEmacs 21.1 and later
20 ;; Please do not make changes that break Emacs 21. Thanks!
24 ;; This file is part of GNU Emacs.
26 ;; GNU Emacs is free software: you can redistribute it and/or modify
27 ;; it under the terms of the GNU General Public License as published by
28 ;; the Free Software Foundation, either version 3 of the License, or
29 ;; (at your option) any later version.
31 ;; GNU Emacs is distributed in the hope that it will be useful,
32 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
33 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
34 ;; GNU General Public License for more details.
36 ;; You should have received a copy of the GNU General Public License
37 ;; along with GNU Emacs. If not, see <http://www.gnu.org/licenses/>.
41 ;; This mode borrows heavily from the Pascal-mode and the cc-mode of Emacs
46 ;; A major mode for editing Verilog HDL source code. When you have
47 ;; entered Verilog mode, you may get more info by pressing C-h m. You
48 ;; may also get online help describing various functions by: C-h f
49 ;; <Name of function you want described>
51 ;; KNOWN BUGS / BUG REPORTS
52 ;; =======================
54 ;; Verilog is a rapidly evolving language, and hence this mode is
55 ;; under continuous development. Hence this is beta code, and likely
56 ;; has bugs. Please report any issues to the issue tracker at
57 ;; http://www.veripool.org/verilog-mode
58 ;; Please use verilog-submit-bug-report to submit a report; type C-c
59 ;; C-b to invoke this and as a result I will have a much easier time
60 ;; of reproducing the bug you find, and hence fixing it.
62 ;; INSTALLING THE MODE
63 ;; ===================
65 ;; An older version of this mode may be already installed as a part of
66 ;; your environment, and one method of updating would be to update
67 ;; your Emacs environment. Sometimes this is difficult for local
68 ;; political/control reasons, and hence you can always install a
69 ;; private copy (or even a shared copy) which overrides the system
72 ;; You can get step by step help in installing this file by going to
73 ;; <http://www.verilog.com/emacs_install.html>
75 ;; The short list of installation instructions are: To set up
76 ;; automatic Verilog mode, put this file in your load path, and put
77 ;; the following in code (please un comment it first!) in your
78 ;; .emacs, or in your site's site-load.el
80 ; (autoload 'verilog-mode "verilog-mode" "Verilog mode" t )
81 ; (add-to-list 'auto-mode-alist '("\\.[ds]?vh?\\'" . verilog-mode))
83 ;; Be sure to examine at the help for verilog-auto, and the other
84 ;; verilog-auto-* functions for some major coding time savers.
86 ;; If you want to customize Verilog mode to fit your needs better,
87 ;; you may add the below lines (the values of the variables presented
88 ;; here are the defaults). Note also that if you use an Emacs that
89 ;; supports custom, it's probably better to use the custom menu to
90 ;; edit these. If working as a member of a large team these settings
91 ;; should be common across all users (in a site-start file), or set
92 ;; in Local Variables in every file. Otherwise, different people's
93 ;; AUTO expansion may result different whitespace changes.
95 ; ;; Enable syntax highlighting of **all** languages
96 ; (global-font-lock-mode t)
98 ; ;; User customization for Verilog mode
99 ; (setq verilog-indent-level 3
100 ; verilog-indent-level-module 3
101 ; verilog-indent-level-declaration 3
102 ; verilog-indent-level-behavioral 3
103 ; verilog-indent-level-directive 1
104 ; verilog-case-indent 2
105 ; verilog-auto-newline t
106 ; verilog-auto-indent-on-newline t
107 ; verilog-tab-always-indent t
108 ; verilog-auto-endcomments t
109 ; verilog-minimum-comment-distance 40
110 ; verilog-indent-begin-after-if t
111 ; verilog-auto-lineup 'declarations
112 ; verilog-highlight-p1800-keywords nil
113 ; verilog-linter "my_lint_shell_command"
120 ;; See commit history at http://www.veripool.org/verilog-mode.html
121 ;; (This section is required to appease checkdoc.)
125 ;; This variable will always hold the version number of the mode
126 (defconst verilog-mode-version
(substring "$$Revision: 820 $$" 12 -
3)
127 "Version of this Verilog mode.")
128 (defconst verilog-mode-release-date
(substring "$$Date: 2012-09-17 20:43:10 -0400 (Mon, 17 Sep 2012) $$" 8 -
3)
129 "Release date of this Verilog mode.")
130 (defconst verilog-mode-release-emacs t
131 "If non-nil, this version of Verilog mode was released with Emacs itself.")
133 (defun verilog-version ()
134 "Inform caller of the version of this file."
136 (message "Using verilog-mode version %s" verilog-mode-version
))
138 ;; Insure we have certain packages, and deal with it if we don't
139 ;; Be sure to note which Emacs flavor and version added each feature.
141 ;; Provide stuff if we are XEmacs
142 (when (featurep 'xemacs
)
147 (require 'regexp-opt
)
149 ;; Bug in 19.28 through 19.30 skeleton.el, not provided.
156 (defmacro when
(cond &rest body
)
157 (list 'if cond
(cons 'progn body
))))
160 (if (fboundp 'unless
)
162 (defmacro unless
(cond &rest body
)
163 (cons 'if
(cons cond
(cons nil body
)))))
166 (if (fboundp 'store-match-data
)
168 (defmacro store-match-data
(&rest args
) nil
))
171 (if (fboundp 'char-before
)
173 (defmacro char-before
(&rest body
)
174 (char-after (1- (point)))))
179 (defsubst point-at-bol
(&optional N
)
180 (save-excursion (beginning-of-line N
) (point))))
185 (defsubst point-at-eol
(&optional N
)
186 (save-excursion (end-of-line N
) (point))))
192 (if (fboundp 'match-string-no-properties
)
194 (defsubst match-string-no-properties
(num &optional string
)
195 "Return string of text matched by last search, without text properties.
196 NUM specifies which parenthesized expression in the last regexp.
197 Value is nil if NUMth pair didn't match, or there were less than NUM pairs.
198 Zero means the entire text matched by the whole regexp or whole string.
199 STRING should be given if the last search was by `string-match' on STRING."
200 (if (match-beginning num
)
204 (match-beginning num
) (match-end num
))))
205 (set-text-properties 0 (length result
) nil result
)
207 (buffer-substring-no-properties (match-beginning num
)
212 (if (and (featurep 'custom
) (fboundp 'custom-declare-variable
))
213 nil
;; We've got what we needed
214 ;; We have the old custom-library, hack around it!
215 (defmacro defgroup
(&rest args
) nil
)
216 (defmacro customize
(&rest args
)
218 "Sorry, Customize is not available with this version of Emacs"))
219 (defmacro defcustom
(var value doc
&rest args
)
220 `(defvar ,var
,value
,doc
))
222 (if (fboundp 'defface
)
224 (defmacro defface
(var values doc
&rest args
)
228 (if (and (featurep 'custom
) (fboundp 'customize-group
))
229 nil
;; We've got what we needed
230 ;; We have an intermediate custom-library, hack around it!
231 (defmacro customize-group
(var &rest args
)
235 (unless (boundp 'inhibit-point-motion-hooks
)
236 (defvar inhibit-point-motion-hooks nil
))
237 (unless (boundp 'deactivate-mark
)
238 (defvar deactivate-mark nil
))
241 ;; OK, do this stuff if we are NOT XEmacs:
242 (unless (featurep 'xemacs
)
243 (unless (fboundp 'region-active-p
)
244 (defmacro region-active-p
()
245 `(and transient-mark-mode mark-active
))))
248 ;; Provide a regular expression optimization routine, using regexp-opt
249 ;; if provided by the user's elisp libraries
251 ;; The below were disabled when GNU Emacs 22 was released;
252 ;; perhaps some still need to be there to support Emacs 21.
253 (if (featurep 'xemacs
)
254 (if (fboundp 'regexp-opt
)
255 ;; regexp-opt is defined, does it take 3 or 2 arguments?
256 (if (fboundp 'function-max-args
)
257 (let ((args (function-max-args `regexp-opt
)))
259 ((eq args
3) ;; It takes 3
260 (condition-case nil
; Hide this defun from emacses
261 ;with just a two input regexp
262 (defun verilog-regexp-opt (a b
)
263 "Deal with differing number of required arguments for `regexp-opt'.
264 Call 'regexp-opt' on A and B."
268 ((eq args
2) ;; It takes 2
269 (defun verilog-regexp-opt (a b
)
270 "Call 'regexp-opt' on A and B."
274 ;; We can't tell; assume it takes 2
275 (defun verilog-regexp-opt (a b
)
276 "Call 'regexp-opt' on A and B."
279 ;; There is no regexp-opt, provide our own
280 (defun verilog-regexp-opt (strings &optional paren shy
)
281 (let ((open (if paren
"\\(" "")) (close (if paren
"\\)" "")))
282 (concat open
(mapconcat 'regexp-quote strings
"\\|") close
)))
285 (defalias 'verilog-regexp-opt
'regexp-opt
)))
288 ;; Both xemacs and emacs
290 (require 'diff
) ;; diff-command and diff-switches
293 (require 'compile
) ;; compilation-error-regexp-alist-alist
296 (unless (fboundp 'buffer-chars-modified-tick
) ;; Emacs 22 added
297 (defmacro buffer-chars-modified-tick
() (buffer-modified-tick)))
299 ;; Added in Emacs 24.1
301 (unless (fboundp 'prog-mode
)
302 (define-derived-mode prog-mode fundamental-mode
"Prog"))
306 (defun verilog-regexp-words (a)
307 "Call 'regexp-opt' with word delimiters for the words A."
308 (concat "\\<" (verilog-regexp-opt a t
) "\\>")))
309 (defun verilog-regexp-words (a)
310 "Call 'regexp-opt' with word delimiters for the words A."
311 ;; The FAQ references this function, so user LISP sometimes calls it
312 (concat "\\<" (verilog-regexp-opt a t
) "\\>"))
314 (defun verilog-easy-menu-filter (menu)
315 "Filter `easy-menu-define' MENU to support new features."
316 (cond ((not (featurep 'xemacs
))
317 menu
) ;; GNU Emacs - passthru
318 ;; XEmacs doesn't support :help. Strip it.
319 ;; Recursively filter the a submenu
321 (mapcar 'verilog-easy-menu-filter menu
))
322 ;; Look for [:help "blah"] and remove
324 (let ((i 0) (out []))
325 (while (< i
(length menu
))
326 (if (equal `:help
(aref menu i
))
328 (setq out
(vconcat out
(vector (aref menu i
)))
331 (t menu
))) ;; Default - ok
332 ;;(verilog-easy-menu-filter
333 ;; `("Verilog" ("MA" ["SAA" nil :help "Help SAA"] ["SAB" nil :help "Help SAA"])
334 ;; "----" ["MB" nil :help "Help MB"]))
336 (defun verilog-define-abbrev (table name expansion
&optional hook
)
337 "Filter `define-abbrev' TABLE NAME EXPANSION and call HOOK.
338 Provides SYSTEM-FLAG in newer Emacs."
340 (define-abbrev table name expansion hook
0 t
)
342 (define-abbrev table name expansion hook
))))
344 (defun verilog-customize ()
345 "Customize variables and other settings used by Verilog-Mode."
347 (customize-group 'verilog-mode
))
349 (defun verilog-font-customize ()
350 "Customize fonts used by Verilog-Mode."
352 (if (fboundp 'customize-apropos
)
353 (customize-apropos "font-lock-*" 'faces
)))
355 (defun verilog-booleanp (value)
356 "Return t if VALUE is boolean.
357 This implements GNU Emacs 22.1's `booleanp' function in earlier Emacs.
358 This function may be removed when Emacs 21 is no longer supported."
359 (or (equal value t
) (equal value nil
)))
361 (defun verilog-insert-last-command-event ()
362 "Insert the `last-command-event'."
363 (insert (if (featurep 'xemacs
)
364 ;; XEmacs 21.5 doesn't like last-command-event
366 ;; And GNU Emacs 22 has obsoleted last-command-char
367 last-command-event
)))
369 (defvar verilog-no-change-functions nil
370 "True if `after-change-functions' is disabled.
371 Use of `syntax-ppss' may break, as ppss's cache may get corrupted.")
373 (defvar verilog-in-hooks nil
374 "True when within a `verilog-run-hooks' block.")
376 (defmacro verilog-run-hooks
(&rest hooks
)
377 "Run each hook in HOOKS using `run-hooks'.
378 Set `verilog-in-hooks' during this time, to assist AUTO caches."
379 `(let ((verilog-in-hooks t
))
380 (run-hooks ,@hooks
)))
382 (defun verilog-syntax-ppss (&optional pos
)
383 (when verilog-no-change-functions
385 (verilog-scan-cache-flush)
386 ;; else don't let the AUTO code itself get away with flushing the cache,
387 ;; as that'll make things very slow
389 (error "%s: Internal problem; use of syntax-ppss when cache may be corrupt"
390 (verilog-point-text))))
391 (if (fboundp 'syntax-ppss
)
393 (parse-partial-sexp (point-min) (or pos
(point)))))
395 (defgroup verilog-mode nil
396 "Major mode for Verilog source code."
400 ; (defgroup verilog-mode-fonts nil
401 ; "Facilitates easy customization fonts used in Verilog source text"
402 ; :link '(customize-apropos "font-lock-*" 'faces)
403 ; :group 'verilog-mode)
405 (defgroup verilog-mode-indent nil
406 "Customize indentation and highlighting of Verilog source text."
407 :group
'verilog-mode
)
409 (defgroup verilog-mode-actions nil
410 "Customize actions on Verilog source text."
411 :group
'verilog-mode
)
413 (defgroup verilog-mode-auto nil
414 "Customize AUTO actions when expanding Verilog source text."
415 :group
'verilog-mode
)
417 (defvar verilog-debug nil
418 "Non-nil means enable debug messages for `verilog-mode' internals.")
420 (defvar verilog-warn-fatal nil
421 "Non-nil means `verilog-warn-error' warnings are fatal `error's.")
423 (defcustom verilog-linter
424 "echo 'No verilog-linter set, see \"M-x describe-variable verilog-linter\"'"
425 "Unix program and arguments to call to run a lint checker on Verilog source.
426 Depending on the `verilog-set-compile-command', this may be invoked when
427 you type \\[compile]. When the compile completes, \\[next-error] will take
428 you to the next lint error."
430 :group
'verilog-mode-actions
)
431 ;; We don't mark it safe, as it's used as a shell command
433 (defcustom verilog-coverage
434 "echo 'No verilog-coverage set, see \"M-x describe-variable verilog-coverage\"'"
435 "Program and arguments to use to annotate for coverage Verilog source.
436 Depending on the `verilog-set-compile-command', this may be invoked when
437 you type \\[compile]. When the compile completes, \\[next-error] will take
438 you to the next lint error."
440 :group
'verilog-mode-actions
)
441 ;; We don't mark it safe, as it's used as a shell command
443 (defcustom verilog-simulator
444 "echo 'No verilog-simulator set, see \"M-x describe-variable verilog-simulator\"'"
445 "Program and arguments to use to interpret Verilog source.
446 Depending on the `verilog-set-compile-command', this may be invoked when
447 you type \\[compile]. When the compile completes, \\[next-error] will take
448 you to the next lint error."
450 :group
'verilog-mode-actions
)
451 ;; We don't mark it safe, as it's used as a shell command
453 (defcustom verilog-compiler
454 "echo 'No verilog-compiler set, see \"M-x describe-variable verilog-compiler\"'"
455 "Program and arguments to use to compile Verilog source.
456 Depending on the `verilog-set-compile-command', this may be invoked when
457 you type \\[compile]. When the compile completes, \\[next-error] will take
458 you to the next lint error."
460 :group
'verilog-mode-actions
)
461 ;; We don't mark it safe, as it's used as a shell command
463 (defcustom verilog-preprocessor
464 ;; Very few tools give preprocessed output, so we'll default to Verilog-Perl
465 "vppreproc __FLAGS__ __FILE__"
466 "Program and arguments to use to preprocess Verilog source.
467 This is invoked with `verilog-preprocess', and depending on the
468 `verilog-set-compile-command', may also be invoked when you type
469 \\[compile]. When the compile completes, \\[next-error] will
470 take you to the next lint error."
472 :group
'verilog-mode-actions
)
473 ;; We don't mark it safe, as it's used as a shell command
475 (defvar verilog-preprocess-history nil
476 "History for `verilog-preprocess'.")
478 (defvar verilog-tool
'verilog-linter
479 "Which tool to use for building compiler-command.
480 Either nil, `verilog-linter, `verilog-compiler,
481 `verilog-coverage, `verilog-preprocessor, or `verilog-simulator.
482 Alternatively use the \"Choose Compilation Action\" menu. See
483 `verilog-set-compile-command' for more information.")
485 (defcustom verilog-highlight-translate-off nil
486 "Non-nil means background-highlight code excluded from translation.
487 That is, all code between \"// synopsys translate_off\" and
488 \"// synopsys translate_on\" is highlighted using a different background color
489 \(face `verilog-font-lock-translate-off-face').
491 Note: This will slow down on-the-fly fontification (and thus editing).
493 Note: Activate the new setting in a Verilog buffer by re-fontifying it (menu
494 entry \"Fontify Buffer\"). XEmacs: turn off and on font locking."
496 :group
'verilog-mode-indent
)
497 ;; Note we don't use :safe, as that would break on Emacsen before 22.0.
498 (put 'verilog-highlight-translate-off
'safe-local-variable
'verilog-booleanp
)
500 (defcustom verilog-auto-lineup
'declarations
501 "Type of statements to lineup across multiple lines.
502 If 'all' is selected, then all line ups described below are done.
504 If 'declaration', then just declarations are lined up with any
505 preceding declarations, taking into account widths and the like,
506 so or example the code:
513 If 'assignment', then assignments are lined up with any preceding
514 assignments, so for example the code
515 a_long_variable <= b + c;
518 a_long_variable <= b + c;
521 In order to speed up editing, large blocks of statements are lined up
522 only when a \\[verilog-pretty-expr] is typed; and large blocks of declarations
523 are lineup only when \\[verilog-pretty-declarations] is typed."
525 :type
'(radio (const :tag
"Line up Assignments and Declarations" all
)
526 (const :tag
"Line up Assignment statements" assignments
)
527 (const :tag
"Line up Declarations" declarations
)
528 (function :tag
"Other"))
529 :group
'verilog-mode-indent
)
530 (put 'verilog-auto-lineup
'safe-local-variable
531 '(lambda (x) (memq x
'(nil all assignments declarations
))))
533 (defcustom verilog-indent-level
3
534 "Indentation of Verilog statements with respect to containing block."
535 :group
'verilog-mode-indent
537 (put 'verilog-indent-level
'safe-local-variable
'integerp
)
539 (defcustom verilog-indent-level-module
3
540 "Indentation of Module level Verilog statements (eg always, initial).
541 Set to 0 to get initial and always statements lined up on the left side of
543 :group
'verilog-mode-indent
545 (put 'verilog-indent-level-module
'safe-local-variable
'integerp
)
547 (defcustom verilog-indent-level-declaration
3
548 "Indentation of declarations with respect to containing block.
549 Set to 0 to get them list right under containing block."
550 :group
'verilog-mode-indent
552 (put 'verilog-indent-level-declaration
'safe-local-variable
'integerp
)
554 (defcustom verilog-indent-declaration-macros nil
555 "How to treat macro expansions in a declaration.
560 If non nil, treat as:
564 :group
'verilog-mode-indent
566 (put 'verilog-indent-declaration-macros
'safe-local-variable
'verilog-booleanp
)
568 (defcustom verilog-indent-lists t
569 "How to treat indenting items in a list.
570 If t (the default), indent as:
571 always @( posedge a or
575 always @( posedge a or
577 :group
'verilog-mode-indent
579 (put 'verilog-indent-lists
'safe-local-variable
'verilog-booleanp
)
581 (defcustom verilog-indent-level-behavioral
3
582 "Absolute indentation of first begin in a task or function block.
583 Set to 0 to get such code to start at the left side of the screen."
584 :group
'verilog-mode-indent
586 (put 'verilog-indent-level-behavioral
'safe-local-variable
'integerp
)
588 (defcustom verilog-indent-level-directive
1
589 "Indentation to add to each level of `ifdef declarations.
590 Set to 0 to have all directives start at the left side of the screen."
591 :group
'verilog-mode-indent
593 (put 'verilog-indent-level-directive
'safe-local-variable
'integerp
)
595 (defcustom verilog-cexp-indent
2
596 "Indentation of Verilog statements split across lines."
597 :group
'verilog-mode-indent
599 (put 'verilog-cexp-indent
'safe-local-variable
'integerp
)
601 (defcustom verilog-case-indent
2
602 "Indentation for case statements."
603 :group
'verilog-mode-indent
605 (put 'verilog-case-indent
'safe-local-variable
'integerp
)
607 (defcustom verilog-auto-newline t
608 "Non-nil means automatically newline after semicolons."
609 :group
'verilog-mode-indent
611 (put 'verilog-auto-newline
'safe-local-variable
'verilog-booleanp
)
613 (defcustom verilog-auto-indent-on-newline t
614 "Non-nil means automatically indent line after newline."
615 :group
'verilog-mode-indent
617 (put 'verilog-auto-indent-on-newline
'safe-local-variable
'verilog-booleanp
)
619 (defcustom verilog-tab-always-indent t
620 "Non-nil means TAB should always re-indent the current line.
621 A nil value means TAB will only reindent when at the beginning of the line."
622 :group
'verilog-mode-indent
624 (put 'verilog-tab-always-indent
'safe-local-variable
'verilog-booleanp
)
626 (defcustom verilog-tab-to-comment nil
627 "Non-nil means TAB moves to the right hand column in preparation for a comment."
628 :group
'verilog-mode-actions
630 (put 'verilog-tab-to-comment
'safe-local-variable
'verilog-booleanp
)
632 (defcustom verilog-indent-begin-after-if t
633 "Non-nil means indent begin statements following if, else, while, etc.
634 Otherwise, line them up."
635 :group
'verilog-mode-indent
637 (put 'verilog-indent-begin-after-if
'safe-local-variable
'verilog-booleanp
)
639 (defcustom verilog-align-ifelse nil
640 "Non-nil means align `else' under matching `if'.
641 Otherwise else is lined up with first character on line holding matching if."
642 :group
'verilog-mode-indent
644 (put 'verilog-align-ifelse
'safe-local-variable
'verilog-booleanp
)
646 (defcustom verilog-minimum-comment-distance
10
647 "Minimum distance (in lines) between begin and end required before a comment.
648 Setting this variable to zero results in every end acquiring a comment; the
649 default avoids too many redundant comments in tight quarters."
650 :group
'verilog-mode-indent
652 (put 'verilog-minimum-comment-distance
'safe-local-variable
'integerp
)
654 (defcustom verilog-highlight-p1800-keywords nil
655 "Non-nil means highlight words newly reserved by IEEE-1800.
656 These will appear in `verilog-font-lock-p1800-face' in order to gently
657 suggest changing where these words are used as variables to something else.
658 A nil value means highlight these words as appropriate for the SystemVerilog
659 IEEE-1800 standard. Note that changing this will require restarting Emacs
660 to see the effect as font color choices are cached by Emacs."
661 :group
'verilog-mode-indent
663 (put 'verilog-highlight-p1800-keywords
'safe-local-variable
'verilog-booleanp
)
665 (defcustom verilog-highlight-grouping-keywords nil
666 "Non-nil means highlight grouping keywords 'begin' and 'end' more dramatically.
667 If false, these words are in the `font-lock-type-face'; if True then they are in
668 `verilog-font-lock-ams-face'. Some find that special highlighting on these
669 grouping constructs allow the structure of the code to be understood at a glance."
670 :group
'verilog-mode-indent
672 (put 'verilog-highlight-grouping-keywords
'safe-local-variable
'verilog-booleanp
)
674 (defcustom verilog-highlight-modules nil
675 "Non-nil means highlight module statements for `verilog-load-file-at-point'.
676 When true, mousing over module names will allow jumping to the
677 module definition. If false, this is not supported. Setting
678 this is experimental, and may lead to bad performance."
679 :group
'verilog-mode-indent
681 (put 'verilog-highlight-modules
'safe-local-variable
'verilog-booleanp
)
683 (defcustom verilog-highlight-includes t
684 "Non-nil means highlight module statements for `verilog-load-file-at-point'.
685 When true, mousing over include file names will allow jumping to the
686 file referenced. If false, this is not supported."
687 :group
'verilog-mode-indent
689 (put 'verilog-highlight-includes
'safe-local-variable
'verilog-booleanp
)
691 (defcustom verilog-auto-declare-nettype nil
692 "Non-nil specifies the data type to use with `verilog-auto-input' etc.
693 Set this to \"wire\" if the Verilog code uses \"`default_nettype
694 none\". Note using `default_nettype none isn't recommended practice; this
695 mode is experimental."
696 :version
"24.1" ;; rev670
697 :group
'verilog-mode-actions
699 (put 'verilog-auto-declare-nettype
'safe-local-variable
`stringp
)
701 (defcustom verilog-auto-wire-type nil
702 "Non-nil specifies the data type to use with `verilog-auto-wire' etc.
703 Set this to \"logic\" for SystemVerilog code, or use `verilog-auto-logic'."
704 :version
"24.1" ;; rev673
705 :group
'verilog-mode-actions
707 (put 'verilog-auto-wire-type
'safe-local-variable
`stringp
)
709 (defcustom verilog-auto-endcomments t
710 "Non-nil means insert a comment /* ... */ after 'end's.
711 The name of the function or case will be set between the braces."
712 :group
'verilog-mode-actions
714 (put 'verilog-auto-endcomments
'safe-local-variable
'verilog-booleanp
)
716 (defcustom verilog-auto-delete-trailing-whitespace nil
717 "Non-nil means to `delete-trailing-whitespace' in `verilog-auto'."
718 :version
"24.1" ;; rev703
719 :group
'verilog-mode-actions
721 (put 'verilog-auto-delete-trailing-whitespace
'safe-local-variable
'verilog-booleanp
)
723 (defcustom verilog-auto-ignore-concat nil
724 "Non-nil means ignore signals in {...} concatenations for AUTOWIRE etc.
725 This will exclude signals referenced as pin connections in {...}
726 from AUTOWIRE, AUTOOUTPUT and friends. This flag should be set
727 for backward compatibility only and not set in new designs; it
728 may be removed in future versions."
729 :group
'verilog-mode-actions
731 (put 'verilog-auto-ignore-concat
'safe-local-variable
'verilog-booleanp
)
733 (defcustom verilog-auto-read-includes nil
734 "Non-nil means to automatically read includes before AUTOs.
735 This will do a `verilog-read-defines' and `verilog-read-includes' before
736 each AUTO expansion. This makes it easier to embed defines and includes,
737 but can result in very slow reading times if there are many or large
739 :group
'verilog-mode-actions
741 (put 'verilog-auto-read-includes
'safe-local-variable
'verilog-booleanp
)
743 (defcustom verilog-auto-save-policy nil
744 "Non-nil indicates action to take when saving a Verilog buffer with AUTOs.
745 A value of `force' will always do a \\[verilog-auto] automatically if
746 needed on every save. A value of `detect' will do \\[verilog-auto]
747 automatically when it thinks necessary. A value of `ask' will query the
748 user when it thinks updating is needed.
750 You should not rely on the 'ask or 'detect policies, they are safeguards
751 only. They do not detect when AUTOINSTs need to be updated because a
752 sub-module's port list has changed."
753 :group
'verilog-mode-actions
754 :type
'(choice (const nil
) (const ask
) (const detect
) (const force
)))
756 (defcustom verilog-auto-star-expand t
757 "Non-nil means to expand SystemVerilog .* instance ports.
758 They will be expanded in the same way as if there was an AUTOINST in the
759 instantiation. See also `verilog-auto-star' and `verilog-auto-star-save'."
760 :group
'verilog-mode-actions
762 (put 'verilog-auto-star-expand
'safe-local-variable
'verilog-booleanp
)
764 (defcustom verilog-auto-star-save nil
765 "Non-nil means save to disk SystemVerilog .* instance expansions.
766 A nil value indicates direct connections will be removed before saving.
767 Only meaningful to those created due to `verilog-auto-star-expand' being set.
769 Instead of setting this, you may want to use /*AUTOINST*/, which will
771 :group
'verilog-mode-actions
773 (put 'verilog-auto-star-save
'safe-local-variable
'verilog-booleanp
)
775 (defvar verilog-auto-update-tick nil
776 "Modification tick at which autos were last performed.")
778 (defvar verilog-auto-last-file-locals nil
779 "Text from file-local-variables during last evaluation.")
781 (defvar verilog-diff-function
'verilog-diff-report
782 "Function to run when `verilog-diff-auto' detects differences.
783 Function takes three arguments, the original buffer, the
784 difference buffer, and the point in original buffer with the
789 (defvar verilog-error-regexp-added nil
)
791 (defvar verilog-error-regexp-emacs-alist
794 "\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 3)
796 "([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\(line[ \t]+\\)?\\([0-9]+\\):.*$" 1 3)
798 ".*\\*[WE],[0-9A-Z]+\\(\[[0-9A-Z_,]+\]\\)? (\\([^ \t,]+\\),\\([0-9]+\\)" 2 3)
800 "[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 1 2)
802 "\\(WARNING\\|ERROR\\|INFO\\)[^:]*: \\([^,]+\\),\\s-+\\(line \\)?\\([0-9]+\\):" 2 4 )
805 \\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\
806 :\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 2 5)
808 "\\(Error\\|Warning\\).*in file (\\([^ \t]+\\) at line *\\([0-9]+\\))" 2 3)
810 "\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 2 3)
812 "Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 2)
814 "\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 2 3)
816 "syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 1 2)
818 "%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 3 4)
820 "^In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\(Warning\\|Error\\|Failure\\)[^\n]*" 1 2)
822 "List of regexps for Verilog compilers.
823 See `compilation-error-regexp-alist' for the formatting. For Emacs 22+.")
825 (defvar verilog-error-regexp-xemacs-alist
826 ;; Emacs form is '((v-tool "re" 1 2) ...)
827 ;; XEmacs form is '(verilog ("re" 1 2) ...)
828 ;; So we can just map from Emacs to XEmacs
829 (cons 'verilog
(mapcar 'cdr verilog-error-regexp-emacs-alist
))
830 "List of regexps for Verilog compilers.
831 See `compilation-error-regexp-alist-alist' for the formatting. For XEmacs.")
833 (defvar verilog-error-font-lock-keywords
836 ("\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 bold t
)
837 ("\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 bold t
)
839 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\(line[ \t]+\\)?\\([0-9]+\\):.*$" 1 bold t
)
840 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\(line[ \t]+\\)?\\([0-9]+\\):.*$" 3 bold t
)
841 ;; verilog-IES (nc-verilog)
842 (".*\\*[WE],[0-9A-Z]+\\(\[[0-9A-Z_,]+\]\\)? (\\([^ \t,]+\\),\\([0-9]+\\)|" 2 bold t
)
843 (".*\\*[WE],[0-9A-Z]+\\(\[[0-9A-Z_,]+\]\\)? (\\([^ \t,]+\\),\\([0-9]+\\)|" 3 bold t
)
844 ;; verilog-surefire-1
845 ("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 1 bold t
)
846 ("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 2 bold t
)
847 ;; verilog-surefire-2
848 ("\\(WARNING\\|ERROR\\|INFO\\): \\([^,]+\\), line \\([0-9]+\\):" 2 bold t
)
849 ("\\(WARNING\\|ERROR\\|INFO\\): \\([^,]+\\), line \\([0-9]+\\):" 3 bold t
)
852 \\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\
853 :\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 bold t
)
855 \\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\
856 :\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 bold t
)
858 ("\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 2 bold t
)
859 ("\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 3 bold t
)
861 ("Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 bold t
)
862 ("Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 bold t
)
864 ("\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 2 bold t
)
865 ("\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 3 bold t
)
867 ("syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 1 bold t
)
868 ("syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 2 bold t
)
870 (".*%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 3 bold t
)
871 (".*%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 4 bold t
)
873 ("^In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\(Warning\\|Error\\|Failure\\)[^\n]*" 1 bold t
)
874 ("^In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\(Warning\\|Error\\|Failure\\)[^\n]*" 2 bold t
)
876 "Keywords to also highlight in Verilog *compilation* buffers.
877 Only used in XEmacs; GNU Emacs uses `verilog-error-regexp-emacs-alist'.")
879 (defcustom verilog-library-flags
'("")
880 "List of standard Verilog arguments to use for /*AUTOINST*/.
881 These arguments are used to find files for `verilog-auto', and match
882 the flags accepted by a standard Verilog-XL simulator.
884 -f filename Reads more `verilog-library-flags' from the filename.
885 +incdir+dir Adds the directory to `verilog-library-directories'.
886 -Idir Adds the directory to `verilog-library-directories'.
887 -y dir Adds the directory to `verilog-library-directories'.
888 +libext+.v Adds the extensions to `verilog-library-extensions'.
889 -v filename Adds the filename to `verilog-library-files'.
891 filename Adds the filename to `verilog-library-files'.
892 This is not recommended, -v is a better choice.
894 You might want these defined in each file; put at the *END* of your file
898 // verilog-library-flags:(\"-y dir -y otherdir\")
901 Verilog-mode attempts to detect changes to this local variable, but they
902 are only insured to be correct when the file is first visited. Thus if you
903 have problems, use \\[find-alternate-file] RET to have these take effect.
905 See also the variables mentioned above."
906 :group
'verilog-mode-auto
907 :type
'(repeat string
))
908 (put 'verilog-library-flags
'safe-local-variable
'listp
)
910 (defcustom verilog-library-directories
'(".")
911 "List of directories when looking for files for /*AUTOINST*/.
912 The directory may be relative to the current file, or absolute.
913 Environment variables are also expanded in the directory names.
914 Having at least the current directory is a good idea.
916 You might want these defined in each file; put at the *END* of your file
920 // verilog-library-directories:(\".\" \"subdir\" \"subdir2\")
923 Verilog-mode attempts to detect changes to this local variable, but they
924 are only insured to be correct when the file is first visited. Thus if you
925 have problems, use \\[find-alternate-file] RET to have these take effect.
927 See also `verilog-library-flags', `verilog-library-files'
928 and `verilog-library-extensions'."
929 :group
'verilog-mode-auto
930 :type
'(repeat file
))
931 (put 'verilog-library-directories
'safe-local-variable
'listp
)
933 (defcustom verilog-library-files
'()
934 "List of files to search for modules.
935 AUTOINST will use this when it needs to resolve a module name.
936 This is a complete path, usually to a technology file with many standard
939 You might want these defined in each file; put at the *END* of your file
943 // verilog-library-files:(\"/some/path/technology.v\" \"/some/path/tech2.v\")
946 Verilog-mode attempts to detect changes to this local variable, but they
947 are only insured to be correct when the file is first visited. Thus if you
948 have problems, use \\[find-alternate-file] RET to have these take effect.
950 See also `verilog-library-flags', `verilog-library-directories'."
951 :group
'verilog-mode-auto
952 :type
'(repeat directory
))
953 (put 'verilog-library-files
'safe-local-variable
'listp
)
955 (defcustom verilog-library-extensions
'(".v" ".sv")
956 "List of extensions to use when looking for files for /*AUTOINST*/.
957 See also `verilog-library-flags', `verilog-library-directories'."
958 :type
'(repeat string
)
959 :group
'verilog-mode-auto
)
960 (put 'verilog-library-extensions
'safe-local-variable
'listp
)
962 (defcustom verilog-active-low-regexp nil
963 "If set, treat signals matching this regexp as active low.
964 This is used for AUTORESET and AUTOTIEOFF. For proper behavior,
965 you will probably also need `verilog-auto-reset-widths' set."
966 :group
'verilog-mode-auto
968 (put 'verilog-active-low-regexp
'safe-local-variable
'stringp
)
970 (defcustom verilog-auto-sense-include-inputs nil
971 "Non-nil means AUTOSENSE should include all inputs.
972 If nil, only inputs that are NOT output signals in the same block are
974 :group
'verilog-mode-auto
976 (put 'verilog-auto-sense-include-inputs
'safe-local-variable
'verilog-booleanp
)
978 (defcustom verilog-auto-sense-defines-constant nil
979 "Non-nil means AUTOSENSE should assume all defines represent constants.
980 When true, the defines will not be included in sensitivity lists. To
981 maintain compatibility with other sites, this should be set at the bottom
982 of each Verilog file that requires it, rather than being set globally."
983 :group
'verilog-mode-auto
985 (put 'verilog-auto-sense-defines-constant
'safe-local-variable
'verilog-booleanp
)
987 (defcustom verilog-auto-reset-blocking-in-non t
988 "Non-nil means AUTORESET will reset blocking statements.
989 When true, AUTORESET will reset in blocking statements those
990 signals which were assigned with blocking assignments (=) even in
991 a block with non-blocking assignments (<=).
993 If nil, all blocking assigned signals are ignored when any
994 non-blocking assignment is in the AUTORESET block. This allows
995 blocking assignments to be used for temporary values and not have
996 those temporaries reset. See example in `verilog-auto-reset'."
997 :version
"24.1" ;; rev718
999 :group
'verilog-mode-auto
)
1000 (put 'verilog-auto-reset-blocking-in-non
'safe-local-variable
'verilog-booleanp
)
1002 (defcustom verilog-auto-reset-widths t
1003 "True means AUTORESET should determine the width of signals.
1004 This is then used to set the width of the zero (32'h0 for example). This
1005 is required by some lint tools that aren't smart enough to ignore widths of
1006 the constant zero. This may result in ugly code when parameters determine
1007 the MSB or LSB of a signal inside an AUTORESET.
1009 If nil, AUTORESET uses \"0\" as the constant.
1011 If 'unbased', AUTORESET used the unbased unsized literal \"'0\"
1012 as the constant. This setting is strongly recommended for
1013 SystemVerilog designs."
1015 :group
'verilog-mode-auto
)
1016 (put 'verilog-auto-reset-widths
'safe-local-variable
1017 '(lambda (x) (memq x
'(nil t unbased
))))
1019 (defcustom verilog-assignment-delay
""
1020 "Text used for delays in delayed assignments. Add a trailing space if set."
1021 :group
'verilog-mode-auto
1023 (put 'verilog-assignment-delay
'safe-local-variable
'stringp
)
1025 (defcustom verilog-auto-arg-sort nil
1026 "Non-nil means AUTOARG signal names will be sorted, not in declaration order.
1027 Declaration order is advantageous with order based instantiations
1028 and is the default for backward compatibility. Sorted order
1029 reduces changes when declarations are moved around in a file, and
1030 it's bad practice to rely on order based instantiations anyhow.
1032 See also `verilog-auto-inst-sort'."
1033 :group
'verilog-mode-auto
1035 (put 'verilog-auto-arg-sort
'safe-local-variable
'verilog-booleanp
)
1037 (defcustom verilog-auto-inst-dot-name nil
1038 "Non-nil means when creating ports with AUTOINST, use .name syntax.
1039 This will use \".port\" instead of \".port(port)\" when possible.
1040 This is only legal in SystemVerilog files, and will confuse older
1041 simulators. Setting `verilog-auto-inst-vector' to nil may also
1042 be desirable to increase how often .name will be used."
1043 :group
'verilog-mode-auto
1045 (put 'verilog-auto-inst-dot-name
'safe-local-variable
'verilog-booleanp
)
1047 (defcustom verilog-auto-inst-param-value nil
1048 "Non-nil means AUTOINST will replace parameters with the parameter value.
1049 If nil, leave parameters as symbolic names.
1051 Parameters must be in Verilog 2001 format #(...), and if a parameter is not
1052 listed as such there (as when the default value is acceptable), it will not
1053 be replaced, and will remain symbolic.
1055 For example, imagine a submodule uses parameters to declare the size of its
1056 inputs. This is then used by an upper module:
1058 module InstModule (o,i);
1060 input [WIDTH-1:0] i;
1070 Note even though PARAM=10, the AUTOINST has left the parameter as a
1071 symbolic name. If `verilog-auto-inst-param-value' is set, this will
1080 :group
'verilog-mode-auto
1082 (put 'verilog-auto-inst-param-value
'safe-local-variable
'verilog-booleanp
)
1084 (defcustom verilog-auto-inst-sort nil
1085 "Non-nil means AUTOINST signals will be sorted, not in declaration order.
1086 Also affects AUTOINSTPARAM. Declaration order is the default for
1087 backward compatibility, and as some teams prefer signals that are
1088 declared together to remain together. Sorted order reduces
1089 changes when declarations are moved around in a file.
1091 See also `verilog-auto-arg-sort'."
1092 :version
"24.1" ;; rev688
1093 :group
'verilog-mode-auto
1095 (put 'verilog-auto-inst-sort
'safe-local-variable
'verilog-booleanp
)
1097 (defcustom verilog-auto-inst-vector t
1098 "Non-nil means when creating default ports with AUTOINST, use bus subscripts.
1099 If nil, skip the subscript when it matches the entire bus as declared in
1100 the module (AUTOWIRE signals always are subscripted, you must manually
1101 declare the wire to have the subscripts removed.) Setting this to nil may
1102 speed up some simulators, but is less general and harder to read, so avoid."
1103 :group
'verilog-mode-auto
1105 (put 'verilog-auto-inst-vector
'safe-local-variable
'verilog-booleanp
)
1107 (defcustom verilog-auto-inst-template-numbers nil
1108 "If true, when creating templated ports with AUTOINST, add a comment.
1110 If t, the comment will add the line number of the template that
1111 was used for that port declaration. This setting is suggested
1112 only for debugging use, as regular use may cause a large numbers
1115 If 'lhs', the comment will show the left hand side of the
1116 AUTO_TEMPLATE rule that is matched. This is less precise than
1117 numbering (t) when multiple rules have the same pin name, but
1118 won't merge conflict."
1119 :group
'verilog-mode-auto
1120 :type
'(choice (const nil
) (const t
) (const lhs
)))
1121 (put 'verilog-auto-inst-template-numbers
'safe-local-variable
1122 '(lambda (x) (memq x
'(nil t lhs
))))
1124 (defcustom verilog-auto-inst-column
40
1125 "Indent-to column number for net name part of AUTOINST created pin."
1126 :group
'verilog-mode-indent
1128 (put 'verilog-auto-inst-column
'safe-local-variable
'integerp
)
1130 (defcustom verilog-auto-inst-interfaced-ports nil
1131 "Non-nil means include interfaced ports in AUTOINST expansions."
1132 :group
'verilog-mode-auto
1135 (put 'verilog-auto-inst-interfaced-ports
'safe-local-variable
'verilog-booleanp
)
1137 (defcustom verilog-auto-input-ignore-regexp nil
1138 "If set, when creating AUTOINPUT list, ignore signals matching this regexp.
1139 See the \\[verilog-faq] for examples on using this."
1140 :group
'verilog-mode-auto
1142 (put 'verilog-auto-input-ignore-regexp
'safe-local-variable
'stringp
)
1144 (defcustom verilog-auto-inout-ignore-regexp nil
1145 "If set, when creating AUTOINOUT list, ignore signals matching this regexp.
1146 See the \\[verilog-faq] for examples on using this."
1147 :group
'verilog-mode-auto
1149 (put 'verilog-auto-inout-ignore-regexp
'safe-local-variable
'stringp
)
1151 (defcustom verilog-auto-output-ignore-regexp nil
1152 "If set, when creating AUTOOUTPUT list, ignore signals matching this regexp.
1153 See the \\[verilog-faq] for examples on using this."
1154 :group
'verilog-mode-auto
1156 (put 'verilog-auto-output-ignore-regexp
'safe-local-variable
'stringp
)
1158 (defcustom verilog-auto-template-warn-unused nil
1159 "Non-nil means report warning if an AUTO_TEMPLATE line is not used.
1160 This feature is not supported before Emacs 21.1 or XEmacs 21.4."
1161 :group
'verilog-mode-auto
1163 (put 'verilog-auto-template-warn-unused
'safe-local-variable
'verilog-booleanp
)
1165 (defcustom verilog-auto-tieoff-declaration
"wire"
1166 "Data type used for the declaration for AUTOTIEOFF.
1167 If \"wire\" then create a wire, if \"assign\" create an
1168 assignment, else the data type for variable creation."
1169 :version
"24.1" ;; rev713
1170 :group
'verilog-mode-auto
1172 (put 'verilog-auto-tieoff-declaration
'safe-local-variable
'stringp
)
1174 (defcustom verilog-auto-tieoff-ignore-regexp nil
1175 "If set, when creating AUTOTIEOFF list, ignore signals matching this regexp.
1176 See the \\[verilog-faq] for examples on using this."
1177 :group
'verilog-mode-auto
1179 (put 'verilog-auto-tieoff-ignore-regexp
'safe-local-variable
'stringp
)
1181 (defcustom verilog-auto-unused-ignore-regexp nil
1182 "If set, when creating AUTOUNUSED list, ignore signals matching this regexp.
1183 See the \\[verilog-faq] for examples on using this."
1184 :group
'verilog-mode-auto
1186 (put 'verilog-auto-unused-ignore-regexp
'safe-local-variable
'stringp
)
1188 (defcustom verilog-typedef-regexp nil
1189 "If non-nil, regular expression that matches Verilog-2001 typedef names.
1190 For example, \"_t$\" matches typedefs named with _t, as in the C language."
1191 :group
'verilog-mode-auto
1193 (put 'verilog-typedef-regexp
'safe-local-variable
'stringp
)
1195 (defcustom verilog-mode-hook
'verilog-set-compile-command
1196 "Hook run after Verilog mode is loaded."
1198 :group
'verilog-mode
)
1200 (defcustom verilog-auto-hook nil
1201 "Hook run after `verilog-mode' updates AUTOs."
1202 :group
'verilog-mode-auto
1205 (defcustom verilog-before-auto-hook nil
1206 "Hook run before `verilog-mode' updates AUTOs."
1207 :group
'verilog-mode-auto
1210 (defcustom verilog-delete-auto-hook nil
1211 "Hook run after `verilog-mode' deletes AUTOs."
1212 :group
'verilog-mode-auto
1215 (defcustom verilog-before-delete-auto-hook nil
1216 "Hook run before `verilog-mode' deletes AUTOs."
1217 :group
'verilog-mode-auto
1220 (defcustom verilog-getopt-flags-hook nil
1221 "Hook run after `verilog-getopt-flags' determines the Verilog option lists."
1222 :group
'verilog-mode-auto
1225 (defcustom verilog-before-getopt-flags-hook nil
1226 "Hook run before `verilog-getopt-flags' determines the Verilog option lists."
1227 :group
'verilog-mode-auto
1230 (defcustom verilog-before-save-font-hook nil
1231 "Hook run before `verilog-save-font-mods' removes highlighting."
1232 :group
'verilog-mode-auto
1235 (defcustom verilog-after-save-font-hook nil
1236 "Hook run after `verilog-save-font-mods' restores highlighting."
1237 :group
'verilog-mode-auto
1240 (defvar verilog-imenu-generic-expression
1241 '((nil "^\\s-*\\(\\(m\\(odule\\|acromodule\\)\\)\\|primitive\\)\\s-+\\([a-zA-Z0-9_.:]+\\)" 4)
1242 ("*Vars*" "^\\s-*\\(reg\\|wire\\)\\s-+\\(\\|\\[[^]]+\\]\\s-+\\)\\([A-Za-z0-9_]+\\)" 3))
1243 "Imenu expression for Verilog mode. See `imenu-generic-expression'.")
1246 ;; provide a verilog-header function.
1247 ;; Customization variables:
1249 (defvar verilog-date-scientific-format nil
1250 "If non-nil, dates are written in scientific format (e.g. 1997/09/17).
1251 If nil, in European format (e.g. 17.09.1997). The brain-dead American
1252 format (e.g. 09/17/1997) is not supported.")
1254 (defvar verilog-company nil
1255 "Default name of Company for Verilog header.
1256 If set will become buffer local.")
1257 (make-variable-buffer-local 'verilog-company
)
1259 (defvar verilog-project nil
1260 "Default name of Project for Verilog header.
1261 If set will become buffer local.")
1262 (make-variable-buffer-local 'verilog-project
)
1264 (defvar verilog-mode-map
1265 (let ((map (make-sparse-keymap)))
1266 (define-key map
";" 'electric-verilog-semi
)
1267 (define-key map
[(control 59)] 'electric-verilog-semi-with-comment
)
1268 (define-key map
":" 'electric-verilog-colon
)
1269 ;;(define-key map "=" 'electric-verilog-equal)
1270 (define-key map
"\`" 'electric-verilog-tick
)
1271 (define-key map
"\t" 'electric-verilog-tab
)
1272 (define-key map
"\r" 'electric-verilog-terminate-line
)
1273 ;; backspace/delete key bindings
1274 (define-key map
[backspace] 'backward-delete-char-untabify)
1275 (unless (boundp 'delete-key-deletes-forward) ; XEmacs variable
1276 (define-key map [delete] 'delete-char)
1277 (define-key map [(meta delete)] 'kill-word))
1278 (define-key map "\M-\C-b" 'electric-verilog-backward-sexp)
1279 (define-key map "\M-\C-f" 'electric-verilog-forward-sexp)
1280 (define-key map "\M-\r" `electric-verilog-terminate-and-indent)
1281 (define-key map "\M-\t" 'verilog-complete-word)
1282 (define-key map "\M-?" 'verilog-show-completions)
1283 ;; Note \C-c and letter are reserved for users
1284 (define-key map "\C-c\`" 'verilog-lint-off)
1285 (define-key map "\C-c\*" 'verilog-delete-auto-star-implicit)
1286 (define-key map "\C-c\?" 'verilog-diff-auto)
1287 (define-key map "\C-c\C-r" 'verilog-label-be)
1288 (define-key map "\C-c\C-i" 'verilog-pretty-declarations)
1289 (define-key map "\C-c=" 'verilog-pretty-expr)
1290 (define-key map "\C-c\C-b" 'verilog-submit-bug-report)
1291 (define-key map "\M-*" 'verilog-star-comment)
1292 (define-key map "\C-c\C-c" 'verilog-comment-region)
1293 (define-key map "\C-c\C-u" 'verilog-uncomment-region)
1294 (when (featurep 'xemacs)
1295 (define-key map [(meta control h)] 'verilog-mark-defun)
1296 (define-key map "\M-\C-a" 'verilog-beg-of-defun)
1297 (define-key map "\M-\C-e" 'verilog-end-of-defun))
1298 (define-key map "\C-c\C-d" 'verilog-goto-defun)
1299 (define-key map "\C-c\C-k" 'verilog-delete-auto)
1300 (define-key map "\C-c\C-a" 'verilog-auto)
1301 (define-key map "\C-c\C-s" 'verilog-auto-save-compile)
1302 (define-key map "\C-c\C-p" 'verilog-preprocess)
1303 (define-key map "\C-c\C-z" 'verilog-inject-auto)
1304 (define-key map "\C-c\C-e" 'verilog-expand-vector)
1305 (define-key map "\C-c\C-h" 'verilog-header)
1307 "Keymap used in Verilog mode.")
1311 verilog-menu verilog-mode-map "Menu for Verilog mode"
1312 (verilog-easy-menu-filter
1314 ("Choose Compilation Action"
1317 (setq verilog-tool nil)
1318 (verilog-set-compile-command))
1320 :selected (equal verilog-tool nil)
1321 :help "When invoking compilation, use compile-command"]
1324 (setq verilog-tool 'verilog-linter)
1325 (verilog-set-compile-command))
1327 :selected (equal verilog-tool `verilog-linter)
1328 :help "When invoking compilation, use lint checker"]
1331 (setq verilog-tool 'verilog-coverage)
1332 (verilog-set-compile-command))
1334 :selected (equal verilog-tool `verilog-coverage)
1335 :help "When invoking compilation, annotate for coverage"]
1338 (setq verilog-tool 'verilog-simulator)
1339 (verilog-set-compile-command))
1341 :selected (equal verilog-tool `verilog-simulator)
1342 :help "When invoking compilation, interpret Verilog source"]
1345 (setq verilog-tool 'verilog-compiler)
1346 (verilog-set-compile-command))
1348 :selected (equal verilog-tool `verilog-compiler)
1349 :help "When invoking compilation, compile Verilog source"]
1352 (setq verilog-tool 'verilog-preprocessor)
1353 (verilog-set-compile-command))
1355 :selected (equal verilog-tool `verilog-preprocessor)
1356 :help "When invoking compilation, preprocess Verilog source, see also `verilog-preprocess'"]
1359 ["Beginning of function" verilog-beg-of-defun
1361 :help "Move backward to the beginning of the current function or procedure"]
1362 ["End of function" verilog-end-of-defun
1364 :help "Move forward to the end of the current function or procedure"]
1365 ["Mark function" verilog-mark-defun
1367 :help "Mark the current Verilog function or procedure"]
1368 ["Goto function/module" verilog-goto-defun
1369 :help "Move to specified Verilog module/task/function"]
1370 ["Move to beginning of block" electric-verilog-backward-sexp
1371 :help "Move backward over one balanced expression"]
1372 ["Move to end of block" electric-verilog-forward-sexp
1373 :help "Move forward over one balanced expression"]
1376 ["Comment Region" verilog-comment-region
1377 :help "Put marked area into a comment"]
1378 ["UnComment Region" verilog-uncomment-region
1379 :help "Uncomment an area commented with Comment Region"]
1380 ["Multi-line comment insert" verilog-star-comment
1381 :help "Insert Verilog /* */ comment at point"]
1382 ["Lint error to comment" verilog-lint-off
1383 :help "Convert a Verilog linter warning line into a disable statement"]
1387 :help "Perform compilation-action (above) on the current buffer"]
1388 ["AUTO, Save, Compile" verilog-auto-save-compile
1389 :help "Recompute AUTOs, save buffer, and compile"]
1390 ["Next Compile Error" next-error
1391 :help "Visit next compilation error message and corresponding source code"]
1392 ["Ignore Lint Warning at point" verilog-lint-off
1393 :help "Convert a Verilog linter warning line into a disable statement"]
1395 ["Line up declarations around point" verilog-pretty-declarations
1396 :help "Line up declarations around point"]
1397 ["Line up equations around point" verilog-pretty-expr
1398 :help "Line up expressions around point"]
1399 ["Redo/insert comments on every end" verilog-label-be
1400 :help "Label matching begin ... end statements"]
1401 ["Expand [x:y] vector line" verilog-expand-vector
1402 :help "Take a signal vector on the current line and expand it to multiple lines"]
1403 ["Insert begin-end block" verilog-insert-block
1404 :help "Insert begin ... end"]
1405 ["Complete word" verilog-complete-word
1406 :help "Complete word at point"]
1408 ["Recompute AUTOs" verilog-auto
1409 :help "Expand AUTO meta-comment statements"]
1410 ["Kill AUTOs" verilog-delete-auto
1411 :help "Remove AUTO expansions"]
1412 ["Diff AUTOs" verilog-diff-auto
1413 :help "Show differences in AUTO expansions"]
1414 ["Inject AUTOs" verilog-inject-auto
1415 :help "Inject AUTOs into legacy non-AUTO buffer"]
1417 ["AUTO General" (describe-function 'verilog-auto)
1418 :help "Help introduction on AUTOs"]
1419 ["AUTO Library Flags" (describe-variable 'verilog-library-flags)
1420 :help "Help on verilog-library-flags"]
1421 ["AUTO Library Path" (describe-variable 'verilog-library-directories)
1422 :help "Help on verilog-library-directories"]
1423 ["AUTO Library Files" (describe-variable 'verilog-library-files)
1424 :help "Help on verilog-library-files"]
1425 ["AUTO Library Extensions" (describe-variable 'verilog-library-extensions)
1426 :help "Help on verilog-library-extensions"]
1427 ["AUTO `define Reading" (describe-function 'verilog-read-defines)
1428 :help "Help on reading `defines"]
1429 ["AUTO `include Reading" (describe-function 'verilog-read-includes)
1430 :help "Help on parsing `includes"]
1431 ["AUTOARG" (describe-function 'verilog-auto-arg)
1432 :help "Help on AUTOARG - declaring module port list"]
1433 ["AUTOASCIIENUM" (describe-function 'verilog-auto-ascii-enum)
1434 :help "Help on AUTOASCIIENUM - creating ASCII for enumerations"]
1435 ["AUTOASSIGNMODPORT" (describe-function 'verilog-auto-assign-modport)
1436 :help "Help on AUTOASSIGNMODPORT - creating assignments to/from modports"]
1437 ["AUTOINOUTCOMP" (describe-function 'verilog-auto-inout-comp)
1438 :help "Help on AUTOINOUTCOMP - copying complemented i/o from another file"]
1439 ["AUTOINOUTIN" (describe-function 'verilog-auto-inout-in)
1440 :help "Help on AUTOINOUTIN - copying i/o from another file as all inputs"]
1441 ["AUTOINOUTMODPORT" (describe-function 'verilog-auto-inout-modport)
1442 :help "Help on AUTOINOUTMODPORT - copying i/o from an interface modport"]
1443 ["AUTOINOUTMODULE" (describe-function 'verilog-auto-inout-module)
1444 :help "Help on AUTOINOUTMODULE - copying i/o from another file"]
1445 ["AUTOINOUTPARAM" (describe-function 'verilog-auto-inout-param)
1446 :help "Help on AUTOINOUTPARAM - copying parameters from another file"]
1447 ["AUTOINSERTLISP" (describe-function 'verilog-auto-insert-lisp)
1448 :help "Help on AUTOINSERTLISP - insert text from a lisp function"]
1449 ["AUTOINOUT" (describe-function 'verilog-auto-inout)
1450 :help "Help on AUTOINOUT - adding inouts from cells"]
1451 ["AUTOINPUT" (describe-function 'verilog-auto-input)
1452 :help "Help on AUTOINPUT - adding inputs from cells"]
1453 ["AUTOINST" (describe-function 'verilog-auto-inst)
1454 :help "Help on AUTOINST - adding pins for cells"]
1455 ["AUTOINST (.*)" (describe-function 'verilog-auto-star)
1456 :help "Help on expanding Verilog-2001 .* pins"]
1457 ["AUTOINSTPARAM" (describe-function 'verilog-auto-inst-param)
1458 :help "Help on AUTOINSTPARAM - adding parameter pins to cells"]
1459 ["AUTOLOGIC" (describe-function 'verilog-auto-logic)
1460 :help "Help on AUTOLOGIC - declaring logic signals"]
1461 ["AUTOOUTPUT" (describe-function 'verilog-auto-output)
1462 :help "Help on AUTOOUTPUT - adding outputs from cells"]
1463 ["AUTOOUTPUTEVERY" (describe-function 'verilog-auto-output-every)
1464 :help "Help on AUTOOUTPUTEVERY - adding outputs of all signals"]
1465 ["AUTOREG" (describe-function 'verilog-auto-reg)
1466 :help "Help on AUTOREG - declaring registers for non-wires"]
1467 ["AUTOREGINPUT" (describe-function 'verilog-auto-reg-input)
1468 :help "Help on AUTOREGINPUT - declaring inputs for non-wires"]
1469 ["AUTORESET" (describe-function 'verilog-auto-reset)
1470 :help "Help on AUTORESET - resetting always blocks"]
1471 ["AUTOSENSE" (describe-function 'verilog-auto-sense)
1472 :help "Help on AUTOSENSE - sensitivity lists for always blocks"]
1473 ["AUTOTIEOFF" (describe-function 'verilog-auto-tieoff)
1474 :help "Help on AUTOTIEOFF - tying off unused outputs"]
1475 ["AUTOUNDEF" (describe-function 'verilog-auto-undef)
1476 :help "Help on AUTOUNDEF - undefine all local defines"]
1477 ["AUTOUNUSED" (describe-function 'verilog-auto-unused)
1478 :help "Help on AUTOUNUSED - terminating unused inputs"]
1479 ["AUTOWIRE" (describe-function 'verilog-auto-wire)
1480 :help "Help on AUTOWIRE - declaring wires for cells"]
1483 ["Submit bug report" verilog-submit-bug-report
1484 :help "Submit via mail a bug report on verilog-mode.el"]
1485 ["Version and FAQ" verilog-faq
1486 :help "Show the current version, and where to get the FAQ etc"]
1487 ["Customize Verilog Mode..." verilog-customize
1488 :help "Customize variables and other settings used by Verilog-Mode"]
1489 ["Customize Verilog Fonts & Colors" verilog-font-customize
1490 :help "Customize fonts used by Verilog-Mode."])))
1493 verilog-stmt-menu verilog-mode-map "Menu for statement templates in Verilog."
1494 (verilog-easy-menu-filter
1496 ["Header" verilog-sk-header
1497 :help "Insert a header block at the top of file"]
1498 ["Comment" verilog-sk-comment
1499 :help "Insert a comment block"]
1501 ["Module" verilog-sk-module
1502 :help "Insert a module .. (/*AUTOARG*/);.. endmodule block"]
1503 ["OVM Class" verilog-sk-ovm-class
1504 :help "Insert an OVM class block"]
1505 ["UVM Class" verilog-sk-uvm-class
1506 :help "Insert an UVM class block"]
1507 ["Primitive" verilog-sk-primitive
1508 :help "Insert a primitive .. (.. );.. endprimitive block"]
1510 ["Input" verilog-sk-input
1511 :help "Insert an input declaration"]
1512 ["Output" verilog-sk-output
1513 :help "Insert an output declaration"]
1514 ["Inout" verilog-sk-inout
1515 :help "Insert an inout declaration"]
1516 ["Wire" verilog-sk-wire
1517 :help "Insert a wire declaration"]
1518 ["Reg" verilog-sk-reg
1519 :help "Insert a register declaration"]
1520 ["Define thing under point as a register" verilog-sk-define-signal
1521 :help "Define signal under point as a register at the top of the module"]
1523 ["Initial" verilog-sk-initial
1524 :help "Insert an initial begin .. end block"]
1525 ["Always" verilog-sk-always
1526 :help "Insert an always @(AS) begin .. end block"]
1527 ["Function" verilog-sk-function
1528 :help "Insert a function .. begin .. end endfunction block"]
1529 ["Task" verilog-sk-task
1530 :help "Insert a task .. begin .. end endtask block"]
1531 ["Specify" verilog-sk-specify
1532 :help "Insert a specify .. endspecify block"]
1533 ["Generate" verilog-sk-generate
1534 :help "Insert a generate .. endgenerate block"]
1536 ["Begin" verilog-sk-begin
1537 :help "Insert a begin .. end block"]
1539 :help "Insert an if (..) begin .. end block"]
1540 ["(if) else" verilog-sk-else-if
1541 :help "Insert an else if (..) begin .. end block"]
1542 ["For" verilog-sk-for
1543 :help "Insert a for (...) begin .. end block"]
1544 ["While" verilog-sk-while
1545 :help "Insert a while (...) begin .. end block"]
1546 ["Fork" verilog-sk-fork
1547 :help "Insert a fork begin .. end .. join block"]
1548 ["Repeat" verilog-sk-repeat
1549 :help "Insert a repeat (..) begin .. end block"]
1550 ["Case" verilog-sk-case
1551 :help "Insert a case block, prompting for details"]
1552 ["Casex" verilog-sk-casex
1553 :help "Insert a casex (...) item: begin.. end endcase block"]
1554 ["Casez" verilog-sk-casez
1555 :help "Insert a casez (...) item: begin.. end endcase block"])))
1557 (defvar verilog-mode-abbrev-table nil
1558 "Abbrev table in use in Verilog-mode buffers.")
1560 (define-abbrev-table 'verilog-mode-abbrev-table ())
1561 (verilog-define-abbrev verilog-mode-abbrev-table "class" "" 'verilog-sk-ovm-class)
1562 (verilog-define-abbrev verilog-mode-abbrev-table "always" "" 'verilog-sk-always)
1563 (verilog-define-abbrev verilog-mode-abbrev-table "begin" nil `verilog-sk-begin)
1564 (verilog-define-abbrev verilog-mode-abbrev-table "case" "" `verilog-sk-case)
1565 (verilog-define-abbrev verilog-mode-abbrev-table "for" "" `verilog-sk-for)
1566 (verilog-define-abbrev verilog-mode-abbrev-table "generate" "" `verilog-sk-generate)
1567 (verilog-define-abbrev verilog-mode-abbrev-table "initial" "" `verilog-sk-initial)
1568 (verilog-define-abbrev verilog-mode-abbrev-table "fork" "" `verilog-sk-fork)
1569 (verilog-define-abbrev verilog-mode-abbrev-table "module" "" `verilog-sk-module)
1570 (verilog-define-abbrev verilog-mode-abbrev-table "primitive" "" `verilog-sk-primitive)
1571 (verilog-define-abbrev verilog-mode-abbrev-table "repeat" "" `verilog-sk-repeat)
1572 (verilog-define-abbrev verilog-mode-abbrev-table "specify" "" `verilog-sk-specify)
1573 (verilog-define-abbrev verilog-mode-abbrev-table "task" "" `verilog-sk-task)
1574 (verilog-define-abbrev verilog-mode-abbrev-table "while" "" `verilog-sk-while)
1575 (verilog-define-abbrev verilog-mode-abbrev-table "casex" "" `verilog-sk-casex)
1576 (verilog-define-abbrev verilog-mode-abbrev-table "casez" "" `verilog-sk-casez)
1577 (verilog-define-abbrev verilog-mode-abbrev-table "if" "" `verilog-sk-if)
1578 (verilog-define-abbrev verilog-mode-abbrev-table "else if" "" `verilog-sk-else-if)
1579 (verilog-define-abbrev verilog-mode-abbrev-table "assign" "" `verilog-sk-assign)
1580 (verilog-define-abbrev verilog-mode-abbrev-table "function" "" `verilog-sk-function)
1581 (verilog-define-abbrev verilog-mode-abbrev-table "input" "" `verilog-sk-input)
1582 (verilog-define-abbrev verilog-mode-abbrev-table "output" "" `verilog-sk-output)
1583 (verilog-define-abbrev verilog-mode-abbrev-table "inout" "" `verilog-sk-inout)
1584 (verilog-define-abbrev verilog-mode-abbrev-table "wire" "" `verilog-sk-wire)
1585 (verilog-define-abbrev verilog-mode-abbrev-table "reg" "" `verilog-sk-reg)
1591 (defsubst verilog-within-string ()
1592 (nth 3 (parse-partial-sexp (point-at-bol) (point))))
1594 (defsubst verilog-string-replace-matches (from-string to-string fixedcase literal string)
1595 "Replace occurrences of FROM-STRING with TO-STRING.
1596 FIXEDCASE and LITERAL as in `replace-match`. STRING is what to replace.
1597 The case (verilog-string-replace-matches \"o\" \"oo\" nil nil \"foobar\")
1598 will break, as the o's continuously replace. xa -> x works ok though."
1599 ;; Hopefully soon to an Emacs built-in
1600 ;; Also note \ in the replacement prevent multiple replacements; IE
1601 ;; (verilog-string-replace-matches "@" "\\\\([0-9]+\\\\)" nil nil "wire@_@")
1602 ;; Gives "wire\([0-9]+\)_@" not "wire\([0-9]+\)_\([0-9]+\)"
1604 (while (string-match from-string string start)
1605 (setq string (replace-match to-string fixedcase literal string)
1606 start (min (length string) (+ (match-beginning 0) (length to-string)))))
1609 (defsubst verilog-string-remove-spaces (string)
1610 "Remove spaces surrounding STRING."
1612 (setq string (verilog-string-replace-matches "^\\s-+" "" nil nil string))
1613 (setq string (verilog-string-replace-matches "\\s-+$" "" nil nil string))
1616 (defsubst verilog-re-search-forward (REGEXP BOUND NOERROR)
1617 ; checkdoc-params: (REGEXP BOUND NOERROR)
1618 "Like `re-search-forward', but skips over match in comments or strings."
1619 (let ((mdata '(nil nil))) ;; So match-end will return nil if no matches found
1621 (re-search-forward REGEXP BOUND NOERROR)
1622 (setq mdata (match-data))
1623 (and (verilog-skip-forward-comment-or-string)
1625 (setq mdata '(nil nil))
1629 (store-match-data mdata)
1632 (defsubst verilog-re-search-backward (REGEXP BOUND NOERROR)
1633 ; checkdoc-params: (REGEXP BOUND NOERROR)
1634 "Like `re-search-backward', but skips over match in comments or strings."
1635 (let ((mdata '(nil nil))) ;; So match-end will return nil if no matches found
1637 (re-search-backward REGEXP BOUND NOERROR)
1638 (setq mdata (match-data))
1639 (and (verilog-skip-backward-comment-or-string)
1641 (setq mdata '(nil nil))
1645 (store-match-data mdata)
1648 (defsubst verilog-re-search-forward-quick (regexp bound noerror)
1649 "Like `verilog-re-search-forward', including use of REGEXP BOUND and NOERROR,
1650 but trashes match data and is faster for REGEXP that doesn't match often.
1651 This uses `verilog-scan' and text properties to ignore comments,
1652 so there may be a large up front penalty for the first search."
1654 (while (and (not pt)
1655 (re-search-forward regexp bound noerror))
1656 (if (verilog-inside-comment-or-string-p)
1657 (re-search-forward "[/\"\n]" nil t) ;; Only way a comment or quote can end
1658 (setq pt (match-end 0))))
1661 (defsubst verilog-re-search-backward-quick (regexp bound noerror)
1662 ; checkdoc-params: (REGEXP BOUND NOERROR)
1663 "Like `verilog-re-search-backward', including use of REGEXP BOUND and NOERROR,
1664 but trashes match data and is faster for REGEXP that doesn't match often.
1665 This uses `verilog-scan' and text properties to ignore comments,
1666 so there may be a large up front penalty for the first search."
1668 (while (and (not pt)
1669 (re-search-backward regexp bound noerror))
1670 (if (verilog-inside-comment-or-string-p)
1671 (re-search-backward "[/\"]" nil t) ;; Only way a comment or quote can begin
1672 (setq pt (match-beginning 0))))
1675 (defsubst verilog-re-search-forward-substr (substr regexp bound noerror)
1676 "Like `re-search-forward', but first search for SUBSTR constant.
1677 Then searched for the normal REGEXP (which contains SUBSTR), with given
1678 BOUND and NOERROR. The REGEXP must fit within a single line.
1679 This speeds up complicated regexp matches."
1680 ;; Problem with overlap: search-forward BAR then FOOBARBAZ won't match.
1681 ;; thus require matches to be on one line, and use beginning-of-line.
1683 (while (and (not done)
1684 (search-forward substr bound noerror))
1687 (setq done (re-search-forward regexp (point-at-eol) noerror)))
1688 (unless (and (<= (match-beginning 0) (point))
1689 (>= (match-end 0) (point)))
1691 (when done (goto-char done))
1693 ;;(verilog-re-search-forward-substr "-end" "get-end-of" nil t) ;;-end (test bait)
1695 (defsubst verilog-re-search-backward-substr (substr regexp bound noerror)
1696 "Like `re-search-backward', but first search for SUBSTR constant.
1697 Then searched for the normal REGEXP (which contains SUBSTR), with given
1698 BOUND and NOERROR. The REGEXP must fit within a single line.
1699 This speeds up complicated regexp matches."
1700 ;; Problem with overlap: search-backward BAR then FOOBARBAZ won't match.
1701 ;; thus require matches to be on one line, and use beginning-of-line.
1703 (while (and (not done)
1704 (search-backward substr bound noerror))
1707 (setq done (re-search-backward regexp (point-at-bol) noerror)))
1708 (unless (and (<= (match-beginning 0) (point))
1709 (>= (match-end 0) (point)))
1711 (when done (goto-char done))
1713 ;;(verilog-re-search-backward-substr "-end" "get-end-of" nil t) ;;-end (test bait)
1715 (defun verilog-delete-trailing-whitespace ()
1716 "Delete trailing spaces or tabs, but not newlines nor linefeeds.
1717 Also add missing final newline.
1719 To call this from the command line, see \\[verilog-batch-diff-auto].
1721 To call on \\[verilog-auto], set `verilog-auto-delete-trailing-whitespace'."
1722 ;; Similar to `delete-trailing-whitespace' but that's not present in XEmacs
1724 (goto-char (point-min))
1725 (while (re-search-forward "[ \t]+$" nil t) ;; Not syntactic WS as no formfeed
1726 (replace-match "" nil nil))
1727 (goto-char (point-max))
1728 (unless (bolp) (insert "\n"))))
1730 (defvar compile-command)
1732 ;; compilation program
1733 (defun verilog-set-compile-command ()
1734 "Function to compute shell command to compile Verilog.
1736 This reads `verilog-tool' and sets `compile-command'. This specifies the
1737 program that executes when you type \\[compile] or
1738 \\[verilog-auto-save-compile].
1740 By default `verilog-tool' uses a Makefile if one exists in the
1741 current directory. If not, it is set to the `verilog-linter',
1742 `verilog-compiler', `verilog-coverage', `verilog-preprocessor',
1743 or `verilog-simulator' variables, as selected with the Verilog ->
1744 \"Choose Compilation Action\" menu.
1746 You should set `verilog-tool' or the other variables to the path and
1747 arguments for your Verilog simulator. For example:
1750 \"(cd /tmp; surecov %s)\".
1752 In the former case, the path to the current buffer is concat'ed to the
1753 value of `verilog-tool'; in the later, the path to the current buffer is
1754 substituted for the %s.
1756 Where __FLAGS__ appears in the string `verilog-current-flags'
1757 will be substituted.
1759 Where __FILE__ appears in the string, the variable
1760 `buffer-file-name' of the current buffer, without the directory
1761 portion, will be substituted."
1764 ((or (file-exists-p "makefile") ;If there is a makefile, use it
1765 (file-exists-p "Makefile"))
1766 (set (make-local-variable 'compile-command) "make "))
1768 (set (make-local-variable 'compile-command)
1770 (if (string-match "%s" (eval verilog-tool))
1771 (format (eval verilog-tool) (or buffer-file-name ""))
1772 (concat (eval verilog-tool) " " (or buffer-file-name "")))
1774 (verilog-modify-compile-command))
1776 (defun verilog-expand-command (command)
1777 "Replace meta-information in COMMAND and return it.
1778 Where __FLAGS__ appears in the string `verilog-current-flags'
1779 will be substituted. Where __FILE__ appears in the string, the
1780 current buffer's file-name, without the directory portion, will
1782 (setq command (verilog-string-replace-matches
1783 ;; Note \\b only works if under verilog syntax table
1784 "\\b__FLAGS__\\b" (verilog-current-flags)
1786 (setq command (verilog-string-replace-matches
1787 "\\b__FILE__\\b" (file-name-nondirectory
1788 (or (buffer-file-name) ""))
1792 (defun verilog-modify-compile-command ()
1793 "Update `compile-command' using `verilog-expand-command'."
1795 (stringp compile-command)
1796 (string-match "\\b\\(__FLAGS__\\|__FILE__\\)\\b" compile-command))
1797 (set (make-local-variable 'compile-command)
1798 (verilog-expand-command compile-command))))
1800 (if (featurep 'xemacs)
1801 ;; Following code only gets called from compilation-mode-hook on XEmacs to add error handling.
1802 (defun verilog-error-regexp-add-xemacs ()
1803 "Teach XEmacs about verilog errors.
1804 Called by `compilation-mode-hook'. This allows \\[next-error] to
1807 (if (boundp 'compilation-error-regexp-systems-alist)
1809 (not (equal compilation-error-regexp-systems-list 'all))
1810 (not (member compilation-error-regexp-systems-list 'verilog)))
1811 (push 'verilog compilation-error-regexp-systems-list)))
1812 (if (boundp 'compilation-error-regexp-alist-alist)
1813 (if (not (assoc 'verilog compilation-error-regexp-alist-alist))
1814 (setcdr compilation-error-regexp-alist-alist
1815 (cons verilog-error-regexp-xemacs-alist
1816 (cdr compilation-error-regexp-alist-alist)))))
1817 (if (boundp 'compilation-font-lock-keywords)
1819 (set (make-local-variable 'compilation-font-lock-keywords)
1820 verilog-error-font-lock-keywords)
1821 (font-lock-set-defaults)))
1822 ;; Need to re-run compilation-error-regexp builder
1823 (if (fboundp 'compilation-build-compilation-error-regexp-alist)
1824 (compilation-build-compilation-error-regexp-alist))
1827 ;; Following code only gets called from compilation-mode-hook on Emacs to add error handling.
1828 (defun verilog-error-regexp-add-emacs ()
1829 "Tell Emacs compile that we are Verilog.
1830 Called by `compilation-mode-hook'. This allows \\[next-error] to
1833 (if (boundp 'compilation-error-regexp-alist-alist)
1835 (if (not (assoc 'verilog-xl-1 compilation-error-regexp-alist-alist))
1838 (push (car item) compilation-error-regexp-alist)
1839 (push item compilation-error-regexp-alist-alist)
1841 verilog-error-regexp-emacs-alist)))))
1843 (if (featurep 'xemacs) (add-hook 'compilation-mode-hook 'verilog-error-regexp-add-xemacs))
1844 (if (featurep 'emacs) (add-hook 'compilation-mode-hook 'verilog-error-regexp-add-emacs))
1846 (defconst verilog-directive-re
1848 (verilog-regexp-words
1850 "`case" "`default" "`define" "`else" "`elsif" "`endfor" "`endif"
1851 "`endprotect" "`endswitch" "`endwhile" "`for" "`format" "`if" "`ifdef"
1852 "`ifndef" "`include" "`let" "`protect" "`switch" "`timescale"
1853 "`time_scale" "`undef" "`while" ))))
1855 (defconst verilog-directive-re-1
1856 (concat "[ \t]*" verilog-directive-re))
1858 (defconst verilog-directive-begin
1859 "\\<`\\(for\\|i\\(f\\|fdef\\|fndef\\)\\|switch\\|while\\)\\>")
1861 (defconst verilog-directive-middle
1862 "\\<`\\(else\\|elsif\\|default\\|case\\)\\>")
1864 (defconst verilog-directive-end
1865 "`\\(endfor\\|endif\\|endswitch\\|endwhile\\)\\>")
1867 (defconst verilog-ovm-begin-re
1871 "`ovm_component_utils_begin"
1872 "`ovm_component_param_utils_begin"
1873 "`ovm_field_utils_begin"
1874 "`ovm_object_utils_begin"
1875 "`ovm_object_param_utils_begin"
1876 "`ovm_sequence_utils_begin"
1877 "`ovm_sequencer_utils_begin"
1880 (defconst verilog-ovm-end-re
1884 "`ovm_component_utils_end"
1885 "`ovm_field_utils_end"
1886 "`ovm_object_utils_end"
1887 "`ovm_sequence_utils_end"
1888 "`ovm_sequencer_utils_end"
1891 (defconst verilog-uvm-begin-re
1895 "`uvm_component_utils_begin"
1896 "`uvm_component_param_utils_begin"
1897 "`uvm_field_utils_begin"
1898 "`uvm_object_utils_begin"
1899 "`uvm_object_param_utils_begin"
1900 "`uvm_sequence_utils_begin"
1901 "`uvm_sequencer_utils_begin"
1904 (defconst verilog-uvm-end-re
1908 "`uvm_component_utils_end"
1909 "`uvm_field_utils_end"
1910 "`uvm_object_utils_end"
1911 "`uvm_sequence_utils_end"
1912 "`uvm_sequencer_utils_end"
1915 (defconst verilog-vmm-begin-re
1919 "`vmm_data_member_begin"
1920 "`vmm_env_member_begin"
1921 "`vmm_scenario_member_begin"
1922 "`vmm_subenv_member_begin"
1923 "`vmm_xactor_member_begin"
1926 (defconst verilog-vmm-end-re
1930 "`vmm_data_member_end"
1931 "`vmm_env_member_end"
1932 "`vmm_scenario_member_end"
1933 "`vmm_subenv_member_end"
1934 "`vmm_xactor_member_end"
1937 (defconst verilog-vmm-statement-re
1941 ;; "`vmm_xactor_member_enum_array"
1942 "`vmm_\\(data\\|env\\|scenario\\|subenv\\|xactor\\)_member_\\(scalar\\|string\\|enum\\|vmm_data\\|channel\\|xactor\\|subenv\\|user_defined\\)\\(_array\\)?"
1943 ;; "`vmm_xactor_member_scalar_array"
1944 ;; "`vmm_xactor_member_scalar"
1947 (defconst verilog-ovm-statement-re
1956 "`ovm_analysis_imp_decl"
1957 "`ovm_blocking_get_imp_decl"
1958 "`ovm_blocking_get_peek_imp_decl"
1959 "`ovm_blocking_master_imp_decl"
1960 "`ovm_blocking_peek_imp_decl"
1961 "`ovm_blocking_put_imp_decl"
1962 "`ovm_blocking_slave_imp_decl"
1963 "`ovm_blocking_transport_imp_decl"
1964 "`ovm_component_registry"
1965 "`ovm_component_registry_param"
1966 "`ovm_component_utils"
1969 "`ovm_declare_sequence_lib"
1976 "`ovm_field_aa_int_byte"
1977 "`ovm_field_aa_int_byte_unsigned"
1978 "`ovm_field_aa_int_int"
1979 "`ovm_field_aa_int_int_unsigned"
1980 "`ovm_field_aa_int_integer"
1981 "`ovm_field_aa_int_integer_unsigned"
1982 "`ovm_field_aa_int_key"
1983 "`ovm_field_aa_int_longint"
1984 "`ovm_field_aa_int_longint_unsigned"
1985 "`ovm_field_aa_int_shortint"
1986 "`ovm_field_aa_int_shortint_unsigned"
1987 "`ovm_field_aa_int_string"
1988 "`ovm_field_aa_object_int"
1989 "`ovm_field_aa_object_string"
1990 "`ovm_field_aa_string_int"
1991 "`ovm_field_aa_string_string"
1992 "`ovm_field_array_int"
1993 "`ovm_field_array_object"
1994 "`ovm_field_array_string"
1999 "`ovm_field_queue_int"
2000 "`ovm_field_queue_object"
2001 "`ovm_field_queue_string"
2002 "`ovm_field_sarray_int"
2007 "`ovm_get_peek_imp_decl"
2014 "`ovm_master_imp_decl"
2016 "`ovm_non_blocking_transport_imp_decl"
2017 "`ovm_nonblocking_get_imp_decl"
2018 "`ovm_nonblocking_get_peek_imp_decl"
2019 "`ovm_nonblocking_master_imp_decl"
2020 "`ovm_nonblocking_peek_imp_decl"
2021 "`ovm_nonblocking_put_imp_decl"
2022 "`ovm_nonblocking_slave_imp_decl"
2023 "`ovm_object_registry"
2024 "`ovm_object_registry_param"
2026 "`ovm_peek_imp_decl"
2027 "`ovm_phase_func_decl"
2028 "`ovm_phase_task_decl"
2029 "`ovm_print_aa_int_object"
2030 "`ovm_print_aa_string_int"
2031 "`ovm_print_aa_string_object"
2032 "`ovm_print_aa_string_string"
2033 "`ovm_print_array_int"
2034 "`ovm_print_array_object"
2035 "`ovm_print_array_string"
2036 "`ovm_print_object_queue"
2037 "`ovm_print_queue_int"
2038 "`ovm_print_string_queue"
2041 "`ovm_rand_send_with"
2043 "`ovm_sequence_utils"
2044 "`ovm_slave_imp_decl"
2045 "`ovm_transport_imp_decl"
2046 "`ovm_update_sequence_lib"
2047 "`ovm_update_sequence_lib_and_item"
2050 "`static_message") nil )))
2052 (defconst verilog-uvm-statement-re
2057 "`uvm_analysis_imp_decl"
2058 "`uvm_blocking_get_imp_decl"
2059 "`uvm_blocking_get_peek_imp_decl"
2060 "`uvm_blocking_master_imp_decl"
2061 "`uvm_blocking_peek_imp_decl"
2062 "`uvm_blocking_put_imp_decl"
2063 "`uvm_blocking_slave_imp_decl"
2064 "`uvm_blocking_transport_imp_decl"
2065 "`uvm_component_param_utils"
2066 "`uvm_component_registry"
2067 "`uvm_component_registry_param"
2068 "`uvm_component_utils"
2071 "`uvm_create_seq" ;; Undocumented in 1.1
2072 "`uvm_declare_p_sequencer"
2073 "`uvm_declare_sequence_lib" ;; Deprecated in 1.1
2076 "`uvm_do_callbacks_exit_on"
2077 "`uvm_do_obj_callbacks"
2078 "`uvm_do_obj_callbacks_exit_on"
2081 "`uvm_do_on_pri_with"
2085 "`uvm_do_seq" ;; Undocumented in 1.1
2086 "`uvm_do_seq_with" ;; Undocumented in 1.1
2089 "`uvm_error_context"
2091 "`uvm_fatal_context"
2092 "`uvm_field_aa_int_byte"
2093 "`uvm_field_aa_int_byte_unsigned"
2094 "`uvm_field_aa_int_enum"
2095 "`uvm_field_aa_int_int"
2096 "`uvm_field_aa_int_int_unsigned"
2097 "`uvm_field_aa_int_integer"
2098 "`uvm_field_aa_int_integer_unsigned"
2099 "`uvm_field_aa_int_key"
2100 "`uvm_field_aa_int_longint"
2101 "`uvm_field_aa_int_longint_unsigned"
2102 "`uvm_field_aa_int_shortint"
2103 "`uvm_field_aa_int_shortint_unsigned"
2104 "`uvm_field_aa_int_string"
2105 "`uvm_field_aa_object_int"
2106 "`uvm_field_aa_object_string"
2107 "`uvm_field_aa_string_int"
2108 "`uvm_field_aa_string_string"
2109 "`uvm_field_array_enum"
2110 "`uvm_field_array_int"
2111 "`uvm_field_array_object"
2112 "`uvm_field_array_string"
2117 "`uvm_field_queue_enum"
2118 "`uvm_field_queue_int"
2119 "`uvm_field_queue_object"
2120 "`uvm_field_queue_string"
2122 "`uvm_field_sarray_enum"
2123 "`uvm_field_sarray_int"
2124 "`uvm_field_sarray_object"
2125 "`uvm_field_sarray_string"
2128 "`uvm_file" ;; Undocumented in 1.1, use `__FILE__
2130 "`uvm_get_peek_imp_decl"
2133 "`uvm_line" ;; Undocumented in 1.1, use `__LINE__
2134 "`uvm_master_imp_decl"
2135 "`uvm_non_blocking_transport_imp_decl" ;; Deprecated in 1.1
2136 "`uvm_nonblocking_get_imp_decl"
2137 "`uvm_nonblocking_get_peek_imp_decl"
2138 "`uvm_nonblocking_master_imp_decl"
2139 "`uvm_nonblocking_peek_imp_decl"
2140 "`uvm_nonblocking_put_imp_decl"
2141 "`uvm_nonblocking_slave_imp_decl"
2142 "`uvm_nonblocking_transport_imp_decl"
2143 "`uvm_object_param_utils"
2144 "`uvm_object_registry"
2145 "`uvm_object_registry_param" ;; Undocumented in 1.1
2159 "`uvm_peek_imp_decl"
2162 "`uvm_rand_send_pri"
2163 "`uvm_rand_send_pri_with"
2164 "`uvm_rand_send_with"
2165 "`uvm_record_attribute"
2170 "`uvm_sequence_utils" ;; Deprecated in 1.1
2171 "`uvm_set_super_type"
2172 "`uvm_slave_imp_decl"
2173 "`uvm_transport_imp_decl"
2175 "`uvm_unpack_arrayN"
2181 "`uvm_unpack_queueN"
2183 "`uvm_unpack_sarray"
2184 "`uvm_unpack_sarrayN"
2185 "`uvm_unpack_string"
2186 "`uvm_update_sequence_lib" ;; Deprecated in 1.1
2187 "`uvm_update_sequence_lib_and_item" ;; Deprecated in 1.1
2189 "`uvm_warning_context") nil )))
2193 ;; Regular expressions used to calculate indent, etc.
2195 (defconst verilog-symbol-re "\\<[a-zA-Z_][a-zA-Z_0-9.]*\\>")
2202 (defconst verilog-assignment-operator-re
2206 ;; blocking assignment_operator
2207 "=" "+=" "-=" "*=" "/=" "%=" "&=" "|=" "^=" "<<=" ">>=" "<<<=" ">>>="
2208 ;; non blocking assignment operator
2211 "==" "!=" "===" "!===" "<=" ">=" "==\?" "!=\?"
2216 ;; Is this a legal verilog operator?
2220 (defconst verilog-assignment-operation-re
2222 ; "\\(^\\s-*[A-Za-z0-9_]+\\(\\[\\([A-Za-z0-9_]+\\)\\]\\)*\\s-*\\)"
2223 ; "\\(^\\s-*[^=<>+-*/%&|^:\\s-]+[^=<>+-*/%&|^\n]*?\\)"
2224 "\\(^.*?\\)" "\\B" verilog-assignment-operator-re "\\B" ))
2226 (defconst verilog-label-re (concat verilog-symbol-re "\\s-*:\\s-*"))
2227 (defconst verilog-property-re
2228 (concat "\\(" verilog-label-re "\\)?"
2229 "\\(\\(assert\\|assume\\|cover\\)\\>\\s-+\\<property\\>\\)\\|\\(assert\\)"))
2230 ;; "\\(assert\\|assume\\|cover\\)\\s-+property\\>"
2232 (defconst verilog-no-indent-begin-re
2233 "\\<\\(if\\|else\\|while\\|for\\|repeat\\|always\\|always_comb\\|always_ff\\|always_latch\\)\\>")
2235 (defconst verilog-ends-re
2236 ;; Parenthesis indicate type of keyword found
2238 "\\(\\<else\\>\\)\\|" ; 1
2239 "\\(\\<if\\>\\)\\|" ; 2
2240 "\\(\\<assert\\>\\)\\|" ; 3
2241 "\\(\\<end\\>\\)\\|" ; 3.1
2242 "\\(\\<endcase\\>\\)\\|" ; 4
2243 "\\(\\<endfunction\\>\\)\\|" ; 5
2244 "\\(\\<endtask\\>\\)\\|" ; 6
2245 "\\(\\<endspecify\\>\\)\\|" ; 7
2246 "\\(\\<endtable\\>\\)\\|" ; 8
2247 "\\(\\<endgenerate\\>\\)\\|" ; 9
2248 "\\(\\<join\\(_any\\|_none\\)?\\>\\)\\|" ; 10
2249 "\\(\\<endclass\\>\\)\\|" ; 11
2250 "\\(\\<endgroup\\>\\)\\|" ; 12
2252 "\\(\\<`vmm_data_member_end\\>\\)\\|"
2253 "\\(\\<`vmm_env_member_end\\>\\)\\|"
2254 "\\(\\<`vmm_scenario_member_end\\>\\)\\|"
2255 "\\(\\<`vmm_subenv_member_end\\>\\)\\|"
2256 "\\(\\<`vmm_xactor_member_end\\>\\)\\|"
2258 "\\(\\<`ovm_component_utils_end\\>\\)\\|"
2259 "\\(\\<`ovm_field_utils_end\\>\\)\\|"
2260 "\\(\\<`ovm_object_utils_end\\>\\)\\|"
2261 "\\(\\<`ovm_sequence_utils_end\\>\\)\\|"
2262 "\\(\\<`ovm_sequencer_utils_end\\>\\)"
2264 "\\(\\<`uvm_component_utils_end\\>\\)\\|"
2265 "\\(\\<`uvm_field_utils_end\\>\\)\\|"
2266 "\\(\\<`uvm_object_utils_end\\>\\)\\|"
2267 "\\(\\<`uvm_sequence_utils_end\\>\\)\\|"
2268 "\\(\\<`uvm_sequencer_utils_end\\>\\)"
2271 (defconst verilog-auto-end-comment-lines-re
2272 ;; Matches to names in this list cause auto-end-commenting
2274 verilog-directive-re "\\)\\|\\("
2276 (verilog-regexp-words
2304 ;;; NOTE: verilog-leap-to-head expects that verilog-end-block-re and
2305 ;;; verilog-end-block-ordered-re matches exactly the same strings.
2306 (defconst verilog-end-block-ordered-re
2307 ;; Parenthesis indicate type of keyword found
2308 (concat "\\(\\<endcase\\>\\)\\|" ; 1
2309 "\\(\\<end\\>\\)\\|" ; 2
2310 "\\(\\<end" ; 3, but not used
2311 "\\(" ; 4, but not used
2312 "\\(function\\)\\|" ; 5
2314 "\\(module\\)\\|" ; 7
2315 "\\(primitive\\)\\|" ; 8
2316 "\\(interface\\)\\|" ; 9
2317 "\\(package\\)\\|" ; 10
2318 "\\(class\\)\\|" ; 11
2319 "\\(group\\)\\|" ; 12
2320 "\\(program\\)\\|" ; 13
2321 "\\(sequence\\)\\|" ; 14
2322 "\\(clocking\\)\\|" ; 15
2324 (defconst verilog-end-block-re
2326 (verilog-regexp-words
2328 `("end" ;; closes begin
2329 "endcase" ;; closes any of case, casex casez or randcase
2330 "join" "join_any" "join_none" ;; closes fork
2345 "`ovm_component_utils_end"
2346 "`ovm_field_utils_end"
2347 "`ovm_object_utils_end"
2348 "`ovm_sequence_utils_end"
2349 "`ovm_sequencer_utils_end"
2351 "`uvm_component_utils_end"
2352 "`uvm_field_utils_end"
2353 "`uvm_object_utils_end"
2354 "`uvm_sequence_utils_end"
2355 "`uvm_sequencer_utils_end"
2357 "`vmm_data_member_end"
2358 "`vmm_env_member_end"
2359 "`vmm_scenario_member_end"
2360 "`vmm_subenv_member_end"
2361 "`vmm_xactor_member_end"
2365 (defconst verilog-endcomment-reason-re
2366 ;; Parenthesis indicate type of keyword found
2368 "\\(\\<begin\\>\\)\\|" ; 1
2369 "\\(\\<else\\>\\)\\|" ; 2
2370 "\\(\\<end\\>\\s-+\\<else\\>\\)\\|" ; 3
2371 "\\(\\<always_comb\\>\\(\[ \t\]*@\\)?\\)\\|" ; 4
2372 "\\(\\<always_ff\\>\\(\[ \t\]*@\\)?\\)\\|" ; 5
2373 "\\(\\<always_latch\\>\\(\[ \t\]*@\\)?\\)\\|" ; 6
2374 "\\(\\<fork\\>\\)\\|" ; 7
2375 "\\(\\<always\\>\\(\[ \t\]*@\\)?\\)\\|"
2377 verilog-property-re "\\|"
2378 "\\(\\(" verilog-label-re "\\)?\\<assert\\>\\)\\|"
2379 "\\(\\<clocking\\>\\)\\|"
2380 "\\(\\<task\\>\\)\\|"
2381 "\\(\\<function\\>\\)\\|"
2382 "\\(\\<initial\\>\\)\\|"
2383 "\\(\\<interface\\>\\)\\|"
2384 "\\(\\<package\\>\\)\\|"
2385 "\\(\\<final\\>\\)\\|"
2387 "\\(\\<while\\>\\)\\|"
2388 "\\(\\<for\\(ever\\|each\\)?\\>\\)\\|"
2389 "\\(\\<repeat\\>\\)\\|\\(\\<wait\\>\\)\\|"
2392 (defconst verilog-named-block-re "begin[ \t]*:")
2394 ;; These words begin a block which can occur inside a module which should be indented,
2395 ;; and closed with the respective word from the end-block list
2397 (defconst verilog-beg-block-re
2399 (verilog-regexp-words
2401 "case" "casex" "casez" "randcase"
2411 "`ovm_component_utils_begin"
2412 "`ovm_component_param_utils_begin"
2413 "`ovm_field_utils_begin"
2414 "`ovm_object_utils_begin"
2415 "`ovm_object_param_utils_begin"
2416 "`ovm_sequence_utils_begin"
2417 "`ovm_sequencer_utils_begin"
2419 "`uvm_component_utils_begin"
2420 "`uvm_component_param_utils_begin"
2421 "`uvm_field_utils_begin"
2422 "`uvm_object_utils_begin"
2423 "`uvm_object_param_utils_begin"
2424 "`uvm_sequence_utils_begin"
2425 "`uvm_sequencer_utils_begin"
2427 "`vmm_data_member_begin"
2428 "`vmm_env_member_begin"
2429 "`vmm_scenario_member_begin"
2430 "`vmm_subenv_member_begin"
2431 "`vmm_xactor_member_begin"
2433 ;; These are the same words, in a specific order in the regular
2434 ;; expression so that matching will work nicely for
2435 ;; verilog-forward-sexp and verilog-calc-indent
2436 (defconst verilog-beg-block-re-ordered
2437 ( concat "\\(\\<begin\\>\\)" ;1
2438 "\\|\\(\\<randcase\\>\\|\\(\\<unique\\s-+\\|priority\\s-+\\)?case[xz]?\\>\\)" ; 2,3
2439 "\\|\\(\\(\\<disable\\>\\s-+\\|\\<wait\\>\\s-+\\)?fork\\>\\)" ;4,5
2440 "\\|\\(\\<class\\>\\)" ;6
2441 "\\|\\(\\<table\\>\\)" ;7
2442 "\\|\\(\\<specify\\>\\)" ;8
2443 "\\|\\(\\<function\\>\\)" ;9
2444 "\\|\\(\\(\\(\\<virtual\\>\\s-+\\)\\|\\(\\<protected\\>\\s-+\\)\\)*\\<function\\>\\)" ;10
2445 "\\|\\(\\<task\\>\\)" ;14
2446 "\\|\\(\\(\\(\\<virtual\\>\\s-+\\)\\|\\(\\<protected\\>\\s-+\\)\\)*\\<task\\>\\)" ;15
2447 "\\|\\(\\<generate\\>\\)" ;18
2448 "\\|\\(\\<covergroup\\>\\)" ;16 20
2449 "\\|\\(\\(\\(\\<cover\\>\\s-+\\)\\|\\(\\<assert\\>\\s-+\\)\\)*\\<property\\>\\)" ;17 21
2450 "\\|\\(\\<\\(rand\\)?sequence\\>\\)" ;21 25
2451 "\\|\\(\\<clocking\\>\\)" ;22 27
2452 "\\|\\(\\<`[ou]vm_[a-z_]+_begin\\>\\)" ;28
2453 "\\|\\(\\<`vmm_[a-z_]+_member_begin\\>\\)"
2457 (defconst verilog-end-block-ordered-rry
2458 [ "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<endcase\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)"
2459 "\\(\\<randcase\\>\\|\\<case[xz]?\\>\\)\\|\\(\\<endcase\\>\\)"
2460 "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)"
2461 "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)"
2462 "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)"
2463 "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)"
2464 "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)"
2465 "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)"
2466 "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)"
2467 "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)"
2468 "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)"
2469 "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)"
2470 "\\(\\<clocking\\>\\)\\|\\(\\<endclocking\\>\\)"
2473 (defconst verilog-nameable-item-re
2475 (verilog-regexp-words
2478 "join" "join_any" "join_none"
2495 (defconst verilog-declaration-opener
2497 (verilog-regexp-words
2498 `("module" "begin" "task" "function"))))
2500 (defconst verilog-declaration-prefix-re
2502 (verilog-regexp-words
2505 "inout" "input" "output" "ref"
2507 "const" "static" "protected" "local"
2509 "localparam" "parameter" "var"
2513 (defconst verilog-declaration-core-re
2515 (verilog-regexp-words
2517 ;; port direction (by themselves)
2518 "inout" "input" "output"
2519 ;; integer_atom_type
2520 "byte" "shortint" "int" "longint" "integer" "time"
2521 ;; integer_vector_type
2524 "shortreal" "real" "realtime"
2526 "supply0" "supply1" "tri" "triand" "trior" "trireg" "tri0" "tri1" "uwire" "wire" "wand" "wor"
2528 "string" "event" "chandle" "virtual" "enum" "genvar"
2531 "mailbox" "semaphore"
2533 (defconst verilog-declaration-re
2534 (concat "\\(" verilog-declaration-prefix-re "\\s-*\\)?" verilog-declaration-core-re))
2535 (defconst verilog-range-re "\\(\\[[^]]*\\]\\s-*\\)+")
2536 (defconst verilog-optional-signed-re "\\s-*\\(signed\\)?")
2537 (defconst verilog-optional-signed-range-re
2539 "\\s-*\\(\\<\\(reg\\|wire\\)\\>\\s-*\\)?\\(\\<signed\\>\\s-*\\)?\\(" verilog-range-re "\\)?"))
2540 (defconst verilog-macroexp-re "`\\sw+")
2542 (defconst verilog-delay-re "#\\s-*\\(\\([0-9_]+\\('s?[hdxbo][0-9a-fA-F_xz]+\\)?\\)\\|\\(([^()]*)\\)\\|\\(\\sw+\\)\\)")
2543 (defconst verilog-declaration-re-2-no-macro
2544 (concat "\\s-*" verilog-declaration-re
2545 "\\s-*\\(\\(" verilog-optional-signed-range-re "\\)\\|\\(" verilog-delay-re "\\)"
2547 (defconst verilog-declaration-re-2-macro
2548 (concat "\\s-*" verilog-declaration-re
2549 "\\s-*\\(\\(" verilog-optional-signed-range-re "\\)\\|\\(" verilog-delay-re "\\)"
2550 "\\|\\(" verilog-macroexp-re "\\)"
2552 (defconst verilog-declaration-re-1-macro
2553 (concat "^" verilog-declaration-re-2-macro))
2555 (defconst verilog-declaration-re-1-no-macro (concat "^" verilog-declaration-re-2-no-macro))
2557 (defconst verilog-defun-re
2558 (eval-when-compile (verilog-regexp-words `("macromodule" "module" "class" "program" "interface" "package" "primitive" "config"))))
2559 (defconst verilog-end-defun-re
2560 (eval-when-compile (verilog-regexp-words `("endmodule" "endclass" "endprogram" "endinterface" "endpackage" "endprimitive" "endconfig"))))
2561 (defconst verilog-zero-indent-re
2562 (concat verilog-defun-re "\\|" verilog-end-defun-re))
2563 (defconst verilog-inst-comment-re
2564 (eval-when-compile (verilog-regexp-words `("Outputs" "Inouts" "Inputs" "Interfaces" "Interfaced"))))
2566 (defconst verilog-behavioral-block-beg-re
2567 (eval-when-compile (verilog-regexp-words `("initial" "final" "always" "always_comb" "always_latch" "always_ff"
2568 "function" "task"))))
2569 (defconst verilog-coverpoint-re "\\w+\\s*:\\s*\\(coverpoint\\|cross\\constraint\\)" )
2570 (defconst verilog-indent-re
2572 (verilog-regexp-words
2575 "always" "always_latch" "always_ff" "always_comb"
2577 ; "unique" "priority"
2578 "case" "casex" "casez" "randcase" "endcase"
2580 "clocking" "endclocking"
2581 "config" "endconfig"
2582 "covergroup" "endgroup"
2583 "fork" "join" "join_any" "join_none"
2584 "function" "endfunction"
2586 "generate" "endgenerate"
2588 "interface" "endinterface"
2589 "module" "macromodule" "endmodule"
2590 "package" "endpackage"
2591 "primitive" "endprimitive"
2592 "program" "endprogram"
2593 "property" "endproperty"
2594 "sequence" "randsequence" "endsequence"
2595 "specify" "endspecify"
2602 "`if" "`ifdef" "`ifndef" "`else" "`elsif" "`endif"
2603 "`while" "`endwhile"
2608 "`protect" "`endprotect"
2609 "`switch" "`endswitch"
2613 "`ovm_component_utils_begin"
2614 "`ovm_component_param_utils_begin"
2615 "`ovm_field_utils_begin"
2616 "`ovm_object_utils_begin"
2617 "`ovm_object_param_utils_begin"
2618 "`ovm_sequence_utils_begin"
2619 "`ovm_sequencer_utils_begin"
2621 "`ovm_component_utils_end"
2622 "`ovm_field_utils_end"
2623 "`ovm_object_utils_end"
2624 "`ovm_sequence_utils_end"
2625 "`ovm_sequencer_utils_end"
2627 "`uvm_component_utils_begin"
2628 "`uvm_component_param_utils_begin"
2629 "`uvm_field_utils_begin"
2630 "`uvm_object_utils_begin"
2631 "`uvm_object_param_utils_begin"
2632 "`uvm_sequence_utils_begin"
2633 "`uvm_sequencer_utils_begin"
2635 "`uvm_component_utils_end" ;; Typo in spec, it's not uvm_component_end
2636 "`uvm_field_utils_end"
2637 "`uvm_object_utils_end"
2638 "`uvm_sequence_utils_end"
2639 "`uvm_sequencer_utils_end"
2641 "`vmm_data_member_begin"
2642 "`vmm_env_member_begin"
2643 "`vmm_scenario_member_begin"
2644 "`vmm_subenv_member_begin"
2645 "`vmm_xactor_member_begin"
2647 "`vmm_data_member_end"
2648 "`vmm_env_member_end"
2649 "`vmm_scenario_member_end"
2650 "`vmm_subenv_member_end"
2651 "`vmm_xactor_member_end"
2654 (defconst verilog-defun-level-not-generate-re
2656 (verilog-regexp-words
2657 `( "module" "macromodule" "primitive" "class" "program"
2658 "interface" "package" "config"))))
2660 (defconst verilog-defun-level-re
2662 (verilog-regexp-words
2664 `( "module" "macromodule" "primitive" "class" "program"
2665 "interface" "package" "config")
2666 `( "initial" "final" "always" "always_comb" "always_ff"
2667 "always_latch" "endtask" "endfunction" )))))
2669 (defconst verilog-defun-level-generate-only-re
2671 (verilog-regexp-words
2672 `( "initial" "final" "always" "always_comb" "always_ff"
2673 "always_latch" "endtask" "endfunction" ))))
2675 (defconst verilog-cpp-level-re
2677 (verilog-regexp-words
2679 "endmodule" "endprimitive" "endinterface" "endpackage" "endprogram" "endclass"
2681 (defconst verilog-disable-fork-re "\\(disable\\|wait\\)\\s-+fork\\>")
2682 (defconst verilog-extended-case-re "\\(\\(unique\\s-+\\|priority\\s-+\\)?case[xz]?\\)")
2683 (defconst verilog-extended-complete-re
2684 (concat "\\(\\(\\<extern\\s-+\\|\\<\\(\\<pure\\>\\s-+\\)?virtual\\s-+\\|\\<protected\\s-+\\)*\\(\\<function\\>\\|\\<task\\>\\)\\)"
2685 "\\|\\(\\(\\<typedef\\>\\s-+\\)*\\(\\<struct\\>\\|\\<union\\>\\|\\<class\\>\\)\\)"
2686 "\\|\\(\\(\\<import\\>\\s-+\\)?\\(\"DPI-C\"\\s-+\\)?\\(\\<pure\\>\\s-+\\)?\\(function\\>\\|task\\>\\)\\)"
2687 "\\|" verilog-extended-case-re ))
2688 (defconst verilog-basic-complete-re
2690 (verilog-regexp-words
2692 "always" "assign" "always_latch" "always_ff" "always_comb" "constraint"
2693 "import" "initial" "final" "module" "macromodule" "repeat" "randcase" "while"
2694 "if" "for" "forever" "foreach" "else" "parameter" "do" "localparam" "assert"
2696 (defconst verilog-complete-reg
2698 verilog-extended-complete-re "\\|\\(" verilog-basic-complete-re "\\)"))
2700 (defconst verilog-end-statement-re
2701 (concat "\\(" verilog-beg-block-re "\\)\\|\\("
2702 verilog-end-block-re "\\)"))
2704 (defconst verilog-endcase-re
2705 (concat verilog-extended-case-re "\\|"
2710 (defconst verilog-exclude-str-start "/* -----\\/----- EXCLUDED -----\\/-----"
2711 "String used to mark beginning of excluded text.")
2712 (defconst verilog-exclude-str-end " -----/\\----- EXCLUDED -----/\\----- */"
2713 "String used to mark end of excluded text.")
2714 (defconst verilog-preprocessor-re
2716 (verilog-regexp-words
2718 "`define" "`include" "`ifdef" "`ifndef" "`if" "`endif" "`else"
2721 (defconst verilog-keywords
2722 '( "`case" "`default" "`define" "`else" "`endfor" "`endif"
2723 "`endprotect" "`endswitch" "`endwhile" "`for" "`format" "`if" "`ifdef"
2724 "`ifndef" "`include" "`let" "`protect" "`switch" "`timescale"
2725 "`time_scale" "`undef" "`while"
2727 "after" "alias" "always" "always_comb" "always_ff" "always_latch" "and"
2728 "assert" "assign" "assume" "automatic" "before" "begin" "bind"
2729 "bins" "binsof" "bit" "break" "buf" "bufif0" "bufif1" "byte"
2730 "case" "casex" "casez" "cell" "chandle" "class" "clocking" "cmos"
2731 "config" "const" "constraint" "context" "continue" "cover"
2732 "covergroup" "coverpoint" "cross" "deassign" "default" "defparam"
2733 "design" "disable" "dist" "do" "edge" "else" "end" "endcase"
2734 "endclass" "endclocking" "endconfig" "endfunction" "endgenerate"
2735 "endgroup" "endinterface" "endmodule" "endpackage" "endprimitive"
2736 "endprogram" "endproperty" "endspecify" "endsequence" "endtable"
2737 "endtask" "enum" "event" "expect" "export" "extends" "extern"
2738 "final" "first_match" "for" "force" "foreach" "forever" "fork"
2739 "forkjoin" "function" "generate" "genvar" "highz0" "highz1" "if"
2740 "iff" "ifnone" "ignore_bins" "illegal_bins" "import" "incdir"
2741 "include" "initial" "inout" "input" "inside" "instance" "int"
2742 "integer" "interface" "intersect" "join" "join_any" "join_none"
2743 "large" "liblist" "library" "local" "localparam" "logic"
2744 "longint" "macromodule" "mailbox" "matches" "medium" "modport" "module"
2745 "nand" "negedge" "new" "nmos" "nor" "noshowcancelled" "not"
2746 "notif0" "notif1" "null" "or" "output" "package" "packed"
2747 "parameter" "pmos" "posedge" "primitive" "priority" "program"
2748 "property" "protected" "pull0" "pull1" "pulldown" "pullup"
2749 "pulsestyle_onevent" "pulsestyle_ondetect" "pure" "rand" "randc"
2750 "randcase" "randsequence" "rcmos" "real" "realtime" "ref" "reg"
2751 "release" "repeat" "return" "rnmos" "rpmos" "rtran" "rtranif0"
2752 "rtranif1" "scalared" "semaphore" "sequence" "shortint" "shortreal"
2753 "showcancelled" "signed" "small" "solve" "specify" "specparam"
2754 "static" "string" "strong0" "strong1" "struct" "super" "supply0"
2755 "supply1" "table" "tagged" "task" "this" "throughout" "time"
2756 "timeprecision" "timeunit" "tran" "tranif0" "tranif1" "tri"
2757 "tri0" "tri1" "triand" "trior" "trireg" "type" "typedef" "union"
2758 "unique" "unsigned" "use" "uwire" "var" "vectored" "virtual" "void"
2759 "wait" "wait_order" "wand" "weak0" "weak1" "while" "wildcard"
2760 "wire" "with" "within" "wor" "xnor" "xor"
2762 "accept_on" "checker" "endchecker" "eventually" "global" "implies"
2763 "let" "nexttime" "reject_on" "restrict" "s_always" "s_eventually"
2764 "s_nexttime" "s_until" "s_until_with" "strong" "sync_accept_on"
2765 "sync_reject_on" "unique0" "until" "until_with" "untyped" "weak"
2767 "List of Verilog keywords.")
2769 (defconst verilog-comment-start-regexp "//\\|/\\*"
2770 "Dual comment value for `comment-start-regexp'.")
2772 (defvar verilog-mode-syntax-table
2773 (let ((table (make-syntax-table)))
2774 ;; Populate the syntax TABLE.
2775 (modify-syntax-entry ?\\ "\\" table)
2776 (modify-syntax-entry ?+ "." table)
2777 (modify-syntax-entry ?- "." table)
2778 (modify-syntax-entry ?= "." table)
2779 (modify-syntax-entry ?% "." table)
2780 (modify-syntax-entry ?< "." table)
2781 (modify-syntax-entry ?> "." table)
2782 (modify-syntax-entry ?& "." table)
2783 (modify-syntax-entry ?| "." table)
2784 (modify-syntax-entry ?` "w" table)
2785 (modify-syntax-entry ?_ "w" table)
2786 (modify-syntax-entry ?\' "." table)
2788 ;; Set up TABLE to handle block and line style comments.
2789 (if (featurep 'xemacs)
2791 ;; XEmacs (formerly Lucid) has the best implementation
2792 (modify-syntax-entry ?/ ". 1456" table)
2793 (modify-syntax-entry ?* ". 23" table)
2794 (modify-syntax-entry ?\n "> b" table))
2795 ;; Emacs does things differently, but we can work with it
2796 (modify-syntax-entry ?/ ". 124b" table)
2797 (modify-syntax-entry ?* ". 23" table)
2798 (modify-syntax-entry ?\n "> b" table))
2800 "Syntax table used in Verilog mode buffers.")
2802 (defvar verilog-font-lock-keywords nil
2803 "Default highlighting for Verilog mode.")
2805 (defvar verilog-font-lock-keywords-1 nil
2806 "Subdued level highlighting for Verilog mode.")
2808 (defvar verilog-font-lock-keywords-2 nil
2809 "Medium level highlighting for Verilog mode.
2810 See also `verilog-font-lock-extra-types'.")
2812 (defvar verilog-font-lock-keywords-3 nil
2813 "Gaudy level highlighting for Verilog mode.
2814 See also `verilog-font-lock-extra-types'.")
2816 (defvar verilog-font-lock-translate-off-face
2817 'verilog-font-lock-translate-off-face
2818 "Font to use for translated off regions.")
2819 (defface verilog-font-lock-translate-off-face
2822 (:background "gray90" :italic t ))
2825 (:background "gray10" :italic t ))
2826 (((class grayscale) (background light))
2827 (:foreground "DimGray" :italic t))
2828 (((class grayscale) (background dark))
2829 (:foreground "LightGray" :italic t))
2831 "Font lock mode face used to background highlight translate-off regions."
2832 :group 'font-lock-highlighting-faces)
2834 (defvar verilog-font-lock-p1800-face
2835 'verilog-font-lock-p1800-face
2836 "Font to use for p1800 keywords.")
2837 (defface verilog-font-lock-p1800-face
2840 (:foreground "DarkOrange3" :bold t ))
2843 (:foreground "orange1" :bold t ))
2845 "Font lock mode face used to highlight P1800 keywords."
2846 :group 'font-lock-highlighting-faces)
2848 (defvar verilog-font-lock-ams-face
2849 'verilog-font-lock-ams-face
2850 "Font to use for Analog/Mixed Signal keywords.")
2851 (defface verilog-font-lock-ams-face
2854 (:foreground "Purple" :bold t ))
2857 (:foreground "orange1" :bold t ))
2859 "Font lock mode face used to highlight AMS keywords."
2860 :group 'font-lock-highlighting-faces)
2862 (defvar verilog-font-grouping-keywords-face
2863 'verilog-font-lock-grouping-keywords-face
2864 "Font to use for Verilog Grouping Keywords (such as begin..end).")
2865 (defface verilog-font-lock-grouping-keywords-face
2868 (:foreground "red4" :bold t ))
2871 (:foreground "red4" :bold t ))
2873 "Font lock mode face used to highlight verilog grouping keywords."
2874 :group 'font-lock-highlighting-faces)
2876 (let* ((verilog-type-font-keywords
2880 "and" "bit" "buf" "bufif0" "bufif1" "cmos" "defparam"
2881 "event" "genvar" "inout" "input" "integer" "localparam"
2882 "logic" "mailbox" "nand" "nmos" "not" "notif0" "notif1" "or"
2883 "output" "parameter" "pmos" "pull0" "pull1" "pulldown" "pullup"
2884 "rcmos" "real" "realtime" "reg" "rnmos" "rpmos" "rtran"
2885 "rtranif0" "rtranif1" "semaphore" "signed" "struct" "supply"
2886 "supply0" "supply1" "time" "tran" "tranif0" "tranif1"
2887 "tri" "tri0" "tri1" "triand" "trior" "trireg" "typedef"
2888 "uwire" "vectored" "wand" "wire" "wor" "xnor" "xor"
2891 (verilog-pragma-keywords
2894 '("surefire" "auto" "synopsys" "rtl_synthesis" "verilint" "leda" "0in"
2897 (verilog-1800-2005-keywords
2900 '("alias" "assert" "assume" "automatic" "before" "bind"
2901 "bins" "binsof" "break" "byte" "cell" "chandle" "class"
2902 "clocking" "config" "const" "constraint" "context" "continue"
2903 "cover" "covergroup" "coverpoint" "cross" "deassign" "design"
2904 "dist" "do" "edge" "endclass" "endclocking" "endconfig"
2905 "endgroup" "endprogram" "endproperty" "endsequence" "enum"
2906 "expect" "export" "extends" "extern" "first_match" "foreach"
2907 "forkjoin" "genvar" "highz0" "highz1" "ifnone" "ignore_bins"
2908 "illegal_bins" "import" "incdir" "include" "inside" "instance"
2909 "int" "intersect" "large" "liblist" "library" "local" "longint"
2910 "matches" "medium" "modport" "new" "noshowcancelled" "null"
2911 "packed" "program" "property" "protected" "pull0" "pull1"
2912 "pulsestyle_onevent" "pulsestyle_ondetect" "pure" "rand" "randc"
2913 "randcase" "randsequence" "ref" "release" "return" "scalared"
2914 "sequence" "shortint" "shortreal" "showcancelled" "small" "solve"
2915 "specparam" "static" "string" "strong0" "strong1" "struct"
2916 "super" "tagged" "this" "throughout" "timeprecision" "timeunit"
2917 "type" "union" "unsigned" "use" "var" "virtual" "void"
2918 "wait_order" "weak0" "weak1" "wildcard" "with" "within"
2921 (verilog-1800-2009-keywords
2924 '("accept_on" "checker" "endchecker" "eventually" "global"
2925 "implies" "let" "nexttime" "reject_on" "restrict" "s_always"
2926 "s_eventually" "s_nexttime" "s_until" "s_until_with" "strong"
2927 "sync_accept_on" "sync_reject_on" "unique0" "until"
2928 "until_with" "untyped" "weak" ) nil )))
2930 (verilog-ams-keywords
2933 '("above" "abs" "absdelay" "acos" "acosh" "ac_stim"
2934 "aliasparam" "analog" "analysis" "asin" "asinh" "atan" "atan2" "atanh"
2935 "branch" "ceil" "connectmodule" "connectrules" "cos" "cosh" "ddt"
2936 "ddx" "discipline" "driver_update" "enddiscipline" "endconnectrules"
2937 "endnature" "endparamset" "exclude" "exp" "final_step" "flicker_noise"
2938 "floor" "flow" "from" "ground" "hypot" "idt" "idtmod" "inf"
2939 "initial_step" "laplace_nd" "laplace_np" "laplace_zd" "laplace_zp"
2940 "last_crossing" "limexp" "ln" "log" "max" "min" "nature"
2941 "net_resolution" "noise_table" "paramset" "potential" "pow" "sin"
2942 "sinh" "slew" "sqrt" "tan" "tanh" "timer" "transition" "white_noise"
2943 "wreal" "zi_nd" "zi_np" "zi_zd" ) nil )))
2945 (verilog-font-keywords
2949 "assign" "case" "casex" "casez" "randcase" "deassign"
2950 "default" "disable" "else" "endcase" "endfunction"
2951 "endgenerate" "endinterface" "endmodule" "endprimitive"
2952 "endspecify" "endtable" "endtask" "final" "for" "force" "return" "break"
2953 "continue" "forever" "fork" "function" "generate" "if" "iff" "initial"
2954 "interface" "join" "join_any" "join_none" "macromodule" "module" "negedge"
2955 "package" "endpackage" "always" "always_comb" "always_ff"
2956 "always_latch" "posedge" "primitive" "priority" "release"
2957 "repeat" "specify" "table" "task" "unique" "wait" "while"
2958 "class" "program" "endclass" "endprogram"
2961 (verilog-font-grouping-keywords
2964 '( "begin" "end" ) nil ))))
2966 (setq verilog-font-lock-keywords
2968 ;; Fontify all builtin keywords
2969 (concat "\\<\\(" verilog-font-keywords "\\|"
2970 ;; And user/system tasks and functions
2971 "\\$[a-zA-Z][a-zA-Z0-9_\\$]*"
2973 ;; Fontify all types
2974 (if verilog-highlight-grouping-keywords
2975 (cons (concat "\\<\\(" verilog-font-grouping-keywords "\\)\\>")
2976 'verilog-font-lock-ams-face)
2977 (cons (concat "\\<\\(" verilog-font-grouping-keywords "\\)\\>")
2978 'font-lock-type-face))
2979 (cons (concat "\\<\\(" verilog-type-font-keywords "\\)\\>")
2980 'font-lock-type-face)
2981 ;; Fontify IEEE-1800-2005 keywords appropriately
2982 (if verilog-highlight-p1800-keywords
2983 (cons (concat "\\<\\(" verilog-1800-2005-keywords "\\)\\>")
2984 'verilog-font-lock-p1800-face)
2985 (cons (concat "\\<\\(" verilog-1800-2005-keywords "\\)\\>")
2986 'font-lock-type-face))
2987 ;; Fontify IEEE-1800-2009 keywords appropriately
2988 (if verilog-highlight-p1800-keywords
2989 (cons (concat "\\<\\(" verilog-1800-2009-keywords "\\)\\>")
2990 'verilog-font-lock-p1800-face)
2991 (cons (concat "\\<\\(" verilog-1800-2009-keywords "\\)\\>")
2992 'font-lock-type-face))
2993 ;; Fontify Verilog-AMS keywords
2994 (cons (concat "\\<\\(" verilog-ams-keywords "\\)\\>")
2995 'verilog-font-lock-ams-face)))
2997 (setq verilog-font-lock-keywords-1
2998 (append verilog-font-lock-keywords
3000 ;; Fontify module definitions
3002 "\\<\\(\\(macro\\)?module\\|primitive\\|class\\|program\\|interface\\|package\\|task\\)\\>\\s-*\\(\\sw+\\)"
3003 '(1 font-lock-keyword-face)
3004 '(3 font-lock-function-name-face 'prepend))
3005 ;; Fontify function definitions
3007 (concat "\\<function\\>\\s-+\\(integer\\|real\\(time\\)?\\|time\\)\\s-+\\(\\sw+\\)" )
3008 '(1 font-lock-keyword-face)
3009 '(3 font-lock-constant-face prepend))
3010 '("\\<function\\>\\s-+\\(\\[[^]]+\\]\\)\\s-+\\(\\sw+\\)"
3011 (1 font-lock-keyword-face)
3012 (2 font-lock-constant-face append))
3013 '("\\<function\\>\\s-+\\(\\sw+\\)"
3014 1 'font-lock-constant-face append))))
3016 (setq verilog-font-lock-keywords-2
3017 (append verilog-font-lock-keywords-1
3020 (concat "\\(//\\s-*\\(" verilog-pragma-keywords "\\)\\s-.*\\)")
3021 ;; Fontify escaped names
3022 '("\\(\\\\\\S-*\\s-\\)" 0 font-lock-function-name-face)
3023 ;; Fontify macro definitions/ uses
3024 '("`\\s-*[A-Za-z][A-Za-z0-9_]*" 0 (if (boundp 'font-lock-preprocessor-face)
3025 'font-lock-preprocessor-face
3026 'font-lock-type-face))
3027 ;; Fontify delays/numbers
3028 '("\\(@\\)\\|\\(#\\s-*\\(\\(\[0-9_.\]+\\('s?[hdxbo][0-9a-fA-F_xz]*\\)?\\)\\|\\(([^()]+)\\|\\sw+\\)\\)\\)"
3029 0 font-lock-type-face append)
3030 ;; Fontify instantiation names
3031 '("\\([A-Za-z][A-Za-z0-9_]*\\)\\s-*(" 1 font-lock-function-name-face)
3034 (setq verilog-font-lock-keywords-3
3035 (append verilog-font-lock-keywords-2
3036 (when verilog-highlight-translate-off
3038 ;; Fontify things in translate off regions
3039 '(verilog-match-translate-off
3040 (0 'verilog-font-lock-translate-off-face prepend))
3044 ;; Buffer state preservation
3046 (defmacro verilog-save-buffer-state (&rest body)
3047 "Execute BODY forms, saving state around insignificant change.
3048 Changes in text properties like `face' or `syntax-table' are
3049 considered insignificant. This macro allows text properties to
3050 be changed, even in a read-only buffer.
3052 A change is considered significant if it affects the buffer text
3053 in any way that isn't completely restored again. Any
3054 user-visible changes to the buffer must not be within a
3055 `verilog-save-buffer-state'."
3056 ;; From c-save-buffer-state
3057 `(let* ((modified (buffer-modified-p))
3058 (buffer-undo-list t)
3059 (inhibit-read-only t)
3060 (inhibit-point-motion-hooks t)
3061 (verilog-no-change-functions t)
3062 before-change-functions
3063 after-change-functions
3065 buffer-file-name ; Prevent primitives checking
3066 buffer-file-truename) ; for file modification
3071 (set-buffer-modified-p nil)))))
3073 (defmacro verilog-save-no-change-functions (&rest body)
3074 "Execute BODY forms, disabling all change hooks in BODY.
3075 For insignificant changes, see instead `verilog-save-buffer-state'."
3076 `(let* ((inhibit-point-motion-hooks t)
3077 (verilog-no-change-functions t)
3078 before-change-functions
3079 after-change-functions)
3082 (defvar verilog-save-font-mod-hooked nil
3083 "Local variable when inside a `verilog-save-font-mods' block.")
3084 (make-variable-buffer-local 'verilog-save-font-mod-hooked)
3086 (defmacro verilog-save-font-mods (&rest body)
3087 "Execute BODY forms, disabling text modifications to allow performing BODY.
3088 Includes temporary disabling of `font-lock' to restore the buffer
3089 to full text form for parsing. Additional actions may be specified with
3090 `verilog-before-save-font-hook' and `verilog-after-save-font-hook'."
3091 ;; Before version 20, match-string with font-lock returns a
3092 ;; vector that is not equal to the string. IE if on "input"
3093 ;; nil==(equal "input" (progn (looking-at "input") (match-string 0)))
3094 `(let* ((hooked (unless verilog-save-font-mod-hooked
3095 (verilog-run-hooks 'verilog-before-save-font-hook)
3097 (verilog-save-font-mod-hooked t)
3098 (fontlocked (when (and (boundp 'font-lock-mode) font-lock-mode)
3104 (when fontlocked (font-lock-mode t))
3105 (when hooked (verilog-run-hooks 'verilog-after-save-font-hook)))))
3108 ;; Comment detection and caching
3110 (defvar verilog-scan-cache-preserving nil
3111 "If set, the specified buffer's comment properties are static.
3112 Buffer changes will be ignored. See `verilog-inside-comment-or-string-p'
3113 and `verilog-scan'.")
3115 (defvar verilog-scan-cache-tick nil
3116 "Modification tick at which `verilog-scan' was last completed.")
3117 (make-variable-buffer-local 'verilog-scan-cache-tick)
3119 (defun verilog-scan-cache-flush ()
3120 "Flush the `verilog-scan' cache."
3121 (setq verilog-scan-cache-tick nil))
3123 (defun verilog-scan-cache-ok-p ()
3124 "Return t iff the scan cache is up to date."
3125 (or (and verilog-scan-cache-preserving
3126 (eq verilog-scan-cache-preserving (current-buffer))
3127 verilog-scan-cache-tick)
3128 (equal verilog-scan-cache-tick (buffer-chars-modified-tick))))
3130 (defmacro verilog-save-scan-cache (&rest body)
3131 "Execute the BODY forms, allowing scan cache preservation within BODY.
3132 This requires that insertions must use `verilog-insert'."
3133 ;; If the buffer is out of date, trash it, as we'll not check later the tick
3134 ;; Note this must work properly if there's multiple layers of calls
3135 ;; to verilog-save-scan-cache even with differing ticks.
3137 (unless (verilog-scan-cache-ok-p) ;; Must be before let
3138 (setq verilog-scan-cache-tick nil))
3139 (let* ((verilog-scan-cache-preserving (current-buffer)))
3142 (defun verilog-scan-region (beg end)
3143 "Parse between BEG and END for `verilog-inside-comment-or-string-p'.
3144 This creates v-cmts properties where comments are in force."
3145 ;; Why properties and not overlays? Overlays have much slower non O(1)
3147 ;; This function is warm - called on every verilog-insert
3150 (verilog-save-buffer-state
3153 (while (< (point) end)
3154 (cond ((looking-at "//")
3156 (or (search-forward "\n" end t)
3158 ;; "1+": The leading // or /* itself isn't considered as
3159 ;; being "inside" the comment, so that a (search-backward)
3160 ;; that lands at the start of the // won't mis-indicate
3161 ;; it's inside a comment. Also otherwise it would be
3162 ;; hard to find a commented out /*AS*/ vs one that isn't
3163 (put-text-property (1+ pt) (point) 'v-cmts t))
3164 ((looking-at "/\\*")
3166 (or (search-forward "*/" end t)
3167 ;; No error - let later code indicate it so we can
3168 ;; use inside functions on-the-fly
3169 ;;(error "%s: Unmatched /* */, at char %d"
3170 ;; (verilog-point-text) (point))
3172 (put-text-property (1+ pt) (point) 'v-cmts t))
3175 (or (re-search-forward "[^\\]\"" end t) ;; don't forward-char first, since we look for a non backslash first
3176 ;; No error - let later code indicate it so we can
3178 (put-text-property (1+ pt) (point) 'v-cmts t))
3181 (if (re-search-forward "[/\"]" end t)
3183 (goto-char end))))))))))
3185 (defun verilog-scan ()
3186 "Parse the buffer, marking all comments with properties.
3187 Also assumes any text inserted since `verilog-scan-cache-tick'
3188 either is ok to parse as a non-comment, or `verilog-insert' was used."
3189 ;; See also `verilog-scan-debug' and `verilog-scan-and-debug'
3190 (unless (verilog-scan-cache-ok-p)
3192 (verilog-save-buffer-state
3194 (message "Scanning %s cache=%s cachetick=%S tick=%S" (current-buffer)
3195 verilog-scan-cache-preserving verilog-scan-cache-tick
3196 (buffer-chars-modified-tick)))
3197 (remove-text-properties (point-min) (point-max) '(v-cmts nil))
3198 (verilog-scan-region (point-min) (point-max))
3199 (setq verilog-scan-cache-tick (buffer-chars-modified-tick))
3200 (when verilog-debug (message "Scanning... done"))))))
3202 (defun verilog-scan-debug ()
3203 "For debugging, show with display face results of `verilog-scan'."
3205 ;;(if dbg (setq dbg (concat dbg (format "verilog-scan-debug\n"))))
3207 (goto-char (point-min))
3208 (remove-text-properties (point-min) (point-max) '(face nil))
3210 (cond ((get-text-property (point) 'v-cmts)
3211 (put-text-property (point) (1+ (point)) `face 'underline)
3212 ;;(if dbg (setq dbg (concat dbg (format " v-cmts at %S\n" (point)))))
3215 (goto-char (or (next-property-change (point)) (point-max))))))))
3217 (defun verilog-scan-and-debug ()
3218 "For debugging, run `verilog-scan' and `verilog-scan-debug'."
3219 (let (verilog-scan-cache-preserving
3220 verilog-scan-cache-tick)
3221 (goto-char (point-min))
3223 (verilog-scan-debug)))
3225 (defun verilog-inside-comment-or-string-p (&optional pos)
3226 "Check if optional point POS is inside a comment.
3227 This may require a slow pre-parse of the buffer with `verilog-scan'
3228 to establish comment properties on all text."
3229 ;; This function is very hot
3232 (and (>= pos (point-min))
3233 (get-text-property pos 'v-cmts))
3234 (get-text-property (point) 'v-cmts)))
3236 (defun verilog-insert (&rest stuff)
3237 "Insert STUFF arguments, tracking for `verilog-inside-comment-or-string-p'.
3238 Any insert that includes a comment must have the entire comment
3239 inserted using a single call to `verilog-insert'."
3242 (insert (car stuff))
3243 (setq stuff (cdr stuff)))
3244 (verilog-scan-region pt (point))))
3248 (defun verilog-declaration-end ()
3249 (search-forward ";"))
3251 (defun verilog-point-text (&optional pointnum)
3252 "Return text describing where POINTNUM or current point is (for errors).
3253 Use filename, if current buffer being edited shorten to just buffer name."
3254 (concat (or (and (equal (window-buffer (selected-window)) (current-buffer))
3258 ":" (int-to-string (1+ (count-lines (point-min) (or pointnum (point)))))))
3260 (defun electric-verilog-backward-sexp ()
3261 "Move backward over one balanced expression."
3263 ;; before that see if we are in a comment
3264 (verilog-backward-sexp))
3266 (defun electric-verilog-forward-sexp ()
3267 "Move forward over one balanced expression."
3269 ;; before that see if we are in a comment
3270 (verilog-forward-sexp))
3272 ;;;used by hs-minor-mode
3273 (defun verilog-forward-sexp-function (arg)
3275 (verilog-backward-sexp)
3276 (verilog-forward-sexp)))
3279 (defun verilog-backward-sexp ()
3284 (if (not (looking-at "\\<"))
3287 ((verilog-skip-backward-comment-or-string))
3288 ((looking-at "\\<else\\>")
3290 verilog-end-block-re
3291 "\\|\\(\\<else\\>\\)"
3292 "\\|\\(\\<if\\>\\)"))
3293 (while (and (not found)
3294 (verilog-re-search-backward reg nil 'move))
3296 ((match-end 1) ; matched verilog-end-block-re
3297 ; try to leap back to matching outward block by striding across
3298 ; indent level changing tokens then immediately
3299 ; previous line governs indentation.
3300 (verilog-leap-to-head))
3301 ((match-end 2) ; else, we're in deep
3302 (setq elsec (1+ elsec)))
3303 ((match-end 3) ; found it
3304 (setq elsec (1- elsec))
3306 ;; Now previous line describes syntax
3307 (setq found 't))))))
3308 ((looking-at verilog-end-block-re)
3309 (verilog-leap-to-head))
3310 ((looking-at "\\(endmodule\\>\\)\\|\\(\\<endprimitive\\>\\)\\|\\(\\<endclass\\>\\)\\|\\(\\<endprogram\\>\\)\\|\\(\\<endinterface\\>\\)\\|\\(\\<endpackage\\>\\)")
3313 (verilog-re-search-backward "\\<\\(macro\\)?module\\>" nil 'move))
3315 (verilog-re-search-backward "\\<primitive\\>" nil 'move))
3317 (verilog-re-search-backward "\\<class\\>" nil 'move))
3319 (verilog-re-search-backward "\\<program\\>" nil 'move))
3321 (verilog-re-search-backward "\\<interface\\>" nil 'move))
3323 (verilog-re-search-backward "\\<package\\>" nil 'move))
3326 (backward-sexp 1))))
3331 (defun verilog-forward-sexp ()
3336 (if (not (looking-at "\\<"))
3339 ((verilog-skip-forward-comment-or-string)
3340 (verilog-forward-syntactic-ws))
3341 ((looking-at verilog-beg-block-re-ordered)
3344 ;; Search forward for matching end
3345 (setq reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)" ))
3347 ;; Search forward for matching endcase
3348 (setq reg "\\(\\<randcase\\>\\|\\(\\<unique\\>\\s-+\\|\\<priority\\>\\s-+\\)?\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" )
3349 (setq md 3) ;; ender is third item in regexp
3352 ;; might be "disable fork" or "wait fork"
3356 (looking-at verilog-disable-fork-re)
3357 (and (looking-at "fork")
3359 (setq here (point)) ;; sometimes a fork is just a fork
3361 (looking-at verilog-disable-fork-re))))
3362 (progn ;; it is a disable fork; ignore it
3363 (goto-char (match-end 0))
3366 (progn ;; it is a nice simple fork
3367 (goto-char here) ;; return from looking for "disable fork"
3368 ;; Search forward for matching join
3369 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" )))))
3371 ;; Search forward for matching endclass
3372 (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
3375 ;; Search forward for matching endtable
3376 (setq reg "\\<endtable\\>" )
3379 ;; Search forward for matching endspecify
3380 (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
3382 ;; Search forward for matching endfunction
3383 (setq reg "\\<endfunction\\>" )
3386 ;; Search forward for matching endfunction
3387 (setq reg "\\<endfunction\\>" )
3390 ;; Search forward for matching endtask
3391 (setq reg "\\<endtask\\>" )
3394 ;; Search forward for matching endtask
3395 (setq reg "\\<endtask\\>" )
3398 ;; Search forward for matching endgenerate
3399 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
3401 ;; Search forward for matching endgroup
3402 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" ))
3404 ;; Search forward for matching endproperty
3405 (setq reg "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)" ))
3407 ;; Search forward for matching endsequence
3408 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)" )
3409 (setq md 3)) ; 3 to get to endsequence in the reg above
3411 ;; Search forward for matching endclocking
3412 (setq reg "\\(\\<clocking\\>\\)\\|\\(\\<endclocking\\>\\)" )))
3419 (while (verilog-re-search-forward reg nil 'move)
3421 ((match-end md) ; a closer in regular expression, so we are climbing out
3422 (setq depth (1- depth))
3423 (if (= 0 depth) ; we are out!
3425 ((match-end 1) ; an opener in the r-e, so we are in deeper now
3426 (setq here (point)) ; remember where we started
3427 (goto-char (match-beginning 1))
3430 (looking-at verilog-disable-fork-re)
3431 (and (looking-at "fork")
3434 (looking-at verilog-disable-fork-re))))
3435 (progn ;; it is a disable fork; another false alarm
3436 (goto-char (match-end 0)))
3437 (progn ;; it is a simple fork (or has nothing to do with fork)
3439 (setq depth (1+ depth))))))))))
3440 (if (verilog-re-search-forward reg nil 'move)
3441 (throw 'skip 1))))))
3443 ((looking-at (concat
3444 "\\(\\<\\(macro\\)?module\\>\\)\\|"
3445 "\\(\\<primitive\\>\\)\\|"
3446 "\\(\\<class\\>\\)\\|"
3447 "\\(\\<program\\>\\)\\|"
3448 "\\(\\<interface\\>\\)\\|"
3449 "\\(\\<package\\>\\)"))
3452 (verilog-re-search-forward "\\<endmodule\\>" nil 'move))
3454 (verilog-re-search-forward "\\<endprimitive\\>" nil 'move))
3456 (verilog-re-search-forward "\\<endclass\\>" nil 'move))
3458 (verilog-re-search-forward "\\<endprogram\\>" nil 'move))
3460 (verilog-re-search-forward "\\<endinterface\\>" nil 'move))
3462 (verilog-re-search-forward "\\<endpackage\\>" nil 'move))
3465 (if (= (following-char) ?\) )
3467 (forward-sexp 1)))))
3470 (if (= (following-char) ?\) )
3472 (forward-sexp 1))))))
3474 (defun verilog-declaration-beg ()
3475 (verilog-re-search-backward verilog-declaration-re (bobp) t))
3481 (defvar verilog-which-tool 1)
3483 (define-derived-mode verilog-mode prog-mode "Verilog"
3484 "Major mode for editing Verilog code.
3485 \\<verilog-mode-map>
3486 See \\[describe-function] verilog-auto (\\[verilog-auto]) for details on how
3487 AUTOs can improve coding efficiency.
3489 Use \\[verilog-faq] for a pointer to frequently asked questions.
3491 NEWLINE, TAB indents for Verilog code.
3492 Delete converts tabs to spaces as it moves back.
3494 Supports highlighting.
3496 Turning on Verilog mode calls the value of the variable `verilog-mode-hook'
3497 with no args, if that value is non-nil.
3499 Variables controlling indentation/edit style:
3501 variable `verilog-indent-level' (default 3)
3502 Indentation of Verilog statements with respect to containing block.
3503 `verilog-indent-level-module' (default 3)
3504 Absolute indentation of Module level Verilog statements.
3505 Set to 0 to get initial and always statements lined up
3506 on the left side of your screen.
3507 `verilog-indent-level-declaration' (default 3)
3508 Indentation of declarations with respect to containing block.
3509 Set to 0 to get them list right under containing block.
3510 `verilog-indent-level-behavioral' (default 3)
3511 Indentation of first begin in a task or function block
3512 Set to 0 to get such code to lined up underneath the task or
3514 `verilog-indent-level-directive' (default 1)
3515 Indentation of `ifdef/`endif blocks.
3516 `verilog-cexp-indent' (default 1)
3517 Indentation of Verilog statements broken across lines i.e.:
3520 `verilog-case-indent' (default 2)
3521 Indentation for case statements.
3522 `verilog-auto-newline' (default nil)
3523 Non-nil means automatically newline after semicolons and the punctuation
3525 `verilog-auto-indent-on-newline' (default t)
3526 Non-nil means automatically indent line after newline.
3527 `verilog-tab-always-indent' (default t)
3528 Non-nil means TAB in Verilog mode should always reindent the current line,
3529 regardless of where in the line point is when the TAB command is used.
3530 `verilog-indent-begin-after-if' (default t)
3531 Non-nil means to indent begin statements following a preceding
3532 if, else, while, for and repeat statements, if any. Otherwise,
3533 the begin is lined up with the preceding token. If t, you get:
3535 begin // amount of indent based on `verilog-cexp-indent'
3539 `verilog-auto-endcomments' (default t)
3540 Non-nil means a comment /* ... */ is set after the ends which ends
3541 cases, tasks, functions and modules.
3542 The type and name of the object will be set between the braces.
3543 `verilog-minimum-comment-distance' (default 10)
3544 Minimum distance (in lines) between begin and end required before a comment
3545 will be inserted. Setting this variable to zero results in every
3546 end acquiring a comment; the default avoids too many redundant
3547 comments in tight quarters.
3548 `verilog-auto-lineup' (default 'declarations)
3549 List of contexts where auto lineup of code should be done.
3551 Variables controlling other actions:
3553 `verilog-linter' (default surelint)
3554 Unix program to call to run the lint checker. This is the default
3555 command for \\[compile-command] and \\[verilog-auto-save-compile].
3557 See \\[customize] for the complete list of variables.
3559 AUTO expansion functions are, in part:
3561 \\[verilog-auto] Expand AUTO statements.
3562 \\[verilog-delete-auto] Remove the AUTOs.
3563 \\[verilog-inject-auto] Insert AUTOs for the first time.
3565 Some other functions are:
3567 \\[verilog-complete-word] Complete word with appropriate possibilities.
3568 \\[verilog-mark-defun] Mark function.
3569 \\[verilog-beg-of-defun] Move to beginning of current function.
3570 \\[verilog-end-of-defun] Move to end of current function.
3571 \\[verilog-label-be] Label matching begin ... end, fork ... join, etc statements.
3573 \\[verilog-comment-region] Put marked area in a comment.
3574 \\[verilog-uncomment-region] Uncomment an area commented with \\[verilog-comment-region].
3575 \\[verilog-insert-block] Insert begin ... end.
3576 \\[verilog-star-comment] Insert /* ... */.
3578 \\[verilog-sk-always] Insert an always @(AS) begin .. end block.
3579 \\[verilog-sk-begin] Insert a begin .. end block.
3580 \\[verilog-sk-case] Insert a case block, prompting for details.
3581 \\[verilog-sk-for] Insert a for (...) begin .. end block, prompting for details.
3582 \\[verilog-sk-generate] Insert a generate .. endgenerate block.
3583 \\[verilog-sk-header] Insert a header block at the top of file.
3584 \\[verilog-sk-initial] Insert an initial begin .. end block.
3585 \\[verilog-sk-fork] Insert a fork begin .. end .. join block.
3586 \\[verilog-sk-module] Insert a module .. (/*AUTOARG*/);.. endmodule block.
3587 \\[verilog-sk-ovm-class] Insert an OVM Class block.
3588 \\[verilog-sk-uvm-class] Insert an UVM Class block.
3589 \\[verilog-sk-primitive] Insert a primitive .. (.. );.. endprimitive block.
3590 \\[verilog-sk-repeat] Insert a repeat (..) begin .. end block.
3591 \\[verilog-sk-specify] Insert a specify .. endspecify block.
3592 \\[verilog-sk-task] Insert a task .. begin .. end endtask block.
3593 \\[verilog-sk-while] Insert a while (...) begin .. end block, prompting for details.
3594 \\[verilog-sk-casex] Insert a casex (...) item: begin.. end endcase block, prompting for details.
3595 \\[verilog-sk-casez] Insert a casez (...) item: begin.. end endcase block, prompting for details.
3596 \\[verilog-sk-if] Insert an if (..) begin .. end block.
3597 \\[verilog-sk-else-if] Insert an else if (..) begin .. end block.
3598 \\[verilog-sk-comment] Insert a comment block.
3599 \\[verilog-sk-assign] Insert an assign .. = ..; statement.
3600 \\[verilog-sk-function] Insert a function .. begin .. end endfunction block.
3601 \\[verilog-sk-input] Insert an input declaration, prompting for details.
3602 \\[verilog-sk-output] Insert an output declaration, prompting for details.
3603 \\[verilog-sk-state-machine] Insert a state machine definition, prompting for details.
3604 \\[verilog-sk-inout] Insert an inout declaration, prompting for details.
3605 \\[verilog-sk-wire] Insert a wire declaration, prompting for details.
3606 \\[verilog-sk-reg] Insert a register declaration, prompting for details.
3607 \\[verilog-sk-define-signal] Define signal under point as a register at the top of the module.
3609 All key bindings can be seen in a Verilog-buffer with \\[describe-bindings].
3610 Key bindings specific to `verilog-mode-map' are:
3612 \\{verilog-mode-map}"
3613 :abbrev-table verilog-mode-abbrev-table
3614 (set (make-local-variable 'beginning-of-defun-function)
3615 'verilog-beg-of-defun)
3616 (set (make-local-variable 'end-of-defun-function)
3617 'verilog-end-of-defun)
3618 (set-syntax-table verilog-mode-syntax-table)
3619 (set (make-local-variable 'indent-line-function)
3620 #'verilog-indent-line-relative)
3621 (setq comment-indent-function 'verilog-comment-indent)
3622 (set (make-local-variable 'parse-sexp-ignore-comments) nil)
3623 (set (make-local-variable 'comment-start) "// ")
3624 (set (make-local-variable 'comment-end) "")
3625 (set (make-local-variable 'comment-start-skip) "/\\*+ *\\|// *")
3626 (set (make-local-variable 'comment-multi-line) nil)
3627 ;; Set up for compilation
3628 (setq verilog-which-tool 1)
3629 (setq verilog-tool 'verilog-linter)
3630 (verilog-set-compile-command)
3631 (when (boundp 'hack-local-variables-hook) ;; Also modify any file-local-variables
3632 (add-hook 'hack-local-variables-hook 'verilog-modify-compile-command t))
3635 (when (featurep 'xemacs)
3636 (easy-menu-add verilog-stmt-menu)
3637 (easy-menu-add verilog-menu)
3638 (setq mode-popup-menu (cons "Verilog Mode" verilog-stmt-menu)))
3640 ;; Stuff for GNU Emacs
3641 (set (make-local-variable 'font-lock-defaults)
3642 `((verilog-font-lock-keywords
3643 verilog-font-lock-keywords-1
3644 verilog-font-lock-keywords-2
3645 verilog-font-lock-keywords-3)
3647 ,(if (functionp 'syntax-ppss)
3648 ;; verilog-beg-of-defun uses syntax-ppss, and syntax-ppss uses
3649 ;; font-lock-beginning-of-syntax-function, so
3650 ;; font-lock-beginning-of-syntax-function, can't use
3651 ;; verilog-beg-of-defun.
3653 'verilog-beg-of-defun)))
3654 ;;------------------------------------------------------------
3655 ;; now hook in 'verilog-highlight-include-files (eldo-mode.el&spice-mode.el)
3656 ;; all buffer local:
3657 (unless noninteractive ;; Else can't see the result, and change hooks are slow
3658 (when (featurep 'xemacs)
3659 (make-local-hook 'font-lock-mode-hook)
3660 (make-local-hook 'font-lock-after-fontify-buffer-hook); doesn't exist in Emacs
3661 (make-local-hook 'after-change-functions))
3662 (add-hook 'font-lock-mode-hook 'verilog-highlight-buffer t t)
3663 (add-hook 'font-lock-after-fontify-buffer-hook 'verilog-highlight-buffer t t) ; not in Emacs
3664 (add-hook 'after-change-functions 'verilog-highlight-region t t))
3666 ;; Tell imenu how to handle Verilog.
3667 (set (make-local-variable 'imenu-generic-expression)
3668 verilog-imenu-generic-expression)
3669 ;; Tell which-func-modes that imenu knows about verilog
3670 (when (and (boundp 'which-func-modes) (listp which-func-modes))
3671 (add-to-list 'which-func-modes 'verilog-mode))
3673 (when (boundp 'hs-special-modes-alist)
3674 (unless (assq 'verilog-mode hs-special-modes-alist)
3675 (setq hs-special-modes-alist
3676 (cons '(verilog-mode-mode "\\<begin\\>" "\\<end\\>" nil
3677 verilog-forward-sexp-function)
3678 hs-special-modes-alist))))
3681 (add-hook 'write-contents-hooks 'verilog-auto-save-check nil 'local)
3682 ;; verilog-mode-hook call added by define-derived-mode
3687 ;; Electric functions
3689 (defun electric-verilog-terminate-line (&optional arg)
3690 "Terminate line and indent next line.
3691 With optional ARG, remove existing end of line comments."
3693 ;; before that see if we are in a comment
3694 (let ((state (save-excursion (verilog-syntax-ppss))))
3696 ((nth 7 state) ; Inside // comment
3699 (delete-horizontal-space)
3704 (beginning-of-line)))
3705 (verilog-indent-line))
3706 ((nth 4 state) ; Inside any comment (hence /**/)
3708 (verilog-more-comment))
3710 ;; First, check if current line should be indented
3712 (delete-horizontal-space)
3714 (skip-chars-forward " \t")
3715 (if (looking-at verilog-auto-end-comment-lines-re)
3716 (let ((indent-str (verilog-indent-line)))
3717 ;; Maybe we should set some endcomments
3718 (if verilog-auto-endcomments
3719 (verilog-set-auto-endcomments indent-str arg))
3721 (delete-horizontal-space)
3728 (delete-horizontal-space)
3730 ;; see if we should line up assignments
3732 (if (or (eq 'all verilog-auto-lineup)
3733 (eq 'assignments verilog-auto-lineup))
3734 (verilog-pretty-expr t "\\(<\\|:\\)?=" ))
3738 (if verilog-auto-indent-on-newline
3739 (verilog-indent-line)))
3743 (defun electric-verilog-terminate-and-indent ()
3744 "Insert a newline and indent for the next statement."
3746 (electric-verilog-terminate-line 1))
3748 (defun electric-verilog-semi ()
3749 "Insert `;' character and reindent the line."
3751 (verilog-insert-last-command-event)
3753 (if (or (verilog-in-comment-or-string-p)
3754 (verilog-in-escaped-name-p))
3758 (verilog-forward-ws&directives)
3759 (verilog-indent-line))
3760 (if (and verilog-auto-newline
3761 (not (verilog-parenthesis-depth)))
3762 (electric-verilog-terminate-line))))
3764 (defun electric-verilog-semi-with-comment ()
3765 "Insert `;' character, reindent the line and indent for comment."
3770 (verilog-indent-line))
3771 (indent-for-comment))
3773 (defun electric-verilog-colon ()
3774 "Insert `:' and do all indentations except line indent on this line."
3776 (verilog-insert-last-command-event)
3777 ;; Do nothing if within string.
3779 (verilog-within-string)
3780 (not (verilog-in-case-region-p)))
3784 (lim (progn (verilog-beg-of-statement) (point))))
3786 (verilog-backward-case-item lim)
3787 (verilog-indent-line)))
3788 ;; (let ((verilog-tab-always-indent nil))
3789 ;; (verilog-indent-line))
3792 ;;(defun electric-verilog-equal ()
3793 ;; "Insert `=', and do indentation if within block."
3795 ;; (verilog-insert-last-command-event)
3796 ;; Could auto line up expressions, but not yet
3797 ;; (if (eq (car (verilog-calculate-indent)) 'block)
3798 ;; (let ((verilog-tab-always-indent nil))
3799 ;; (verilog-indent-command)))
3802 (defun electric-verilog-tick ()
3803 "Insert back-tick, and indent to column 0 if this is a CPP directive."
3805 (verilog-insert-last-command-event)
3807 (if (verilog-in-directive-p)
3808 (verilog-indent-line))))
3810 (defun electric-verilog-tab ()
3811 "Function called when TAB is pressed in Verilog mode."
3813 ;; If verilog-tab-always-indent, indent the beginning of the line.
3815 ;; The region is active, indent it.
3816 ((and (region-active-p)
3817 (not (eq (region-beginning) (region-end))))
3818 (indent-region (region-beginning) (region-end) nil))
3819 ((or verilog-tab-always-indent
3821 (skip-chars-backward " \t")
3823 (let* ((oldpnt (point))
3827 (skip-chars-forward " \t")
3828 (verilog-indent-line)
3829 (back-to-indentation)
3831 (if (< (point) boi-point)
3832 (back-to-indentation)
3833 (cond ((not verilog-tab-to-comment))
3837 (indent-for-comment)
3838 (when (and (eolp) (= oldpnt (point)))
3839 ; kill existing comment
3841 (re-search-forward comment-start-skip oldpnt 'move)
3842 (goto-char (match-beginning 0))
3843 (skip-chars-backward " \t")
3844 (kill-region (point) oldpnt)))))))
3845 (t (progn (insert "\t")))))
3850 ;; Interactive functions
3853 (defun verilog-indent-buffer ()
3854 "Indent-region the entire buffer as Verilog code.
3855 To call this from the command line, see \\[verilog-batch-indent]."
3858 (indent-region (point-min) (point-max) nil))
3860 (defun verilog-insert-block ()
3861 "Insert Verilog begin ... end; block in the code with right indentation."
3863 (verilog-indent-line)
3865 (electric-verilog-terminate-line)
3867 (electric-verilog-terminate-line)
3870 (verilog-indent-line)))
3872 (defun verilog-star-comment ()
3873 "Insert Verilog star comment at point."
3875 (verilog-indent-line)
3883 (defun verilog-insert-1 (fmt max)
3884 "Use format string FMT to insert integers 0 to MAX - 1.
3885 Inserts one integer per line, at the current column. Stops early
3886 if it reaches the end of the buffer."
3887 (let ((col (current-column))
3891 (insert (format fmt n))
3893 ;; Note that this function does not bother to check for lines
3894 ;; shorter than col.
3898 (move-to-column col))))))
3900 (defun verilog-insert-indices (max)
3901 "Insert a set of indices into a rectangle.
3902 The upper left corner is defined by point. Indices begin with 0
3903 and extend to the MAX - 1. If no prefix arg is given, the user
3904 is prompted for a value. The indices are surrounded by square
3905 brackets \[]. For example, the following code with the point
3906 located after the first 'a' gives:
3912 a = b ==> insert-indices ==> a[ 4] = b
3918 (interactive "NMAX: ")
3919 (verilog-insert-1 "[%3d]" max))
3921 (defun verilog-generate-numbers (max)
3922 "Insert a set of generated numbers into a rectangle.
3923 The upper left corner is defined by point. The numbers are padded to three
3924 digits, starting with 000 and extending to (MAX - 1). If no prefix argument
3925 is supplied, then the user is prompted for the MAX number. Consider the
3926 following code fragment:
3932 buf buf ==> generate-numbers ==> buf buf004
3938 (interactive "NMAX: ")
3939 (verilog-insert-1 "%3.3d" max))
3941 (defun verilog-mark-defun ()
3942 "Mark the current Verilog function (or procedure).
3943 This puts the mark at the end, and point at the beginning."
3945 (if (featurep 'xemacs)
3948 (verilog-end-of-defun)
3950 (verilog-beg-of-defun)
3951 (if (fboundp 'zmacs-activate-region)
3952 (zmacs-activate-region)))
3955 (defun verilog-comment-region (start end)
3956 ; checkdoc-params: (start end)
3957 "Put the region into a Verilog comment.
3958 The comments that are in this area are \"deformed\":
3959 `*)' becomes `!(*' and `}' becomes `!{'.
3960 These deformed comments are returned to normal if you use
3961 \\[verilog-uncomment-region] to undo the commenting.
3963 The commented area starts with `verilog-exclude-str-start', and ends with
3964 `verilog-exclude-str-end'. But if you change these variables,
3965 \\[verilog-uncomment-region] won't recognize the comments."
3968 ;; Insert start and endcomments
3970 (if (and (save-excursion (skip-chars-forward " \t") (eolp))
3971 (not (save-excursion (skip-chars-backward " \t") (bolp))))
3973 (beginning-of-line))
3974 (insert verilog-exclude-str-end)
3979 (insert verilog-exclude-str-start)
3981 ;; Replace end-comments within commented area
3984 (while (re-search-backward "\\*/" start t)
3985 (replace-match "*-/" t t)))
3987 (let ((s+1 (1+ start)))
3988 (while (re-search-backward "/\\*" s+1 t)
3989 (replace-match "/-*" t t))))))
3991 (defun verilog-uncomment-region ()
3992 "Uncomment a commented area; change deformed comments back to normal.
3993 This command does nothing if the pointer is not in a commented
3994 area. See also `verilog-comment-region'."
3997 (let ((start (point))
3999 ;; Find the boundaries of the comment
4001 (setq start (progn (search-backward verilog-exclude-str-start nil t)
4003 (setq end (progn (search-forward verilog-exclude-str-end nil t)
4005 ;; Check if we're really inside a comment
4006 (if (or (equal start (point)) (<= end (point)))
4007 (message "Not standing within commented area.")
4009 ;; Remove endcomment
4012 (let ((pos (point)))
4014 (delete-region pos (1+ (point))))
4015 ;; Change comments back to normal
4017 (while (re-search-backward "\\*-/" start t)
4018 (replace-match "*/" t t)))
4020 (while (re-search-backward "/-\\*" start t)
4021 (replace-match "/*" t t)))
4022 ;; Remove start comment
4025 (let ((pos (point)))
4027 (delete-region pos (1+ (point)))))))))
4029 (defun verilog-beg-of-defun ()
4030 "Move backward to the beginning of the current function or procedure."
4032 (verilog-re-search-backward verilog-defun-re nil 'move))
4034 (defun verilog-beg-of-defun-quick ()
4035 "Move backward to the beginning of the current function or procedure.
4036 Uses `verilog-scan' cache."
4038 (verilog-re-search-backward-quick verilog-defun-re nil 'move))
4040 (defun verilog-end-of-defun ()
4041 "Move forward to the end of the current function or procedure."
4043 (verilog-re-search-forward verilog-end-defun-re nil 'move))
4045 (defun verilog-get-beg-of-defun (&optional warn)
4047 (cond ((verilog-re-search-forward-quick verilog-defun-re nil t)
4050 (error "%s: Can't find module beginning" (verilog-point-text))
4052 (defun verilog-get-end-of-defun (&optional warn)
4054 (cond ((verilog-re-search-forward-quick verilog-end-defun-re nil t)
4057 (error "%s: Can't find endmodule" (verilog-point-text))
4060 (defun verilog-label-be (&optional arg)
4061 "Label matching begin ... end, fork ... join and case ... endcase statements.
4062 With ARG, first kill any existing labels."
4067 (verilog-beg-of-defun)
4070 (verilog-end-of-defun)
4072 (goto-char (marker-position b))
4074 (message "Relabeling module..."))
4076 (> (marker-position e) (point))
4077 (verilog-re-search-forward
4079 "\\<end\\(\\(function\\)\\|\\(task\\)\\|\\(module\\)\\|\\(primitive\\)\\|\\(interface\\)\\|\\(package\\)\\|\\(case\\)\\)?\\>"
4080 "\\|\\(`endif\\)\\|\\(`else\\)")
4082 (goto-char (match-beginning 0))
4083 (let ((indent-str (verilog-indent-line)))
4084 (verilog-set-auto-endcomments indent-str 't)
4086 (delete-horizontal-space))
4088 (if (= 9 (% cnt 10))
4089 (message "%d..." cnt)))
4094 (message "%d lines auto commented" cnt))))
4096 (defun verilog-beg-of-statement ()
4097 "Move backward to beginning of statement."
4099 ;; Move back token by token until we see the end
4100 ;; of some earlier line.
4103 ;; If the current point does not begin a new
4104 ;; statement, as in the character ahead of us is a ';', or SOF
4105 ;; or the string after us unambiguously starts a statement,
4106 ;; or the token before us unambiguously ends a statement,
4107 ;; then move back a token and test again.
4109 ;; stop if beginning of buffer
4111 ;; stop if we find a ;
4112 (= (preceding-char) ?\;)
4113 ;; stop if we see a named coverpoint
4114 (looking-at "\\w+\\W*:\\W*\\(coverpoint\\|cross\\|constraint\\)")
4115 ;; keep going if we are in the middle of a word
4116 (not (or (looking-at "\\<") (forward-word -1)))
4117 ;; stop if we see an assertion (perhaps labeled)
4119 (looking-at "\\(\\<\\(assert\\|assume\\|cover\\)\\>\\s-+\\<property\\>\\)\\|\\(\\<assert\\>\\)")
4123 (verilog-backward-token)
4124 (if (looking-at verilog-label-re)
4127 ;; stop if we see an extended complete reg, perhaps a complete one
4129 (looking-at verilog-complete-reg)
4131 (while (and (looking-at verilog-extended-complete-re)
4132 (progn (setq p (point))
4133 (verilog-backward-token)
4136 ;; stop if we see a complete reg (previous found extended ones)
4137 (looking-at verilog-basic-complete-re)
4138 ;; stop if previous token is an ender
4140 (verilog-backward-token)
4142 (looking-at verilog-end-block-re)
4143 (looking-at verilog-preprocessor-re))))) ;; end of test
4144 (verilog-backward-syntactic-ws)
4145 (verilog-backward-token))
4146 ;; Now point is where the previous line ended.
4147 (verilog-forward-syntactic-ws)))
4149 (defun verilog-beg-of-statement-1 ()
4150 "Move backward to beginning of statement."
4152 (if (verilog-in-comment-p)
4153 (verilog-backward-syntactic-ws))
4156 (while (not (looking-at verilog-complete-reg))
4158 (verilog-backward-syntactic-ws)
4160 (= (preceding-char) ?\;)
4162 (verilog-backward-token)
4163 (looking-at verilog-ends-re)))
4167 (verilog-backward-token))))
4168 (verilog-forward-syntactic-ws)))
4171 ; (not (looking-at verilog-complete-reg))
4173 ; (not (= (preceding-char) ?\;)))
4174 ; (verilog-backward-token)
4175 ; (verilog-backward-syntactic-ws)
4176 ; (setq pt (point)))
4178 ; ;(verilog-forward-syntactic-ws)
4180 (defun verilog-end-of-statement ()
4181 "Move forward to end of current statement."
4185 ((verilog-in-directive-p)
4189 ((looking-at verilog-beg-block-re)
4190 (verilog-forward-sexp))
4192 ((equal (char-after) ?\})
4195 ;; Skip to end of statement
4196 ((condition-case nil
4201 (verilog-skip-forward-comment-or-string)
4204 (cond ((looking-at "[ \t]*;")
4205 (skip-chars-forward "^;")
4207 (throw 'found (point)))
4210 (looking-at verilog-beg-block-re))
4211 (goto-char (match-beginning 0))
4213 ((looking-at "[ \t]*)")
4214 (throw 'found (point)))
4216 (throw 'found (point)))
4222 ;; Skip a whole block
4225 (verilog-re-search-forward verilog-end-statement-re nil 'move)
4226 (setq nest (if (match-end 1)
4230 (throw 'found (point)))
4232 (throw 'found (verilog-end-of-statement))))))
4235 (defun verilog-in-case-region-p ()
4236 "Return true if in a case region.
4237 More specifically, point @ in the line foo : @ begin"
4241 (progn (verilog-forward-syntactic-ws)
4242 (looking-at "\\<begin\\>"))
4243 (progn (verilog-backward-syntactic-ws)
4244 (= (preceding-char) ?\:)))
4248 (verilog-re-search-backward
4249 (concat "\\(\\<module\\>\\)\\|\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|"
4250 "\\(\\<endcase\\>\\)\\>")
4254 (setq nest (1+ nest)))
4258 (setq nest (1- nest)))
4260 (throw 'found (= nest 0)))))))
4263 (defun verilog-backward-up-list (arg)
4264 "Call `backward-up-list' ARG, ignoring comments."
4265 (let ((parse-sexp-ignore-comments t))
4266 (backward-up-list arg)))
4268 (defun verilog-forward-sexp-cmt (arg)
4269 "Call `forward-sexp' ARG, inside comments."
4270 (let ((parse-sexp-ignore-comments nil))
4271 (forward-sexp arg)))
4273 (defun verilog-forward-sexp-ign-cmt (arg)
4274 "Call `forward-sexp' ARG, ignoring comments."
4275 (let ((parse-sexp-ignore-comments t))
4276 (forward-sexp arg)))
4278 (defun verilog-in-generate-region-p ()
4279 "Return true if in a generate region.
4280 More specifically, after a generate and before an endgenerate."
4287 (verilog-re-search-backward
4288 "\\<\\(module\\)\\|\\(generate\\)\\|\\(endgenerate\\)\\>" nil 'move)
4290 ((match-end 1) ; module - we have crawled out
4292 ((match-end 2) ; generate
4293 (setq nest (1- nest)))
4294 ((match-end 3) ; endgenerate
4295 (setq nest (1+ nest))))))))
4296 (= nest 0) )) ; return nest
4298 (defun verilog-in-fork-region-p ()
4299 "Return true if between a fork and join."
4301 (let ((lim (save-excursion (verilog-beg-of-defun) (point)))
4306 (verilog-re-search-backward "\\<\\(fork\\)\\|\\(join\\(_any\\|_none\\)?\\)\\>" lim 'move)
4308 ((match-end 1) ; fork
4309 (setq nest (1- nest)))
4310 ((match-end 2) ; join
4311 (setq nest (1+ nest)))))))
4312 (= nest 0) )) ; return nest
4314 (defun verilog-backward-case-item (lim)
4315 "Skip backward to nearest enclosing case item.
4316 Limit search to point LIM."
4322 (verilog-re-search-backward verilog-endcomment-reason-re
4325 ;; Try to find the real :
4326 (if (save-excursion (search-backward ":" lim1 t))
4332 (verilog-re-search-backward "\\(\\[\\)\\|\\(\\]\\)\\|\\(:\\)"
4336 (setq colon (1+ colon))
4338 (error "%s: unbalanced [" (verilog-point-text))))
4340 (setq colon (1- colon)))
4343 (setq colon (1+ colon)))))
4344 ;; Skip back to beginning of case item
4345 (skip-chars-backward "\t ")
4346 (verilog-skip-backward-comment-or-string)
4351 (verilog-re-search-backward
4352 "\\<\\(case[zx]?\\)\\>\\|;\\|\\<end\\>" nil 'move)
4356 (goto-char (match-end 1))
4357 (verilog-forward-ws&directives)
4358 (if (looking-at "(")
4361 (verilog-forward-ws&directives)))
4364 (goto-char (match-end 0))
4365 (verilog-forward-ws&directives)
4367 (error "Malformed case item"))))
4368 (setq str (buffer-substring b e))
4372 "[ \t]*\\(\\(\n\\)\\|\\(//\\)\\|\\(/\\*\\)\\)" str))
4373 (setq str (concat (substring str 0 e) "...")))
4382 (defun verilog-kill-existing-comment ()
4383 "Kill auto comment on this line."
4391 (search-forward "//" e t))))
4393 (delete-region (- b 2) e)))))
4395 (defconst verilog-directive-nest-re
4396 (concat "\\(`else\\>\\)\\|"
4397 "\\(`endif\\>\\)\\|"
4399 "\\(`ifdef\\>\\)\\|"
4400 "\\(`ifndef\\>\\)\\|"
4402 (defun verilog-set-auto-endcomments (indent-str kill-existing-comment)
4403 "Add ending comment with given INDENT-STR.
4404 With KILL-EXISTING-COMMENT, remove what was there before.
4405 Insert `// case: 7 ' or `// NAME ' on this line if appropriate.
4406 Insert `// case expr ' if this line ends a case block.
4407 Insert `// ifdef FOO ' if this line ends code conditional on FOO.
4408 Insert `// NAME ' if this line ends a function, task, module,
4409 primitive or interface named NAME."
4412 (; Comment close preprocessor directives
4414 (looking-at "\\(`endif\\)\\|\\(`else\\)")
4415 (or kill-existing-comment
4416 (not (save-excursion
4418 (search-backward "//" (point-at-bol) t)))))
4421 (else (if (match-end 2) "!" " ")))
4423 (if kill-existing-comment
4424 (verilog-kill-existing-comment))
4425 (delete-horizontal-space)
4428 (while (and (/= nest 0)
4429 (verilog-re-search-backward verilog-directive-nest-re nil 'move))
4431 ((match-end 1) ; `else
4434 ((match-end 2) ; `endif
4435 (setq nest (1+ nest)))
4436 ((match-end 3) ; `if
4437 (setq nest (1- nest)))
4438 ((match-end 4) ; `ifdef
4439 (setq nest (1- nest)))
4440 ((match-end 5) ; `ifndef
4441 (setq nest (1- nest)))
4442 ((match-end 6) ; `elsif
4453 (skip-chars-forward "^ \t")
4454 (verilog-forward-syntactic-ws)
4457 (skip-chars-forward "a-zA-Z0-9_")
4460 (if (> (count-lines (point) b) verilog-minimum-comment-distance)
4461 (insert (concat " // " else m " " (buffer-substring b e))))
4463 (insert " // unmatched `else, `elsif or `endif")
4466 (; Comment close case/class/function/task/module and named block
4467 (and (looking-at "\\<end")
4468 (or kill-existing-comment
4469 (not (save-excursion
4471 (search-backward "//" (point-at-bol) t)))))
4472 (let ((type (car indent-str)))
4473 (unless (eq type 'declaration)
4474 (unless (looking-at (concat "\\(" verilog-end-block-ordered-re "\\)[ \t]*:")) ;; ignore named ends
4475 (if (looking-at verilog-end-block-ordered-re)
4477 (;- This is a case block; search back for the start of this case
4478 (match-end 1) ;; of verilog-end-block-ordered-re
4481 (str "UNMATCHED!!"))
4483 (verilog-leap-to-head)
4485 ((looking-at "\\<randcase\\>")
4486 (setq str "randcase")
4488 ((looking-at "\\(\\(unique\\s-+\\|priority\\s-+\\)?case[xz]?\\)")
4489 (goto-char (match-end 0))
4490 (setq str (concat (match-string 0) " " (verilog-get-expr)))
4494 (if kill-existing-comment
4495 (verilog-kill-existing-comment))
4496 (delete-horizontal-space)
4497 (insert (concat " // " str ))
4498 (if err (ding 't))))
4500 (;- This is a begin..end block
4501 (match-end 2) ;; of verilog-end-block-ordered-re
4502 (let ((str " // UNMATCHED !!")
4508 (verilog-leap-to-head)
4509 (setq there (point))
4510 (if (not (match-end 0))
4514 (if kill-existing-comment
4515 (verilog-kill-existing-comment))
4516 (delete-horizontal-space)
4520 (save-excursion (verilog-beg-of-defun) (point)))
4523 (;-- handle named block differently
4524 (looking-at verilog-named-block-re)
4525 (search-forward ":")
4526 (setq there (point))
4527 (setq str (verilog-get-expr))
4529 (setq str (concat " // block: " str )))
4531 ((verilog-in-case-region-p) ;-- handle case item differently
4533 (setq str (verilog-backward-case-item lim))
4534 (setq there (point))
4536 (setq str (concat " // case: " str )))
4538 (;- try to find "reason" for this begin
4542 ;; (verilog-backward-token)
4543 (verilog-beg-of-statement)
4547 ((looking-at verilog-endcomment-reason-re)
4548 (setq there (match-end 0))
4549 (setq cntx (concat (match-string 0) " "))
4555 (if (and (verilog-continued-line)
4556 (looking-at "\\<repeat\\>\\|\\<wait\\>\\|\\<always\\>"))
4558 (goto-char (match-end 0))
4559 (setq there (point))
4561 (concat " // " (match-string 0) " " (verilog-get-expr))))
4567 ( reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<if\\>\\)\\|\\(assert\\)"))
4569 (while (verilog-re-search-backward reg nil 'move)
4571 ((match-end 1) ; begin
4572 (setq nest (1- nest)))
4573 ((match-end 2) ; end
4574 (setq nest (1+ nest)))
4578 (goto-char (match-end 0))
4579 (setq there (point))
4581 (setq str (verilog-get-expr))
4582 (setq str (concat " // else: !if" str ))
4587 (goto-char (match-end 0))
4588 (setq there (point))
4590 (setq str (verilog-get-expr))
4591 (setq str (concat " // else: !assert " str ))
4592 (throw 'skip 1)))))))))
4597 (reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<if\\>\\)\\|\\(assert\\)"))
4599 (while (verilog-re-search-backward reg nil 'move)
4601 ((match-end 1) ; begin
4602 (setq nest (1- nest)))
4603 ((match-end 2) ; end
4604 (setq nest (1+ nest)))
4608 (goto-char (match-end 0))
4609 (setq there (point))
4611 (setq str (verilog-get-expr))
4612 (setq str (concat " // else: !if" str ))
4617 (goto-char (match-end 0))
4618 (setq there (point))
4620 (setq str (verilog-get-expr))
4621 (setq str (concat " // else: !assert " str ))
4622 (throw 'skip 1)))))))))
4624 (; always_comb, always_ff, always_latch
4625 (or (match-end 4) (match-end 5) (match-end 6))
4626 (goto-char (match-end 0))
4627 (setq there (point))
4629 (setq str (concat " // " cntx )))
4631 (;- task/function/initial et cetera
4634 (goto-char (match-end 0))
4635 (setq there (point))
4637 (setq str (concat " // " cntx (verilog-get-expr))))
4640 (setq str " // auto-endcomment confused "))))
4643 (verilog-in-case-region-p) ;-- handle case item differently
4645 (setq there (point))
4647 (setq str (verilog-backward-case-item lim))))
4649 (setq str (concat " // case: " str )))
4651 ((verilog-in-fork-region-p)
4653 (setq str " // fork branch" ))
4655 ((looking-at "\\<end\\>")
4658 (verilog-forward-syntactic-ws)
4660 (setq str (verilog-get-expr))
4661 (setq str (concat " // " cntx str )))
4666 (if kill-existing-comment
4667 (verilog-kill-existing-comment))
4668 (delete-horizontal-space)
4670 (> (count-lines here there) verilog-minimum-comment-distance))
4674 (;- this is endclass, which can be nested
4675 (match-end 11) ;; of verilog-end-block-ordered-re
4678 (reg "\\<\\(class\\)\\|\\(endclass\\)\\|\\(package\\|primitive\\|\\(macro\\)?module\\)\\>")
4682 (while (verilog-re-search-backward reg nil 'move)
4684 ((match-end 3) ; endclass
4686 (setq string "unmatched endclass")
4689 ((match-end 2) ; endclass
4690 (setq nest (1+ nest)))
4692 ((match-end 1) ; class
4693 (setq nest (1- nest))
4696 (goto-char (match-end 0))
4699 (skip-chars-forward "^ \t")
4700 (verilog-forward-ws&directives)
4703 (skip-chars-forward "a-zA-Z0-9_")
4705 (setq string (buffer-substring b e)))
4709 (insert (concat " // " string ))))
4711 (;- this is end{function,generate,task,module,primitive,table,generate}
4712 ;- which can not be nested.
4714 (let (string reg (name-re nil))
4716 (if kill-existing-comment
4718 (verilog-kill-existing-comment)))
4719 (delete-horizontal-space)
4722 ((match-end 5) ;; of verilog-end-block-ordered-re
4723 (setq reg "\\(\\<function\\>\\)\\|\\(\\<\\(endfunction\\|task\\|\\(macro\\)?module\\|primitive\\)\\>\\)")
4724 (setq name-re "\\w+\\s-*("))
4725 ((match-end 6) ;; of verilog-end-block-ordered-re
4726 (setq reg "\\(\\<task\\>\\)\\|\\(\\<\\(endtask\\|function\\|\\(macro\\)?module\\|primitive\\)\\>\\)")
4727 (setq name-re "\\w+\\s-*("))
4728 ((match-end 7) ;; of verilog-end-block-ordered-re
4729 (setq reg "\\(\\<\\(macro\\)?module\\>\\)\\|\\<endmodule\\>"))
4730 ((match-end 8) ;; of verilog-end-block-ordered-re
4731 (setq reg "\\(\\<primitive\\>\\)\\|\\(\\<\\(endprimitive\\|package\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4732 ((match-end 9) ;; of verilog-end-block-ordered-re
4733 (setq reg "\\(\\<interface\\>\\)\\|\\(\\<\\(endinterface\\|package\\|primitive\\|\\(macro\\)?module\\)\\>\\)"))
4734 ((match-end 10) ;; of verilog-end-block-ordered-re
4735 (setq reg "\\(\\<package\\>\\)\\|\\(\\<\\(endpackage\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4736 ((match-end 11) ;; of verilog-end-block-ordered-re
4737 (setq reg "\\(\\<class\\>\\)\\|\\(\\<\\(endclass\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4738 ((match-end 12) ;; of verilog-end-block-ordered-re
4739 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<\\(endcovergroup\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4740 ((match-end 13) ;; of verilog-end-block-ordered-re
4741 (setq reg "\\(\\<program\\>\\)\\|\\(\\<\\(endprogram\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4742 ((match-end 14) ;; of verilog-end-block-ordered-re
4743 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<\\(endsequence\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
4744 ((match-end 15) ;; of verilog-end-block-ordered-re
4745 (setq reg "\\(\\<clocking\\>\\)\\|\\<endclocking\\>"))
4747 (t (error "Problem in verilog-set-auto-endcomments")))
4750 (verilog-re-search-backward reg nil 'move)
4754 (skip-chars-forward "^ \t")
4755 (verilog-forward-ws&directives)
4756 (if (looking-at "static\\|automatic")
4758 (goto-char (match-end 0))
4759 (verilog-forward-ws&directives)))
4760 (if (and name-re (verilog-re-search-forward name-re nil 'move))
4762 (goto-char (match-beginning 0))
4763 (verilog-forward-ws&directives)))
4766 (skip-chars-forward "a-zA-Z0-9_")
4768 (setq string (buffer-substring b e)))
4771 (setq string "unmatched end(function|task|module|primitive|interface|package|class|clocking)")))))
4773 (insert (concat " // " string )))
4776 (defun verilog-get-expr()
4777 "Grab expression at point, e.g, case ( a | b & (c ^d))."
4779 (verilog-forward-syntactic-ws)
4780 (skip-chars-forward " \t")
4786 (verilog-forward-syntactic-ws)
4787 (if (looking-at "(")
4790 (while (and (/= par 0)
4791 (verilog-re-search-forward "\\((\\)\\|\\()\\)" nil 'move))
4794 (setq par (1+ par)))
4796 (setq par (1- par)))))))
4800 (while (and (/= par 0)
4801 (verilog-re-search-forward "\\((\\)\\|\\()\\)" nil 'move))
4804 (setq par (1+ par)))
4806 (setq par (1- par)))))
4810 (while (and (/= par 0)
4811 (verilog-re-search-forward "\\(\\[\\)\\|\\(\\]\\)" nil 'move))
4814 (setq par (1+ par)))
4816 (setq par (1- par)))))
4817 (verilog-forward-syntactic-ws)
4818 (skip-chars-forward "^ \t\n\f")
4820 ((looking-at "/[/\\*]")
4823 (skip-chars-forward "^: \t\n\f")
4825 (str (buffer-substring b e)))
4826 (if (setq e (string-match "[ \t]*\\(\\(\n\\)\\|\\(//\\)\\|\\(/\\*\\)\\)" str))
4827 (setq str (concat (substring str 0 e) "...")))
4830 (defun verilog-expand-vector ()
4831 "Take a signal vector on the current line and expand it to multiple lines.
4832 Useful for creating tri's and other expanded fields."
4834 (verilog-expand-vector-internal "[" "]"))
4836 (defun verilog-expand-vector-internal (bra ket)
4837 "Given BRA, the start brace and KET, the end brace, expand one line into many lines."
4840 (let ((signal-string (buffer-substring (point)
4842 (end-of-line) (point)))))
4846 "\\([0-9]*\\)\\(:[0-9]*\\|\\)\\(::[0-9---]*\\|\\)"
4848 "\\(.*\\)$") signal-string)
4849 (let* ((sig-head (match-string 1 signal-string))
4850 (vec-start (string-to-number (match-string 2 signal-string)))
4851 (vec-end (if (= (match-beginning 3) (match-end 3))
4854 (substring signal-string (1+ (match-beginning 3))
4857 (if (= (match-beginning 4) (match-end 4))
4860 (substring signal-string (+ 2 (match-beginning 4))
4862 (sig-tail (match-string 5 signal-string))
4867 (let ((tmp vec-start))
4868 (setq vec-start vec-end
4870 vec-range (- vec-range))))
4871 (if (< vec-end vec-start)
4872 (while (<= vec-end vec-start)
4873 (setq vec (append vec (list vec-start)))
4874 (setq vec-start (- vec-start vec-range)))
4875 (while (<= vec-start vec-end)
4876 (setq vec (append vec (list vec-start)))
4877 (setq vec-start (+ vec-start vec-range))))
4879 ;; Delete current line
4880 (delete-region (point) (progn (forward-line 0) (point)))
4884 (insert (concat sig-head bra
4885 (int-to-string (car vec)) ket sig-tail "\n"))
4886 (setq vec (cdr vec)))
4891 (defun verilog-strip-comments ()
4892 "Strip all comments from the Verilog code."
4894 (goto-char (point-min))
4895 (while (re-search-forward "//" nil t)
4896 (if (verilog-within-string)
4897 (re-search-forward "\"" nil t)
4898 (if (verilog-in-star-comment-p)
4899 (re-search-forward "\*/" nil t)
4900 (let ((bpt (- (point) 2)))
4902 (delete-region bpt (point))))))
4904 (goto-char (point-min))
4905 (while (re-search-forward "/\\*" nil t)
4906 (if (verilog-within-string)
4907 (re-search-forward "\"" nil t)
4908 (let ((bpt (- (point) 2)))
4909 (re-search-forward "\\*/")
4910 (delete-region bpt (point))))))
4912 (defun verilog-one-line ()
4913 "Convert structural Verilog instances to occupy one line."
4915 (goto-char (point-min))
4916 (while (re-search-forward "\\([^;]\\)[ \t]*\n[ \t]*" nil t)
4917 (replace-match "\\1 " nil nil)))
4919 (defun verilog-linter-name ()
4920 "Return name of linter, either surelint or verilint."
4921 (let ((compile-word1 (verilog-string-replace-matches "\\s .*$" "" nil nil
4923 (lint-word1 (verilog-string-replace-matches "\\s .*$" "" nil nil
4925 (cond ((equal compile-word1 "surelint") `surelint)
4926 ((equal compile-word1 "verilint") `verilint)
4927 ((equal lint-word1 "surelint") `surelint)
4928 ((equal lint-word1 "verilint") `verilint)
4929 (t `surelint)))) ;; back compatibility
4931 (defun verilog-lint-off ()
4932 "Convert a Verilog linter warning line into a disable statement.
4934 pci_bfm_null.v, line 46: Unused input: pci_rst_
4935 becomes a comment for the appropriate tool.
4937 The first word of the `compile-command' or `verilog-linter'
4938 variables is used to determine which product is being used.
4940 See \\[verilog-surelint-off] and \\[verilog-verilint-off]."
4942 (let ((linter (verilog-linter-name)))
4943 (cond ((equal linter `surelint)
4944 (verilog-surelint-off))
4945 ((equal linter `verilint)
4946 (verilog-verilint-off))
4947 (t (error "Linter name not set")))))
4949 (defvar compilation-last-buffer)
4950 (defvar next-error-last-buffer)
4952 (defun verilog-surelint-off ()
4953 "Convert a SureLint warning line into a disable statement.
4954 Run from Verilog source window; assumes there is a *compile* buffer
4955 with point set appropriately.
4958 WARNING [STD-UDDONX]: xx.v, line 8: output out is never assigned.
4960 // surefire lint_line_off UDDONX"
4962 (let ((buff (if (boundp 'next-error-last-buffer)
4963 next-error-last-buffer
4964 compilation-last-buffer)))
4965 (when (buffer-live-p buff)
4967 (switch-to-buffer buff)
4970 (looking-at "\\(INFO\\|WARNING\\|ERROR\\) \\[[^-]+-\\([^]]+\\)\\]: \\([^,]+\\), line \\([0-9]+\\): \\(.*\\)$")
4971 (let* ((code (match-string 2))
4972 (file (match-string 3))
4973 (line (match-string 4))
4974 (buffer (get-file-buffer file))
4979 (and (file-exists-p file)
4980 (find-file-noselect file)))
4982 (let* ((pop-up-windows t))
4983 (let ((name (expand-file-name
4985 (format "Find this error in: (default %s) "
4988 (if (file-directory-p name)
4989 (setq name (expand-file-name filename name)))
4991 (and (file-exists-p name)
4992 (find-file-noselect name))))))))
4993 (switch-to-buffer buffer)
4994 (goto-char (point-min))
4995 (forward-line (- (string-to-number line)))
4999 ((verilog-in-slash-comment-p)
5000 (re-search-backward "//")
5002 ((looking-at "// surefire lint_off_line ")
5003 (goto-char (match-end 0))
5004 (let ((lim (point-at-eol)))
5005 (if (re-search-forward code lim 'move)
5007 (insert (concat " " code)))))
5010 ((verilog-in-star-comment-p)
5011 (re-search-backward "/\*")
5012 (insert (format " // surefire lint_off_line %6s" code )))
5014 (insert (format " // surefire lint_off_line %6s" code ))
5017 (defun verilog-verilint-off ()
5018 "Convert a Verilint warning line into a disable statement.
5021 (W240) pci_bfm_null.v, line 46: Unused input: pci_rst_
5023 //Verilint 240 off // WARNING: Unused input"
5027 (when (looking-at "\\(.*\\)([WE]\\([0-9A-Z]+\\)).*,\\s +line\\s +[0-9]+:\\s +\\([^:\n]+\\):?.*$")
5028 (replace-match (format
5029 ;; %3s makes numbers 1-999 line up nicely
5030 "\\1//Verilint %3s off // WARNING: \\3"
5033 (verilog-indent-line))))
5035 (defun verilog-auto-save-compile ()
5036 "Update automatics with \\[verilog-auto], save the buffer, and compile."
5038 (verilog-auto) ; Always do it for safety
5040 (compile compile-command))
5042 (defun verilog-preprocess (&optional command filename)
5043 "Preprocess the buffer, similar to `compile', but put output in Verilog-Mode.
5044 Takes optional COMMAND or defaults to `verilog-preprocessor', and
5045 FILENAME to find directory to run in, or defaults to `buffer-file-name`."
5048 (let ((default (verilog-expand-command verilog-preprocessor)))
5049 (set (make-local-variable `verilog-preprocessor)
5050 (read-from-minibuffer "Run Preprocessor (like this): "
5052 'verilog-preprocess-history default)))))
5053 (unless command (setq command (verilog-expand-command verilog-preprocessor)))
5054 (let* ((fontlocked (and (boundp 'font-lock-mode) font-lock-mode))
5055 (dir (file-name-directory (or filename buffer-file-name)))
5056 (cmd (concat "cd " dir "; " command)))
5057 (with-output-to-temp-buffer "*Verilog-Preprocessed*"
5058 (with-current-buffer (get-buffer "*Verilog-Preprocessed*")
5059 (insert (concat "// " cmd "\n"))
5060 (call-process shell-file-name nil t nil shell-command-switch cmd)
5062 ;; Without this force, it takes a few idle seconds
5063 ;; to get the color, which is very jarring
5064 (when fontlocked (font-lock-fontify-buffer))))))
5071 (defun verilog-warn (string &rest args)
5072 "Print a warning with `format' using STRING and optional ARGS."
5073 (apply 'message (concat "%%Warning: " string) args))
5075 (defun verilog-warn-error (string &rest args)
5076 "Call `error' using STRING and optional ARGS.
5077 If `verilog-warn-fatal' is non-nil, call `verilog-warn' instead."
5078 (if verilog-warn-fatal
5079 (apply 'error string args)
5080 (apply 'verilog-warn string args)))
5082 (defmacro verilog-batch-error-wrapper (&rest body)
5083 "Execute BODY and add error prefix to any errors found.
5084 This lets programs calling batch mode to easily extract error messages."
5085 `(let ((verilog-warn-fatal nil))
5089 (error "%%Error: %s%s" (error-message-string err)
5090 (if (featurep 'xemacs) "\n" "")))))) ;; XEmacs forgets to add a newline
5092 (defun verilog-batch-execute-func (funref &optional no-save)
5093 "Internal processing of a batch command.
5094 Runs FUNREF on all command arguments.
5095 Save the result unless optional NO-SAVE is t."
5096 (verilog-batch-error-wrapper
5097 ;; Setting global variables like that is *VERY NASTY* !!! --Stef
5098 ;; However, this function is called only when Emacs is being used as
5099 ;; a standalone language instead of as an editor, so we'll live.
5101 ;; General globals needed
5102 (setq make-backup-files nil)
5103 (setq-default make-backup-files nil)
5104 (setq enable-local-variables t)
5105 (setq enable-local-eval t)
5106 ;; Make sure any sub-files we read get proper mode
5107 (setq-default major-mode 'verilog-mode)
5108 ;; Ditto files already read in
5110 (when (buffer-file-name buf)
5111 (with-current-buffer buf
5114 ;; Process the files
5115 (mapcar (lambda (buf)
5116 (when (buffer-file-name buf)
5118 (if (not (file-exists-p (buffer-file-name buf)))
5120 (concat "File not found: " (buffer-file-name buf))))
5121 (message (concat "Processing " (buffer-file-name buf)))
5124 (unless no-save (save-buffer)))))
5127 (defun verilog-batch-auto ()
5128 "For use with --batch, perform automatic expansions as a stand-alone tool.
5129 This sets up the appropriate Verilog mode environment, updates automatics
5130 with \\[verilog-auto] on all command-line files, and saves the buffers.
5131 For proper results, multiple filenames need to be passed on the command
5132 line in bottom-up order."
5133 (unless noninteractive
5134 (error "Use verilog-batch-auto only with --batch")) ;; Otherwise we'd mess up buffer modes
5135 (verilog-batch-execute-func `verilog-auto))
5137 (defun verilog-batch-delete-auto ()
5138 "For use with --batch, perform automatic deletion as a stand-alone tool.
5139 This sets up the appropriate Verilog mode environment, deletes automatics
5140 with \\[verilog-delete-auto] on all command-line files, and saves the buffers."
5141 (unless noninteractive
5142 (error "Use verilog-batch-delete-auto only with --batch")) ;; Otherwise we'd mess up buffer modes
5143 (verilog-batch-execute-func `verilog-delete-auto))
5145 (defun verilog-batch-delete-trailing-whitespace ()
5146 "For use with --batch, perform whitespace deletion as a stand-alone tool.
5147 This sets up the appropriate Verilog mode environment, removes
5148 whitespace with \\[verilog-delete-trailing-whitespace] on all
5149 command-line files, and saves the buffers."
5150 (unless noninteractive
5151 (error "Use verilog-batch-delete-trailing-whitespace only with --batch")) ;; Otherwise we'd mess up buffer modes
5152 (verilog-batch-execute-func `verilog-delete-trailing-whitespace))
5154 (defun verilog-batch-diff-auto ()
5155 "For use with --batch, perform automatic differences as a stand-alone tool.
5156 This sets up the appropriate Verilog mode environment, expand automatics
5157 with \\[verilog-diff-auto] on all command-line files, and reports an error
5158 if any differences are observed. This is appropriate for adding to regressions
5159 to insure automatics are always properly maintained."
5160 (unless noninteractive
5161 (error "Use verilog-batch-diff-auto only with --batch")) ;; Otherwise we'd mess up buffer modes
5162 (verilog-batch-execute-func `verilog-diff-auto t))
5164 (defun verilog-batch-inject-auto ()
5165 "For use with --batch, perform automatic injection as a stand-alone tool.
5166 This sets up the appropriate Verilog mode environment, injects new automatics
5167 with \\[verilog-inject-auto] on all command-line files, and saves the buffers.
5168 For proper results, multiple filenames need to be passed on the command
5169 line in bottom-up order."
5170 (unless noninteractive
5171 (error "Use verilog-batch-inject-auto only with --batch")) ;; Otherwise we'd mess up buffer modes
5172 (verilog-batch-execute-func `verilog-inject-auto))
5174 (defun verilog-batch-indent ()
5175 "For use with --batch, reindent an entire file as a stand-alone tool.
5176 This sets up the appropriate Verilog mode environment, calls
5177 \\[verilog-indent-buffer] on all command-line files, and saves the buffers."
5178 (unless noninteractive
5179 (error "Use verilog-batch-indent only with --batch")) ;; Otherwise we'd mess up buffer modes
5180 (verilog-batch-execute-func `verilog-indent-buffer))
5186 (defconst verilog-indent-alist
5187 '((block . (+ ind verilog-indent-level))
5188 (case . (+ ind verilog-case-indent))
5189 (cparenexp . (+ ind verilog-indent-level))
5190 (cexp . (+ ind verilog-cexp-indent))
5191 (defun . verilog-indent-level-module)
5192 (declaration . verilog-indent-level-declaration)
5193 (directive . (verilog-calculate-indent-directive))
5194 (tf . verilog-indent-level)
5195 (behavioral . (+ verilog-indent-level-behavioral verilog-indent-level-module))
5198 (comment . (verilog-comment-indent))
5202 (defun verilog-continued-line-1 (lim)
5203 "Return true if this is a continued line.
5204 Set point to where line starts. Limit search to point LIM."
5205 (let ((continued 't))
5206 (if (eq 0 (forward-line -1))
5209 (verilog-backward-ws&directives lim)
5211 (setq continued nil)
5212 (setq continued (verilog-backward-token))))
5213 (setq continued nil))
5216 (defun verilog-calculate-indent ()
5217 "Calculate the indent of the current Verilog line.
5218 Examine previous lines. Once a line is found that is definitive as to the
5219 type of the current line, return that lines' indent level and its type.
5220 Return a list of two elements: (INDENT-TYPE INDENT-LEVEL)."
5222 (let* ((starting_position (point))
5224 (begin (looking-at "[ \t]*begin\\>"))
5225 (lim (save-excursion (verilog-re-search-backward "\\(\\<begin\\>\\)\\|\\(\\<module\\>\\)" nil t)))
5226 (type (catch 'nesting
5227 ;; Keep working backwards until we can figure out
5228 ;; what type of statement this is.
5229 ;; Basically we need to figure out
5230 ;; 1) if this is a continuation of the previous line;
5231 ;; 2) are we in a block scope (begin..end)
5233 ;; if we are in a comment, done.
5234 (if (verilog-in-star-comment-p)
5235 (throw 'nesting 'comment))
5237 ;; if we have a directive, done.
5238 (if (save-excursion (beginning-of-line)
5239 (and (looking-at verilog-directive-re-1)
5240 (not (or (looking-at "[ \t]*`[ou]vm_")
5241 (looking-at "[ \t]*`vmm_")))))
5242 (throw 'nesting 'directive))
5243 ;; indent structs as if there were module level
5244 (if (verilog-in-struct-p)
5245 (throw 'nesting 'block))
5247 ;; if we are in a parenthesized list, and the user likes to indent these, return.
5248 ;; unless we are in the newfangled coverpoint or constraint blocks
5250 verilog-indent-lists
5252 (not (verilog-in-coverage-p))
5255 (throw 'nesting 'block)))
5257 ;; See if we are continuing a previous line
5259 ;; trap out if we crawl off the top of the buffer
5260 (if (bobp) (throw 'nesting 'cpp))
5262 (if (verilog-continued-line-1 lim)
5265 (not (looking-at verilog-complete-reg))
5266 (verilog-continued-line-1 lim))
5267 (progn (goto-char sp)
5268 (throw 'nesting 'cexp))
5273 (not verilog-indent-begin-after-if)
5274 (looking-at verilog-no-indent-begin-re))
5277 (skip-chars-forward " \t")
5278 (throw 'nesting 'statement))
5280 (throw 'nesting 'cexp))))
5281 ;; not a continued line
5282 (goto-char starting_position))
5284 (if (looking-at "\\<else\\>")
5285 ;; search back for governing if, striding across begin..end pairs
5288 (while (verilog-re-search-backward verilog-ends-re nil 'move)
5290 ((match-end 1) ; else, we're in deep
5291 (setq elsec (1+ elsec)))
5293 (setq elsec (1- elsec))
5295 (if verilog-align-ifelse
5296 (throw 'nesting 'statement)
5297 (progn ;; back up to first word on this line
5299 (verilog-forward-syntactic-ws)
5300 (throw 'nesting 'statement)))))
5301 ((match-end 3) ; assert block
5302 (setq elsec (1- elsec))
5303 (verilog-beg-of-statement) ;; doesn't get to beginning
5304 (if (looking-at verilog-property-re)
5305 (throw 'nesting 'statement) ; We don't need an endproperty for these
5306 (throw 'nesting 'block) ;We still need an endproperty
5309 ; try to leap back to matching outward block by striding across
5310 ; indent level changing tokens then immediately
5311 ; previous line governs indentation.
5312 (let (( reg) (nest 1))
5313 ;; verilog-ends => else|if|end|join(_any|_none|)|endcase|endclass|endtable|endspecify|endfunction|endtask|endgenerate|endgroup
5315 ((match-end 4) ; end
5316 ;; Search back for matching begin
5317 (setq reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)" ))
5318 ((match-end 5) ; endcase
5319 ;; Search back for matching case
5320 (setq reg "\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" ))
5321 ((match-end 6) ; endfunction
5322 ;; Search back for matching function
5323 (setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" ))
5324 ((match-end 7) ; endtask
5325 ;; Search back for matching task
5326 (setq reg "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)" ))
5327 ((match-end 8) ; endspecify
5328 ;; Search back for matching specify
5329 (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
5330 ((match-end 9) ; endtable
5331 ;; Search back for matching table
5332 (setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" ))
5333 ((match-end 10) ; endgenerate
5334 ;; Search back for matching generate
5335 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
5336 ((match-end 11) ; joins
5337 ;; Search back for matching fork
5338 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|none\\)?\\>\\)" ))
5339 ((match-end 12) ; class
5340 ;; Search back for matching class
5341 (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
5342 ((match-end 13) ; covergroup
5343 ;; Search back for matching covergroup
5344 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" )))
5346 (while (verilog-re-search-backward reg nil 'move)
5348 ((match-end 1) ; begin
5349 (setq nest (1- nest))
5352 ((match-end 2) ; end
5353 (setq nest (1+ nest)))))
5355 (throw 'nesting (verilog-calc-1)))
5359 ;; Return type of block and indent level.
5362 (if (> par 0) ; Unclosed Parenthesis
5363 (list 'cparenexp par)
5366 (list type (verilog-case-indent-level)))
5367 ((eq type 'statement)
5368 (list type (current-column)))
5372 (list type (verilog-current-indent-level))))))))
5374 (defun verilog-wai ()
5375 "Show matching nesting block for debugging."
5378 (let* ((type (verilog-calc-1))
5380 ;; Return type of block and indent level.
5384 verilog-indent-lists
5385 (not(or (verilog-in-coverage-p)
5386 (verilog-in-struct-p)))
5391 (setq depth (verilog-case-indent-level)))
5392 ((eq type 'statement)
5393 (setq depth (current-column)))
5397 (setq depth (verilog-current-indent-level)))))
5398 (message "You are at nesting %s depth %d" type depth))))
5399 (defun verilog-calc-1 ()
5401 (let ((re (concat "\\({\\|}\\|" verilog-indent-re "\\)")))
5402 (while (verilog-re-search-backward re nil 'move)
5405 ((equal (char-after) ?\{)
5406 (if (verilog-at-constraint-p)
5407 (throw 'nesting 'block)))
5409 ((equal (char-after) ?\})
5410 (let ((there (verilog-at-close-constraint-p)))
5411 (if there ;; we are at the } that closes a constraint. Find the { that opens it
5415 (verilog-beg-of-statement)))))
5417 ((looking-at verilog-beg-block-re-ordered)
5419 ((match-end 2) ; *sigh* could be "unique case" or "priority casex"
5420 (let ((here (point)))
5421 (verilog-beg-of-statement)
5422 (if (looking-at verilog-extended-case-re)
5423 (throw 'nesting 'case)
5425 (throw 'nesting 'case))
5427 ((match-end 4) ; *sigh* could be "disable fork"
5428 (let ((here (point)))
5429 (verilog-beg-of-statement)
5430 (if (looking-at verilog-disable-fork-re)
5431 t ; this is a normal statement
5432 (progn ; or is fork, starts a new block
5434 (throw 'nesting 'block)))))
5436 ((match-end 27) ; *sigh* might be a clocking declaration
5437 (let ((here (point)))
5438 (if (verilog-in-paren)
5439 t ; this is a normal statement
5440 (progn ; or is fork, starts a new block
5442 (throw 'nesting 'block)))))
5444 ;; need to consider typedef struct here...
5445 ((looking-at "\\<class\\|struct\\|function\\|task\\>")
5446 ; *sigh* These words have an optional prefix:
5447 ; extern {virtual|protected}? function a();
5448 ; typedef class foo;
5449 ; and we don't want to confuse this with
5454 (verilog-beg-of-statement)
5455 (if (looking-at verilog-beg-block-re-ordered)
5456 (throw 'nesting 'block)
5457 (throw 'nesting 'defun)))
5460 ((looking-at "\\<property\\>")
5462 ; {assert|assume|cover} property (); are complete
5463 ; and could also be labeled: - foo: assert property
5465 ; property ID () ... needs end_property
5466 (verilog-beg-of-statement)
5467 (if (looking-at verilog-property-re)
5468 (throw 'continue 'statement) ; We don't need an endproperty for these
5469 (throw 'nesting 'block) ;We still need an endproperty
5472 (t (throw 'nesting 'block))))
5474 ((looking-at verilog-end-block-re)
5475 (verilog-leap-to-head)
5476 (if (verilog-in-case-region-p)
5478 (verilog-leap-to-case-head)
5479 (if (looking-at verilog-extended-case-re)
5480 (throw 'nesting 'case)))))
5482 ((looking-at verilog-defun-level-re)
5483 (if (looking-at verilog-defun-level-generate-only-re)
5484 (if (verilog-in-generate-region-p)
5485 (throw 'continue 'foo) ; always block in a generate - keep looking
5486 (throw 'nesting 'defun))
5487 (throw 'nesting 'defun)))
5489 ((looking-at verilog-cpp-level-re)
5490 (throw 'nesting 'cpp))
5493 (throw 'nesting 'cpp)))))
5495 (throw 'nesting 'cpp))))
5497 (defun verilog-calculate-indent-directive ()
5498 "Return indentation level for directive.
5499 For speed, the searcher looks at the last directive, not the indent
5500 of the appropriate enclosing block."
5501 (let ((base -1) ;; Indent of the line that determines our indentation
5502 (ind 0)) ;; Relative offset caused by other directives (like `endif on same line as `else)
5503 ;; Start at current location, scan back for another directive
5507 (while (and (< base 0)
5508 (verilog-re-search-backward verilog-directive-re nil t))
5509 (cond ((save-excursion (skip-chars-backward " \t") (bolp))
5510 (setq base (current-indentation))))
5511 (cond ((and (looking-at verilog-directive-end) (< base 0)) ;; Only matters when not at BOL
5512 (setq ind (- ind verilog-indent-level-directive)))
5513 ((and (looking-at verilog-directive-middle) (>= base 0)) ;; Only matters when at BOL
5514 (setq ind (+ ind verilog-indent-level-directive)))
5515 ((looking-at verilog-directive-begin)
5516 (setq ind (+ ind verilog-indent-level-directive)))))
5517 ;; Adjust indent to starting indent of critical line
5518 (setq ind (max 0 (+ ind base))))
5522 (skip-chars-forward " \t")
5523 (cond ((or (looking-at verilog-directive-middle)
5524 (looking-at verilog-directive-end))
5525 (setq ind (max 0 (- ind verilog-indent-level-directive))))))
5528 (defun verilog-leap-to-case-head ()
5531 (verilog-re-search-backward
5533 "\\(\\<randcase\\>\\|\\(\\<unique\\s-+\\|priority\\s-+\\)?\\<case[xz]?\\>\\)"
5534 "\\|\\(\\<endcase\\>\\)" )
5538 (let ((here (point)))
5539 (verilog-beg-of-statement)
5540 (unless (looking-at verilog-extended-case-re)
5542 (setq nest (1- nest)))
5544 (setq nest (1+ nest)))
5549 (defun verilog-leap-to-head ()
5550 "Move point to the head of this block.
5551 Jump from end to matching begin, from endcase to matching case, and so on."
5557 ((looking-at "\\<end\\>")
5558 ;; 1: Search back for matching begin
5559 (setq reg (concat "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|"
5560 "\\(\\<endcase\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" )))
5561 ((looking-at "\\<endtask\\>")
5562 ;; 2: Search back for matching task
5563 (setq reg "\\(\\<task\\>\\)\\|\\(\\(\\(\\<virtual\\>\\s-+\\)\\|\\(\\<protected\\>\\s-+\\)\\)+\\<task\\>\\)")
5565 ((looking-at "\\<endcase\\>")
5567 (verilog-leap-to-case-head) )
5568 (setq reg nil) ; to force skip
5571 ((looking-at "\\<join\\(_any\\|_none\\)?\\>")
5572 ;; 4: Search back for matching fork
5573 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" ))
5574 ((looking-at "\\<endclass\\>")
5575 ;; 5: Search back for matching class
5576 (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
5577 ((looking-at "\\<endtable\\>")
5578 ;; 6: Search back for matching table
5579 (setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" ))
5580 ((looking-at "\\<endspecify\\>")
5581 ;; 7: Search back for matching specify
5582 (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
5583 ((looking-at "\\<endfunction\\>")
5584 ;; 8: Search back for matching function
5585 (setq reg "\\(\\<function\\>\\)\\|\\(\\(\\(\\<virtual\\>\\s-+\\)\\|\\(\\<protected\\>\\s-+\\)\\)+\\<function\\>\\)")
5587 ;;(setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" ))
5588 ((looking-at "\\<endgenerate\\>")
5589 ;; 8: Search back for matching generate
5590 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
5591 ((looking-at "\\<endgroup\\>")
5592 ;; 10: Search back for matching covergroup
5593 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" ))
5594 ((looking-at "\\<endproperty\\>")
5595 ;; 11: Search back for matching property
5596 (setq reg "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)" ))
5597 ((looking-at verilog-uvm-end-re)
5598 ;; 12: Search back for matching sequence
5599 (setq reg (concat "\\(" verilog-uvm-begin-re "\\|" verilog-uvm-end-re "\\)")))
5600 ((looking-at verilog-ovm-end-re)
5601 ;; 12: Search back for matching sequence
5602 (setq reg (concat "\\(" verilog-ovm-begin-re "\\|" verilog-ovm-end-re "\\)")))
5603 ((looking-at verilog-vmm-end-re)
5604 ;; 12: Search back for matching sequence
5605 (setq reg (concat "\\(" verilog-vmm-begin-re "\\|" verilog-vmm-end-re "\\)")))
5606 ((looking-at "\\<endinterface\\>")
5607 ;; 12: Search back for matching interface
5608 (setq reg "\\(\\<interface\\>\\)\\|\\(\\<endinterface\\>\\)" ))
5609 ((looking-at "\\<endsequence\\>")
5610 ;; 12: Search back for matching sequence
5611 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)" ))
5612 ((looking-at "\\<endclocking\\>")
5613 ;; 12: Search back for matching clocking
5614 (setq reg "\\(\\<clocking\\)\\|\\(\\<endclocking\\>\\)" )))
5617 (if (eq nesting 'yes)
5619 (while (verilog-re-search-backward reg nil 'move)
5621 ((match-end 1) ; begin
5622 (if (looking-at "fork")
5623 (let ((here (point)))
5624 (verilog-beg-of-statement)
5625 (unless (looking-at verilog-disable-fork-re)
5627 (setq nest (1- nest))))
5628 (setq nest (1- nest)))
5630 ;; Now previous line describes syntax
5635 ((match-end 2) ; end
5636 (setq nest (1+ nest)))
5638 ;; endcase, jump to case
5640 (setq nest (1+ nest))
5642 (setq reg "\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" ))
5644 ;; join, jump to fork
5646 (setq nest (1+ nest))
5648 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" ))
5652 (verilog-re-search-backward reg nil 'move)
5653 (match-end 1)) ; task -> could be virtual and/or protected
5655 (verilog-beg-of-statement)
5657 (throw 'skip 1)))))))
5659 (defun verilog-continued-line ()
5660 "Return true if this is a continued line.
5661 Set point to where line starts."
5662 (let ((continued 't))
5663 (if (eq 0 (forward-line -1))
5666 (verilog-backward-ws&directives)
5668 (setq continued nil)
5669 (while (and continued
5671 (skip-chars-backward " \t")
5673 (setq continued (verilog-backward-token)))))
5674 (setq continued nil))
5677 (defun verilog-backward-token ()
5678 "Step backward token, returning true if this is a continued line."
5680 (verilog-backward-syntactic-ws)
5684 (;-- Anything ending in a ; is complete
5685 (= (preceding-char) ?\;)
5687 (; If a "}" is prefixed by a ";", then this is a complete statement
5688 ; i.e.: constraint foo { a = b; }
5689 (= (preceding-char) ?\})
5692 (not(verilog-at-close-constraint-p))))
5693 (;-- constraint foo { a = b }
5694 ; is a complete statement. *sigh*
5695 (= (preceding-char) ?\{)
5698 (not (verilog-at-constraint-p))))
5700 (= (preceding-char) ?\")
5702 (verilog-skip-backward-comment-or-string)
5706 (= (preceding-char) ?\])
5708 (verilog-backward-open-bracket)
5711 (;-- Could be 'case (foo)' or 'always @(bar)' which is complete
5712 ; also could be simply '@(foo)'
5714 ; (b, ... which ISN'T complete
5715 ;;;; Do we need this???
5716 (= (preceding-char) ?\))
5719 (verilog-backward-up-list 1)
5720 (verilog-backward-syntactic-ws)
5721 (let ((back (point)))
5725 ((looking-at "\\<\\(always\\(_latch\\|_ff\\|_comb\\)?\\|case\\(\\|[xz]\\)\\|for\\(\\|each\\|ever\\)\\|i\\(f\\|nitial\\)\\|repeat\\|while\\)\\>")
5726 (not (looking-at "\\<randcase\\>\\|\\<case[xz]?\\>[^:]")))
5727 ((looking-at verilog-uvm-statement-re)
5729 ((looking-at verilog-uvm-begin-re)
5731 ((looking-at verilog-uvm-end-re)
5733 ((looking-at verilog-ovm-statement-re)
5735 ((looking-at verilog-ovm-begin-re)
5737 ((looking-at verilog-ovm-end-re)
5739 ;; JBA find VMM macros
5740 ((looking-at verilog-vmm-statement-re)
5742 ((looking-at verilog-vmm-begin-re)
5744 ((looking-at verilog-vmm-end-re)
5746 ;; JBA trying to catch macro lines with no ; at end
5747 ((looking-at "\\<`")
5752 ((= (preceding-char) ?\@)
5755 (verilog-backward-token)
5756 (not (looking-at "\\<\\(always\\(_latch\\|_ff\\|_comb\\)?\\|initial\\|while\\)\\>"))))
5757 ((= (preceding-char) ?\#)
5761 (;-- any of begin|initial|while are complete statements; 'begin : foo' is also complete
5764 (while (= (preceding-char) ?\_)
5767 ((looking-at "\\<else\\>")
5769 ((looking-at verilog-behavioral-block-beg-re)
5771 ((looking-at verilog-indent-re)
5776 (verilog-backward-syntactic-ws)
5778 ((= (preceding-char) ?\:)
5780 (verilog-backward-syntactic-ws)
5782 (if (looking-at verilog-nameable-item-re )
5785 ((= (preceding-char) ?\#)
5788 ((= (preceding-char) ?\`)
5796 (defun verilog-backward-syntactic-ws ()
5797 "Move backwards putting point after first non-whitespace non-comment."
5798 (verilog-skip-backward-comments)
5799 (forward-comment (- (buffer-size))))
5801 (defun verilog-backward-syntactic-ws-quick ()
5802 "As with `verilog-backward-syntactic-ws' but use `verilog-scan' cache."
5803 (while (cond ((bobp)
5805 ((> (skip-syntax-backward " ") 0)
5807 ((eq (preceding-char) ?\n) ;; \n's terminate // so aren't space syntax
5810 ((or (verilog-inside-comment-or-string-p (1- (point)))
5811 (verilog-inside-comment-or-string-p (point)))
5812 (re-search-backward "[/\"]" nil t) ;; Only way a comment or quote can begin
5815 (defun verilog-forward-syntactic-ws ()
5816 (verilog-skip-forward-comment-p)
5817 (forward-comment (buffer-size)))
5819 (defun verilog-backward-ws&directives (&optional bound)
5820 "Backward skip over syntactic whitespace and compiler directives for Emacs 19.
5821 Optional BOUND limits search."
5823 (let* ((bound (or bound (point-min)))
5826 (if (< bound (point))
5828 (let ((state (save-excursion (verilog-syntax-ppss))))
5830 ((nth 7 state) ;; in // comment
5831 (verilog-re-search-backward "//" nil 'move)
5832 (skip-chars-backward "/"))
5833 ((nth 4 state) ;; in /* */ comment
5834 (verilog-re-search-backward "/\*" nil 'move))))
5835 (narrow-to-region bound (point))
5836 (while (/= here (point))
5838 (verilog-skip-backward-comments)
5843 ((and verilog-highlight-translate-off
5844 (verilog-within-translate-off))
5845 (verilog-back-to-start-translate-off (point-min)))
5846 ((looking-at verilog-directive-re-1)
5850 (if p (goto-char p))))))))
5852 (defun verilog-forward-ws&directives (&optional bound)
5853 "Forward skip over syntactic whitespace and compiler directives for Emacs 19.
5854 Optional BOUND limits search."
5856 (let* ((bound (or bound (point-max)))
5859 (if (> bound (point))
5861 (let ((state (save-excursion (verilog-syntax-ppss))))
5863 ((nth 7 state) ;; in // comment
5866 (skip-chars-forward " \t\n\f")
5868 ((nth 4 state) ;; in /* */ comment
5869 (verilog-re-search-forward "\*\/\\s-*" nil 'move))))
5870 (narrow-to-region (point) bound)
5871 (while (/= here (point))
5874 (forward-comment (buffer-size))
5875 (and (looking-at "\\s-*(\\*.*\\*)\\s-*") ;; Attribute
5876 (goto-char (match-end 0)))
5879 (if (looking-at verilog-directive-re-1)
5882 (beginning-of-line 2))))))))
5884 (defun verilog-in-comment-p ()
5885 "Return true if in a star or // comment."
5886 (let ((state (save-excursion (verilog-syntax-ppss))))
5887 (or (nth 4 state) (nth 7 state))))
5889 (defun verilog-in-star-comment-p ()
5890 "Return true if in a star comment."
5891 (let ((state (save-excursion (verilog-syntax-ppss))))
5893 (nth 4 state) ; t if in a comment of style a // or b /**/
5895 (nth 7 state) ; t if in a comment of style b /**/
5898 (defun verilog-in-slash-comment-p ()
5899 "Return true if in a slash comment."
5900 (let ((state (save-excursion (verilog-syntax-ppss))))
5903 (defun verilog-in-comment-or-string-p ()
5904 "Return true if in a string or comment."
5905 (let ((state (save-excursion (verilog-syntax-ppss))))
5906 (or (nth 3 state) (nth 4 state) (nth 7 state)))) ; Inside string or comment)
5908 (defun verilog-in-attribute-p ()
5909 "Return true if point is in an attribute (* [] attribute *)."
5912 (verilog-re-search-backward "\\((\\*\\)\\|\\(\\*)\\)" nil 'move)
5913 (numberp (match-beginning 1)))))
5915 (defun verilog-in-parameter-p ()
5916 "Return true if point is in a parameter assignment #( p1=1, p2=5)."
5919 (verilog-re-search-backward "\\(#(\\)\\|\\()\\)" nil 'move)
5920 (numberp (match-beginning 1)))))
5922 (defun verilog-in-escaped-name-p ()
5923 "Return true if in an escaped name."
5926 (skip-chars-backward "^ \t\n\f")
5927 (if (equal (char-after (point) ) ?\\ )
5930 (defun verilog-in-directive-p ()
5931 "Return true if in a directive."
5934 (looking-at verilog-directive-re-1)))
5936 (defun verilog-in-parenthesis-p ()
5937 "Return true if in a ( ) expression (but not { } or [ ])."
5940 (verilog-re-search-backward "\\((\\)\\|\\()\\)" nil 'move)
5941 (numberp (match-beginning 1)))))
5943 (defun verilog-in-paren ()
5944 "Return true if in a parenthetical expression.
5945 May cache result using `verilog-syntax-ppss'."
5946 (let ((state (save-excursion (verilog-syntax-ppss))))
5947 (> (nth 0 state) 0 )))
5949 (defun verilog-in-paren-quick ()
5950 "Return true if in a parenthetical expression.
5951 Always starts from `point-min', to allow inserts with hooks disabled."
5952 ;; The -quick refers to its use alongside the other -quick functions,
5953 ;; not that it's likely to be faster than verilog-in-paren.
5954 (let ((state (save-excursion (parse-partial-sexp (point-min) (point)))))
5955 (> (nth 0 state) 0 )))
5957 (defun verilog-in-struct-p ()
5958 "Return true if in a struct declaration."
5961 (if (verilog-in-paren)
5963 (verilog-backward-up-list 1)
5964 (verilog-at-struct-p)
5968 (defun verilog-in-coverage-p ()
5969 "Return true if in a constraint or coverpoint expression."
5972 (if (verilog-in-paren)
5974 (verilog-backward-up-list 1)
5975 (verilog-at-constraint-p)
5978 (defun verilog-at-close-constraint-p ()
5979 "If at the } that closes a constraint or covergroup, return true."
5981 (equal (char-after) ?\})
5985 (verilog-backward-ws&directives)
5986 (if (equal (char-before) ?\;)
5990 (defun verilog-at-constraint-p ()
5991 "If at the { of a constraint or coverpoint definition, return true, moving point to constraint."
5994 (equal (char-after) ?\{)
5996 (progn (backward-char 1)
5997 (verilog-backward-ws&directives)
5998 (equal (char-before) ?\;))))
6000 (verilog-re-search-backward "\\<constraint\\|coverpoint\\|cross\\>" nil 'move)
6004 (defun verilog-at-struct-p ()
6005 "If at the { of a struct, return true, moving point to struct."
6007 (if (and (equal (char-after) ?\{)
6008 (verilog-backward-token))
6009 (looking-at "\\<struct\\|union\\|packed\\|\\(un\\)?signed\\>")
6012 (defun verilog-parenthesis-depth ()
6013 "Return non zero if in parenthetical-expression."
6014 (save-excursion (nth 1 (verilog-syntax-ppss))))
6017 (defun verilog-skip-forward-comment-or-string ()
6018 "Return true if in a string or comment."
6019 (let ((state (save-excursion (verilog-syntax-ppss))))
6021 ((nth 3 state) ;Inside string
6022 (search-forward "\"")
6024 ((nth 7 state) ;Inside // comment
6027 ((nth 4 state) ;Inside any comment (hence /**/)
6028 (search-forward "*/"))
6032 (defun verilog-skip-backward-comment-or-string ()
6033 "Return true if in a string or comment."
6034 (let ((state (save-excursion (verilog-syntax-ppss))))
6036 ((nth 3 state) ;Inside string
6037 (search-backward "\"")
6039 ((nth 7 state) ;Inside // comment
6040 (search-backward "//")
6041 (skip-chars-backward "/")
6043 ((nth 4 state) ;Inside /* */ comment
6044 (search-backward "/*")
6049 (defun verilog-skip-backward-comments ()
6050 "Return true if a comment was skipped."
6054 (let ((state (save-excursion (verilog-syntax-ppss))))
6056 ((nth 7 state) ;Inside // comment
6057 (search-backward "//")
6058 (skip-chars-backward "/")
6059 (skip-chars-backward " \t\n\f")
6061 ((nth 4 state) ;Inside /* */ comment
6062 (search-backward "/*")
6063 (skip-chars-backward " \t\n\f")
6066 (= (char-before) ?\/)
6067 (= (char-before (1- (point))) ?\*))
6068 (goto-char (- (point) 2))
6069 t) ;; Let nth 4 state handle the rest
6071 (= (char-before) ?\))
6072 (= (char-before (1- (point))) ?\*))
6073 (goto-char (- (point) 2))
6074 (if (search-backward "(*" nil t)
6076 (skip-chars-backward " \t\n\f")
6079 (goto-char (+ (point) 2))
6082 (/= (skip-chars-backward " \t\n\f") 0))))))))
6084 (defun verilog-skip-forward-comment-p ()
6085 "If in comment, move to end and return true."
6087 (state (save-excursion (verilog-syntax-ppss)))
6089 ((nth 3 state) ;Inside string
6091 ((nth 7 state) ;Inside // comment
6095 ((nth 4 state) ;Inside /* comment
6096 (search-forward "*/")
6098 ((verilog-in-attribute-p) ;Inside (* attribute
6099 (search-forward "*)" nil t)
6102 (skip-chars-forward " \t\n\f")
6105 ((looking-at "\\/\\*")
6108 (goto-char (match-end 0))
6109 (if (search-forward "*/" nil t)
6111 (skip-chars-forward " \t\n\f")
6116 ((looking-at "(\\*")
6119 (goto-char (match-end 0))
6120 (if (search-forward "*)" nil t)
6122 (skip-chars-forward " \t\n\f")
6130 (defun verilog-indent-line-relative ()
6131 "Cheap version of indent line.
6132 Only look at a few lines to determine indent level."
6136 (if (looking-at "^[ \t]*$")
6137 (cond ;- A blank line; No need to be too smart.
6139 (setq indent-str (list 'cpp 0)))
6140 ((verilog-continued-line)
6141 (let ((sp1 (point)))
6142 (if (verilog-continued-line)
6146 (list 'statement (verilog-current-indent-level))))
6148 (setq indent-str (list 'block (verilog-current-indent-level)))))
6151 (setq indent-str (verilog-calculate-indent))))
6152 (progn (skip-chars-forward " \t")
6153 (setq indent-str (verilog-calculate-indent))))
6154 (verilog-do-indent indent-str)))
6156 (defun verilog-indent-line ()
6157 "Indent for special part of code."
6158 (verilog-do-indent (verilog-calculate-indent)))
6160 (defun verilog-do-indent (indent-str)
6161 (let ((type (car indent-str))
6162 (ind (car (cdr indent-str))))
6164 (; handle continued exp
6166 (let ((here (point)))
6167 (verilog-backward-syntactic-ws)
6170 (= (preceding-char) ?\,)
6171 (= (preceding-char) ?\])
6173 (verilog-beg-of-statement-1)
6174 (looking-at verilog-declaration-re)))
6179 (verilog-beg-of-statement-1)
6181 (if (looking-at verilog-declaration-re)
6182 (progn ;; we have multiple words
6183 (goto-char (match-end 0))
6184 (skip-chars-forward " \t")
6186 ((and verilog-indent-declaration-macros
6187 (= (following-char) ?\`))
6191 (skip-chars-forward " \t")))
6192 ((= (following-char) ?\[)
6195 (verilog-backward-up-list -1)
6196 (skip-chars-forward " \t"))))
6200 (+ (current-column) verilog-cexp-indent))))))
6202 (indent-line-to val)
6203 (if (and (not verilog-indent-lists)
6205 (verilog-pretty-declarations-auto))
6207 ((= (preceding-char) ?\) )
6209 (let ((val (eval (cdr (assoc type verilog-indent-alist)))))
6210 (indent-line-to val)))
6214 (verilog-beg-of-statement-1)
6215 (if (and (< (point) here)
6216 (verilog-re-search-forward "=[ \\t]*" here 'move))
6217 (setq val (current-column))
6218 (setq val (eval (cdr (assoc type verilog-indent-alist)))))
6220 (indent-line-to val))))))
6222 (; handle inside parenthetical expressions
6223 (eq type 'cparenexp)
6225 (val (save-excursion
6226 (verilog-backward-up-list 1)
6228 (if verilog-indent-lists
6229 (skip-chars-forward " \t")
6230 (verilog-forward-syntactic-ws))
6234 (decl (save-excursion
6236 (verilog-forward-syntactic-ws)
6238 (looking-at verilog-declaration-re))))
6239 (indent-line-to val)
6241 (verilog-pretty-declarations-auto))))
6243 (;-- Handle the ends
6245 (looking-at verilog-end-block-re )
6246 (verilog-at-close-constraint-p))
6247 (let ((val (if (eq type 'statement)
6248 (- ind verilog-indent-level)
6250 (indent-line-to val)))
6252 (;-- Case -- maybe line 'em up
6253 (and (eq type 'case) (not (looking-at "^[ \t]*$")))
6256 ((looking-at "\\<endcase\\>")
6257 (indent-line-to ind))
6259 (let ((val (eval (cdr (assoc type verilog-indent-alist)))))
6260 (indent-line-to val))))))
6263 (and (eq type 'defun)
6264 (looking-at verilog-zero-indent-re))
6271 (looking-at verilog-declaration-re))
6272 (verilog-indent-declaration ind))
6274 (;-- Everything else
6276 (let ((val (eval (cdr (assoc type verilog-indent-alist)))))
6277 (indent-line-to val))))
6279 (if (looking-at "[ \t]+$")
6280 (skip-chars-forward " \t"))
6281 indent-str ; Return indent data
6284 (defun verilog-current-indent-level ()
6285 "Return the indent-level of the current statement."
6289 (setq par-pos (verilog-parenthesis-depth))
6293 (setq par-pos (verilog-parenthesis-depth)))
6294 (skip-chars-forward " \t")
6297 (defun verilog-case-indent-level ()
6298 "Return the indent-level of the current statement.
6299 Do not count named blocks or case-statements."
6301 (skip-chars-forward " \t")
6303 ((looking-at verilog-named-block-re)
6305 ((and (not (looking-at verilog-extended-case-re))
6306 (looking-at "^[^:;]+[ \t]*:"))
6307 (verilog-re-search-forward ":" nil t)
6308 (skip-chars-forward " \t")
6311 (current-column)))))
6313 (defun verilog-indent-comment ()
6314 "Indent current line as comment."
6317 ((verilog-in-star-comment-p)
6319 (re-search-backward "/\\*" nil t)
6320 (1+(current-column))))
6325 (re-search-backward "//" nil t)
6326 (current-column))))))
6327 (indent-line-to stcol)
6330 (defun verilog-more-comment ()
6331 "Make more comment lines like the previous."
6335 ((verilog-in-star-comment-p)
6338 (re-search-backward "/\\*" nil t)
6339 (1+(current-column))))
6344 (re-search-backward "//" nil t)
6345 (current-column))))))
6351 (skip-chars-forward " \t")
6355 (defun verilog-comment-indent (&optional arg)
6356 "Return the column number the line should be indented to.
6357 ARG is ignored, for `comment-indent-function' compatibility."
6359 ((verilog-in-star-comment-p)
6361 (re-search-backward "/\\*" nil t)
6362 (1+(current-column))))
6367 (re-search-backward "//" nil t)
6368 (current-column)))))
6372 (defun verilog-pretty-declarations-auto (&optional quiet)
6373 "Call `verilog-pretty-declarations' QUIET based on `verilog-auto-lineup'."
6374 (when (or (eq 'all verilog-auto-lineup)
6375 (eq 'declarations verilog-auto-lineup))
6376 (verilog-pretty-declarations quiet)))
6378 (defun verilog-pretty-declarations (&optional quiet)
6379 "Line up declarations around point.
6380 Be verbose about progress unless optional QUIET set."
6382 (let* ((m1 (make-marker))
6396 ; (verilog-beg-of-statement-1)
6398 (verilog-forward-syntactic-ws)
6399 (and (not (verilog-in-directive-p)) ;; could have `define input foo
6400 (looking-at verilog-declaration-re)))
6402 (if (verilog-parenthesis-depth)
6403 ;; in an argument list or parameter block
6404 (setq el (verilog-backward-up-list -1)
6407 (verilog-backward-up-list 1)
6408 (forward-line) ;; ignore ( input foo,
6409 (verilog-re-search-forward verilog-declaration-re el 'move)
6410 (goto-char (match-beginning 0))
6411 (skip-chars-backward " \t")
6413 startpos (set-marker (make-marker) start)
6416 (verilog-backward-up-list -1)
6418 (verilog-backward-syntactic-ws)
6420 endpos (set-marker (make-marker) end)
6424 (skip-chars-forward " \t")
6427 ;; in a declaration block (not in argument list)
6430 (verilog-beg-of-statement-1)
6431 (while (and (looking-at verilog-declaration-re)
6433 (skip-chars-backward " \t")
6436 (verilog-backward-syntactic-ws)
6438 (verilog-beg-of-statement-1))
6440 startpos (set-marker (make-marker) start)
6443 (verilog-end-of-statement)
6444 (setq e (point)) ;Might be on last line
6445 (verilog-forward-syntactic-ws)
6446 (while (looking-at verilog-declaration-re)
6447 (verilog-end-of-statement)
6449 (verilog-forward-syntactic-ws))
6451 endpos (set-marker (make-marker) end)
6454 (verilog-do-indent (verilog-calculate-indent))
6455 (verilog-forward-ws&directives)
6457 ;; OK, start and end are set
6458 (goto-char (marker-position startpos))
6459 (if (and (not quiet)
6460 (> (- end start) 100))
6461 (message "Lining up declarations..(please stand by)"))
6462 ;; Get the beginning of line indent first
6463 (while (progn (setq e (marker-position endpos))
6466 ((save-excursion (skip-chars-backward " \t")
6468 (verilog-forward-ws&directives)
6469 (indent-line-to base-ind)
6470 (verilog-forward-ws&directives)
6472 (verilog-re-search-forward "[ \t\n\f]" e 'move)))
6475 (verilog-re-search-forward "[ \t\n\f]" e 'move)))
6478 ;; Now find biggest prefix
6479 (setq ind (verilog-get-lineup-indent (marker-position startpos) endpos))
6480 ;; Now indent each line.
6481 (goto-char (marker-position startpos))
6482 (while (progn (setq e (marker-position endpos))
6483 (setq r (- e (point)))
6486 (unless quiet (message "%d" r))
6487 ;;(verilog-do-indent (verilog-calculate-indent)))
6488 (verilog-forward-ws&directives)
6490 ((or (and verilog-indent-declaration-macros
6491 (looking-at verilog-declaration-re-2-macro))
6492 (looking-at verilog-declaration-re-2-no-macro))
6493 (let ((p (match-end 0)))
6495 (if (verilog-re-search-forward "[[#`]" p 'move)
6499 (goto-char (marker-position m1))
6505 ((verilog-continued-line-1 (marker-position startpos))
6507 (indent-line-to ind))
6508 ((verilog-in-struct-p)
6509 ;; could have a declaration of a user defined item
6511 (verilog-end-of-statement))
6512 (t ; Must be comment or white space
6514 (verilog-forward-ws&directives)
6517 (unless quiet (message "")))))))
6519 (defun verilog-pretty-expr (&optional quiet myre)
6520 "Line up expressions around point, optionally QUIET with regexp MYRE ignored."
6522 (if (not (verilog-in-comment-or-string-p))
6524 (let ( (rexp (concat "^\\s-*" verilog-complete-reg))
6525 (rexp1 (concat "^\\s-*" verilog-basic-complete-re)))
6527 (if (and (not (looking-at rexp ))
6528 (looking-at verilog-assignment-operation-re)
6530 (goto-char (match-end 2))
6531 (and (not (verilog-in-attribute-p))
6532 (not (verilog-in-parameter-p))
6533 (not (verilog-in-comment-or-string-p)))))
6534 (let* ((here (point))
6540 (verilog-backward-syntactic-ws)
6542 (while (and (not (looking-at rexp1))
6543 (looking-at verilog-assignment-operation-re)
6547 (verilog-backward-syntactic-ws)
6549 ) ;Ack, need to grok `define
6555 (setq e (point)) ;Might be on last line
6556 (verilog-forward-syntactic-ws)
6559 (not (looking-at rexp1 ))
6560 (looking-at verilog-assignment-operation-re)
6563 (not (eq e (point)))))
6565 (verilog-forward-syntactic-ws)
6569 (endpos (set-marker (make-marker) end))
6573 (verilog-do-indent (verilog-calculate-indent))
6574 (if (and (not quiet)
6575 (> (- end start) 100))
6576 (message "Lining up expressions..(please stand by)"))
6578 ;; Set indent to minimum throughout region
6579 (while (< (point) (marker-position endpos))
6581 (verilog-just-one-space verilog-assignment-operation-re)
6583 (verilog-do-indent (verilog-calculate-indent))
6585 (verilog-forward-syntactic-ws)
6588 ;; Now find biggest prefix
6589 (setq ind (verilog-get-lineup-indent-2 verilog-assignment-operation-re start endpos))
6591 ;; Now indent each line.
6593 (while (progn (setq e (marker-position endpos))
6594 (setq r (- e (point)))
6597 (if (not quiet) (message "%d" r))
6599 ((looking-at verilog-assignment-operation-re)
6600 (goto-char (match-beginning 2))
6601 (if (not (or (verilog-in-parenthesis-p) ;; leave attributes and comparisons alone
6602 (verilog-in-coverage-p)))
6603 (if (eq (char-after) ?=)
6604 (indent-to (1+ ind)) ; line up the = of the <= with surrounding =
6608 ((verilog-continued-line-1 start)
6610 (indent-line-to ind))
6611 (t ; Must be comment or white space
6613 (verilog-forward-ws&directives)
6617 (unless quiet (message ""))
6620 (defun verilog-just-one-space (myre)
6621 "Remove extra spaces around regular expression MYRE."
6623 (if (and (not(looking-at verilog-complete-reg))
6625 (let ((p1 (match-end 1))
6631 (just-one-space)))))
6633 (defun verilog-indent-declaration (baseind)
6634 "Indent current lines as declaration.
6635 Line up the variable names based on previous declaration's indentation.
6636 BASEIND is the base indent to offset everything."
6638 (let ((pos (point-marker))
6639 (lim (save-excursion
6640 ;; (verilog-re-search-backward verilog-declaration-opener nil 'move)
6641 (verilog-re-search-backward "\\(\\<begin\\>\\)\\|\\(\\<module\\>\\)\\|\\(\\<task\\>\\)" nil 'move)
6647 (+ baseind (eval (cdr (assoc 'declaration verilog-indent-alist)))))
6648 (indent-line-to val)
6650 ;; Use previous declaration (in this module) as template.
6651 (if (or (eq 'all verilog-auto-lineup)
6652 (eq 'declarations verilog-auto-lineup))
6653 (if (verilog-re-search-backward
6654 (or (and verilog-indent-declaration-macros
6655 verilog-declaration-re-1-macro)
6656 verilog-declaration-re-1-no-macro) lim t)
6658 (goto-char (match-end 0))
6659 (skip-chars-forward " \t")
6660 (setq ind (current-column))
6664 (eval (cdr (assoc 'declaration verilog-indent-alist)))))
6665 (indent-line-to val)
6666 (if (and verilog-indent-declaration-macros
6667 (looking-at verilog-declaration-re-2-macro))
6668 (let ((p (match-end 0)))
6670 (if (verilog-re-search-forward "[[#`]" p 'move)
6674 (goto-char (marker-position m1))
6677 (if (/= (current-column) ind)
6681 (if (looking-at verilog-declaration-re-2-no-macro)
6682 (let ((p (match-end 0)))
6684 (if (verilog-re-search-forward "[[`#]" p 'move)
6688 (goto-char (marker-position m1))
6691 (if (/= (current-column) ind)
6694 (indent-to ind))))))))))
6697 (defun verilog-get-lineup-indent (b edpos)
6698 "Return the indent level that will line up several lines within the region.
6699 Region is defined by B and EDPOS."
6703 ;; Get rightmost position
6704 (while (progn (setq e (marker-position edpos))
6706 (if (verilog-re-search-forward
6707 (or (and verilog-indent-declaration-macros
6708 verilog-declaration-re-1-macro)
6709 verilog-declaration-re-1-no-macro) e 'move)
6711 (goto-char (match-end 0))
6712 (verilog-backward-syntactic-ws)
6713 (if (> (current-column) ind)
6714 (setq ind (current-column)))
6715 (goto-char (match-end 0)))))
6718 ;; No lineup-string found
6721 (verilog-backward-syntactic-ws)
6722 ;;(skip-chars-backward " \t")
6723 (1+ (current-column))))))
6725 (defun verilog-get-lineup-indent-2 (myre b edpos)
6726 "Return the indent level that will line up several lines within the region."
6730 ;; Get rightmost position
6731 (while (progn (setq e (marker-position edpos))
6733 (if (and (verilog-re-search-forward myre e 'move)
6734 (not (verilog-in-attribute-p))) ;; skip attribute exprs
6736 (goto-char (match-beginning 2))
6737 (verilog-backward-syntactic-ws)
6738 (if (> (current-column) ind)
6739 (setq ind (current-column)))
6740 (goto-char (match-end 0)))
6744 ;; No lineup-string found
6747 (skip-chars-backward " \t")
6748 (1+ (current-column))))))
6750 (defun verilog-comment-depth (type val)
6751 "A useful mode debugging aide. TYPE and VAL are comments for insertion."
6759 (if (re-search-backward " /\\* \[#-\]# \[a-zA-Z\]+ \[0-9\]+ ## \\*/" b t)
6761 (replace-match " /* -# ## */")
6765 (insert " /* ## ## */"))))
6768 (format "%s %d" type val))))
6774 (defvar verilog-str nil)
6775 (defvar verilog-all nil)
6776 (defvar verilog-pred nil)
6777 (defvar verilog-buffer-to-use nil)
6778 (defvar verilog-flag nil)
6779 (defvar verilog-toggle-completions nil
6780 "True means \\<verilog-mode-map>\\[verilog-complete-word] should try all possible completions one by one.
6781 Repeated use of \\[verilog-complete-word] will show you all of them.
6782 Normally, when there is more than one possible completion,
6783 it displays a list of all possible completions.")
6786 (defvar verilog-type-keywords
6788 "and" "buf" "bufif0" "bufif1" "cmos" "defparam" "inout" "input"
6789 "integer" "localparam" "logic" "mailbox" "nand" "nmos" "nor" "not" "notif0"
6790 "notif1" "or" "output" "parameter" "pmos" "pull0" "pull1" "pulldown" "pullup"
6791 "rcmos" "real" "realtime" "reg" "rnmos" "rpmos" "rtran" "rtranif0"
6792 "rtranif1" "semaphore" "time" "tran" "tranif0" "tranif1" "tri" "tri0" "tri1"
6793 "triand" "trior" "trireg" "wand" "wire" "wor" "xnor" "xor"
6795 "Keywords for types used when completing a word in a declaration or parmlist.
6796 \(integer, real, reg...)")
6798 (defvar verilog-cpp-keywords
6799 '("module" "macromodule" "primitive" "timescale" "define" "ifdef" "ifndef" "else"
6801 "Keywords to complete when at first word of a line in declarative scope.
6802 \(initial, always, begin, assign...)
6803 The procedures and variables defined within the Verilog program
6804 will be completed at runtime and should not be added to this list.")
6806 (defvar verilog-defun-keywords
6809 "always" "always_comb" "always_ff" "always_latch" "assign"
6810 "begin" "end" "generate" "endgenerate" "module" "endmodule"
6811 "specify" "endspecify" "function" "endfunction" "initial" "final"
6812 "task" "endtask" "primitive" "endprimitive"
6814 verilog-type-keywords)
6815 "Keywords to complete when at first word of a line in declarative scope.
6816 \(initial, always, begin, assign...)
6817 The procedures and variables defined within the Verilog program
6818 will be completed at runtime and should not be added to this list.")
6820 (defvar verilog-block-keywords
6822 "begin" "break" "case" "continue" "else" "end" "endfunction"
6823 "endgenerate" "endinterface" "endpackage" "endspecify" "endtask"
6824 "for" "fork" "if" "join" "join_any" "join_none" "repeat" "return"
6826 "Keywords to complete when at first word of a line in behavioral scope.
6827 \(begin, if, then, else, for, fork...)
6828 The procedures and variables defined within the Verilog program
6829 will be completed at runtime and should not be added to this list.")
6831 (defvar verilog-tf-keywords
6832 '("begin" "break" "fork" "join" "join_any" "join_none" "case" "end" "endtask" "endfunction" "if" "else" "for" "while" "repeat")
6833 "Keywords to complete when at first word of a line in a task or function.
6834 \(begin, if, then, else, for, fork.)
6835 The procedures and variables defined within the Verilog program
6836 will be completed at runtime and should not be added to this list.")
6838 (defvar verilog-case-keywords
6839 '("begin" "fork" "join" "join_any" "join_none" "case" "end" "endcase" "if" "else" "for" "repeat")
6840 "Keywords to complete when at first word of a line in case scope.
6841 \(begin, if, then, else, for, fork...)
6842 The procedures and variables defined within the Verilog program
6843 will be completed at runtime and should not be added to this list.")
6845 (defvar verilog-separator-keywords
6846 '("else" "then" "begin")
6847 "Keywords to complete when NOT standing at the first word of a statement.
6848 \(else, then, begin...)
6849 Variables and function names defined within the Verilog program
6850 will be completed at runtime and should not be added to this list.")
6852 (defvar verilog-gate-ios
6853 ;; All these have an implied {"input"...} at the end
6867 ("pulldown" "output")
6872 ("rtran" "inout" "inout")
6873 ("rtranif0" "inout" "inout")
6874 ("rtranif1" "inout" "inout")
6875 ("tran" "inout" "inout")
6876 ("tranif0" "inout" "inout")
6877 ("tranif1" "inout" "inout")
6880 "Map of direction for each positional argument to each gate primitive.")
6882 (defvar verilog-gate-keywords (mapcar `car verilog-gate-ios)
6883 "Keywords for gate primitives.")
6885 (defun verilog-string-diff (str1 str2)
6886 "Return index of first letter where STR1 and STR2 differs."
6890 (if (or (> (1+ diff) (length str1))
6891 (> (1+ diff) (length str2)))
6893 (or (equal (aref str1 diff) (aref str2 diff))
6895 (setq diff (1+ diff))))))
6897 ;; Calculate all possible completions for functions if argument is `function',
6898 ;; completions for procedures if argument is `procedure' or both functions and
6899 ;; procedures otherwise.
6901 (defun verilog-func-completion (type)
6902 "Build regular expression for module/task/function names.
6903 TYPE is 'module, 'tf for task or function, or t if unknown."
6904 (if (string= verilog-str "")
6905 (setq verilog-str "[a-zA-Z_]"))
6906 (let ((verilog-str (concat (cond
6907 ((eq type 'module) "\\<\\(module\\)\\s +")
6908 ((eq type 'tf) "\\<\\(task\\|function\\)\\s +")
6909 (t "\\<\\(task\\|function\\|module\\)\\s +"))
6910 "\\<\\(" verilog-str "[a-zA-Z0-9_.]*\\)\\>"))
6913 (if (not (looking-at verilog-defun-re))
6914 (verilog-re-search-backward verilog-defun-re nil t))
6917 ;; Search through all reachable functions
6918 (goto-char (point-min))
6919 (while (verilog-re-search-forward verilog-str (point-max) t)
6920 (progn (setq match (buffer-substring (match-beginning 2)
6922 (if (or (null verilog-pred)
6923 (funcall verilog-pred match))
6924 (setq verilog-all (cons match verilog-all)))))
6925 (if (match-beginning 0)
6926 (goto-char (match-beginning 0)))))
6928 (defun verilog-get-completion-decl (end)
6929 "Macro for searching through current declaration (var, type or const)
6930 for matches of `str' and adding the occurrence tp `all' through point END."
6931 (let ((re (or (and verilog-indent-declaration-macros
6932 verilog-declaration-re-2-macro)
6933 verilog-declaration-re-2-no-macro))
6936 (while (and (< (point) end)
6937 (verilog-re-search-forward re end t))
6938 ;; Traverse current line
6939 (setq decl-end (save-excursion (verilog-declaration-end)))
6940 (while (and (verilog-re-search-forward verilog-symbol-re decl-end t)
6941 (not (match-end 1)))
6942 (setq match (buffer-substring (match-beginning 0) (match-end 0)))
6943 (if (string-match (concat "\\<" verilog-str) match)
6944 (if (or (null verilog-pred)
6945 (funcall verilog-pred match))
6946 (setq verilog-all (cons match verilog-all)))))
6950 (defun verilog-type-completion ()
6951 "Calculate all possible completions for types."
6952 (let ((start (point))
6954 ;; Search for all reachable type declarations
6955 (while (or (verilog-beg-of-defun)
6956 (setq goon (not goon)))
6958 (if (and (< start (prog1 (save-excursion (verilog-end-of-defun)
6961 (verilog-re-search-forward
6962 "\\<type\\>\\|\\<\\(begin\\|function\\|procedure\\)\\>"
6964 (not (match-end 1)))
6965 ;; Check current type declaration
6966 (verilog-get-completion-decl start))))))
6968 (defun verilog-var-completion ()
6969 "Calculate all possible completions for variables (or constants)."
6970 (let ((start (point)))
6971 ;; Search for all reachable var declarations
6972 (verilog-beg-of-defun)
6974 ;; Check var declarations
6975 (verilog-get-completion-decl start))))
6977 (defun verilog-keyword-completion (keyword-list)
6978 "Give list of all possible completions of keywords in KEYWORD-LIST."
6980 (if (string-match (concat "\\<" verilog-str) s)
6981 (if (or (null verilog-pred)
6982 (funcall verilog-pred s))
6983 (setq verilog-all (cons s verilog-all)))))
6987 (defun verilog-completion (verilog-str verilog-pred verilog-flag)
6988 "Function passed to `completing-read', `try-completion' or `all-completions'.
6989 Called to get completion on VERILOG-STR. If VERILOG-PRED is non-nil, it
6990 must be a function to be called for every match to check if this should
6991 really be a match. If VERILOG-FLAG is t, the function returns a list of
6992 all possible completions. If VERILOG-FLAG is nil it returns a string,
6993 the longest possible completion, or t if VERILOG-STR is an exact match.
6994 If VERILOG-FLAG is 'lambda, the function returns t if VERILOG-STR is an
6995 exact match, nil otherwise."
6997 (let ((verilog-all nil))
6998 ;; Set buffer to use for searching labels. This should be set
6999 ;; within functions which use verilog-completions
7000 (set-buffer verilog-buffer-to-use)
7002 ;; Determine what should be completed
7003 (let ((state (car (verilog-calculate-indent))))
7004 (cond ((eq state 'defun)
7005 (save-excursion (verilog-var-completion))
7006 (verilog-func-completion 'module)
7007 (verilog-keyword-completion verilog-defun-keywords))
7009 ((eq state 'behavioral)
7010 (save-excursion (verilog-var-completion))
7011 (verilog-func-completion 'module)
7012 (verilog-keyword-completion verilog-defun-keywords))
7015 (save-excursion (verilog-var-completion))
7016 (verilog-func-completion 'tf)
7017 (verilog-keyword-completion verilog-block-keywords))
7020 (save-excursion (verilog-var-completion))
7021 (verilog-func-completion 'tf)
7022 (verilog-keyword-completion verilog-case-keywords))
7025 (save-excursion (verilog-var-completion))
7026 (verilog-func-completion 'tf)
7027 (verilog-keyword-completion verilog-tf-keywords))
7030 (save-excursion (verilog-var-completion))
7031 (verilog-keyword-completion verilog-cpp-keywords))
7033 ((eq state 'cparenexp)
7034 (save-excursion (verilog-var-completion)))
7037 (save-excursion (verilog-var-completion))
7038 (verilog-func-completion 'both)
7039 (verilog-keyword-completion verilog-separator-keywords))))
7041 ;; Now we have built a list of all matches. Give response to caller
7042 (verilog-completion-response))))
7044 (defun verilog-completion-response ()
7045 (cond ((or (equal verilog-flag 'lambda) (null verilog-flag))
7046 ;; This was not called by all-completions
7047 (if (null verilog-all)
7048 ;; Return nil if there was no matching label
7050 ;; Get longest string common in the labels
7051 (let* ((elm (cdr verilog-all))
7052 (match (car verilog-all))
7053 (min (length match))
7055 (if (string= match verilog-str)
7056 ;; Return t if first match was an exact match
7058 (while (not (null elm))
7059 ;; Find longest common string
7060 (if (< (setq tmp (verilog-string-diff match (car elm))) min)
7063 (setq match (substring match 0 min))))
7064 ;; Terminate with match=t if this is an exact match
7065 (if (string= (car elm) verilog-str)
7069 (setq elm (cdr elm)))))
7070 ;; If this is a test just for exact match, return nil ot t
7071 (if (and (equal verilog-flag 'lambda) (not (equal match 't)))
7074 ;; If flag is t, this was called by all-completions. Return
7075 ;; list of all possible completions
7079 (defvar verilog-last-word-numb 0)
7080 (defvar verilog-last-word-shown nil)
7081 (defvar verilog-last-completions nil)
7083 (defun verilog-complete-word ()
7084 "Complete word at current point.
7085 \(See also `verilog-toggle-completions', `verilog-type-keywords',
7086 and `verilog-separator-keywords'.)"
7088 (let* ((b (save-excursion (skip-chars-backward "a-zA-Z0-9_") (point)))
7089 (e (save-excursion (skip-chars-forward "a-zA-Z0-9_") (point)))
7090 (verilog-str (buffer-substring b e))
7091 ;; The following variable is used in verilog-completion
7092 (verilog-buffer-to-use (current-buffer))
7093 (allcomp (if (and verilog-toggle-completions
7094 (string= verilog-last-word-shown verilog-str))
7095 verilog-last-completions
7096 (all-completions verilog-str 'verilog-completion)))
7097 (match (if verilog-toggle-completions
7099 verilog-str (mapcar (lambda (elm)
7100 (cons elm 0)) allcomp)))))
7101 ;; Delete old string
7104 ;; Toggle-completions inserts whole labels
7105 (if verilog-toggle-completions
7107 ;; Update entry number in list
7108 (setq verilog-last-completions allcomp
7109 verilog-last-word-numb
7110 (if (>= verilog-last-word-numb (1- (length allcomp)))
7112 (1+ verilog-last-word-numb)))
7113 (setq verilog-last-word-shown (elt allcomp verilog-last-word-numb))
7114 ;; Display next match or same string if no match was found
7115 (if (not (null allcomp))
7116 (insert "" verilog-last-word-shown)
7117 (insert "" verilog-str)
7118 (message "(No match)")))
7119 ;; The other form of completion does not necessarily do that.
7121 ;; Insert match if found, or the original string if no match
7122 (if (or (null match) (equal match 't))
7123 (progn (insert "" verilog-str)
7124 (message "(No match)"))
7126 ;; Give message about current status of completion
7127 (cond ((equal match 't)
7128 (if (not (null (cdr allcomp)))
7129 (message "(Complete but not unique)")
7130 (message "(Sole completion)")))
7131 ;; Display buffer if the current completion didn't help
7132 ;; on completing the label.
7133 ((and (not (null (cdr allcomp))) (= (length verilog-str)
7135 (with-output-to-temp-buffer "*Completions*"
7136 (display-completion-list allcomp))
7137 ;; Wait for a key press. Then delete *Completion* window
7138 (momentary-string-display "" (point))
7139 (delete-window (get-buffer-window (get-buffer "*Completions*")))
7142 (defun verilog-show-completions ()
7143 "Show all possible completions at current point."
7145 (let* ((b (save-excursion (skip-chars-backward "a-zA-Z0-9_") (point)))
7146 (e (save-excursion (skip-chars-forward "a-zA-Z0-9_") (point)))
7147 (verilog-str (buffer-substring b e))
7148 ;; The following variable is used in verilog-completion
7149 (verilog-buffer-to-use (current-buffer))
7150 (allcomp (if (and verilog-toggle-completions
7151 (string= verilog-last-word-shown verilog-str))
7152 verilog-last-completions
7153 (all-completions verilog-str 'verilog-completion))))
7154 ;; Show possible completions in a temporary buffer.
7155 (with-output-to-temp-buffer "*Completions*"
7156 (display-completion-list allcomp))
7157 ;; Wait for a key press. Then delete *Completion* window
7158 (momentary-string-display "" (point))
7159 (delete-window (get-buffer-window (get-buffer "*Completions*")))))
7162 (defun verilog-get-default-symbol ()
7163 "Return symbol around current point as a string."
7165 (buffer-substring (progn
7166 (skip-chars-backward " \t")
7167 (skip-chars-backward "a-zA-Z0-9_")
7170 (skip-chars-forward "a-zA-Z0-9_")
7173 (defun verilog-build-defun-re (str &optional arg)
7174 "Return function/task/module starting with STR as regular expression.
7175 With optional second ARG non-nil, STR is the complete name of the instruction."
7177 (concat "^\\(function\\|task\\|module\\)[ \t]+\\(" str "\\)\\>")
7178 (concat "^\\(function\\|task\\|module\\)[ \t]+\\(" str "[a-zA-Z0-9_]*\\)\\>")))
7180 (defun verilog-comp-defun (verilog-str verilog-pred verilog-flag)
7181 "Function passed to `completing-read', `try-completion' or `all-completions'.
7182 Returns a completion on any function name based on VERILOG-STR prefix. If
7183 VERILOG-PRED is non-nil, it must be a function to be called for every match
7184 to check if this should really be a match. If VERILOG-FLAG is t, the
7185 function returns a list of all possible completions. If it is nil it
7186 returns a string, the longest possible completion, or t if VERILOG-STR is
7187 an exact match. If VERILOG-FLAG is 'lambda, the function returns t if
7188 VERILOG-STR is an exact match, nil otherwise."
7190 (let ((verilog-all nil)
7193 ;; Set buffer to use for searching labels. This should be set
7194 ;; within functions which use verilog-completions
7195 (set-buffer verilog-buffer-to-use)
7197 (let ((verilog-str verilog-str))
7198 ;; Build regular expression for functions
7199 (if (string= verilog-str "")
7200 (setq verilog-str (verilog-build-defun-re "[a-zA-Z_]"))
7201 (setq verilog-str (verilog-build-defun-re verilog-str)))
7202 (goto-char (point-min))
7204 ;; Build a list of all possible completions
7205 (while (verilog-re-search-forward verilog-str nil t)
7206 (setq match (buffer-substring (match-beginning 2) (match-end 2)))
7207 (if (or (null verilog-pred)
7208 (funcall verilog-pred match))
7209 (setq verilog-all (cons match verilog-all)))))
7211 ;; Now we have built a list of all matches. Give response to caller
7212 (verilog-completion-response))))
7214 (defun verilog-goto-defun ()
7215 "Move to specified Verilog module/interface/task/function.
7216 The default is a name found in the buffer around point.
7217 If search fails, other files are checked based on
7218 `verilog-library-flags'."
7220 (let* ((default (verilog-get-default-symbol))
7221 ;; The following variable is used in verilog-comp-function
7222 (verilog-buffer-to-use (current-buffer))
7223 (label (if (not (string= default ""))
7224 ;; Do completion with default
7225 (completing-read (concat "Goto-Label: (default "
7227 'verilog-comp-defun nil nil "")
7228 ;; There is no default value. Complete without it
7229 (completing-read "Goto-Label: "
7230 'verilog-comp-defun nil nil "")))
7232 ;; Make sure library paths are correct, in case need to resolve module
7233 (verilog-auto-reeval-locals)
7234 (verilog-getopt-flags)
7235 ;; If there was no response on prompt, use default value
7236 (if (string= label "")
7237 (setq label default))
7238 ;; Goto right place in buffer if label is not an empty string
7239 (or (string= label "")
7242 (goto-char (point-min))
7244 (re-search-forward (verilog-build-defun-re label t) nil t)))
7247 (beginning-of-line))
7249 (verilog-goto-defun-file label))))
7251 ;; Eliminate compile warning
7252 (defvar occur-pos-list)
7254 (defun verilog-showscopes ()
7255 "List all scopes in this module."
7257 (let ((buffer (current-buffer))
7261 (prevpos (point-min))
7262 (final-context-start (make-marker))
7263 (regexp "\\(module\\s-+\\w+\\s-*(\\)\\|\\(\\w+\\s-+\\w+\\s-*(\\)"))
7264 (with-output-to-temp-buffer "*Occur*"
7266 (message (format "Searching for %s ..." regexp))
7267 ;; Find next match, but give up if prev match was at end of buffer.
7268 (while (and (not (= prevpos (point-max)))
7269 (verilog-re-search-forward regexp nil t))
7270 (goto-char (match-beginning 0))
7273 (setq linenum (+ linenum (count-lines prevpos (point)))))
7274 (setq prevpos (point))
7275 (goto-char (match-end 0))
7276 (let* ((start (save-excursion
7277 (goto-char (match-beginning 0))
7278 (forward-line (if (< nlines 0) nlines (- nlines)))
7280 (end (save-excursion
7281 (goto-char (match-end 0))
7283 (forward-line (1+ nlines))
7286 (tag (format "%3d" linenum))
7287 (empty (make-string (length tag) ?\ ))
7290 (setq tem (make-marker))
7291 (set-marker tem (point))
7292 (set-buffer standard-output)
7293 (setq occur-pos-list (cons tem occur-pos-list))
7294 (or first (zerop nlines)
7295 (insert "--------\n"))
7297 (insert-buffer-substring buffer start end)
7298 (backward-char (- end start))
7299 (setq tem (if (< nlines 0) (- nlines) nlines))
7303 (setq tem (1- tem)))
7304 (let ((this-linenum linenum))
7305 (set-marker final-context-start
7306 (+ (point) (- (match-end 0) (match-beginning 0))))
7307 (while (< (point) final-context-start)
7309 (setq tag (format "%3d" this-linenum)))
7310 (insert tag ?:)))))))
7311 (set-buffer-modified-p nil))))
7314 ;; Highlight helper functions
7315 (defconst verilog-directive-regexp "\\(translate\\|coverage\\|lint\\)_")
7316 (defun verilog-within-translate-off ()
7317 "Return point if within translate-off region, else nil."
7318 (and (save-excursion
7320 (concat "//\\s-*.*\\s-*" verilog-directive-regexp "\\(on\\|off\\)\\>")
7322 (equal "off" (match-string 2))
7325 (defun verilog-start-translate-off (limit)
7326 "Return point before translate-off directive if before LIMIT, else nil."
7327 (when (re-search-forward
7328 (concat "//\\s-*.*\\s-*" verilog-directive-regexp "off\\>")
7330 (match-beginning 0)))
7332 (defun verilog-back-to-start-translate-off (limit)
7333 "Return point before translate-off directive if before LIMIT, else nil."
7334 (when (re-search-backward
7335 (concat "//\\s-*.*\\s-*" verilog-directive-regexp "off\\>")
7337 (match-beginning 0)))
7339 (defun verilog-end-translate-off (limit)
7340 "Return point after translate-on directive if before LIMIT, else nil."
7342 (re-search-forward (concat
7343 "//\\s-*.*\\s-*" verilog-directive-regexp "on\\>") limit t))
7345 (defun verilog-match-translate-off (limit)
7346 "Match a translate-off block, setting `match-data' and returning t, else nil.
7347 Bound search by LIMIT."
7348 (when (< (point) limit)
7349 (let ((start (or (verilog-within-translate-off)
7350 (verilog-start-translate-off limit)))
7351 (case-fold-search t))
7353 (let ((end (or (verilog-end-translate-off limit) limit)))
7354 (set-match-data (list start end))
7355 (goto-char end))))))
7357 (defun verilog-font-lock-match-item (limit)
7358 "Match, and move over, any declaration item after point.
7359 Bound search by LIMIT. Adapted from
7360 `font-lock-match-c-style-declaration-item-and-skip-to-next'."
7363 (narrow-to-region (point-min) limit)
7365 (when (looking-at "\\s-*\\([a-zA-Z]\\w*\\)")
7367 (goto-char (match-end 1))
7368 ;; move to next item
7369 (if (looking-at "\\(\\s-*,\\)")
7370 (goto-char (match-end 1))
7375 ;; Added by Subbu Meiyappan for Header
7377 (defun verilog-header ()
7378 "Insert a standard Verilog file header.
7379 See also `verilog-sk-header' for an alternative format."
7381 (let ((start (point)))
7383 //-----------------------------------------------------------------------------
7385 // Project : <project>
7386 //-----------------------------------------------------------------------------
7387 // File : <filename>
7388 // Author : <author>
7389 // Created : <credate>
7390 // Last modified : <moddate>
7391 //-----------------------------------------------------------------------------
7394 //-----------------------------------------------------------------------------
7395 // Copyright (c) <copydate> by <company> This model is the confidential and
7396 // proprietary property of <company> and the possession or use of this
7397 // file requires a written license from <company>.
7398 //------------------------------------------------------------------------------
7399 // Modification history :
7401 //-----------------------------------------------------------------------------
7405 (search-forward "<filename>")
7406 (replace-match (buffer-name) t t)
7407 (search-forward "<author>") (replace-match "" t t)
7408 (insert (user-full-name))
7409 (insert " <" (user-login-name) "@" (system-name) ">")
7410 (search-forward "<credate>") (replace-match "" t t)
7411 (verilog-insert-date)
7412 (search-forward "<moddate>") (replace-match "" t t)
7413 (verilog-insert-date)
7414 (search-forward "<copydate>") (replace-match "" t t)
7415 (verilog-insert-year)
7416 (search-forward "<modhist>") (replace-match "" t t)
7417 (verilog-insert-date)
7418 (insert " : created")
7421 (setq string (read-string "title: "))
7422 (search-forward "<title>")
7423 (replace-match string t t)
7424 (setq string (read-string "project: " verilog-project))
7425 (setq verilog-project string)
7426 (search-forward "<project>")
7427 (replace-match string t t)
7428 (setq string (read-string "Company: " verilog-company))
7429 (setq verilog-company string)
7430 (search-forward "<company>")
7431 (replace-match string t t)
7432 (search-forward "<company>")
7433 (replace-match string t t)
7434 (search-forward "<company>")
7435 (replace-match string t t)
7436 (search-backward "<description>")
7437 (replace-match "" t t))))
7439 ;; verilog-header Uses the verilog-insert-date function
7441 (defun verilog-insert-date ()
7442 "Insert date from the system."
7444 (if verilog-date-scientific-format
7445 (insert (format-time-string "%Y/%m/%d"))
7446 (insert (format-time-string "%d.%m.%Y"))))
7448 (defun verilog-insert-year ()
7449 "Insert year from the system."
7451 (insert (format-time-string "%Y")))
7455 ;; Signal list parsing
7458 ;; Elements of a signal list
7459 ;; Unfortunately we use 'assoc' on this, so can't be a vector
7460 (defsubst verilog-sig-new (name bits comment mem enum signed type multidim modport)
7461 (list name bits comment mem enum signed type multidim modport))
7462 (defsubst verilog-sig-name (sig)
7464 (defsubst verilog-sig-bits (sig)
7466 (defsubst verilog-sig-comment (sig)
7468 (defsubst verilog-sig-memory (sig)
7470 (defsubst verilog-sig-enum (sig)
7472 (defsubst verilog-sig-signed (sig)
7474 (defsubst verilog-sig-type (sig)
7476 (defsubst verilog-sig-type-set (sig type)
7477 (setcar (nthcdr 6 sig) type))
7478 (defsubst verilog-sig-multidim (sig)
7480 (defsubst verilog-sig-multidim-string (sig)
7481 (if (verilog-sig-multidim sig)
7482 (let ((str "") (args (verilog-sig-multidim sig)))
7484 (setq str (concat str (car args)))
7485 (setq args (cdr args)))
7487 (defsubst verilog-sig-modport (sig)
7489 (defsubst verilog-sig-width (sig)
7490 (verilog-make-width-expression (verilog-sig-bits sig)))
7492 (defsubst verilog-alw-new (outputs-del outputs-imm temps inputs)
7493 (vector outputs-del outputs-imm temps inputs))
7494 (defsubst verilog-alw-get-outputs-delayed (sigs)
7496 (defsubst verilog-alw-get-outputs-immediate (sigs)
7498 (defsubst verilog-alw-get-temps (sigs)
7500 (defsubst verilog-alw-get-inputs (sigs)
7502 (defsubst verilog-alw-get-uses-delayed (sigs)
7505 (defsubst verilog-modport-new (name clockings decls)
7506 (list name clockings decls))
7507 (defsubst verilog-modport-name (sig)
7509 (defsubst verilog-modport-clockings (sig)
7510 (nth 1 sig)) ;; Returns list of names
7511 (defsubst verilog-modport-clockings-add (sig val)
7512 (setcar (nthcdr 1 sig) (cons val (nth 1 sig))))
7513 (defsubst verilog-modport-decls (sig)
7514 (nth 2 sig)) ;; Returns verilog-decls-* structure
7515 (defsubst verilog-modport-decls-set (sig val)
7516 (setcar (nthcdr 2 sig) val))
7518 (defsubst verilog-modi-new (name fob pt type)
7519 (vector name fob pt type))
7520 (defsubst verilog-modi-name (modi)
7522 (defsubst verilog-modi-file-or-buffer (modi)
7524 (defsubst verilog-modi-get-point (modi)
7526 (defsubst verilog-modi-get-type (modi) ;; "module" or "interface"
7528 (defsubst verilog-modi-get-decls (modi)
7529 (verilog-modi-cache-results modi 'verilog-read-decls))
7530 (defsubst verilog-modi-get-sub-decls (modi)
7531 (verilog-modi-cache-results modi 'verilog-read-sub-decls))
7533 ;; Signal reading for given module
7534 ;; Note these all take modi's - as returned from verilog-modi-current
7535 (defsubst verilog-decls-new (out inout in vars modports assigns consts gparams interfaces)
7536 (vector out inout in vars modports assigns consts gparams interfaces))
7537 (defsubst verilog-decls-append (a b)
7538 (cond ((not a) b) ((not b) a)
7539 (t (vector (append (aref a 0) (aref b 0)) (append (aref a 1) (aref b 1))
7540 (append (aref a 2) (aref b 2)) (append (aref a 3) (aref b 3))
7541 (append (aref a 4) (aref b 4)) (append (aref a 5) (aref b 5))
7542 (append (aref a 6) (aref b 6)) (append (aref a 7) (aref b 7))
7543 (append (aref a 8) (aref b 8))))))
7544 (defsubst verilog-decls-get-outputs (decls)
7546 (defsubst verilog-decls-get-inouts (decls)
7548 (defsubst verilog-decls-get-inputs (decls)
7550 (defsubst verilog-decls-get-vars (decls)
7552 (defsubst verilog-decls-get-modports (decls) ;; Also for clocking blocks; contains another verilog-decls struct
7553 (aref decls 4)) ;; Returns verilog-modport* structure
7554 (defsubst verilog-decls-get-assigns (decls)
7556 (defsubst verilog-decls-get-consts (decls)
7558 (defsubst verilog-decls-get-gparams (decls)
7560 (defsubst verilog-decls-get-interfaces (decls)
7564 (defsubst verilog-subdecls-new (out inout in intf intfd)
7565 (vector out inout in intf intfd))
7566 (defsubst verilog-subdecls-get-outputs (subdecls)
7568 (defsubst verilog-subdecls-get-inouts (subdecls)
7570 (defsubst verilog-subdecls-get-inputs (subdecls)
7572 (defsubst verilog-subdecls-get-interfaces (subdecls)
7574 (defsubst verilog-subdecls-get-interfaced (subdecls)
7577 (defun verilog-signals-from-signame (signame-list)
7578 "Return signals in standard form from SIGNAME-LIST, a simple list of names."
7579 (mapcar (lambda (name) (verilog-sig-new name nil nil nil nil nil nil nil nil))
7582 (defun verilog-signals-in (in-list not-list)
7583 "Return list of signals in IN-LIST that are also in NOT-LIST.
7584 Also remove any duplicates in IN-LIST.
7585 Signals must be in standard (base vector) form."
7586 ;; This function is hot, so implemented as O(1)
7587 (cond ((eval-when-compile (fboundp 'make-hash-table))
7588 (let ((ht (make-hash-table :test 'equal :rehash-size 4.0))
7589 (ht-not (make-hash-table :test 'equal :rehash-size 4.0))
7592 (puthash (car (car not-list)) t ht-not)
7593 (setq not-list (cdr not-list)))
7595 (when (and (gethash (verilog-sig-name (car in-list)) ht-not)
7596 (not (gethash (verilog-sig-name (car in-list)) ht)))
7597 (setq out-list (cons (car in-list) out-list))
7598 (puthash (verilog-sig-name (car in-list)) t ht))
7599 (setq in-list (cdr in-list)))
7600 (nreverse out-list)))
7601 ;; Slower Fallback if no hash tables (pre Emacs 21.1/XEmacs 21.4)
7605 (if (and (assoc (verilog-sig-name (car in-list)) not-list)
7606 (not (assoc (verilog-sig-name (car in-list)) out-list)))
7607 (setq out-list (cons (car in-list) out-list)))
7608 (setq in-list (cdr in-list)))
7609 (nreverse out-list)))))
7610 ;;(verilog-signals-in '(("A" "") ("B" "") ("DEL" "[2:3]")) '(("DEL" "") ("C" "")))
7612 (defun verilog-signals-not-in (in-list not-list)
7613 "Return list of signals in IN-LIST that aren't also in NOT-LIST.
7614 Also remove any duplicates in IN-LIST.
7615 Signals must be in standard (base vector) form."
7616 ;; This function is hot, so implemented as O(1)
7617 (cond ((eval-when-compile (fboundp 'make-hash-table))
7618 (let ((ht (make-hash-table :test 'equal :rehash-size 4.0))
7621 (puthash (car (car not-list)) t ht)
7622 (setq not-list (cdr not-list)))
7624 (when (not (gethash (verilog-sig-name (car in-list)) ht))
7625 (setq out-list (cons (car in-list) out-list))
7626 (puthash (verilog-sig-name (car in-list)) t ht))
7627 (setq in-list (cdr in-list)))
7628 (nreverse out-list)))
7629 ;; Slower Fallback if no hash tables (pre Emacs 21.1/XEmacs 21.4)
7633 (if (and (not (assoc (verilog-sig-name (car in-list)) not-list))
7634 (not (assoc (verilog-sig-name (car in-list)) out-list)))
7635 (setq out-list (cons (car in-list) out-list)))
7636 (setq in-list (cdr in-list)))
7637 (nreverse out-list)))))
7638 ;;(verilog-signals-not-in '(("A" "") ("B" "") ("DEL" "[2:3]")) '(("DEL" "") ("EXT" "")))
7640 (defun verilog-signals-memory (in-list)
7641 "Return list of signals in IN-LIST that are memorized (multidimensional)."
7644 (if (nth 3 (car in-list))
7645 (setq out-list (cons (car in-list) out-list)))
7646 (setq in-list (cdr in-list)))
7648 ;;(verilog-signals-memory '(("A" nil nil "[3:0]")) '(("B" nil nil nil)))
7650 (defun verilog-signals-sort-compare (a b)
7651 "Compare signal A and B for sorting."
7652 (string< (verilog-sig-name a) (verilog-sig-name b)))
7654 (defun verilog-signals-not-params (in-list)
7655 "Return list of signals in IN-LIST that aren't parameters or numeric constants."
7658 (unless (boundp (intern (concat "vh-" (verilog-sig-name (car in-list)))))
7659 (setq out-list (cons (car in-list) out-list)))
7660 (setq in-list (cdr in-list)))
7661 (nreverse out-list)))
7663 (defun verilog-signals-with (func in-list)
7664 "Return IN-LIST with only signals where FUNC passed each signal is true."
7667 (when (funcall func (car in-list))
7668 (setq out-list (cons (car in-list) out-list)))
7669 (setq in-list (cdr in-list)))
7670 (nreverse out-list)))
7672 (defun verilog-signals-combine-bus (in-list)
7673 "Return a list of signals in IN-LIST, with buses combined.
7674 Duplicate signals are also removed. For example A[2] and A[1] become A[2:1]."
7677 sig highbit lowbit ; Temp information about current signal
7678 sv-name sv-highbit sv-lowbit ; Details about signal we are forming
7679 sv-comment sv-memory sv-enum sv-signed sv-type sv-multidim sv-busstring
7682 ;; Shove signals so duplicated signals will be adjacent
7683 (setq in-list (sort in-list `verilog-signals-sort-compare))
7685 (setq sig (car in-list))
7686 ;; No current signal; form from existing details
7688 (setq sv-name (verilog-sig-name sig)
7691 sv-comment (verilog-sig-comment sig)
7692 sv-memory (verilog-sig-memory sig)
7693 sv-enum (verilog-sig-enum sig)
7694 sv-signed (verilog-sig-signed sig)
7695 sv-type (verilog-sig-type sig)
7696 sv-multidim (verilog-sig-multidim sig)
7697 sv-modport (verilog-sig-modport sig)
7700 ;; Extract bus details
7701 (setq bus (verilog-sig-bits sig))
7702 (setq bus (and bus (verilog-simplify-range-expression bus)))
7704 (or (and (string-match "\\[\\([0-9]+\\):\\([0-9]+\\)\\]" bus)
7705 (setq highbit (string-to-number (match-string 1 bus))
7706 lowbit (string-to-number
7707 (match-string 2 bus))))
7708 (and (string-match "\\[\\([0-9]+\\)\\]" bus)
7709 (setq highbit (string-to-number (match-string 1 bus))
7711 ;; Combine bits in bus
7713 (setq sv-highbit (max highbit sv-highbit)
7714 sv-lowbit (min lowbit sv-lowbit))
7715 (setq sv-highbit highbit
7718 ;; String, probably something like `preproc:0
7719 (setq sv-busstring bus)))
7720 ;; Peek ahead to next signal
7721 (setq in-list (cdr in-list))
7722 (setq sig (car in-list))
7723 (cond ((and sig (equal sv-name (verilog-sig-name sig)))
7724 ;; Combine with this signal
7725 (when (and sv-busstring
7726 (not (equal sv-busstring (verilog-sig-bits sig))))
7727 (when nil ;; Debugging
7728 (message (concat "Warning, can't merge into single bus "
7730 ", the AUTOs may be wrong")))
7731 (setq buswarn ", Couldn't Merge"))
7732 (if (verilog-sig-comment sig) (setq combo ", ..."))
7733 (setq sv-memory (or sv-memory (verilog-sig-memory sig))
7734 sv-enum (or sv-enum (verilog-sig-enum sig))
7735 sv-signed (or sv-signed (verilog-sig-signed sig))
7736 sv-type (or sv-type (verilog-sig-type sig))
7737 sv-multidim (or sv-multidim (verilog-sig-multidim sig))
7738 sv-modport (or sv-modport (verilog-sig-modport sig))))
7739 ;; Doesn't match next signal, add to queue, zero in prep for next
7740 ;; Note sig may also be nil for the last signal in the list
7743 (cons (verilog-sig-new
7747 (concat "[" (int-to-string sv-highbit) ":"
7748 (int-to-string sv-lowbit) "]")))
7749 (concat sv-comment combo buswarn)
7750 sv-memory sv-enum sv-signed sv-type sv-multidim sv-modport)
7756 (defun verilog-sig-tieoff (sig)
7757 "Return tieoff expression for given SIG, with appropriate width.
7758 Tieoff value uses `verilog-active-low-regexp' and
7759 `verilog-auto-reset-widths'."
7761 (if (and verilog-active-low-regexp
7762 (string-match verilog-active-low-regexp (verilog-sig-name sig)))
7764 (cond ((not verilog-auto-reset-widths)
7766 ((equal verilog-auto-reset-widths 'unbased)
7768 ;; Else presume verilog-auto-reset-widths is true
7770 (let* ((width (verilog-sig-width sig)))
7771 (if (string-match "^[0-9]+$" width)
7772 (concat width (if (verilog-sig-signed sig) "'sh0" "'h0"))
7773 (concat "{" width "{1'b0}}")))))))
7779 (defun verilog-decls-princ (decls &optional header prefix)
7780 "For debug, dump the `verilog-read-decls' structure DECLS."
7782 (if header (princ header))
7783 (setq prefix (or prefix ""))
7784 (verilog-signals-princ (verilog-decls-get-outputs decls)
7785 (concat prefix "Outputs:\n") (concat prefix " "))
7786 (verilog-signals-princ (verilog-decls-get-inouts decls)
7787 (concat prefix "Inout:\n") (concat prefix " "))
7788 (verilog-signals-princ (verilog-decls-get-inputs decls)
7789 (concat prefix "Inputs:\n") (concat prefix " "))
7790 (verilog-signals-princ (verilog-decls-get-vars decls)
7791 (concat prefix "Vars:\n") (concat prefix " "))
7792 (verilog-signals-princ (verilog-decls-get-assigns decls)
7793 (concat prefix "Assigns:\n") (concat prefix " "))
7794 (verilog-signals-princ (verilog-decls-get-consts decls)
7795 (concat prefix "Consts:\n") (concat prefix " "))
7796 (verilog-signals-princ (verilog-decls-get-gparams decls)
7797 (concat prefix "Gparams:\n") (concat prefix " "))
7798 (verilog-signals-princ (verilog-decls-get-interfaces decls)
7799 (concat prefix "Interfaces:\n") (concat prefix " "))
7800 (verilog-modport-princ (verilog-decls-get-modports decls)
7801 (concat prefix "Modports:\n") (concat prefix " "))
7804 (defun verilog-signals-princ (signals &optional header prefix)
7805 "For debug, dump internal SIGNALS structures, with HEADER and PREFIX."
7807 (if header (princ header))
7809 (let ((sig (car signals)))
7810 (setq signals (cdr signals))
7812 (princ "\"") (princ (verilog-sig-name sig)) (princ "\"")
7813 (princ " bits=") (princ (verilog-sig-bits sig))
7814 (princ " cmt=") (princ (verilog-sig-comment sig))
7815 (princ " mem=") (princ (verilog-sig-memory sig))
7816 (princ " enum=") (princ (verilog-sig-enum sig))
7817 (princ " sign=") (princ (verilog-sig-signed sig))
7818 (princ " type=") (princ (verilog-sig-type sig))
7819 (princ " dim=") (princ (verilog-sig-multidim sig))
7820 (princ " modp=") (princ (verilog-sig-modport sig))
7823 (defun verilog-modport-princ (modports &optional header prefix)
7824 "For debug, dump internal MODPORT structures, with HEADER and PREFIX."
7826 (if header (princ header))
7828 (let ((sig (car modports)))
7829 (setq modports (cdr modports))
7831 (princ "\"") (princ (verilog-modport-name sig)) (princ "\"")
7832 (princ " clockings=") (princ (verilog-modport-clockings sig))
7834 (verilog-decls-princ (verilog-modport-decls sig)
7835 (concat prefix " syms:\n")
7836 (concat prefix " "))))))
7839 ;; Port/Wire/Etc Reading
7842 (defun verilog-read-inst-backward-name ()
7843 "Internal. Move point back to beginning of inst-name."
7844 (verilog-backward-open-paren)
7847 (verilog-re-search-backward-quick "\\()\\|\\b[a-zA-Z0-9`_\$]\\|\\]\\)" nil nil) ; ] isn't word boundary
7848 (cond ((looking-at ")")
7849 (verilog-backward-open-paren))
7850 (t (setq done t)))))
7851 (while (looking-at "\\]")
7852 (verilog-backward-open-bracket)
7853 (verilog-re-search-backward-quick "\\(\\b[a-zA-Z0-9`_\$]\\|\\]\\)" nil nil))
7854 (skip-chars-backward "a-zA-Z0-9`_$"))
7856 (defun verilog-read-inst-module-matcher ()
7857 "Set match data 0 with module_name when point is inside instantiation."
7858 (verilog-read-inst-backward-name)
7859 ;; Skip over instantiation name
7860 (verilog-re-search-backward-quick "\\(\\b[a-zA-Z0-9`_\$]\\|)\\)" nil nil) ; ) isn't word boundary
7861 ;; Check for parameterized instantiations
7862 (when (looking-at ")")
7863 (verilog-backward-open-paren)
7864 (verilog-re-search-backward-quick "\\b[a-zA-Z0-9`_\$]" nil nil))
7865 (skip-chars-backward "a-zA-Z0-9'_$")
7866 (looking-at "[a-zA-Z0-9`_\$]+")
7867 ;; Important: don't use match string, this must work with Emacs 19 font-lock on
7868 (buffer-substring-no-properties (match-beginning 0) (match-end 0))
7869 ;; Caller assumes match-beginning/match-end is still set
7872 (defun verilog-read-inst-module ()
7873 "Return module_name when point is inside instantiation."
7875 (verilog-read-inst-module-matcher)))
7877 (defun verilog-read-inst-name ()
7878 "Return instance_name when point is inside instantiation."
7880 (verilog-read-inst-backward-name)
7881 (looking-at "[a-zA-Z0-9`_\$]+")
7882 ;; Important: don't use match string, this must work with Emacs 19 font-lock on
7883 (buffer-substring-no-properties (match-beginning 0) (match-end 0))))
7885 (defun verilog-read-module-name ()
7886 "Return module name when after its ( or ;."
7888 (re-search-backward "[(;]")
7889 ;; Due to "module x import y (" we must search for declaration begin
7890 (verilog-re-search-backward-quick verilog-defun-re nil nil)
7891 (goto-char (match-end 0))
7892 (verilog-re-search-forward-quick "\\b[a-zA-Z0-9`_\$]+" nil nil)
7893 ;; Important: don't use match string, this must work with Emacs 19 font-lock on
7894 (verilog-symbol-detick
7895 (buffer-substring-no-properties (match-beginning 0) (match-end 0)) t)))
7897 (defun verilog-read-inst-param-value ()
7898 "Return list of parameters and values when point is inside instantiation."
7900 (verilog-read-inst-backward-name)
7901 ;; Skip over instantiation name
7902 (verilog-re-search-backward-quick "\\(\\b[a-zA-Z0-9`_\$]\\|)\\)" nil nil) ; ) isn't word boundary
7903 ;; If there are parameterized instantiations
7904 (when (looking-at ")")
7905 (let ((end-pt (point))
7907 param-name paren-beg-pt param-value)
7908 (verilog-backward-open-paren)
7909 (while (verilog-re-search-forward-quick "\\." end-pt t)
7910 (verilog-re-search-forward-quick "\\([a-zA-Z0-9`_\$]\\)" nil nil)
7911 (skip-chars-backward "a-zA-Z0-9'_$")
7912 (looking-at "[a-zA-Z0-9`_\$]+")
7913 (setq param-name (buffer-substring-no-properties
7914 (match-beginning 0) (match-end 0)))
7915 (verilog-re-search-forward-quick "(" nil nil)
7916 (setq paren-beg-pt (point))
7917 (verilog-forward-close-paren)
7918 (setq param-value (verilog-string-remove-spaces
7919 (buffer-substring-no-properties
7920 paren-beg-pt (1- (point)))))
7921 (setq params (cons (list param-name param-value) params)))
7924 (defun verilog-read-auto-params (num-param &optional max-param)
7925 "Return parameter list inside auto.
7926 Optional NUM-PARAM and MAX-PARAM check for a specific number of parameters."
7929 ;; /*AUTOPUNT("parameter", "parameter")*/
7931 (while (looking-at "(?\\s *\"\\([^\"]*\\)\"\\s *,?")
7932 (setq olist (cons (match-string 1) olist))
7933 (goto-char (match-end 0))))
7934 (or (eq nil num-param)
7935 (<= num-param (length olist))
7936 (error "%s: Expected %d parameters" (verilog-point-text) num-param))
7937 (if (eq max-param nil) (setq max-param num-param))
7938 (or (eq nil max-param)
7939 (>= max-param (length olist))
7940 (error "%s: Expected <= %d parameters" (verilog-point-text) max-param))
7943 (defun verilog-read-decls ()
7944 "Compute signal declaration information for the current module at point.
7945 Return an array of [outputs inouts inputs wire reg assign const]."
7946 (let ((end-mod-point (or (verilog-get-end-of-defun t) (point-max)))
7947 (functask 0) (paren 0) (sig-paren 0) (v2kargs-ok t)
7948 in-modport in-clocking ptype ign-prop
7949 sigs-in sigs-out sigs-inout sigs-var sigs-assign sigs-const
7950 sigs-gparam sigs-intf sigs-modports
7951 vec expect-signal keywd newsig rvalue enum io signed typedefed multidim
7955 (verilog-beg-of-defun-quick)
7956 (setq sigs-const (verilog-read-auto-constants (point) end-mod-point))
7957 (while (< (point) end-mod-point)
7958 ;;(if dbg (setq dbg (concat dbg (format "Pt %s Vec %s C%c Kwd'%s'\n" (point) vec (following-char) keywd))))
7961 (if (looking-at "[^\n]*\\(auto\\|synopsys\\)\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
7962 (setq enum (match-string 2)))
7963 (search-forward "\n"))
7964 ((looking-at "/\\*")
7966 (if (looking-at "[^\n]*\\(auto\\|synopsys\\)\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
7967 (setq enum (match-string 2)))
7968 (or (search-forward "*/")
7969 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
7970 ((looking-at "(\\*")
7971 ;; To advance past either "(*)" or "(* ... *)" don't forward past first *
7973 (or (search-forward "*)")
7974 (error "%s: Unmatched (* *), at char %d" (verilog-point-text) (point))))
7975 ((eq ?\" (following-char))
7976 (or (re-search-forward "[^\\]\"" nil t) ;; don't forward-char first, since we look for a non backslash first
7977 (error "%s: Unmatched quotes, at char %d" (verilog-point-text) (point))))
7978 ((eq ?\; (following-char))
7979 (when (and in-modport (not (eq in-modport t))) ;; end of a modport declaration
7980 (verilog-modport-decls-set
7982 (verilog-decls-new sigs-out sigs-inout sigs-in
7983 nil nil nil nil nil nil))
7984 ;; Pop from varstack to restore state to pre-clocking
7985 (setq tmp (car varstack)
7986 varstack (cdr varstack)
7987 sigs-out (aref tmp 0)
7988 sigs-inout (aref tmp 1)
7989 sigs-in (aref tmp 2)))
7990 (setq vec nil io nil expect-signal nil newsig nil paren 0 rvalue nil
7991 v2kargs-ok nil in-modport nil ign-prop nil)
7993 ((eq ?= (following-char))
7994 (setq rvalue t newsig nil)
7996 ((and (eq ?, (following-char))
7997 (eq paren sig-paren))
8000 ;; ,'s can occur inside {} & funcs
8001 ((looking-at "[{(]")
8002 (setq paren (1+ paren))
8004 ((looking-at "[})]")
8005 (setq paren (1- paren))
8007 (when (< paren sig-paren)
8008 (setq expect-signal nil))) ; ) that ends variables inside v2k arg list
8009 ((looking-at "\\s-*\\(\\[[^]]+\\]\\)")
8010 (goto-char (match-end 0))
8011 (cond (newsig ; Memory, not just width. Patch last signal added's memory (nth 3)
8012 (setcar (cdr (cdr (cdr newsig)))
8013 (if (verilog-sig-memory newsig)
8014 (concat (verilog-sig-memory newsig) (match-string 1))
8016 (vec ;; Multidimensional
8017 (setq multidim (cons vec multidim))
8018 (setq vec (verilog-string-replace-matches
8019 "\\s-+" "" nil nil (match-string 1))))
8021 (setq vec (verilog-string-replace-matches
8022 "\\s-+" "" nil nil (match-string 1))))))
8023 ;; Normal or escaped identifier -- note we remember the \ if escaped
8024 ((looking-at "\\s-*\\([a-zA-Z0-9`_$]+\\|\\\\[^ \t\n\f]+\\)")
8025 (goto-char (match-end 0))
8026 (setq keywd (match-string 1))
8027 (when (string-match "^\\\\" (match-string 1))
8028 (setq keywd (concat keywd " "))) ;; Escaped ID needs space at end
8029 ;; Add any :: package names to same identifier
8030 (while (looking-at "\\s-*::\\s-*\\([a-zA-Z0-9`_$]+\\|\\\\[^ \t\n\f]+\\)")
8031 (goto-char (match-end 0))
8032 (setq keywd (concat keywd "::" (match-string 1)))
8033 (when (string-match "^\\\\" (match-string 1))
8034 (setq keywd (concat keywd " ")))) ;; Escaped ID needs space at end
8035 (cond ((equal keywd "input")
8036 (setq vec nil enum nil rvalue nil newsig nil signed nil
8037 typedefed nil multidim nil ptype nil modport nil
8038 expect-signal 'sigs-in io t sig-paren paren))
8039 ((equal keywd "output")
8040 (setq vec nil enum nil rvalue nil newsig nil signed nil
8041 typedefed nil multidim nil ptype nil modport nil
8042 expect-signal 'sigs-out io t sig-paren paren))
8043 ((equal keywd "inout")
8044 (setq vec nil enum nil rvalue nil newsig nil signed nil
8045 typedefed nil multidim nil ptype nil modport nil
8046 expect-signal 'sigs-inout io t sig-paren paren))
8047 ((equal keywd "parameter")
8048 (setq vec nil enum nil rvalue nil signed nil
8049 typedefed nil multidim nil ptype nil modport nil
8050 expect-signal 'sigs-gparam io t sig-paren paren))
8051 ((member keywd '("wire" "reg" ; Fast
8053 "tri" "tri0" "tri1" "triand" "trior" "trireg"
8054 "uwire" "wand" "wor"
8055 ;; integer_atom_type
8056 "byte" "shortint" "int" "longint" "integer" "time"
8058 ;; integer_vector_type - "reg" above
8061 "shortreal" "real" "realtime"
8063 "string" "event" "chandle"))
8066 (if typedefed (concat typedefed " " keywd) keywd)))
8067 (t (setq vec nil enum nil rvalue nil signed nil
8068 typedefed nil multidim nil sig-paren paren
8069 expect-signal 'sigs-var modport nil))))
8070 ((equal keywd "assign")
8071 (setq vec nil enum nil rvalue nil signed nil
8072 typedefed nil multidim nil ptype nil modport nil
8073 expect-signal 'sigs-assign sig-paren paren))
8074 ((member keywd '("localparam" "genvar"))
8076 (setq vec nil enum nil rvalue nil signed nil
8077 typedefed nil multidim nil ptype nil modport nil
8078 expect-signal 'sigs-const sig-paren paren)))
8079 ((member keywd '("signed" "unsigned"))
8080 (setq signed keywd))
8081 ((member keywd '("assert" "assume" "cover" "expect" "restrict"))
8083 ((member keywd '("class" "covergroup" "function"
8084 "property" "randsequence" "sequence" "task"))
8086 (setq functask (1+ functask))))
8087 ((member keywd '("endclass" "endgroup" "endfunction"
8088 "endproperty" "endsequence" "endtask"))
8089 (setq functask (1- functask)))
8090 ((equal keywd "modport")
8091 (setq in-modport t))
8092 ((equal keywd "clocking")
8093 (setq in-clocking t))
8094 ((equal keywd "type")
8096 ;; Ifdef? Ignore name of define
8097 ((member keywd '("`ifdef" "`ifndef" "`elsif"))
8101 (verilog-typedef-name-p keywd))
8102 (setq typedefed keywd))
8103 ;; Interface with optional modport in v2k arglist?
8104 ;; Skip over parsing modport, and take the interface name as the type
8108 (looking-at "\\s-*\\(\\.\\(\\s-*[a-zA-Z`_$][a-zA-Z0-9`_$]*\\)\\|\\)\\s-*[a-zA-Z`_$][a-zA-Z0-9`_$]*"))
8109 (when (match-end 2) (goto-char (match-end 2)))
8110 (setq vec nil enum nil rvalue nil signed nil
8111 typedefed keywd multidim nil ptype nil modport (match-string 2)
8112 newsig nil sig-paren paren
8113 expect-signal 'sigs-intf io t ))
8114 ;; Ignore dotted LHS assignments: "assign foo.bar = z;"
8115 ((looking-at "\\s-*\\.")
8116 (goto-char (match-end 0))
8118 (setq expect-signal nil)))
8119 ;; "modport <keywd>"
8120 ((and (eq in-modport t)
8121 (not (member keywd verilog-keywords)))
8122 (setq in-modport (verilog-modport-new keywd nil nil))
8123 (setq sigs-modports (cons in-modport sigs-modports))
8124 ;; Push old sig values to stack and point to new signal list
8125 (setq varstack (cons (vector sigs-out sigs-inout sigs-in)
8127 (setq sigs-in nil sigs-inout nil sigs-out nil))
8128 ;; "modport x (clocking <keywd>)"
8129 ((and in-modport in-clocking)
8130 (verilog-modport-clockings-add in-modport keywd)
8131 (setq in-clocking nil))
8134 (equal keywd "endclocking"))
8135 (unless (eq in-clocking t)
8136 (verilog-modport-decls-set
8138 (verilog-decls-new sigs-out sigs-inout sigs-in
8139 nil nil nil nil nil nil))
8140 ;; Pop from varstack to restore state to pre-clocking
8141 (setq tmp (car varstack)
8142 varstack (cdr varstack)
8143 sigs-out (aref tmp 0)
8144 sigs-inout (aref tmp 1)
8145 sigs-in (aref tmp 2)))
8146 (setq in-clocking nil))
8147 ;; "clocking <keywd>"
8148 ((and (eq in-clocking t)
8149 (not (member keywd verilog-keywords)))
8150 (setq in-clocking (verilog-modport-new keywd nil nil))
8151 (setq sigs-modports (cons in-clocking sigs-modports))
8152 ;; Push old sig values to stack and point to new signal list
8153 (setq varstack (cons (vector sigs-out sigs-inout sigs-in)
8155 (setq sigs-in nil sigs-inout nil sigs-out nil))
8156 ;; New signal, maybe?
8160 (not (member keywd verilog-keywords)))
8161 ;; Add new signal to expect-signal's variable
8162 (setq newsig (verilog-sig-new keywd vec nil nil enum signed typedefed multidim modport))
8163 (set expect-signal (cons newsig
8164 (symbol-value expect-signal))))))
8167 (skip-syntax-forward " "))
8169 (setq tmp (verilog-decls-new (nreverse sigs-out)
8170 (nreverse sigs-inout)
8173 (nreverse sigs-modports)
8174 (nreverse sigs-assign)
8175 (nreverse sigs-const)
8176 (nreverse sigs-gparam)
8177 (nreverse sigs-intf)))
8178 ;;(if dbg (verilog-decls-princ tmp))
8181 (defvar verilog-read-sub-decls-in-interfaced nil
8182 "For `verilog-read-sub-decls', process next signal as under interfaced block.")
8184 (defvar verilog-read-sub-decls-gate-ios nil
8185 "For `verilog-read-sub-decls', gate IO pins remaining, nil if non-primitive.")
8188 ;; Prevent compile warnings; these are let's, not globals
8189 ;; Do not remove the eval-when-compile
8190 ;; - we want an error when we are debugging this code if they are refed.
8195 (defvar sigs-intfd))
8197 (defun verilog-read-sub-decls-sig (submoddecls comment port sig vec multidim)
8198 "For `verilog-read-sub-decls-line', add a signal."
8199 ;; sig eq t to indicate .name syntax
8200 ;;(message "vrsds: %s(%S)" port sig)
8201 (let ((dotname (eq sig t))
8204 (setq port (verilog-symbol-detick-denumber port))
8205 (setq sig (if dotname port (verilog-symbol-detick-denumber sig)))
8206 (if vec (setq vec (verilog-symbol-detick-denumber vec)))
8207 (if multidim (setq multidim (mapcar `verilog-symbol-detick-denumber multidim)))
8208 (unless (or (not sig)
8209 (equal sig "")) ;; Ignore .foo(1'b1) assignments
8210 (cond ((or (setq portdata (assoc port (verilog-decls-get-inouts submoddecls)))
8211 (equal "inout" verilog-read-sub-decls-gate-ios))
8213 (cons (verilog-sig-new
8215 (if dotname (verilog-sig-bits portdata) vec)
8216 (concat "To/From " comment)
8217 (verilog-sig-memory portdata)
8219 (verilog-sig-signed portdata)
8220 (unless (member (verilog-sig-type portdata) '("wire" "reg"))
8221 (verilog-sig-type portdata))
8224 ((or (setq portdata (assoc port (verilog-decls-get-outputs submoddecls)))
8225 (equal "output" verilog-read-sub-decls-gate-ios))
8227 (cons (verilog-sig-new
8229 (if dotname (verilog-sig-bits portdata) vec)
8230 (concat "From " comment)
8231 (verilog-sig-memory portdata)
8233 (verilog-sig-signed portdata)
8234 ;; Though ok in SV, in V2K code, propagating the
8235 ;; "reg" in "output reg" upwards isn't legal.
8236 ;; Also for backwards compatibility we don't propagate
8237 ;; "input wire" upwards.
8238 ;; See also `verilog-signals-edit-wire-reg'.
8239 (unless (member (verilog-sig-type portdata) '("wire" "reg"))
8240 (verilog-sig-type portdata))
8243 ((or (setq portdata (assoc port (verilog-decls-get-inputs submoddecls)))
8244 (equal "input" verilog-read-sub-decls-gate-ios))
8246 (cons (verilog-sig-new
8248 (if dotname (verilog-sig-bits portdata) vec)
8249 (concat "To " comment)
8250 (verilog-sig-memory portdata)
8252 (verilog-sig-signed portdata)
8253 (unless (member (verilog-sig-type portdata) '("wire" "reg"))
8254 (verilog-sig-type portdata))
8257 ((setq portdata (assoc port (verilog-decls-get-interfaces submoddecls)))
8259 (cons (verilog-sig-new
8261 (if dotname (verilog-sig-bits portdata) vec)
8262 (concat "To/From " comment)
8263 (verilog-sig-memory portdata)
8265 (verilog-sig-signed portdata)
8266 (verilog-sig-type portdata)
8269 ((setq portdata (and verilog-read-sub-decls-in-interfaced
8270 (assoc port (verilog-decls-get-vars submoddecls))))
8272 (cons (verilog-sig-new
8274 (if dotname (verilog-sig-bits portdata) vec)
8275 (concat "To/From " comment)
8276 (verilog-sig-memory portdata)
8278 (verilog-sig-signed portdata)
8279 (verilog-sig-type portdata)
8282 ;; (t -- warning pin isn't defined.) ; Leave for lint tool
8285 (defun verilog-read-sub-decls-expr (submoddecls comment port expr)
8286 "For `verilog-read-sub-decls-line', parse a subexpression and add signals."
8287 ;;(message "vrsde: '%s'" expr)
8288 ;; Replace special /*[....]*/ comments inserted by verilog-auto-inst-port
8289 (setq expr (verilog-string-replace-matches "/\\*\\(\\[[^*]+\\]\\)\\*/" "\\1" nil nil expr))
8290 ;; Remove front operators
8291 (setq expr (verilog-string-replace-matches "^\\s-*[---+~!|&]+\\s-*" "" nil nil expr))
8294 ;; {..., a, b} requires us to recurse on a,b
8295 ;; To support {#{},{#{a,b}} we'll just split everything on [{},]
8296 ((string-match "^\\s-*{\\(.*\\)}\\s-*$" expr)
8297 (unless verilog-auto-ignore-concat
8298 (let ((mlst (split-string (match-string 1 expr) "[{},]"))
8300 (while (setq mstr (pop mlst))
8301 (verilog-read-sub-decls-expr submoddecls comment port mstr)))))
8303 (let (sig vec multidim)
8304 ;; Remove leading reduction operators, etc
8305 (setq expr (verilog-string-replace-matches "^\\s-*[---+~!|&]+\\s-*" "" nil nil expr))
8306 ;;(message "vrsde-ptop: '%s'" expr)
8307 (cond ;; Find \signal. Final space is part of escaped signal name
8308 ((string-match "^\\s-*\\(\\\\[^ \t\n\f]+\\s-\\)" expr)
8309 ;;(message "vrsde-s: '%s'" (match-string 1 expr))
8310 (setq sig (match-string 1 expr)
8311 expr (substring expr (match-end 0))))
8313 ((string-match "^\\s-*\\([a-zA-Z_][a-zA-Z_0-9]*\\)" expr)
8314 ;;(message "vrsde-s: '%s'" (match-string 1 expr))
8315 (setq sig (verilog-string-remove-spaces (match-string 1 expr))
8316 expr (substring expr (match-end 0)))))
8317 ;; Find [vector] or [multi][multi][multi][vector]
8318 (while (string-match "^\\s-*\\(\\[[^]]+\\]\\)" expr)
8319 ;;(message "vrsde-v: '%s'" (match-string 1 expr))
8320 (when vec (setq multidim (cons vec multidim)))
8321 (setq vec (match-string 1 expr)
8322 expr (substring expr (match-end 0))))
8323 ;; If found signal, and nothing unrecognized, add the signal
8324 ;;(message "vrsde-rem: '%s'" expr)
8325 (when (and sig (string-match "^\\s-*$" expr))
8326 (verilog-read-sub-decls-sig submoddecls comment port sig vec multidim))))))
8328 (defun verilog-read-sub-decls-line (submoddecls comment)
8329 "For `verilog-read-sub-decls', read lines of port defs until none match.
8330 Inserts the list of signals found, using submodi to look up each port."
8336 (cond ((looking-at "\\s-*\\.\\s-*\\([a-zA-Z0-9`_$]*\\)\\s-*(\\s-*")
8337 (setq port (match-string 1))
8338 (goto-char (match-end 0)))
8340 ((looking-at "\\s-*\\.\\s-*\\(\\\\[^ \t\n\f]*\\)\\s-*(\\s-*")
8341 (setq port (concat (match-string 1) " ")) ;; escaped id's need trailing space
8342 (goto-char (match-end 0)))
8344 ((looking-at "\\s-*\\.\\s-*\\([a-zA-Z0-9`_$]*\\)\\s-*[,)/]")
8345 (verilog-read-sub-decls-sig
8346 submoddecls comment (match-string 1) t ; sig==t for .name
8347 nil nil) ; vec multidim
8350 ((looking-at "\\s-*\\.\\s-*\\(\\\\[^ \t\n\f]*\\)\\s-*[,)/]")
8351 (verilog-read-sub-decls-sig
8352 submoddecls comment (concat (match-string 1) " ") t ; sig==t for .name
8353 nil nil) ; vec multidim
8356 ((looking-at "\\s-*\\.[^(]*(")
8357 (setq port nil) ;; skip this line
8358 (goto-char (match-end 0)))
8360 (setq port nil done t))) ;; Unknown, ignore rest of line
8361 ;; Get signal name. Point is at the first-non-space after (
8362 ;; We intentionally ignore (non-escaped) signals with .s in them
8363 ;; this prevents AUTOWIRE etc from noticing hierarchical sigs.
8365 (cond ((looking-at "\\([a-zA-Z_][a-zA-Z_0-9]*\\)\\s-*)")
8366 (verilog-read-sub-decls-sig
8367 submoddecls comment port
8368 (verilog-string-remove-spaces (match-string 1)) ; sig
8369 nil nil)) ; vec multidim
8371 ((looking-at "\\([a-zA-Z_][a-zA-Z_0-9]*\\)\\s-*\\(\\[[^]]+\\]\\)\\s-*)")
8372 (verilog-read-sub-decls-sig
8373 submoddecls comment port
8374 (verilog-string-remove-spaces (match-string 1)) ; sig
8375 (match-string 2) nil)) ; vec multidim
8376 ;; Fastpath was above looking-at's.
8377 ;; For something more complicated invoke a parser
8378 ((looking-at "[^)]+")
8379 (verilog-read-sub-decls-expr
8380 submoddecls comment port
8382 (point) (1- (progn (search-backward "(") ; start at (
8383 (verilog-forward-sexp-ign-cmt 1)
8384 (point)))))))) ; expr
8386 (forward-line 1)))))
8388 (defun verilog-read-sub-decls-gate (submoddecls comment submod end-inst-point)
8389 "For `verilog-read-sub-decls', read lines of UDP gate decl until none match.
8390 Inserts the list of signals found."
8392 (let ((iolist (cdr (assoc submod verilog-gate-ios))))
8393 (while (< (point) end-inst-point)
8394 ;; Get primitive's signal name, as will never have port, and no trailing )
8395 (cond ((looking-at "//")
8396 (search-forward "\n"))
8397 ((looking-at "/\\*")
8398 (or (search-forward "*/")
8399 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
8400 ((looking-at "(\\*")
8401 ;; To advance past either "(*)" or "(* ... *)" don't forward past first *
8403 (or (search-forward "*)")
8404 (error "%s: Unmatched (* *), at char %d" (verilog-point-text) (point))))
8405 ;; On pins, parse and advance to next pin
8406 ;; Looking at pin, but *not* an // Output comment, or ) to end the inst
8407 ((looking-at "\\s-*[a-zA-Z0-9`_$({}\\\\][^,]*")
8408 (goto-char (match-end 0))
8409 (setq verilog-read-sub-decls-gate-ios (or (car iolist) "input")
8410 iolist (cdr iolist))
8411 (verilog-read-sub-decls-expr
8412 submoddecls comment "primitive_port"
8416 (skip-syntax-forward " ")))))))
8418 (defun verilog-read-sub-decls ()
8419 "Internally parse signals going to modules under this module.
8420 Return an array of [ outputs inouts inputs ] signals for modules that are
8421 instantiated in this module. For example if declare A A (.B(SIG)) and SIG
8422 is an output, then SIG will be included in the list.
8424 This only works on instantiations created with /*AUTOINST*/ converted by
8425 \\[verilog-auto-inst]. Otherwise, it would have to read in the whole
8426 component library to determine connectivity of the design.
8428 One work around for this problem is to manually create // Inputs and //
8429 Outputs comments above subcell signals, for example:
8437 (let ((end-mod-point (verilog-get-end-of-defun t))
8438 st-point end-inst-point
8439 ;; below 3 modified by verilog-read-sub-decls-line
8440 sigs-out sigs-inout sigs-in sigs-intf sigs-intfd)
8441 (verilog-beg-of-defun-quick)
8442 (while (verilog-re-search-forward-quick "\\(/\\*AUTOINST\\*/\\|\\.\\*\\)" end-mod-point t)
8444 (goto-char (match-beginning 0))
8445 (unless (verilog-inside-comment-or-string-p)
8446 ;; Attempt to snarf a comment
8447 (let* ((submod (verilog-read-inst-module))
8448 (inst (verilog-read-inst-name))
8449 (subprim (member submod verilog-gate-keywords))
8450 (comment (concat inst " of " submod ".v"))
8451 submodi submoddecls)
8454 (setq submodi `primitive
8455 submoddecls (verilog-decls-new nil nil nil nil nil nil nil nil nil)
8456 comment (concat inst " of " submod))
8457 (verilog-backward-open-paren)
8458 (setq end-inst-point (save-excursion (verilog-forward-sexp-ign-cmt 1)
8462 (verilog-read-sub-decls-gate submoddecls comment submod end-inst-point))
8465 (when (setq submodi (verilog-modi-lookup submod t))
8466 (setq submoddecls (verilog-modi-get-decls submodi)
8467 verilog-read-sub-decls-gate-ios nil)
8468 (verilog-backward-open-paren)
8469 (setq end-inst-point (save-excursion (verilog-forward-sexp-ign-cmt 1)
8472 ;; This could have used a list created by verilog-auto-inst
8473 ;; However I want it to be runnable even on user's manually added signals
8474 (let ((verilog-read-sub-decls-in-interfaced t))
8475 (while (re-search-forward "\\s *(?\\s *// Interfaced" end-inst-point t)
8476 (verilog-read-sub-decls-line submoddecls comment))) ;; Modifies sigs-ifd
8477 (goto-char st-point)
8478 (while (re-search-forward "\\s *(?\\s *// Interfaces" end-inst-point t)
8479 (verilog-read-sub-decls-line submoddecls comment)) ;; Modifies sigs-out
8480 (goto-char st-point)
8481 (while (re-search-forward "\\s *(?\\s *// Outputs" end-inst-point t)
8482 (verilog-read-sub-decls-line submoddecls comment)) ;; Modifies sigs-out
8483 (goto-char st-point)
8484 (while (re-search-forward "\\s *(?\\s *// Inouts" end-inst-point t)
8485 (verilog-read-sub-decls-line submoddecls comment)) ;; Modifies sigs-inout
8486 (goto-char st-point)
8487 (while (re-search-forward "\\s *(?\\s *// Inputs" end-inst-point t)
8488 (verilog-read-sub-decls-line submoddecls comment)) ;; Modifies sigs-in
8490 ;; Combine duplicate bits
8491 ;;(setq rr (vector sigs-out sigs-inout sigs-in))
8492 (verilog-subdecls-new
8493 (verilog-signals-combine-bus (nreverse sigs-out))
8494 (verilog-signals-combine-bus (nreverse sigs-inout))
8495 (verilog-signals-combine-bus (nreverse sigs-in))
8496 (verilog-signals-combine-bus (nreverse sigs-intf))
8497 (verilog-signals-combine-bus (nreverse sigs-intfd))))))
8499 (defun verilog-read-inst-pins ()
8500 "Return an array of [ pins ] for the current instantiation at point.
8501 For example if declare A A (.B(SIG)) then B will be included in the list."
8503 (let ((end-mod-point (point)) ;; presume at /*AUTOINST*/ point
8505 (verilog-backward-open-paren)
8506 (while (re-search-forward "\\.\\([^(,) \t\n\f]*\\)\\s-*" end-mod-point t)
8507 (setq pin (match-string 1))
8508 (unless (verilog-inside-comment-or-string-p)
8509 (setq pins (cons (list pin) pins))
8510 (when (looking-at "(")
8511 (verilog-forward-sexp-ign-cmt 1))))
8514 (defun verilog-read-arg-pins ()
8515 "Return an array of [ pins ] for the current argument declaration at point."
8517 (let ((end-mod-point (point)) ;; presume at /*AUTOARG*/ point
8519 (verilog-backward-open-paren)
8520 (while (re-search-forward "\\([a-zA-Z0-9$_.%`]+\\)" end-mod-point t)
8521 (setq pin (match-string 1))
8522 (unless (verilog-inside-comment-or-string-p)
8523 (setq pins (cons (list pin) pins))))
8526 (defun verilog-read-auto-constants (beg end-mod-point)
8527 "Return a list of AUTO_CONSTANTs used in the region from BEG to END-MOD-POINT."
8530 (let (sig-list tpl-end-pt)
8532 (while (re-search-forward "\\<AUTO_CONSTANT" end-mod-point t)
8533 (if (not (looking-at "\\s *("))
8534 (error "%s: Missing () after AUTO_CONSTANT" (verilog-point-text)))
8535 (search-forward "(" end-mod-point)
8536 (setq tpl-end-pt (save-excursion
8538 (verilog-forward-sexp-cmt 1) ;; Moves to paren that closes argdecl's
8541 (while (re-search-forward "\\s-*\\([\"a-zA-Z0-9$_.%`]+\\)\\s-*,*" tpl-end-pt t)
8542 (setq sig-list (cons (list (match-string 1) nil nil) sig-list))))
8545 (defvar verilog-cache-has-lisp nil "True if any AUTO_LISP in buffer.")
8546 (make-variable-buffer-local 'verilog-cache-has-lisp)
8548 (defun verilog-read-auto-lisp-present ()
8549 "Set `verilog-cache-has-lisp' if any AUTO_LISP in this buffer."
8551 (goto-char (point-min))
8552 (setq verilog-cache-has-lisp (re-search-forward "\\<AUTO_LISP(" nil t))))
8554 (defun verilog-read-auto-lisp (start end)
8555 "Look for and evaluate an AUTO_LISP between START and END.
8556 Must call `verilog-read-auto-lisp-present' before this function."
8557 ;; This function is expensive for large buffers, so we cache if any AUTO_LISP exists
8558 (when verilog-cache-has-lisp
8561 (while (re-search-forward "\\<AUTO_LISP(" end t)
8563 (let* ((beg-pt (prog1 (point)
8564 (verilog-forward-sexp-cmt 1))) ;; Closing paren
8566 (verilog-in-hooks t))
8567 (eval-region beg-pt end-pt nil))))))
8570 ;; Prevent compile warnings; these are let's, not globals
8571 ;; Do not remove the eval-when-compile
8572 ;; - we want an error when we are debugging this code if they are refed.
8576 (defvar sigs-out-unk)
8578 (defvar vector-skip-list))
8580 (defun verilog-read-always-signals-recurse
8581 (exit-keywd rvalue temp-next)
8582 "Recursive routine for parentheses/bracket matching.
8583 EXIT-KEYWD is expression to stop at, nil if top level.
8584 RVALUE is true if at right hand side of equal.
8585 IGNORE-NEXT is true to ignore next token, fake from inside case statement."
8586 (let* ((semi-rvalue (equal "endcase" exit-keywd)) ;; true if after a ; we are looking for rvalue
8587 keywd last-keywd sig-tolk sig-last-tolk gotend got-sig got-list end-else-check
8589 ;;(if dbg (setq dbg (concat dbg (format "Recursion %S %S %S\n" exit-keywd rvalue temp-next))))
8590 (while (not (or (eobp) gotend))
8593 (search-forward "\n"))
8594 ((looking-at "/\\*")
8595 (or (search-forward "*/")
8596 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
8597 ((looking-at "(\\*")
8598 ;; To advance past either "(*)" or "(* ... *)" don't forward past first *
8600 (or (search-forward "*)")
8601 (error "%s: Unmatched (* *), at char %d" (verilog-point-text) (point))))
8602 (t (setq keywd (buffer-substring-no-properties
8604 (save-excursion (when (eq 0 (skip-chars-forward "a-zA-Z0-9$_.%`"))
8607 sig-last-tolk sig-tolk
8609 ;;(if dbg (setq dbg (concat dbg (format "\tPt=%S %S\trv=%S in=%S ee=%S gs=%S\n" (point) keywd rvalue ignore-next end-else-check got-sig))))
8612 (or (re-search-forward "[^\\]\"" nil t)
8613 (error "%s: Unmatched quotes, at char %d" (verilog-point-text) (point))))
8614 ;; else at top level loop, keep parsing
8615 ((and end-else-check (equal keywd "else"))
8616 ;;(if dbg (setq dbg (concat dbg (format "\tif-check-else %s\n" keywd))))
8617 ;; no forward movement, want to see else in lower loop
8618 (setq end-else-check nil))
8619 ;; End at top level loop
8620 ((and end-else-check (looking-at "[^ \t\n\f]"))
8621 ;;(if dbg (setq dbg (concat dbg (format "\tif-check-else-other %s\n" keywd))))
8624 ((and exit-keywd (equal keywd exit-keywd))
8626 (forward-char (length keywd)))
8627 ;; Standard tokens...
8629 (setq ignore-next nil rvalue semi-rvalue)
8630 ;; Final statement at top level loop?
8631 (when (not exit-keywd)
8632 ;;(if dbg (setq dbg (concat dbg (format "\ttop-end-check %s\n" keywd))))
8633 (setq end-else-check t))
8636 (if (looking-at "'[sS]?[hdxboHDXBO]?[ \t]*[0-9a-fA-F_xzXZ?]+")
8637 (goto-char (match-end 0))
8639 ((equal keywd ":") ;; Case statement, begin/end label, x?y:z
8640 (cond ((equal "endcase" exit-keywd) ;; case x: y=z; statement next
8641 (setq ignore-next nil rvalue nil))
8642 ((equal "?" exit-keywd) ;; x?y:z rvalue
8644 ((equal "]" exit-keywd) ;; [x:y] rvalue
8646 (got-sig ;; label: statement
8647 (setq ignore-next nil rvalue semi-rvalue got-sig nil))
8648 ((not rvalue) ;; begin label
8649 (setq ignore-next t rvalue nil)))
8653 ;;(if dbg (setq dbg (concat dbg (format "\t\tequal got-sig=%S got-list=%s\n" got-sig got-list))))
8654 (set got-list (cons got-sig (symbol-value got-list)))
8657 (if (eq (char-before) ?< )
8658 (setq sigs-out-d (append sigs-out-d sigs-out-unk)
8660 (setq sigs-out-i (append sigs-out-i sigs-out-unk)
8662 (setq ignore-next nil rvalue t)
8666 (verilog-read-always-signals-recurse ":" rvalue nil))
8669 (verilog-read-always-signals-recurse "]" t nil))
8672 (cond (sig-last-tolk ;; Function call; zap last signal
8673 (setq got-sig nil)))
8674 (cond ((equal last-keywd "for")
8675 ;; temp-next: Variables on LHS are lvalues, but generally we want
8676 ;; to ignore them, assuming they are loop increments
8677 (verilog-read-always-signals-recurse ";" nil t)
8678 (verilog-read-always-signals-recurse ";" t nil)
8679 (verilog-read-always-signals-recurse ")" nil nil))
8680 (t (verilog-read-always-signals-recurse ")" t nil))))
8681 ((equal keywd "begin")
8682 (skip-syntax-forward "w_")
8683 (verilog-read-always-signals-recurse "end" nil nil)
8684 ;;(if dbg (setq dbg (concat dbg (format "\tgot-end %s\n" exit-keywd))))
8685 (setq ignore-next nil rvalue semi-rvalue)
8686 (if (not exit-keywd) (setq end-else-check t)))
8687 ((member keywd '("case" "casex" "casez"))
8688 (skip-syntax-forward "w_")
8689 (verilog-read-always-signals-recurse "endcase" t nil)
8690 (setq ignore-next nil rvalue semi-rvalue)
8691 (if (not exit-keywd) (setq gotend t))) ;; top level begin/end
8692 ((string-match "^[$`a-zA-Z_]" keywd) ;; not exactly word constituent
8693 (cond ((member keywd '("`ifdef" "`ifndef" "`elsif"))
8694 (setq ignore-next t))
8696 (member keywd verilog-keywords)
8697 (string-match "^\\$" keywd)) ;; PLI task
8698 (setq ignore-next nil))
8700 (setq keywd (verilog-symbol-detick-denumber keywd))
8702 (set got-list (cons got-sig (symbol-value got-list)))
8703 ;;(if dbg (setq dbg (concat dbg (format "\t\tgot-sig=%S got-list=%S\n" got-sig got-list))))
8705 (setq got-list (cond (temp-next 'sigs-temp)
8708 got-sig (if (or (not keywd)
8709 (assoc keywd (symbol-value got-list)))
8710 nil (list keywd nil nil))
8713 (skip-chars-forward "a-zA-Z0-9$_.%`"))
8716 ;; End of non-comment token
8717 (setq last-keywd keywd)))
8718 (skip-syntax-forward " "))
8719 ;; Append the final pending signal
8721 ;;(if dbg (setq dbg (concat dbg (format "\t\tfinal got-sig=%S got-list=%s\n" got-sig got-list))))
8722 (set got-list (cons got-sig (symbol-value got-list)))
8724 ;;(if dbg (setq dbg (concat dbg (format "ENDRecursion %s\n" exit-keywd))))
8727 (defun verilog-read-always-signals ()
8728 "Parse always block at point and return list of (outputs inout inputs)."
8731 sigs-out-d sigs-out-i sigs-out-unk sigs-temp sigs-in)
8732 (search-forward ")")
8733 (verilog-read-always-signals-recurse nil nil nil)
8734 (setq sigs-out-i (append sigs-out-i sigs-out-unk)
8736 ;;(if dbg (with-current-buffer (get-buffer-create "*vl-dbg*")) (delete-region (point-min) (point-max)) (insert dbg) (setq dbg ""))
8737 ;; Return what was found
8738 (verilog-alw-new sigs-out-d sigs-out-i sigs-temp sigs-in))))
8740 (defun verilog-read-instants ()
8741 "Parse module at point and return list of ( ( file instance ) ... )."
8742 (verilog-beg-of-defun-quick)
8743 (let* ((end-mod-point (verilog-get-end-of-defun t))
8745 (instants-list nil))
8747 (while (< (point) end-mod-point)
8748 ;; Stay at level 0, no comments
8750 (setq state (parse-partial-sexp (point) end-mod-point 0 t nil))
8751 (or (> (car state) 0) ; in parens
8752 (nth 5 state) ; comment
8756 (if (looking-at "^\\s-*\\([a-zA-Z0-9`_$]+\\)\\s-+\\([a-zA-Z0-9`_$]+\\)\\s-*(")
8757 ;;(if (looking-at "^\\(.+\\)$")
8758 (let ((module (match-string 1))
8759 (instant (match-string 2)))
8760 (if (not (member module verilog-keywords))
8761 (setq instants-list (cons (list module instant) instants-list)))))
8766 (defun verilog-read-auto-template-middle ()
8767 "With point in middle of an AUTO_TEMPLATE, parse it.
8768 Returns REGEXP and list of ( (signal_name connection_name)... )."
8771 (let ((tpl-regexp "\\([0-9]+\\)")
8772 (lineno -1) ; -1 to offset for the AUTO_TEMPLATE's newline
8774 tpl-sig-list tpl-wild-list tpl-end-pt rep)
8776 ;; We reserve @"..." for future lisp expressions that evaluate
8777 ;; once-per-AUTOINST
8778 (when (looking-at "\\s-*\"\\([^\"]*\\)\"")
8779 (setq tpl-regexp (match-string 1))
8780 (goto-char (match-end 0)))
8781 (search-forward "(")
8782 ;; Parse lines in the template
8783 (when (or verilog-auto-inst-template-numbers
8784 verilog-auto-template-warn-unused)
8786 (let ((pre-pt (point)))
8787 (goto-char (point-min))
8788 (while (search-forward "AUTO_TEMPLATE" pre-pt t)
8789 (setq templateno (1+ templateno)))
8790 (while (< (point) pre-pt)
8792 (setq lineno (1+ lineno))))))
8793 (setq tpl-end-pt (save-excursion
8795 (verilog-forward-sexp-cmt 1) ;; Moves to paren that closes argdecl's
8799 (while (< (point) tpl-end-pt)
8800 (cond ((looking-at "\\s-*\\.\\([a-zA-Z0-9`_$]+\\)\\s-*(\\(.*\\))\\s-*\\(,\\|)\\s-*;\\)")
8803 (match-string-no-properties 1)
8804 (match-string-no-properties 2)
8807 (goto-char (match-end 0)))
8810 ;; Regexp bug in XEmacs disallows ][ inside [], and wants + last
8811 "\\s-*\\.\\(\\([a-zA-Z0-9`_$+@^.*?|---]+\\|[][]\\|\\\\[()|]\\)+\\)\\s-*(\\(.*\\))\\s-*\\(,\\|)\\s-*;\\)")
8812 (setq rep (match-string-no-properties 3))
8813 (goto-char (match-end 0))
8817 (verilog-string-replace-matches "@" "\\\\([0-9]+\\\\)" nil nil
8823 ((looking-at "[ \t\f]+")
8824 (goto-char (match-end 0)))
8826 (setq lineno (1+ lineno))
8827 (goto-char (match-end 0)))
8829 (search-forward "\n")
8830 (setq lineno (1+ lineno)))
8831 ((looking-at "/\\*")
8833 (or (search-forward "*/")
8834 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
8836 (error "%s: AUTO_TEMPLATE parsing error: %s"
8837 (verilog-point-text)
8838 (progn (looking-at ".*$") (match-string 0))))))
8841 (list tpl-sig-list tpl-wild-list)))))
8843 (defun verilog-read-auto-template (module)
8844 "Look for an auto_template for the instantiation of the given MODULE.
8845 If found returns `verilog-read-auto-template-inside' structure."
8849 ;; Note this search is expensive, as we hunt from mod-begin to point
8850 ;; for every instantiation. Likewise in verilog-read-auto-lisp.
8851 ;; So, we look first for an exact string rather than a slow regexp.
8852 ;; Someday we may keep a cache of every template, but this would also
8853 ;; need to record the relative position of each AUTOINST, as multiple
8854 ;; templates exist for each module, and we're inserting lines.
8856 ;; See also regexp in `verilog-auto-template-lint'
8857 (verilog-re-search-backward-substr
8859 (concat "^\\s-*/?\\*?\\s-*" module "\\s-+AUTO_TEMPLATE") nil t)
8860 ;; Also try forward of this AUTOINST
8861 ;; This is for historical support; this isn't speced as working
8864 (verilog-re-search-forward-substr
8866 (concat "^\\s-*/?\\*?\\s-*" module "\\s-+AUTO_TEMPLATE") nil t)))
8867 (goto-char (match-end 0))
8868 (verilog-read-auto-template-middle))
8869 ;; If no template found
8870 (t (vector "" nil))))))
8871 ;;(progn (find-file "auto-template.v") (verilog-read-auto-template "ptl_entry"))
8873 (defvar verilog-auto-template-hits nil "Successful lookups with `verilog-read-auto-template-hit'.")
8874 (make-variable-buffer-local 'verilog-auto-template-hits)
8876 (defun verilog-read-auto-template-hit (tpl-ass)
8877 "Record that TPL-ASS template from `verilog-read-auto-template' was used."
8878 (when (eval-when-compile (fboundp 'make-hash-table)) ;; else feature not allowed
8879 (when verilog-auto-template-warn-unused
8880 (unless verilog-auto-template-hits
8881 (setq verilog-auto-template-hits
8882 (make-hash-table :test 'equal :rehash-size 4.0)))
8883 (puthash (vector (nth 2 tpl-ass) (nth 3 tpl-ass)) t
8884 verilog-auto-template-hits))))
8886 (defun verilog-set-define (defname defvalue &optional buffer enumname)
8887 "Set the definition DEFNAME to the DEFVALUE in the given BUFFER.
8888 Optionally associate it with the specified enumeration ENUMNAME."
8889 (with-current-buffer (or buffer (current-buffer))
8890 (let ((mac (intern (concat "vh-" defname))))
8891 ;;(message "Define %s=%s" defname defvalue) (sleep-for 1)
8892 ;; Need to define to a constant if no value given
8893 (set (make-local-variable mac)
8894 (if (equal defvalue "") "1" defvalue)))
8896 (let ((enumvar (intern (concat "venum-" enumname))))
8897 ;;(message "Define %s=%s" defname defvalue) (sleep-for 1)
8898 (unless (boundp enumvar) (set enumvar nil))
8899 (add-to-list (make-local-variable enumvar) defname)))))
8901 (defun verilog-read-defines (&optional filename recurse subcall)
8902 "Read `defines and parameters for the current file, or optional FILENAME.
8903 If the filename is provided, `verilog-library-flags' will be used to
8904 resolve it. If optional RECURSE is non-nil, recurse through `includes.
8906 Parameters must be simple assignments to constants, or have their own
8907 \"parameter\" label rather than a list of parameters. Thus:
8909 parameter X = 5, Y = 10; // Ok
8910 parameter X = {1'b1, 2'h2}; // Ok
8911 parameter X = {1'b1, 2'h2}, Y = 10; // Bad, make into 2 parameter lines
8913 Defines must be simple text substitutions, one on a line, starting
8914 at the beginning of the line. Any ifdefs or multiline comments around the
8917 Defines are stored inside Emacs variables using the name vh-{definename}.
8919 This function is useful for setting vh-* variables. The file variables
8920 feature can be used to set defines that `verilog-mode' can see; put at the
8921 *END* of your file something like:
8924 // vh-macro:\"macro_definition\"
8927 If macros are defined earlier in the same file and you want their values,
8928 you can read them automatically (provided `enable-local-eval' is on):
8931 // eval:(verilog-read-defines)
8932 // eval:(verilog-read-defines \"group_standard_includes.v\")
8935 Note these are only read when the file is first visited, you must use
8936 \\[find-alternate-file] RET to have these take effect after editing them!
8938 If you want to disable the \"Process `eval' or hook local variables\"
8939 warning message, you need to add to your init file:
8941 (setq enable-local-eval t)"
8942 (let ((origbuf (current-buffer)))
8944 (unless subcall (verilog-getopt-flags))
8946 (let ((fns (verilog-library-filenames filename (buffer-file-name))))
8948 (set-buffer (find-file-noselect (car fns)))
8949 (error (concat (verilog-point-text)
8950 ": Can't find verilog-read-defines file: " filename)))))
8952 (goto-char (point-min))
8953 (while (re-search-forward "^\\s-*`include\\s-+\\([^ \t\n\f]+\\)" nil t)
8954 (let ((inc (verilog-string-replace-matches
8955 "\"" "" nil nil (match-string-no-properties 1))))
8956 (unless (verilog-inside-comment-or-string-p)
8957 (verilog-read-defines inc recurse t)))))
8959 ;; note we don't use verilog-re... it's faster this way, and that
8960 ;; function has problems when comments are at the end of the define
8961 (goto-char (point-min))
8962 (while (re-search-forward "^\\s-*`define\\s-+\\([a-zA-Z0-9_$]+\\)\\s-+\\(.*\\)$" nil t)
8963 (let ((defname (match-string-no-properties 1))
8964 (defvalue (match-string-no-properties 2)))
8965 (setq defvalue (verilog-string-replace-matches "\\s-*/[/*].*$" "" nil nil defvalue))
8966 (verilog-set-define defname defvalue origbuf)))
8967 ;; Hack: Read parameters
8968 (goto-char (point-min))
8969 (while (re-search-forward
8970 "^\\s-*\\(parameter\\|localparam\\)\\(\\s-*\\[[^]]*\\]\\)?\\s-*" nil t)
8972 ;; The primary way of getting defines is verilog-read-decls
8973 ;; However, that isn't called yet for included files, so we'll add another scheme
8974 (if (looking-at "[^\n]*\\(auto\\|synopsys\\)\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
8975 (setq enumname (match-string-no-properties 2)))
8976 (forward-comment 99999)
8977 (while (looking-at (concat "\\s-*,?\\s-*\\(?:/[/*].*?$\\)?\\s-*\\([a-zA-Z0-9_$]+\\)"
8978 "\\s-*=\\s-*\\([^;,]*\\),?\\s-*\\(/[/*].*?$\\)?\\s-*"))
8979 (verilog-set-define (match-string-no-properties 1)
8980 (match-string-no-properties 2) origbuf enumname)
8981 (goto-char (match-end 0))
8982 (forward-comment 99999)))))))
8984 (defun verilog-read-includes ()
8985 "Read `includes for the current file.
8986 This will find all of the `includes which are at the beginning of lines,
8987 ignoring any ifdefs or multiline comments around them.
8988 `verilog-read-defines' is then performed on the current and each included
8991 It is often useful put at the *END* of your file something like:
8994 // eval:(verilog-read-defines)
8995 // eval:(verilog-read-includes)
8998 Note includes are only read when the file is first visited, you must use
8999 \\[find-alternate-file] RET to have these take effect after editing them!
9001 It is good to get in the habit of including all needed files in each .v
9002 file that needs it, rather than waiting for compile time. This will aid
9003 this process, Verilint, and readability. To prevent defining the same
9004 variable over and over when many modules are compiled together, put a test
9005 around the inside each include file:
9007 foo.v (an include file):
9008 `ifdef _FOO_V // include if not already included
9011 ... contents of file
9013 ;;slow: (verilog-read-defines nil t))
9015 (verilog-getopt-flags)
9016 (goto-char (point-min))
9017 (while (re-search-forward "^\\s-*`include\\s-+\\([^ \t\n\f]+\\)" nil t)
9018 (let ((inc (verilog-string-replace-matches "\"" "" nil nil (match-string 1))))
9019 (verilog-read-defines inc nil t)))))
9021 (defun verilog-read-signals (&optional start end)
9022 "Return a simple list of all possible signals in the file.
9023 Bounded by optional region from START to END. Overly aggressive but fast.
9024 Some macros and such are also found and included. For dinotrace.el."
9025 (let (sigs-all keywd)
9026 (progn;save-excursion
9027 (goto-char (or start (point-min)))
9028 (setq end (or end (point-max)))
9029 (while (re-search-forward "[\"/a-zA-Z_.%`]" end t)
9033 (search-forward "\n"))
9034 ((looking-at "/\\*")
9035 (search-forward "*/"))
9036 ((looking-at "(\\*")
9037 (or (looking-at "(\\*\\s-*)") ; It's a "always @ (*)"
9038 (search-forward "*)")))
9039 ((eq ?\" (following-char))
9040 (re-search-forward "[^\\]\"")) ;; don't forward-char first, since we look for a non backslash first
9041 ((looking-at "\\s-*\\([a-zA-Z0-9$_.%`]+\\)")
9042 (goto-char (match-end 0))
9043 (setq keywd (match-string-no-properties 1))
9044 (or (member keywd verilog-keywords)
9045 (member keywd sigs-all)
9046 (setq sigs-all (cons keywd sigs-all))))
9047 (t (forward-char 1))))
9052 ;; Argument file parsing
9055 (defun verilog-getopt (arglist)
9056 "Parse -f, -v etc arguments in ARGLIST list or string."
9057 (unless (listp arglist) (setq arglist (list arglist)))
9058 (let ((space-args '())
9060 ;; Split on spaces, so users can pass whole command lines
9062 (setq arg (car arglist)
9063 arglist (cdr arglist))
9064 (while (string-match "^\\([^ \t\n\f]+\\)[ \t\n\f]*\\(.*$\\)" arg)
9065 (setq space-args (append space-args
9066 (list (match-string-no-properties 1 arg))))
9067 (setq arg (match-string 2 arg))))
9070 (setq arg (car space-args)
9071 space-args (cdr space-args))
9075 (setq next-param arg))
9077 (setq next-param arg))
9079 (setq next-param arg))
9080 ;; +libext+(ext1)+(ext2)...
9081 ((string-match "^\\+libext\\+\\(.*\\)" arg)
9082 (setq arg (match-string 1 arg))
9083 (while (string-match "\\([^+]+\\)\\+?\\(.*\\)" arg)
9084 (verilog-add-list-unique `verilog-library-extensions
9085 (match-string 1 arg))
9086 (setq arg (match-string 2 arg))))
9088 ((or (string-match "^-D\\([^+=]*\\)[+=]\\(.*\\)" arg) ;; -Ddefine=val
9089 (string-match "^-D\\([^+=]*\\)\\(\\)" arg) ;; -Ddefine
9090 (string-match "^\\+define\\([^+=]*\\)[+=]\\(.*\\)" arg) ;; +define+val
9091 (string-match "^\\+define\\([^+=]*\\)\\(\\)" arg)) ;; +define+define
9092 (verilog-set-define (match-string 1 arg) (match-string 2 arg)))
9094 ((or (string-match "^\\+incdir\\+\\(.*\\)" arg) ;; +incdir+dir
9095 (string-match "^-I\\(.*\\)" arg)) ;; -Idir
9096 (verilog-add-list-unique `verilog-library-directories
9097 (match-string 1 (substitute-in-file-name arg))))
9099 ((equal "+librescan" arg))
9100 ((string-match "^-U\\(.*\\)" arg)) ;; -Udefine
9101 ;; Second parameters
9102 ((equal next-param "-f")
9103 (setq next-param nil)
9104 (verilog-getopt-file (substitute-in-file-name arg)))
9105 ((equal next-param "-v")
9106 (setq next-param nil)
9107 (verilog-add-list-unique `verilog-library-files
9108 (substitute-in-file-name arg)))
9109 ((equal next-param "-y")
9110 (setq next-param nil)
9111 (verilog-add-list-unique `verilog-library-directories
9112 (substitute-in-file-name arg)))
9114 ((string-match "^[^-+]" arg)
9115 (verilog-add-list-unique `verilog-library-files
9116 (substitute-in-file-name arg)))
9117 ;; Default - ignore; no warning
9119 ;;(verilog-getopt (list "+libext+.a+.b" "+incdir+foodir" "+define+a+aval" "-f" "otherf" "-v" "library" "-y" "dir"))
9121 (defun verilog-getopt-file (filename)
9122 "Read Verilog options from the specified FILENAME."
9124 (let ((fns (verilog-library-filenames filename (buffer-file-name)))
9125 (orig-buffer (current-buffer))
9128 (set-buffer (find-file-noselect (car fns)))
9129 (error (concat (verilog-point-text)
9130 ": Can't find verilog-getopt-file -f file: " filename)))
9131 (goto-char (point-min))
9133 (setq line (buffer-substring (point) (point-at-eol)))
9135 (when (string-match "//" line)
9136 (setq line (substring line 0 (match-beginning 0))))
9137 (with-current-buffer orig-buffer ; Variables are buffer-local, so need right context.
9138 (verilog-getopt line))))))
9140 (defun verilog-getopt-flags ()
9141 "Convert `verilog-library-flags' into standard library variables."
9142 ;; If the flags are local, then all the outputs should be local also
9143 (when (local-variable-p `verilog-library-flags (current-buffer))
9144 (mapc 'make-local-variable '(verilog-library-extensions
9145 verilog-library-directories
9146 verilog-library-files
9147 verilog-library-flags)))
9148 ;; Allow user to customize
9149 (verilog-run-hooks 'verilog-before-getopt-flags-hook)
9150 ;; Process arguments
9151 (verilog-getopt verilog-library-flags)
9152 ;; Allow user to customize
9153 (verilog-run-hooks 'verilog-getopt-flags-hook))
9155 (defun verilog-add-list-unique (varref object)
9156 "Append to VARREF list the given OBJECT,
9157 unless it is already a member of the variable's list."
9158 (unless (member object (symbol-value varref))
9159 (set varref (append (symbol-value varref) (list object))))
9161 ;;(progn (setq l '()) (verilog-add-list-unique `l "a") (verilog-add-list-unique `l "a") l)
9163 (defun verilog-current-flags ()
9164 "Convert `verilog-library-flags' and similar variables to command line.
9165 Used for __FLAGS__ in `verilog-expand-command'."
9166 (let ((cmd (mapconcat `concat verilog-library-flags " ")))
9167 (when (equal cmd "")
9169 "+libext+" (mapconcat `concat verilog-library-extensions "+")
9170 (mapconcat (lambda (i) (concat " -y " i " +incdir+" i))
9171 verilog-library-directories "")
9172 (mapconcat (lambda (i) (concat " -v " i))
9173 verilog-library-files ""))))
9175 ;;(verilog-current-flags)
9179 ;; Cached directory support
9182 (defvar verilog-dir-cache-preserving nil
9183 "If set, the directory cache is enabled, and file system changes are ignored.
9184 See `verilog-dir-exists-p' and `verilog-dir-files'.")
9186 ;; If adding new cached variable, add also to verilog-preserve-dir-cache
9187 (defvar verilog-dir-cache-list nil
9188 "Alist of (((Cwd Dirname) Results)...) for caching `verilog-dir-files'.")
9189 (defvar verilog-dir-cache-lib-filenames nil
9190 "Cached data for `verilog-library-filenames'.")
9192 (defmacro verilog-preserve-dir-cache (&rest body)
9193 "Execute the BODY forms, allowing directory cache preservation within BODY.
9194 This means that changes inside BODY made to the file system will not be
9195 seen by the `verilog-dir-files' and related functions."
9196 `(let ((verilog-dir-cache-preserving (current-buffer))
9197 verilog-dir-cache-list
9198 verilog-dir-cache-lib-filenames)
9201 (defun verilog-dir-files (dirname)
9202 "Return all filenames in the DIRNAME directory.
9203 Relative paths depend on the `default-directory'.
9204 Results are cached if inside `verilog-preserve-dir-cache'."
9205 (unless verilog-dir-cache-preserving
9206 (setq verilog-dir-cache-list nil)) ;; Cache disabled
9207 ;; We don't use expand-file-name on the dirname to make key, as it's slow
9208 (let* ((cache-key (list dirname default-directory))
9209 (fass (assoc cache-key verilog-dir-cache-list))
9211 (cond (fass ;; Return data from cache hit
9214 (setq exp-dirname (expand-file-name dirname)
9215 data (and (file-directory-p exp-dirname)
9216 (directory-files exp-dirname nil nil nil)))
9217 ;; Note we also encache nil for non-existing dirs.
9218 (setq verilog-dir-cache-list (cons (list cache-key data)
9219 verilog-dir-cache-list))
9221 ;; Miss-and-hit test:
9222 ;;(verilog-preserve-dir-cache (prin1 (verilog-dir-files "."))
9223 ;; (prin1 (verilog-dir-files ".")) nil)
9225 (defun verilog-dir-file-exists-p (filename)
9226 "Return true if FILENAME exists.
9227 Like `file-exists-p' but results are cached if inside
9228 `verilog-preserve-dir-cache'."
9229 (let* ((dirname (file-name-directory filename))
9230 ;; Correct for file-name-nondirectory returning same if no slash.
9231 (dirnamed (if (or (not dirname) (equal dirname filename))
9232 default-directory dirname))
9233 (flist (verilog-dir-files dirnamed)))
9235 (member (file-name-nondirectory filename) flist)
9237 ;;(verilog-dir-file-exists-p "verilog-mode.el")
9238 ;;(verilog-dir-file-exists-p "../verilog-mode/verilog-mode.el")
9242 ;; Module name lookup
9245 (defun verilog-module-inside-filename-p (module filename)
9246 "Return modi if MODULE is specified inside FILENAME, else nil.
9247 Allows version control to check out the file if need be."
9248 (and (or (file-exists-p filename)
9249 (and (fboundp 'vc-backend)
9250 (vc-backend filename)))
9252 (with-current-buffer (find-file-noselect filename)
9254 (goto-char (point-min))
9256 ;; It may be tempting to look for verilog-defun-re,
9257 ;; don't, it slows things down a lot!
9258 (verilog-re-search-forward-quick "\\<\\(module\\|interface\\|program\\)\\>" nil t)
9259 (setq type (match-string-no-properties 0))
9260 (verilog-re-search-forward-quick "[(;]" nil t))
9261 (if (equal module (verilog-read-module-name))
9262 (setq modi (verilog-modi-new module filename (point) type))))
9265 (defun verilog-is-number (symbol)
9266 "Return true if SYMBOL is number-like."
9267 (or (string-match "^[0-9 \t:]+$" symbol)
9268 (string-match "^[---]*[0-9]+$" symbol)
9269 (string-match "^[0-9 \t]+'s?[hdxbo][0-9a-fA-F_xz? \t]*$" symbol)))
9271 (defun verilog-symbol-detick (symbol wing-it)
9272 "Return an expanded SYMBOL name without any defines.
9273 If the variable vh-{symbol} is defined, return that value.
9274 If undefined, and WING-IT, return just SYMBOL without the tick, else nil."
9275 (while (and symbol (string-match "^`" symbol))
9276 (setq symbol (substring symbol 1))
9278 (if (boundp (intern (concat "vh-" symbol)))
9279 ;; Emacs has a bug where boundp on a buffer-local
9280 ;; variable in only one buffer returns t in another.
9281 ;; This can confuse, so check for nil.
9282 (let ((val (eval (intern (concat "vh-" symbol)))))
9284 (if wing-it symbol nil)
9286 (if wing-it symbol nil))))
9288 ;;(verilog-symbol-detick "`mod" nil)
9290 (defun verilog-symbol-detick-denumber (symbol)
9291 "Return SYMBOL with defines converted and any numbers dropped to nil."
9292 (when (string-match "^`" symbol)
9293 ;; This only will work if the define is a simple signal, not
9294 ;; something like a[b]. Sorry, it should be substituted into the parser
9296 (verilog-string-replace-matches
9297 "\[[^0-9: \t]+\]" "" nil nil
9298 (or (verilog-symbol-detick symbol nil)
9299 (if verilog-auto-sense-defines-constant
9302 (if (verilog-is-number symbol)
9306 (defun verilog-symbol-detick-text (text)
9307 "Return TEXT without any known defines.
9308 If the variable vh-{symbol} is defined, substitute that value."
9309 (let ((ok t) symbol val)
9310 (while (and ok (string-match "`\\([a-zA-Z0-9_]+\\)" text))
9311 (setq symbol (match-string 1 text))
9314 (boundp (intern (concat "vh-" symbol)))
9315 ;; Emacs has a bug where boundp on a buffer-local
9316 ;; variable in only one buffer returns t in another.
9317 ;; This can confuse, so check for nil.
9318 (setq val (eval (intern (concat "vh-" symbol)))))
9319 (setq text (replace-match val nil nil text)))
9320 (t (setq ok nil)))))
9322 ;;(progn (setq vh-mod "`foo" vh-foo "bar") (verilog-symbol-detick-text "bar `mod `undefed"))
9324 (defun verilog-expand-dirnames (&optional dirnames)
9325 "Return a list of existing directories given a list of wildcarded DIRNAMES.
9326 Or, just the existing dirnames themselves if there are no wildcards."
9327 ;; Note this function is performance critical.
9328 ;; Do not call anything that requires disk access that cannot be cached.
9330 (unless dirnames (error "`verilog-library-directories' should include at least '.'"))
9331 (setq dirnames (reverse dirnames)) ; not nreverse
9333 pattern dirfile dirfiles dirname root filename rest basefile)
9335 (setq dirname (substitute-in-file-name (car dirnames))
9336 dirnames (cdr dirnames))
9337 (cond ((string-match (concat "^\\(\\|[/\\]*[^*?]*[/\\]\\)" ;; root
9338 "\\([^/\\]*[*?][^/\\]*\\)" ;; filename with *?
9341 (setq root (match-string 1 dirname)
9342 filename (match-string 2 dirname)
9343 rest (match-string 3 dirname)
9345 ;; now replace those * and ? with .+ and .
9346 ;; use ^ and /> to get only whole file names
9347 (setq pattern (verilog-string-replace-matches "[*]" ".+" nil nil pattern)
9348 pattern (verilog-string-replace-matches "[?]" "." nil nil pattern)
9349 pattern (concat "^" pattern "$")
9350 dirfiles (verilog-dir-files root))
9352 (setq basefile (car dirfiles)
9353 dirfile (expand-file-name (concat root basefile rest))
9354 dirfiles (cdr dirfiles))
9355 (if (and (string-match pattern basefile)
9356 ;; Don't allow abc/*/rtl to match abc/rtl via ..
9357 (not (equal basefile "."))
9358 (not (equal basefile ".."))
9359 (file-directory-p dirfile))
9360 (setq dirlist (cons dirfile dirlist)))))
9363 (if (file-directory-p dirname)
9364 (setq dirlist (cons dirname dirlist))))))
9366 ;;(verilog-expand-dirnames (list "." ".." "nonexist" "../*" "/home/wsnyder/*/v"))
9368 (defun verilog-library-filenames (filename &optional current check-ext)
9369 "Return a search path to find the given FILENAME or module name.
9370 Uses the optional CURRENT filename or variable `buffer-file-name', plus
9371 `verilog-library-directories' and `verilog-library-extensions'
9372 variables to build the path. With optional CHECK-EXT also check
9373 `verilog-library-extensions'."
9374 (unless current (setq current (buffer-file-name)))
9375 (unless verilog-dir-cache-preserving
9376 (setq verilog-dir-cache-lib-filenames nil))
9377 (let* ((cache-key (list filename current check-ext))
9378 (fass (assoc cache-key verilog-dir-cache-lib-filenames))
9379 chkdirs chkdir chkexts fn outlist)
9380 (cond (fass ;; Return data from cache hit
9383 ;; Note this expand can't be easily cached, as we need to
9384 ;; pick up buffer-local variables for newly read sub-module files
9385 (setq chkdirs (verilog-expand-dirnames verilog-library-directories))
9387 (setq chkdir (expand-file-name (car chkdirs)
9388 (file-name-directory current))
9389 chkexts (if check-ext verilog-library-extensions `("")))
9391 (setq fn (expand-file-name (concat filename (car chkexts))
9393 ;;(message "Check for %s" fn)
9394 (if (verilog-dir-file-exists-p fn)
9395 (setq outlist (cons (expand-file-name
9396 fn (file-name-directory current))
9398 (setq chkexts (cdr chkexts)))
9399 (setq chkdirs (cdr chkdirs)))
9400 (setq outlist (nreverse outlist))
9401 (setq verilog-dir-cache-lib-filenames
9402 (cons (list cache-key outlist)
9403 verilog-dir-cache-lib-filenames))
9406 (defun verilog-module-filenames (module current)
9407 "Return a search path to find the given MODULE name.
9408 Uses the CURRENT filename, `verilog-library-extensions',
9409 `verilog-library-directories' and `verilog-library-files'
9410 variables to build the path."
9411 ;; Return search locations for it
9412 (append (list current) ; first, current buffer
9413 (verilog-library-filenames module current t)
9414 verilog-library-files)) ; finally, any libraries
9417 ;; Module Information
9419 ;; Many of these functions work on "modi" a module information structure
9420 ;; A modi is: [module-name-string file-name begin-point]
9422 (defvar verilog-cache-enabled t
9423 "Non-nil enables caching of signals, etc. Set to nil for debugging to make things SLOW!")
9425 (defvar verilog-modi-cache-list nil
9426 "Cache of ((Module Function) Buf-Tick Buf-Modtime Func-Returns)...
9427 For speeding up verilog-modi-get-* commands.
9429 (make-variable-buffer-local 'verilog-modi-cache-list)
9431 (defvar verilog-modi-cache-preserve-tick nil
9432 "Modification tick after which the cache is still considered valid.
9433 Use `verilog-preserve-modi-cache' to set it.")
9434 (defvar verilog-modi-cache-preserve-buffer nil
9435 "Modification tick after which the cache is still considered valid.
9436 Use `verilog-preserve-modi-cache' to set it.")
9437 (defvar verilog-modi-cache-current-enable nil
9438 "Non-nil means allow caching `verilog-modi-current', set by let().")
9439 (defvar verilog-modi-cache-current nil
9440 "Currently active `verilog-modi-current', if any, set by let().")
9441 (defvar verilog-modi-cache-current-max nil
9442 "Current endmodule point for `verilog-modi-cache-current', if any.")
9444 (defun verilog-modi-current ()
9445 "Return the modi structure for the module currently at point, possibly cached."
9446 (cond ((and verilog-modi-cache-current
9447 (>= (point) (verilog-modi-get-point verilog-modi-cache-current))
9448 (<= (point) verilog-modi-cache-current-max))
9449 ;; Slow assertion, for debugging the cache:
9450 ;;(or (equal verilog-modi-cache-current (verilog-modi-current-get)) (debug))
9451 verilog-modi-cache-current)
9452 (verilog-modi-cache-current-enable
9453 (setq verilog-modi-cache-current (verilog-modi-current-get)
9454 verilog-modi-cache-current-max
9455 ;; The cache expires when we pass "endmodule" as then the
9456 ;; current modi may change to the next module
9457 ;; This relies on the AUTOs generally inserting, not deleting text
9459 (verilog-re-search-forward-quick verilog-end-defun-re nil nil)))
9460 verilog-modi-cache-current)
9462 (verilog-modi-current-get))))
9464 (defun verilog-modi-current-get ()
9465 "Return the modi structure for the module currently at point."
9466 (let* (name type pt)
9467 ;; read current module's name
9469 (verilog-re-search-backward-quick verilog-defun-re nil nil)
9470 (setq type (match-string-no-properties 0))
9471 (verilog-re-search-forward-quick "(" nil nil)
9472 (setq name (verilog-read-module-name))
9474 ;; return modi - note this vector built two places
9475 (verilog-modi-new name (or (buffer-file-name) (current-buffer)) pt type)))
9477 (defvar verilog-modi-lookup-cache nil "Hash of (modulename modi).")
9478 (make-variable-buffer-local 'verilog-modi-lookup-cache)
9479 (defvar verilog-modi-lookup-last-current nil "Cache of `current-buffer' at last lookup.")
9480 (defvar verilog-modi-lookup-last-tick nil "Cache of `buffer-chars-modified-tick' at last lookup.")
9482 (defun verilog-modi-lookup (module allow-cache &optional ignore-error)
9483 "Find the file and point at which MODULE is defined.
9484 If ALLOW-CACHE is set, check and remember cache of previous lookups.
9485 Return modi if successful, else print message unless IGNORE-ERROR is true."
9486 (let* ((current (or (buffer-file-name) (current-buffer)))
9489 ;;(message "verilog-modi-lookup: %s" module)
9490 (cond ((and verilog-modi-lookup-cache
9491 verilog-cache-enabled
9493 (setq modi (gethash module verilog-modi-lookup-cache))
9494 (equal verilog-modi-lookup-last-current current)
9495 ;; Iff hit is in current buffer, then tick must match
9496 (or (equal verilog-modi-lookup-last-tick (buffer-chars-modified-tick))
9497 (not (equal current (verilog-modi-file-or-buffer modi)))))
9498 ;;(message "verilog-modi-lookup: HIT %S" modi)
9501 (t (let* ((realname (verilog-symbol-detick module t))
9502 (orig-filenames (verilog-module-filenames realname current))
9503 (filenames orig-filenames)
9505 (while (and filenames (not mif))
9506 (if (not (setq mif (verilog-module-inside-filename-p realname (car filenames))))
9507 (setq filenames (cdr filenames))))
9508 ;; mif has correct form to become later elements of modi
9509 (cond (mif (setq modi mif))
9512 (error (concat (verilog-point-text)
9513 ": Can't locate " module " module definition"
9514 (if (not (equal module realname))
9515 (concat " (Expanded macro to " realname ")")
9517 "\n Check the verilog-library-directories variable."
9518 "\n I looked in (if not listed, doesn't exist):\n\t"
9519 (mapconcat 'concat orig-filenames "\n\t"))))))
9520 (when (eval-when-compile (fboundp 'make-hash-table))
9521 (unless verilog-modi-lookup-cache
9522 (setq verilog-modi-lookup-cache
9523 (make-hash-table :test 'equal :rehash-size 4.0)))
9524 (puthash module modi verilog-modi-lookup-cache))
9525 (setq verilog-modi-lookup-last-current current
9526 verilog-modi-lookup-last-tick (buffer-chars-modified-tick)))))
9529 (defun verilog-modi-filename (modi)
9530 "Filename of MODI, or name of buffer if it's never been saved."
9531 (if (bufferp (verilog-modi-file-or-buffer modi))
9532 (or (buffer-file-name (verilog-modi-file-or-buffer modi))
9533 (buffer-name (verilog-modi-file-or-buffer modi)))
9534 (verilog-modi-file-or-buffer modi)))
9536 (defun verilog-modi-goto (modi)
9537 "Move point/buffer to specified MODI."
9538 (or modi (error "Passed unfound modi to goto, check earlier"))
9539 (set-buffer (if (bufferp (verilog-modi-file-or-buffer modi))
9540 (verilog-modi-file-or-buffer modi)
9541 (find-file-noselect (verilog-modi-file-or-buffer modi))))
9542 (or (equal major-mode `verilog-mode) ;; Put into Verilog mode to get syntax
9544 (goto-char (verilog-modi-get-point modi)))
9546 (defun verilog-goto-defun-file (module)
9547 "Move point to the file at which a given MODULE is defined."
9548 (interactive "sGoto File for Module: ")
9549 (let* ((modi (verilog-modi-lookup module nil)))
9551 (verilog-modi-goto modi)
9552 (switch-to-buffer (current-buffer)))))
9554 (defun verilog-modi-cache-results (modi function)
9555 "Run on MODI the given FUNCTION. Locate the module in a file.
9556 Cache the output of function so next call may have faster access."
9558 (save-excursion ;; Cache is buffer-local so can't avoid this.
9559 (verilog-modi-goto modi)
9560 (if (and (setq fass (assoc (list modi function)
9561 verilog-modi-cache-list))
9562 ;; Destroy caching when incorrect; Modified or file changed
9563 (not (and verilog-cache-enabled
9564 (or (equal (buffer-chars-modified-tick) (nth 1 fass))
9565 (and verilog-modi-cache-preserve-tick
9566 (<= verilog-modi-cache-preserve-tick (nth 1 fass))
9567 (equal verilog-modi-cache-preserve-buffer (current-buffer))))
9568 (equal (visited-file-modtime) (nth 2 fass)))))
9569 (setq verilog-modi-cache-list nil
9572 ;; Return data from cache hit
9576 ;; Clear then restore any highlighting to make emacs19 happy
9578 (verilog-save-font-mods
9579 (setq func-returns (funcall function)))
9580 ;; Cache for next time
9581 (setq verilog-modi-cache-list
9582 (cons (list (list modi function)
9583 (buffer-chars-modified-tick)
9584 (visited-file-modtime)
9586 verilog-modi-cache-list))
9589 (defun verilog-modi-cache-add (modi function element sig-list)
9590 "Add function return results to the module cache.
9591 Update MODI's cache for given FUNCTION so that the return ELEMENT of that
9592 function now contains the additional SIG-LIST parameters."
9595 (verilog-modi-goto modi)
9596 (if (setq fass (assoc (list modi function)
9597 verilog-modi-cache-list))
9598 (let ((func-returns (nth 3 fass)))
9599 (aset func-returns element
9600 (append sig-list (aref func-returns element))))))))
9602 (defmacro verilog-preserve-modi-cache (&rest body)
9603 "Execute the BODY forms, allowing cache preservation within BODY.
9604 This means that changes to the buffer will not result in the cache being
9605 flushed. If the changes affect the modsig state, they must call the
9606 modsig-cache-add-* function, else the results of later calls may be
9607 incorrect. Without this, changes are assumed to be adding/removing signals
9608 and invalidating the cache."
9609 `(let ((verilog-modi-cache-preserve-tick (buffer-chars-modified-tick))
9610 (verilog-modi-cache-preserve-buffer (current-buffer)))
9614 (defun verilog-modi-modport-lookup-one (modi name &optional ignore-error)
9615 "Given a MODI, return the declarations related to the given modport NAME."
9616 ;; Recursive routine - see below
9617 (let* ((realname (verilog-symbol-detick name t))
9618 (modport (assoc name (verilog-decls-get-modports (verilog-modi-get-decls modi)))))
9619 (or modport ignore-error
9620 (error (concat (verilog-point-text)
9621 ": Can't locate " name " modport definition"
9622 (if (not (equal name realname))
9623 (concat " (Expanded macro to " realname ")")
9625 (let* ((decls (verilog-modport-decls modport))
9626 (clks (verilog-modport-clockings modport)))
9627 ;; Now expand any clocking's
9629 (setq decls (verilog-decls-append
9631 (verilog-modi-modport-lookup-one modi (car clks) ignore-error)))
9632 (setq clks (cdr clks)))
9635 (defun verilog-modi-modport-lookup (modi name-re &optional ignore-error)
9636 "Given a MODI, return the declarations related to the given modport NAME-RE.
9637 If the modport points to any clocking blocks, expand the signals to include
9638 those clocking block's signals."
9639 ;; Recursive routine - see below
9640 (let* ((mod-decls (verilog-modi-get-decls modi))
9641 (clks (verilog-decls-get-modports mod-decls))
9642 (name-re (concat "^" name-re "$"))
9643 (decls (verilog-decls-new nil nil nil nil nil nil nil nil nil)))
9644 ;; Pull in all modports
9646 (when (string-match name-re (verilog-modport-name (car clks)))
9647 (setq decls (verilog-decls-append
9649 (verilog-modi-modport-lookup-one modi (verilog-modport-name (car clks)) ignore-error))))
9650 (setq clks (cdr clks)))
9653 (defun verilog-signals-matching-enum (in-list enum)
9654 "Return all signals in IN-LIST matching the given ENUM."
9657 (if (equal (verilog-sig-enum (car in-list)) enum)
9658 (setq out-list (cons (car in-list) out-list)))
9659 (setq in-list (cdr in-list)))
9661 (let* ((enumvar (intern (concat "venum-" enum)))
9662 (enumlist (and (boundp enumvar) (eval enumvar))))
9664 (add-to-list 'out-list (list (car enumlist)))
9665 (setq enumlist (cdr enumlist))))
9666 (nreverse out-list)))
9668 (defun verilog-signals-matching-regexp (in-list regexp)
9669 "Return all signals in IN-LIST matching the given REGEXP, if non-nil."
9670 (if (or (not regexp) (equal regexp ""))
9674 (if (string-match regexp (verilog-sig-name (car in-list)))
9675 (setq out-list (cons (car in-list) out-list)))
9676 (setq in-list (cdr in-list)))
9677 (nreverse out-list))))
9679 (defun verilog-signals-not-matching-regexp (in-list regexp)
9680 "Return all signals in IN-LIST not matching the given REGEXP, if non-nil."
9681 (if (or (not regexp) (equal regexp ""))
9685 (if (not (string-match regexp (verilog-sig-name (car in-list))))
9686 (setq out-list (cons (car in-list) out-list)))
9687 (setq in-list (cdr in-list)))
9688 (nreverse out-list))))
9690 (defun verilog-signals-matching-dir-re (in-list decl-type regexp)
9691 "Return all signals in IN-LIST matching the given DECL-TYPE and REGEXP,
9693 (if (or (not regexp) (equal regexp ""))
9695 (let (out-list to-match)
9697 ;; Note verilog-insert-one-definition matches on this order
9698 (setq to-match (concat
9700 " " (verilog-sig-signed (car in-list))
9701 " " (verilog-sig-multidim (car in-list))
9702 (verilog-sig-bits (car in-list))))
9703 (if (string-match regexp to-match)
9704 (setq out-list (cons (car in-list) out-list)))
9705 (setq in-list (cdr in-list)))
9706 (nreverse out-list))))
9708 (defun verilog-signals-edit-wire-reg (in-list)
9709 "Return all signals in IN-LIST with wire/reg data types made blank."
9710 (mapcar (lambda (sig)
9711 (when (member (verilog-sig-type sig) '("wire" "reg"))
9712 (verilog-sig-type-set sig nil))
9716 (defun verilog-decls-get-signals (decls)
9717 "Return all declared signals in DECLS, excluding 'assign' statements."
9719 (verilog-decls-get-outputs decls)
9720 (verilog-decls-get-inouts decls)
9721 (verilog-decls-get-inputs decls)
9722 (verilog-decls-get-vars decls)
9723 (verilog-decls-get-consts decls)
9724 (verilog-decls-get-gparams decls)))
9726 (defun verilog-decls-get-ports (decls)
9728 (verilog-decls-get-outputs decls)
9729 (verilog-decls-get-inouts decls)
9730 (verilog-decls-get-inputs decls)))
9732 (defun verilog-decls-get-iovars (decls)
9734 (verilog-decls-get-vars decls)
9735 (verilog-decls-get-outputs decls)
9736 (verilog-decls-get-inouts decls)
9737 (verilog-decls-get-inputs decls)))
9739 (defsubst verilog-modi-cache-add-outputs (modi sig-list)
9740 (verilog-modi-cache-add modi 'verilog-read-decls 0 sig-list))
9741 (defsubst verilog-modi-cache-add-inouts (modi sig-list)
9742 (verilog-modi-cache-add modi 'verilog-read-decls 1 sig-list))
9743 (defsubst verilog-modi-cache-add-inputs (modi sig-list)
9744 (verilog-modi-cache-add modi 'verilog-read-decls 2 sig-list))
9745 (defsubst verilog-modi-cache-add-vars (modi sig-list)
9746 (verilog-modi-cache-add modi 'verilog-read-decls 3 sig-list))
9747 (defsubst verilog-modi-cache-add-gparams (modi sig-list)
9748 (verilog-modi-cache-add modi 'verilog-read-decls 7 sig-list))
9752 ;; Auto creation utilities
9755 (defun verilog-auto-re-search-do (search-for func)
9756 "Search for the given auto text regexp SEARCH-FOR, and perform FUNC where it occurs."
9757 (goto-char (point-min))
9758 (while (verilog-re-search-forward-quick search-for nil t)
9761 (defun verilog-insert-one-definition (sig type indent-pt)
9762 "Print out a definition for SIG of the given TYPE,
9763 with appropriate INDENT-PT indentation."
9764 (indent-to indent-pt)
9765 ;; Note verilog-signals-matching-dir-re matches on this order
9767 (when (verilog-sig-modport sig)
9768 (insert "." (verilog-sig-modport sig)))
9769 (when (verilog-sig-signed sig)
9770 (insert " " (verilog-sig-signed sig)))
9771 (when (verilog-sig-multidim sig)
9772 (insert " " (verilog-sig-multidim-string sig)))
9773 (when (verilog-sig-bits sig)
9774 (insert " " (verilog-sig-bits sig)))
9775 (indent-to (max 24 (+ indent-pt 16)))
9776 (unless (= (char-syntax (preceding-char)) ?\ )
9777 (insert " ")) ; Need space between "]name" if indent-to did nothing
9778 (insert (verilog-sig-name sig))
9779 (when (verilog-sig-memory sig)
9780 (insert " " (verilog-sig-memory sig))))
9782 (defun verilog-insert-definition (modi sigs direction indent-pt v2k &optional dont-sort)
9783 "Print out a definition for MODI's list of SIGS of the given DIRECTION,
9784 with appropriate INDENT-PT indentation. If V2K, use Verilog 2001 I/O
9785 format. Sort unless DONT-SORT. DIRECTION is normally wire/reg/output.
9786 When MODI is non-null, also add to modi-cache, for tracking."
9788 (cond ((equal direction "wire")
9789 (verilog-modi-cache-add-vars modi sigs))
9790 ((equal direction "reg")
9791 (verilog-modi-cache-add-vars modi sigs))
9792 ((equal direction "output")
9793 (verilog-modi-cache-add-outputs modi sigs)
9794 (when verilog-auto-declare-nettype
9795 (verilog-modi-cache-add-vars modi sigs)))
9796 ((equal direction "input")
9797 (verilog-modi-cache-add-inputs modi sigs)
9798 (when verilog-auto-declare-nettype
9799 (verilog-modi-cache-add-vars modi sigs)))
9800 ((equal direction "inout")
9801 (verilog-modi-cache-add-inouts modi sigs)
9802 (when verilog-auto-declare-nettype
9803 (verilog-modi-cache-add-vars modi sigs)))
9804 ((equal direction "interface"))
9805 ((equal direction "parameter")
9806 (verilog-modi-cache-add-gparams modi sigs))
9808 (error "Unsupported verilog-insert-definition direction: %s" direction))))
9810 (setq sigs (sort (copy-alist sigs) `verilog-signals-sort-compare)))
9812 (let ((sig (car sigs)))
9813 (verilog-insert-one-definition
9815 ;; Want "type x" or "output type x", not "wire type x"
9816 (cond ((or (verilog-sig-type sig)
9817 verilog-auto-wire-type)
9819 (when (member direction '("input" "output" "inout"))
9820 (concat direction " "))
9821 (or (verilog-sig-type sig)
9822 verilog-auto-wire-type)))
9823 ((and verilog-auto-declare-nettype
9824 (member direction '("input" "output" "inout")))
9825 (concat direction " " verilog-auto-declare-nettype))
9829 (insert (if v2k "," ";"))
9830 (if (or (not (verilog-sig-comment sig))
9831 (equal "" (verilog-sig-comment sig)))
9833 (indent-to (max 48 (+ indent-pt 40)))
9834 (verilog-insert "// " (verilog-sig-comment sig) "\n"))
9835 (setq sigs (cdr sigs)))))
9838 (if (not (boundp 'indent-pt))
9839 (defvar indent-pt nil "Local used by insert-indent")))
9841 (defun verilog-insert-indent (&rest stuff)
9842 "Indent to position stored in local `indent-pt' variable, then insert STUFF.
9843 Presumes that any newlines end a list element."
9844 (let ((need-indent t))
9846 (if need-indent (indent-to indent-pt))
9847 (setq need-indent nil)
9848 (verilog-insert (car stuff))
9849 (setq need-indent (string-match "\n$" (car stuff))
9850 stuff (cdr stuff)))))
9851 ;;(let ((indent-pt 10)) (verilog-insert-indent "hello\n" "addon" "there\n"))
9853 (defun verilog-forward-or-insert-line ()
9854 "Move forward a line, unless at EOB, then insert a newline."
9855 (if (eobp) (insert "\n")
9858 (defun verilog-repair-open-comma ()
9859 "Insert comma if previous argument is other than an open parenthesis or endif."
9860 ;; We can't just search backward for ) as it might be inside another expression.
9861 ;; Also want "`ifdef X input foo `endif" to just leave things to the human to deal with
9863 (verilog-backward-syntactic-ws-quick)
9864 (when (and (not (save-excursion ;; Not beginning (, or existing ,
9866 (looking-at "[(,]")))
9867 (not (save-excursion ;; Not `endif, or user define
9869 (skip-chars-backward "[a-zA-Z0-9_`]")
9873 (defun verilog-repair-close-comma ()
9874 "If point is at a comma followed by a close parenthesis, fix it.
9875 This repairs those mis-inserted by an AUTOARG."
9876 ;; It would be much nicer if Verilog allowed extra commas like Perl does!
9878 (verilog-forward-close-paren)
9880 (verilog-backward-syntactic-ws-quick)
9882 (when (looking-at ",")
9885 (defun verilog-get-list (start end)
9886 "Return the elements of a comma separated list between START and END."
9888 (let ((my-list (list))
9891 (while (< (point) end)
9892 (when (re-search-forward "\\([^,{]+\\)" end t)
9893 (setq my-string (verilog-string-remove-spaces (match-string 1)))
9894 (setq my-list (nconc my-list (list my-string) ))
9895 (goto-char (match-end 0))))
9898 (defun verilog-make-width-expression (range-exp)
9899 "Return an expression calculating the length of a range [x:y] in RANGE-EXP."
9901 (cond ((not range-exp)
9904 (if (string-match "^\\[\\(.*\\)\\]$" range-exp)
9905 (setq range-exp (match-string 1 range-exp)))
9906 (cond ((not range-exp)
9908 ;; [#:#] We can compute a numeric result
9909 ((string-match "^\\s *\\([0-9]+\\)\\s *:\\s *\\([0-9]+\\)\\s *$"
9912 (1+ (abs (- (string-to-number (match-string 1 range-exp))
9913 (string-to-number (match-string 2 range-exp)))))))
9914 ;; [PARAM-1:0] can just return PARAM
9915 ((string-match "^\\s *\\([a-zA-Z_][a-zA-Z0-9_]*\\)\\s *-\\s *1\\s *:\\s *0\\s *$" range-exp)
9916 (match-string 1 range-exp))
9917 ;; [arbitrary] need math
9918 ((string-match "^\\(.*\\)\\s *:\\s *\\(.*\\)\\s *$" range-exp)
9919 (concat "(1+(" (match-string 1 range-exp) ")"
9920 (if (equal "0" (match-string 2 range-exp))
9921 "" ;; Don't bother with -(0)
9922 (concat "-(" (match-string 2 range-exp) ")"))
9925 ;;(verilog-make-width-expression "`A:`B")
9927 (defun verilog-simplify-range-expression (expr)
9928 "Return a simplified range expression with constants eliminated from EXPR."
9929 ;; Note this is always called with brackets; ie [z] or [z:z]
9930 (if (not (string-match "[---+*()]" expr))
9931 expr ;; short-circuit
9934 (while (not (equal last-pass out))
9935 (setq last-pass out)
9936 ;; Prefix regexp needs beginning of match, or some symbol of
9937 ;; lesser or equal precedence. We assume the [:]'s exist in expr.
9939 (while (string-match
9940 (concat "\\([[({:*+-]\\)" ; - must be last
9941 "(\\<\\([0-9A-Za-z_]+\\))"
9944 (setq out (replace-match "\\1\\2\\3" nil nil out)))
9945 (while (string-match
9946 (concat "\\([[({:*+-]\\)" ; - must be last
9947 "\\$clog2\\s *(\\<\\([0-9]+\\))"
9950 (setq out (replace-match
9952 (match-string 1 out)
9953 (int-to-string (verilog-clog2 (string-to-number (match-string 2 out))))
9954 (match-string 3 out))
9956 ;; For precedence do * before +/-
9957 (while (string-match
9958 (concat "\\([[({:*+-]\\)"
9959 "\\([0-9]+\\)\\s *\\([*]\\)\\s *\\([0-9]+\\)"
9962 (setq out (replace-match
9963 (concat (match-string 1 out)
9964 (int-to-string (* (string-to-number (match-string 2 out))
9965 (string-to-number (match-string 4 out))))
9966 (match-string 5 out))
9968 (while (string-match
9969 (concat "\\([[({:+-]\\)" ; No * here as higher prec
9970 "\\([0-9]+\\)\\s *\\([---+]\\)\\s *\\([0-9]+\\)"
9973 (let ((pre (match-string 1 out))
9974 (lhs (string-to-number (match-string 2 out)))
9975 (rhs (string-to-number (match-string 4 out)))
9976 (post (match-string 5 out))
9978 (when (equal pre "-")
9980 (setq val (if (equal (match-string 3 out) "-")
9984 (concat (if (and (equal pre "-")
9986 "" ;; Not "--20" but just "-20"
9993 ;;(verilog-simplify-range-expression "[1:3]") ;; 1
9994 ;;(verilog-simplify-range-expression "[(1):3]") ;; 1
9995 ;;(verilog-simplify-range-expression "[(((16)+1)+1+(1+1))]") ;;20
9996 ;;(verilog-simplify-range-expression "[(2*3+6*7)]") ;; 48
9997 ;;(verilog-simplify-range-expression "[(FOO*4-1*2)]") ;; FOO*4-2
9998 ;;(verilog-simplify-range-expression "[(FOO*4+1-1)]") ;; FOO*4+0
9999 ;;(verilog-simplify-range-expression "[(func(BAR))]") ;; func(BAR)
10000 ;;(verilog-simplify-range-expression "[FOO-1+1-1+1]") ;; FOO-0
10001 ;;(verilog-simplify-range-expression "[$clog2(2)]") ;; 1
10002 ;;(verilog-simplify-range-expression "[$clog2(7)]") ;; 3
10004 (defun verilog-clog2 (value)
10005 "Compute $clog2 - ceiling log2 of VALUE."
10008 (ceiling (/ (log value) (log 2)))))
10010 (defun verilog-typedef-name-p (variable-name)
10011 "Return true if the VARIABLE-NAME is a type definition."
10012 (when verilog-typedef-regexp
10013 (string-match verilog-typedef-regexp variable-name)))
10019 (defun verilog-delete-autos-lined ()
10020 "Delete autos that occupy multiple lines, between begin and end comments."
10021 ;; The newline must not have a comment property, so we must
10022 ;; delete the end auto's newline, not the first newline
10024 (let ((pt (point)))
10026 (looking-at "\\s-*// Beginning")
10027 (search-forward "// End of automatic" nil t))
10031 (delete-region pt (point)))))
10033 (defun verilog-delete-empty-auto-pair ()
10034 "Delete begin/end auto pair at point, if empty."
10036 (when (looking-at (concat "\\s-*// Beginning of automatic.*\n"
10037 "\\s-*// End of automatics\n"))
10038 (delete-region (point) (save-excursion (forward-line 2) (point)))))
10040 (defun verilog-forward-close-paren ()
10041 "Find the close parenthesis that match the current point.
10042 Ignore other close parenthesis with matching open parens."
10044 (while (> parens 0)
10045 (unless (verilog-re-search-forward-quick "[()]" nil t)
10046 (error "%s: Mismatching ()" (verilog-point-text)))
10047 (cond ((= (preceding-char) ?\( )
10048 (setq parens (1+ parens)))
10049 ((= (preceding-char) ?\) )
10050 (setq parens (1- parens)))))))
10052 (defun verilog-backward-open-paren ()
10053 "Find the open parenthesis that match the current point.
10054 Ignore other open parenthesis with matching close parens."
10056 (while (> parens 0)
10057 (unless (verilog-re-search-backward-quick "[()]" nil t)
10058 (error "%s: Mismatching ()" (verilog-point-text)))
10059 (cond ((= (following-char) ?\) )
10060 (setq parens (1+ parens)))
10061 ((= (following-char) ?\( )
10062 (setq parens (1- parens)))))))
10064 (defun verilog-backward-open-bracket ()
10065 "Find the open bracket that match the current point.
10066 Ignore other open bracket with matching close bracket."
10068 (while (> parens 0)
10069 (unless (verilog-re-search-backward-quick "[][]" nil t)
10070 (error "%s: Mismatching []" (verilog-point-text)))
10071 (cond ((= (following-char) ?\] )
10072 (setq parens (1+ parens)))
10073 ((= (following-char) ?\[ )
10074 (setq parens (1- parens)))))))
10076 (defun verilog-delete-to-paren ()
10077 "Delete the automatic inst/sense/arg created by autos.
10078 Deletion stops at the matching end parenthesis, outside comments."
10079 (delete-region (point)
10081 (verilog-backward-open-paren)
10082 (verilog-forward-sexp-ign-cmt 1) ;; Moves to paren that closes argdecl's
10086 (defun verilog-auto-star-safe ()
10087 "Return if a .* AUTOINST is safe to delete or expand.
10088 It was created by the AUTOS themselves, or by the user."
10089 (and verilog-auto-star-expand
10091 (concat "[ \t\n\f,]*\\([)]\\|// " verilog-inst-comment-re "\\)"))))
10093 (defun verilog-delete-auto-star-all ()
10094 "Delete a .* AUTOINST, if it is safe."
10095 (when (verilog-auto-star-safe)
10096 (verilog-delete-to-paren)))
10098 (defun verilog-delete-auto-star-implicit ()
10099 "Delete all .* implicit connections created by `verilog-auto-star'.
10100 This function will be called automatically at save unless
10101 `verilog-auto-star-save' is set, any non-templated expanded pins will be
10104 (let (paren-pt indent have-close-paren)
10106 (goto-char (point-min))
10107 ;; We need to match these even outside of comments.
10108 ;; For reasonable performance, we don't check if inside comments, sorry.
10109 (while (re-search-forward "// Implicit \\.\\*" nil t)
10110 (setq paren-pt (point))
10111 (beginning-of-line)
10112 (setq have-close-paren
10114 (when (search-forward ");" paren-pt t)
10115 (setq indent (current-indentation))
10117 (delete-region (point) (+ 1 paren-pt)) ; Nuke line incl CR
10118 (when have-close-paren
10119 ;; Delete extra commentary
10123 (looking-at (concat "\\s *//\\s *" verilog-inst-comment-re "\n")))
10124 (delete-region (match-beginning 0) (match-end 0))))
10125 ;; If it is simple, we can put the ); on the same line as the last text
10126 (let ((rtn-pt (point)))
10128 (while (progn (backward-char 1)
10129 (looking-at "[ \t\n\f]")))
10130 (when (looking-at ",")
10131 (delete-region (+ 1 (point)) rtn-pt))))
10133 (indent-to indent))
10135 ;; Still need to kill final comma - always is one as we put one after the .*
10136 (re-search-backward ",")
10137 (delete-char 1))))))
10139 (defun verilog-delete-auto ()
10140 "Delete the automatic outputs, regs, and wires created by \\[verilog-auto].
10141 Use \\[verilog-auto] to re-insert the updated AUTOs.
10143 The hooks `verilog-before-delete-auto-hook' and `verilog-delete-auto-hook' are
10144 called before and after this function, respectively."
10147 (if (buffer-file-name)
10148 (find-file-noselect (buffer-file-name))) ;; To check we have latest version
10149 (verilog-save-no-change-functions
10150 (verilog-save-scan-cache
10151 ;; Allow user to customize
10152 (verilog-run-hooks 'verilog-before-delete-auto-hook)
10154 ;; Remove those that have multi-line insertions, possibly with parameters
10155 ;; We allow anything beginning with AUTO, so that users can add their own
10157 (verilog-auto-re-search-do
10158 (concat "/\\*AUTO[A-Za-z0-9_]+"
10159 ;; Optional parens or quoted parameter or .* for (((...)))
10160 "\\(\\|([^)]*)\\|(\"[^\"]*\")\\).*?"
10162 'verilog-delete-autos-lined)
10163 ;; Remove those that are in parenthesis
10164 (verilog-auto-re-search-do
10167 (verilog-regexp-words
10168 `("AS" "AUTOARG" "AUTOCONCATWIDTH" "AUTOINST" "AUTOINSTPARAM"
10171 'verilog-delete-to-paren)
10172 ;; Do .* instantiations, but avoid removing any user pins by looking for our magic comments
10173 (verilog-auto-re-search-do "\\.\\*"
10174 'verilog-delete-auto-star-all)
10175 ;; Remove template comments ... anywhere in case was pasted after AUTOINST removed
10176 (goto-char (point-min))
10177 (while (re-search-forward "\\s-*// \\(Templated\\|Implicit \\.\\*\\)\\([ \tLT0-9]*\\| LHS: .*\\)?$" nil t)
10178 (replace-match ""))
10181 (verilog-run-hooks 'verilog-delete-auto-hook)))))
10187 (defun verilog-inject-auto ()
10188 "Examine legacy non-AUTO code and insert AUTOs in appropriate places.
10190 Any always @ blocks with sensitivity lists that match computed lists will
10191 be replaced with /*AS*/ comments.
10193 Any cells will get /*AUTOINST*/ added to the end of the pin list.
10194 Pins with have identical names will be deleted.
10196 Argument lists will not be deleted, /*AUTOARG*/ will only be inserted to
10197 support adding new ports. You may wish to delete older ports yourself.
10201 module ExampInject (i, o);
10207 InstModule instName
10212 Typing \\[verilog-inject-auto] will make this into:
10214 module ExampInject (i, o/*AUTOARG*/
10219 always @ (/*AS*/i or j)
10221 InstModule instName
10230 (defun verilog-inject-arg ()
10231 "Inject AUTOARG into new code. See `verilog-inject-auto'."
10232 ;; Presume one module per file.
10234 (goto-char (point-min))
10235 (while (verilog-re-search-forward-quick "\\<module\\>" nil t)
10236 (let ((endmodp (save-excursion
10237 (verilog-re-search-forward-quick "\\<endmodule\\>" nil t)
10239 ;; See if there's already a comment .. inside a comment so not verilog-re-search
10240 (when (not (re-search-forward "/\\*AUTOARG\\*/" endmodp t))
10241 (verilog-re-search-forward-quick ";" nil t)
10243 (verilog-backward-syntactic-ws-quick)
10244 (backward-char 1) ; Moves to paren that closes argdecl's
10245 (when (looking-at ")")
10246 (verilog-insert "/*AUTOARG*/")))))))
10248 (defun verilog-inject-sense ()
10249 "Inject AUTOSENSE into new code. See `verilog-inject-auto'."
10251 (goto-char (point-min))
10252 (while (verilog-re-search-forward-quick "\\<always\\s *@\\s *(" nil t)
10253 (let* ((start-pt (point))
10254 (modi (verilog-modi-current))
10255 (moddecls (verilog-modi-get-decls modi))
10259 (verilog-forward-sexp-ign-cmt 1)
10260 (backward-char 1) ;; End )
10261 (when (not (verilog-re-search-backward-quick "/\\*\\(AUTOSENSE\\|AS\\)\\*/" start-pt t))
10262 (setq pre-sigs (verilog-signals-from-signame
10263 (verilog-read-signals start-pt (point)))
10264 got-sigs (verilog-auto-sense-sigs moddecls nil))
10265 (when (not (or (verilog-signals-not-in pre-sigs got-sigs) ; Both are equal?
10266 (verilog-signals-not-in got-sigs pre-sigs)))
10267 (delete-region start-pt (point))
10268 (verilog-insert "/*AS*/")))))))
10270 (defun verilog-inject-inst ()
10271 "Inject AUTOINST into new code. See `verilog-inject-auto'."
10273 (goto-char (point-min))
10274 ;; It's hard to distinguish modules; we'll instead search for pins.
10275 (while (verilog-re-search-forward-quick "\\.\\s *[a-zA-Z0-9`_\$]+\\s *(\\s *[a-zA-Z0-9`_\$]+\\s *)" nil t)
10276 (verilog-backward-open-paren) ;; Inst start
10278 ((= (preceding-char) ?\#) ;; #(...) parameter section, not pin. Skip.
10280 (verilog-forward-close-paren)) ;; Parameters done
10283 (let ((indent-pt (+ (current-column)))
10284 (end-pt (save-excursion (verilog-forward-close-paren) (point))))
10285 (cond ((verilog-re-search-forward-quick "\\(/\\*AUTOINST\\*/\\|\\.\\*\\)" end-pt t)
10286 (goto-char end-pt)) ;; Already there, continue search with next instance
10288 ;; Delete identical interconnect
10289 (let ((case-fold-search nil)) ;; So we don't convert upper-to-lower, etc
10290 (while (verilog-re-search-forward-quick "\\.\\s *\\([a-zA-Z0-9`_\$]+\\)*\\s *(\\s *\\1\\s *)\\s *" end-pt t)
10291 (delete-region (match-beginning 0) (match-end 0))
10292 (setq end-pt (- end-pt (- (match-end 0) (match-beginning 0)))) ;; Keep it correct
10293 (while (or (looking-at "[ \t\n\f,]+")
10294 (looking-at "//[^\n]*"))
10295 (delete-region (match-beginning 0) (match-end 0))
10296 (setq end-pt (- end-pt (- (match-end 0) (match-beginning 0)))))))
10297 (verilog-forward-close-paren)
10299 ;; Not verilog-re-search, as we don't want to strip comments
10300 (while (re-search-backward "[ \t\n\f]+" (- (point) 1) t)
10301 (delete-region (match-beginning 0) (match-end 0)))
10302 (verilog-insert "\n")
10303 (verilog-insert-indent "/*AUTOINST*/")))))))))
10309 (defun verilog-diff-buffers-p (b1 b2 &optional whitespace)
10310 "Return nil if buffers B1 and B2 have same contents.
10311 Else, return point in B1 that first mismatches.
10312 If optional WHITESPACE true, ignore whitespace."
10314 (let* ((case-fold-search nil) ;; compare-buffer-substrings cares
10315 (p1 (with-current-buffer b1 (goto-char (point-min))))
10316 (p2 (with-current-buffer b2 (goto-char (point-min))))
10317 (maxp1 (with-current-buffer b1 (point-max)))
10318 (maxp2 (with-current-buffer b2 (point-max)))
10321 (while (not (and (eq p1 op1) (eq p2 op2)))
10322 ;; If both windows have whitespace optionally skip over it.
10324 ;; skip-syntax-* doesn't count \n
10325 (with-current-buffer b1
10327 (skip-chars-forward " \t\n\r\f\v")
10329 (with-current-buffer b2
10331 (skip-chars-forward " \t\n\r\f\v")
10332 (setq p2 (point))))
10333 (setq size (min (- maxp1 p1) (- maxp2 p2)))
10334 (setq progress (compare-buffer-substrings b2 p2 (+ size p2)
10335 b1 p1 (+ size p1)))
10336 (setq progress (if (zerop progress) size (1- (abs progress))))
10337 (setq op1 p1 op2 p2
10339 p2 (+ p2 progress)))
10341 (if (and (eq p1 maxp1) (eq p2 maxp2))
10344 (defun verilog-diff-file-with-buffer (f1 b2 &optional whitespace show)
10345 "View the differences between file F1 and buffer B2.
10346 This requires the external program `diff-command' to be in your `exec-path',
10347 and uses `diff-switches' in which you may want to have \"-u\" flag.
10348 Ignores WHITESPACE if t, and writes output to stdout if SHOW."
10349 ;; Similar to `diff-buffer-with-file' but works on XEmacs, and doesn't
10350 ;; call `diff' as `diff' has different calling semantics on different
10351 ;; versions of Emacs.
10352 (if (not (file-exists-p f1))
10353 (message "Buffer %s has no associated file on disc" (buffer-name b2))
10354 (with-temp-buffer "*Verilog-Diff*"
10355 (let ((outbuf (current-buffer))
10356 (f2 (make-temp-file "vm-diff-auto-")))
10359 (with-current-buffer b2
10362 (write-region (point-min) (point-max) f2 nil 'nomessage)))
10363 (call-process diff-command nil outbuf t
10364 diff-switches ;; User may want -u in diff-switches
10365 (if whitespace "-b" "")
10367 ;; Print out results. Alternatively we could have call-processed
10368 ;; ourself, but this way we can reuse diff switches
10370 (with-current-buffer outbuf (message "%s" (buffer-string))))))
10372 (when (file-exists-p f2)
10373 (delete-file f2))))))
10375 (defun verilog-diff-report (b1 b2 diffpt)
10376 "Report differences detected with `verilog-diff-auto'.
10377 Differences are between buffers B1 and B2, starting at point
10378 DIFFPT. This function is called via `verilog-diff-function'."
10379 (let ((name1 (with-current-buffer b1 (buffer-file-name))))
10380 (verilog-warn "%s:%d: Difference in AUTO expansion found"
10381 name1 (with-current-buffer b1
10382 (1+ (count-lines (point-min) (point)))))
10383 (cond (noninteractive
10384 (verilog-diff-file-with-buffer name1 b2 t t))
10386 (ediff-buffers b1 b2)))))
10388 (defun verilog-diff-auto ()
10389 "Expand AUTOs in a temporary buffer and indicate any change.
10390 Whitespace differences are ignored to determine identicalness, but
10391 once a difference is detected, whitespace differences may be shown.
10393 To call this from the command line, see \\[verilog-batch-diff-auto].
10395 The action on differences is selected with
10396 `verilog-diff-function'. The default is `verilog-diff-report'
10397 which will report an error and run `ediff' in interactive mode,
10398 or `diff' in batch mode."
10400 (let ((b1 (current-buffer)) b2 diffpt
10401 (name1 (buffer-file-name))
10402 (newname "*Verilog-Diff*"))
10404 (when (get-buffer newname)
10405 (kill-buffer newname))
10406 (setq b2 (let (buffer-file-name) ;; Else clone is upset
10407 (clone-buffer newname)))
10408 (with-current-buffer b2
10409 ;; auto requires the filename, but can't have same filename in two
10410 ;; buffers; so override both b1 and b2's names
10411 (let ((buffer-file-name name1))
10414 (with-current-buffer b1 (setq buffer-file-name nil))
10416 (when (not verilog-auto-star-save)
10417 (verilog-delete-auto-star-implicit)))
10418 ;; Restore name if unwind
10419 (with-current-buffer b1 (setq buffer-file-name name1)))))
10421 (setq diffpt (verilog-diff-buffers-p b1 b2 t))
10422 (cond ((not diffpt)
10423 (unless noninteractive (message "AUTO expansion identical"))
10424 (kill-buffer newname)) ;; Nice to cleanup after oneself
10426 (funcall verilog-diff-function b1 b2 diffpt)))
10427 ;; Return result of compare
10435 (defun verilog-auto-save-check ()
10436 "On saving see if we need auto update."
10437 (cond ((not verilog-auto-save-policy)) ; disabled
10438 ((not (save-excursion
10440 (let ((case-fold-search nil))
10441 (goto-char (point-min))
10442 (re-search-forward "AUTO" nil t))))))
10443 ((eq verilog-auto-save-policy 'force)
10445 ((not (buffer-modified-p)))
10446 ((eq verilog-auto-update-tick (buffer-chars-modified-tick))) ; up-to-date
10447 ((eq verilog-auto-save-policy 'detect)
10450 (when (yes-or-no-p "AUTO statements not recomputed, do it now? ")
10452 ;; Don't ask again if didn't update
10453 (set (make-local-variable 'verilog-auto-update-tick) (buffer-chars-modified-tick))))
10454 (when (not verilog-auto-star-save)
10455 (verilog-delete-auto-star-implicit))
10456 nil) ;; Always return nil -- we don't write the file ourselves
10458 (defun verilog-auto-read-locals ()
10459 "Return file local variable segment at bottom of file."
10461 (goto-char (point-max))
10462 (if (re-search-backward "Local Variables:" nil t)
10463 (buffer-substring-no-properties (point) (point-max))
10466 (defun verilog-auto-reeval-locals (&optional force)
10467 "Read file local variable segment at bottom of file if it has changed.
10468 If FORCE, always reread it."
10469 (let ((curlocal (verilog-auto-read-locals)))
10470 (when (or force (not (equal verilog-auto-last-file-locals curlocal)))
10471 (set (make-local-variable 'verilog-auto-last-file-locals) curlocal)
10472 ;; Note this may cause this function to be recursively invoked,
10473 ;; because hack-local-variables may call (verilog-mode)
10474 ;; The above when statement will prevent it from recursing forever.
10475 (hack-local-variables)
10482 (defun verilog-auto-arg-ports (sigs message indent-pt)
10483 "Print a list of ports for an AUTOINST.
10484 Takes SIGS list, adds MESSAGE to front and inserts each at INDENT-PT."
10486 (when verilog-auto-arg-sort
10487 (setq sigs (sort (copy-alist sigs) `verilog-signals-sort-compare)))
10489 (indent-to indent-pt)
10493 (indent-to indent-pt)
10495 (cond ((> (+ 2 (current-column) (length (verilog-sig-name (car sigs)))) fill-column)
10497 (indent-to indent-pt))
10498 (t (insert space)))
10499 (insert (verilog-sig-name (car sigs)) ",")
10500 (setq sigs (cdr sigs)
10503 (defun verilog-auto-arg ()
10504 "Expand AUTOARG statements.
10505 Replace the argument declarations at the beginning of the
10506 module with ones automatically derived from input and output
10507 statements. This can be dangerous if the module is instantiated
10508 using position-based connections, so use only name-based when
10509 instantiating the resulting module. Long lines are split based
10510 on the `fill-column', see \\[set-fill-column].
10513 Concatenation and outputting partial buses is not supported.
10515 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
10519 module ExampArg (/*AUTOARG*/);
10524 Typing \\[verilog-auto] will make this into:
10526 module ExampArg (/*AUTOARG*/
10536 The argument declarations may be printed in declaration order to best suit
10537 order based instantiations, or alphabetically, based on the
10538 `verilog-auto-arg-sort' variable.
10540 Any ports declared between the ( and /*AUTOARG*/ are presumed to be
10541 predeclared and are not redeclared by AUTOARG. AUTOARG will make a
10542 conservative guess on adding a comma for the first signal, if you have
10543 any ifdefs or complicated expressions before the AUTOARG you will need
10544 to choose the comma yourself.
10546 Avoid declaring ports manually, as it makes code harder to maintain."
10548 (let* ((modi (verilog-modi-current))
10549 (moddecls (verilog-modi-get-decls modi))
10550 (skip-pins (aref (verilog-read-arg-pins) 0)))
10551 (verilog-repair-open-comma)
10552 (verilog-auto-arg-ports (verilog-signals-not-in
10553 (verilog-decls-get-outputs moddecls)
10556 verilog-indent-level-declaration)
10557 (verilog-auto-arg-ports (verilog-signals-not-in
10558 (verilog-decls-get-inouts moddecls)
10561 verilog-indent-level-declaration)
10562 (verilog-auto-arg-ports (verilog-signals-not-in
10563 (verilog-decls-get-inputs moddecls)
10566 verilog-indent-level-declaration)
10567 (verilog-repair-close-comma)
10568 (unless (eq (char-before) ?/ )
10570 (indent-to verilog-indent-level-declaration))))
10572 (defun verilog-auto-assign-modport ()
10573 "Expand AUTOASSIGNMODPORT statements, as part of \\[verilog-auto].
10574 Take input/output/inout statements from the specified interface
10575 and modport and use to build assignments into the modport, for
10576 making verification modules that connect to UVM interfaces.
10578 The first parameter is the name of an interface.
10580 The second parameter is a regexp of modports to read from in
10583 The third parameter is the instance name to use to dot reference into.
10585 The optional fourth parameter is a regular expression, and only
10586 signals matching the regular expression will be included.
10590 Interface names must be resolvable to filenames. See `verilog-auto-inst'.
10592 Inouts are not supported, as assignments must be unidirectional.
10594 If a signal is part of the interface header and in both a
10595 modport and the interface itself, it will not be listed. (As
10596 this would result in a syntax error when the connections are
10599 See the example in `verilog-auto-inout-modport'."
10601 (let* ((params (verilog-read-auto-params 3 4))
10602 (submod (nth 0 params))
10603 (modport-re (nth 1 params))
10604 (inst-name (nth 2 params))
10605 (regexp (nth 3 params))
10606 direction-re submodi) ;; direction argument not supported until requested
10607 ;; Lookup position, etc of co-module
10608 ;; Note this may raise an error
10609 (when (setq submodi (verilog-modi-lookup submod t))
10610 (let* ((indent-pt (current-indentation))
10611 (modi (verilog-modi-current))
10612 (submoddecls (verilog-modi-get-decls submodi))
10613 (submodportdecls (verilog-modi-modport-lookup submodi modport-re))
10614 (sig-list-i (verilog-signals-in ;; Decls doesn't have data types, must resolve
10615 (verilog-decls-get-vars submoddecls)
10616 (verilog-signals-not-in
10617 (verilog-decls-get-inputs submodportdecls)
10618 (verilog-decls-get-ports submoddecls))))
10619 (sig-list-o (verilog-signals-in ;; Decls doesn't have data types, must resolve
10620 (verilog-decls-get-vars submoddecls)
10621 (verilog-signals-not-in
10622 (verilog-decls-get-outputs submodportdecls)
10623 (verilog-decls-get-ports submoddecls)))))
10625 (setq sig-list-i (verilog-signals-edit-wire-reg
10626 (verilog-signals-matching-dir-re
10627 (verilog-signals-matching-regexp sig-list-i regexp)
10628 "input" direction-re))
10629 sig-list-o (verilog-signals-edit-wire-reg
10630 (verilog-signals-matching-dir-re
10631 (verilog-signals-matching-regexp sig-list-o regexp)
10632 "output" direction-re)))
10633 (setq sig-list-i (sort (copy-alist sig-list-i) `verilog-signals-sort-compare))
10634 (setq sig-list-o (sort (copy-alist sig-list-o) `verilog-signals-sort-compare))
10635 (when (or sig-list-i sig-list-o)
10636 (verilog-insert-indent "// Beginning of automatic assignments from modport\n")
10637 ;; Don't sort them so an upper AUTOINST will match the main module
10638 (let ((sigs sig-list-o))
10640 (verilog-insert-indent "assign " (verilog-sig-name (car sigs))
10642 "." (verilog-sig-name (car sigs)) ";\n")
10643 (setq sigs (cdr sigs))))
10644 (let ((sigs sig-list-i))
10646 (verilog-insert-indent "assign " inst-name
10647 "." (verilog-sig-name (car sigs))
10648 " = " (verilog-sig-name (car sigs)) ";\n")
10649 (setq sigs (cdr sigs))))
10650 (verilog-insert-indent "// End of automatics\n")))))))
10652 (defun verilog-auto-inst-port-map (port-st)
10655 (defvar vl-cell-type nil "See `verilog-auto-inst'.") ; Prevent compile warning
10656 (defvar vl-cell-name nil "See `verilog-auto-inst'.") ; Prevent compile warning
10657 (defvar vl-modport nil "See `verilog-auto-inst'.") ; Prevent compile warning
10658 (defvar vl-name nil "See `verilog-auto-inst'.") ; Prevent compile warning
10659 (defvar vl-width nil "See `verilog-auto-inst'.") ; Prevent compile warning
10660 (defvar vl-dir nil "See `verilog-auto-inst'.") ; Prevent compile warning
10661 (defvar vl-bits nil "See `verilog-auto-inst'.") ; Prevent compile warning
10662 (defvar vl-mbits nil "See `verilog-auto-inst'.") ; Prevent compile warning
10664 (defun verilog-auto-inst-port (port-st indent-pt tpl-list tpl-num for-star par-values)
10665 "Print out an instantiation connection for this PORT-ST.
10666 Insert to INDENT-PT, use template TPL-LIST.
10667 @ are instantiation numbers, replaced with TPL-NUM.
10668 @\"(expression @)\" are evaluated, with @ as a variable.
10669 If FOR-STAR add comment it is a .* expansion.
10670 If PAR-VALUES replace final strings with these parameter values."
10671 (let* ((port (verilog-sig-name port-st))
10672 (tpl-ass (or (assoc port (car tpl-list))
10673 (verilog-auto-inst-port-map port-st)))
10674 ;; vl-* are documented for user use
10675 (vl-name (verilog-sig-name port-st))
10676 (vl-width (verilog-sig-width port-st))
10677 (vl-modport (verilog-sig-modport port-st))
10678 (vl-mbits (if (verilog-sig-multidim port-st)
10679 (verilog-sig-multidim-string port-st) ""))
10680 (vl-bits (if (or verilog-auto-inst-vector
10681 (not (assoc port vector-skip-list))
10682 (not (equal (verilog-sig-bits port-st)
10683 (verilog-sig-bits (assoc port vector-skip-list)))))
10684 (or (verilog-sig-bits port-st) "")
10686 (case-fold-search nil)
10687 (check-values par-values)
10689 ;; Replace parameters in bit-width
10690 (when (and check-values
10691 (not (equal vl-bits "")))
10692 (while check-values
10693 (setq vl-bits (verilog-string-replace-matches
10694 (concat "\\<" (nth 0 (car check-values)) "\\>")
10695 (concat "(" (nth 1 (car check-values)) ")")
10697 vl-mbits (verilog-string-replace-matches
10698 (concat "\\<" (nth 0 (car check-values)) "\\>")
10699 (concat "(" (nth 1 (car check-values)) ")")
10701 check-values (cdr check-values)))
10702 (setq vl-bits (verilog-simplify-range-expression vl-bits)
10703 vl-mbits (verilog-simplify-range-expression vl-mbits)
10704 vl-width (verilog-make-width-expression vl-bits))) ; Not in the loop for speed
10705 ;; Default net value if not found
10706 (setq tpl-net (concat port
10707 (if vl-modport (concat "." vl-modport) "")
10708 (if (verilog-sig-multidim port-st)
10709 (concat "/*" vl-mbits vl-bits "*/")
10710 (concat vl-bits))))
10712 (cond (tpl-ass ; Template of exact port name
10713 (setq tpl-net (nth 1 tpl-ass)))
10714 ((nth 1 tpl-list) ; Wildcards in template, search them
10715 (let ((wildcards (nth 1 tpl-list)))
10717 (when (string-match (nth 0 (car wildcards)) port)
10718 (setq tpl-ass (car wildcards) ; so allow @ parsing
10719 tpl-net (replace-match (nth 1 (car wildcards))
10721 (setq wildcards (cdr wildcards))))))
10722 ;; Parse Templated variable
10724 ;; Evaluate @"(lispcode)"
10725 (when (string-match "@\".*[^\\]\"" tpl-net)
10726 (while (string-match "@\"\\(\\([^\\\"]*\\(\\\\.\\)*\\)*\\)\"" tpl-net)
10729 (substring tpl-net 0 (match-beginning 0))
10731 (let* ((expr (match-string 1 tpl-net))
10734 (setq expr (verilog-string-replace-matches "\\\\\"" "\"" nil nil expr))
10735 (setq expr (verilog-string-replace-matches "@" tpl-num nil nil expr))
10736 (prin1 (eval (car (read-from-string expr)))
10737 (lambda (ch) ())))))
10738 (if (numberp value) (setq value (number-to-string value)))
10740 (substring tpl-net (match-end 0))))))
10741 ;; Replace @ and [] magic variables in final output
10742 (setq tpl-net (verilog-string-replace-matches "@" tpl-num nil nil tpl-net))
10743 (setq tpl-net (verilog-string-replace-matches "\\[\\]" vl-bits nil nil tpl-net)))
10745 (indent-to indent-pt)
10747 (unless (and verilog-auto-inst-dot-name
10748 (equal port tpl-net))
10749 (indent-to verilog-auto-inst-column)
10750 (insert "(" tpl-net ")"))
10753 (verilog-read-auto-template-hit tpl-ass)
10754 (indent-to (+ (if (< verilog-auto-inst-column 48) 24 16)
10755 verilog-auto-inst-column))
10756 ;; verilog-insert requires the complete comment in one call - including the newline
10757 (cond ((equal verilog-auto-inst-template-numbers `lhs)
10758 (verilog-insert " // Templated"
10759 " LHS: " (nth 0 tpl-ass)
10761 (verilog-auto-inst-template-numbers
10762 (verilog-insert " // Templated"
10763 " T" (int-to-string (nth 2 tpl-ass))
10764 " L" (int-to-string (nth 3 tpl-ass))
10767 (verilog-insert " // Templated\n"))))
10769 (indent-to (+ (if (< verilog-auto-inst-column 48) 24 16)
10770 verilog-auto-inst-column))
10771 (verilog-insert " // Implicit .\*\n")) ;For some reason the . or * must be escaped...
10774 ;;(verilog-auto-inst-port (list "foo" "[5:0]") 10 (list (list "foo" "a@\"(% (+ @ 1) 4)\"a")) "3")
10775 ;;(x "incom[@\"(+ (* 8 @) 7)\":@\"(* 8 @)\"]")
10776 ;;(x ".out (outgo[@\"(concat (+ (* 8 @) 7) \\\":\\\" ( * 8 @))\"]));")
10778 (defun verilog-auto-inst-port-list (sig-list indent-pt tpl-list tpl-num for-star par-values)
10779 "For `verilog-auto-inst' print a list of ports using `verilog-auto-inst-port'."
10780 (when verilog-auto-inst-sort
10781 (setq sig-list (sort (copy-alist sig-list) `verilog-signals-sort-compare)))
10782 (mapc (lambda (port)
10783 (verilog-auto-inst-port port indent-pt
10784 tpl-list tpl-num for-star par-values))
10787 (defun verilog-auto-inst-first ()
10788 "Insert , etc before first ever port in this instant, as part of \\[verilog-auto-inst]."
10789 ;; Do we need a trailing comma?
10790 ;; There maybe an ifdef or something similar before us. What a mess. Thus
10791 ;; to avoid trouble we only insert on preceding ) or *.
10792 ;; Insert first port on new line
10793 (insert "\n") ;; Must insert before search, so point will move forward if insert comma
10795 (verilog-re-search-backward-quick "[^ \t\n\f]" nil nil)
10796 (when (looking-at ")\\|\\*") ;; Generally don't insert, unless we are fairly sure
10800 (defun verilog-auto-star ()
10801 "Expand SystemVerilog .* pins, as part of \\[verilog-auto].
10803 If `verilog-auto-star-expand' is set, .* pins are treated if they were
10804 AUTOINST statements, otherwise they are ignored. For safety, Verilog mode
10805 will also ignore any .* that are not last in your pin list (this prevents
10806 it from deleting pins following the .* when it expands the AUTOINST.)
10808 On writing your file, unless `verilog-auto-star-save' is set, any
10809 non-templated expanded pins will be removed. You may do this at any time
10810 with \\[verilog-delete-auto-star-implicit].
10812 If you are converting a module to use .* for the first time, you may wish
10813 to use \\[verilog-inject-auto] and then replace the created AUTOINST with .*.
10815 See `verilog-auto-inst' for examples, templates, and more information."
10816 (when (verilog-auto-star-safe)
10817 (verilog-auto-inst)))
10819 (defun verilog-auto-inst ()
10820 "Expand AUTOINST statements, as part of \\[verilog-auto].
10821 Replace the pin connections to an instantiation or interface
10822 declaration with ones automatically derived from the module or
10823 interface header of the instantiated item.
10825 If `verilog-auto-star-expand' is set, also expand SystemVerilog .* ports,
10826 and delete them before saving unless `verilog-auto-star-save' is set.
10827 See `verilog-auto-star' for more information.
10829 The pins are printed in declaration order or alphabetically,
10830 based on the `verilog-auto-inst-sort' variable.
10833 Module names must be resolvable to filenames by adding a
10834 `verilog-library-extensions', and being found in the same directory, or
10835 by changing the variable `verilog-library-flags' or
10836 `verilog-library-directories'. Macros `modname are translated through the
10837 vh-{name} Emacs variable, if that is not found, it just ignores the `.
10839 In templates you must have one signal per line, ending in a ), or ));,
10840 and have proper () nesting, including a final ); to end the template.
10842 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
10844 SystemVerilog multidimensional input/output has only experimental support.
10846 SystemVerilog .name syntax is used if `verilog-auto-inst-dot-name' is set.
10848 Parameters referenced by the instantiation will remain symbolic, unless
10849 `verilog-auto-inst-param-value' is set.
10851 Gate primitives (and/or) may have AUTOINST for the purpose of
10852 AUTOWIRE declarations, etc. Gates are the only case when
10853 position based connections are passed.
10855 For example, first take the submodule InstModule.v:
10857 module InstModule (o,i);
10860 wire [31:0] o = {32{i}};
10863 This is then used in an upper level module:
10865 module ExampInst (o,i);
10868 InstModule instName
10872 Typing \\[verilog-auto] will make this into:
10874 module ExampInst (o,i);
10877 InstModule instName
10885 Where the list of inputs and outputs came from the inst module.
10889 Unless you are instantiating a module multiple times, or the module is
10890 something trivial like an adder, DO NOT CHANGE SIGNAL NAMES ACROSS HIERARCHY.
10891 It just makes for unmaintainable code. To sanitize signal names, try
10892 vrename from URL `http://www.veripool.org'.
10894 When you need to violate this suggestion there are two ways to list
10895 exceptions, placing them before the AUTOINST, or using templates.
10897 Any ports defined before the /*AUTOINST*/ are not included in the list of
10898 automatics. This is similar to making a template as described below, but
10899 is restricted to simple connections just like you normally make. Also note
10900 that any signals before the AUTOINST will only be picked up by AUTOWIRE if
10901 you have the appropriate // Input or // Output comment, and exactly the
10902 same line formatting as AUTOINST itself uses.
10904 InstModule instName
10906 .i (my_i_dont_mess_with_it),
10914 For multiple instantiations based upon a single template, create a
10915 commented out template:
10917 /* InstModule AUTO_TEMPLATE (
10922 Templates go ABOVE the instantiation(s). When an instantiation is
10923 expanded `verilog-mode' simply searches up for the closest template.
10924 Thus you can have multiple templates for the same module, just alternate
10925 between the template for an instantiation and the instantiation itself.
10926 (For backward compatibility if no template is found above, it
10927 will also look below, but do not use this behavior in new designs.)
10929 The module name must be the same as the name of the module in the
10930 instantiation name, and the code \"AUTO_TEMPLATE\" must be in these exact
10931 words and capitalized. Only signals that must be different for each
10932 instantiation need to be listed.
10934 Inside a template, a [] in a connection name (with nothing else inside
10935 the brackets) will be replaced by the same bus subscript as it is being
10936 connected to, or the [] will be removed if it is a single bit signal.
10937 Generally it is a good idea to do this for all connections in a template,
10938 as then they will work for any width signal, and with AUTOWIRE. See
10939 PTL_BUS becoming PTL_BUSNEW below.
10941 If you have a complicated template, set `verilog-auto-inst-template-numbers'
10942 to see which regexps are matching. Don't leave that mode set after
10943 debugging is completed though, it will result in lots of extra differences
10944 and merge conflicts.
10946 Setting `verilog-auto-template-warn-unused' will report errors
10947 if any template lines are unused.
10951 /* InstModule AUTO_TEMPLATE (
10952 .ptl_bus (ptl_busnew[]),
10955 InstModule ms2m (/*AUTOINST*/);
10957 Typing \\[verilog-auto] will make this into:
10959 InstModule ms2m (/*AUTOINST*/
10961 .NotInTemplate (NotInTemplate),
10962 .ptl_bus (ptl_busnew[3:0]), // Templated
10966 Multiple Module Templates:
10968 The same template lines can be applied to multiple modules with
10969 the syntax as follows:
10971 /* InstModuleA AUTO_TEMPLATE
10972 InstModuleB AUTO_TEMPLATE
10973 InstModuleC AUTO_TEMPLATE
10974 InstModuleD AUTO_TEMPLATE (
10975 .ptl_bus (ptl_busnew[]),
10979 Note there is only one AUTO_TEMPLATE opening parenthesis.
10983 It is common to instantiate a cell multiple times, so templates make it
10984 trivial to substitute part of the cell name into the connection name.
10986 /* InstName AUTO_TEMPLATE <optional \"REGEXP\"> (
10988 .sig2 (sigy[@\"(% (+ 1 @) 4)\"]),
10992 If no regular expression is provided immediately after the AUTO_TEMPLATE
10993 keyword, then the @ character in any connection names will be replaced
10994 with the instantiation number; the first digits found in the cell's
10995 instantiation name.
10997 If a regular expression is provided, the @ character will be replaced
10998 with the first \(\) grouping that matches against the cell name. Using a
10999 regexp of \"\\([0-9]+\\)\" provides identical values for @ as when no
11000 regexp is provided. If you use multiple layers of parenthesis,
11001 \"test\\([^0-9]+\\)_\\([0-9]+\\)\" would replace @ with non-number
11002 characters after test and before _, whereas
11003 \"\\(test\\([a-z]+\\)_\\([0-9]+\\)\\)\" would replace @ with the entire
11008 /* InstModule AUTO_TEMPLATE (
11009 .ptl_mapvalidx (ptl_mapvalid[@]),
11010 .ptl_mapvalidp1x (ptl_mapvalid[@\"(% (+ 1 @) 4)\"]),
11013 InstModule ms2m (/*AUTOINST*/);
11015 Typing \\[verilog-auto] will make this into:
11017 InstModule ms2m (/*AUTOINST*/
11019 .ptl_mapvalidx (ptl_mapvalid[2]),
11020 .ptl_mapvalidp1x (ptl_mapvalid[3]));
11022 Note the @ character was replaced with the 2 from \"ms2m\".
11024 Alternatively, using a regular expression for @:
11026 /* InstModule AUTO_TEMPLATE \"_\\([a-z]+\\)\" (
11027 .ptl_mapvalidx (@_ptl_mapvalid),
11028 .ptl_mapvalidp1x (ptl_mapvalid_@),
11031 InstModule ms2_FOO (/*AUTOINST*/);
11032 InstModule ms2_BAR (/*AUTOINST*/);
11034 Typing \\[verilog-auto] will make this into:
11036 InstModule ms2_FOO (/*AUTOINST*/
11038 .ptl_mapvalidx (FOO_ptl_mapvalid),
11039 .ptl_mapvalidp1x (ptl_mapvalid_FOO));
11040 InstModule ms2_BAR (/*AUTOINST*/
11042 .ptl_mapvalidx (BAR_ptl_mapvalid),
11043 .ptl_mapvalidp1x (ptl_mapvalid_BAR));
11048 A template entry of the form
11050 .pci_req\\([0-9]+\\)_l (pci_req_jtag_[\\1]),
11052 will apply an Emacs style regular expression search for any port beginning
11053 in pci_req followed by numbers and ending in _l and connecting that to
11054 the pci_req_jtag_[] net, with the bus subscript coming from what matches
11055 inside the first set of \\( \\). Thus pci_req2_l becomes pci_req_jtag_[2].
11057 Since \\([0-9]+\\) is so common and ugly to read, a @ in the port name
11058 does the same thing. (Note a @ in the connection/replacement text is
11059 completely different -- still use \\1 there!) Thus this is the same as
11060 the above template:
11062 .pci_req@_l (pci_req_jtag_[\\1]),
11064 Here's another example to remove the _l, useful when naming conventions
11065 specify _ alone to mean active low. Note the use of [] to keep the bus
11068 .\\(.*\\)_l (\\1_[]),
11072 First any regular expression template is expanded.
11074 If the syntax @\"( ... )\" is found in a connection, the expression in
11075 quotes will be evaluated as a Lisp expression, with @ replaced by the
11076 instantiation number. The MAPVALIDP1X example above would put @+1 modulo
11077 4 into the brackets. Quote all double-quotes inside the expression with
11078 a leading backslash (\\\"...\\\"); or if the Lisp template is also a
11079 regexp template backslash the backslash quote (\\\\\"...\\\\\").
11081 There are special variables defined that are useful in these
11084 vl-name Name portion of the input/output port.
11085 vl-bits Bus bits portion of the input/output port ('[2:0]').
11086 vl-mbits Multidimensional array bits for port ('[2:0][3:0]').
11087 vl-width Width of the input/output port ('3' for [2:0]).
11088 May be a (...) expression if bits isn't a constant.
11089 vl-dir Direction of the pin input/output/inout/interface.
11090 vl-modport The modport, if an interface with a modport.
11091 vl-cell-type Module name/type of the cell ('InstModule').
11092 vl-cell-name Instance name of the cell ('instName').
11094 Normal Lisp variables may be used in expressions. See
11095 `verilog-read-defines' which can set vh-{definename} variables for use
11096 here. Also, any comments of the form:
11098 /*AUTO_LISP(setq foo 1)*/
11100 will evaluate any Lisp expression inside the parenthesis between the
11101 beginning of the buffer and the point of the AUTOINST. This allows
11102 functions to be defined or variables to be changed between instantiations.
11103 (See also `verilog-auto-insert-lisp' if you want the output from your
11104 lisp function to be inserted.)
11106 Note that when using lisp expressions errors may occur when @ is not a
11107 number; you may need to use the standard Emacs Lisp functions
11108 `number-to-string' and `string-to-number'.
11110 After the evaluation is completed, @ substitution and [] substitution
11113 For more information see the \\[verilog-faq] and forums at URL
11114 `http://www.veripool.org'."
11117 (let* ((pt (point))
11118 (for-star (save-excursion (backward-char 2) (looking-at "\\.\\*")))
11119 (indent-pt (save-excursion (verilog-backward-open-paren)
11120 (1+ (current-column))))
11121 (verilog-auto-inst-column (max verilog-auto-inst-column
11122 (+ 16 (* 8 (/ (+ indent-pt 7) 8)))))
11123 (modi (verilog-modi-current))
11124 (moddecls (verilog-modi-get-decls modi))
11125 (vector-skip-list (unless verilog-auto-inst-vector
11126 (verilog-decls-get-signals moddecls)))
11127 submod submodi submoddecls
11128 inst skip-pins tpl-list tpl-num did-first par-values)
11130 ;; Find module name that is instantiated
11131 (setq submod (verilog-read-inst-module)
11132 inst (verilog-read-inst-name)
11133 vl-cell-type submod
11135 skip-pins (aref (verilog-read-inst-pins) 0))
11137 ;; Parse any AUTO_LISP() before here
11138 (verilog-read-auto-lisp (point-min) pt)
11140 ;; Read parameters (after AUTO_LISP)
11141 (setq par-values (and verilog-auto-inst-param-value
11142 (verilog-read-inst-param-value)))
11144 ;; Lookup position, etc of submodule
11145 ;; Note this may raise an error
11146 (when (and (not (member submod verilog-gate-keywords))
11147 (setq submodi (verilog-modi-lookup submod t)))
11148 (setq submoddecls (verilog-modi-get-decls submodi))
11149 ;; If there's a number in the instantiation, it may be an argument to the
11150 ;; automatic variable instantiation program.
11151 (let* ((tpl-info (verilog-read-auto-template submod))
11152 (tpl-regexp (aref tpl-info 0)))
11153 (setq tpl-num (if (string-match tpl-regexp inst)
11154 (match-string 1 inst)
11156 tpl-list (aref tpl-info 1)))
11157 ;; Find submodule's signals and dump
11158 (let ((sig-list (and (equal (verilog-modi-get-type submodi) "interface")
11159 (verilog-signals-not-in
11160 (verilog-decls-get-vars submoddecls)
11162 (vl-dir "interfaced"))
11163 (when (and sig-list
11164 verilog-auto-inst-interfaced-ports)
11165 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
11166 ;; Note these are searched for in verilog-read-sub-decls.
11167 (verilog-insert-indent "// Interfaced\n")
11168 (verilog-auto-inst-port-list sig-list indent-pt
11169 tpl-list tpl-num for-star par-values)))
11170 (let ((sig-list (verilog-signals-not-in
11171 (verilog-decls-get-interfaces submoddecls)
11173 (vl-dir "interface"))
11175 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
11176 ;; Note these are searched for in verilog-read-sub-decls.
11177 (verilog-insert-indent "// Interfaces\n")
11178 (verilog-auto-inst-port-list sig-list indent-pt
11179 tpl-list tpl-num for-star par-values)))
11180 (let ((sig-list (verilog-signals-not-in
11181 (verilog-decls-get-outputs submoddecls)
11185 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
11186 (verilog-insert-indent "// Outputs\n")
11187 (verilog-auto-inst-port-list sig-list indent-pt
11188 tpl-list tpl-num for-star par-values)))
11189 (let ((sig-list (verilog-signals-not-in
11190 (verilog-decls-get-inouts submoddecls)
11194 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
11195 (verilog-insert-indent "// Inouts\n")
11196 (verilog-auto-inst-port-list sig-list indent-pt
11197 tpl-list tpl-num for-star par-values)))
11198 (let ((sig-list (verilog-signals-not-in
11199 (verilog-decls-get-inputs submoddecls)
11203 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
11204 (verilog-insert-indent "// Inputs\n")
11205 (verilog-auto-inst-port-list sig-list indent-pt
11206 tpl-list tpl-num for-star par-values)))
11210 (re-search-backward "," pt t)
11213 (search-forward "\n") ;; Added by inst-port
11215 (if (search-forward ")" nil t) ;; From user, moved up a line
11217 (if (search-forward ";" nil t) ;; Don't error if user had syntax error and forgot it
11218 (delete-char -1)))))))))
11220 (defun verilog-auto-inst-param ()
11221 "Expand AUTOINSTPARAM statements, as part of \\[verilog-auto].
11222 Replace the parameter connections to an instantiation with ones
11223 automatically derived from the module header of the instantiated netlist.
11225 See \\[verilog-auto-inst] for limitations, and templates to customize the
11228 For example, first take the submodule InstModule.v:
11230 module InstModule (o,i);
11234 This is then used in an upper level module:
11236 module ExampInst (o,i);
11238 InstModule #(/*AUTOINSTPARAM*/)
11239 instName (/*AUTOINST*/);
11242 Typing \\[verilog-auto] will make this into:
11244 module ExampInst (o,i);
11247 InstModule #(/*AUTOINSTPARAM*/
11250 instName (/*AUTOINST*/);
11253 Where the list of parameter connections come from the inst module.
11257 You can customize the parameter connections using AUTO_TEMPLATEs,
11258 just as you would with \\[verilog-auto-inst]."
11261 (let* ((pt (point))
11262 (indent-pt (save-excursion (verilog-backward-open-paren)
11263 (1+ (current-column))))
11264 (verilog-auto-inst-column (max verilog-auto-inst-column
11265 (+ 16 (* 8 (/ (+ indent-pt 7) 8)))))
11266 (modi (verilog-modi-current))
11267 (moddecls (verilog-modi-get-decls modi))
11268 (vector-skip-list (unless verilog-auto-inst-vector
11269 (verilog-decls-get-signals moddecls)))
11270 submod submodi submoddecls
11271 inst skip-pins tpl-list tpl-num did-first)
11272 ;; Find module name that is instantiated
11273 (setq submod (save-excursion
11274 ;; Get to the point where AUTOINST normally is to read the module
11275 (verilog-re-search-forward-quick "[(;]" nil nil)
11276 (verilog-read-inst-module))
11277 inst (save-excursion
11278 ;; Get to the point where AUTOINST normally is to read the module
11279 (verilog-re-search-forward-quick "[(;]" nil nil)
11280 (verilog-read-inst-name))
11281 vl-cell-type submod
11283 skip-pins (aref (verilog-read-inst-pins) 0))
11285 ;; Parse any AUTO_LISP() before here
11286 (verilog-read-auto-lisp (point-min) pt)
11288 ;; Lookup position, etc of submodule
11289 ;; Note this may raise an error
11290 (when (setq submodi (verilog-modi-lookup submod t))
11291 (setq submoddecls (verilog-modi-get-decls submodi))
11292 ;; If there's a number in the instantiation, it may be an argument to the
11293 ;; automatic variable instantiation program.
11294 (let* ((tpl-info (verilog-read-auto-template submod))
11295 (tpl-regexp (aref tpl-info 0)))
11296 (setq tpl-num (if (string-match tpl-regexp inst)
11297 (match-string 1 inst)
11299 tpl-list (aref tpl-info 1)))
11300 ;; Find submodule's signals and dump
11301 (let ((sig-list (verilog-signals-not-in
11302 (verilog-decls-get-gparams submoddecls)
11304 (vl-dir "parameter"))
11306 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
11307 ;; Note these are searched for in verilog-read-sub-decls.
11308 (verilog-insert-indent "// Parameters\n")
11309 (verilog-auto-inst-port-list sig-list indent-pt
11310 tpl-list tpl-num nil nil)))
11314 (re-search-backward "," pt t)
11317 (search-forward "\n") ;; Added by inst-port
11319 (if (search-forward ")" nil t) ;; From user, moved up a line
11320 (delete-char -1)))))))))
11322 (defun verilog-auto-reg ()
11323 "Expand AUTOREG statements, as part of \\[verilog-auto].
11324 Make reg statements for any output that isn't already declared,
11325 and isn't a wire output from a block. `verilog-auto-wire-type'
11326 may be used to change the datatype of the declarations.
11329 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
11331 This does NOT work on memories, declare those yourself.
11335 module ExampReg (o,i);
11342 Typing \\[verilog-auto] will make this into:
11344 module ExampReg (o,i);
11348 // Beginning of automatic regs (for this module's undeclared outputs)
11350 // End of automatics
11354 ;; Point must be at insertion point.
11355 (let* ((indent-pt (current-indentation))
11356 (modi (verilog-modi-current))
11357 (moddecls (verilog-modi-get-decls modi))
11358 (modsubdecls (verilog-modi-get-sub-decls modi))
11359 (sig-list (verilog-signals-not-in
11360 (verilog-decls-get-outputs moddecls)
11361 (append (verilog-signals-with ;; ignore typed signals
11363 (verilog-decls-get-outputs moddecls))
11364 (verilog-decls-get-vars moddecls)
11365 (verilog-decls-get-assigns moddecls)
11366 (verilog-decls-get-consts moddecls)
11367 (verilog-decls-get-gparams moddecls)
11368 (verilog-subdecls-get-interfaced modsubdecls)
11369 (verilog-subdecls-get-outputs modsubdecls)
11370 (verilog-subdecls-get-inouts modsubdecls)))))
11372 (verilog-forward-or-insert-line)
11373 (verilog-insert-indent "// Beginning of automatic regs (for this module's undeclared outputs)\n")
11374 (verilog-insert-definition modi sig-list "reg" indent-pt nil)
11375 (verilog-insert-indent "// End of automatics\n")))))
11377 (defun verilog-auto-reg-input ()
11378 "Expand AUTOREGINPUT statements, as part of \\[verilog-auto].
11379 Make reg statements instantiation inputs that aren't already declared.
11380 This is useful for making a top level shell for testing the module that is
11381 to be instantiated.
11384 This ONLY detects inputs of AUTOINSTants (see `verilog-read-sub-decls').
11386 This does NOT work on memories, declare those yourself.
11388 An example (see `verilog-auto-inst' for what else is going on here):
11390 module ExampRegInput (o,i);
11394 InstModule instName
11398 Typing \\[verilog-auto] will make this into:
11400 module ExampRegInput (o,i);
11404 // Beginning of automatic reg inputs (for undeclared ...
11405 reg [31:0] iv; // From inst of inst.v
11406 // End of automatics
11407 InstModule instName
11415 ;; Point must be at insertion point.
11416 (let* ((indent-pt (current-indentation))
11417 (modi (verilog-modi-current))
11418 (moddecls (verilog-modi-get-decls modi))
11419 (modsubdecls (verilog-modi-get-sub-decls modi))
11420 (sig-list (verilog-signals-combine-bus
11421 (verilog-signals-not-in
11422 (append (verilog-subdecls-get-inputs modsubdecls)
11423 (verilog-subdecls-get-inouts modsubdecls))
11424 (append (verilog-decls-get-signals moddecls)
11425 (verilog-decls-get-assigns moddecls))))))
11427 (verilog-forward-or-insert-line)
11428 (verilog-insert-indent "// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)\n")
11429 (verilog-insert-definition modi sig-list "reg" indent-pt nil)
11430 (verilog-insert-indent "// End of automatics\n")))))
11432 (defun verilog-auto-logic-setup ()
11433 "Prepare variables due to AUTOLOGIC."
11434 (unless verilog-auto-wire-type
11435 (set (make-local-variable 'verilog-auto-wire-type)
11438 (defun verilog-auto-logic ()
11439 "Expand AUTOLOGIC statements, as part of \\[verilog-auto].
11440 Make wire statements using the SystemVerilog logic keyword.
11441 This is currently equivalent to:
11445 with the below at the bottom of the file
11447 // Local Variables:
11448 // verilog-auto-logic-type:\"logic\"
11451 In the future AUTOLOGIC may declare additional identifiers,
11452 while AUTOWIRE will not."
11454 (verilog-auto-logic-setup)
11455 (verilog-auto-wire)))
11457 (defun verilog-auto-wire ()
11458 "Expand AUTOWIRE statements, as part of \\[verilog-auto].
11459 Make wire statements for instantiations outputs that aren't
11460 already declared. `verilog-auto-wire-type' may be used to change
11461 the datatype of the declarations.
11464 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls'),
11465 and all buses must have widths, such as those from AUTOINST, or using []
11468 This does NOT work on memories or SystemVerilog .name connections,
11469 declare those yourself.
11471 Verilog mode will add \"Couldn't Merge\" comments to signals it cannot
11472 determine how to bus together. This occurs when you have ports with
11473 non-numeric or non-sequential bus subscripts. If Verilog mode
11474 mis-guessed, you'll have to declare them yourself.
11476 An example (see `verilog-auto-inst' for what else is going on here):
11478 module ExampWire (o,i);
11482 InstModule instName
11486 Typing \\[verilog-auto] will make this into:
11488 module ExampWire (o,i);
11492 // Beginning of automatic wires
11493 wire [31:0] ov; // From inst of inst.v
11494 // End of automatics
11495 InstModule instName
11504 ;; Point must be at insertion point.
11505 (let* ((indent-pt (current-indentation))
11506 (modi (verilog-modi-current))
11507 (moddecls (verilog-modi-get-decls modi))
11508 (modsubdecls (verilog-modi-get-sub-decls modi))
11509 (sig-list (verilog-signals-combine-bus
11510 (verilog-signals-not-in
11511 (append (verilog-subdecls-get-outputs modsubdecls)
11512 (verilog-subdecls-get-inouts modsubdecls))
11513 (verilog-decls-get-signals moddecls)))))
11515 (verilog-forward-or-insert-line)
11516 (verilog-insert-indent "// Beginning of automatic wires (for undeclared instantiated-module outputs)\n")
11517 (verilog-insert-definition modi sig-list "wire" indent-pt nil)
11518 (verilog-insert-indent "// End of automatics\n")
11519 ;; We used to optionally call verilog-pretty-declarations and
11520 ;; verilog-pretty-expr here, but it's too slow on huge modules,
11521 ;; plus makes everyone's module change. Finally those call
11522 ;; syntax-ppss which is broken when change hooks are disabled.
11525 (defun verilog-auto-output ()
11526 "Expand AUTOOUTPUT statements, as part of \\[verilog-auto].
11527 Make output statements for any output signal from an /*AUTOINST*/ that
11528 isn't an input to another AUTOINST. This is useful for modules which
11529 only instantiate other modules.
11532 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
11534 If placed inside the parenthesis of a module declaration, it creates
11535 Verilog 2001 style, else uses Verilog 1995 style.
11537 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
11538 instantiation, all bets are off. (For example due to an AUTO_TEMPLATE).
11540 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
11542 Signals matching `verilog-auto-output-ignore-regexp' are not included.
11544 An example (see `verilog-auto-inst' for what else is going on here):
11546 module ExampOutput (ov,i);
11549 InstModule instName
11553 Typing \\[verilog-auto] will make this into:
11555 module ExampOutput (ov,i);
11558 // Beginning of automatic outputs (from unused autoinst outputs)
11559 output [31:0] ov; // From inst of inst.v
11560 // End of automatics
11561 InstModule instName
11569 You may also provide an optional regular expression, in which case only
11570 signals matching the regular expression will be included. For example the
11571 same expansion will result from only extracting outputs starting with ov:
11573 /*AUTOOUTPUT(\"^ov\")*/"
11575 ;; Point must be at insertion point.
11576 (let* ((indent-pt (current-indentation))
11577 (params (verilog-read-auto-params 0 1))
11578 (regexp (nth 0 params))
11579 (v2k (verilog-in-paren-quick))
11580 (modi (verilog-modi-current))
11581 (moddecls (verilog-modi-get-decls modi))
11582 (modsubdecls (verilog-modi-get-sub-decls modi))
11583 (sig-list (verilog-signals-not-in
11584 (verilog-subdecls-get-outputs modsubdecls)
11585 (append (verilog-decls-get-outputs moddecls)
11586 (verilog-decls-get-inouts moddecls)
11587 (verilog-subdecls-get-inputs modsubdecls)
11588 (verilog-subdecls-get-inouts modsubdecls)))))
11590 (setq sig-list (verilog-signals-matching-regexp
11592 (setq sig-list (verilog-signals-not-matching-regexp
11593 sig-list verilog-auto-output-ignore-regexp))
11594 (verilog-forward-or-insert-line)
11595 (when v2k (verilog-repair-open-comma))
11597 (verilog-insert-indent "// Beginning of automatic outputs (from unused autoinst outputs)\n")
11598 (verilog-insert-definition modi sig-list "output" indent-pt v2k)
11599 (verilog-insert-indent "// End of automatics\n"))
11600 (when v2k (verilog-repair-close-comma)))))
11602 (defun verilog-auto-output-every ()
11603 "Expand AUTOOUTPUTEVERY statements, as part of \\[verilog-auto].
11604 Make output statements for any signals that aren't primary inputs or
11605 outputs already. This makes every signal in the design an output. This is
11606 useful to get Synopsys to preserve every signal in the design, since it
11607 won't optimize away the outputs.
11611 module ExampOutputEvery (o,i,tempa,tempb);
11614 /*AUTOOUTPUTEVERY*/
11616 wire tempb = tempa;
11620 Typing \\[verilog-auto] will make this into:
11622 module ExampOutputEvery (o,i,tempa,tempb);
11625 /*AUTOOUTPUTEVERY*/
11626 // Beginning of automatic outputs (every signal)
11629 // End of automatics
11631 wire tempb = tempa;
11635 ;;Point must be at insertion point
11636 (let* ((indent-pt (current-indentation))
11637 (v2k (verilog-in-paren-quick))
11638 (modi (verilog-modi-current))
11639 (moddecls (verilog-modi-get-decls modi))
11640 (sig-list (verilog-signals-combine-bus
11641 (verilog-signals-not-in
11642 (verilog-decls-get-signals moddecls)
11643 (verilog-decls-get-ports moddecls)))))
11644 (verilog-forward-or-insert-line)
11645 (when v2k (verilog-repair-open-comma))
11647 (verilog-insert-indent "// Beginning of automatic outputs (every signal)\n")
11648 (verilog-insert-definition modi sig-list "output" indent-pt v2k)
11649 (verilog-insert-indent "// End of automatics\n"))
11650 (when v2k (verilog-repair-close-comma)))))
11652 (defun verilog-auto-input ()
11653 "Expand AUTOINPUT statements, as part of \\[verilog-auto].
11654 Make input statements for any input signal into an /*AUTOINST*/ that
11655 isn't declared elsewhere inside the module. This is useful for modules which
11656 only instantiate other modules.
11659 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
11661 If placed inside the parenthesis of a module declaration, it creates
11662 Verilog 2001 style, else uses Verilog 1995 style.
11664 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
11665 instantiation, all bets are off. (For example due to an AUTO_TEMPLATE).
11667 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
11669 Signals matching `verilog-auto-input-ignore-regexp' are not included.
11671 An example (see `verilog-auto-inst' for what else is going on here):
11673 module ExampInput (ov,i);
11676 InstModule instName
11680 Typing \\[verilog-auto] will make this into:
11682 module ExampInput (ov,i);
11685 // Beginning of automatic inputs (from unused autoinst inputs)
11686 input i; // From inst of inst.v
11687 // End of automatics
11688 InstModule instName
11696 You may also provide an optional regular expression, in which case only
11697 signals matching the regular expression will be included. For example the
11698 same expansion will result from only extracting inputs starting with i:
11700 /*AUTOINPUT(\"^i\")*/"
11702 (let* ((indent-pt (current-indentation))
11703 (params (verilog-read-auto-params 0 1))
11704 (regexp (nth 0 params))
11705 (v2k (verilog-in-paren-quick))
11706 (modi (verilog-modi-current))
11707 (moddecls (verilog-modi-get-decls modi))
11708 (modsubdecls (verilog-modi-get-sub-decls modi))
11709 (sig-list (verilog-signals-not-in
11710 (verilog-subdecls-get-inputs modsubdecls)
11711 (append (verilog-decls-get-inputs moddecls)
11712 (verilog-decls-get-inouts moddecls)
11713 (verilog-decls-get-vars moddecls)
11714 (verilog-decls-get-consts moddecls)
11715 (verilog-decls-get-gparams moddecls)
11716 (verilog-subdecls-get-interfaced modsubdecls)
11717 (verilog-subdecls-get-outputs modsubdecls)
11718 (verilog-subdecls-get-inouts modsubdecls)))))
11720 (setq sig-list (verilog-signals-matching-regexp
11722 (setq sig-list (verilog-signals-not-matching-regexp
11723 sig-list verilog-auto-input-ignore-regexp))
11724 (verilog-forward-or-insert-line)
11725 (when v2k (verilog-repair-open-comma))
11727 (verilog-insert-indent "// Beginning of automatic inputs (from unused autoinst inputs)\n")
11728 (verilog-insert-definition modi sig-list "input" indent-pt v2k)
11729 (verilog-insert-indent "// End of automatics\n"))
11730 (when v2k (verilog-repair-close-comma)))))
11732 (defun verilog-auto-inout ()
11733 "Expand AUTOINOUT statements, as part of \\[verilog-auto].
11734 Make inout statements for any inout signal in an /*AUTOINST*/ that
11735 isn't declared elsewhere inside the module.
11738 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
11740 If placed inside the parenthesis of a module declaration, it creates
11741 Verilog 2001 style, else uses Verilog 1995 style.
11743 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
11744 instantiation, all bets are off. (For example due to an AUTO_TEMPLATE).
11746 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
11748 Signals matching `verilog-auto-inout-ignore-regexp' are not included.
11750 An example (see `verilog-auto-inst' for what else is going on here):
11752 module ExampInout (ov,i);
11755 InstModule instName
11759 Typing \\[verilog-auto] will make this into:
11761 module ExampInout (ov,i);
11764 // Beginning of automatic inouts (from unused autoinst inouts)
11765 inout [31:0] ov; // From inst of inst.v
11766 // End of automatics
11767 InstModule instName
11775 You may also provide an optional regular expression, in which case only
11776 signals matching the regular expression will be included. For example the
11777 same expansion will result from only extracting inouts starting with i:
11779 /*AUTOINOUT(\"^i\")*/"
11781 ;; Point must be at insertion point.
11782 (let* ((indent-pt (current-indentation))
11783 (params (verilog-read-auto-params 0 1))
11784 (regexp (nth 0 params))
11785 (v2k (verilog-in-paren-quick))
11786 (modi (verilog-modi-current))
11787 (moddecls (verilog-modi-get-decls modi))
11788 (modsubdecls (verilog-modi-get-sub-decls modi))
11789 (sig-list (verilog-signals-not-in
11790 (verilog-subdecls-get-inouts modsubdecls)
11791 (append (verilog-decls-get-outputs moddecls)
11792 (verilog-decls-get-inouts moddecls)
11793 (verilog-decls-get-inputs moddecls)
11794 (verilog-subdecls-get-inputs modsubdecls)
11795 (verilog-subdecls-get-outputs modsubdecls)))))
11797 (setq sig-list (verilog-signals-matching-regexp
11799 (setq sig-list (verilog-signals-not-matching-regexp
11800 sig-list verilog-auto-inout-ignore-regexp))
11801 (verilog-forward-or-insert-line)
11802 (when v2k (verilog-repair-open-comma))
11804 (verilog-insert-indent "// Beginning of automatic inouts (from unused autoinst inouts)\n")
11805 (verilog-insert-definition modi sig-list "inout" indent-pt v2k)
11806 (verilog-insert-indent "// End of automatics\n"))
11807 (when v2k (verilog-repair-close-comma)))))
11809 (defun verilog-auto-inout-module (&optional complement all-in)
11810 "Expand AUTOINOUTMODULE statements, as part of \\[verilog-auto].
11811 Take input/output/inout statements from the specified module and insert
11812 into the current module. This is useful for making null templates and
11813 shell modules which need to have identical I/O with another module.
11814 Any I/O which are already defined in this module will not be redefined.
11815 For the complement of this function, see `verilog-auto-inout-comp',
11816 and to make monitors with all inputs, see `verilog-auto-inout-in'.
11819 If placed inside the parenthesis of a module declaration, it creates
11820 Verilog 2001 style, else uses Verilog 1995 style.
11822 Concatenation and outputting partial buses is not supported.
11824 Module names must be resolvable to filenames. See `verilog-auto-inst'.
11826 Signals are not inserted in the same order as in the original module,
11827 though they will appear to be in the same order to an AUTOINST
11828 instantiating either module.
11830 Signals declared as \"output reg\" or \"output wire\" etc will
11831 lose the wire/reg declaration so that shell modules may
11832 generate those outputs differently. However, \"output logic\"
11837 module ExampShell (/*AUTOARG*/);
11838 /*AUTOINOUTMODULE(\"ExampMain\")*/
11841 module ExampMain (i,o,io);
11847 Typing \\[verilog-auto] will make this into:
11849 module ExampShell (/*AUTOARG*/i,o,io);
11850 /*AUTOINOUTMODULE(\"ExampMain\")*/
11851 // Beginning of automatic in/out/inouts (from specific module)
11855 // End of automatics
11858 You may also provide an optional regular expression, in which case only
11859 signals matching the regular expression will be included. For example the
11860 same expansion will result from only extracting signals starting with i:
11862 /*AUTOINOUTMODULE(\"ExampMain\",\"^i\")*/
11864 You may also provide an optional second regular expression, in
11865 which case only signals which have that pin direction and data
11866 type will be included. This matches against everything before
11867 the signal name in the declaration, for example against
11868 \"input\" (single bit), \"output logic\" (direction and type) or
11869 \"output [1:0]\" (direction and implicit type). You also
11870 probably want to skip spaces in your regexp.
11872 For example, the below will result in matching the output \"o\"
11873 against the previous example's module:
11875 /*AUTOINOUTMODULE(\"ExampMain\",\"\",\"^output.*\")*/"
11877 (let* ((params (verilog-read-auto-params 1 3))
11878 (submod (nth 0 params))
11879 (regexp (nth 1 params))
11880 (direction-re (nth 2 params))
11882 ;; Lookup position, etc of co-module
11883 ;; Note this may raise an error
11884 (when (setq submodi (verilog-modi-lookup submod t))
11885 (let* ((indent-pt (current-indentation))
11886 (v2k (verilog-in-paren-quick))
11887 (modi (verilog-modi-current))
11888 (moddecls (verilog-modi-get-decls modi))
11889 (submoddecls (verilog-modi-get-decls submodi))
11890 (sig-list-i (verilog-signals-not-in
11893 (verilog-decls-get-inputs submoddecls)
11894 (verilog-decls-get-inouts submoddecls)
11895 (verilog-decls-get-outputs submoddecls)))
11897 (verilog-decls-get-outputs submoddecls))
11898 (t (verilog-decls-get-inputs submoddecls)))
11899 (append (verilog-decls-get-inputs moddecls))))
11900 (sig-list-o (verilog-signals-not-in
11903 (verilog-decls-get-inputs submoddecls))
11904 (t (verilog-decls-get-outputs submoddecls)))
11905 (append (verilog-decls-get-outputs moddecls))))
11906 (sig-list-io (verilog-signals-not-in
11908 (t (verilog-decls-get-inouts submoddecls)))
11909 (append (verilog-decls-get-inouts moddecls))))
11910 (sig-list-if (verilog-signals-not-in
11911 (verilog-decls-get-interfaces submoddecls)
11912 (append (verilog-decls-get-interfaces moddecls)))))
11914 (setq sig-list-i (verilog-signals-edit-wire-reg
11915 (verilog-signals-matching-dir-re
11916 (verilog-signals-matching-regexp sig-list-i regexp)
11917 "input" direction-re))
11918 sig-list-o (verilog-signals-edit-wire-reg
11919 (verilog-signals-matching-dir-re
11920 (verilog-signals-matching-regexp sig-list-o regexp)
11921 "output" direction-re))
11922 sig-list-io (verilog-signals-edit-wire-reg
11923 (verilog-signals-matching-dir-re
11924 (verilog-signals-matching-regexp sig-list-io regexp)
11925 "inout" direction-re))
11926 sig-list-if (verilog-signals-matching-dir-re
11927 (verilog-signals-matching-regexp sig-list-if regexp)
11928 "interface" direction-re))
11929 (when v2k (verilog-repair-open-comma))
11930 (when (or sig-list-i sig-list-o sig-list-io)
11931 (verilog-insert-indent "// Beginning of automatic in/out/inouts (from specific module)\n")
11932 ;; Don't sort them so an upper AUTOINST will match the main module
11933 (verilog-insert-definition modi sig-list-o "output" indent-pt v2k t)
11934 (verilog-insert-definition modi sig-list-io "inout" indent-pt v2k t)
11935 (verilog-insert-definition modi sig-list-i "input" indent-pt v2k t)
11936 (verilog-insert-definition modi sig-list-if "interface" indent-pt v2k t)
11937 (verilog-insert-indent "// End of automatics\n"))
11938 (when v2k (verilog-repair-close-comma)))))))
11940 (defun verilog-auto-inout-comp ()
11941 "Expand AUTOINOUTCOMP statements, as part of \\[verilog-auto].
11942 Take input/output/inout statements from the specified module and
11943 insert the inverse into the current module (inputs become outputs
11944 and vice-versa.) This is useful for making test and stimulus
11945 modules which need to have complementing I/O with another module.
11946 Any I/O which are already defined in this module will not be
11947 redefined. For the complement of this function, see
11948 `verilog-auto-inout-module'.
11951 If placed inside the parenthesis of a module declaration, it creates
11952 Verilog 2001 style, else uses Verilog 1995 style.
11954 Concatenation and outputting partial buses is not supported.
11956 Module names must be resolvable to filenames. See `verilog-auto-inst'.
11958 Signals are not inserted in the same order as in the original module,
11959 though they will appear to be in the same order to an AUTOINST
11960 instantiating either module.
11964 module ExampShell (/*AUTOARG*/);
11965 /*AUTOINOUTCOMP(\"ExampMain\")*/
11968 module ExampMain (i,o,io);
11974 Typing \\[verilog-auto] will make this into:
11976 module ExampShell (/*AUTOARG*/i,o,io);
11977 /*AUTOINOUTCOMP(\"ExampMain\")*/
11978 // Beginning of automatic in/out/inouts (from specific module)
11982 // End of automatics
11985 You may also provide an optional regular expression, in which case only
11986 signals matching the regular expression will be included. For example the
11987 same expansion will result from only extracting signals starting with i:
11989 /*AUTOINOUTCOMP(\"ExampMain\",\"^i\")*/"
11990 (verilog-auto-inout-module t nil))
11992 (defun verilog-auto-inout-in ()
11993 "Expand AUTOINOUTIN statements, as part of \\[verilog-auto].
11994 Take input/output/inout statements from the specified module and
11995 insert them as all inputs into the current module. This is
11996 useful for making monitor modules which need to see all signals
11997 as inputs based on another module. Any I/O which are already
11998 defined in this module will not be redefined. See also
11999 `verilog-auto-inout-module'.
12002 If placed inside the parenthesis of a module declaration, it creates
12003 Verilog 2001 style, else uses Verilog 1995 style.
12005 Concatenation and outputting partial buses is not supported.
12007 Module names must be resolvable to filenames. See `verilog-auto-inst'.
12009 Signals are not inserted in the same order as in the original module,
12010 though they will appear to be in the same order to an AUTOINST
12011 instantiating either module.
12015 module ExampShell (/*AUTOARG*/);
12016 /*AUTOINOUTIN(\"ExampMain\")*/
12019 module ExampMain (i,o,io);
12025 Typing \\[verilog-auto] will make this into:
12027 module ExampShell (/*AUTOARG*/i,o,io);
12028 /*AUTOINOUTIN(\"ExampMain\")*/
12029 // Beginning of automatic in/out/inouts (from specific module)
12033 // End of automatics
12036 You may also provide an optional regular expression, in which case only
12037 signals matching the regular expression will be included. For example the
12038 same expansion will result from only extracting signals starting with i:
12040 /*AUTOINOUTCOMP(\"ExampMain\",\"^i\")*/"
12041 (verilog-auto-inout-module nil t))
12043 (defun verilog-auto-inout-param ()
12044 "Expand AUTOINOUTPARAM statements, as part of \\[verilog-auto].
12045 Take input/output/inout statements from the specified module and insert
12046 into the current module. This is useful for making null templates and
12047 shell modules which need to have identical I/O with another module.
12048 Any I/O which are already defined in this module will not be redefined.
12049 For the complement of this function, see `verilog-auto-inout-comp',
12050 and to make monitors with all inputs, see `verilog-auto-inout-in'.
12053 If placed inside the parenthesis of a module declaration, it creates
12054 Verilog 2001 style, else uses Verilog 1995 style.
12056 Concatenation and outputting partial buses is not supported.
12058 Module names must be resolvable to filenames. See `verilog-auto-inst'.
12060 Signals are not inserted in the same order as in the original module,
12061 though they will appear to be in the same order to an AUTOINST
12062 instantiating either module.
12064 Signals declared as \"output reg\" or \"output wire\" etc will
12065 lose the wire/reg declaration so that shell modules may
12066 generate those outputs differently. However, \"output logic\"
12071 module ExampShell (/*AUTOARG*/);
12072 /*AUTOINOUTMODULE(\"ExampMain\")*/
12075 module ExampMain (i,o,io);
12081 Typing \\[verilog-auto] will make this into:
12083 module ExampShell (/*AUTOARG*/i,o,io);
12084 /*AUTOINOUTMODULE(\"ExampMain\")*/
12085 // Beginning of automatic in/out/inouts (from specific module)
12089 // End of automatics
12092 You may also provide an optional regular expression, in which case only
12093 signals matching the regular expression will be included. For example the
12094 same expansion will result from only extracting signals starting with i:
12096 /*AUTOINOUTMODULE(\"ExampMain\",\"^i\")*/
12098 You may also provide an optional second regular expression, in
12099 which case only signals which have that pin direction and data
12100 type will be included. This matches against everything before
12101 the signal name in the declaration, for example against
12102 \"input\" (single bit), \"output logic\" (direction and type) or
12103 \"output [1:0]\" (direction and implicit type). You also
12104 probably want to skip spaces in your regexp.
12106 For example, the below will result in matching the output \"o\"
12107 against the previous example's module:
12109 /*AUTOINOUTMODULE(\"ExampMain\",\"\",\"^output.*\")*/
12111 You may also provide an optional third regular expression, in
12112 which case any parameter names that match the given regexp will
12113 be included. Including parameters is off by default. To include
12114 all signals and parameters, use:
12116 /*AUTOINOUTMODULE(\"ExampMain\",\".*\",\".*\",\".*\")*/"
12118 (let* ((params (verilog-read-auto-params 1 2))
12119 (submod (nth 0 params))
12120 (regexp (nth 1 params))
12122 ;; Lookup position, etc of co-module
12123 ;; Note this may raise an error
12124 (when (setq submodi (verilog-modi-lookup submod t))
12125 (let* ((indent-pt (current-indentation))
12126 (v2k (verilog-in-paren-quick))
12127 (modi (verilog-modi-current))
12128 (moddecls (verilog-modi-get-decls modi))
12129 (submoddecls (verilog-modi-get-decls submodi))
12130 (sig-list-p (verilog-signals-not-in
12131 (verilog-decls-get-gparams submoddecls)
12132 (append (verilog-decls-get-gparams moddecls)))))
12134 (setq sig-list-p (verilog-signals-matching-regexp sig-list-p regexp))
12135 (when v2k (verilog-repair-open-comma))
12137 (verilog-insert-indent "// Beginning of automatic parameters (from specific module)\n")
12138 ;; Don't sort them so an upper AUTOINST will match the main module
12139 (verilog-insert-definition modi sig-list-p "parameter" indent-pt v2k t)
12140 (verilog-insert-indent "// End of automatics\n"))
12141 (when v2k (verilog-repair-close-comma)))))))
12143 (defun verilog-auto-inout-modport ()
12144 "Expand AUTOINOUTMODPORT statements, as part of \\[verilog-auto].
12145 Take input/output/inout statements from the specified interface
12146 and modport and insert into the current module. This is useful
12147 for making verification modules that connect to UVM interfaces.
12149 The first parameter is the name of an interface.
12151 The second parameter is a regexp of modports to read from in
12154 The optional third parameter is a regular expression, and only
12155 signals matching the regular expression will be included.
12158 If placed inside the parenthesis of a module declaration, it creates
12159 Verilog 2001 style, else uses Verilog 1995 style.
12161 Interface names must be resolvable to filenames. See `verilog-auto-inst'.
12163 As with other autos, any inputs/outputs declared in the module
12164 will suppress the AUTO from redeclaring an input/output by
12170 ( input logic clk );
12172 logic [7:0] req_dat;
12173 clocking mon_clkblk @(posedge clk);
12177 modport mp(clocking mon_clkblk);
12182 /*AUTOINOUTMODPORT(\"ExampIf\" \"mp\")*/
12183 // Beginning of automatic in/out/inouts (from modport)
12184 input [7:0] req_dat,
12186 // End of automatics
12188 /*AUTOASSIGNMODPORT(\"ExampIf\" \"mp\")*/
12191 Typing \\[verilog-auto] will make this into:
12196 /*AUTOINOUTMODPORT(\"ExampIf\" \"mp\")*/
12197 // Beginning of automatic in/out/inouts (from modport)
12200 // End of automatics
12203 If the modport is part of a UVM monitor/driver class, this
12204 creates a wrapper module that may be used to instantiate the
12205 driver/monitor using AUTOINST in the testbench."
12207 (let* ((params (verilog-read-auto-params 2 3))
12208 (submod (nth 0 params))
12209 (modport-re (nth 1 params))
12210 (regexp (nth 2 params))
12211 direction-re submodi) ;; direction argument not supported until requested
12212 ;; Lookup position, etc of co-module
12213 ;; Note this may raise an error
12214 (when (setq submodi (verilog-modi-lookup submod t))
12215 (let* ((indent-pt (current-indentation))
12216 (v2k (verilog-in-paren-quick))
12217 (modi (verilog-modi-current))
12218 (moddecls (verilog-modi-get-decls modi))
12219 (submoddecls (verilog-modi-get-decls submodi))
12220 (submodportdecls (verilog-modi-modport-lookup submodi modport-re))
12221 (sig-list-i (verilog-signals-in ;; Decls doesn't have data types, must resolve
12222 (verilog-decls-get-vars submoddecls)
12223 (verilog-signals-not-in
12224 (verilog-decls-get-inputs submodportdecls)
12225 (append (verilog-decls-get-ports submoddecls)
12226 (verilog-decls-get-ports moddecls)))))
12227 (sig-list-o (verilog-signals-in ;; Decls doesn't have data types, must resolve
12228 (verilog-decls-get-vars submoddecls)
12229 (verilog-signals-not-in
12230 (verilog-decls-get-outputs submodportdecls)
12231 (append (verilog-decls-get-ports submoddecls)
12232 (verilog-decls-get-ports moddecls)))))
12233 (sig-list-io (verilog-signals-in ;; Decls doesn't have data types, must resolve
12234 (verilog-decls-get-vars submoddecls)
12235 (verilog-signals-not-in
12236 (verilog-decls-get-inouts submodportdecls)
12237 (append (verilog-decls-get-ports submoddecls)
12238 (verilog-decls-get-ports moddecls))))))
12240 (setq sig-list-i (verilog-signals-edit-wire-reg
12241 (verilog-signals-matching-dir-re
12242 (verilog-signals-matching-regexp sig-list-i regexp)
12243 "input" direction-re))
12244 sig-list-o (verilog-signals-edit-wire-reg
12245 (verilog-signals-matching-dir-re
12246 (verilog-signals-matching-regexp sig-list-o regexp)
12247 "output" direction-re))
12248 sig-list-io (verilog-signals-edit-wire-reg
12249 (verilog-signals-matching-dir-re
12250 (verilog-signals-matching-regexp sig-list-io regexp)
12251 "inout" direction-re)))
12252 (when v2k (verilog-repair-open-comma))
12253 (when (or sig-list-i sig-list-o sig-list-io)
12254 (verilog-insert-indent "// Beginning of automatic in/out/inouts (from modport)\n")
12255 ;; Don't sort them so an upper AUTOINST will match the main module
12256 (verilog-insert-definition modi sig-list-o "output" indent-pt v2k t)
12257 (verilog-insert-definition modi sig-list-io "inout" indent-pt v2k t)
12258 (verilog-insert-definition modi sig-list-i "input" indent-pt v2k t)
12259 (verilog-insert-indent "// End of automatics\n"))
12260 (when v2k (verilog-repair-close-comma)))))))
12262 (defun verilog-auto-insert-lisp ()
12263 "Expand AUTOINSERTLISP statements, as part of \\[verilog-auto].
12264 The Lisp code provided is called, and the Lisp code calls
12265 `insert` to insert text into the current file beginning on the
12266 line after the AUTOINSERTLISP.
12268 See also AUTO_LISP, which takes a Lisp expression and evaluates
12269 it during `verilog-auto-inst' but does not insert any text.
12273 module ExampInsertLisp;
12274 /*AUTOINSERTLISP(my-verilog-insert-hello \"world\")*/
12277 // For this example we declare the function in the
12278 // module's file itself. Often you'd define it instead
12279 // in a site-start.el or init file.
12283 (defun my-verilog-insert-hello (who)
12284 (insert (concat \"initial $write(\\\"hello \" who \"\\\");\\n\")))
12288 Typing \\[verilog-auto] will call my-verilog-insert-hello and
12289 expand the above into:
12291 // Beginning of automatic insert lisp
12292 initial $write(\"hello world\");
12293 // End of automatics
12295 You can also call an external program and insert the returned
12298 /*AUTOINSERTLISP(insert (shell-command-to-string \"echo //hello\"))*/
12299 // Beginning of automatic insert lisp
12301 // End of automatics"
12303 ;; Point is at end of /*AUTO...*/
12304 (let* ((indent-pt (current-indentation))
12305 (cmd-end-pt (save-excursion (search-backward ")")
12307 (point))) ;; Closing paren
12308 (cmd-beg-pt (save-excursion (goto-char cmd-end-pt)
12309 (backward-sexp 1) ;; Inside comment
12310 (point))) ;; Beginning paren
12311 (cmd (buffer-substring-no-properties cmd-beg-pt cmd-end-pt)))
12312 (verilog-forward-or-insert-line)
12313 ;; Some commands don't move point (like insert-file) so we always
12314 ;; add the begin/end comments, then delete it if not needed
12315 (verilog-insert-indent "// Beginning of automatic insert lisp\n")
12316 (verilog-insert-indent "// End of automatics\n")
12320 (setq verilog-scan-cache-tick nil) ;; Clear cache; inserted unknown text
12321 (verilog-delete-empty-auto-pair))))
12323 (defun verilog-auto-sense-sigs (moddecls presense-sigs)
12324 "Return list of signals for current AUTOSENSE block."
12325 (let* ((sigss (verilog-read-always-signals))
12326 (sig-list (verilog-signals-not-params
12327 (verilog-signals-not-in (verilog-alw-get-inputs sigss)
12328 (append (and (not verilog-auto-sense-include-inputs)
12329 (verilog-alw-get-outputs-delayed sigss))
12330 (and (not verilog-auto-sense-include-inputs)
12331 (verilog-alw-get-outputs-immediate sigss))
12332 (verilog-alw-get-temps sigss)
12333 (verilog-decls-get-consts moddecls)
12334 (verilog-decls-get-gparams moddecls)
12338 (defun verilog-auto-sense ()
12339 "Expand AUTOSENSE statements, as part of \\[verilog-auto].
12340 Replace the always (/*AUTOSENSE*/) sensitivity list (/*AS*/ for short)
12341 with one automatically derived from all inputs declared in the always
12342 statement. Signals that are generated within the same always block are NOT
12343 placed into the sensitivity list (see `verilog-auto-sense-include-inputs').
12344 Long lines are split based on the `fill-column', see \\[set-fill-column].
12347 Verilog does not allow memories (multidimensional arrays) in sensitivity
12348 lists. AUTOSENSE will thus exclude them, and add a /*memory or*/ comment.
12351 AUTOSENSE cannot always determine if a `define is a constant or a signal
12352 (it could be in an include file for example). If a `define or other signal
12353 is put into the AUTOSENSE list and is not desired, use the AUTO_CONSTANT
12354 declaration anywhere in the module (parenthesis are required):
12356 /* AUTO_CONSTANT ( `this_is_really_constant_dont_autosense_it ) */
12358 Better yet, use a parameter, which will be understood to be constant
12362 If AUTOSENSE makes a mistake, please report it. (First try putting
12363 a begin/end after your always!) As a workaround, if a signal that
12364 shouldn't be in the sensitivity list was, use the AUTO_CONSTANT above.
12365 If a signal should be in the sensitivity list wasn't, placing it before
12366 the /*AUTOSENSE*/ comment will prevent it from being deleted when the
12367 autos are updated (or added if it occurs there already).
12371 always @ (/*AS*/) begin
12372 /* AUTO_CONSTANT (`constant) */
12373 outin = ina | inb | `constant;
12377 Typing \\[verilog-auto] will make this into:
12379 always @ (/*AS*/ina or inb) begin
12380 /* AUTO_CONSTANT (`constant) */
12381 outin = ina | inb | `constant;
12385 Note in Verilog 2001, you can often get the same result from the new @*
12386 operator. (This was added to the language in part due to AUTOSENSE!)
12389 outin = ina | inb | `constant;
12394 (let* ((start-pt (save-excursion
12395 (verilog-re-search-backward-quick "(" nil t)
12397 (indent-pt (save-excursion
12398 (or (and (goto-char start-pt) (1+ (current-column)))
12399 (current-indentation))))
12400 (modi (verilog-modi-current))
12401 (moddecls (verilog-modi-get-decls modi))
12402 (sig-memories (verilog-signals-memory
12403 (verilog-decls-get-vars moddecls)))
12404 sig-list not-first presense-sigs)
12405 ;; Read signals in always, eliminate outputs from sense list
12406 (setq presense-sigs (verilog-signals-from-signame
12408 (verilog-read-signals start-pt (point)))))
12409 (setq sig-list (verilog-auto-sense-sigs moddecls presense-sigs))
12411 (let ((tlen (length sig-list)))
12412 (setq sig-list (verilog-signals-not-in sig-list sig-memories))
12413 (if (not (eq tlen (length sig-list))) (verilog-insert " /*memory or*/ "))))
12414 (if (and presense-sigs ;; Add a "or" if not "(.... or /*AUTOSENSE*/"
12415 (save-excursion (goto-char (point))
12416 (verilog-re-search-backward-quick "[a-zA-Z0-9$_.%`]+" start-pt t)
12417 (verilog-re-search-backward-quick "\\s-" start-pt t)
12418 (while (looking-at "\\s-`endif")
12419 (verilog-re-search-backward-quick "[a-zA-Z0-9$_.%`]+" start-pt t)
12420 (verilog-re-search-backward-quick "\\s-" start-pt t))
12421 (not (looking-at "\\s-or\\b"))))
12422 (setq not-first t))
12423 (setq sig-list (sort sig-list `verilog-signals-sort-compare))
12425 (cond ((> (+ 4 (current-column) (length (verilog-sig-name (car sig-list)))) fill-column) ;+4 for width of or
12427 (indent-to indent-pt)
12428 (if not-first (insert "or ")))
12429 (not-first (insert " or ")))
12430 (insert (verilog-sig-name (car sig-list)))
12431 (setq sig-list (cdr sig-list)
12434 (defun verilog-auto-reset ()
12435 "Expand AUTORESET statements, as part of \\[verilog-auto].
12436 Replace the /*AUTORESET*/ comment with code to initialize all
12437 registers set elsewhere in the always block.
12440 AUTORESET will not clear memories.
12442 AUTORESET uses <= if the signal has a <= assignment in the block,
12445 If <= is used, all = assigned variables are ignored if
12446 `verilog-auto-reset-blocking-in-non' is nil; they are presumed
12449 /*AUTORESET*/ presumes that any signals mentioned between the previous
12450 begin/case/if statement and the AUTORESET comment are being reset manually
12451 and should not be automatically reset. This includes omitting any signals
12452 used on the right hand side of assignments.
12454 By default, AUTORESET will include the width of the signal in the
12455 autos, SystemVerilog designs may want to change this. To control
12456 this behavior, see `verilog-auto-reset-widths'.
12458 AUTORESET ties signals to deasserted, which is presumed to be zero.
12459 Signals that match `verilog-active-low-regexp' will be deasserted by tying
12464 always @(posedge clk or negedge reset_l) begin
12465 if (!reset_l) begin
12476 Typing \\[verilog-auto] will make this into:
12478 always @(posedge core_clk or negedge reset_l) begin
12479 if (!reset_l) begin
12482 // Beginning of autoreset for uninitialized flops
12484 b = 0; // if `verilog-auto-reset-blocking-in-non' true
12485 // End of automatics
12497 (let* ((indent-pt (current-indentation))
12498 (modi (verilog-modi-current))
12499 (moddecls (verilog-modi-get-decls modi))
12500 (all-list (verilog-decls-get-signals moddecls))
12501 sigss sig-list dly-list prereset-sigs)
12502 ;; Read signals in always, eliminate outputs from reset list
12503 (setq prereset-sigs (verilog-signals-from-signame
12505 (verilog-read-signals
12507 (verilog-re-search-backward-quick "\\(@\\|\\<begin\\>\\|\\<if\\>\\|\\<case\\>\\)" nil t)
12511 (verilog-re-search-backward-quick "@" nil t)
12512 (setq sigss (verilog-read-always-signals)))
12513 (setq dly-list (verilog-alw-get-outputs-delayed sigss))
12514 (setq sig-list (verilog-signals-not-in (append
12515 (verilog-alw-get-outputs-delayed sigss)
12516 (when (or (not (verilog-alw-get-uses-delayed sigss))
12517 verilog-auto-reset-blocking-in-non)
12518 (verilog-alw-get-outputs-immediate sigss)))
12520 (verilog-alw-get-temps sigss)
12522 (setq sig-list (sort sig-list `verilog-signals-sort-compare))
12525 (verilog-insert-indent "// Beginning of autoreset for uninitialized flops\n");
12527 (let ((sig (or (assoc (verilog-sig-name (car sig-list)) all-list) ;; As sig-list has no widths
12529 (indent-to indent-pt)
12530 (insert (verilog-sig-name sig)
12531 (if (assoc (verilog-sig-name sig) dly-list)
12532 (concat " <= " verilog-assignment-delay)
12534 (verilog-sig-tieoff sig)
12536 (setq sig-list (cdr sig-list))))
12537 (verilog-insert-indent "// End of automatics")))))
12539 (defun verilog-auto-tieoff ()
12540 "Expand AUTOTIEOFF statements, as part of \\[verilog-auto].
12541 Replace the /*AUTOTIEOFF*/ comment with code to wire-tie all unused output
12542 signals to deasserted.
12544 /*AUTOTIEOFF*/ is used to make stub modules; modules that have the same
12545 input/output list as another module, but no internals. Specifically, it
12546 finds all outputs in the module, and if that input is not otherwise declared
12547 as a register or wire, creates a tieoff.
12549 AUTORESET ties signals to deasserted, which is presumed to be zero.
12550 Signals that match `verilog-active-low-regexp' will be deasserted by tying
12553 You can add signals you do not want included in AUTOTIEOFF with
12554 `verilog-auto-tieoff-ignore-regexp'.
12556 `verilog-auto-wire-type' may be used to change the datatype of
12559 `verilog-auto-reset-widths' may be used to change how the tieoff
12560 value's width is generated.
12562 An example of making a stub for another module:
12564 module ExampStub (/*AUTOINST*/);
12565 /*AUTOINOUTPARAM(\"Foo\")*/
12566 /*AUTOINOUTMODULE(\"Foo\")*/
12568 // verilator lint_off UNUSED
12569 wire _unused_ok = &{1'b0,
12572 // verilator lint_on UNUSED
12575 Typing \\[verilog-auto] will make this into:
12577 module ExampStub (/*AUTOINST*/...);
12578 /*AUTOINOUTPARAM(\"Foo\")*/
12579 /*AUTOINOUTMODULE(\"Foo\")*/
12580 // Beginning of autotieoff
12582 // End of automatics
12585 // Beginning of autotieoff
12586 wire [2:0] foo = 3'b0;
12587 // End of automatics
12593 (let* ((indent-pt (current-indentation))
12594 (modi (verilog-modi-current))
12595 (moddecls (verilog-modi-get-decls modi))
12596 (modsubdecls (verilog-modi-get-sub-decls modi))
12597 (sig-list (verilog-signals-not-in
12598 (verilog-decls-get-outputs moddecls)
12599 (append (verilog-decls-get-vars moddecls)
12600 (verilog-decls-get-assigns moddecls)
12601 (verilog-decls-get-consts moddecls)
12602 (verilog-decls-get-gparams moddecls)
12603 (verilog-subdecls-get-interfaced modsubdecls)
12604 (verilog-subdecls-get-outputs modsubdecls)
12605 (verilog-subdecls-get-inouts modsubdecls)))))
12606 (setq sig-list (verilog-signals-not-matching-regexp
12607 sig-list verilog-auto-tieoff-ignore-regexp))
12609 (verilog-forward-or-insert-line)
12610 (verilog-insert-indent "// Beginning of automatic tieoffs (for this module's unterminated outputs)\n")
12611 (setq sig-list (sort (copy-alist sig-list) `verilog-signals-sort-compare))
12612 (verilog-modi-cache-add-vars modi sig-list) ; Before we trash list
12614 (let ((sig (car sig-list)))
12615 (cond ((equal verilog-auto-tieoff-declaration "assign")
12616 (indent-to indent-pt)
12617 (insert "assign " (verilog-sig-name sig)))
12619 (verilog-insert-one-definition sig verilog-auto-tieoff-declaration indent-pt)))
12620 (indent-to (max 48 (+ indent-pt 40)))
12621 (insert "= " (verilog-sig-tieoff sig)
12623 (setq sig-list (cdr sig-list))))
12624 (verilog-insert-indent "// End of automatics\n")))))
12626 (defun verilog-auto-undef ()
12627 "Expand AUTOUNDEF statements, as part of \\[verilog-auto].
12628 Take any `defines since the last AUTOUNDEF in the current file
12629 and create `undefs for them. This is used to insure that
12630 file-local defines do not pollute the global `define name space.
12633 AUTOUNDEF presumes any identifier following `define is the
12634 name of a define. Any `ifdefs are ignored.
12636 AUTOUNDEF suppresses creating an `undef for any define that was
12637 `undefed before the AUTOUNDEF. This may be used to work around
12638 the ignoring of `ifdefs as shown below.
12647 `undef M_BAZ // Emacs will see this and not `undef M_BAZ
12652 Typing \\[verilog-auto] will make this into:
12656 // Beginning of automatic undefs
12659 // End of automatics
12661 You may also provide an optional regular expression, in which case only
12662 defines the regular expression will be undefed."
12664 (let* ((params (verilog-read-auto-params 0 1))
12665 (regexp (nth 0 params))
12666 (indent-pt (current-indentation))
12670 ;; Scan from start of file, or last AUTOUNDEF
12671 (or (verilog-re-search-backward-quick "/\\*AUTOUNDEF\\>" end-pt t)
12672 (goto-char (point-min)))
12673 (while (verilog-re-search-forward-quick
12674 "`\\(define\\|undef\\)\\s-*\\([a-zA-Z_][a-zA-Z_0-9]*\\)" end-pt t)
12675 (cond ((equal (match-string-no-properties 1) "define")
12676 (setq def (match-string-no-properties 2))
12677 (when (and (or (not regexp)
12678 (string-match regexp def))
12679 (not (member def defs))) ;; delete-dups not in 21.1
12680 (setq defs (cons def defs))))
12682 (setq defs (delete (match-string-no-properties 2) defs))))))
12684 (setq defs (sort defs 'string<))
12686 (verilog-forward-or-insert-line)
12687 (verilog-insert-indent "// Beginning of automatic undefs\n")
12689 (verilog-insert-indent "`undef " (car defs) "\n")
12690 (setq defs (cdr defs)))
12691 (verilog-insert-indent "// End of automatics\n")))))
12693 (defun verilog-auto-unused ()
12694 "Expand AUTOUNUSED statements, as part of \\[verilog-auto].
12695 Replace the /*AUTOUNUSED*/ comment with a comma separated list of all unused
12696 input and inout signals.
12698 /*AUTOUNUSED*/ is used to make stub modules; modules that have the same
12699 input/output list as another module, but no internals. Specifically, it
12700 finds all inputs and inouts in the module, and if that input is not otherwise
12701 used, adds it to a comma separated list.
12703 The comma separated list is intended to be used to create a _unused_ok
12704 signal. Using the exact name \"_unused_ok\" for name of the temporary
12705 signal is recommended as it will insure maximum forward compatibility, it
12706 also makes lint warnings easy to understand; ignore any unused warnings
12707 with \"unused\" in the signal name.
12709 To reduce simulation time, the _unused_ok signal should be forced to a
12710 constant to prevent wiggling. The easiest thing to do is use a
12711 reduction-and with 1'b0 as shown.
12713 This way all unused signals are in one place, making it convenient to add
12714 your tool's specific pragmas around the assignment to disable any unused
12717 You can add signals you do not want included in AUTOUNUSED with
12718 `verilog-auto-unused-ignore-regexp'.
12720 An example of making a stub for another module:
12722 module ExampStub (/*AUTOINST*/);
12723 /*AUTOINOUTPARAM(\"Examp\")*/
12724 /*AUTOINOUTMODULE(\"Examp\")*/
12726 // verilator lint_off UNUSED
12727 wire _unused_ok = &{1'b0,
12730 // verilator lint_on UNUSED
12733 Typing \\[verilog-auto] will make this into:
12736 // verilator lint_off UNUSED
12737 wire _unused_ok = &{1'b0,
12739 // Beginning of automatics
12743 // End of automatics
12745 // verilator lint_on UNUSED
12750 (let* ((indent-pt (progn (search-backward "/*") (current-column)))
12751 (modi (verilog-modi-current))
12752 (moddecls (verilog-modi-get-decls modi))
12753 (modsubdecls (verilog-modi-get-sub-decls modi))
12754 (sig-list (verilog-signals-not-in
12755 (append (verilog-decls-get-inputs moddecls)
12756 (verilog-decls-get-inouts moddecls))
12757 (append (verilog-subdecls-get-inputs modsubdecls)
12758 (verilog-subdecls-get-inouts modsubdecls)))))
12759 (setq sig-list (verilog-signals-not-matching-regexp
12760 sig-list verilog-auto-unused-ignore-regexp))
12762 (verilog-forward-or-insert-line)
12763 (verilog-insert-indent "// Beginning of automatic unused inputs\n")
12764 (setq sig-list (sort (copy-alist sig-list) `verilog-signals-sort-compare))
12766 (let ((sig (car sig-list)))
12767 (indent-to indent-pt)
12768 (insert (verilog-sig-name sig) ",\n")
12769 (setq sig-list (cdr sig-list))))
12770 (verilog-insert-indent "// End of automatics\n")))))
12772 (defun verilog-enum-ascii (signm elim-regexp)
12773 "Convert an enum name SIGNM to an ascii string for insertion.
12774 Remove user provided prefix ELIM-REGEXP."
12775 (or elim-regexp (setq elim-regexp "_ DONT MATCH IT_"))
12776 (let ((case-fold-search t))
12777 ;; All upper becomes all lower for readability
12778 (downcase (verilog-string-replace-matches elim-regexp "" nil nil signm))))
12780 (defun verilog-auto-ascii-enum ()
12781 "Expand AUTOASCIIENUM statements, as part of \\[verilog-auto].
12782 Create a register to contain the ASCII decode of an enumerated signal type.
12783 This will allow trace viewers to show the ASCII name of states.
12785 First, parameters are built into an enumeration using the synopsys enum
12786 comment. The comment must be between the keyword and the symbol.
12787 \(Annoying, but that's what Synopsys's dc_shell FSM reader requires.)
12789 Next, registers which that enum applies to are also tagged with the same
12792 Finally, an AUTOASCIIENUM command is used.
12794 The first parameter is the name of the signal to be decoded.
12796 The second parameter is the name to store the ASCII code into. For the
12797 signal foo, I suggest the name _foo__ascii, where the leading _ indicates
12798 a signal that is just for simulation, and the magic characters _ascii
12799 tell viewers like Dinotrace to display in ASCII format.
12801 The third optional parameter is a string which will be removed
12802 from the state names. It defaults to \"\" which removes nothing.
12804 The fourth optional parameter is \"onehot\" to force one-hot
12805 decoding. If unspecified, if and only if the first parameter
12806 width is 2^(number of states in enum) and does NOT match the
12807 width of the enum, the signal is assumed to be a one-hot
12808 decode. Otherwise, it's a normal encoded state vector.
12810 `verilog-auto-wire-type' may be used to change the datatype of
12813 \"auto enum\" may be used in place of \"synopsys enum\".
12817 //== State enumeration
12818 parameter [2:0] // synopsys enum state_info
12822 //== State variables
12823 reg [2:0] /* synopsys enum state_info */
12824 state_r; /* synopsys state_vector state_r */
12825 reg [2:0] /* synopsys enum state_info */
12828 /*AUTOASCIIENUM(\"state_r\", \"state_ascii_r\", \"SM_\")*/
12830 Typing \\[verilog-auto] will make this into:
12832 ... same front matter ...
12834 /*AUTOASCIIENUM(\"state_r\", \"state_ascii_r\", \"SM_\")*/
12835 // Beginning of automatic ASCII enum decoding
12836 reg [39:0] state_ascii_r; // Decode of state_r
12837 always @(state_r) begin
12839 SM_IDLE: state_ascii_r = \"idle \";
12840 SM_SEND: state_ascii_r = \"send \";
12841 SM_WAIT1: state_ascii_r = \"wait1\";
12842 default: state_ascii_r = \"%Erro\";
12845 // End of automatics"
12847 (let* ((params (verilog-read-auto-params 2 4))
12848 (undecode-name (nth 0 params))
12849 (ascii-name (nth 1 params))
12850 (elim-regexp (and (nth 2 params)
12851 (not (equal (nth 2 params) ""))
12853 (one-hot-flag (nth 3 params))
12855 (indent-pt (current-indentation))
12856 (modi (verilog-modi-current))
12857 (moddecls (verilog-modi-get-decls modi))
12859 (sig-list-consts (append (verilog-decls-get-consts moddecls)
12860 (verilog-decls-get-gparams moddecls)))
12861 (sig-list-all (verilog-decls-get-iovars moddecls))
12863 (undecode-sig (or (assoc undecode-name sig-list-all)
12864 (error "%s: Signal %s not found in design" (verilog-point-text) undecode-name)))
12865 (undecode-enum (or (verilog-sig-enum undecode-sig)
12866 (error "%s: Signal %s does not have an enum tag" (verilog-point-text) undecode-name)))
12868 (enum-sigs (verilog-signals-not-in
12869 (or (verilog-signals-matching-enum sig-list-consts undecode-enum)
12870 (error "%s: No state definitions for %s" (verilog-point-text) undecode-enum))
12874 (string-match "onehot" (or one-hot-flag ""))
12875 (and ;; width(enum) != width(sig)
12876 (or (not (verilog-sig-bits (car enum-sigs)))
12877 (not (equal (verilog-sig-width (car enum-sigs))
12878 (verilog-sig-width undecode-sig))))
12879 ;; count(enums) == width(sig)
12880 (equal (number-to-string (length enum-sigs))
12881 (verilog-sig-width undecode-sig)))))
12885 ;; Find number of ascii chars needed
12886 (let ((tmp-sigs enum-sigs))
12888 (setq enum-chars (max enum-chars (length (verilog-sig-name (car tmp-sigs))))
12889 ascii-chars (max ascii-chars (length (verilog-enum-ascii
12890 (verilog-sig-name (car tmp-sigs))
12892 tmp-sigs (cdr tmp-sigs))))
12894 (verilog-forward-or-insert-line)
12895 (verilog-insert-indent "// Beginning of automatic ASCII enum decoding\n")
12896 (let ((decode-sig-list (list (list ascii-name (format "[%d:0]" (- (* ascii-chars 8) 1))
12897 (concat "Decode of " undecode-name) nil nil))))
12898 (verilog-insert-definition modi decode-sig-list "reg" indent-pt nil))
12900 (verilog-insert-indent "always @(" undecode-name ") begin\n")
12901 (setq indent-pt (+ indent-pt verilog-indent-level))
12902 (verilog-insert-indent "case ({" undecode-name "})\n")
12903 (setq indent-pt (+ indent-pt verilog-case-indent))
12905 (let ((tmp-sigs enum-sigs)
12906 (chrfmt (format "%%-%ds %s = \"%%-%ds\";\n"
12907 (+ (if one-hot 9 1) (max 8 enum-chars))
12908 ascii-name ascii-chars))
12909 (errname (substring "%Error" 0 (min 6 ascii-chars))))
12911 (verilog-insert-indent
12914 (concat (if one-hot "(")
12915 ;; Use enum-sigs length as that's numeric
12916 ;; verilog-sig-width undecode-sig might not be.
12917 (if one-hot (number-to-string (length enum-sigs)))
12918 ;; We use a shift instead of var[index]
12919 ;; so that a non-one hot value will show as error.
12920 (if one-hot "'b1<<")
12921 (verilog-sig-name (car tmp-sigs))
12922 (if one-hot ")") ":")
12923 (verilog-enum-ascii (verilog-sig-name (car tmp-sigs))
12925 (setq tmp-sigs (cdr tmp-sigs)))
12926 (verilog-insert-indent (format chrfmt "default:" errname)))
12928 (setq indent-pt (- indent-pt verilog-case-indent))
12929 (verilog-insert-indent "endcase\n")
12930 (setq indent-pt (- indent-pt verilog-indent-level))
12931 (verilog-insert-indent "end\n"
12932 "// End of automatics\n"))))
12934 (defun verilog-auto-templated-rel ()
12935 "Replace Templated relative line numbers with absolute line numbers.
12936 Internal use only. This hacks around the line numbers in AUTOINST Templates
12937 being different from the final output's line numbering."
12938 (let ((templateno 0) (template-line (list 0)) (buf-line 1))
12939 ;; Find line number each template is on
12940 ;; Count lines as we go, as otherwise it's O(n^2) to use count-lines
12941 (goto-char (point-min))
12942 (while (not (eobp))
12943 (when (looking-at ".*AUTO_TEMPLATE")
12944 (setq templateno (1+ templateno))
12945 (setq template-line (cons buf-line template-line)))
12946 (setq buf-line (1+ buf-line))
12948 (setq template-line (nreverse template-line))
12949 ;; Replace T# L# with absolute line number
12950 (goto-char (point-min))
12951 (while (re-search-forward " Templated T\\([0-9]+\\) L\\([0-9]+\\)" nil t)
12953 (concat " Templated "
12954 (int-to-string (+ (nth (string-to-number (match-string 1))
12956 (string-to-number (match-string 2)))))
12959 (defun verilog-auto-template-lint ()
12960 "Check AUTO_TEMPLATEs for unused lines.
12961 Enable with `verilog-auto-template-warn-unused'."
12962 (let ((name1 (or (buffer-file-name) (buffer-name))))
12964 (goto-char (point-min))
12965 (while (re-search-forward
12966 "^\\s-*/?\\*?\\s-*[a-zA-Z0-9`_$]+\\s-+AUTO_TEMPLATE" nil t)
12967 (let* ((tpl-info (verilog-read-auto-template-middle))
12968 (tpl-list (aref tpl-info 1))
12969 (tlines (append (nth 0 tpl-list) (nth 1 tpl-list)))
12972 (setq tpl-ass (car tlines)
12973 tlines (cdr tlines))
12975 (unless (or (not (eval-when-compile (fboundp 'make-hash-table))) ;; Not supported, no warning
12976 (not verilog-auto-template-hits)
12977 (gethash (vector (nth 2 tpl-ass) (nth 3 tpl-ass))
12978 verilog-auto-template-hits))
12979 (verilog-warn-error "%s:%d: AUTO_TEMPLATE line unused: \".%s (%s)\""
12981 (+ (elt tpl-ass 3) ;; Template line number
12982 (count-lines (point-min) (point)))
12983 (elt tpl-ass 0) (elt tpl-ass 1))
12991 (defun verilog-auto (&optional inject) ; Use verilog-inject-auto instead of passing an arg
12992 "Expand AUTO statements.
12993 Look for any /*AUTO...*/ commands in the code, as used in
12994 instantiations or argument headers. Update the list of signals
12995 following the /*AUTO...*/ command.
12997 Use \\[verilog-delete-auto] to remove the AUTOs.
12999 Use \\[verilog-diff-auto] to see differences in AUTO expansion.
13001 Use \\[verilog-inject-auto] to insert AUTOs for the first time.
13003 Use \\[verilog-faq] for a pointer to frequently asked questions.
13005 The hooks `verilog-before-auto-hook' and `verilog-auto-hook' are
13006 called before and after this function, respectively.
13009 module ModuleName (/*AUTOARG*/);
13014 InstMod instName #(/*AUTOINSTPARAM*/) (/*AUTOINST*/);
13016 You can also update the AUTOs from the shell using:
13017 emacs --batch <filenames.v> -f verilog-batch-auto
13018 Or fix indentation with:
13019 emacs --batch <filenames.v> -f verilog-batch-indent
13020 Likewise, you can delete or inject AUTOs with:
13021 emacs --batch <filenames.v> -f verilog-batch-delete-auto
13022 emacs --batch <filenames.v> -f verilog-batch-inject-auto
13023 Or check if AUTOs have the same expansion
13024 emacs --batch <filenames.v> -f verilog-batch-diff-auto
13026 Using \\[describe-function], see also:
13027 `verilog-auto-arg' for AUTOARG module instantiations
13028 `verilog-auto-ascii-enum' for AUTOASCIIENUM enumeration decoding
13029 `verilog-auto-assign-modport' for AUTOASSIGNMODPORT assignment to/from modport
13030 `verilog-auto-inout-comp' for AUTOINOUTCOMP copy complemented i/o
13031 `verilog-auto-inout-in' for AUTOINOUTIN inputs for all i/o
13032 `verilog-auto-inout-modport' for AUTOINOUTMODPORT i/o from an interface modport
13033 `verilog-auto-inout-module' for AUTOINOUTMODULE copying i/o from elsewhere
13034 `verilog-auto-inout-param' for AUTOINOUTPARAM copying params from elsewhere
13035 `verilog-auto-inout' for AUTOINOUT making hierarchy inouts
13036 `verilog-auto-input' for AUTOINPUT making hierarchy inputs
13037 `verilog-auto-insert-lisp' for AUTOINSERTLISP insert code from lisp function
13038 `verilog-auto-inst' for AUTOINST instantiation pins
13039 `verilog-auto-star' for AUTOINST .* SystemVerilog pins
13040 `verilog-auto-inst-param' for AUTOINSTPARAM instantiation params
13041 `verilog-auto-logic' for AUTOLOGIC declaring logic signals
13042 `verilog-auto-output' for AUTOOUTPUT making hierarchy outputs
13043 `verilog-auto-output-every' for AUTOOUTPUTEVERY making all outputs
13044 `verilog-auto-reg' for AUTOREG registers
13045 `verilog-auto-reg-input' for AUTOREGINPUT instantiation registers
13046 `verilog-auto-reset' for AUTORESET flop resets
13047 `verilog-auto-sense' for AUTOSENSE always sensitivity lists
13048 `verilog-auto-tieoff' for AUTOTIEOFF output tieoffs
13049 `verilog-auto-undef' for AUTOUNDEF `undef of local `defines
13050 `verilog-auto-unused' for AUTOUNUSED unused inputs/inouts
13051 `verilog-auto-wire' for AUTOWIRE instantiation wires
13053 `verilog-read-defines' for reading `define values
13054 `verilog-read-includes' for reading `includes
13056 If you have bugs with these autos, please file an issue at
13057 URL `http://www.veripool.org/verilog-mode' or contact the AUTOAUTHOR
13058 Wilson Snyder (wsnyder@wsnyder.org)."
13060 (unless noninteractive (message "Updating AUTOs..."))
13061 (if (fboundp 'dinotrace-unannotate-all)
13062 (dinotrace-unannotate-all))
13063 (verilog-save-font-mods
13064 (let ((oldbuf (if (not (buffer-modified-p))
13066 ;; Cache directories; we don't write new files, so can't change
13067 (verilog-dir-cache-preserving t)
13068 ;; Cache current module
13069 (verilog-modi-cache-current-enable t)
13070 (verilog-modi-cache-current-max (point-min)) ; IE it's invalid
13071 verilog-modi-cache-current)
13073 ;; Disable change hooks for speed
13074 ;; This let can't be part of above let; must restore
13075 ;; after-change-functions before font-lock resumes
13076 (verilog-save-no-change-functions
13077 (verilog-save-scan-cache
13079 ;; Wipe cache; otherwise if we AUTOed a block above this one,
13080 ;; we'll misremember we have generated IOs, confusing AUTOOUTPUT
13081 (setq verilog-modi-cache-list nil)
13083 (setq verilog-auto-template-hits nil)
13084 ;; If we're not in verilog-mode, change syntax table so parsing works right
13085 (unless (eq major-mode `verilog-mode) (verilog-mode))
13086 ;; Allow user to customize
13087 (verilog-run-hooks 'verilog-before-auto-hook)
13088 ;; Try to save the user from needing to revert-file to reread file local-variables
13089 (verilog-auto-reeval-locals)
13090 (verilog-read-auto-lisp-present)
13091 (verilog-read-auto-lisp (point-min) (point-max))
13092 (verilog-getopt-flags)
13093 ;; From here on out, we can cache anything we read from disk
13094 (verilog-preserve-dir-cache
13095 ;; These two may seem obvious to do always, but on large includes it can be way too slow
13096 (when verilog-auto-read-includes
13097 (verilog-read-includes)
13098 (verilog-read-defines nil nil t))
13099 ;; Setup variables due to SystemVerilog expansion
13100 (verilog-auto-re-search-do "/\\*AUTOLOGIC\\*/" 'verilog-auto-logic-setup)
13101 ;; This particular ordering is important
13102 ;; INST: Lower modules correct, no internal dependencies, FIRST
13103 (verilog-preserve-modi-cache
13104 ;; Clear existing autos else we'll be screwed by existing ones
13105 (verilog-delete-auto)
13106 ;; Injection if appropriate
13108 (verilog-inject-inst)
13109 (verilog-inject-sense)
13110 (verilog-inject-arg))
13112 ;; Do user inserts first, so their code can insert AUTOs
13113 ;; We may provide an AUTOINSERTLISPLAST if another cleanup pass is needed
13114 (verilog-auto-re-search-do "/\\*AUTOINSERTLISP(.*?)\\*/"
13115 'verilog-auto-insert-lisp)
13116 ;; Expand instances before need the signals the instances input/output
13117 (verilog-auto-re-search-do "/\\*AUTOINSTPARAM\\*/" 'verilog-auto-inst-param)
13118 (verilog-auto-re-search-do "/\\*AUTOINST\\*/" 'verilog-auto-inst)
13119 (verilog-auto-re-search-do "\\.\\*" 'verilog-auto-star)
13120 ;; Doesn't matter when done, but combine it with a common changer
13121 (verilog-auto-re-search-do "/\\*\\(AUTOSENSE\\|AS\\)\\*/" 'verilog-auto-sense)
13122 (verilog-auto-re-search-do "/\\*AUTORESET\\*/" 'verilog-auto-reset)
13123 ;; Must be done before autoin/out as creates a reg
13124 (verilog-auto-re-search-do "/\\*AUTOASCIIENUM(.*?)\\*/" 'verilog-auto-ascii-enum)
13126 ;; first in/outs from other files
13127 (verilog-auto-re-search-do "/\\*AUTOINOUTMODPORT(.*?)\\*/" 'verilog-auto-inout-modport)
13128 (verilog-auto-re-search-do "/\\*AUTOINOUTMODULE(.*?)\\*/" 'verilog-auto-inout-module)
13129 (verilog-auto-re-search-do "/\\*AUTOINOUTCOMP(.*?)\\*/" 'verilog-auto-inout-comp)
13130 (verilog-auto-re-search-do "/\\*AUTOINOUTIN(.*?)\\*/" 'verilog-auto-inout-in)
13131 (verilog-auto-re-search-do "/\\*AUTOINOUTPARAM(.*?)\\*/" 'verilog-auto-inout-param)
13132 ;; next in/outs which need previous sucked inputs first
13133 (verilog-auto-re-search-do "/\\*AUTOOUTPUT\\((.*?)\\)?\\*/" 'verilog-auto-output)
13134 (verilog-auto-re-search-do "/\\*AUTOINPUT\\((.*?)\\)?\\*/" 'verilog-auto-input)
13135 (verilog-auto-re-search-do "/\\*AUTOINOUT\\((.*?)\\)?\\*/" 'verilog-auto-inout)
13136 ;; Then tie off those in/outs
13137 (verilog-auto-re-search-do "/\\*AUTOTIEOFF\\*/" 'verilog-auto-tieoff)
13138 ;; These can be anywhere after AUTOINSERTLISP
13139 (verilog-auto-re-search-do "/\\*AUTOUNDEF\\((.*?)\\)?\\*/" 'verilog-auto-undef)
13140 ;; Wires/regs must be after inputs/outputs
13141 (verilog-auto-re-search-do "/\\*AUTOASSIGNMODPORT(.*?)\\*/" 'verilog-auto-assign-modport)
13142 (verilog-auto-re-search-do "/\\*AUTOLOGIC\\*/" 'verilog-auto-logic)
13143 (verilog-auto-re-search-do "/\\*AUTOWIRE\\*/" 'verilog-auto-wire)
13144 (verilog-auto-re-search-do "/\\*AUTOREG\\*/" 'verilog-auto-reg)
13145 (verilog-auto-re-search-do "/\\*AUTOREGINPUT\\*/" 'verilog-auto-reg-input)
13146 ;; outputevery needs AUTOOUTPUTs done first
13147 (verilog-auto-re-search-do "/\\*AUTOOUTPUTEVERY\\*/" 'verilog-auto-output-every)
13148 ;; After we've created all new variables
13149 (verilog-auto-re-search-do "/\\*AUTOUNUSED\\*/" 'verilog-auto-unused)
13150 ;; Must be after all inputs outputs are generated
13151 (verilog-auto-re-search-do "/\\*AUTOARG\\*/" 'verilog-auto-arg)
13152 ;; Fix line numbers (comments only)
13153 (when verilog-auto-inst-template-numbers
13154 (verilog-auto-templated-rel))
13155 (when verilog-auto-template-warn-unused
13156 (verilog-auto-template-lint))))
13158 (verilog-run-hooks 'verilog-auto-hook)
13160 (when verilog-auto-delete-trailing-whitespace
13161 (verilog-delete-trailing-whitespace))
13163 (set (make-local-variable 'verilog-auto-update-tick) (buffer-chars-modified-tick))
13165 ;; If end result is same as when started, clear modified flag
13166 (cond ((and oldbuf (equal oldbuf (buffer-string)))
13167 (set-buffer-modified-p nil)
13168 (unless noninteractive (message "Updating AUTOs...done (no changes)")))
13169 (t (unless noninteractive (message "Updating AUTOs...done"))))
13170 ;; End of after-change protection
13173 ;; Currently handled in verilog-save-font-mods
13178 ;; Skeleton based code insertion
13180 (defvar verilog-template-map
13181 (let ((map (make-sparse-keymap)))
13182 (define-key map "a" 'verilog-sk-always)
13183 (define-key map "b" 'verilog-sk-begin)
13184 (define-key map "c" 'verilog-sk-case)
13185 (define-key map "f" 'verilog-sk-for)
13186 (define-key map "g" 'verilog-sk-generate)
13187 (define-key map "h" 'verilog-sk-header)
13188 (define-key map "i" 'verilog-sk-initial)
13189 (define-key map "j" 'verilog-sk-fork)
13190 (define-key map "m" 'verilog-sk-module)
13191 (define-key map "o" 'verilog-sk-ovm-class)
13192 (define-key map "p" 'verilog-sk-primitive)
13193 (define-key map "r" 'verilog-sk-repeat)
13194 (define-key map "s" 'verilog-sk-specify)
13195 (define-key map "t" 'verilog-sk-task)
13196 (define-key map "u" 'verilog-sk-uvm-class)
13197 (define-key map "w" 'verilog-sk-while)
13198 (define-key map "x" 'verilog-sk-casex)
13199 (define-key map "z" 'verilog-sk-casez)
13200 (define-key map "?" 'verilog-sk-if)
13201 (define-key map ":" 'verilog-sk-else-if)
13202 (define-key map "/" 'verilog-sk-comment)
13203 (define-key map "A" 'verilog-sk-assign)
13204 (define-key map "F" 'verilog-sk-function)
13205 (define-key map "I" 'verilog-sk-input)
13206 (define-key map "O" 'verilog-sk-output)
13207 (define-key map "S" 'verilog-sk-state-machine)
13208 (define-key map "=" 'verilog-sk-inout)
13209 (define-key map "W" 'verilog-sk-wire)
13210 (define-key map "R" 'verilog-sk-reg)
13211 (define-key map "D" 'verilog-sk-define-signal)
13213 "Keymap used in Verilog mode for smart template operations.")
13217 ;; Place the templates into Verilog Mode. They may be inserted under any key.
13218 ;; C-c C-t will be the default. If you use templates a lot, you
13219 ;; may want to consider moving the binding to another key in your init
13222 ;; Note \C-c and letter are reserved for users
13223 (define-key verilog-mode-map "\C-c\C-t" verilog-template-map)
13225 ;;; ---- statement skeletons ------------------------------------------
13227 (define-skeleton verilog-sk-prompt-condition
13228 "Prompt for the loop condition."
13229 "[condition]: " str )
13231 (define-skeleton verilog-sk-prompt-init
13232 "Prompt for the loop init statement."
13233 "[initial statement]: " str )
13235 (define-skeleton verilog-sk-prompt-inc
13236 "Prompt for the loop increment statement."
13237 "[increment statement]: " str )
13239 (define-skeleton verilog-sk-prompt-name
13240 "Prompt for the name of something."
13243 (define-skeleton verilog-sk-prompt-clock
13244 "Prompt for the name of something."
13245 "name and edge of clock(s): " str)
13247 (defvar verilog-sk-reset nil)
13248 (defun verilog-sk-prompt-reset ()
13249 "Prompt for the name of a state machine reset."
13250 (setq verilog-sk-reset (read-string "name of reset: " "rst")))
13253 (define-skeleton verilog-sk-prompt-state-selector
13254 "Prompt for the name of a state machine selector."
13255 "name of selector (eg {a,b,c,d}): " str )
13257 (define-skeleton verilog-sk-prompt-output
13258 "Prompt for the name of something."
13261 (define-skeleton verilog-sk-prompt-msb
13262 "Prompt for most significant bit specification."
13263 "msb:" str & ?: & '(verilog-sk-prompt-lsb) | -1 )
13265 (define-skeleton verilog-sk-prompt-lsb
13266 "Prompt for least significant bit specification."
13269 (defvar verilog-sk-p nil)
13270 (define-skeleton verilog-sk-prompt-width
13271 "Prompt for a width specification."
13274 (setq verilog-sk-p (point))
13275 (verilog-sk-prompt-msb)
13276 (if (> (point) verilog-sk-p) "] " " ")))
13278 (defun verilog-sk-header ()
13279 "Insert a descriptive header at the top of the file.
13280 See also `verilog-header' for an alternative format."
13283 (goto-char (point-min))
13284 (verilog-sk-header-tmpl)))
13286 (define-skeleton verilog-sk-header-tmpl
13287 "Insert a comment block containing the module title, author, etc."
13289 "// -*- Mode: Verilog -*-"
13290 "\n// Filename : " (buffer-name)
13291 "\n// Description : " str
13292 "\n// Author : " (user-full-name)
13293 "\n// Created On : " (current-time-string)
13294 "\n// Last Modified By: " (user-full-name)
13295 "\n// Last Modified On: " (current-time-string)
13296 "\n// Update Count : 0"
13297 "\n// Status : Unknown, Use with caution!"
13300 (define-skeleton verilog-sk-module
13301 "Insert a module definition."
13303 > "module " '(verilog-sk-prompt-name) " (/*AUTOARG*/ ) ;" \n
13305 > (- verilog-indent-level-behavioral) "endmodule" (progn (electric-verilog-terminate-line) nil))
13307 ;;; ------------------------------------------------------------------------
13308 ;;; Define a default OVM class, with macros and new()
13309 ;;; ------------------------------------------------------------------------
13311 (define-skeleton verilog-sk-ovm-class
13312 "Insert a class definition"
13314 > "class " (setq name (skeleton-read "Name: ")) " extends " (skeleton-read "Extends: ") ";" \n
13316 > "`ovm_object_utils_begin(" name ")" \n
13317 > (- verilog-indent-level) " `ovm_object_utils_end" \n
13319 > "function new(name=\"" name "\");" \n
13320 > "super.new(name);" \n
13321 > (- verilog-indent-level) "endfunction" \n
13323 > "endclass" (progn (electric-verilog-terminate-line) nil))
13325 (define-skeleton verilog-sk-uvm-class
13326 "Insert a class definition"
13328 > "class " (setq name (skeleton-read "Name: ")) " extends " (skeleton-read "Extends: ") ";" \n
13330 > "`uvm_object_utils_begin(" name ")" \n
13331 > (- verilog-indent-level) " `uvm_object_utils_end" \n
13333 > "function new(name=\"" name "\");" \n
13334 > "super.new(name);" \n
13335 > (- verilog-indent-level) "endfunction" \n
13337 > "endclass" (progn (electric-verilog-terminate-line) nil))
13339 (define-skeleton verilog-sk-primitive
13340 "Insert a task definition."
13342 > "primitive " '(verilog-sk-prompt-name) " ( " '(verilog-sk-prompt-output) ("input:" ", " str ) " );"\n
13344 > (- verilog-indent-level-behavioral) "endprimitive" (progn (electric-verilog-terminate-line) nil))
13346 (define-skeleton verilog-sk-task
13347 "Insert a task definition."
13349 > "task " '(verilog-sk-prompt-name) & ?; \n
13353 > (- verilog-indent-level-behavioral) "end" \n
13354 > (- verilog-indent-level-behavioral) "endtask" (progn (electric-verilog-terminate-line) nil))
13356 (define-skeleton verilog-sk-function
13357 "Insert a function definition."
13359 > "function [" '(verilog-sk-prompt-width) | -1 '(verilog-sk-prompt-name) ?; \n
13363 > (- verilog-indent-level-behavioral) "end" \n
13364 > (- verilog-indent-level-behavioral) "endfunction" (progn (electric-verilog-terminate-line) nil))
13366 (define-skeleton verilog-sk-always
13367 "Insert always block. Uses the minibuffer to prompt
13368 for sensitivity list."
13370 > "always @ ( /*AUTOSENSE*/ ) begin\n"
13372 > (- verilog-indent-level-behavioral) "end" \n >
13375 (define-skeleton verilog-sk-initial
13376 "Insert an initial block."
13378 > "initial begin\n"
13380 > (- verilog-indent-level-behavioral) "end" \n > )
13382 (define-skeleton verilog-sk-specify
13383 "Insert specify block. "
13387 > (- verilog-indent-level-behavioral) "endspecify" \n > )
13389 (define-skeleton verilog-sk-generate
13390 "Insert generate block. "
13394 > (- verilog-indent-level-behavioral) "endgenerate" \n > )
13396 (define-skeleton verilog-sk-begin
13397 "Insert begin end block. Uses the minibuffer to prompt for name."
13399 > "begin" '(verilog-sk-prompt-name) \n
13401 > (- verilog-indent-level-behavioral) "end"
13404 (define-skeleton verilog-sk-fork
13405 "Insert a fork join block."
13410 > (- verilog-indent-level-behavioral) "end" \n
13413 > (- verilog-indent-level-behavioral) "end" \n
13414 > (- verilog-indent-level-behavioral) "join" \n
13418 (define-skeleton verilog-sk-case
13419 "Build skeleton case statement, prompting for the selector expression,
13420 and the case items."
13421 "[selector expression]: "
13422 > "case (" str ") " \n
13423 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n > )
13424 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil))
13426 (define-skeleton verilog-sk-casex
13427 "Build skeleton casex statement, prompting for the selector expression,
13428 and the case items."
13429 "[selector expression]: "
13430 > "casex (" str ") " \n
13431 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n > )
13432 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil))
13434 (define-skeleton verilog-sk-casez
13435 "Build skeleton casez statement, prompting for the selector expression,
13436 and the case items."
13437 "[selector expression]: "
13438 > "casez (" str ") " \n
13439 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n > )
13440 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil))
13442 (define-skeleton verilog-sk-if
13443 "Insert a skeleton if statement."
13444 > "if (" '(verilog-sk-prompt-condition) & ")" " begin" \n
13446 > (- verilog-indent-level-behavioral) "end " \n )
13448 (define-skeleton verilog-sk-else-if
13449 "Insert a skeleton else if statement."
13450 > (verilog-indent-line) "else if ("
13451 (progn (setq verilog-sk-p (point)) nil) '(verilog-sk-prompt-condition) (if (> (point) verilog-sk-p) ") " -1 ) & " begin" \n
13453 > "end" (progn (electric-verilog-terminate-line) nil))
13455 (define-skeleton verilog-sk-datadef
13456 "Common routine to get data definition."
13458 '(verilog-sk-prompt-width) | -1 ("name (RET to end):" str ", ") -2 ";" \n)
13460 (define-skeleton verilog-sk-input
13461 "Insert an input definition."
13463 > "input [" '(verilog-sk-datadef))
13465 (define-skeleton verilog-sk-output
13466 "Insert an output definition."
13468 > "output [" '(verilog-sk-datadef))
13470 (define-skeleton verilog-sk-inout
13471 "Insert an inout definition."
13473 > "inout [" '(verilog-sk-datadef))
13475 (defvar verilog-sk-signal nil)
13476 (define-skeleton verilog-sk-def-reg
13477 "Insert a reg definition."
13479 > "reg [" '(verilog-sk-prompt-width) | -1 verilog-sk-signal ";" \n (verilog-pretty-declarations-auto) )
13481 (defun verilog-sk-define-signal ()
13482 "Insert a definition of signal under point at top of module."
13484 (let* ((sig-re "[a-zA-Z0-9_]*")
13485 (v1 (buffer-substring
13487 (skip-chars-backward sig-re)
13490 (skip-chars-forward sig-re)
13492 (if (not (member v1 verilog-keywords))
13494 (setq verilog-sk-signal v1)
13495 (verilog-beg-of-defun)
13496 (verilog-end-of-statement)
13497 (verilog-forward-syntactic-ws)
13498 (verilog-sk-def-reg)
13499 (message "signal at point is %s" v1))
13500 (message "object at point (%s) is a keyword" v1))))
13502 (define-skeleton verilog-sk-wire
13503 "Insert a wire definition."
13505 > "wire [" '(verilog-sk-datadef))
13507 (define-skeleton verilog-sk-reg
13508 "Insert a reg definition."
13510 > "reg [" '(verilog-sk-datadef))
13512 (define-skeleton verilog-sk-assign
13513 "Insert a skeleton assign statement."
13515 > "assign " '(verilog-sk-prompt-name) " = " _ ";" \n)
13517 (define-skeleton verilog-sk-while
13518 "Insert a skeleton while loop statement."
13520 > "while (" '(verilog-sk-prompt-condition) ") begin" \n
13522 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil))
13524 (define-skeleton verilog-sk-repeat
13525 "Insert a skeleton repeat loop statement."
13527 > "repeat (" '(verilog-sk-prompt-condition) ") begin" \n
13529 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil))
13531 (define-skeleton verilog-sk-for
13532 "Insert a skeleton while loop statement."
13535 '(verilog-sk-prompt-init) "; "
13536 '(verilog-sk-prompt-condition) "; "
13537 '(verilog-sk-prompt-inc)
13540 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil))
13542 (define-skeleton verilog-sk-comment
13543 "Inserts three comment lines, making a display comment."
13549 (define-skeleton verilog-sk-state-machine
13550 "Insert a state machine definition."
13551 "Name of state variable: "
13552 '(setq input "state")
13553 > "// State registers for " str | -23 \n
13554 '(setq verilog-sk-state str)
13555 > "reg [" '(verilog-sk-prompt-width) | -1 verilog-sk-state ", next_" verilog-sk-state ?; \n
13558 > "// State FF for " verilog-sk-state \n
13559 > "always @ ( " (read-string "clock:" "posedge clk") " or " (verilog-sk-prompt-reset) " ) begin" \n
13560 > "if ( " verilog-sk-reset " ) " verilog-sk-state " = 0; else" \n
13561 > verilog-sk-state " = next_" verilog-sk-state ?; \n
13562 > (- verilog-indent-level-behavioral) "end" (progn (electric-verilog-terminate-line) nil)
13564 > "// Next State Logic for " verilog-sk-state \n
13565 > "always @ ( /*AUTOSENSE*/ ) begin\n"
13566 > "case (" '(verilog-sk-prompt-state-selector) ") " \n
13567 > ("case selector: " str ": begin" \n > "next_" verilog-sk-state " = " _ ";" \n > (- verilog-indent-level-behavioral) "end" \n )
13568 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil)
13569 > (- verilog-indent-level-behavioral) "end" (progn (electric-verilog-terminate-line) nil))
13573 ;; Include file loading with mouse/return event
13575 ;; idea & first impl.: M. Rouat (eldo-mode.el)
13576 ;; second (emacs/xemacs) impl.: G. Van der Plas (spice-mode.el)
13578 (if (featurep 'xemacs)
13579 (require 'overlay))
13581 (defconst verilog-include-file-regexp
13582 "^`include\\s-+\"\\([^\n\"]*\\)\""
13583 "Regexp that matches the include file.")
13585 (defvar verilog-mode-mouse-map
13586 (let ((map (make-sparse-keymap))) ; as described in info pages, make a map
13587 (set-keymap-parent map verilog-mode-map)
13588 ;; mouse button bindings
13589 (define-key map "\r" 'verilog-load-file-at-point)
13590 (if (featurep 'xemacs)
13591 (define-key map 'button2 'verilog-load-file-at-mouse);ffap-at-mouse ?
13592 (define-key map [mouse-2] 'verilog-load-file-at-mouse))
13593 (if (featurep 'xemacs)
13594 (define-key map 'Sh-button2 'mouse-yank) ; you wanna paste don't you ?
13595 (define-key map [S-mouse-2] 'mouse-yank-at-click))
13597 "Map containing mouse bindings for `verilog-mode'.")
13600 (defun verilog-highlight-region (beg end old-len)
13601 "Colorize included files and modules in the (changed?) region.
13602 Clicking on the middle-mouse button loads them in a buffer (as in dired)."
13603 (when (or verilog-highlight-includes
13604 verilog-highlight-modules)
13606 (save-match-data ;; A query-replace may call this function - do not disturb
13607 (verilog-save-buffer-state
13608 (verilog-save-scan-cache
13611 (setq end-point (point-at-eol))
13613 (beginning-of-line) ; scan entire line
13614 ;; delete overlays existing on this line
13615 (let ((overlays (overlays-in (point) end-point)))
13618 (overlay-get (car overlays) 'detachable)
13619 (or (overlay-get (car overlays) 'verilog-include-file)
13620 (overlay-get (car overlays) 'verilog-inst-module)))
13621 (delete-overlay (car overlays)))
13622 (setq overlays (cdr overlays))))
13624 ;; make new include overlays
13625 (when verilog-highlight-includes
13626 (while (search-forward-regexp verilog-include-file-regexp end-point t)
13627 (goto-char (match-beginning 1))
13628 (let ((ov (make-overlay (match-beginning 1) (match-end 1))))
13629 (overlay-put ov 'start-closed 't)
13630 (overlay-put ov 'end-closed 't)
13631 (overlay-put ov 'evaporate 't)
13632 (overlay-put ov 'verilog-include-file 't)
13633 (overlay-put ov 'mouse-face 'highlight)
13634 (overlay-put ov 'local-map verilog-mode-mouse-map))))
13636 ;; make new module overlays
13638 ;; This scanner is syntax-fragile, so don't get bent
13639 (when verilog-highlight-modules
13640 (condition-case nil
13641 (while (verilog-re-search-forward-quick "\\(/\\*AUTOINST\\*/\\|\\.\\*\\)" end-point t)
13643 (goto-char (match-beginning 0))
13644 (unless (verilog-inside-comment-or-string-p)
13645 (verilog-read-inst-module-matcher) ;; sets match 0
13646 (let* ((ov (make-overlay (match-beginning 0) (match-end 0))))
13647 (overlay-put ov 'start-closed 't)
13648 (overlay-put ov 'end-closed 't)
13649 (overlay-put ov 'evaporate 't)
13650 (overlay-put ov 'verilog-inst-module 't)
13651 (overlay-put ov 'mouse-face 'highlight)
13652 (overlay-put ov 'local-map verilog-mode-mouse-map)))))
13655 ;; Future highlights:
13656 ;; variables - make an Occur buffer of where referenced
13657 ;; pins - make an Occur buffer of the sig in the declaration module
13660 (defun verilog-highlight-buffer ()
13661 "Colorize included files and modules across the whole buffer."
13662 ;; Invoked via verilog-mode calling font-lock then `font-lock-mode-hook'
13664 ;; delete and remake overlays
13665 (verilog-highlight-region (point-min) (point-max) nil))
13667 ;; Deprecated, but was interactive, so we'll keep it around
13668 (defalias 'verilog-colorize-include-files-buffer 'verilog-highlight-buffer)
13670 ;; ffap-at-mouse isn't useful for Verilog mode. It uses library paths.
13671 ;; so define this function to do more or less the same as ffap-at-mouse
13672 ;; but first resolve filename...
13673 (defun verilog-load-file-at-mouse (event)
13674 "Load file under button 2 click's EVENT.
13675 Files are checked based on `verilog-library-flags'."
13677 (save-excursion ;; implement a Verilog specific ffap-at-mouse
13678 (mouse-set-point event)
13679 (verilog-load-file-at-point t)))
13681 ;; ffap isn't usable for Verilog mode. It uses library paths.
13682 ;; so define this function to do more or less the same as ffap
13683 ;; but first resolve filename...
13684 (defun verilog-load-file-at-point (&optional warn)
13685 "Load file under point.
13686 If WARN, throw warning if not found.
13687 Files are checked based on `verilog-library-flags'."
13689 (save-excursion ;; implement a Verilog specific ffap
13690 (let ((overlays (overlays-in (point) (point)))
13692 (while (and overlays (not hit))
13693 (when (overlay-get (car overlays) 'verilog-inst-module)
13694 (verilog-goto-defun-file (buffer-substring
13695 (overlay-start (car overlays))
13696 (overlay-end (car overlays))))
13698 (setq overlays (cdr overlays)))
13700 (beginning-of-line)
13701 (when (and (not hit)
13702 (looking-at verilog-include-file-regexp))
13703 (if (and (car (verilog-library-filenames
13704 (match-string 1) (buffer-file-name)))
13705 (file-readable-p (car (verilog-library-filenames
13706 (match-string 1) (buffer-file-name)))))
13707 (find-file (car (verilog-library-filenames
13708 (match-string 1) (buffer-file-name))))
13711 "File '%s' isn't readable, use shift-mouse2 to paste in this field"
13712 (match-string 1))))))))
13718 (defun verilog-faq ()
13719 "Tell the user their current version, and where to get the FAQ etc."
13721 (with-output-to-temp-buffer "*verilog-mode help*"
13722 (princ (format "You are using verilog-mode %s\n" verilog-mode-version))
13724 (princ "For new releases, see http://www.verilog.com\n")
13726 (princ "For frequently asked questions, see http://www.veripool.org/verilog-mode-faq.html\n")
13728 (princ "To submit a bug, use M-x verilog-submit-bug-report\n")
13731 (autoload 'reporter-submit-bug-report "reporter")
13732 (defvar reporter-prompt-for-summary-p)
13734 (defun verilog-submit-bug-report ()
13735 "Submit via mail a bug report on verilog-mode.el."
13737 (let ((reporter-prompt-for-summary-p t))
13738 (reporter-submit-bug-report
13739 "mac@verilog.com, wsnyder@wsnyder.org"
13740 (concat "verilog-mode v" verilog-mode-version)
13742 verilog-active-low-regexp
13743 verilog-after-save-font-hook
13744 verilog-align-ifelse
13745 verilog-assignment-delay
13746 verilog-auto-arg-sort
13747 verilog-auto-declare-nettype
13748 verilog-auto-delete-trailing-whitespace
13749 verilog-auto-endcomments
13751 verilog-auto-ignore-concat
13752 verilog-auto-indent-on-newline
13753 verilog-auto-inout-ignore-regexp
13754 verilog-auto-input-ignore-regexp
13755 verilog-auto-inst-column
13756 verilog-auto-inst-dot-name
13757 verilog-auto-inst-interfaced-ports
13758 verilog-auto-inst-param-value
13759 verilog-auto-inst-sort
13760 verilog-auto-inst-template-numbers
13761 verilog-auto-inst-vector
13762 verilog-auto-lineup
13763 verilog-auto-newline
13764 verilog-auto-output-ignore-regexp
13765 verilog-auto-read-includes
13766 verilog-auto-reset-blocking-in-non
13767 verilog-auto-reset-widths
13768 verilog-auto-save-policy
13769 verilog-auto-sense-defines-constant
13770 verilog-auto-sense-include-inputs
13771 verilog-auto-star-expand
13772 verilog-auto-star-save
13773 verilog-auto-template-warn-unused
13774 verilog-auto-tieoff-declaration
13775 verilog-auto-tieoff-ignore-regexp
13776 verilog-auto-unused-ignore-regexp
13777 verilog-auto-wire-type
13778 verilog-before-auto-hook
13779 verilog-before-delete-auto-hook
13780 verilog-before-getopt-flags-hook
13781 verilog-before-save-font-hook
13782 verilog-cache-enabled
13783 verilog-case-indent
13784 verilog-cexp-indent
13787 verilog-delete-auto-hook
13788 verilog-getopt-flags-hook
13789 verilog-highlight-grouping-keywords
13790 verilog-highlight-includes
13791 verilog-highlight-modules
13792 verilog-highlight-p1800-keywords
13793 verilog-highlight-translate-off
13794 verilog-indent-begin-after-if
13795 verilog-indent-declaration-macros
13796 verilog-indent-level
13797 verilog-indent-level-behavioral
13798 verilog-indent-level-declaration
13799 verilog-indent-level-directive
13800 verilog-indent-level-module
13801 verilog-indent-lists
13802 verilog-library-directories
13803 verilog-library-extensions
13804 verilog-library-files
13805 verilog-library-flags
13807 verilog-minimum-comment-distance
13809 verilog-mode-release-date
13810 verilog-mode-release-emacs
13811 verilog-mode-version
13812 verilog-preprocessor
13814 verilog-tab-always-indent
13815 verilog-tab-to-comment
13816 verilog-typedef-regexp
13822 I want to report a bug.
13824 Before I go further, I want to say that Verilog mode has changed my life.
13825 I save so much time, my files are colored nicely, my co workers respect
13826 my coding ability... until now. I'd really appreciate anything you
13827 could do to help me out with this minor deficiency in the product.
13829 I've taken a look at the Verilog-Mode FAQ at
13830 http://www.veripool.org/verilog-mode-faq.html.
13832 And, I've considered filing the bug on the issue tracker at
13833 http://www.veripool.org/verilog-mode-bugs
13834 since I realize that public bugs are easier for you to track,
13835 and for others to search, but would prefer to email.
13837 So, to reproduce the bug, start a fresh Emacs via " invocation-name "
13838 -no-init-file -no-site-file'. In a new buffer, in Verilog mode, type
13839 the code included below.
13841 Given those lines, I expected [[Fill in here]] to happen;
13842 but instead, [[Fill in here]] happens!.
13844 == The code: =="))))
13846 (provide 'verilog-mode)
13848 ;; Local Variables:
13849 ;; checkdoc-permit-comma-termination-flag:t
13850 ;; checkdoc-force-docstrings-flag:nil
13853 ;;; verilog-mode.el ends here