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0a2d0bd4 JB |
1 | ;;; mixal-mode.el --- Major mode for the mix asm language. |
2 | ||
ba318903 | 3 | ;; Copyright (C) 2003-2014 Free Software Foundation, Inc. |
0a2d0bd4 | 4 | |
f8b4fcda SM |
5 | ;; Author: Pieter E.J. Pareit <pieter.pareit@gmail.com> |
6 | ;; Maintainer: Pieter E.J. Pareit <pieter.pareit@gmail.com> | |
0a2d0bd4 JB |
7 | ;; Created: 09 Nov 2002 |
8 | ;; Version: 0.1 | |
88f4758e | 9 | ;; Keywords: languages, Knuth, mix, mixal, asm, mixvm, The Art Of Computer Programming |
0a2d0bd4 | 10 | |
1a484753 GM |
11 | ;; This file is part of GNU Emacs. |
12 | ||
b1fc2b50 | 13 | ;; GNU Emacs is free software: you can redistribute it and/or modify |
1a484753 | 14 | ;; it under the terms of the GNU General Public License as published by |
b1fc2b50 GM |
15 | ;; the Free Software Foundation, either version 3 of the License, or |
16 | ;; (at your option) any later version. | |
1a484753 GM |
17 | |
18 | ;; GNU Emacs is distributed in the hope that it will be useful, | |
19 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | ;; GNU General Public License for more details. | |
22 | ||
23 | ;; You should have received a copy of the GNU General Public License | |
b1fc2b50 | 24 | ;; along with GNU Emacs. If not, see <http://www.gnu.org/licenses/>. |
1a484753 | 25 | |
0a2d0bd4 JB |
26 | ;;; Commentary: |
27 | ;; Major mode for the mix asm language. | |
28 | ;; The mix asm language is described in "The Art Of Computer Programming". | |
29 | ;; | |
f8b4fcda SM |
30 | ;; For optimal use, also use GNU MDK. Compiling needs mixasm, running |
31 | ;; and debugging needs mixvm and mixvm.el from GNU MDK. You can get | |
0a2d0bd4 JB |
32 | ;; GNU MDK from `https://savannah.gnu.org/projects/mdk/' and |
33 | ;; `ftp://ftp.gnu.org/pub/gnu/mdk'. | |
34 | ;; | |
865fe16f | 35 | ;; To use this mode, place the following in your init file: |
0a2d0bd4 JB |
36 | ;; `(load-file "/PATH-TO-FILE/mixal-mode.el")'. |
37 | ;; When you load a file with the extension .mixal the mode will be started | |
f8b4fcda SM |
38 | ;; automatic. If you want to start the mode manual, use `M-x mixal-mode'. |
39 | ;; Font locking will work, the behavior of tabs is the same as Emacs's | |
40 | ;; default behavior. You can compile a source file with `C-c c' you can | |
0a2d0bd4 JB |
41 | ;; run a compiled file with `C-c r' or run it in debug mode with `C-c d'. |
42 | ;; You can get more information about a particular operation code by using | |
43 | ;; mixal-describe-operation-code or `C-h o'. | |
44 | ;; | |
45 | ;; Have fun. | |
46 | ||
47 | ;;; History: | |
f8b4fcda | 48 | ;; Version 0.3: |
0471d426 SM |
49 | ;; 12/10/05: Stefan Monnier <monnier@iro.umontreal.ca> |
50 | ;; Use font-lock-syntactic-keywords to detect/mark comments. | |
51 | ;; Use [^ \t\n]+ to match the operand part of a line. | |
52 | ;; Drop mixal-operation-codes. | |
53 | ;; Build the mixal-operation-codes-alist immediately. | |
54 | ;; Use `interactive' in mixal-describe-operation-code. | |
55 | ;; Remove useless ".*$" at the end of some regexps. | |
56 | ;; Fix the definition of comment-start-skip. | |
f8b4fcda SM |
57 | ;; 08/10/05: sync mdk and emacs cvs |
58 | ;; from emacs: compile-command and require-final-newline | |
59 | ;; from mdk: see version 0.2 | |
60 | ;; correct my email address | |
61 | ;; Version 0.2: | |
62 | ;; 06/04/05: mixasm no longer needs -g option | |
63 | ;; fontlocking of comments works in all? cases now | |
64 | ;; added some more mixal-operation-codes | |
0a2d0bd4 JB |
65 | ;; Version 0.1: |
66 | ;; Version 0.1.1: | |
67 | ;; 22/11/02: bugfix in fontlocking, needed to add a '-' to the regex. | |
68 | ;; 19/11/02: completed implementing mixal-describe-operation-code. | |
69 | ;; 13/11/02: implemented compile, mixal-run and mixal-debug. | |
70 | ;; 10/11/02: implemented font-locking and syntax table. | |
71 | ;; 09/11/02: started mixal-mode. | |
72 | ||
73 | ;;; Code: | |
3db571c0 JB |
74 | (defvar compile-command) |
75 | ||
0a2d0bd4 JB |
76 | ;;; Key map |
77 | (defvar mixal-mode-map | |
78 | (let ((map (make-sparse-keymap))) | |
a3507bd3 SM |
79 | (define-key map "\C-c\C-c" 'compile) |
80 | (define-key map "\C-c\C-r" 'mixal-run) | |
81 | (define-key map "\C-c\C-d" 'mixal-debug) | |
82 | (define-key map "\C-h\C-o" 'mixal-describe-operation-code) | |
0a2d0bd4 JB |
83 | map) |
84 | "Keymap for `mixal-mode'.") | |
f8b4fcda | 85 | ;; (makunbound 'mixal-mode-map) |
0a2d0bd4 JB |
86 | |
87 | ;;; Syntax table | |
88 | (defvar mixal-mode-syntax-table | |
89 | (let ((st (make-syntax-table))) | |
0471d426 | 90 | ;; We need to do a bit more to make fontlocking for comments work. |
cf38dd42 | 91 | ;; See use of syntax-propertize-function. |
0471d426 SM |
92 | ;; (modify-syntax-entry ?* "<" st) |
93 | (modify-syntax-entry ?\n ">" st) | |
0a2d0bd4 | 94 | st) |
0471d426 | 95 | "Syntax table for `mixal-mode'.") |
0a2d0bd4 JB |
96 | |
97 | (defvar mixal-font-lock-label-face 'font-lock-variable-name-face | |
98 | "Face name to use for label names. | |
99 | Default value is that of `font-lock-variable-name-face', but you can modify | |
100 | its value.") | |
101 | ||
102 | (defvar mixal-font-lock-operation-code-face 'font-lock-keyword-face | |
103 | "Face name to use for operation code names. | |
104 | Default value is that of `font-lock-keyword-face', but you can modify its | |
105 | value.") | |
106 | ||
107 | (defvar mixal-font-lock-assembly-pseudoinstruction-face 'font-lock-builtin-face | |
108 | "Face name to use for assembly pseudoinstruction names. | |
109 | Default value is that of `font-lock-builtin-face', but you can modify its | |
110 | value.") | |
111 | ||
0a2d0bd4 JB |
112 | (defvar mixal-assembly-pseudoinstructions |
113 | '("ORIG" "EQU" "CON" "ALF" "END") | |
f8b4fcda | 114 | "List of possible assembly pseudoinstructions.") |
0a2d0bd4 | 115 | |
0a2d0bd4 JB |
116 | ;;;; Compilation |
117 | ;; Output from mixasm is compatible with default behavior of emacs, | |
118 | ;; I just added a key (C-cc) and modified the make-command. | |
119 | ||
120 | ;;;; Indentation | |
121 | ;; Tabs works well by default. | |
122 | ||
123 | ;;;; Describe | |
0471d426 SM |
124 | (defvar mixal-operation-codes-alist |
125 | ;; FIXME: the codes FADD, FSUB, FMUL, FDIV, JRAD, and FCMP were in | |
126 | ;; mixal-operation-codes but not here. They should probably be added here. | |
5e339ee2 | 127 | ;; |
8511877a SM |
128 | ;; We used to define this with a backquote and subexps like ,(+ 8 3) for |
129 | ;; better clarity, but the resulting code was too big and caused the | |
130 | ;; byte-compiler to eat up all the stack space. Even using | |
131 | ;; `eval-when-compile' didn't help because the byte-compiler insists on | |
132 | ;; compiling the code before evaluating it. | |
133 | '((LDA loading "load A" 8 field | |
134 | "Put in rA the contents of cell no. M. | |
0a2d0bd4 JB |
135 | Uses a + when there is no sign in subfield. Subfield is left padded with |
136 | zeros to make a word." | |
8511877a | 137 | 2) |
0a2d0bd4 | 138 | |
8511877a SM |
139 | (LDX loading "load X" 15 field |
140 | "Put in rX the contents of cell no. M. | |
0a2d0bd4 JB |
141 | Uses a + when there is no sign in subfield. Subfield is left padded with |
142 | zeros to make a word." | |
8511877a | 143 | 2) |
0a2d0bd4 | 144 | |
8511877a SM |
145 | (LD1 loading "load I1" 9 field |
146 | "Put in rI1 the contents of cell no. M. | |
0a2d0bd4 | 147 | Uses a + when there is no sign in subfield. Subfield is left padded with |
5a5fa834 PE |
148 | zeros to make a word. Index registers only have 2 bytes and a sign; trying |
149 | to set anything more than that will result in undefined behavior." | |
8511877a | 150 | 2) |
0a2d0bd4 | 151 | |
8511877a SM |
152 | (LD2 loading "load I2" 10 field |
153 | "Put in rI2 the contents of cell no. M. | |
0a2d0bd4 | 154 | Uses a + when there is no sign in subfield. Subfield is left padded with |
5a5fa834 PE |
155 | zeros to make a word. Index registers only have 2 bytes and a sign; trying |
156 | to set anything more than that will result in undefined behavior." | |
8511877a | 157 | 2) |
0a2d0bd4 | 158 | |
8511877a SM |
159 | (LD3 loading "load I3" 11 field |
160 | "Put in rI3 the contents of cell no. M. | |
0a2d0bd4 | 161 | Uses a + when there is no sign in subfield. Subfield is left padded with |
5a5fa834 PE |
162 | zeros to make a word. Index registers only have 2 bytes and a sign; trying |
163 | to set anything more than that will result in undefined behavior." | |
8511877a | 164 | 2) |
0a2d0bd4 | 165 | |
8511877a SM |
166 | (LD4 loading "load I4" 12 field |
167 | "Put in rI4 the contents of cell no. M. | |
0a2d0bd4 | 168 | Uses a + when there is no sign in subfield. Subfield is left padded with |
5a5fa834 PE |
169 | zeros to make a word. Index registers only have 2 bytes and a sign; trying |
170 | to set anything more than that will result in undefined behavior." | |
8511877a | 171 | 2) |
0a2d0bd4 | 172 | |
8511877a SM |
173 | (LD5 loading "load I5" 13 field |
174 | "Put in rI5 the contents of cell no. M. | |
0a2d0bd4 | 175 | Uses a + when there is no sign in subfield. Subfield is left padded with |
5a5fa834 PE |
176 | zeros to make a word. Index registers only have 2 bytes and a sign; trying |
177 | to set anything more than that will result in undefined behavior." | |
8511877a | 178 | 2) |
0a2d0bd4 | 179 | |
8511877a SM |
180 | (LD6 loading "load I6" 14 field |
181 | "Put in rI6 the contents of cell no. M. | |
0a2d0bd4 | 182 | Uses a + when there is no sign in subfield. Subfield is left padded with |
5a5fa834 PE |
183 | zeros to make a word. Index registers only have 2 bytes and a sign; trying |
184 | to set anything more than that will result in undefined behavior." | |
8511877a | 185 | 2) |
0a2d0bd4 | 186 | |
8511877a SM |
187 | (LDAN loading "load A negative" 16 field |
188 | "Put in rA the contents of cell no. M, with opposite sign. | |
0a2d0bd4 JB |
189 | Uses a + when there is no sign in subfield, otherwise use the opposite sign. |
190 | Subfield is left padded with zeros to make a word." | |
8511877a | 191 | 2) |
0a2d0bd4 | 192 | |
8511877a SM |
193 | (LDXN loading "load X negative" 23 field |
194 | "Put in rX the contents of cell no. M, with opposite sign. | |
0a2d0bd4 JB |
195 | Uses a + when there is no sign in subfield, otherwise use the opposite sign. |
196 | Subfield is left padded with zeros to make a word." | |
8511877a | 197 | 2) |
0a2d0bd4 | 198 | |
8511877a SM |
199 | (LD1N loading "load I1 negative" 17 field |
200 | "Put in rI1 the contents of cell no. M, with opposite sign. | |
0a2d0bd4 JB |
201 | Uses a + when there is no sign in subfield, otherwise use the opposite sign. |
202 | Subfield is left padded with zeros to make a word. Index registers only | |
5a5fa834 | 203 | have 2 bytes and a sign; trying to set anything more than that will result |
0a2d0bd4 | 204 | in undefined behavior." |
8511877a | 205 | 2) |
0a2d0bd4 | 206 | |
8511877a SM |
207 | (LD2N loading "load I2 negative" 18 field |
208 | "Put in rI2 the contents of cell no. M, with opposite sign. | |
0a2d0bd4 JB |
209 | Uses a + when there is no sign in subfield, otherwise use the opposite sign. |
210 | Subfield is left padded with zeros to make a word. Index registers only | |
5a5fa834 | 211 | have 2 bytes and a sign; trying to set anything more than that will result |
0a2d0bd4 | 212 | in undefined behavior." |
8511877a | 213 | 2) |
0a2d0bd4 | 214 | |
8511877a SM |
215 | (LD3N loading "load I3 negative" 19 field |
216 | "Put in rI3 the contents of cell no. M, with opposite sign. | |
0a2d0bd4 JB |
217 | Uses a + when there is no sign in subfield, otherwise use the opposite sign. |
218 | Subfield is left padded with zeros to make a word. Index registers only | |
5a5fa834 | 219 | have 2 bytes and a sign; trying to set anything more than that will result |
0a2d0bd4 | 220 | in undefined behavior." |
8511877a | 221 | 2) |
0a2d0bd4 | 222 | |
8511877a SM |
223 | (LD4N loading "load I4 negative" 20 field |
224 | "Put in rI4 the contents of cell no. M, with opposite sign. | |
0a2d0bd4 JB |
225 | Uses a + when there is no sign in subfield, otherwise use the opposite sign. |
226 | Subfield is left padded with zeros to make a word. Index registers only | |
5a5fa834 | 227 | have 2 bytes and a sign; trying to set anything more than that will result |
0a2d0bd4 | 228 | in undefined behavior." |
8511877a | 229 | 2) |
0a2d0bd4 | 230 | |
8511877a SM |
231 | (LD5N loading "load I5 negative" 21 field |
232 | "Put in rI5 the contents of cell no. M, with opposite sign. | |
0a2d0bd4 JB |
233 | Uses a + when there is no sign in subfield, otherwise use the opposite sign. |
234 | Subfield is left padded with zeros to make a word. Index registers only | |
5a5fa834 | 235 | have 2 bytes and a sign; trying to set anything more than that will result |
0a2d0bd4 | 236 | in undefined behavior." |
8511877a | 237 | 2) |
0a2d0bd4 | 238 | |
8511877a SM |
239 | (LD6N loading "load I6 negative" 22 field |
240 | "Put in rI6 the contents of cell no. M, with opposite sign. | |
0a2d0bd4 JB |
241 | Uses a + when there is no sign in subfield, otherwise use the opposite sign. |
242 | Subfield is left padded with zeros to make a word. Index registers only | |
5a5fa834 | 243 | have 2 bytes and a sign; trying to set anything more than that will result |
0a2d0bd4 | 244 | in undefined behavior." |
8511877a | 245 | 2) |
0a2d0bd4 | 246 | |
8511877a SM |
247 | (STA storing "store A" 24 field |
248 | "Store in cell Nr. M the contents of rA. | |
0a2d0bd4 JB |
249 | The modification of the operation code represents the subfield of the |
250 | memory cell that is to be overwritten with bytes from a register. These | |
251 | bytes are taken beginning by the rightmost side of the register. The | |
252 | sign of the memory cell is not changed, unless it is part of the subfield." | |
8511877a | 253 | 2) |
0a2d0bd4 | 254 | |
8511877a SM |
255 | (STX storing "store X" 31 field |
256 | "Store in cell Nr. M the contents of rX. | |
0a2d0bd4 JB |
257 | The modification of the operation code represents the subfield of the |
258 | memory cell that is to be overwritten with bytes from a register. These | |
259 | bytes are taken beginning by the rightmost side of the register. The | |
260 | sign of the memory cell is not changed, unless it is part of the subfield." | |
8511877a | 261 | 2) |
0a2d0bd4 | 262 | |
8511877a SM |
263 | (ST1 storing "store I1" 25 field |
264 | "Store in cell Nr. M the contents of rI1. | |
0a2d0bd4 JB |
265 | The modification of the operation code represents the subfield of the |
266 | memory cell that is to be overwritten with bytes from a register. These | |
267 | bytes are taken beginning by the rightmost side of the register. The | |
268 | sign of the memory cell is not changed, unless it is part of the subfield. | |
269 | Because index registers only have 2 bytes and a sign, the rest of the bytes | |
270 | are assumed to be 0." | |
8511877a | 271 | 2) |
0a2d0bd4 | 272 | |
8511877a SM |
273 | (ST2 storing "store I2" 26 field |
274 | "Store in cell Nr. M the contents of rI2. | |
0a2d0bd4 JB |
275 | The modification of the operation code represents the subfield of the |
276 | memory cell that is to be overwritten with bytes from a register. These | |
277 | bytes are taken beginning by the rightmost side of the register. The | |
278 | sign of the memory cell is not changed, unless it is part of the subfield. | |
279 | Because index registers only have 2 bytes and a sign, the rest of the bytes | |
280 | are assumed to be 0." | |
8511877a | 281 | 2) |
0a2d0bd4 | 282 | |
8511877a SM |
283 | (ST3 storing "store I3" 27 field |
284 | "Store in cell Nr. M the contents of rI3. | |
0a2d0bd4 JB |
285 | The modification of the operation code represents the subfield of the |
286 | memory cell that is to be overwritten with bytes from a register. These | |
287 | bytes are taken beginning by the rightmost side of the register. The | |
288 | sign of the memory cell is not changed, unless it is part of the subfield. | |
289 | Because index registers only have 2 bytes and a sign, the rest of the bytes | |
290 | are assumed to be 0." | |
8511877a | 291 | 2) |
0a2d0bd4 | 292 | |
8511877a SM |
293 | (ST4 storing "store I4" 28 field |
294 | "Store in cell Nr. M the contents of rI4. | |
0a2d0bd4 JB |
295 | The modification of the operation code represents the subfield of the |
296 | memory cell that is to be overwritten with bytes from a register. These | |
297 | bytes are taken beginning by the rightmost side of the register. The | |
298 | sign of the memory cell is not changed, unless it is part of the subfield. | |
299 | Because index registers only have 2 bytes and a sign, the rest of the bytes | |
300 | are assumed to be 0." | |
8511877a | 301 | 2) |
0a2d0bd4 | 302 | |
8511877a SM |
303 | (ST5 storing "store I5" 29 field |
304 | "Store in cell Nr. M the contents of rI5. | |
0a2d0bd4 JB |
305 | The modification of the operation code represents the subfield of the |
306 | memory cell that is to be overwritten with bytes from a register. These | |
307 | bytes are taken beginning by the rightmost side of the register. The | |
308 | sign of the memory cell is not changed, unless it is part of the subfield. | |
309 | Because index registers only have 2 bytes and a sign, the rest of the bytes | |
310 | are assumed to be 0." | |
8511877a | 311 | 2) |
0a2d0bd4 | 312 | |
8511877a SM |
313 | (ST6 storing "store I6" 30 field |
314 | "Store in cell Nr. M the contents of rI6. | |
0a2d0bd4 JB |
315 | The modification of the operation code represents the subfield of the |
316 | memory cell that is to be overwritten with bytes from a register. These | |
317 | bytes are taken beginning by the rightmost side of the register. The | |
318 | sign of the memory cell is not changed, unless it is part of the subfield. | |
319 | Because index registers only have 2 bytes and a sign, the rest of the bytes | |
320 | are assumed to be 0." | |
8511877a | 321 | 2) |
0a2d0bd4 | 322 | |
8511877a SM |
323 | (STJ storing "store J" 32 field |
324 | "Store in cell Nr. M the contents of rJ. | |
0a2d0bd4 JB |
325 | The modification of the operation code represents the subfield of the |
326 | memory cell that is to be overwritten with bytes from a register. These | |
327 | bytes are taken beginning by the rightmost side of the register. The sign | |
328 | of rJ is always +, sign of the memory cell is not changed, unless it is | |
329 | part of the subfield. The default field for STJ is (0:2)." | |
8511877a | 330 | 2) |
0a2d0bd4 | 331 | |
8511877a SM |
332 | (STZ storing "store zero" 33 field |
333 | "Store in cell Nr. M '+ 0'. | |
0a2d0bd4 JB |
334 | The modification of the operation code represents the subfield of the |
335 | memory cell that is to be overwritten with zeros." | |
8511877a | 336 | 2) |
0a2d0bd4 | 337 | |
8511877a SM |
338 | (ADD arithmetic "add" 1 field |
339 | "Add to A the contents of cell Nr. M. | |
0a2d0bd4 JB |
340 | Subfield is padded with zero to make a word. |
341 | If the result is to large, the operation result modulo 1,073,741,823 (the | |
342 | maximum value storable in a MIX word) is stored in `rA', and the overflow | |
343 | toggle is set to TRUE." | |
8511877a | 344 | 2) |
0a2d0bd4 | 345 | |
8511877a SM |
346 | (SUB arithmetic "subtract" 2 field |
347 | "Subtract to A the contents of cell Nr. M. | |
0a2d0bd4 JB |
348 | Subfield is padded with zero to make a word. |
349 | If the result is to large, the operation result modulo 1,073,741,823 (the | |
350 | maximum value storable in a MIX word) is stored in `rA', and the overflow | |
351 | toggle is set to TRUE." | |
8511877a | 352 | 2) |
0a2d0bd4 | 353 | |
8511877a SM |
354 | (MUL arithmetic "multiply" 3 field |
355 | "Multiplies the contents of cell Nr. M with A, result is 10 bytes and stored in rA and rX. | |
0a2d0bd4 | 356 | The sign is + if the sign of rA and cell M where the same, otherwise, it is -" |
8511877a | 357 | 10) |
0a2d0bd4 | 358 | |
8511877a SM |
359 | (DIV arithmetic "divide" 4 field |
360 | "Both rA and rX are taken together and divided by cell Nr. M, quotient is placed in rA, remainder in rX. | |
0a2d0bd4 | 361 | The sign is taken from rA, and after the divide the sign of rA is set to + when |
0471d426 SM |
362 | both the sign of rA and M where the same. Divide by zero and overflow of rA |
363 | result in undefined behavior." | |
8511877a | 364 | 12) |
0a2d0bd4 | 365 | |
8511877a SM |
366 | (ENTA address-transfer "enter A" 48 |
367 | "Literal value is stored in rA. | |
0a2d0bd4 | 368 | Indexed, stores value of index in rA." |
8511877a | 369 | 1) |
0a2d0bd4 | 370 | |
8511877a SM |
371 | (ENTX address-transfer "enter X" 55 |
372 | "Literal value is stored in rX. | |
0a2d0bd4 | 373 | Indexed, stores value of index in rX." |
8511877a | 374 | 1) |
0a2d0bd4 | 375 | |
8511877a SM |
376 | (ENT1 address-transfer "Enter rI1" 49 |
377 | "Literal value is stored in rI1. | |
0a2d0bd4 | 378 | Indexed, stores value of index in rI1." |
8511877a | 379 | 1) |
0a2d0bd4 | 380 | |
8511877a SM |
381 | (ENT2 address-transfer "Enter rI2" 50 |
382 | "Literal value is stored in rI2. | |
0a2d0bd4 | 383 | Indexed, stores value of index in rI2." |
8511877a | 384 | 1) |
0a2d0bd4 | 385 | |
8511877a SM |
386 | (ENT3 address-transfer "Enter rI3" 51 |
387 | "Literal value is stored in rI3. | |
0a2d0bd4 | 388 | Indexed, stores value of index in rI3." |
8511877a | 389 | 1) |
0a2d0bd4 | 390 | |
8511877a SM |
391 | (ENT4 address-transfer "Enter rI4" 52 |
392 | "Literal value is stored in rI4. | |
0a2d0bd4 | 393 | Indexed, stores value of index in rI4." |
8511877a | 394 | 1) |
0a2d0bd4 | 395 | |
8511877a SM |
396 | (ENT5 address-transfer "Enter rI5" 53 |
397 | "Literal value is stored in rI5. | |
0a2d0bd4 | 398 | Indexed, stores value of index in rI5." |
8511877a | 399 | 1) |
0a2d0bd4 | 400 | |
8511877a SM |
401 | (ENT6 address-transfer "Enter rI6" 54 |
402 | "Literal value is stored in rI6. | |
0a2d0bd4 | 403 | Indexed, stores value of index in rI6." |
8511877a | 404 | 1) |
0a2d0bd4 | 405 | |
8511877a SM |
406 | (ENNA address-transfer "enter negative A" 48 |
407 | "Literal value is stored in rA with opposite sign. | |
0a2d0bd4 | 408 | Indexed, stores value of index in rA with opposite sign." |
8511877a | 409 | 1) |
0a2d0bd4 | 410 | |
8511877a SM |
411 | (ENNX address-transfer "enter negative X" 55 |
412 | "Literal value is stored in rX with opposite sign. | |
0a2d0bd4 | 413 | Indexed, stores value of index in rX with opposite sign." |
8511877a | 414 | 1) |
0a2d0bd4 | 415 | |
8511877a SM |
416 | (ENN1 address-transfer "Enter negative rI1" 49 |
417 | "Literal value is stored in rI1 with opposite sign. | |
0a2d0bd4 | 418 | Indexed, stores value of index in rI1 with opposite sign." |
8511877a | 419 | 1) |
0a2d0bd4 | 420 | |
8511877a SM |
421 | (ENN2 address-transfer "Enter negative rI2" 50 |
422 | "Literal value is stored in rI2 with opposite sign. | |
0a2d0bd4 | 423 | Indexed, stores value of index in rI2 with opposite sign." |
8511877a | 424 | 1) |
0a2d0bd4 | 425 | |
8511877a SM |
426 | (ENN3 address-transfer "Enter negative rI3" 51 |
427 | "Literal value is stored in rI3 with opposite sign. | |
0a2d0bd4 | 428 | Indexed, stores value of index in rI3 with opposite sign." |
8511877a | 429 | 1) |
0a2d0bd4 | 430 | |
8511877a SM |
431 | (ENN4 address-transfer "Enter negative rI4" 52 |
432 | "Literal value is stored in rI4 with opposite sign. | |
0a2d0bd4 | 433 | Indexed, stores value of index in rI4 with opposite sign." |
8511877a | 434 | 1) |
0a2d0bd4 | 435 | |
8511877a SM |
436 | (ENN5 address-transfer "Enter negative rI5" 53 |
437 | "Literal value is stored in rI5 with opposite sign. | |
0a2d0bd4 | 438 | Indexed, stores value of index in rI5 with opposite sign." |
8511877a | 439 | 1) |
0a2d0bd4 | 440 | |
8511877a SM |
441 | (ENN6 address-transfer "Enter negative rI6" 54 |
442 | "Literal value is stored in rI6 with opposite sign. | |
0a2d0bd4 | 443 | Indexed, stores value of index in rI6 with opposite sign." |
8511877a | 444 | 1) |
0a2d0bd4 | 445 | |
8511877a SM |
446 | (INCA address-transfer "increase A" 48 |
447 | "Increase register A with the literal value of M. | |
0a2d0bd4 | 448 | On overflow the overflow toggle is set." |
8511877a | 449 | 1) |
0a2d0bd4 | 450 | |
8511877a SM |
451 | (INCX address-transfer "increase X" 55 |
452 | "Increase register X with the literal value of M. | |
0a2d0bd4 | 453 | On overflow the overflow toggle is set." |
8511877a | 454 | 1) |
0a2d0bd4 | 455 | |
8511877a SM |
456 | (INC1 address-transfer "increase I1" 49 |
457 | "Increase register I1 with the literal value of M. | |
0a2d0bd4 JB |
458 | The result is undefined when the result does not fit in |
459 | 2 bytes." | |
8511877a | 460 | 1) |
0a2d0bd4 | 461 | |
8511877a SM |
462 | (INC2 address-transfer "increase I2" 50 |
463 | "Increase register I2 with the literal value of M. | |
0a2d0bd4 JB |
464 | The result is undefined when the result does not fit in |
465 | 2 bytes." | |
8511877a | 466 | 1) |
0a2d0bd4 | 467 | |
8511877a SM |
468 | (INC3 address-transfer "increase I3" 51 |
469 | "Increase register I3 with the literal value of M. | |
0a2d0bd4 JB |
470 | The result is undefined when the result does not fit in |
471 | 2 bytes." | |
8511877a | 472 | 1) |
0a2d0bd4 | 473 | |
8511877a SM |
474 | (INC4 address-transfer "increase I4" 52 |
475 | "Increase register I4 with the literal value of M. | |
0a2d0bd4 JB |
476 | The result is undefined when the result does not fit in |
477 | 2 bytes." | |
8511877a | 478 | 1) |
0a2d0bd4 | 479 | |
8511877a SM |
480 | (INC5 address-transfer "increase I5" 53 |
481 | "Increase register I5 with the literal value of M. | |
0a2d0bd4 JB |
482 | The result is undefined when the result does not fit in |
483 | 2 bytes." | |
8511877a | 484 | 1) |
0a2d0bd4 | 485 | |
8511877a SM |
486 | (INC6 address-transfer "increase I6" 54 |
487 | "Increase register I6 with the literal value of M. | |
0a2d0bd4 JB |
488 | The result is undefined when the result does not fit in |
489 | 2 bytes." | |
8511877a | 490 | 1) |
0a2d0bd4 | 491 | |
8511877a SM |
492 | (DECA address-transfer "decrease A" 48 |
493 | "Decrease register A with the literal value of M. | |
0a2d0bd4 | 494 | On overflow the overflow toggle is set." |
8511877a | 495 | 1) |
0a2d0bd4 | 496 | |
8511877a SM |
497 | (DECX address-transfer "decrease X" 55 |
498 | "Decrease register X with the literal value of M. | |
0a2d0bd4 | 499 | On overflow the overflow toggle is set." |
8511877a | 500 | 1) |
0a2d0bd4 | 501 | |
8511877a SM |
502 | (DEC1 address-transfer "decrease I1" 49 |
503 | "Decrease register I1 with the literal value of M. | |
0a2d0bd4 JB |
504 | The result is undefined when the result does not fit in |
505 | 2 bytes." | |
8511877a | 506 | 1) |
0a2d0bd4 | 507 | |
8511877a SM |
508 | (DEC2 address-transfer "decrease I2" 50 |
509 | "Decrease register I2 with the literal value of M. | |
0a2d0bd4 JB |
510 | The result is undefined when the result does not fit in |
511 | 2 bytes." | |
8511877a | 512 | 1) |
0a2d0bd4 | 513 | |
8511877a SM |
514 | (DEC3 address-transfer "decrease I3" 51 |
515 | "Decrease register I3 with the literal value of M. | |
0a2d0bd4 JB |
516 | The result is undefined when the result does not fit in |
517 | 2 bytes." | |
8511877a | 518 | 1) |
0a2d0bd4 | 519 | |
8511877a SM |
520 | (DEC4 address-transfer "decrease I4" 52 |
521 | "Decrease register I4 with the literal value of M. | |
0a2d0bd4 JB |
522 | The result is undefined when the result does not fit in |
523 | 2 bytes." | |
8511877a | 524 | 1) |
0a2d0bd4 | 525 | |
8511877a SM |
526 | (DEC5 address-transfer "decrease I5" 53 |
527 | "Decrease register I5 with the literal value of M. | |
0a2d0bd4 JB |
528 | The result is undefined when the result does not fit in |
529 | 2 bytes." | |
8511877a | 530 | 1) |
0a2d0bd4 | 531 | |
8511877a SM |
532 | (DEC6 address-transfer "decrease I6" 54 |
533 | "Decrease register I6 with the literal value of M. | |
0a2d0bd4 JB |
534 | The result is undefined when the result does not fit in |
535 | 2 bytes." | |
8511877a | 536 | 1) |
0a2d0bd4 | 537 | |
8511877a SM |
538 | (CMPA comparison "compare A" 56 field |
539 | "Compare contents of A with contents of M. | |
0a2d0bd4 JB |
540 | The field specifier works on both fields. The comparison indicator |
541 | is set to LESS, EQUAL or GREATER depending on the outcome." | |
8511877a | 542 | 2) |
0a2d0bd4 | 543 | |
8511877a SM |
544 | (CMPX comparison "compare X" 63 field |
545 | "Compare contents of rX with contents of M. | |
0a2d0bd4 JB |
546 | The field specifier works on both fields. The comparison indicator |
547 | is set to LESS, EQUAL or GREATER depending on the outcome." | |
8511877a | 548 | 2) |
0a2d0bd4 | 549 | |
8511877a SM |
550 | (CMP1 comparison "compare I1" 57 field |
551 | "Compare contents of rI1 with contents of M. | |
0a2d0bd4 JB |
552 | The field specifier works on both fields. The comparison indicator |
553 | is set to LESS, EQUAL or GREATER depending on the outcome. Bit 1,2 and 3 | |
554 | have a value of 0." | |
8511877a | 555 | 2) |
0a2d0bd4 | 556 | |
8511877a SM |
557 | (CMP2 comparison "compare I2" 58 field |
558 | "Compare contents of rI2 with contents of M. | |
0a2d0bd4 JB |
559 | The field specifier works on both fields. The comparison indicator |
560 | is set to LESS, EQUAL or GREATER depending on the outcome. Bit 1,2 and 3 | |
561 | have a value of 0." | |
8511877a | 562 | 2) |
0a2d0bd4 | 563 | |
8511877a SM |
564 | (CMP3 comparison "compare I3" 59 field |
565 | "Compare contents of rI3 with contents of M. | |
0a2d0bd4 JB |
566 | The field specifier works on both fields. The comparison indicator |
567 | is set to LESS, EQUAL or GREATER depending on the outcome. Bit 1,2 and 3 | |
568 | have a value of 0." | |
8511877a | 569 | 2) |
0a2d0bd4 | 570 | |
8511877a SM |
571 | (CMP4 comparison "compare I4" 60 field |
572 | "Compare contents of rI4 with contents of M. | |
0a2d0bd4 JB |
573 | The field specifier works on both fields. The comparison indicator |
574 | is set to LESS, EQUAL or GREATER depending on the outcome. Bit 1,2 and 3 | |
575 | have a value of 0." | |
8511877a | 576 | 2) |
0a2d0bd4 | 577 | |
8511877a SM |
578 | (CMP5 comparison "compare I5" 61 field |
579 | "Compare contents of rI5 with contents of M. | |
0a2d0bd4 JB |
580 | The field specifier works on both fields. The comparison indicator |
581 | is set to LESS, EQUAL or GREATER depending on the outcome. Bit 1,2 and 3 | |
582 | have a value of 0." | |
8511877a | 583 | 2) |
0a2d0bd4 | 584 | |
8511877a SM |
585 | (CMP6 comparison "compare I6" 62 field |
586 | "Compare contents of rI6 with contents of M. | |
0a2d0bd4 JB |
587 | The field specifier works on both fields. The comparison indicator |
588 | is set to LESS, EQUAL or GREATER depending on the outcome. Bit 1,2 and 3 | |
589 | have a value of 0." | |
8511877a | 590 | 2) |
0a2d0bd4 | 591 | |
8511877a SM |
592 | (JMP jump "jump" 39 |
593 | "Unconditional jump. | |
0a2d0bd4 JB |
594 | Register J is set to the value of the next instruction that would have |
595 | been executed when there was no jump." | |
8511877a | 596 | 1) |
0a2d0bd4 | 597 | |
8511877a SM |
598 | (JSJ jump "jump, save J" 39 |
599 | "Unconditional jump, but rJ is not modified." | |
600 | 1) | |
0a2d0bd4 | 601 | |
8511877a SM |
602 | (JOV jump "jump on overflow" 39 |
603 | "Jump if OV is set (and turn it off). | |
0a2d0bd4 JB |
604 | Register J is set to the value of the next instruction that would have |
605 | been executed when there was no jump." | |
8511877a | 606 | 1) |
0a2d0bd4 | 607 | |
8511877a SM |
608 | (JNOV jump "Jump on no overflow" 39 |
609 | "Jump if OV is not set (and turn it off). | |
0a2d0bd4 JB |
610 | Register J is set to the value of the next instruction that would have |
611 | been executed when there was no jump." | |
8511877a | 612 | 1) |
0a2d0bd4 | 613 | |
8511877a SM |
614 | (JL jump "Jump on less" 39 |
615 | "Jump if '[CM] = L'. | |
0a2d0bd4 JB |
616 | Register J is set to the value of the next instruction that would have |
617 | been executed when there was no jump." | |
8511877a | 618 | 1) |
0a2d0bd4 | 619 | |
8511877a SM |
620 | (JE jump "Jump on equal" 39 |
621 | "Jump if '[CM] = E'. | |
0a2d0bd4 JB |
622 | Register J is set to the value of the next instruction that would have |
623 | been executed when there was no jump." | |
8511877a | 624 | 1) |
0a2d0bd4 | 625 | |
8511877a SM |
626 | (JG jump "Jump on greater" 39 |
627 | "Jump if '[CM] = G'. | |
0a2d0bd4 JB |
628 | Register J is set to the value of the next instruction that would have |
629 | been executed when there was no jump." | |
8511877a | 630 | 1) |
0a2d0bd4 | 631 | |
8511877a SM |
632 | (JGE jump "Jump on not less" 39 |
633 | "Jump if '[CM]' does not equal 'L'. | |
0a2d0bd4 JB |
634 | Register J is set to the value of the next instruction that would have |
635 | been executed when there was no jump." | |
8511877a | 636 | 1) |
0a2d0bd4 | 637 | |
8511877a SM |
638 | (JNE jump "Jump on not equal" 39 |
639 | "Jump if '[CM]' does not equal 'E'. | |
0a2d0bd4 JB |
640 | Register J is set to the value of the next instruction that would have |
641 | been executed when there was no jump." | |
8511877a | 642 | 1) |
0a2d0bd4 | 643 | |
8511877a SM |
644 | (JLE jump "Jump on not greater" 39 |
645 | "Jump if '[CM]' does not equal 'G'. | |
0a2d0bd4 JB |
646 | Register J is set to the value of the next instruction that would have |
647 | been executed when there was no jump." | |
8511877a | 648 | 1) |
0a2d0bd4 | 649 | |
8511877a SM |
650 | (JAN jump "jump A negative" 40 |
651 | "Jump if the content of rA is negative. | |
0a2d0bd4 JB |
652 | Register J is set to the value of the next instruction that would have |
653 | been executed when there was no jump." | |
8511877a | 654 | 1) |
0a2d0bd4 | 655 | |
8511877a SM |
656 | (JAZ jump "jump A zero" 40 |
657 | "Jump if the content of rA is zero. | |
0a2d0bd4 JB |
658 | Register J is set to the value of the next instruction that would have |
659 | been executed when there was no jump." | |
8511877a | 660 | 1) |
0a2d0bd4 | 661 | |
8511877a SM |
662 | (JAP jump "jump A positive" 40 |
663 | "Jump if the content of rA is positive. | |
0a2d0bd4 JB |
664 | Register J is set to the value of the next instruction that would have |
665 | been executed when there was no jump." | |
8511877a | 666 | 1) |
0a2d0bd4 | 667 | |
8511877a SM |
668 | (JANN jump "jump A non-negative" 40 |
669 | "Jump if the content of rA is non-negative. | |
0a2d0bd4 JB |
670 | Register J is set to the value of the next instruction that would have |
671 | been executed when there was no jump." | |
8511877a | 672 | 1) |
0a2d0bd4 | 673 | |
8511877a SM |
674 | (JANZ jump "jump A non-zero" 40 |
675 | "Jump if the content of rA is non-zero. | |
0a2d0bd4 JB |
676 | Register J is set to the value of the next instruction that would have |
677 | been executed when there was no jump." | |
8511877a | 678 | 1) |
0a2d0bd4 | 679 | |
8511877a SM |
680 | (JANP jump "jump A non-positive" 40 |
681 | "Jump if the content of rA is non-positive. | |
0a2d0bd4 JB |
682 | Register J is set to the value of the next instruction that would have |
683 | been executed when there was no jump." | |
8511877a | 684 | 1) |
0a2d0bd4 | 685 | |
8511877a SM |
686 | (JXN jump "jump X negative" 47 |
687 | "Jump if the content of rX is negative. | |
0a2d0bd4 JB |
688 | Register J is set to the value of the next instruction that would have |
689 | been executed when there was no jump." | |
8511877a | 690 | 1) |
0a2d0bd4 | 691 | |
8511877a SM |
692 | (JXZ jump "jump X zero" 47 |
693 | "Jump if the content of rX is zero. | |
0a2d0bd4 JB |
694 | Register J is set to the value of the next instruction that would have |
695 | been executed when there was no jump." | |
8511877a | 696 | 1) |
0a2d0bd4 | 697 | |
8511877a SM |
698 | (JXP jump "jump X positive" 47 |
699 | "Jump if the content of rX is positive. | |
0a2d0bd4 JB |
700 | Register J is set to the value of the next instruction that would have |
701 | been executed when there was no jump." | |
8511877a | 702 | 1) |
0a2d0bd4 | 703 | |
8511877a SM |
704 | (JXNN jump "jump X non-negative" 47 |
705 | "Jump if the content of rX is non-negative. | |
0a2d0bd4 JB |
706 | Register J is set to the value of the next instruction that would have |
707 | been executed when there was no jump." | |
8511877a | 708 | 1) |
0a2d0bd4 | 709 | |
8511877a SM |
710 | (JXNZ jump "jump X non-zero" 47 |
711 | "Jump if the content of rX is non-zero. | |
0a2d0bd4 JB |
712 | Register J is set to the value of the next instruction that would have |
713 | been executed when there was no jump." | |
8511877a | 714 | 1) |
0a2d0bd4 | 715 | |
8511877a SM |
716 | (JXNP jump "jump X non-positive" 47 |
717 | "Jump if the content of rX is non-positive. | |
0a2d0bd4 JB |
718 | Register J is set to the value of the next instruction that would have |
719 | been executed when there was no jump." | |
8511877a | 720 | 1) |
0a2d0bd4 | 721 | |
8511877a SM |
722 | (J1N jump "jump I1 negative" 41 |
723 | "Jump if the content of rI1 is negative. | |
0a2d0bd4 JB |
724 | Register J is set to the value of the next instruction that would have |
725 | been executed when there was no jump." | |
8511877a | 726 | 1) |
0a2d0bd4 | 727 | |
8511877a SM |
728 | (J1Z jump "jump I1 zero" 41 |
729 | "Jump if the content of rI1 is zero. | |
0a2d0bd4 JB |
730 | Register J is set to the value of the next instruction that would have |
731 | been executed when there was no jump." | |
8511877a | 732 | 1) |
0a2d0bd4 | 733 | |
8511877a SM |
734 | (J1P jump "jump I1 positive" 41 |
735 | "Jump if the content of rI1 is positive. | |
0a2d0bd4 JB |
736 | Register J is set to the value of the next instruction that would have |
737 | been executed when there was no jump." | |
8511877a | 738 | 1) |
0a2d0bd4 | 739 | |
8511877a SM |
740 | (J1NN jump "jump I1 non-negative" 41 |
741 | "Jump if the content of rI1 is non-negative. | |
0a2d0bd4 JB |
742 | Register J is set to the value of the next instruction that would have |
743 | been executed when there was no jump." | |
8511877a | 744 | 1) |
0a2d0bd4 | 745 | |
8511877a SM |
746 | (J1NZ jump "jump I1 non-zero" 41 |
747 | "Jump if the content of rI1 is non-zero. | |
0a2d0bd4 JB |
748 | Register J is set to the value of the next instruction that would have |
749 | been executed when there was no jump." | |
8511877a | 750 | 1) |
0a2d0bd4 | 751 | |
8511877a SM |
752 | (J1NP jump "jump I1 non-positive" 41 |
753 | "Jump if the content of rI1 is non-positive. | |
0a2d0bd4 JB |
754 | Register J is set to the value of the next instruction that would have |
755 | been executed when there was no jump." | |
8511877a | 756 | 1) |
0a2d0bd4 | 757 | |
8511877a SM |
758 | (J2N jump "jump I2 negative" 41 |
759 | "Jump if the content of rI2 is negative. | |
0a2d0bd4 JB |
760 | Register J is set to the value of the next instruction that would have |
761 | been executed when there was no jump." | |
8511877a | 762 | 1) |
0a2d0bd4 | 763 | |
8511877a SM |
764 | (J2Z jump "jump I2 zero" 41 |
765 | "Jump if the content of rI2 is zero. | |
0a2d0bd4 JB |
766 | Register J is set to the value of the next instruction that would have |
767 | been executed when there was no jump." | |
8511877a | 768 | 1) |
0a2d0bd4 | 769 | |
8511877a SM |
770 | (J2P jump "jump I2 positive" 41 |
771 | "Jump if the content of rI2 is positive. | |
0a2d0bd4 JB |
772 | Register J is set to the value of the next instruction that would have |
773 | been executed when there was no jump." | |
8511877a | 774 | 1) |
0a2d0bd4 | 775 | |
8511877a SM |
776 | (J2NN jump "jump I2 non-negative" 41 |
777 | "Jump if the content of rI2 is non-negative. | |
0a2d0bd4 JB |
778 | Register J is set to the value of the next instruction that would have |
779 | been executed when there was no jump." | |
8511877a | 780 | 1) |
0a2d0bd4 | 781 | |
8511877a SM |
782 | (J2NZ jump "jump I2 non-zero" 41 |
783 | "Jump if the content of rI2 is non-zero. | |
0a2d0bd4 JB |
784 | Register J is set to the value of the next instruction that would have |
785 | been executed when there was no jump." | |
8511877a | 786 | 1) |
0a2d0bd4 | 787 | |
8511877a SM |
788 | (J2NP jump "jump I2 non-positive" 41 |
789 | "Jump if the content of rI2 is non-positive. | |
0a2d0bd4 JB |
790 | Register J is set to the value of the next instruction that would have |
791 | been executed when there was no jump." | |
8511877a | 792 | 1) |
0a2d0bd4 | 793 | |
8511877a SM |
794 | (J3N jump "jump I3 negative" 41 |
795 | "Jump if the content of rI3 is negative. | |
0a2d0bd4 JB |
796 | Register J is set to the value of the next instruction that would have |
797 | been executed when there was no jump." | |
8511877a | 798 | 1) |
0a2d0bd4 | 799 | |
8511877a SM |
800 | (J3Z jump "jump I3 zero" 41 |
801 | "Jump if the content of rI3 is zero. | |
0a2d0bd4 JB |
802 | Register J is set to the value of the next instruction that would have |
803 | been executed when there was no jump." | |
8511877a | 804 | 1) |
0a2d0bd4 | 805 | |
8511877a SM |
806 | (J3P jump "jump I3 positive" 41 |
807 | "Jump if the content of rI3 is positive. | |
0a2d0bd4 JB |
808 | Register J is set to the value of the next instruction that would have |
809 | been executed when there was no jump." | |
8511877a | 810 | 1) |
0a2d0bd4 | 811 | |
8511877a SM |
812 | (J3NN jump "jump I3 non-negative" 41 |
813 | "Jump if the content of rI3 is non-negative. | |
0a2d0bd4 JB |
814 | Register J is set to the value of the next instruction that would have |
815 | been executed when there was no jump." | |
8511877a | 816 | 1) |
0a2d0bd4 | 817 | |
8511877a SM |
818 | (J3NZ jump "jump I3 non-zero" 41 |
819 | "Jump if the content of rI3 is non-zero. | |
0a2d0bd4 JB |
820 | Register J is set to the value of the next instruction that would have |
821 | been executed when there was no jump." | |
8511877a | 822 | 1) |
0a2d0bd4 | 823 | |
8511877a SM |
824 | (J3NP jump "jump I3 non-positive" 41 |
825 | "Jump if the content of rI3 is non-positive. | |
0a2d0bd4 JB |
826 | Register J is set to the value of the next instruction that would have |
827 | been executed when there was no jump." | |
8511877a | 828 | 1) |
0a2d0bd4 | 829 | |
8511877a SM |
830 | (J4N jump "jump I4 negative" 41 |
831 | "Jump if the content of rI4 is negative. | |
0a2d0bd4 JB |
832 | Register J is set to the value of the next instruction that would have |
833 | been executed when there was no jump." | |
8511877a | 834 | 1) |
0a2d0bd4 | 835 | |
8511877a SM |
836 | (J4Z jump "jump I4 zero" 41 |
837 | "Jump if the content of rI4 is zero. | |
0a2d0bd4 JB |
838 | Register J is set to the value of the next instruction that would have |
839 | been executed when there was no jump." | |
8511877a | 840 | 1) |
0a2d0bd4 | 841 | |
8511877a SM |
842 | (J4P jump "jump I4 positive" 41 |
843 | "Jump if the content of rI4 is positive. | |
0a2d0bd4 JB |
844 | Register J is set to the value of the next instruction that would have |
845 | been executed when there was no jump." | |
8511877a | 846 | 1) |
0a2d0bd4 | 847 | |
8511877a SM |
848 | (J4NN jump "jump I4 non-negative" 41 |
849 | "Jump if the content of rI4 is non-negative. | |
0a2d0bd4 JB |
850 | Register J is set to the value of the next instruction that would have |
851 | been executed when there was no jump." | |
8511877a | 852 | 1) |
0a2d0bd4 | 853 | |
8511877a SM |
854 | (J4NZ jump "jump I4 non-zero" 41 |
855 | "Jump if the content of rI4 is non-zero. | |
0a2d0bd4 JB |
856 | Register J is set to the value of the next instruction that would have |
857 | been executed when there was no jump." | |
8511877a | 858 | 1) |
0a2d0bd4 | 859 | |
8511877a SM |
860 | (J4NP jump "jump I4 non-positive" 41 |
861 | "Jump if the content of rI4 is non-positive. | |
0a2d0bd4 JB |
862 | Register J is set to the value of the next instruction that would have |
863 | been executed when there was no jump." | |
8511877a | 864 | 1) |
0a2d0bd4 | 865 | |
8511877a SM |
866 | (J5N jump "jump I5 negative" 41 |
867 | "Jump if the content of rI5 is negative. | |
0a2d0bd4 JB |
868 | Register J is set to the value of the next instruction that would have |
869 | been executed when there was no jump." | |
8511877a | 870 | 1) |
0a2d0bd4 | 871 | |
8511877a SM |
872 | (J5Z jump "jump I5 zero" 41 |
873 | "Jump if the content of rI5 is zero. | |
0a2d0bd4 JB |
874 | Register J is set to the value of the next instruction that would have |
875 | been executed when there was no jump." | |
8511877a | 876 | 1) |
0a2d0bd4 | 877 | |
8511877a SM |
878 | (J5P jump "jump I5 positive" 41 |
879 | "Jump if the content of rI5 is positive. | |
0a2d0bd4 JB |
880 | Register J is set to the value of the next instruction that would have |
881 | been executed when there was no jump." | |
8511877a | 882 | 1) |
0a2d0bd4 | 883 | |
8511877a SM |
884 | (J5NN jump "jump I5 non-negative" 41 |
885 | "Jump if the content of rI5 is non-negative. | |
0a2d0bd4 JB |
886 | Register J is set to the value of the next instruction that would have |
887 | been executed when there was no jump." | |
8511877a | 888 | 1) |
0a2d0bd4 | 889 | |
8511877a SM |
890 | (J5NZ jump "jump I5 non-zero" 41 |
891 | "Jump if the content of rI5 is non-zero. | |
0a2d0bd4 JB |
892 | Register J is set to the value of the next instruction that would have |
893 | been executed when there was no jump." | |
8511877a | 894 | 1) |
0a2d0bd4 | 895 | |
8511877a SM |
896 | (J5NP jump "jump I5 non-positive" 41 |
897 | "Jump if the content of rI5 is non-positive. | |
0a2d0bd4 JB |
898 | Register J is set to the value of the next instruction that would have |
899 | been executed when there was no jump." | |
8511877a | 900 | 1) |
0a2d0bd4 | 901 | |
8511877a SM |
902 | (J6N jump "jump I6 negative" 41 |
903 | "Jump if the content of rI6 is negative. | |
0a2d0bd4 JB |
904 | Register J is set to the value of the next instruction that would have |
905 | been executed when there was no jump." | |
8511877a | 906 | 1) |
0a2d0bd4 | 907 | |
8511877a SM |
908 | (J6Z jump "jump I6 zero" 41 |
909 | "Jump if the content of rI6 is zero. | |
0a2d0bd4 JB |
910 | Register J is set to the value of the next instruction that would have |
911 | been executed when there was no jump." | |
8511877a | 912 | 1) |
0a2d0bd4 | 913 | |
8511877a SM |
914 | (J6P jump "jump I6 positive" 41 |
915 | "Jump if the content of rI6 is positive. | |
0a2d0bd4 JB |
916 | Register J is set to the value of the next instruction that would have |
917 | been executed when there was no jump." | |
8511877a | 918 | 1) |
0a2d0bd4 | 919 | |
8511877a SM |
920 | (J6NN jump "jump I6 non-negative" 41 |
921 | "Jump if the content of rI6 is non-negative. | |
0a2d0bd4 JB |
922 | Register J is set to the value of the next instruction that would have |
923 | been executed when there was no jump." | |
8511877a | 924 | 1) |
0a2d0bd4 | 925 | |
8511877a SM |
926 | (J6NZ jump "jump I6 non-zero" 41 |
927 | "Jump if the content of rI6 is non-zero. | |
0a2d0bd4 JB |
928 | Register J is set to the value of the next instruction that would have |
929 | been executed when there was no jump." | |
8511877a | 930 | 1) |
0a2d0bd4 | 931 | |
8511877a SM |
932 | (J6NP jump "jump I6 non-positive" 41 |
933 | "Jump if the content of rI6 is non-positive. | |
0a2d0bd4 JB |
934 | Register J is set to the value of the next instruction that would have |
935 | been executed when there was no jump." | |
8511877a | 936 | 1) |
0a2d0bd4 | 937 | |
8511877a SM |
938 | (SLA miscellaneous "shift left A" 6 |
939 | "Shift to A, M bytes left. | |
0a2d0bd4 | 940 | Hero's will be added to the right." |
8511877a | 941 | 2) |
0a2d0bd4 | 942 | |
8511877a SM |
943 | (SRA miscellaneous "shift right A" 6 |
944 | "Shift to A, M bytes right. | |
0a2d0bd4 | 945 | Zeros will be added to the left." |
8511877a | 946 | 2) |
0a2d0bd4 | 947 | |
8511877a SM |
948 | (SLAX miscellaneous "shift left AX" 6 |
949 | "Shift AX, M bytes left. | |
0a2d0bd4 | 950 | Zeros will be added to the right." |
8511877a | 951 | 2) |
0a2d0bd4 JB |
952 | |
953 | ||
8511877a SM |
954 | (SRAX miscellaneous "shift right AX" 6 |
955 | "Shift AX, M bytes right. | |
0a2d0bd4 | 956 | Zeros will be added to the left." |
8511877a | 957 | 2) |
0a2d0bd4 | 958 | |
8511877a SM |
959 | (SLC miscellaneous "shift left AX circularly" 6 |
960 | "Shift AX, M bytes left circularly. | |
0a2d0bd4 | 961 | The bytes that fall off to the left will be added to the right." |
8511877a | 962 | 2) |
0a2d0bd4 | 963 | |
8511877a SM |
964 | (SRC miscellaneous "shift right AX circularly" 6 |
965 | "Shift AX, M bytes right circularly. | |
0a2d0bd4 | 966 | The bytes that fall off to the right will be added to the left." |
8511877a | 967 | 2) |
0a2d0bd4 | 968 | |
8511877a SM |
969 | (MOVE miscellaneous "move" 7 number |
970 | "Move MOD words from M to the location stored in rI1." | |
971 | (+ 1 (* 2 number))) | |
0a2d0bd4 | 972 | |
8511877a SM |
973 | (NOP miscellaneous "no operation" 0 ignored |
974 | "No operation, M and F are not used by the machine." | |
975 | 1) | |
0a2d0bd4 | 976 | |
8511877a SM |
977 | (HLT miscellaneous "halt" 5 |
978 | "Halt. | |
0a2d0bd4 | 979 | Stop instruction fetching." |
8511877a | 980 | 1) |
0a2d0bd4 | 981 | |
8511877a SM |
982 | (IN input-output "input" 36 unit |
983 | "Transfer a block of words from the specified unit to memory. | |
0a2d0bd4 | 984 | The transfer starts at address M." |
8511877a | 985 | 1) |
0a2d0bd4 | 986 | |
8511877a SM |
987 | (OUT input-output "output" 37 unit |
988 | "Transfer a block of words from memory. | |
0a2d0bd4 | 989 | The transfer starts at address M to the specified unit." |
8511877a | 990 | 1) |
0a2d0bd4 | 991 | |
8511877a SM |
992 | (IOC input-output "input-output control" 35 unit |
993 | "Perform a control operation. | |
0a2d0bd4 | 994 | The control operation is given by M on the specified unit." |
8511877a | 995 | 1) |
0a2d0bd4 | 996 | |
8511877a SM |
997 | (JRED input-output "jump ready" 38 unit |
998 | "Jump to M if the specified unit is ready." | |
999 | 1) | |
0a2d0bd4 | 1000 | |
8511877a SM |
1001 | (JBUS input-output "jump busy" 34 unit |
1002 | "Jump to M if the specified unit is busy." | |
1003 | 1) | |
0a2d0bd4 | 1004 | |
8511877a SM |
1005 | (NUM conversion "convert to numeric" 5 |
1006 | "Convert rAX to its numerical value and store it in rA. | |
0a2d0bd4 JB |
1007 | the register rAX is assumed to contain a character representation of |
1008 | a number." | |
8511877a | 1009 | 10) |
0a2d0bd4 | 1010 | |
8511877a SM |
1011 | (CHAR conversion "convert to characters" 5 |
1012 | "Convert the number stored in rA to a character representation. | |
0a2d0bd4 | 1013 | The converted character representation is stored in rAX." |
8511877a | 1014 | 10)) |
0471d426 SM |
1015 | |
1016 | "Alist that contains all the possible operation codes for mix. | |
1017 | Each elt has the form | |
1018 | (OP-CODE GROUP FULL-NAME C-BYTE F-BYTE DESCRIPTION EXECUTION-TIME) | |
6a3ccec7 | 1019 | Where OP-CODE is the text of the opcode as a symbol, |
0471d426 SM |
1020 | FULL-NAME is the human readable name as a string, |
1021 | C-BYTE is the operation code telling what operation is to be performed, | |
1022 | F-BYTE holds a modification of the operation code which can be a symbol | |
1023 | or a number, | |
1024 | DESCRIPTION contains an string with a description about the operation code and | |
1025 | EXECUTION-TIME holds info about the time it takes, number or string.") | |
1026 | ;; (makunbound 'mixal-operation-codes-alist) | |
1027 | ||
1028 | ||
1029 | ;;; Font-locking: | |
cf38dd42 SM |
1030 | (defconst mixal-syntax-propertize-function |
1031 | (syntax-propertize-rules | |
1032 | ;; Normal comments start with a * in column 0 and end at end of line. | |
1033 | ("^\\*" (0 "<")) | |
1034 | ;; Every line can end with a comment which is placed after the operand. | |
1035 | ;; I assume here that mnemonics without operands can not have a comment. | |
1036 | ("^[[:alnum:]]*[ \t]+[[:alnum:]]+[ \t]+[^ \n\t]+[ \t]*\\([ \t]\\)[^\n \t]" | |
1037 | (1 "<")))) | |
0471d426 SM |
1038 | |
1039 | (defvar mixal-font-lock-keywords | |
1040 | `(("^\\([A-Z0-9a-z]+\\)" | |
1041 | (1 mixal-font-lock-label-face)) | |
1042 | (,(regexp-opt (mapcar (lambda (x) (symbol-name (car x))) | |
1043 | mixal-operation-codes-alist) 'words) | |
1044 | . mixal-font-lock-operation-code-face) | |
1045 | (,(regexp-opt mixal-assembly-pseudoinstructions 'words) | |
1046 | . mixal-font-lock-assembly-pseudoinstruction-face) | |
1047 | ("^[A-Z0-9a-z]*[ \t]+[A-ZO-9a-z]+[ \t]+\\(=.*=\\)" | |
1048 | (1 font-lock-constant-face))) | |
1049 | "Keyword highlighting specification for `mixal-mode'.") | |
1050 | ;; (makunbound 'mixal-font-lock-keywords) | |
0a2d0bd4 JB |
1051 | |
1052 | (defvar mixal-describe-operation-code-history nil | |
1053 | "History list for describe operation code.") | |
1054 | ||
0471d426 | 1055 | (defun mixal-describe-operation-code (op-code) |
0a2d0bd4 | 1056 | "Display the full documentation of OP-CODE." |
0471d426 SM |
1057 | (interactive |
1058 | (list | |
0a2d0bd4 JB |
1059 | (let* ((completion-ignore-case t) |
1060 | ;; we already have a list, but it is not in the right format | |
da6062e6 | 1061 | ;; transform it to a valid table so completion can use it |
4f91a816 | 1062 | (table (mapcar (lambda (elm) (cons (symbol-name (car elm)) nil)) |
0a2d0bd4 JB |
1063 | mixal-operation-codes-alist)) |
1064 | ;; prompt is different depending on we are close to a valid op-code | |
0471d426 SM |
1065 | (have-default (assq (intern-soft (current-word)) |
1066 | mixal-operation-codes-alist)) | |
0a2d0bd4 JB |
1067 | (prompt (concat "Describe operation code " |
1068 | (if have-default | |
1069 | (concat "(default " (current-word) "): ") | |
1070 | ": ")))) | |
0471d426 SM |
1071 | ;; As the operation code to the user. |
1072 | (completing-read prompt table nil t nil | |
1073 | 'mixal-describe-operation-code-history | |
1074 | (current-word))))) | |
0a2d0bd4 JB |
1075 | ;; get the info on the op-code and output it to the help buffer |
1076 | (let ((op-code-help (assq (intern-soft op-code) mixal-operation-codes-alist))) | |
1077 | (when op-code-help | |
1078 | (with-output-to-temp-buffer (buffer-name (get-buffer-create "*Help*")) | |
1079 | (princ op-code) (princ " is an mix operation code\n\n") | |
1080 | (princ (nth 5 op-code-help)) (terpri) (terpri) | |
1081 | (princ " group: ") (princ (nth 1 op-code-help)) (terpri) | |
1082 | (princ " nice name: ") (princ (nth 2 op-code-help)) (terpri) | |
1083 | (princ " OPCODE / C: ") (princ (nth 3 op-code-help)) (terpri) | |
1084 | (princ " MOD / F: ") (princ (nth 4 op-code-help)) (terpri) | |
1085 | (princ " time: ") (princ (nth 6 op-code-help)) (terpri))))) | |
1086 | ||
1087 | ;;;; Running | |
1088 | (defun mixal-run () | |
f8b4fcda | 1089 | "Run mixal file in current buffer, assumes that file has been compiled." |
0a2d0bd4 | 1090 | (interactive) |
91dd4dc4 DN |
1091 | (if (fboundp 'mixvm) |
1092 | (mixvm (concat "mixvm -r -t -d " | |
1093 | (file-name-sans-extension (buffer-file-name)))) | |
1094 | (error "mixvm.el needs to be loaded to run `mixvm'"))) | |
0a2d0bd4 JB |
1095 | |
1096 | (defun mixal-debug () | |
f8b4fcda SM |
1097 | "Start mixvm for debugging. |
1098 | Assumes that file has been compiled with debugging support." | |
0a2d0bd4 | 1099 | (interactive) |
91dd4dc4 DN |
1100 | (if (fboundp 'mixvm) |
1101 | (mixvm (concat "mixvm " | |
1102 | (file-name-sans-extension (buffer-file-name)))) | |
1103 | (error "mixvm.el needs to be loaded to run `mixvm'"))) | |
0a2d0bd4 JB |
1104 | |
1105 | ;;;###autoload | |
c5cde042 | 1106 | (define-derived-mode mixal-mode prog-mode "mixal" |
175069ef | 1107 | "Major mode for the mixal asm language." |
0a2d0bd4 | 1108 | (set (make-local-variable 'comment-start) "*") |
0471d426 SM |
1109 | (set (make-local-variable 'comment-start-skip) "^\\*[ \t]*") |
1110 | (set (make-local-variable 'font-lock-defaults) | |
cf38dd42 SM |
1111 | `(mixal-font-lock-keywords)) |
1112 | (set (make-local-variable 'syntax-propertize-function) | |
1113 | mixal-syntax-propertize-function) | |
f8b4fcda SM |
1114 | ;; might add an indent function in the future |
1115 | ;; (set (make-local-variable 'indent-line-function) 'mixal-indent-line) | |
55e47f95 GM |
1116 | (set (make-local-variable 'compile-command) |
1117 | (concat "mixasm " | |
1118 | (if buffer-file-name | |
1119 | (shell-quote-argument buffer-file-name))))) | |
0a2d0bd4 | 1120 | |
0a2d0bd4 | 1121 | (provide 'mixal-mode) |
ab5796a9 | 1122 | |
0a2d0bd4 | 1123 | ;;; mixal-mode.el ends here |