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1 | ;;; mixal-mode.el --- Major mode for the mix asm language. |
2 | ||
034babe1 | 3 | ;; Copyright (C) 2003, 2004, 2005 Free Software Foundation |
0a2d0bd4 JB |
4 | |
5 | ;; This program is free software; you can redistribute it and/or | |
6 | ;; modify it under the terms of the GNU General Public License as | |
7 | ;; published by the Free Software Foundation; either version 2 of | |
8 | ;; the License, or (at your option) any later version. | |
9 | ||
10 | ;; This program is distributed in the hope that it will be | |
11 | ;; useful, but WITHOUT ANY WARRANTY; without even the implied | |
12 | ;; warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR | |
13 | ;; PURPOSE. See the GNU General Public License for more details. | |
14 | ||
15 | ;; You should have received a copy of the GNU General Public | |
16 | ;; License along with this program; if not, write to the Free | |
3a35cf56 LK |
17 | ;; Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, |
18 | ;; MA 02110-1301 USA | |
0a2d0bd4 | 19 | |
f8b4fcda SM |
20 | ;; Author: Pieter E.J. Pareit <pieter.pareit@gmail.com> |
21 | ;; Maintainer: Pieter E.J. Pareit <pieter.pareit@gmail.com> | |
0a2d0bd4 JB |
22 | ;; Created: 09 Nov 2002 |
23 | ;; Version: 0.1 | |
24 | ;; Keywords: Knuth mix mixal asm mixvm "The Art Of Computer Programming" | |
25 | ||
26 | ;;; Commentary: | |
27 | ;; Major mode for the mix asm language. | |
28 | ;; The mix asm language is described in "The Art Of Computer Programming". | |
29 | ;; | |
f8b4fcda SM |
30 | ;; For optimal use, also use GNU MDK. Compiling needs mixasm, running |
31 | ;; and debugging needs mixvm and mixvm.el from GNU MDK. You can get | |
0a2d0bd4 JB |
32 | ;; GNU MDK from `https://savannah.gnu.org/projects/mdk/' and |
33 | ;; `ftp://ftp.gnu.org/pub/gnu/mdk'. | |
34 | ;; | |
35 | ;; To use this mode, place the following in your .emacs file: | |
36 | ;; `(load-file "/PATH-TO-FILE/mixal-mode.el")'. | |
37 | ;; When you load a file with the extension .mixal the mode will be started | |
f8b4fcda SM |
38 | ;; automatic. If you want to start the mode manual, use `M-x mixal-mode'. |
39 | ;; Font locking will work, the behavior of tabs is the same as Emacs's | |
40 | ;; default behavior. You can compile a source file with `C-c c' you can | |
0a2d0bd4 JB |
41 | ;; run a compiled file with `C-c r' or run it in debug mode with `C-c d'. |
42 | ;; You can get more information about a particular operation code by using | |
43 | ;; mixal-describe-operation-code or `C-h o'. | |
44 | ;; | |
45 | ;; Have fun. | |
46 | ||
47 | ;;; History: | |
f8b4fcda | 48 | ;; Version 0.3: |
0471d426 SM |
49 | ;; 12/10/05: Stefan Monnier <monnier@iro.umontreal.ca> |
50 | ;; Use font-lock-syntactic-keywords to detect/mark comments. | |
51 | ;; Use [^ \t\n]+ to match the operand part of a line. | |
52 | ;; Drop mixal-operation-codes. | |
53 | ;; Build the mixal-operation-codes-alist immediately. | |
54 | ;; Use `interactive' in mixal-describe-operation-code. | |
55 | ;; Remove useless ".*$" at the end of some regexps. | |
56 | ;; Fix the definition of comment-start-skip. | |
f8b4fcda SM |
57 | ;; 08/10/05: sync mdk and emacs cvs |
58 | ;; from emacs: compile-command and require-final-newline | |
59 | ;; from mdk: see version 0.2 | |
60 | ;; correct my email address | |
61 | ;; Version 0.2: | |
62 | ;; 06/04/05: mixasm no longer needs -g option | |
63 | ;; fontlocking of comments works in all? cases now | |
64 | ;; added some more mixal-operation-codes | |
0a2d0bd4 JB |
65 | ;; Version 0.1: |
66 | ;; Version 0.1.1: | |
67 | ;; 22/11/02: bugfix in fontlocking, needed to add a '-' to the regex. | |
68 | ;; 19/11/02: completed implementing mixal-describe-operation-code. | |
69 | ;; 13/11/02: implemented compile, mixal-run and mixal-debug. | |
70 | ;; 10/11/02: implemented font-locking and syntax table. | |
71 | ;; 09/11/02: started mixal-mode. | |
72 | ||
73 | ;;; Code: | |
3db571c0 JB |
74 | (defvar compile-command) |
75 | ||
0a2d0bd4 JB |
76 | ;;; Key map |
77 | (defvar mixal-mode-map | |
78 | (let ((map (make-sparse-keymap))) | |
79 | (define-key map "\C-cc" 'compile) | |
80 | (define-key map "\C-cr" 'mixal-run) | |
81 | (define-key map "\C-cd" 'mixal-debug) | |
82 | (define-key map "\C-ho" 'mixal-describe-operation-code) | |
83 | map) | |
84 | "Keymap for `mixal-mode'.") | |
f8b4fcda | 85 | ;; (makunbound 'mixal-mode-map) |
0a2d0bd4 JB |
86 | |
87 | ;;; Syntax table | |
88 | (defvar mixal-mode-syntax-table | |
89 | (let ((st (make-syntax-table))) | |
0471d426 SM |
90 | ;; We need to do a bit more to make fontlocking for comments work. |
91 | ;; See mixal-font-lock-syntactic-keywords. | |
92 | ;; (modify-syntax-entry ?* "<" st) | |
93 | (modify-syntax-entry ?\n ">" st) | |
0a2d0bd4 | 94 | st) |
0471d426 | 95 | "Syntax table for `mixal-mode'.") |
0a2d0bd4 JB |
96 | |
97 | (defvar mixal-font-lock-label-face 'font-lock-variable-name-face | |
98 | "Face name to use for label names. | |
99 | Default value is that of `font-lock-variable-name-face', but you can modify | |
100 | its value.") | |
101 | ||
102 | (defvar mixal-font-lock-operation-code-face 'font-lock-keyword-face | |
103 | "Face name to use for operation code names. | |
104 | Default value is that of `font-lock-keyword-face', but you can modify its | |
105 | value.") | |
106 | ||
107 | (defvar mixal-font-lock-assembly-pseudoinstruction-face 'font-lock-builtin-face | |
108 | "Face name to use for assembly pseudoinstruction names. | |
109 | Default value is that of `font-lock-builtin-face', but you can modify its | |
110 | value.") | |
111 | ||
0a2d0bd4 JB |
112 | (defvar mixal-assembly-pseudoinstructions |
113 | '("ORIG" "EQU" "CON" "ALF" "END") | |
f8b4fcda | 114 | "List of possible assembly pseudoinstructions.") |
0a2d0bd4 | 115 | |
0a2d0bd4 JB |
116 | ;;;; Compilation |
117 | ;; Output from mixasm is compatible with default behavior of emacs, | |
118 | ;; I just added a key (C-cc) and modified the make-command. | |
119 | ||
120 | ;;;; Indentation | |
121 | ;; Tabs works well by default. | |
122 | ||
123 | ;;;; Describe | |
0471d426 SM |
124 | (defvar mixal-operation-codes-alist |
125 | ;; FIXME: the codes FADD, FSUB, FMUL, FDIV, JRAD, and FCMP were in | |
126 | ;; mixal-operation-codes but not here. They should probably be added here. | |
b4a63d75 SM |
127 | (eval-when-compile |
128 | `((LDA loading "load A" 8 field | |
129 | "Put in rA the contents of cell no. M. | |
0a2d0bd4 JB |
130 | Uses a + when there is no sign in subfield. Subfield is left padded with |
131 | zeros to make a word." | |
b4a63d75 | 132 | 2) |
0a2d0bd4 | 133 | |
b4a63d75 SM |
134 | (LDX loading "load X" 15 field |
135 | "Put in rX the contents of cell no. M. | |
0a2d0bd4 JB |
136 | Uses a + when there is no sign in subfield. Subfield is left padded with |
137 | zeros to make a word." | |
b4a63d75 | 138 | 2) |
0a2d0bd4 | 139 | |
b4a63d75 SM |
140 | (LD1 loading "load I1" ,(+ 8 1) field |
141 | "Put in rI1 the contents of cell no. M. | |
0a2d0bd4 JB |
142 | Uses a + when there is no sign in subfield. Subfield is left padded with |
143 | zeros to make a word. Index registers only have 2 bytes and a sign, Trying | |
144 | to set anything more that that will result in undefined behavior." | |
b4a63d75 | 145 | 2) |
0a2d0bd4 | 146 | |
b4a63d75 SM |
147 | (LD2 loading "load I2" ,(+ 8 2) field |
148 | "Put in rI2 the contents of cell no. M. | |
0a2d0bd4 JB |
149 | Uses a + when there is no sign in subfield. Subfield is left padded with |
150 | zeros to make a word. Index registers only have 2 bytes and a sign, Trying | |
151 | to set anything more that that will result in undefined behavior." | |
b4a63d75 | 152 | 2) |
0a2d0bd4 | 153 | |
b4a63d75 SM |
154 | (LD3 loading "load I3" ,(+ 8 3) field |
155 | "Put in rI3 the contents of cell no. M. | |
0a2d0bd4 JB |
156 | Uses a + when there is no sign in subfield. Subfield is left padded with |
157 | zeros to make a word. Index registers only have 2 bytes and a sign, Trying | |
158 | to set anything more that that will result in undefined behavior." | |
b4a63d75 | 159 | 2) |
0a2d0bd4 | 160 | |
b4a63d75 SM |
161 | (LD4 loading "load I4" ,(+ 8 4) field |
162 | "Put in rI4 the contents of cell no. M. | |
0a2d0bd4 JB |
163 | Uses a + when there is no sign in subfield. Subfield is left padded with |
164 | zeros to make a word. Index registers only have 2 bytes and a sign, Trying | |
165 | to set anything more that that will result in undefined behavior." | |
b4a63d75 | 166 | 2) |
0a2d0bd4 | 167 | |
b4a63d75 SM |
168 | (LD5 loading "load I5" ,(+ 8 5) field |
169 | "Put in rI5 the contents of cell no. M. | |
0a2d0bd4 JB |
170 | Uses a + when there is no sign in subfield. Subfield is left padded with |
171 | zeros to make a word. Index registers only have 2 bytes and a sign, Trying | |
172 | to set anything more that that will result in undefined behavior." | |
b4a63d75 | 173 | 2) |
0a2d0bd4 | 174 | |
b4a63d75 SM |
175 | (LD6 loading "load I6" ,(+ 8 6) field |
176 | "Put in rI6 the contents of cell no. M. | |
0a2d0bd4 JB |
177 | Uses a + when there is no sign in subfield. Subfield is left padded with |
178 | zeros to make a word. Index registers only have 2 bytes and a sign, Trying | |
179 | to set anything more that that will result in undefined behavior." | |
b4a63d75 | 180 | 2) |
0a2d0bd4 | 181 | |
b4a63d75 SM |
182 | (LDAN loading "load A negative" 16 field |
183 | "Put in rA the contents of cell no. M, with opposite sign. | |
0a2d0bd4 JB |
184 | Uses a + when there is no sign in subfield, otherwise use the opposite sign. |
185 | Subfield is left padded with zeros to make a word." | |
b4a63d75 | 186 | 2) |
0a2d0bd4 | 187 | |
b4a63d75 SM |
188 | (LDXN loading "load X negative" 23 field |
189 | "Put in rX the contents of cell no. M, with opposite sign. | |
0a2d0bd4 JB |
190 | Uses a + when there is no sign in subfield, otherwise use the opposite sign. |
191 | Subfield is left padded with zeros to make a word." | |
b4a63d75 | 192 | 2) |
0a2d0bd4 | 193 | |
b4a63d75 SM |
194 | (LD1N loading "load I1 negative" ,(+ 16 1) field |
195 | "Put in rI1 the contents of cell no. M, with opposite sign. | |
0a2d0bd4 JB |
196 | Uses a + when there is no sign in subfield, otherwise use the opposite sign. |
197 | Subfield is left padded with zeros to make a word. Index registers only | |
198 | have 2 bytes and a sign, Trying to set anything more that that will result | |
199 | in undefined behavior." | |
b4a63d75 | 200 | 2) |
0a2d0bd4 | 201 | |
b4a63d75 SM |
202 | (LD2N loading "load I2 negative" ,(+ 16 2) field |
203 | "Put in rI2 the contents of cell no. M, with opposite sign. | |
0a2d0bd4 JB |
204 | Uses a + when there is no sign in subfield, otherwise use the opposite sign. |
205 | Subfield is left padded with zeros to make a word. Index registers only | |
206 | have 2 bytes and a sign, Trying to set anything more that that will result | |
207 | in undefined behavior." | |
b4a63d75 | 208 | 2) |
0a2d0bd4 | 209 | |
b4a63d75 SM |
210 | (LD3N loading "load I3 negative" ,(+ 16 3) field |
211 | "Put in rI3 the contents of cell no. M, with opposite sign. | |
0a2d0bd4 JB |
212 | Uses a + when there is no sign in subfield, otherwise use the opposite sign. |
213 | Subfield is left padded with zeros to make a word. Index registers only | |
214 | have 2 bytes and a sign, Trying to set anything more that that will result | |
215 | in undefined behavior." | |
b4a63d75 | 216 | 2) |
0a2d0bd4 | 217 | |
b4a63d75 SM |
218 | (LD4N loading "load I4 negative" ,(+ 16 4) field |
219 | "Put in rI4 the contents of cell no. M, with opposite sign. | |
0a2d0bd4 JB |
220 | Uses a + when there is no sign in subfield, otherwise use the opposite sign. |
221 | Subfield is left padded with zeros to make a word. Index registers only | |
222 | have 2 bytes and a sign, Trying to set anything more that that will result | |
223 | in undefined behavior." | |
b4a63d75 | 224 | 2) |
0a2d0bd4 | 225 | |
b4a63d75 SM |
226 | (LD5N loading "load I5 negative" ,(+ 16 5) field |
227 | "Put in rI5 the contents of cell no. M, with opposite sign. | |
0a2d0bd4 JB |
228 | Uses a + when there is no sign in subfield, otherwise use the opposite sign. |
229 | Subfield is left padded with zeros to make a word. Index registers only | |
230 | have 2 bytes and a sign, Trying to set anything more that that will result | |
231 | in undefined behavior." | |
b4a63d75 | 232 | 2) |
0a2d0bd4 | 233 | |
b4a63d75 SM |
234 | (LD6N loading "load I6 negative" ,(+ 16 6) field |
235 | "Put in rI6 the contents of cell no. M, with opposite sign. | |
0a2d0bd4 JB |
236 | Uses a + when there is no sign in subfield, otherwise use the opposite sign. |
237 | Subfield is left padded with zeros to make a word. Index registers only | |
238 | have 2 bytes and a sign, Trying to set anything more that that will result | |
239 | in undefined behavior." | |
b4a63d75 | 240 | 2) |
0a2d0bd4 | 241 | |
b4a63d75 SM |
242 | (STA storing "store A" 24 field |
243 | "Store in cell Nr. M the contents of rA. | |
0a2d0bd4 JB |
244 | The modification of the operation code represents the subfield of the |
245 | memory cell that is to be overwritten with bytes from a register. These | |
246 | bytes are taken beginning by the rightmost side of the register. The | |
247 | sign of the memory cell is not changed, unless it is part of the subfield." | |
b4a63d75 | 248 | 2) |
0a2d0bd4 | 249 | |
b4a63d75 SM |
250 | (STX storing "store X" 31 field |
251 | "Store in cell Nr. M the contents of rX. | |
0a2d0bd4 JB |
252 | The modification of the operation code represents the subfield of the |
253 | memory cell that is to be overwritten with bytes from a register. These | |
254 | bytes are taken beginning by the rightmost side of the register. The | |
255 | sign of the memory cell is not changed, unless it is part of the subfield." | |
b4a63d75 | 256 | 2) |
0a2d0bd4 | 257 | |
b4a63d75 SM |
258 | (ST1 storing "store I1" ,(+ 24 1) field |
259 | "Store in cell Nr. M the contents of rI1. | |
0a2d0bd4 JB |
260 | The modification of the operation code represents the subfield of the |
261 | memory cell that is to be overwritten with bytes from a register. These | |
262 | bytes are taken beginning by the rightmost side of the register. The | |
263 | sign of the memory cell is not changed, unless it is part of the subfield. | |
264 | Because index registers only have 2 bytes and a sign, the rest of the bytes | |
265 | are assumed to be 0." | |
b4a63d75 | 266 | 2) |
0a2d0bd4 | 267 | |
b4a63d75 SM |
268 | (ST2 storing "store I2" ,(+ 24 2) field |
269 | "Store in cell Nr. M the contents of rI2. | |
0a2d0bd4 JB |
270 | The modification of the operation code represents the subfield of the |
271 | memory cell that is to be overwritten with bytes from a register. These | |
272 | bytes are taken beginning by the rightmost side of the register. The | |
273 | sign of the memory cell is not changed, unless it is part of the subfield. | |
274 | Because index registers only have 2 bytes and a sign, the rest of the bytes | |
275 | are assumed to be 0." | |
b4a63d75 | 276 | 2) |
0a2d0bd4 | 277 | |
b4a63d75 SM |
278 | (ST3 storing "store I3" ,(+ 24 3) field |
279 | "Store in cell Nr. M the contents of rI3. | |
0a2d0bd4 JB |
280 | The modification of the operation code represents the subfield of the |
281 | memory cell that is to be overwritten with bytes from a register. These | |
282 | bytes are taken beginning by the rightmost side of the register. The | |
283 | sign of the memory cell is not changed, unless it is part of the subfield. | |
284 | Because index registers only have 2 bytes and a sign, the rest of the bytes | |
285 | are assumed to be 0." | |
b4a63d75 | 286 | 2) |
0a2d0bd4 | 287 | |
b4a63d75 SM |
288 | (ST4 storing "store I4" ,(+ 24 4) field |
289 | "Store in cell Nr. M the contents of rI4. | |
0a2d0bd4 JB |
290 | The modification of the operation code represents the subfield of the |
291 | memory cell that is to be overwritten with bytes from a register. These | |
292 | bytes are taken beginning by the rightmost side of the register. The | |
293 | sign of the memory cell is not changed, unless it is part of the subfield. | |
294 | Because index registers only have 2 bytes and a sign, the rest of the bytes | |
295 | are assumed to be 0." | |
b4a63d75 | 296 | 2) |
0a2d0bd4 | 297 | |
b4a63d75 SM |
298 | (ST5 storing "store I5" ,(+ 24 5) field |
299 | "Store in cell Nr. M the contents of rI5. | |
0a2d0bd4 JB |
300 | The modification of the operation code represents the subfield of the |
301 | memory cell that is to be overwritten with bytes from a register. These | |
302 | bytes are taken beginning by the rightmost side of the register. The | |
303 | sign of the memory cell is not changed, unless it is part of the subfield. | |
304 | Because index registers only have 2 bytes and a sign, the rest of the bytes | |
305 | are assumed to be 0." | |
b4a63d75 | 306 | 2) |
0a2d0bd4 | 307 | |
b4a63d75 SM |
308 | (ST6 storing "store I6" ,(+ 24 6) field |
309 | "Store in cell Nr. M the contents of rI6. | |
0a2d0bd4 JB |
310 | The modification of the operation code represents the subfield of the |
311 | memory cell that is to be overwritten with bytes from a register. These | |
312 | bytes are taken beginning by the rightmost side of the register. The | |
313 | sign of the memory cell is not changed, unless it is part of the subfield. | |
314 | Because index registers only have 2 bytes and a sign, the rest of the bytes | |
315 | are assumed to be 0." | |
b4a63d75 | 316 | 2) |
0a2d0bd4 | 317 | |
b4a63d75 SM |
318 | (STJ storing "store J" 32 field |
319 | "Store in cell Nr. M the contents of rJ. | |
0a2d0bd4 JB |
320 | The modification of the operation code represents the subfield of the |
321 | memory cell that is to be overwritten with bytes from a register. These | |
322 | bytes are taken beginning by the rightmost side of the register. The sign | |
323 | of rJ is always +, sign of the memory cell is not changed, unless it is | |
324 | part of the subfield. The default field for STJ is (0:2)." | |
b4a63d75 | 325 | 2) |
0a2d0bd4 | 326 | |
b4a63d75 SM |
327 | (STZ storing "store zero" 33 field |
328 | "Store in cell Nr. M '+ 0'. | |
0a2d0bd4 JB |
329 | The modification of the operation code represents the subfield of the |
330 | memory cell that is to be overwritten with zeros." | |
b4a63d75 | 331 | 2) |
0a2d0bd4 | 332 | |
b4a63d75 SM |
333 | (ADD arithmetic "add" 1 field |
334 | "Add to A the contents of cell Nr. M. | |
0a2d0bd4 JB |
335 | Subfield is padded with zero to make a word. |
336 | If the result is to large, the operation result modulo 1,073,741,823 (the | |
337 | maximum value storable in a MIX word) is stored in `rA', and the overflow | |
338 | toggle is set to TRUE." | |
b4a63d75 | 339 | 2) |
0a2d0bd4 | 340 | |
b4a63d75 SM |
341 | (SUB arithmetic "subtract" 2 field |
342 | "Subtract to A the contents of cell Nr. M. | |
0a2d0bd4 JB |
343 | Subfield is padded with zero to make a word. |
344 | If the result is to large, the operation result modulo 1,073,741,823 (the | |
345 | maximum value storable in a MIX word) is stored in `rA', and the overflow | |
346 | toggle is set to TRUE." | |
b4a63d75 | 347 | 2) |
0a2d0bd4 | 348 | |
b4a63d75 SM |
349 | (MUL arithmetic "multiply" 3 field |
350 | "Multiplies the contents of cell Nr. M with A, result is 10 bytes and stored in rA and rX. | |
0a2d0bd4 | 351 | The sign is + if the sign of rA and cell M where the same, otherwise, it is -" |
b4a63d75 | 352 | 10) |
0a2d0bd4 | 353 | |
b4a63d75 SM |
354 | (DIV arithmetic "divide" 4 field |
355 | "Both rA and rX are taken together and divided by cell Nr. M, quotient is placed in rA, remainder in rX. | |
0a2d0bd4 | 356 | The sign is taken from rA, and after the divide the sign of rA is set to + when |
0471d426 SM |
357 | both the sign of rA and M where the same. Divide by zero and overflow of rA |
358 | result in undefined behavior." | |
b4a63d75 | 359 | 12) |
0a2d0bd4 | 360 | |
b4a63d75 SM |
361 | (ENTA address-transfer "enter A" 48 |
362 | "Literal value is stored in rA. | |
0a2d0bd4 | 363 | Indexed, stores value of index in rA." |
b4a63d75 | 364 | 1) |
0a2d0bd4 | 365 | |
b4a63d75 SM |
366 | (ENTX address-transfer "enter X" 55 |
367 | "Literal value is stored in rX. | |
0a2d0bd4 | 368 | Indexed, stores value of index in rX." |
b4a63d75 | 369 | 1) |
0a2d0bd4 | 370 | |
b4a63d75 SM |
371 | (ENT1 address-transfer "Enter rI1" ,(+ 48 1) |
372 | "Literal value is stored in rI1. | |
0a2d0bd4 | 373 | Indexed, stores value of index in rI1." |
b4a63d75 | 374 | 1) |
0a2d0bd4 | 375 | |
b4a63d75 SM |
376 | (ENT2 address-transfer "Enter rI2" ,(+ 48 2) |
377 | "Literal value is stored in rI2. | |
0a2d0bd4 | 378 | Indexed, stores value of index in rI2." |
b4a63d75 | 379 | 1) |
0a2d0bd4 | 380 | |
b4a63d75 SM |
381 | (ENT3 address-transfer "Enter rI3" ,(+ 48 3) |
382 | "Literal value is stored in rI3. | |
0a2d0bd4 | 383 | Indexed, stores value of index in rI3." |
b4a63d75 | 384 | 1) |
0a2d0bd4 | 385 | |
b4a63d75 SM |
386 | (ENT4 address-transfer "Enter rI4" ,(+ 48 4) |
387 | "Literal value is stored in rI4. | |
0a2d0bd4 | 388 | Indexed, stores value of index in rI4." |
b4a63d75 | 389 | 1) |
0a2d0bd4 | 390 | |
b4a63d75 SM |
391 | (ENT5 address-transfer "Enter rI5" ,(+ 48 5) |
392 | "Literal value is stored in rI5. | |
0a2d0bd4 | 393 | Indexed, stores value of index in rI5." |
b4a63d75 | 394 | 1) |
0a2d0bd4 | 395 | |
b4a63d75 SM |
396 | (ENT6 address-transfer "Enter rI6" ,(+ 48 6) |
397 | "Literal value is stored in rI6. | |
0a2d0bd4 | 398 | Indexed, stores value of index in rI6." |
b4a63d75 | 399 | 1) |
0a2d0bd4 | 400 | |
b4a63d75 SM |
401 | (ENNA address-transfer "enter negative A" 48 |
402 | "Literal value is stored in rA with opposite sign. | |
0a2d0bd4 | 403 | Indexed, stores value of index in rA with opposite sign." |
b4a63d75 | 404 | 1) |
0a2d0bd4 | 405 | |
b4a63d75 SM |
406 | (ENNX address-transfer "enter negative X" 55 |
407 | "Literal value is stored in rX with opposite sign. | |
0a2d0bd4 | 408 | Indexed, stores value of index in rX with opposite sign." |
b4a63d75 | 409 | 1) |
0a2d0bd4 | 410 | |
b4a63d75 SM |
411 | (ENN1 address-transfer "Enter negative rI1" ,(+ 48 1) |
412 | "Literal value is stored in rI1 with opposite sign. | |
0a2d0bd4 | 413 | Indexed, stores value of index in rI1 with opposite sign." |
b4a63d75 | 414 | 1) |
0a2d0bd4 | 415 | |
b4a63d75 SM |
416 | (ENN2 address-transfer "Enter negative rI2" ,(+ 48 2) |
417 | "Literal value is stored in rI2 with opposite sign. | |
0a2d0bd4 | 418 | Indexed, stores value of index in rI2 with opposite sign." |
b4a63d75 | 419 | 1) |
0a2d0bd4 | 420 | |
b4a63d75 SM |
421 | (ENN3 address-transfer "Enter negative rI3" ,(+ 48 3) |
422 | "Literal value is stored in rI3 with opposite sign. | |
0a2d0bd4 | 423 | Indexed, stores value of index in rI3 with opposite sign." |
b4a63d75 | 424 | 1) |
0a2d0bd4 | 425 | |
b4a63d75 SM |
426 | (ENN4 address-transfer "Enter negative rI4" ,(+ 48 4) |
427 | "Literal value is stored in rI4 with opposite sign. | |
0a2d0bd4 | 428 | Indexed, stores value of index in rI4 with opposite sign." |
b4a63d75 | 429 | 1) |
0a2d0bd4 | 430 | |
b4a63d75 SM |
431 | (ENN5 address-transfer "Enter negative rI5" ,(+ 48 5) |
432 | "Literal value is stored in rI5 with opposite sign. | |
0a2d0bd4 | 433 | Indexed, stores value of index in rI5 with opposite sign." |
b4a63d75 | 434 | 1) |
0a2d0bd4 | 435 | |
b4a63d75 SM |
436 | (ENN6 address-transfer "Enter negative rI6" ,(+ 48 6) |
437 | "Literal value is stored in rI6 with opposite sign. | |
0a2d0bd4 | 438 | Indexed, stores value of index in rI6 with opposite sign." |
b4a63d75 | 439 | 1) |
0a2d0bd4 | 440 | |
b4a63d75 SM |
441 | (INCA address-transfer "increase A" 48 |
442 | "Increase register A with the literal value of M. | |
0a2d0bd4 | 443 | On overflow the overflow toggle is set." |
b4a63d75 | 444 | 1) |
0a2d0bd4 | 445 | |
b4a63d75 SM |
446 | (INCX address-transfer "increase X" 55 |
447 | "Increase register X with the literal value of M. | |
0a2d0bd4 | 448 | On overflow the overflow toggle is set." |
b4a63d75 | 449 | 1) |
0a2d0bd4 | 450 | |
b4a63d75 SM |
451 | (INC1 address-transfer "increase I1" ,(+ 48 1) |
452 | "Increase register I1 with the literal value of M. | |
0a2d0bd4 JB |
453 | The result is undefined when the result does not fit in |
454 | 2 bytes." | |
b4a63d75 | 455 | 1) |
0a2d0bd4 | 456 | |
b4a63d75 SM |
457 | (INC2 address-transfer "increase I2" ,(+ 48 2) |
458 | "Increase register I2 with the literal value of M. | |
0a2d0bd4 JB |
459 | The result is undefined when the result does not fit in |
460 | 2 bytes." | |
b4a63d75 | 461 | 1) |
0a2d0bd4 | 462 | |
b4a63d75 SM |
463 | (INC3 address-transfer "increase I3" ,(+ 48 3) |
464 | "Increase register I3 with the literal value of M. | |
0a2d0bd4 JB |
465 | The result is undefined when the result does not fit in |
466 | 2 bytes." | |
b4a63d75 | 467 | 1) |
0a2d0bd4 | 468 | |
b4a63d75 SM |
469 | (INC4 address-transfer "increase I4" ,(+ 48 4) |
470 | "Increase register I4 with the literal value of M. | |
0a2d0bd4 JB |
471 | The result is undefined when the result does not fit in |
472 | 2 bytes." | |
b4a63d75 | 473 | 1) |
0a2d0bd4 | 474 | |
b4a63d75 SM |
475 | (INC5 address-transfer "increase I5" ,(+ 48 5) |
476 | "Increase register I5 with the literal value of M. | |
0a2d0bd4 JB |
477 | The result is undefined when the result does not fit in |
478 | 2 bytes." | |
b4a63d75 | 479 | 1) |
0a2d0bd4 | 480 | |
b4a63d75 SM |
481 | (INC6 address-transfer "increase I6" ,(+ 48 6) |
482 | "Increase register I6 with the literal value of M. | |
0a2d0bd4 JB |
483 | The result is undefined when the result does not fit in |
484 | 2 bytes." | |
b4a63d75 | 485 | 1) |
0a2d0bd4 | 486 | |
b4a63d75 SM |
487 | (DECA address-transfer "decrease A" 48 |
488 | "Decrease register A with the literal value of M. | |
0a2d0bd4 | 489 | On overflow the overflow toggle is set." |
b4a63d75 | 490 | 1) |
0a2d0bd4 | 491 | |
b4a63d75 SM |
492 | (DECX address-transfer "decrease X" 55 |
493 | "Decrease register X with the literal value of M. | |
0a2d0bd4 | 494 | On overflow the overflow toggle is set." |
b4a63d75 | 495 | 1) |
0a2d0bd4 | 496 | |
b4a63d75 SM |
497 | (DEC1 address-transfer "decrease I1" ,(+ 48 1) |
498 | "Decrease register I1 with the literal value of M. | |
0a2d0bd4 JB |
499 | The result is undefined when the result does not fit in |
500 | 2 bytes." | |
b4a63d75 | 501 | 1) |
0a2d0bd4 | 502 | |
b4a63d75 SM |
503 | (DEC2 address-transfer "decrease I2" ,(+ 48 2) |
504 | "Decrease register I2 with the literal value of M. | |
0a2d0bd4 JB |
505 | The result is undefined when the result does not fit in |
506 | 2 bytes." | |
b4a63d75 | 507 | 1) |
0a2d0bd4 | 508 | |
b4a63d75 SM |
509 | (DEC3 address-transfer "decrease I3" ,(+ 48 3) |
510 | "Decrease register I3 with the literal value of M. | |
0a2d0bd4 JB |
511 | The result is undefined when the result does not fit in |
512 | 2 bytes." | |
b4a63d75 | 513 | 1) |
0a2d0bd4 | 514 | |
b4a63d75 SM |
515 | (DEC4 address-transfer "decrease I4" ,(+ 48 4) |
516 | "Decrease register I4 with the literal value of M. | |
0a2d0bd4 JB |
517 | The result is undefined when the result does not fit in |
518 | 2 bytes." | |
b4a63d75 | 519 | 1) |
0a2d0bd4 | 520 | |
b4a63d75 SM |
521 | (DEC5 address-transfer "decrease I5" ,(+ 48 5) |
522 | "Decrease register I5 with the literal value of M. | |
0a2d0bd4 JB |
523 | The result is undefined when the result does not fit in |
524 | 2 bytes." | |
b4a63d75 | 525 | 1) |
0a2d0bd4 | 526 | |
b4a63d75 SM |
527 | (DEC6 address-transfer "decrease I6" ,(+ 48 6) |
528 | "Decrease register I6 with the literal value of M. | |
0a2d0bd4 JB |
529 | The result is undefined when the result does not fit in |
530 | 2 bytes." | |
b4a63d75 | 531 | 1) |
0a2d0bd4 | 532 | |
b4a63d75 SM |
533 | (CMPA comparison "compare A" 56 field |
534 | "Compare contents of A with contents of M. | |
0a2d0bd4 JB |
535 | The field specifier works on both fields. The comparison indicator |
536 | is set to LESS, EQUAL or GREATER depending on the outcome." | |
b4a63d75 | 537 | 2) |
0a2d0bd4 JB |
538 | |
539 | ||
b4a63d75 SM |
540 | (CMPX comparison "compare X" 63 field |
541 | "Compare contents of rX with contents of M. | |
0a2d0bd4 JB |
542 | The field specifier works on both fields. The comparison indicator |
543 | is set to LESS, EQUAL or GREATER depending on the outcome." | |
b4a63d75 | 544 | 2) |
0a2d0bd4 JB |
545 | |
546 | ||
b4a63d75 SM |
547 | (CMP1 comparison "compare I1" ,(+ 56 1) field |
548 | "Compare contents of rI1 with contents of M. | |
0a2d0bd4 JB |
549 | The field specifier works on both fields. The comparison indicator |
550 | is set to LESS, EQUAL or GREATER depending on the outcome. Bit 1,2 and 3 | |
551 | have a value of 0." | |
b4a63d75 | 552 | 2) |
0a2d0bd4 JB |
553 | |
554 | ||
b4a63d75 SM |
555 | (CMP2 comparison "compare I2" ,(+ 56 2) field |
556 | "Compare contents of rI2 with contents of M. | |
0a2d0bd4 JB |
557 | The field specifier works on both fields. The comparison indicator |
558 | is set to LESS, EQUAL or GREATER depending on the outcome. Bit 1,2 and 3 | |
559 | have a value of 0." | |
b4a63d75 | 560 | 2) |
0a2d0bd4 JB |
561 | |
562 | ||
b4a63d75 SM |
563 | (CMP3 comparison "compare I3" ,(+ 56 3) field |
564 | "Compare contents of rI3 with contents of M. | |
0a2d0bd4 JB |
565 | The field specifier works on both fields. The comparison indicator |
566 | is set to LESS, EQUAL or GREATER depending on the outcome. Bit 1,2 and 3 | |
567 | have a value of 0." | |
b4a63d75 | 568 | 2) |
0a2d0bd4 JB |
569 | |
570 | ||
b4a63d75 SM |
571 | (CMP4 comparison "compare I4" ,(+ 56 4) field |
572 | "Compare contents of rI4 with contents of M. | |
0a2d0bd4 JB |
573 | The field specifier works on both fields. The comparison indicator |
574 | is set to LESS, EQUAL or GREATER depending on the outcome. Bit 1,2 and 3 | |
575 | have a value of 0." | |
b4a63d75 | 576 | 2) |
0a2d0bd4 JB |
577 | |
578 | ||
b4a63d75 SM |
579 | (CMP5 comparison "compare I5" ,(+ 56 5) field |
580 | "Compare contents of rI5 with contents of M. | |
0a2d0bd4 JB |
581 | The field specifier works on both fields. The comparison indicator |
582 | is set to LESS, EQUAL or GREATER depending on the outcome. Bit 1,2 and 3 | |
583 | have a value of 0." | |
b4a63d75 | 584 | 2) |
0a2d0bd4 JB |
585 | |
586 | ||
b4a63d75 SM |
587 | (CMP6 comparison "compare I6" ,(+ 56 6) field |
588 | "Compare contents of rI6 with contents of M. | |
0a2d0bd4 JB |
589 | The field specifier works on both fields. The comparison indicator |
590 | is set to LESS, EQUAL or GREATER depending on the outcome. Bit 1,2 and 3 | |
591 | have a value of 0." | |
b4a63d75 | 592 | 2) |
0a2d0bd4 | 593 | |
b4a63d75 SM |
594 | (JMP jump "jump" 39 |
595 | "Unconditional jump. | |
0a2d0bd4 JB |
596 | Register J is set to the value of the next instruction that would have |
597 | been executed when there was no jump." | |
b4a63d75 | 598 | 1) |
0a2d0bd4 | 599 | |
b4a63d75 SM |
600 | (JSJ jump "jump, save J" 39 |
601 | "Unconditional jump, but rJ is not modified." | |
602 | 1) | |
0a2d0bd4 | 603 | |
b4a63d75 SM |
604 | (JOV jump "jump on overflow" 39 |
605 | "Jump if OV is set (and turn it off). | |
0a2d0bd4 JB |
606 | Register J is set to the value of the next instruction that would have |
607 | been executed when there was no jump." | |
b4a63d75 | 608 | 1) |
0a2d0bd4 | 609 | |
b4a63d75 SM |
610 | (JNOV jump "Jump on no overflow" 39 |
611 | "Jump if OV is not set (and turn it off). | |
0a2d0bd4 JB |
612 | Register J is set to the value of the next instruction that would have |
613 | been executed when there was no jump." | |
b4a63d75 | 614 | 1) |
0a2d0bd4 | 615 | |
b4a63d75 SM |
616 | (JL jump "Jump on less" 39 |
617 | "Jump if '[CM] = L'. | |
0a2d0bd4 JB |
618 | Register J is set to the value of the next instruction that would have |
619 | been executed when there was no jump." | |
b4a63d75 | 620 | 1) |
0a2d0bd4 JB |
621 | |
622 | ||
b4a63d75 SM |
623 | (JE jump "Jump on equal" 39 |
624 | "Jump if '[CM] = E'. | |
0a2d0bd4 JB |
625 | Register J is set to the value of the next instruction that would have |
626 | been executed when there was no jump." | |
b4a63d75 | 627 | 1) |
0a2d0bd4 JB |
628 | |
629 | ||
b4a63d75 SM |
630 | (JG jump "Jump on greater" 39 |
631 | "Jump if '[CM] = G'. | |
0a2d0bd4 JB |
632 | Register J is set to the value of the next instruction that would have |
633 | been executed when there was no jump." | |
b4a63d75 | 634 | 1) |
0a2d0bd4 JB |
635 | |
636 | ||
b4a63d75 SM |
637 | (JGE jump "Jump on not less" 39 |
638 | "Jump if '[CM]' does not equal 'L'. | |
0a2d0bd4 JB |
639 | Register J is set to the value of the next instruction that would have |
640 | been executed when there was no jump." | |
b4a63d75 | 641 | 1) |
0a2d0bd4 JB |
642 | |
643 | ||
b4a63d75 SM |
644 | (JNE jump "Jump on not equal" 39 |
645 | "Jump if '[CM]' does not equal 'E'. | |
0a2d0bd4 JB |
646 | Register J is set to the value of the next instruction that would have |
647 | been executed when there was no jump." | |
b4a63d75 | 648 | 1) |
0a2d0bd4 JB |
649 | |
650 | ||
b4a63d75 SM |
651 | (JLE jump "Jump on not greater" 39 |
652 | "Jump if '[CM]' does not equal 'G'. | |
0a2d0bd4 JB |
653 | Register J is set to the value of the next instruction that would have |
654 | been executed when there was no jump." | |
b4a63d75 | 655 | 1) |
0a2d0bd4 | 656 | |
b4a63d75 SM |
657 | (JAN jump "jump A negative" 40 |
658 | "Jump if the content of rA is negative. | |
0a2d0bd4 JB |
659 | Register J is set to the value of the next instruction that would have |
660 | been executed when there was no jump." | |
b4a63d75 | 661 | 1) |
0a2d0bd4 JB |
662 | |
663 | ||
b4a63d75 SM |
664 | (JAZ jump "jump A zero" 40 |
665 | "Jump if the content of rA is zero. | |
0a2d0bd4 JB |
666 | Register J is set to the value of the next instruction that would have |
667 | been executed when there was no jump." | |
b4a63d75 | 668 | 1) |
0a2d0bd4 JB |
669 | |
670 | ||
b4a63d75 SM |
671 | (JAP jump "jump A positive" 40 |
672 | "Jump if the content of rA is positive. | |
0a2d0bd4 JB |
673 | Register J is set to the value of the next instruction that would have |
674 | been executed when there was no jump." | |
b4a63d75 | 675 | 1) |
0a2d0bd4 JB |
676 | |
677 | ||
b4a63d75 SM |
678 | (JANN jump "jump A non-negative" 40 |
679 | "Jump if the content of rA is non-negative. | |
0a2d0bd4 JB |
680 | Register J is set to the value of the next instruction that would have |
681 | been executed when there was no jump." | |
b4a63d75 | 682 | 1) |
0a2d0bd4 JB |
683 | |
684 | ||
b4a63d75 SM |
685 | (JANZ jump "jump A non-zero" 40 |
686 | "Jump if the content of rA is non-zero. | |
0a2d0bd4 JB |
687 | Register J is set to the value of the next instruction that would have |
688 | been executed when there was no jump." | |
b4a63d75 | 689 | 1) |
0a2d0bd4 JB |
690 | |
691 | ||
b4a63d75 SM |
692 | (JANP jump "jump A non-positive" 40 |
693 | "Jump if the content of rA is non-positive. | |
0a2d0bd4 JB |
694 | Register J is set to the value of the next instruction that would have |
695 | been executed when there was no jump." | |
b4a63d75 | 696 | 1) |
0a2d0bd4 | 697 | |
b4a63d75 SM |
698 | (JXN jump "jump X negative" 47 |
699 | "Jump if the content of rX is negative. | |
0a2d0bd4 JB |
700 | Register J is set to the value of the next instruction that would have |
701 | been executed when there was no jump." | |
b4a63d75 | 702 | 1) |
0a2d0bd4 JB |
703 | |
704 | ||
b4a63d75 SM |
705 | (JXZ jump "jump X zero" 47 |
706 | "Jump if the content of rX is zero. | |
0a2d0bd4 JB |
707 | Register J is set to the value of the next instruction that would have |
708 | been executed when there was no jump." | |
b4a63d75 | 709 | 1) |
0a2d0bd4 JB |
710 | |
711 | ||
b4a63d75 SM |
712 | (JXP jump "jump X positive" 47 |
713 | "Jump if the content of rX is positive. | |
0a2d0bd4 JB |
714 | Register J is set to the value of the next instruction that would have |
715 | been executed when there was no jump." | |
b4a63d75 | 716 | 1) |
0a2d0bd4 JB |
717 | |
718 | ||
b4a63d75 SM |
719 | (JXNN jump "jump X non-negative" 47 |
720 | "Jump if the content of rX is non-negative. | |
0a2d0bd4 JB |
721 | Register J is set to the value of the next instruction that would have |
722 | been executed when there was no jump." | |
b4a63d75 | 723 | 1) |
0a2d0bd4 JB |
724 | |
725 | ||
b4a63d75 SM |
726 | (JXNZ jump "jump X non-zero" 47 |
727 | "Jump if the content of rX is non-zero. | |
0a2d0bd4 JB |
728 | Register J is set to the value of the next instruction that would have |
729 | been executed when there was no jump." | |
b4a63d75 | 730 | 1) |
0a2d0bd4 JB |
731 | |
732 | ||
b4a63d75 SM |
733 | (JXNP jump "jump X non-positive" 47 |
734 | "Jump if the content of rX is non-positive. | |
0a2d0bd4 JB |
735 | Register J is set to the value of the next instruction that would have |
736 | been executed when there was no jump." | |
b4a63d75 | 737 | 1) |
0a2d0bd4 | 738 | |
b4a63d75 SM |
739 | (J1N jump "jump I1 negative" ,(+ 40 1) |
740 | "Jump if the content of rI1 is negative. | |
0a2d0bd4 JB |
741 | Register J is set to the value of the next instruction that would have |
742 | been executed when there was no jump." | |
b4a63d75 | 743 | 1) |
0a2d0bd4 JB |
744 | |
745 | ||
b4a63d75 SM |
746 | (J1Z jump "jump I1 zero" ,(+ 40 1) |
747 | "Jump if the content of rI1 is zero. | |
0a2d0bd4 JB |
748 | Register J is set to the value of the next instruction that would have |
749 | been executed when there was no jump." | |
b4a63d75 | 750 | 1) |
0a2d0bd4 JB |
751 | |
752 | ||
b4a63d75 SM |
753 | (J1P jump "jump I1 positive" ,(+ 40 1) |
754 | "Jump if the content of rI1 is positive. | |
0a2d0bd4 JB |
755 | Register J is set to the value of the next instruction that would have |
756 | been executed when there was no jump." | |
b4a63d75 | 757 | 1) |
0a2d0bd4 JB |
758 | |
759 | ||
b4a63d75 SM |
760 | (J1NN jump "jump I1 non-negative" ,(+ 40 1) |
761 | "Jump if the content of rI1 is non-negative. | |
0a2d0bd4 JB |
762 | Register J is set to the value of the next instruction that would have |
763 | been executed when there was no jump." | |
b4a63d75 | 764 | 1) |
0a2d0bd4 JB |
765 | |
766 | ||
b4a63d75 SM |
767 | (J1NZ jump "jump I1 non-zero" ,(+ 40 1) |
768 | "Jump if the content of rI1 is non-zero. | |
0a2d0bd4 JB |
769 | Register J is set to the value of the next instruction that would have |
770 | been executed when there was no jump." | |
b4a63d75 | 771 | 1) |
0a2d0bd4 JB |
772 | |
773 | ||
b4a63d75 SM |
774 | (J1NP jump "jump I1 non-positive" ,(+ 40 1) |
775 | "Jump if the content of rI1 is non-positive. | |
0a2d0bd4 JB |
776 | Register J is set to the value of the next instruction that would have |
777 | been executed when there was no jump." | |
b4a63d75 | 778 | 1) |
0a2d0bd4 | 779 | |
b4a63d75 SM |
780 | (J2N jump "jump I2 negative" ,(+ 40 1) |
781 | "Jump if the content of rI2 is negative. | |
0a2d0bd4 JB |
782 | Register J is set to the value of the next instruction that would have |
783 | been executed when there was no jump." | |
b4a63d75 | 784 | 1) |
0a2d0bd4 JB |
785 | |
786 | ||
b4a63d75 SM |
787 | (J2Z jump "jump I2 zero" ,(+ 40 1) |
788 | "Jump if the content of rI2 is zero. | |
0a2d0bd4 JB |
789 | Register J is set to the value of the next instruction that would have |
790 | been executed when there was no jump." | |
b4a63d75 | 791 | 1) |
0a2d0bd4 JB |
792 | |
793 | ||
b4a63d75 SM |
794 | (J2P jump "jump I2 positive" ,(+ 40 1) |
795 | "Jump if the content of rI2 is positive. | |
0a2d0bd4 JB |
796 | Register J is set to the value of the next instruction that would have |
797 | been executed when there was no jump." | |
b4a63d75 | 798 | 1) |
0a2d0bd4 JB |
799 | |
800 | ||
b4a63d75 SM |
801 | (J2NN jump "jump I2 non-negative" ,(+ 40 1) |
802 | "Jump if the content of rI2 is non-negative. | |
0a2d0bd4 JB |
803 | Register J is set to the value of the next instruction that would have |
804 | been executed when there was no jump." | |
b4a63d75 | 805 | 1) |
0a2d0bd4 JB |
806 | |
807 | ||
b4a63d75 SM |
808 | (J2NZ jump "jump I2 non-zero" ,(+ 40 1) |
809 | "Jump if the content of rI2 is non-zero. | |
0a2d0bd4 JB |
810 | Register J is set to the value of the next instruction that would have |
811 | been executed when there was no jump." | |
b4a63d75 | 812 | 1) |
0a2d0bd4 JB |
813 | |
814 | ||
b4a63d75 SM |
815 | (J2NP jump "jump I2 non-positive" ,(+ 40 1) |
816 | "Jump if the content of rI2 is non-positive. | |
0a2d0bd4 JB |
817 | Register J is set to the value of the next instruction that would have |
818 | been executed when there was no jump." | |
b4a63d75 | 819 | 1) |
0a2d0bd4 JB |
820 | |
821 | ||
b4a63d75 SM |
822 | (J3N jump "jump I3 negative" ,(+ 40 1) |
823 | "Jump if the content of rI3 is negative. | |
0a2d0bd4 JB |
824 | Register J is set to the value of the next instruction that would have |
825 | been executed when there was no jump." | |
b4a63d75 | 826 | 1) |
0a2d0bd4 JB |
827 | |
828 | ||
b4a63d75 SM |
829 | (J3Z jump "jump I3 zero" ,(+ 40 1) |
830 | "Jump if the content of rI3 is zero. | |
0a2d0bd4 JB |
831 | Register J is set to the value of the next instruction that would have |
832 | been executed when there was no jump." | |
b4a63d75 | 833 | 1) |
0a2d0bd4 JB |
834 | |
835 | ||
b4a63d75 SM |
836 | (J3P jump "jump I3 positive" ,(+ 40 1) |
837 | "Jump if the content of rI3 is positive. | |
0a2d0bd4 JB |
838 | Register J is set to the value of the next instruction that would have |
839 | been executed when there was no jump." | |
b4a63d75 | 840 | 1) |
0a2d0bd4 JB |
841 | |
842 | ||
b4a63d75 SM |
843 | (J3NN jump "jump I3 non-negative" ,(+ 40 1) |
844 | "Jump if the content of rI3 is non-negative. | |
0a2d0bd4 JB |
845 | Register J is set to the value of the next instruction that would have |
846 | been executed when there was no jump." | |
b4a63d75 | 847 | 1) |
0a2d0bd4 JB |
848 | |
849 | ||
b4a63d75 SM |
850 | (J3NZ jump "jump I3 non-zero" ,(+ 40 1) |
851 | "Jump if the content of rI3 is non-zero. | |
0a2d0bd4 JB |
852 | Register J is set to the value of the next instruction that would have |
853 | been executed when there was no jump." | |
b4a63d75 | 854 | 1) |
0a2d0bd4 JB |
855 | |
856 | ||
b4a63d75 SM |
857 | (J3NP jump "jump I3 non-positive" ,(+ 40 1) |
858 | "Jump if the content of rI3 is non-positive. | |
0a2d0bd4 JB |
859 | Register J is set to the value of the next instruction that would have |
860 | been executed when there was no jump." | |
b4a63d75 | 861 | 1) |
0a2d0bd4 JB |
862 | |
863 | ||
b4a63d75 SM |
864 | (J4N jump "jump I4 negative" ,(+ 40 1) |
865 | "Jump if the content of rI4 is negative. | |
0a2d0bd4 JB |
866 | Register J is set to the value of the next instruction that would have |
867 | been executed when there was no jump." | |
b4a63d75 | 868 | 1) |
0a2d0bd4 JB |
869 | |
870 | ||
b4a63d75 SM |
871 | (J4Z jump "jump I4 zero" ,(+ 40 1) |
872 | "Jump if the content of rI4 is zero. | |
0a2d0bd4 JB |
873 | Register J is set to the value of the next instruction that would have |
874 | been executed when there was no jump." | |
b4a63d75 | 875 | 1) |
0a2d0bd4 JB |
876 | |
877 | ||
b4a63d75 SM |
878 | (J4P jump "jump I4 positive" ,(+ 40 1) |
879 | "Jump if the content of rI4 is positive. | |
0a2d0bd4 JB |
880 | Register J is set to the value of the next instruction that would have |
881 | been executed when there was no jump." | |
b4a63d75 | 882 | 1) |
0a2d0bd4 JB |
883 | |
884 | ||
b4a63d75 SM |
885 | (J4NN jump "jump I4 non-negative" ,(+ 40 1) |
886 | "Jump if the content of rI4 is non-negative. | |
0a2d0bd4 JB |
887 | Register J is set to the value of the next instruction that would have |
888 | been executed when there was no jump." | |
b4a63d75 | 889 | 1) |
0a2d0bd4 JB |
890 | |
891 | ||
b4a63d75 SM |
892 | (J4NZ jump "jump I4 non-zero" ,(+ 40 1) |
893 | "Jump if the content of rI4 is non-zero. | |
0a2d0bd4 JB |
894 | Register J is set to the value of the next instruction that would have |
895 | been executed when there was no jump." | |
b4a63d75 | 896 | 1) |
0a2d0bd4 JB |
897 | |
898 | ||
b4a63d75 SM |
899 | (J4NP jump "jump I4 non-positive" ,(+ 40 1) |
900 | "Jump if the content of rI4 is non-positive. | |
0a2d0bd4 JB |
901 | Register J is set to the value of the next instruction that would have |
902 | been executed when there was no jump." | |
b4a63d75 | 903 | 1) |
0a2d0bd4 JB |
904 | |
905 | ||
b4a63d75 SM |
906 | (J5N jump "jump I5 negative" ,(+ 40 1) |
907 | "Jump if the content of rI5 is negative. | |
0a2d0bd4 JB |
908 | Register J is set to the value of the next instruction that would have |
909 | been executed when there was no jump." | |
b4a63d75 | 910 | 1) |
0a2d0bd4 JB |
911 | |
912 | ||
b4a63d75 SM |
913 | (J5Z jump "jump I5 zero" ,(+ 40 1) |
914 | "Jump if the content of rI5 is zero. | |
0a2d0bd4 JB |
915 | Register J is set to the value of the next instruction that would have |
916 | been executed when there was no jump." | |
b4a63d75 | 917 | 1) |
0a2d0bd4 JB |
918 | |
919 | ||
b4a63d75 SM |
920 | (J5P jump "jump I5 positive" ,(+ 40 1) |
921 | "Jump if the content of rI5 is positive. | |
0a2d0bd4 JB |
922 | Register J is set to the value of the next instruction that would have |
923 | been executed when there was no jump." | |
b4a63d75 | 924 | 1) |
0a2d0bd4 JB |
925 | |
926 | ||
b4a63d75 SM |
927 | (J5NN jump "jump I5 non-negative" ,(+ 40 1) |
928 | "Jump if the content of rI5 is non-negative. | |
0a2d0bd4 JB |
929 | Register J is set to the value of the next instruction that would have |
930 | been executed when there was no jump." | |
b4a63d75 | 931 | 1) |
0a2d0bd4 JB |
932 | |
933 | ||
b4a63d75 SM |
934 | (J5NZ jump "jump I5 non-zero" ,(+ 40 1) |
935 | "Jump if the content of rI5 is non-zero. | |
0a2d0bd4 JB |
936 | Register J is set to the value of the next instruction that would have |
937 | been executed when there was no jump." | |
b4a63d75 | 938 | 1) |
0a2d0bd4 JB |
939 | |
940 | ||
b4a63d75 SM |
941 | (J5NP jump "jump I5 non-positive" ,(+ 40 1) |
942 | "Jump if the content of rI5 is non-positive. | |
0a2d0bd4 JB |
943 | Register J is set to the value of the next instruction that would have |
944 | been executed when there was no jump." | |
b4a63d75 | 945 | 1) |
0a2d0bd4 JB |
946 | |
947 | ||
b4a63d75 SM |
948 | (J6N jump "jump I6 negative" ,(+ 40 1) |
949 | "Jump if the content of rI6 is negative. | |
0a2d0bd4 JB |
950 | Register J is set to the value of the next instruction that would have |
951 | been executed when there was no jump." | |
b4a63d75 | 952 | 1) |
0a2d0bd4 JB |
953 | |
954 | ||
b4a63d75 SM |
955 | (J6Z jump "jump I6 zero" ,(+ 40 1) |
956 | "Jump if the content of rI6 is zero. | |
0a2d0bd4 JB |
957 | Register J is set to the value of the next instruction that would have |
958 | been executed when there was no jump." | |
b4a63d75 | 959 | 1) |
0a2d0bd4 JB |
960 | |
961 | ||
b4a63d75 SM |
962 | (J6P jump "jump I6 positive" ,(+ 40 1) |
963 | "Jump if the content of rI6 is positive. | |
0a2d0bd4 JB |
964 | Register J is set to the value of the next instruction that would have |
965 | been executed when there was no jump." | |
b4a63d75 | 966 | 1) |
0a2d0bd4 JB |
967 | |
968 | ||
b4a63d75 SM |
969 | (J6NN jump "jump I6 non-negative" ,(+ 40 1) |
970 | "Jump if the content of rI6 is non-negative. | |
0a2d0bd4 JB |
971 | Register J is set to the value of the next instruction that would have |
972 | been executed when there was no jump." | |
b4a63d75 | 973 | 1) |
0a2d0bd4 JB |
974 | |
975 | ||
b4a63d75 SM |
976 | (J6NZ jump "jump I6 non-zero" ,(+ 40 1) |
977 | "Jump if the content of rI6 is non-zero. | |
0a2d0bd4 JB |
978 | Register J is set to the value of the next instruction that would have |
979 | been executed when there was no jump." | |
b4a63d75 | 980 | 1) |
0a2d0bd4 JB |
981 | |
982 | ||
b4a63d75 SM |
983 | (J6NP jump "jump I6 non-positive" ,(+ 40 1) |
984 | "Jump if the content of rI6 is non-positive. | |
0a2d0bd4 JB |
985 | Register J is set to the value of the next instruction that would have |
986 | been executed when there was no jump." | |
b4a63d75 | 987 | 1) |
0a2d0bd4 | 988 | |
b4a63d75 SM |
989 | (SLA miscellaneous "shift left A" 6 |
990 | "Shift to A, M bytes left. | |
0a2d0bd4 | 991 | Hero's will be added to the right." |
b4a63d75 | 992 | 2) |
0a2d0bd4 JB |
993 | |
994 | ||
b4a63d75 SM |
995 | (SRA miscellaneous "shift right A" 6 |
996 | "Shift to A, M bytes right. | |
0a2d0bd4 | 997 | Zeros will be added to the left." |
b4a63d75 | 998 | 2) |
0a2d0bd4 JB |
999 | |
1000 | ||
b4a63d75 SM |
1001 | (SLAX miscellaneous "shift left AX" 6 |
1002 | "Shift AX, M bytes left. | |
0a2d0bd4 | 1003 | Zeros will be added to the right." |
b4a63d75 | 1004 | 2) |
0a2d0bd4 JB |
1005 | |
1006 | ||
1007 | ||
b4a63d75 SM |
1008 | (SRAX miscellaneous "shift right AX" 6 |
1009 | "Shift AX, M bytes right. | |
0a2d0bd4 | 1010 | Zeros will be added to the left." |
b4a63d75 | 1011 | 2) |
0a2d0bd4 JB |
1012 | |
1013 | ||
b4a63d75 SM |
1014 | (SLC miscellaneous "shift left AX circularly" 6 |
1015 | "Shift AX, M bytes left circularly. | |
0a2d0bd4 | 1016 | The bytes that fall off to the left will be added to the right." |
b4a63d75 | 1017 | 2) |
0a2d0bd4 JB |
1018 | |
1019 | ||
b4a63d75 SM |
1020 | (SRC miscellaneous "shift right AX circularly" 6 |
1021 | "Shift AX, M bytes right circularly. | |
0a2d0bd4 | 1022 | The bytes that fall off to the right will be added to the left." |
b4a63d75 | 1023 | 2) |
0a2d0bd4 | 1024 | |
b4a63d75 SM |
1025 | (MOVE miscellaneous "move" 7 number |
1026 | "Move MOD words from M to the location stored in rI1." | |
1027 | (+ 1 (* 2 number))) | |
0a2d0bd4 | 1028 | |
b4a63d75 SM |
1029 | (NOP miscellaneous "no operation" 0 ignored |
1030 | "No operation, M and F are not used by the machine." | |
1031 | 1) | |
0a2d0bd4 | 1032 | |
b4a63d75 SM |
1033 | (HLT miscellaneous "halt" 5 |
1034 | "Halt. | |
0a2d0bd4 | 1035 | Stop instruction fetching." |
b4a63d75 | 1036 | 1) |
0a2d0bd4 | 1037 | |
b4a63d75 SM |
1038 | (IN input-output "input" 36 unit |
1039 | "Transfer a block of words from the specified unit to memory. | |
0a2d0bd4 | 1040 | The transfer starts at address M." |
b4a63d75 | 1041 | 1) |
0a2d0bd4 | 1042 | |
b4a63d75 SM |
1043 | (OUT input-output "output" 37 unit |
1044 | "Transfer a block of words from memory. | |
0a2d0bd4 | 1045 | The transfer starts at address M to the specified unit." |
b4a63d75 | 1046 | 1) |
0a2d0bd4 | 1047 | |
b4a63d75 SM |
1048 | (IOC input-output "input-output control" 35 unit |
1049 | "Perform a control operation. | |
0a2d0bd4 | 1050 | The control operation is given by M on the specified unit." |
b4a63d75 | 1051 | 1) |
0a2d0bd4 | 1052 | |
b4a63d75 SM |
1053 | (JRED input-output "jump ready" 38 unit |
1054 | "Jump to M if the specified unit is ready." | |
1055 | 1) | |
0a2d0bd4 JB |
1056 | |
1057 | ||
b4a63d75 SM |
1058 | (JBUS input-output "jump busy" 34 unit |
1059 | "Jump to M if the specified unit is busy." | |
1060 | 1) | |
0a2d0bd4 | 1061 | |
b4a63d75 SM |
1062 | (NUM conversion "convert to numeric" 5 |
1063 | "Convert rAX to its numerical value and store it in rA. | |
0a2d0bd4 JB |
1064 | the register rAX is assumed to contain a character representation of |
1065 | a number." | |
b4a63d75 | 1066 | 10) |
0a2d0bd4 | 1067 | |
b4a63d75 SM |
1068 | (CHAR conversion "convert to characters" 5 |
1069 | "Convert the number stored in rA to a character representation. | |
0a2d0bd4 | 1070 | The converted character representation is stored in rAX." |
b4a63d75 | 1071 | 10))) |
0471d426 SM |
1072 | |
1073 | "Alist that contains all the possible operation codes for mix. | |
1074 | Each elt has the form | |
1075 | (OP-CODE GROUP FULL-NAME C-BYTE F-BYTE DESCRIPTION EXECUTION-TIME) | |
1076 | Where OP-CODE is the text of the opcode as an symbol, | |
1077 | FULL-NAME is the human readable name as a string, | |
1078 | C-BYTE is the operation code telling what operation is to be performed, | |
1079 | F-BYTE holds a modification of the operation code which can be a symbol | |
1080 | or a number, | |
1081 | DESCRIPTION contains an string with a description about the operation code and | |
1082 | EXECUTION-TIME holds info about the time it takes, number or string.") | |
1083 | ;; (makunbound 'mixal-operation-codes-alist) | |
1084 | ||
1085 | ||
1086 | ;;; Font-locking: | |
1087 | (defvar mixal-font-lock-syntactic-keywords | |
1088 | ;; Normal comments start with a * in column 0 and end at end of line. | |
1089 | '(("^\\*" (0 '(11))) ;(string-to-syntax "<") == '(11) | |
1090 | ;; Every line can end with a comment which is placed after the operand. | |
1091 | ;; I assume here that mnemonics without operands can not have a comment. | |
1092 | ("^[[:alnum:]]*[ \t]+[[:alnum:]]+[ \t]+[^ \n\t]+[ \t]*\\([ \t]\\)[^\n \t]" | |
1093 | (1 '(11))))) | |
1094 | ||
1095 | (defvar mixal-font-lock-keywords | |
1096 | `(("^\\([A-Z0-9a-z]+\\)" | |
1097 | (1 mixal-font-lock-label-face)) | |
1098 | (,(regexp-opt (mapcar (lambda (x) (symbol-name (car x))) | |
1099 | mixal-operation-codes-alist) 'words) | |
1100 | . mixal-font-lock-operation-code-face) | |
1101 | (,(regexp-opt mixal-assembly-pseudoinstructions 'words) | |
1102 | . mixal-font-lock-assembly-pseudoinstruction-face) | |
1103 | ("^[A-Z0-9a-z]*[ \t]+[A-ZO-9a-z]+[ \t]+\\(=.*=\\)" | |
1104 | (1 font-lock-constant-face))) | |
1105 | "Keyword highlighting specification for `mixal-mode'.") | |
1106 | ;; (makunbound 'mixal-font-lock-keywords) | |
0a2d0bd4 JB |
1107 | |
1108 | (defvar mixal-describe-operation-code-history nil | |
1109 | "History list for describe operation code.") | |
1110 | ||
0471d426 | 1111 | (defun mixal-describe-operation-code (op-code) |
0a2d0bd4 | 1112 | "Display the full documentation of OP-CODE." |
0471d426 SM |
1113 | (interactive |
1114 | (list | |
0a2d0bd4 JB |
1115 | (let* ((completion-ignore-case t) |
1116 | ;; we already have a list, but it is not in the right format | |
1117 | ;; transform it to a valid table so completition can use it | |
1118 | (table (mapcar '(lambda (elm) | |
1119 | (cons (symbol-name (car elm)) nil)) | |
1120 | mixal-operation-codes-alist)) | |
1121 | ;; prompt is different depending on we are close to a valid op-code | |
0471d426 SM |
1122 | (have-default (assq (intern-soft (current-word)) |
1123 | mixal-operation-codes-alist)) | |
0a2d0bd4 JB |
1124 | (prompt (concat "Describe operation code " |
1125 | (if have-default | |
1126 | (concat "(default " (current-word) "): ") | |
1127 | ": ")))) | |
0471d426 SM |
1128 | ;; As the operation code to the user. |
1129 | (completing-read prompt table nil t nil | |
1130 | 'mixal-describe-operation-code-history | |
1131 | (current-word))))) | |
0a2d0bd4 JB |
1132 | ;; get the info on the op-code and output it to the help buffer |
1133 | (let ((op-code-help (assq (intern-soft op-code) mixal-operation-codes-alist))) | |
1134 | (when op-code-help | |
1135 | (with-output-to-temp-buffer (buffer-name (get-buffer-create "*Help*")) | |
1136 | (princ op-code) (princ " is an mix operation code\n\n") | |
1137 | (princ (nth 5 op-code-help)) (terpri) (terpri) | |
1138 | (princ " group: ") (princ (nth 1 op-code-help)) (terpri) | |
1139 | (princ " nice name: ") (princ (nth 2 op-code-help)) (terpri) | |
1140 | (princ " OPCODE / C: ") (princ (nth 3 op-code-help)) (terpri) | |
1141 | (princ " MOD / F: ") (princ (nth 4 op-code-help)) (terpri) | |
1142 | (princ " time: ") (princ (nth 6 op-code-help)) (terpri))))) | |
1143 | ||
1144 | ;;;; Running | |
1145 | (defun mixal-run () | |
f8b4fcda | 1146 | "Run mixal file in current buffer, assumes that file has been compiled." |
0a2d0bd4 JB |
1147 | (interactive) |
1148 | (mixvm (concat "mixvm -r -t -d " | |
1149 | (file-name-sans-extension (buffer-file-name))))) | |
1150 | ||
1151 | (defun mixal-debug () | |
f8b4fcda SM |
1152 | "Start mixvm for debugging. |
1153 | Assumes that file has been compiled with debugging support." | |
0a2d0bd4 JB |
1154 | (interactive) |
1155 | (mixvm (concat "mixvm " | |
1156 | (file-name-sans-extension (buffer-file-name))))) | |
1157 | ||
1158 | ;;;###autoload | |
1159 | (define-derived-mode mixal-mode fundamental-mode "mixal" | |
1160 | "Major mode for the mixal asm language. | |
1161 | \\{mixal-mode-map}" | |
1162 | (set (make-local-variable 'comment-start) "*") | |
0471d426 SM |
1163 | (set (make-local-variable 'comment-start-skip) "^\\*[ \t]*") |
1164 | (set (make-local-variable 'font-lock-defaults) | |
1165 | `(mixal-font-lock-keywords nil nil nil nil | |
1166 | (font-lock-syntactic-keywords . ,mixal-font-lock-syntactic-keywords) | |
1167 | (parse-sexp-lookup-properties . t))) | |
f8b4fcda SM |
1168 | ;; might add an indent function in the future |
1169 | ;; (set (make-local-variable 'indent-line-function) 'mixal-indent-line) | |
1170 | (set (make-local-variable 'compile-command) (concat "mixasm " | |
0a2d0bd4 JB |
1171 | buffer-file-name)) |
1172 | ;; mixasm will do strange when there is no final newline, | |
6c11795e RS |
1173 | ;; so let Emacs ensure that it is always there |
1174 | (set (make-local-variable 'require-final-newline) | |
1175 | mode-require-final-newline)) | |
0a2d0bd4 JB |
1176 | |
1177 | ;;;###autoload | |
1178 | (add-to-list 'auto-mode-alist '("\\.mixal\\'" . mixal-mode)) | |
1179 | ||
1180 | (provide 'mixal-mode) | |
ab5796a9 | 1181 | |
f8b4fcda | 1182 | ;; arch-tag: be7c128a-bf61-4951-a90e-9398267ce3f3 |
0a2d0bd4 | 1183 | ;;; mixal-mode.el ends here |