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0a2d0bd4 JB |
1 | ;;; mixal-mode.el --- Major mode for the mix asm language. |
2 | ||
73b0cd50 | 3 | ;; Copyright (C) 2003-2011 |
d7a0267c | 4 | ;; Free Software Foundation, Inc. |
0a2d0bd4 | 5 | |
f8b4fcda SM |
6 | ;; Author: Pieter E.J. Pareit <pieter.pareit@gmail.com> |
7 | ;; Maintainer: Pieter E.J. Pareit <pieter.pareit@gmail.com> | |
0a2d0bd4 JB |
8 | ;; Created: 09 Nov 2002 |
9 | ;; Version: 0.1 | |
88f4758e | 10 | ;; Keywords: languages, Knuth, mix, mixal, asm, mixvm, The Art Of Computer Programming |
0a2d0bd4 | 11 | |
1a484753 GM |
12 | ;; This file is part of GNU Emacs. |
13 | ||
b1fc2b50 | 14 | ;; GNU Emacs is free software: you can redistribute it and/or modify |
1a484753 | 15 | ;; it under the terms of the GNU General Public License as published by |
b1fc2b50 GM |
16 | ;; the Free Software Foundation, either version 3 of the License, or |
17 | ;; (at your option) any later version. | |
1a484753 GM |
18 | |
19 | ;; GNU Emacs is distributed in the hope that it will be useful, | |
20 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
22 | ;; GNU General Public License for more details. | |
23 | ||
24 | ;; You should have received a copy of the GNU General Public License | |
b1fc2b50 | 25 | ;; along with GNU Emacs. If not, see <http://www.gnu.org/licenses/>. |
1a484753 | 26 | |
0a2d0bd4 JB |
27 | ;;; Commentary: |
28 | ;; Major mode for the mix asm language. | |
29 | ;; The mix asm language is described in "The Art Of Computer Programming". | |
30 | ;; | |
f8b4fcda SM |
31 | ;; For optimal use, also use GNU MDK. Compiling needs mixasm, running |
32 | ;; and debugging needs mixvm and mixvm.el from GNU MDK. You can get | |
0a2d0bd4 JB |
33 | ;; GNU MDK from `https://savannah.gnu.org/projects/mdk/' and |
34 | ;; `ftp://ftp.gnu.org/pub/gnu/mdk'. | |
35 | ;; | |
36 | ;; To use this mode, place the following in your .emacs file: | |
37 | ;; `(load-file "/PATH-TO-FILE/mixal-mode.el")'. | |
38 | ;; When you load a file with the extension .mixal the mode will be started | |
f8b4fcda SM |
39 | ;; automatic. If you want to start the mode manual, use `M-x mixal-mode'. |
40 | ;; Font locking will work, the behavior of tabs is the same as Emacs's | |
41 | ;; default behavior. You can compile a source file with `C-c c' you can | |
0a2d0bd4 JB |
42 | ;; run a compiled file with `C-c r' or run it in debug mode with `C-c d'. |
43 | ;; You can get more information about a particular operation code by using | |
44 | ;; mixal-describe-operation-code or `C-h o'. | |
45 | ;; | |
46 | ;; Have fun. | |
47 | ||
48 | ;;; History: | |
f8b4fcda | 49 | ;; Version 0.3: |
0471d426 SM |
50 | ;; 12/10/05: Stefan Monnier <monnier@iro.umontreal.ca> |
51 | ;; Use font-lock-syntactic-keywords to detect/mark comments. | |
52 | ;; Use [^ \t\n]+ to match the operand part of a line. | |
53 | ;; Drop mixal-operation-codes. | |
54 | ;; Build the mixal-operation-codes-alist immediately. | |
55 | ;; Use `interactive' in mixal-describe-operation-code. | |
56 | ;; Remove useless ".*$" at the end of some regexps. | |
57 | ;; Fix the definition of comment-start-skip. | |
f8b4fcda SM |
58 | ;; 08/10/05: sync mdk and emacs cvs |
59 | ;; from emacs: compile-command and require-final-newline | |
60 | ;; from mdk: see version 0.2 | |
61 | ;; correct my email address | |
62 | ;; Version 0.2: | |
63 | ;; 06/04/05: mixasm no longer needs -g option | |
64 | ;; fontlocking of comments works in all? cases now | |
65 | ;; added some more mixal-operation-codes | |
0a2d0bd4 JB |
66 | ;; Version 0.1: |
67 | ;; Version 0.1.1: | |
68 | ;; 22/11/02: bugfix in fontlocking, needed to add a '-' to the regex. | |
69 | ;; 19/11/02: completed implementing mixal-describe-operation-code. | |
70 | ;; 13/11/02: implemented compile, mixal-run and mixal-debug. | |
71 | ;; 10/11/02: implemented font-locking and syntax table. | |
72 | ;; 09/11/02: started mixal-mode. | |
73 | ||
74 | ;;; Code: | |
3db571c0 JB |
75 | (defvar compile-command) |
76 | ||
0a2d0bd4 JB |
77 | ;;; Key map |
78 | (defvar mixal-mode-map | |
79 | (let ((map (make-sparse-keymap))) | |
a3507bd3 SM |
80 | (define-key map "\C-c\C-c" 'compile) |
81 | (define-key map "\C-c\C-r" 'mixal-run) | |
82 | (define-key map "\C-c\C-d" 'mixal-debug) | |
83 | (define-key map "\C-h\C-o" 'mixal-describe-operation-code) | |
0a2d0bd4 JB |
84 | map) |
85 | "Keymap for `mixal-mode'.") | |
f8b4fcda | 86 | ;; (makunbound 'mixal-mode-map) |
0a2d0bd4 JB |
87 | |
88 | ;;; Syntax table | |
89 | (defvar mixal-mode-syntax-table | |
90 | (let ((st (make-syntax-table))) | |
0471d426 | 91 | ;; We need to do a bit more to make fontlocking for comments work. |
cf38dd42 | 92 | ;; See use of syntax-propertize-function. |
0471d426 SM |
93 | ;; (modify-syntax-entry ?* "<" st) |
94 | (modify-syntax-entry ?\n ">" st) | |
0a2d0bd4 | 95 | st) |
0471d426 | 96 | "Syntax table for `mixal-mode'.") |
0a2d0bd4 JB |
97 | |
98 | (defvar mixal-font-lock-label-face 'font-lock-variable-name-face | |
99 | "Face name to use for label names. | |
100 | Default value is that of `font-lock-variable-name-face', but you can modify | |
101 | its value.") | |
102 | ||
103 | (defvar mixal-font-lock-operation-code-face 'font-lock-keyword-face | |
104 | "Face name to use for operation code names. | |
105 | Default value is that of `font-lock-keyword-face', but you can modify its | |
106 | value.") | |
107 | ||
108 | (defvar mixal-font-lock-assembly-pseudoinstruction-face 'font-lock-builtin-face | |
109 | "Face name to use for assembly pseudoinstruction names. | |
110 | Default value is that of `font-lock-builtin-face', but you can modify its | |
111 | value.") | |
112 | ||
0a2d0bd4 JB |
113 | (defvar mixal-assembly-pseudoinstructions |
114 | '("ORIG" "EQU" "CON" "ALF" "END") | |
f8b4fcda | 115 | "List of possible assembly pseudoinstructions.") |
0a2d0bd4 | 116 | |
0a2d0bd4 JB |
117 | ;;;; Compilation |
118 | ;; Output from mixasm is compatible with default behavior of emacs, | |
119 | ;; I just added a key (C-cc) and modified the make-command. | |
120 | ||
121 | ;;;; Indentation | |
122 | ;; Tabs works well by default. | |
123 | ||
124 | ;;;; Describe | |
0471d426 SM |
125 | (defvar mixal-operation-codes-alist |
126 | ;; FIXME: the codes FADD, FSUB, FMUL, FDIV, JRAD, and FCMP were in | |
127 | ;; mixal-operation-codes but not here. They should probably be added here. | |
5e339ee2 | 128 | ;; |
8511877a SM |
129 | ;; We used to define this with a backquote and subexps like ,(+ 8 3) for |
130 | ;; better clarity, but the resulting code was too big and caused the | |
131 | ;; byte-compiler to eat up all the stack space. Even using | |
132 | ;; `eval-when-compile' didn't help because the byte-compiler insists on | |
133 | ;; compiling the code before evaluating it. | |
134 | '((LDA loading "load A" 8 field | |
135 | "Put in rA the contents of cell no. M. | |
0a2d0bd4 JB |
136 | Uses a + when there is no sign in subfield. Subfield is left padded with |
137 | zeros to make a word." | |
8511877a | 138 | 2) |
0a2d0bd4 | 139 | |
8511877a SM |
140 | (LDX loading "load X" 15 field |
141 | "Put in rX the contents of cell no. M. | |
0a2d0bd4 JB |
142 | Uses a + when there is no sign in subfield. Subfield is left padded with |
143 | zeros to make a word." | |
8511877a | 144 | 2) |
0a2d0bd4 | 145 | |
8511877a SM |
146 | (LD1 loading "load I1" 9 field |
147 | "Put in rI1 the contents of cell no. M. | |
0a2d0bd4 JB |
148 | Uses a + when there is no sign in subfield. Subfield is left padded with |
149 | zeros to make a word. Index registers only have 2 bytes and a sign, Trying | |
150 | to set anything more that that will result in undefined behavior." | |
8511877a | 151 | 2) |
0a2d0bd4 | 152 | |
8511877a SM |
153 | (LD2 loading "load I2" 10 field |
154 | "Put in rI2 the contents of cell no. M. | |
0a2d0bd4 JB |
155 | Uses a + when there is no sign in subfield. Subfield is left padded with |
156 | zeros to make a word. Index registers only have 2 bytes and a sign, Trying | |
157 | to set anything more that that will result in undefined behavior." | |
8511877a | 158 | 2) |
0a2d0bd4 | 159 | |
8511877a SM |
160 | (LD3 loading "load I3" 11 field |
161 | "Put in rI3 the contents of cell no. M. | |
0a2d0bd4 JB |
162 | Uses a + when there is no sign in subfield. Subfield is left padded with |
163 | zeros to make a word. Index registers only have 2 bytes and a sign, Trying | |
164 | to set anything more that that will result in undefined behavior." | |
8511877a | 165 | 2) |
0a2d0bd4 | 166 | |
8511877a SM |
167 | (LD4 loading "load I4" 12 field |
168 | "Put in rI4 the contents of cell no. M. | |
0a2d0bd4 JB |
169 | Uses a + when there is no sign in subfield. Subfield is left padded with |
170 | zeros to make a word. Index registers only have 2 bytes and a sign, Trying | |
171 | to set anything more that that will result in undefined behavior." | |
8511877a | 172 | 2) |
0a2d0bd4 | 173 | |
8511877a SM |
174 | (LD5 loading "load I5" 13 field |
175 | "Put in rI5 the contents of cell no. M. | |
0a2d0bd4 JB |
176 | Uses a + when there is no sign in subfield. Subfield is left padded with |
177 | zeros to make a word. Index registers only have 2 bytes and a sign, Trying | |
178 | to set anything more that that will result in undefined behavior." | |
8511877a | 179 | 2) |
0a2d0bd4 | 180 | |
8511877a SM |
181 | (LD6 loading "load I6" 14 field |
182 | "Put in rI6 the contents of cell no. M. | |
0a2d0bd4 JB |
183 | Uses a + when there is no sign in subfield. Subfield is left padded with |
184 | zeros to make a word. Index registers only have 2 bytes and a sign, Trying | |
185 | to set anything more that that will result in undefined behavior." | |
8511877a | 186 | 2) |
0a2d0bd4 | 187 | |
8511877a SM |
188 | (LDAN loading "load A negative" 16 field |
189 | "Put in rA the contents of cell no. M, with opposite sign. | |
0a2d0bd4 JB |
190 | Uses a + when there is no sign in subfield, otherwise use the opposite sign. |
191 | Subfield is left padded with zeros to make a word." | |
8511877a | 192 | 2) |
0a2d0bd4 | 193 | |
8511877a SM |
194 | (LDXN loading "load X negative" 23 field |
195 | "Put in rX the contents of cell no. M, with opposite sign. | |
0a2d0bd4 JB |
196 | Uses a + when there is no sign in subfield, otherwise use the opposite sign. |
197 | Subfield is left padded with zeros to make a word." | |
8511877a | 198 | 2) |
0a2d0bd4 | 199 | |
8511877a SM |
200 | (LD1N loading "load I1 negative" 17 field |
201 | "Put in rI1 the contents of cell no. M, with opposite sign. | |
0a2d0bd4 JB |
202 | Uses a + when there is no sign in subfield, otherwise use the opposite sign. |
203 | Subfield is left padded with zeros to make a word. Index registers only | |
204 | have 2 bytes and a sign, Trying to set anything more that that will result | |
205 | in undefined behavior." | |
8511877a | 206 | 2) |
0a2d0bd4 | 207 | |
8511877a SM |
208 | (LD2N loading "load I2 negative" 18 field |
209 | "Put in rI2 the contents of cell no. M, with opposite sign. | |
0a2d0bd4 JB |
210 | Uses a + when there is no sign in subfield, otherwise use the opposite sign. |
211 | Subfield is left padded with zeros to make a word. Index registers only | |
212 | have 2 bytes and a sign, Trying to set anything more that that will result | |
213 | in undefined behavior." | |
8511877a | 214 | 2) |
0a2d0bd4 | 215 | |
8511877a SM |
216 | (LD3N loading "load I3 negative" 19 field |
217 | "Put in rI3 the contents of cell no. M, with opposite sign. | |
0a2d0bd4 JB |
218 | Uses a + when there is no sign in subfield, otherwise use the opposite sign. |
219 | Subfield is left padded with zeros to make a word. Index registers only | |
220 | have 2 bytes and a sign, Trying to set anything more that that will result | |
221 | in undefined behavior." | |
8511877a | 222 | 2) |
0a2d0bd4 | 223 | |
8511877a SM |
224 | (LD4N loading "load I4 negative" 20 field |
225 | "Put in rI4 the contents of cell no. M, with opposite sign. | |
0a2d0bd4 JB |
226 | Uses a + when there is no sign in subfield, otherwise use the opposite sign. |
227 | Subfield is left padded with zeros to make a word. Index registers only | |
228 | have 2 bytes and a sign, Trying to set anything more that that will result | |
229 | in undefined behavior." | |
8511877a | 230 | 2) |
0a2d0bd4 | 231 | |
8511877a SM |
232 | (LD5N loading "load I5 negative" 21 field |
233 | "Put in rI5 the contents of cell no. M, with opposite sign. | |
0a2d0bd4 JB |
234 | Uses a + when there is no sign in subfield, otherwise use the opposite sign. |
235 | Subfield is left padded with zeros to make a word. Index registers only | |
236 | have 2 bytes and a sign, Trying to set anything more that that will result | |
237 | in undefined behavior." | |
8511877a | 238 | 2) |
0a2d0bd4 | 239 | |
8511877a SM |
240 | (LD6N loading "load I6 negative" 22 field |
241 | "Put in rI6 the contents of cell no. M, with opposite sign. | |
0a2d0bd4 JB |
242 | Uses a + when there is no sign in subfield, otherwise use the opposite sign. |
243 | Subfield is left padded with zeros to make a word. Index registers only | |
244 | have 2 bytes and a sign, Trying to set anything more that that will result | |
245 | in undefined behavior." | |
8511877a | 246 | 2) |
0a2d0bd4 | 247 | |
8511877a SM |
248 | (STA storing "store A" 24 field |
249 | "Store in cell Nr. M the contents of rA. | |
0a2d0bd4 JB |
250 | The modification of the operation code represents the subfield of the |
251 | memory cell that is to be overwritten with bytes from a register. These | |
252 | bytes are taken beginning by the rightmost side of the register. The | |
253 | sign of the memory cell is not changed, unless it is part of the subfield." | |
8511877a | 254 | 2) |
0a2d0bd4 | 255 | |
8511877a SM |
256 | (STX storing "store X" 31 field |
257 | "Store in cell Nr. M the contents of rX. | |
0a2d0bd4 JB |
258 | The modification of the operation code represents the subfield of the |
259 | memory cell that is to be overwritten with bytes from a register. These | |
260 | bytes are taken beginning by the rightmost side of the register. The | |
261 | sign of the memory cell is not changed, unless it is part of the subfield." | |
8511877a | 262 | 2) |
0a2d0bd4 | 263 | |
8511877a SM |
264 | (ST1 storing "store I1" 25 field |
265 | "Store in cell Nr. M the contents of rI1. | |
0a2d0bd4 JB |
266 | The modification of the operation code represents the subfield of the |
267 | memory cell that is to be overwritten with bytes from a register. These | |
268 | bytes are taken beginning by the rightmost side of the register. The | |
269 | sign of the memory cell is not changed, unless it is part of the subfield. | |
270 | Because index registers only have 2 bytes and a sign, the rest of the bytes | |
271 | are assumed to be 0." | |
8511877a | 272 | 2) |
0a2d0bd4 | 273 | |
8511877a SM |
274 | (ST2 storing "store I2" 26 field |
275 | "Store in cell Nr. M the contents of rI2. | |
0a2d0bd4 JB |
276 | The modification of the operation code represents the subfield of the |
277 | memory cell that is to be overwritten with bytes from a register. These | |
278 | bytes are taken beginning by the rightmost side of the register. The | |
279 | sign of the memory cell is not changed, unless it is part of the subfield. | |
280 | Because index registers only have 2 bytes and a sign, the rest of the bytes | |
281 | are assumed to be 0." | |
8511877a | 282 | 2) |
0a2d0bd4 | 283 | |
8511877a SM |
284 | (ST3 storing "store I3" 27 field |
285 | "Store in cell Nr. M the contents of rI3. | |
0a2d0bd4 JB |
286 | The modification of the operation code represents the subfield of the |
287 | memory cell that is to be overwritten with bytes from a register. These | |
288 | bytes are taken beginning by the rightmost side of the register. The | |
289 | sign of the memory cell is not changed, unless it is part of the subfield. | |
290 | Because index registers only have 2 bytes and a sign, the rest of the bytes | |
291 | are assumed to be 0." | |
8511877a | 292 | 2) |
0a2d0bd4 | 293 | |
8511877a SM |
294 | (ST4 storing "store I4" 28 field |
295 | "Store in cell Nr. M the contents of rI4. | |
0a2d0bd4 JB |
296 | The modification of the operation code represents the subfield of the |
297 | memory cell that is to be overwritten with bytes from a register. These | |
298 | bytes are taken beginning by the rightmost side of the register. The | |
299 | sign of the memory cell is not changed, unless it is part of the subfield. | |
300 | Because index registers only have 2 bytes and a sign, the rest of the bytes | |
301 | are assumed to be 0." | |
8511877a | 302 | 2) |
0a2d0bd4 | 303 | |
8511877a SM |
304 | (ST5 storing "store I5" 29 field |
305 | "Store in cell Nr. M the contents of rI5. | |
0a2d0bd4 JB |
306 | The modification of the operation code represents the subfield of the |
307 | memory cell that is to be overwritten with bytes from a register. These | |
308 | bytes are taken beginning by the rightmost side of the register. The | |
309 | sign of the memory cell is not changed, unless it is part of the subfield. | |
310 | Because index registers only have 2 bytes and a sign, the rest of the bytes | |
311 | are assumed to be 0." | |
8511877a | 312 | 2) |
0a2d0bd4 | 313 | |
8511877a SM |
314 | (ST6 storing "store I6" 30 field |
315 | "Store in cell Nr. M the contents of rI6. | |
0a2d0bd4 JB |
316 | The modification of the operation code represents the subfield of the |
317 | memory cell that is to be overwritten with bytes from a register. These | |
318 | bytes are taken beginning by the rightmost side of the register. The | |
319 | sign of the memory cell is not changed, unless it is part of the subfield. | |
320 | Because index registers only have 2 bytes and a sign, the rest of the bytes | |
321 | are assumed to be 0." | |
8511877a | 322 | 2) |
0a2d0bd4 | 323 | |
8511877a SM |
324 | (STJ storing "store J" 32 field |
325 | "Store in cell Nr. M the contents of rJ. | |
0a2d0bd4 JB |
326 | The modification of the operation code represents the subfield of the |
327 | memory cell that is to be overwritten with bytes from a register. These | |
328 | bytes are taken beginning by the rightmost side of the register. The sign | |
329 | of rJ is always +, sign of the memory cell is not changed, unless it is | |
330 | part of the subfield. The default field for STJ is (0:2)." | |
8511877a | 331 | 2) |
0a2d0bd4 | 332 | |
8511877a SM |
333 | (STZ storing "store zero" 33 field |
334 | "Store in cell Nr. M '+ 0'. | |
0a2d0bd4 JB |
335 | The modification of the operation code represents the subfield of the |
336 | memory cell that is to be overwritten with zeros." | |
8511877a | 337 | 2) |
0a2d0bd4 | 338 | |
8511877a SM |
339 | (ADD arithmetic "add" 1 field |
340 | "Add to A the contents of cell Nr. M. | |
0a2d0bd4 JB |
341 | Subfield is padded with zero to make a word. |
342 | If the result is to large, the operation result modulo 1,073,741,823 (the | |
343 | maximum value storable in a MIX word) is stored in `rA', and the overflow | |
344 | toggle is set to TRUE." | |
8511877a | 345 | 2) |
0a2d0bd4 | 346 | |
8511877a SM |
347 | (SUB arithmetic "subtract" 2 field |
348 | "Subtract to A the contents of cell Nr. M. | |
0a2d0bd4 JB |
349 | Subfield is padded with zero to make a word. |
350 | If the result is to large, the operation result modulo 1,073,741,823 (the | |
351 | maximum value storable in a MIX word) is stored in `rA', and the overflow | |
352 | toggle is set to TRUE." | |
8511877a | 353 | 2) |
0a2d0bd4 | 354 | |
8511877a SM |
355 | (MUL arithmetic "multiply" 3 field |
356 | "Multiplies the contents of cell Nr. M with A, result is 10 bytes and stored in rA and rX. | |
0a2d0bd4 | 357 | The sign is + if the sign of rA and cell M where the same, otherwise, it is -" |
8511877a | 358 | 10) |
0a2d0bd4 | 359 | |
8511877a SM |
360 | (DIV arithmetic "divide" 4 field |
361 | "Both rA and rX are taken together and divided by cell Nr. M, quotient is placed in rA, remainder in rX. | |
0a2d0bd4 | 362 | The sign is taken from rA, and after the divide the sign of rA is set to + when |
0471d426 SM |
363 | both the sign of rA and M where the same. Divide by zero and overflow of rA |
364 | result in undefined behavior." | |
8511877a | 365 | 12) |
0a2d0bd4 | 366 | |
8511877a SM |
367 | (ENTA address-transfer "enter A" 48 |
368 | "Literal value is stored in rA. | |
0a2d0bd4 | 369 | Indexed, stores value of index in rA." |
8511877a | 370 | 1) |
0a2d0bd4 | 371 | |
8511877a SM |
372 | (ENTX address-transfer "enter X" 55 |
373 | "Literal value is stored in rX. | |
0a2d0bd4 | 374 | Indexed, stores value of index in rX." |
8511877a | 375 | 1) |
0a2d0bd4 | 376 | |
8511877a SM |
377 | (ENT1 address-transfer "Enter rI1" 49 |
378 | "Literal value is stored in rI1. | |
0a2d0bd4 | 379 | Indexed, stores value of index in rI1." |
8511877a | 380 | 1) |
0a2d0bd4 | 381 | |
8511877a SM |
382 | (ENT2 address-transfer "Enter rI2" 50 |
383 | "Literal value is stored in rI2. | |
0a2d0bd4 | 384 | Indexed, stores value of index in rI2." |
8511877a | 385 | 1) |
0a2d0bd4 | 386 | |
8511877a SM |
387 | (ENT3 address-transfer "Enter rI3" 51 |
388 | "Literal value is stored in rI3. | |
0a2d0bd4 | 389 | Indexed, stores value of index in rI3." |
8511877a | 390 | 1) |
0a2d0bd4 | 391 | |
8511877a SM |
392 | (ENT4 address-transfer "Enter rI4" 52 |
393 | "Literal value is stored in rI4. | |
0a2d0bd4 | 394 | Indexed, stores value of index in rI4." |
8511877a | 395 | 1) |
0a2d0bd4 | 396 | |
8511877a SM |
397 | (ENT5 address-transfer "Enter rI5" 53 |
398 | "Literal value is stored in rI5. | |
0a2d0bd4 | 399 | Indexed, stores value of index in rI5." |
8511877a | 400 | 1) |
0a2d0bd4 | 401 | |
8511877a SM |
402 | (ENT6 address-transfer "Enter rI6" 54 |
403 | "Literal value is stored in rI6. | |
0a2d0bd4 | 404 | Indexed, stores value of index in rI6." |
8511877a | 405 | 1) |
0a2d0bd4 | 406 | |
8511877a SM |
407 | (ENNA address-transfer "enter negative A" 48 |
408 | "Literal value is stored in rA with opposite sign. | |
0a2d0bd4 | 409 | Indexed, stores value of index in rA with opposite sign." |
8511877a | 410 | 1) |
0a2d0bd4 | 411 | |
8511877a SM |
412 | (ENNX address-transfer "enter negative X" 55 |
413 | "Literal value is stored in rX with opposite sign. | |
0a2d0bd4 | 414 | Indexed, stores value of index in rX with opposite sign." |
8511877a | 415 | 1) |
0a2d0bd4 | 416 | |
8511877a SM |
417 | (ENN1 address-transfer "Enter negative rI1" 49 |
418 | "Literal value is stored in rI1 with opposite sign. | |
0a2d0bd4 | 419 | Indexed, stores value of index in rI1 with opposite sign." |
8511877a | 420 | 1) |
0a2d0bd4 | 421 | |
8511877a SM |
422 | (ENN2 address-transfer "Enter negative rI2" 50 |
423 | "Literal value is stored in rI2 with opposite sign. | |
0a2d0bd4 | 424 | Indexed, stores value of index in rI2 with opposite sign." |
8511877a | 425 | 1) |
0a2d0bd4 | 426 | |
8511877a SM |
427 | (ENN3 address-transfer "Enter negative rI3" 51 |
428 | "Literal value is stored in rI3 with opposite sign. | |
0a2d0bd4 | 429 | Indexed, stores value of index in rI3 with opposite sign." |
8511877a | 430 | 1) |
0a2d0bd4 | 431 | |
8511877a SM |
432 | (ENN4 address-transfer "Enter negative rI4" 52 |
433 | "Literal value is stored in rI4 with opposite sign. | |
0a2d0bd4 | 434 | Indexed, stores value of index in rI4 with opposite sign." |
8511877a | 435 | 1) |
0a2d0bd4 | 436 | |
8511877a SM |
437 | (ENN5 address-transfer "Enter negative rI5" 53 |
438 | "Literal value is stored in rI5 with opposite sign. | |
0a2d0bd4 | 439 | Indexed, stores value of index in rI5 with opposite sign." |
8511877a | 440 | 1) |
0a2d0bd4 | 441 | |
8511877a SM |
442 | (ENN6 address-transfer "Enter negative rI6" 54 |
443 | "Literal value is stored in rI6 with opposite sign. | |
0a2d0bd4 | 444 | Indexed, stores value of index in rI6 with opposite sign." |
8511877a | 445 | 1) |
0a2d0bd4 | 446 | |
8511877a SM |
447 | (INCA address-transfer "increase A" 48 |
448 | "Increase register A with the literal value of M. | |
0a2d0bd4 | 449 | On overflow the overflow toggle is set." |
8511877a | 450 | 1) |
0a2d0bd4 | 451 | |
8511877a SM |
452 | (INCX address-transfer "increase X" 55 |
453 | "Increase register X with the literal value of M. | |
0a2d0bd4 | 454 | On overflow the overflow toggle is set." |
8511877a | 455 | 1) |
0a2d0bd4 | 456 | |
8511877a SM |
457 | (INC1 address-transfer "increase I1" 49 |
458 | "Increase register I1 with the literal value of M. | |
0a2d0bd4 JB |
459 | The result is undefined when the result does not fit in |
460 | 2 bytes." | |
8511877a | 461 | 1) |
0a2d0bd4 | 462 | |
8511877a SM |
463 | (INC2 address-transfer "increase I2" 50 |
464 | "Increase register I2 with the literal value of M. | |
0a2d0bd4 JB |
465 | The result is undefined when the result does not fit in |
466 | 2 bytes." | |
8511877a | 467 | 1) |
0a2d0bd4 | 468 | |
8511877a SM |
469 | (INC3 address-transfer "increase I3" 51 |
470 | "Increase register I3 with the literal value of M. | |
0a2d0bd4 JB |
471 | The result is undefined when the result does not fit in |
472 | 2 bytes." | |
8511877a | 473 | 1) |
0a2d0bd4 | 474 | |
8511877a SM |
475 | (INC4 address-transfer "increase I4" 52 |
476 | "Increase register I4 with the literal value of M. | |
0a2d0bd4 JB |
477 | The result is undefined when the result does not fit in |
478 | 2 bytes." | |
8511877a | 479 | 1) |
0a2d0bd4 | 480 | |
8511877a SM |
481 | (INC5 address-transfer "increase I5" 53 |
482 | "Increase register I5 with the literal value of M. | |
0a2d0bd4 JB |
483 | The result is undefined when the result does not fit in |
484 | 2 bytes." | |
8511877a | 485 | 1) |
0a2d0bd4 | 486 | |
8511877a SM |
487 | (INC6 address-transfer "increase I6" 54 |
488 | "Increase register I6 with the literal value of M. | |
0a2d0bd4 JB |
489 | The result is undefined when the result does not fit in |
490 | 2 bytes." | |
8511877a | 491 | 1) |
0a2d0bd4 | 492 | |
8511877a SM |
493 | (DECA address-transfer "decrease A" 48 |
494 | "Decrease register A with the literal value of M. | |
0a2d0bd4 | 495 | On overflow the overflow toggle is set." |
8511877a | 496 | 1) |
0a2d0bd4 | 497 | |
8511877a SM |
498 | (DECX address-transfer "decrease X" 55 |
499 | "Decrease register X with the literal value of M. | |
0a2d0bd4 | 500 | On overflow the overflow toggle is set." |
8511877a | 501 | 1) |
0a2d0bd4 | 502 | |
8511877a SM |
503 | (DEC1 address-transfer "decrease I1" 49 |
504 | "Decrease register I1 with the literal value of M. | |
0a2d0bd4 JB |
505 | The result is undefined when the result does not fit in |
506 | 2 bytes." | |
8511877a | 507 | 1) |
0a2d0bd4 | 508 | |
8511877a SM |
509 | (DEC2 address-transfer "decrease I2" 50 |
510 | "Decrease register I2 with the literal value of M. | |
0a2d0bd4 JB |
511 | The result is undefined when the result does not fit in |
512 | 2 bytes." | |
8511877a | 513 | 1) |
0a2d0bd4 | 514 | |
8511877a SM |
515 | (DEC3 address-transfer "decrease I3" 51 |
516 | "Decrease register I3 with the literal value of M. | |
0a2d0bd4 JB |
517 | The result is undefined when the result does not fit in |
518 | 2 bytes." | |
8511877a | 519 | 1) |
0a2d0bd4 | 520 | |
8511877a SM |
521 | (DEC4 address-transfer "decrease I4" 52 |
522 | "Decrease register I4 with the literal value of M. | |
0a2d0bd4 JB |
523 | The result is undefined when the result does not fit in |
524 | 2 bytes." | |
8511877a | 525 | 1) |
0a2d0bd4 | 526 | |
8511877a SM |
527 | (DEC5 address-transfer "decrease I5" 53 |
528 | "Decrease register I5 with the literal value of M. | |
0a2d0bd4 JB |
529 | The result is undefined when the result does not fit in |
530 | 2 bytes." | |
8511877a | 531 | 1) |
0a2d0bd4 | 532 | |
8511877a SM |
533 | (DEC6 address-transfer "decrease I6" 54 |
534 | "Decrease register I6 with the literal value of M. | |
0a2d0bd4 JB |
535 | The result is undefined when the result does not fit in |
536 | 2 bytes." | |
8511877a | 537 | 1) |
0a2d0bd4 | 538 | |
8511877a SM |
539 | (CMPA comparison "compare A" 56 field |
540 | "Compare contents of A with contents of M. | |
0a2d0bd4 JB |
541 | The field specifier works on both fields. The comparison indicator |
542 | is set to LESS, EQUAL or GREATER depending on the outcome." | |
8511877a | 543 | 2) |
0a2d0bd4 | 544 | |
8511877a SM |
545 | (CMPX comparison "compare X" 63 field |
546 | "Compare contents of rX with contents of M. | |
0a2d0bd4 JB |
547 | The field specifier works on both fields. The comparison indicator |
548 | is set to LESS, EQUAL or GREATER depending on the outcome." | |
8511877a | 549 | 2) |
0a2d0bd4 | 550 | |
8511877a SM |
551 | (CMP1 comparison "compare I1" 57 field |
552 | "Compare contents of rI1 with contents of M. | |
0a2d0bd4 JB |
553 | The field specifier works on both fields. The comparison indicator |
554 | is set to LESS, EQUAL or GREATER depending on the outcome. Bit 1,2 and 3 | |
555 | have a value of 0." | |
8511877a | 556 | 2) |
0a2d0bd4 | 557 | |
8511877a SM |
558 | (CMP2 comparison "compare I2" 58 field |
559 | "Compare contents of rI2 with contents of M. | |
0a2d0bd4 JB |
560 | The field specifier works on both fields. The comparison indicator |
561 | is set to LESS, EQUAL or GREATER depending on the outcome. Bit 1,2 and 3 | |
562 | have a value of 0." | |
8511877a | 563 | 2) |
0a2d0bd4 | 564 | |
8511877a SM |
565 | (CMP3 comparison "compare I3" 59 field |
566 | "Compare contents of rI3 with contents of M. | |
0a2d0bd4 JB |
567 | The field specifier works on both fields. The comparison indicator |
568 | is set to LESS, EQUAL or GREATER depending on the outcome. Bit 1,2 and 3 | |
569 | have a value of 0." | |
8511877a | 570 | 2) |
0a2d0bd4 | 571 | |
8511877a SM |
572 | (CMP4 comparison "compare I4" 60 field |
573 | "Compare contents of rI4 with contents of M. | |
0a2d0bd4 JB |
574 | The field specifier works on both fields. The comparison indicator |
575 | is set to LESS, EQUAL or GREATER depending on the outcome. Bit 1,2 and 3 | |
576 | have a value of 0." | |
8511877a | 577 | 2) |
0a2d0bd4 | 578 | |
8511877a SM |
579 | (CMP5 comparison "compare I5" 61 field |
580 | "Compare contents of rI5 with contents of M. | |
0a2d0bd4 JB |
581 | The field specifier works on both fields. The comparison indicator |
582 | is set to LESS, EQUAL or GREATER depending on the outcome. Bit 1,2 and 3 | |
583 | have a value of 0." | |
8511877a | 584 | 2) |
0a2d0bd4 | 585 | |
8511877a SM |
586 | (CMP6 comparison "compare I6" 62 field |
587 | "Compare contents of rI6 with contents of M. | |
0a2d0bd4 JB |
588 | The field specifier works on both fields. The comparison indicator |
589 | is set to LESS, EQUAL or GREATER depending on the outcome. Bit 1,2 and 3 | |
590 | have a value of 0." | |
8511877a | 591 | 2) |
0a2d0bd4 | 592 | |
8511877a SM |
593 | (JMP jump "jump" 39 |
594 | "Unconditional jump. | |
0a2d0bd4 JB |
595 | Register J is set to the value of the next instruction that would have |
596 | been executed when there was no jump." | |
8511877a | 597 | 1) |
0a2d0bd4 | 598 | |
8511877a SM |
599 | (JSJ jump "jump, save J" 39 |
600 | "Unconditional jump, but rJ is not modified." | |
601 | 1) | |
0a2d0bd4 | 602 | |
8511877a SM |
603 | (JOV jump "jump on overflow" 39 |
604 | "Jump if OV is set (and turn it off). | |
0a2d0bd4 JB |
605 | Register J is set to the value of the next instruction that would have |
606 | been executed when there was no jump." | |
8511877a | 607 | 1) |
0a2d0bd4 | 608 | |
8511877a SM |
609 | (JNOV jump "Jump on no overflow" 39 |
610 | "Jump if OV is not set (and turn it off). | |
0a2d0bd4 JB |
611 | Register J is set to the value of the next instruction that would have |
612 | been executed when there was no jump." | |
8511877a | 613 | 1) |
0a2d0bd4 | 614 | |
8511877a SM |
615 | (JL jump "Jump on less" 39 |
616 | "Jump if '[CM] = L'. | |
0a2d0bd4 JB |
617 | Register J is set to the value of the next instruction that would have |
618 | been executed when there was no jump." | |
8511877a | 619 | 1) |
0a2d0bd4 | 620 | |
8511877a SM |
621 | (JE jump "Jump on equal" 39 |
622 | "Jump if '[CM] = E'. | |
0a2d0bd4 JB |
623 | Register J is set to the value of the next instruction that would have |
624 | been executed when there was no jump." | |
8511877a | 625 | 1) |
0a2d0bd4 | 626 | |
8511877a SM |
627 | (JG jump "Jump on greater" 39 |
628 | "Jump if '[CM] = G'. | |
0a2d0bd4 JB |
629 | Register J is set to the value of the next instruction that would have |
630 | been executed when there was no jump." | |
8511877a | 631 | 1) |
0a2d0bd4 | 632 | |
8511877a SM |
633 | (JGE jump "Jump on not less" 39 |
634 | "Jump if '[CM]' does not equal 'L'. | |
0a2d0bd4 JB |
635 | Register J is set to the value of the next instruction that would have |
636 | been executed when there was no jump." | |
8511877a | 637 | 1) |
0a2d0bd4 | 638 | |
8511877a SM |
639 | (JNE jump "Jump on not equal" 39 |
640 | "Jump if '[CM]' does not equal 'E'. | |
0a2d0bd4 JB |
641 | Register J is set to the value of the next instruction that would have |
642 | been executed when there was no jump." | |
8511877a | 643 | 1) |
0a2d0bd4 | 644 | |
8511877a SM |
645 | (JLE jump "Jump on not greater" 39 |
646 | "Jump if '[CM]' does not equal 'G'. | |
0a2d0bd4 JB |
647 | Register J is set to the value of the next instruction that would have |
648 | been executed when there was no jump." | |
8511877a | 649 | 1) |
0a2d0bd4 | 650 | |
8511877a SM |
651 | (JAN jump "jump A negative" 40 |
652 | "Jump if the content of rA is negative. | |
0a2d0bd4 JB |
653 | Register J is set to the value of the next instruction that would have |
654 | been executed when there was no jump." | |
8511877a | 655 | 1) |
0a2d0bd4 | 656 | |
8511877a SM |
657 | (JAZ jump "jump A zero" 40 |
658 | "Jump if the content of rA is zero. | |
0a2d0bd4 JB |
659 | Register J is set to the value of the next instruction that would have |
660 | been executed when there was no jump." | |
8511877a | 661 | 1) |
0a2d0bd4 | 662 | |
8511877a SM |
663 | (JAP jump "jump A positive" 40 |
664 | "Jump if the content of rA is positive. | |
0a2d0bd4 JB |
665 | Register J is set to the value of the next instruction that would have |
666 | been executed when there was no jump." | |
8511877a | 667 | 1) |
0a2d0bd4 | 668 | |
8511877a SM |
669 | (JANN jump "jump A non-negative" 40 |
670 | "Jump if the content of rA is non-negative. | |
0a2d0bd4 JB |
671 | Register J is set to the value of the next instruction that would have |
672 | been executed when there was no jump." | |
8511877a | 673 | 1) |
0a2d0bd4 | 674 | |
8511877a SM |
675 | (JANZ jump "jump A non-zero" 40 |
676 | "Jump if the content of rA is non-zero. | |
0a2d0bd4 JB |
677 | Register J is set to the value of the next instruction that would have |
678 | been executed when there was no jump." | |
8511877a | 679 | 1) |
0a2d0bd4 | 680 | |
8511877a SM |
681 | (JANP jump "jump A non-positive" 40 |
682 | "Jump if the content of rA is non-positive. | |
0a2d0bd4 JB |
683 | Register J is set to the value of the next instruction that would have |
684 | been executed when there was no jump." | |
8511877a | 685 | 1) |
0a2d0bd4 | 686 | |
8511877a SM |
687 | (JXN jump "jump X negative" 47 |
688 | "Jump if the content of rX is negative. | |
0a2d0bd4 JB |
689 | Register J is set to the value of the next instruction that would have |
690 | been executed when there was no jump." | |
8511877a | 691 | 1) |
0a2d0bd4 | 692 | |
8511877a SM |
693 | (JXZ jump "jump X zero" 47 |
694 | "Jump if the content of rX is zero. | |
0a2d0bd4 JB |
695 | Register J is set to the value of the next instruction that would have |
696 | been executed when there was no jump." | |
8511877a | 697 | 1) |
0a2d0bd4 | 698 | |
8511877a SM |
699 | (JXP jump "jump X positive" 47 |
700 | "Jump if the content of rX is positive. | |
0a2d0bd4 JB |
701 | Register J is set to the value of the next instruction that would have |
702 | been executed when there was no jump." | |
8511877a | 703 | 1) |
0a2d0bd4 | 704 | |
8511877a SM |
705 | (JXNN jump "jump X non-negative" 47 |
706 | "Jump if the content of rX is non-negative. | |
0a2d0bd4 JB |
707 | Register J is set to the value of the next instruction that would have |
708 | been executed when there was no jump." | |
8511877a | 709 | 1) |
0a2d0bd4 | 710 | |
8511877a SM |
711 | (JXNZ jump "jump X non-zero" 47 |
712 | "Jump if the content of rX is non-zero. | |
0a2d0bd4 JB |
713 | Register J is set to the value of the next instruction that would have |
714 | been executed when there was no jump." | |
8511877a | 715 | 1) |
0a2d0bd4 | 716 | |
8511877a SM |
717 | (JXNP jump "jump X non-positive" 47 |
718 | "Jump if the content of rX is non-positive. | |
0a2d0bd4 JB |
719 | Register J is set to the value of the next instruction that would have |
720 | been executed when there was no jump." | |
8511877a | 721 | 1) |
0a2d0bd4 | 722 | |
8511877a SM |
723 | (J1N jump "jump I1 negative" 41 |
724 | "Jump if the content of rI1 is negative. | |
0a2d0bd4 JB |
725 | Register J is set to the value of the next instruction that would have |
726 | been executed when there was no jump." | |
8511877a | 727 | 1) |
0a2d0bd4 | 728 | |
8511877a SM |
729 | (J1Z jump "jump I1 zero" 41 |
730 | "Jump if the content of rI1 is zero. | |
0a2d0bd4 JB |
731 | Register J is set to the value of the next instruction that would have |
732 | been executed when there was no jump." | |
8511877a | 733 | 1) |
0a2d0bd4 | 734 | |
8511877a SM |
735 | (J1P jump "jump I1 positive" 41 |
736 | "Jump if the content of rI1 is positive. | |
0a2d0bd4 JB |
737 | Register J is set to the value of the next instruction that would have |
738 | been executed when there was no jump." | |
8511877a | 739 | 1) |
0a2d0bd4 | 740 | |
8511877a SM |
741 | (J1NN jump "jump I1 non-negative" 41 |
742 | "Jump if the content of rI1 is non-negative. | |
0a2d0bd4 JB |
743 | Register J is set to the value of the next instruction that would have |
744 | been executed when there was no jump." | |
8511877a | 745 | 1) |
0a2d0bd4 | 746 | |
8511877a SM |
747 | (J1NZ jump "jump I1 non-zero" 41 |
748 | "Jump if the content of rI1 is non-zero. | |
0a2d0bd4 JB |
749 | Register J is set to the value of the next instruction that would have |
750 | been executed when there was no jump." | |
8511877a | 751 | 1) |
0a2d0bd4 | 752 | |
8511877a SM |
753 | (J1NP jump "jump I1 non-positive" 41 |
754 | "Jump if the content of rI1 is non-positive. | |
0a2d0bd4 JB |
755 | Register J is set to the value of the next instruction that would have |
756 | been executed when there was no jump." | |
8511877a | 757 | 1) |
0a2d0bd4 | 758 | |
8511877a SM |
759 | (J2N jump "jump I2 negative" 41 |
760 | "Jump if the content of rI2 is negative. | |
0a2d0bd4 JB |
761 | Register J is set to the value of the next instruction that would have |
762 | been executed when there was no jump." | |
8511877a | 763 | 1) |
0a2d0bd4 | 764 | |
8511877a SM |
765 | (J2Z jump "jump I2 zero" 41 |
766 | "Jump if the content of rI2 is zero. | |
0a2d0bd4 JB |
767 | Register J is set to the value of the next instruction that would have |
768 | been executed when there was no jump." | |
8511877a | 769 | 1) |
0a2d0bd4 | 770 | |
8511877a SM |
771 | (J2P jump "jump I2 positive" 41 |
772 | "Jump if the content of rI2 is positive. | |
0a2d0bd4 JB |
773 | Register J is set to the value of the next instruction that would have |
774 | been executed when there was no jump." | |
8511877a | 775 | 1) |
0a2d0bd4 | 776 | |
8511877a SM |
777 | (J2NN jump "jump I2 non-negative" 41 |
778 | "Jump if the content of rI2 is non-negative. | |
0a2d0bd4 JB |
779 | Register J is set to the value of the next instruction that would have |
780 | been executed when there was no jump." | |
8511877a | 781 | 1) |
0a2d0bd4 | 782 | |
8511877a SM |
783 | (J2NZ jump "jump I2 non-zero" 41 |
784 | "Jump if the content of rI2 is non-zero. | |
0a2d0bd4 JB |
785 | Register J is set to the value of the next instruction that would have |
786 | been executed when there was no jump." | |
8511877a | 787 | 1) |
0a2d0bd4 | 788 | |
8511877a SM |
789 | (J2NP jump "jump I2 non-positive" 41 |
790 | "Jump if the content of rI2 is non-positive. | |
0a2d0bd4 JB |
791 | Register J is set to the value of the next instruction that would have |
792 | been executed when there was no jump." | |
8511877a | 793 | 1) |
0a2d0bd4 | 794 | |
8511877a SM |
795 | (J3N jump "jump I3 negative" 41 |
796 | "Jump if the content of rI3 is negative. | |
0a2d0bd4 JB |
797 | Register J is set to the value of the next instruction that would have |
798 | been executed when there was no jump." | |
8511877a | 799 | 1) |
0a2d0bd4 | 800 | |
8511877a SM |
801 | (J3Z jump "jump I3 zero" 41 |
802 | "Jump if the content of rI3 is zero. | |
0a2d0bd4 JB |
803 | Register J is set to the value of the next instruction that would have |
804 | been executed when there was no jump." | |
8511877a | 805 | 1) |
0a2d0bd4 | 806 | |
8511877a SM |
807 | (J3P jump "jump I3 positive" 41 |
808 | "Jump if the content of rI3 is positive. | |
0a2d0bd4 JB |
809 | Register J is set to the value of the next instruction that would have |
810 | been executed when there was no jump." | |
8511877a | 811 | 1) |
0a2d0bd4 | 812 | |
8511877a SM |
813 | (J3NN jump "jump I3 non-negative" 41 |
814 | "Jump if the content of rI3 is non-negative. | |
0a2d0bd4 JB |
815 | Register J is set to the value of the next instruction that would have |
816 | been executed when there was no jump." | |
8511877a | 817 | 1) |
0a2d0bd4 | 818 | |
8511877a SM |
819 | (J3NZ jump "jump I3 non-zero" 41 |
820 | "Jump if the content of rI3 is non-zero. | |
0a2d0bd4 JB |
821 | Register J is set to the value of the next instruction that would have |
822 | been executed when there was no jump." | |
8511877a | 823 | 1) |
0a2d0bd4 | 824 | |
8511877a SM |
825 | (J3NP jump "jump I3 non-positive" 41 |
826 | "Jump if the content of rI3 is non-positive. | |
0a2d0bd4 JB |
827 | Register J is set to the value of the next instruction that would have |
828 | been executed when there was no jump." | |
8511877a | 829 | 1) |
0a2d0bd4 | 830 | |
8511877a SM |
831 | (J4N jump "jump I4 negative" 41 |
832 | "Jump if the content of rI4 is negative. | |
0a2d0bd4 JB |
833 | Register J is set to the value of the next instruction that would have |
834 | been executed when there was no jump." | |
8511877a | 835 | 1) |
0a2d0bd4 | 836 | |
8511877a SM |
837 | (J4Z jump "jump I4 zero" 41 |
838 | "Jump if the content of rI4 is zero. | |
0a2d0bd4 JB |
839 | Register J is set to the value of the next instruction that would have |
840 | been executed when there was no jump." | |
8511877a | 841 | 1) |
0a2d0bd4 | 842 | |
8511877a SM |
843 | (J4P jump "jump I4 positive" 41 |
844 | "Jump if the content of rI4 is positive. | |
0a2d0bd4 JB |
845 | Register J is set to the value of the next instruction that would have |
846 | been executed when there was no jump." | |
8511877a | 847 | 1) |
0a2d0bd4 | 848 | |
8511877a SM |
849 | (J4NN jump "jump I4 non-negative" 41 |
850 | "Jump if the content of rI4 is non-negative. | |
0a2d0bd4 JB |
851 | Register J is set to the value of the next instruction that would have |
852 | been executed when there was no jump." | |
8511877a | 853 | 1) |
0a2d0bd4 | 854 | |
8511877a SM |
855 | (J4NZ jump "jump I4 non-zero" 41 |
856 | "Jump if the content of rI4 is non-zero. | |
0a2d0bd4 JB |
857 | Register J is set to the value of the next instruction that would have |
858 | been executed when there was no jump." | |
8511877a | 859 | 1) |
0a2d0bd4 | 860 | |
8511877a SM |
861 | (J4NP jump "jump I4 non-positive" 41 |
862 | "Jump if the content of rI4 is non-positive. | |
0a2d0bd4 JB |
863 | Register J is set to the value of the next instruction that would have |
864 | been executed when there was no jump." | |
8511877a | 865 | 1) |
0a2d0bd4 | 866 | |
8511877a SM |
867 | (J5N jump "jump I5 negative" 41 |
868 | "Jump if the content of rI5 is negative. | |
0a2d0bd4 JB |
869 | Register J is set to the value of the next instruction that would have |
870 | been executed when there was no jump." | |
8511877a | 871 | 1) |
0a2d0bd4 | 872 | |
8511877a SM |
873 | (J5Z jump "jump I5 zero" 41 |
874 | "Jump if the content of rI5 is zero. | |
0a2d0bd4 JB |
875 | Register J is set to the value of the next instruction that would have |
876 | been executed when there was no jump." | |
8511877a | 877 | 1) |
0a2d0bd4 | 878 | |
8511877a SM |
879 | (J5P jump "jump I5 positive" 41 |
880 | "Jump if the content of rI5 is positive. | |
0a2d0bd4 JB |
881 | Register J is set to the value of the next instruction that would have |
882 | been executed when there was no jump." | |
8511877a | 883 | 1) |
0a2d0bd4 | 884 | |
8511877a SM |
885 | (J5NN jump "jump I5 non-negative" 41 |
886 | "Jump if the content of rI5 is non-negative. | |
0a2d0bd4 JB |
887 | Register J is set to the value of the next instruction that would have |
888 | been executed when there was no jump." | |
8511877a | 889 | 1) |
0a2d0bd4 | 890 | |
8511877a SM |
891 | (J5NZ jump "jump I5 non-zero" 41 |
892 | "Jump if the content of rI5 is non-zero. | |
0a2d0bd4 JB |
893 | Register J is set to the value of the next instruction that would have |
894 | been executed when there was no jump." | |
8511877a | 895 | 1) |
0a2d0bd4 | 896 | |
8511877a SM |
897 | (J5NP jump "jump I5 non-positive" 41 |
898 | "Jump if the content of rI5 is non-positive. | |
0a2d0bd4 JB |
899 | Register J is set to the value of the next instruction that would have |
900 | been executed when there was no jump." | |
8511877a | 901 | 1) |
0a2d0bd4 | 902 | |
8511877a SM |
903 | (J6N jump "jump I6 negative" 41 |
904 | "Jump if the content of rI6 is negative. | |
0a2d0bd4 JB |
905 | Register J is set to the value of the next instruction that would have |
906 | been executed when there was no jump." | |
8511877a | 907 | 1) |
0a2d0bd4 | 908 | |
8511877a SM |
909 | (J6Z jump "jump I6 zero" 41 |
910 | "Jump if the content of rI6 is zero. | |
0a2d0bd4 JB |
911 | Register J is set to the value of the next instruction that would have |
912 | been executed when there was no jump." | |
8511877a | 913 | 1) |
0a2d0bd4 | 914 | |
8511877a SM |
915 | (J6P jump "jump I6 positive" 41 |
916 | "Jump if the content of rI6 is positive. | |
0a2d0bd4 JB |
917 | Register J is set to the value of the next instruction that would have |
918 | been executed when there was no jump." | |
8511877a | 919 | 1) |
0a2d0bd4 | 920 | |
8511877a SM |
921 | (J6NN jump "jump I6 non-negative" 41 |
922 | "Jump if the content of rI6 is non-negative. | |
0a2d0bd4 JB |
923 | Register J is set to the value of the next instruction that would have |
924 | been executed when there was no jump." | |
8511877a | 925 | 1) |
0a2d0bd4 | 926 | |
8511877a SM |
927 | (J6NZ jump "jump I6 non-zero" 41 |
928 | "Jump if the content of rI6 is non-zero. | |
0a2d0bd4 JB |
929 | Register J is set to the value of the next instruction that would have |
930 | been executed when there was no jump." | |
8511877a | 931 | 1) |
0a2d0bd4 | 932 | |
8511877a SM |
933 | (J6NP jump "jump I6 non-positive" 41 |
934 | "Jump if the content of rI6 is non-positive. | |
0a2d0bd4 JB |
935 | Register J is set to the value of the next instruction that would have |
936 | been executed when there was no jump." | |
8511877a | 937 | 1) |
0a2d0bd4 | 938 | |
8511877a SM |
939 | (SLA miscellaneous "shift left A" 6 |
940 | "Shift to A, M bytes left. | |
0a2d0bd4 | 941 | Hero's will be added to the right." |
8511877a | 942 | 2) |
0a2d0bd4 | 943 | |
8511877a SM |
944 | (SRA miscellaneous "shift right A" 6 |
945 | "Shift to A, M bytes right. | |
0a2d0bd4 | 946 | Zeros will be added to the left." |
8511877a | 947 | 2) |
0a2d0bd4 | 948 | |
8511877a SM |
949 | (SLAX miscellaneous "shift left AX" 6 |
950 | "Shift AX, M bytes left. | |
0a2d0bd4 | 951 | Zeros will be added to the right." |
8511877a | 952 | 2) |
0a2d0bd4 JB |
953 | |
954 | ||
8511877a SM |
955 | (SRAX miscellaneous "shift right AX" 6 |
956 | "Shift AX, M bytes right. | |
0a2d0bd4 | 957 | Zeros will be added to the left." |
8511877a | 958 | 2) |
0a2d0bd4 | 959 | |
8511877a SM |
960 | (SLC miscellaneous "shift left AX circularly" 6 |
961 | "Shift AX, M bytes left circularly. | |
0a2d0bd4 | 962 | The bytes that fall off to the left will be added to the right." |
8511877a | 963 | 2) |
0a2d0bd4 | 964 | |
8511877a SM |
965 | (SRC miscellaneous "shift right AX circularly" 6 |
966 | "Shift AX, M bytes right circularly. | |
0a2d0bd4 | 967 | The bytes that fall off to the right will be added to the left." |
8511877a | 968 | 2) |
0a2d0bd4 | 969 | |
8511877a SM |
970 | (MOVE miscellaneous "move" 7 number |
971 | "Move MOD words from M to the location stored in rI1." | |
972 | (+ 1 (* 2 number))) | |
0a2d0bd4 | 973 | |
8511877a SM |
974 | (NOP miscellaneous "no operation" 0 ignored |
975 | "No operation, M and F are not used by the machine." | |
976 | 1) | |
0a2d0bd4 | 977 | |
8511877a SM |
978 | (HLT miscellaneous "halt" 5 |
979 | "Halt. | |
0a2d0bd4 | 980 | Stop instruction fetching." |
8511877a | 981 | 1) |
0a2d0bd4 | 982 | |
8511877a SM |
983 | (IN input-output "input" 36 unit |
984 | "Transfer a block of words from the specified unit to memory. | |
0a2d0bd4 | 985 | The transfer starts at address M." |
8511877a | 986 | 1) |
0a2d0bd4 | 987 | |
8511877a SM |
988 | (OUT input-output "output" 37 unit |
989 | "Transfer a block of words from memory. | |
0a2d0bd4 | 990 | The transfer starts at address M to the specified unit." |
8511877a | 991 | 1) |
0a2d0bd4 | 992 | |
8511877a SM |
993 | (IOC input-output "input-output control" 35 unit |
994 | "Perform a control operation. | |
0a2d0bd4 | 995 | The control operation is given by M on the specified unit." |
8511877a | 996 | 1) |
0a2d0bd4 | 997 | |
8511877a SM |
998 | (JRED input-output "jump ready" 38 unit |
999 | "Jump to M if the specified unit is ready." | |
1000 | 1) | |
0a2d0bd4 | 1001 | |
8511877a SM |
1002 | (JBUS input-output "jump busy" 34 unit |
1003 | "Jump to M if the specified unit is busy." | |
1004 | 1) | |
0a2d0bd4 | 1005 | |
8511877a SM |
1006 | (NUM conversion "convert to numeric" 5 |
1007 | "Convert rAX to its numerical value and store it in rA. | |
0a2d0bd4 JB |
1008 | the register rAX is assumed to contain a character representation of |
1009 | a number." | |
8511877a | 1010 | 10) |
0a2d0bd4 | 1011 | |
8511877a SM |
1012 | (CHAR conversion "convert to characters" 5 |
1013 | "Convert the number stored in rA to a character representation. | |
0a2d0bd4 | 1014 | The converted character representation is stored in rAX." |
8511877a | 1015 | 10)) |
0471d426 SM |
1016 | |
1017 | "Alist that contains all the possible operation codes for mix. | |
1018 | Each elt has the form | |
1019 | (OP-CODE GROUP FULL-NAME C-BYTE F-BYTE DESCRIPTION EXECUTION-TIME) | |
6a3ccec7 | 1020 | Where OP-CODE is the text of the opcode as a symbol, |
0471d426 SM |
1021 | FULL-NAME is the human readable name as a string, |
1022 | C-BYTE is the operation code telling what operation is to be performed, | |
1023 | F-BYTE holds a modification of the operation code which can be a symbol | |
1024 | or a number, | |
1025 | DESCRIPTION contains an string with a description about the operation code and | |
1026 | EXECUTION-TIME holds info about the time it takes, number or string.") | |
1027 | ;; (makunbound 'mixal-operation-codes-alist) | |
1028 | ||
1029 | ||
1030 | ;;; Font-locking: | |
cf38dd42 SM |
1031 | (defconst mixal-syntax-propertize-function |
1032 | (syntax-propertize-rules | |
1033 | ;; Normal comments start with a * in column 0 and end at end of line. | |
1034 | ("^\\*" (0 "<")) | |
1035 | ;; Every line can end with a comment which is placed after the operand. | |
1036 | ;; I assume here that mnemonics without operands can not have a comment. | |
1037 | ("^[[:alnum:]]*[ \t]+[[:alnum:]]+[ \t]+[^ \n\t]+[ \t]*\\([ \t]\\)[^\n \t]" | |
1038 | (1 "<")))) | |
0471d426 SM |
1039 | |
1040 | (defvar mixal-font-lock-keywords | |
1041 | `(("^\\([A-Z0-9a-z]+\\)" | |
1042 | (1 mixal-font-lock-label-face)) | |
1043 | (,(regexp-opt (mapcar (lambda (x) (symbol-name (car x))) | |
1044 | mixal-operation-codes-alist) 'words) | |
1045 | . mixal-font-lock-operation-code-face) | |
1046 | (,(regexp-opt mixal-assembly-pseudoinstructions 'words) | |
1047 | . mixal-font-lock-assembly-pseudoinstruction-face) | |
1048 | ("^[A-Z0-9a-z]*[ \t]+[A-ZO-9a-z]+[ \t]+\\(=.*=\\)" | |
1049 | (1 font-lock-constant-face))) | |
1050 | "Keyword highlighting specification for `mixal-mode'.") | |
1051 | ;; (makunbound 'mixal-font-lock-keywords) | |
0a2d0bd4 JB |
1052 | |
1053 | (defvar mixal-describe-operation-code-history nil | |
1054 | "History list for describe operation code.") | |
1055 | ||
0471d426 | 1056 | (defun mixal-describe-operation-code (op-code) |
0a2d0bd4 | 1057 | "Display the full documentation of OP-CODE." |
0471d426 SM |
1058 | (interactive |
1059 | (list | |
0a2d0bd4 JB |
1060 | (let* ((completion-ignore-case t) |
1061 | ;; we already have a list, but it is not in the right format | |
1062 | ;; transform it to a valid table so completition can use it | |
1063 | (table (mapcar '(lambda (elm) | |
1064 | (cons (symbol-name (car elm)) nil)) | |
1065 | mixal-operation-codes-alist)) | |
1066 | ;; prompt is different depending on we are close to a valid op-code | |
0471d426 SM |
1067 | (have-default (assq (intern-soft (current-word)) |
1068 | mixal-operation-codes-alist)) | |
0a2d0bd4 JB |
1069 | (prompt (concat "Describe operation code " |
1070 | (if have-default | |
1071 | (concat "(default " (current-word) "): ") | |
1072 | ": ")))) | |
0471d426 SM |
1073 | ;; As the operation code to the user. |
1074 | (completing-read prompt table nil t nil | |
1075 | 'mixal-describe-operation-code-history | |
1076 | (current-word))))) | |
0a2d0bd4 JB |
1077 | ;; get the info on the op-code and output it to the help buffer |
1078 | (let ((op-code-help (assq (intern-soft op-code) mixal-operation-codes-alist))) | |
1079 | (when op-code-help | |
1080 | (with-output-to-temp-buffer (buffer-name (get-buffer-create "*Help*")) | |
1081 | (princ op-code) (princ " is an mix operation code\n\n") | |
1082 | (princ (nth 5 op-code-help)) (terpri) (terpri) | |
1083 | (princ " group: ") (princ (nth 1 op-code-help)) (terpri) | |
1084 | (princ " nice name: ") (princ (nth 2 op-code-help)) (terpri) | |
1085 | (princ " OPCODE / C: ") (princ (nth 3 op-code-help)) (terpri) | |
1086 | (princ " MOD / F: ") (princ (nth 4 op-code-help)) (terpri) | |
1087 | (princ " time: ") (princ (nth 6 op-code-help)) (terpri))))) | |
1088 | ||
1089 | ;;;; Running | |
1090 | (defun mixal-run () | |
f8b4fcda | 1091 | "Run mixal file in current buffer, assumes that file has been compiled." |
0a2d0bd4 | 1092 | (interactive) |
91dd4dc4 DN |
1093 | (if (fboundp 'mixvm) |
1094 | (mixvm (concat "mixvm -r -t -d " | |
1095 | (file-name-sans-extension (buffer-file-name)))) | |
1096 | (error "mixvm.el needs to be loaded to run `mixvm'"))) | |
0a2d0bd4 JB |
1097 | |
1098 | (defun mixal-debug () | |
f8b4fcda SM |
1099 | "Start mixvm for debugging. |
1100 | Assumes that file has been compiled with debugging support." | |
0a2d0bd4 | 1101 | (interactive) |
91dd4dc4 DN |
1102 | (if (fboundp 'mixvm) |
1103 | (mixvm (concat "mixvm " | |
1104 | (file-name-sans-extension (buffer-file-name)))) | |
1105 | (error "mixvm.el needs to be loaded to run `mixvm'"))) | |
0a2d0bd4 JB |
1106 | |
1107 | ;;;###autoload | |
1108 | (define-derived-mode mixal-mode fundamental-mode "mixal" | |
175069ef | 1109 | "Major mode for the mixal asm language." |
0a2d0bd4 | 1110 | (set (make-local-variable 'comment-start) "*") |
0471d426 SM |
1111 | (set (make-local-variable 'comment-start-skip) "^\\*[ \t]*") |
1112 | (set (make-local-variable 'font-lock-defaults) | |
cf38dd42 SM |
1113 | `(mixal-font-lock-keywords)) |
1114 | (set (make-local-variable 'syntax-propertize-function) | |
1115 | mixal-syntax-propertize-function) | |
f8b4fcda SM |
1116 | ;; might add an indent function in the future |
1117 | ;; (set (make-local-variable 'indent-line-function) 'mixal-indent-line) | |
1118 | (set (make-local-variable 'compile-command) (concat "mixasm " | |
175069ef | 1119 | buffer-file-name))) |
0a2d0bd4 | 1120 | |
0a2d0bd4 | 1121 | (provide 'mixal-mode) |
ab5796a9 | 1122 | |
0a2d0bd4 | 1123 | ;;; mixal-mode.el ends here |