3 * IPACX specific routines
5 * Author Joerg Petersohn
6 * Derived from hisax_isac.c, isac.c, hscx.c and others
8 * This software may be used and distributed according to the terms
9 * of the GNU General Public License, incorporated herein by reference.
12 #include <linux/kernel.h>
13 #include <linux/config.h>
14 #include <linux/init.h>
15 #include <linux/workqueue.h>
21 #define DBUSY_TIMER_VALUE 80
22 #define TIMER3_VALUE 7000
23 #define MAX_DFRAME_LEN_L1 300
24 #define B_FIFO_SIZE 64
25 #define D_FIFO_SIZE 32
26 static spinlock_t ipacx_lock
= SPIN_LOCK_UNLOCKED
;
28 // ipacx interrupt mask values
29 #define _MASK_IMASK 0x2E // global mask
30 #define _MASKB_IMASK 0x0B
31 #define _MASKD_IMASK 0x03 // all on
33 //----------------------------------------------------------
34 // local function declarations
35 //----------------------------------------------------------
36 static void ph_command(struct IsdnCardState
*cs
, unsigned int command
);
37 static inline void cic_int(struct IsdnCardState
*cs
);
38 static void dch_l2l1(struct PStack
*st
, int pr
, void *arg
);
39 static void dbusy_timer_handler(struct IsdnCardState
*cs
);
40 static void ipacx_new_ph(struct IsdnCardState
*cs
);
41 static void dch_bh(void *data
);
42 static void dch_sched_event(struct IsdnCardState
*cs
, int event
);
43 static void dch_empty_fifo(struct IsdnCardState
*cs
, int count
);
44 static void dch_fill_fifo(struct IsdnCardState
*cs
);
45 static inline void dch_int(struct IsdnCardState
*cs
);
46 static void __devinit
dch_setstack(struct PStack
*st
, struct IsdnCardState
*cs
);
47 static void __devinit
dch_init(struct IsdnCardState
*cs
);
48 static void bch_l2l1(struct PStack
*st
, int pr
, void *arg
);
49 static void bch_sched_event(struct BCState
*bcs
, int event
);
50 static void bch_empty_fifo(struct BCState
*bcs
, int count
);
51 static void bch_fill_fifo(struct BCState
*bcs
);
52 static void bch_int(struct IsdnCardState
*cs
, u_char hscx
);
53 static void bch_mode(struct BCState
*bcs
, int mode
, int bc
);
54 static void bch_close_state(struct BCState
*bcs
);
55 static int bch_open_state(struct IsdnCardState
*cs
, struct BCState
*bcs
);
56 static int bch_setstack(struct PStack
*st
, struct BCState
*bcs
);
57 static void __devinit
bch_init(struct IsdnCardState
*cs
, int hscx
);
58 static void __init
clear_pending_ints(struct IsdnCardState
*cs
);
60 //----------------------------------------------------------
61 // Issue Layer 1 command to chip
62 //----------------------------------------------------------
64 ph_command(struct IsdnCardState
*cs
, unsigned int command
)
66 if (cs
->debug
&L1_DEB_ISAC
)
67 debugl1(cs
, "ph_command (%#x) in (%#x)", command
,
68 cs
->dc
.isac
.ph_state
);
69 cs
->writeisac(cs
, IPACX_CIX0
, (command
<< 4) | 0x0E);
72 //----------------------------------------------------------
73 // Transceiver interrupt handler
74 //----------------------------------------------------------
76 cic_int(struct IsdnCardState
*cs
)
80 event
= cs
->readisac(cs
, IPACX_CIR0
) >> 4;
81 if (cs
->debug
&L1_DEB_ISAC
) debugl1(cs
, "cic_int(event=%#x)", event
);
82 cs
->dc
.isac
.ph_state
= event
;
83 dch_sched_event(cs
, D_L1STATECHANGE
);
86 //==========================================================
87 // D channel functions
88 //==========================================================
90 //----------------------------------------------------------
91 // Command entry point
92 //----------------------------------------------------------
94 dch_l2l1(struct PStack
*st
, int pr
, void *arg
)
96 struct IsdnCardState
*cs
= (struct IsdnCardState
*) st
->l1
.hardware
;
97 struct sk_buff
*skb
= arg
;
98 u_char cda1_cr
, cda2_cr
;
101 case (PH_DATA
|REQUEST
):
102 if (cs
->debug
&DEB_DLOG_HEX
) LogFrame(cs
, skb
->data
, skb
->len
);
103 if (cs
->debug
&DEB_DLOG_VERBOSE
) dlogframe(cs
, skb
, 0);
105 skb_queue_tail(&cs
->sq
, skb
);
107 if (cs
->debug
&L1_DEB_LAPD
) Logl2Frame(cs
, skb
, "PH_DATA Queued", 0);
113 if (cs
->debug
&L1_DEB_LAPD
) Logl2Frame(cs
, skb
, "PH_DATA", 0);
119 case (PH_PULL
|INDICATION
):
121 if (cs
->debug
& L1_DEB_WARN
)
122 debugl1(cs
, " l2l1 tx_skb exist this shouldn't happen");
123 skb_queue_tail(&cs
->sq
, skb
);
126 if (cs
->debug
& DEB_DLOG_HEX
) LogFrame(cs
, skb
->data
, skb
->len
);
127 if (cs
->debug
& DEB_DLOG_VERBOSE
) dlogframe(cs
, skb
, 0);
131 if (cs
->debug
& L1_DEB_LAPD
) Logl2Frame(cs
, skb
, "PH_DATA_PULLED", 0);
136 case (PH_PULL
| REQUEST
):
138 if (cs
->debug
& L1_DEB_LAPD
) debugl1(cs
, "-> PH_REQUEST_PULL");
141 clear_bit(FLG_L1_PULL_REQ
, &st
->l1
.Flags
);
142 st
->l2
.l1l2(st
, PH_PULL
| CONFIRM
, NULL
);
144 set_bit(FLG_L1_PULL_REQ
, &st
->l1
.Flags
);
147 case (HW_RESET
| REQUEST
):
148 case (HW_ENABLE
| REQUEST
):
149 ph_command(cs
, IPACX_CMD_TIM
);
152 case (HW_INFO3
| REQUEST
):
153 ph_command(cs
, IPACX_CMD_AR8
);
156 case (HW_TESTLOOP
| REQUEST
):
157 cs
->writeisac(cs
, IPACX_CDA_TSDP10
, 0x80); // Timeslot 0 is B1
158 cs
->writeisac(cs
, IPACX_CDA_TSDP11
, 0x81); // Timeslot 0 is B1
159 cda1_cr
= cs
->readisac(cs
, IPACX_CDA1_CR
);
160 cda2_cr
= cs
->readisac(cs
, IPACX_CDA2_CR
);
161 if ((long)arg
&1) { // loop B1
162 cs
->writeisac(cs
, IPACX_CDA1_CR
, cda1_cr
|0x0a);
165 cs
->writeisac(cs
, IPACX_CDA1_CR
, cda1_cr
&~0x0a);
167 if ((long)arg
&2) { // loop B2
168 cs
->writeisac(cs
, IPACX_CDA1_CR
, cda1_cr
|0x14);
171 cs
->writeisac(cs
, IPACX_CDA1_CR
, cda1_cr
&~0x14);
175 case (HW_DEACTIVATE
| RESPONSE
):
176 skb_queue_purge(&cs
->rq
);
177 skb_queue_purge(&cs
->sq
);
179 dev_kfree_skb_any(cs
->tx_skb
);
182 if (test_and_clear_bit(FLG_DBUSY_TIMER
, &cs
->HW_Flags
))
183 del_timer(&cs
->dbusytimer
);
187 if (cs
->debug
&L1_DEB_WARN
) debugl1(cs
, "dch_l2l1 unknown %04x", pr
);
192 //----------------------------------------------------------
193 //----------------------------------------------------------
195 dbusy_timer_handler(struct IsdnCardState
*cs
)
200 if (test_bit(FLG_DBUSY_TIMER
, &cs
->HW_Flags
)) {
201 rbchd
= cs
->readisac(cs
, IPACX_RBCHD
);
202 stard
= cs
->readisac(cs
, IPACX_STARD
);
204 debugl1(cs
, "D-Channel Busy RBCHD %02x STARD %02x", rbchd
, stard
);
205 if (!(stard
&0x40)) { // D-Channel Busy
206 set_bit(FLG_L1_DBUSY
, &cs
->HW_Flags
);
207 for (st
= cs
->stlist
; st
; st
= st
->next
) {
208 st
->l2
.l1l2(st
, PH_PAUSE
| INDICATION
, NULL
); // flow control on
211 // seems we lost an interrupt; reset transceiver */
212 clear_bit(FLG_DBUSY_TIMER
, &cs
->HW_Flags
);
214 dev_kfree_skb_any(cs
->tx_skb
);
218 printk(KERN_WARNING
"HiSax: ISAC D-Channel Busy no skb\n");
219 debugl1(cs
, "D-Channel Busy no skb");
221 cs
->writeisac(cs
, IPACX_CMDRD
, 0x01); // Tx reset, generates XPR
226 //----------------------------------------------------------
227 // L1 state machine intermediate layer to isdnl1 module
228 //----------------------------------------------------------
230 ipacx_new_ph(struct IsdnCardState
*cs
)
232 switch (cs
->dc
.isac
.ph_state
) {
233 case (IPACX_IND_RES
):
234 ph_command(cs
, IPACX_CMD_DI
);
235 l1_msg(cs
, HW_RESET
| INDICATION
, NULL
);
239 l1_msg(cs
, HW_DEACTIVATE
| CONFIRM
, NULL
);
243 l1_msg(cs
, HW_DEACTIVATE
| INDICATION
, NULL
);
247 l1_msg(cs
, HW_POWERUP
| CONFIRM
, NULL
);
250 case (IPACX_IND_RSY
):
251 l1_msg(cs
, HW_RSYNC
| INDICATION
, NULL
);
255 l1_msg(cs
, HW_INFO2
| INDICATION
, NULL
);
258 case (IPACX_IND_AI8
):
259 l1_msg(cs
, HW_INFO4_P8
| INDICATION
, NULL
);
262 case (IPACX_IND_AI10
):
263 l1_msg(cs
, HW_INFO4_P10
| INDICATION
, NULL
);
271 //----------------------------------------------------------
272 // bottom half handler for D channel
273 //----------------------------------------------------------
277 struct IsdnCardState
*cs
= data
;
282 if (test_and_clear_bit(D_CLEARBUSY
, &cs
->event
)) {
283 if (cs
->debug
) debugl1(cs
, "D-Channel Busy cleared");
284 for (st
= cs
->stlist
; st
; st
= st
->next
) {
285 st
->l2
.l1l2(st
, PH_PAUSE
| CONFIRM
, NULL
);
289 if (test_and_clear_bit(D_RCVBUFREADY
, &cs
->event
)) {
290 DChannel_proc_rcv(cs
);
293 if (test_and_clear_bit(D_XMTBUFREADY
, &cs
->event
)) {
294 DChannel_proc_xmt(cs
);
297 if (test_and_clear_bit(D_L1STATECHANGE
, &cs
->event
)) {
302 //----------------------------------------------------------
303 // proceed with bottom half handler dch_bh()
304 //----------------------------------------------------------
306 dch_sched_event(struct IsdnCardState
*cs
, int event
)
308 set_bit(event
, &cs
->event
);
309 schedule_work(&cs
->work
);
312 //----------------------------------------------------------
313 // Fill buffer from receive FIFO
314 //----------------------------------------------------------
316 dch_empty_fifo(struct IsdnCardState
*cs
, int count
)
321 if ((cs
->debug
&L1_DEB_ISAC
) && !(cs
->debug
&L1_DEB_ISAC_FIFO
))
322 debugl1(cs
, "dch_empty_fifo()");
324 // message too large, remove
325 if ((cs
->rcvidx
+ count
) >= MAX_DFRAME_LEN_L1
) {
326 if (cs
->debug
&L1_DEB_WARN
)
327 debugl1(cs
, "dch_empty_fifo() incoming message too large");
328 cs
->writeisac(cs
, IPACX_CMDRD
, 0x80); // RMC
333 ptr
= cs
->rcvbuf
+ cs
->rcvidx
;
336 spin_lock_irqsave(&ipacx_lock
, flags
);
337 cs
->readisacfifo(cs
, ptr
, count
);
338 cs
->writeisac(cs
, IPACX_CMDRD
, 0x80); // RMC
339 spin_unlock_irqrestore(&ipacx_lock
, flags
);
341 if (cs
->debug
&L1_DEB_ISAC_FIFO
) {
344 t
+= sprintf(t
, "dch_empty_fifo() cnt %d", count
);
345 QuickHex(t
, ptr
, count
);
346 debugl1(cs
, cs
->dlog
);
350 //----------------------------------------------------------
351 // Fill transmit FIFO
352 //----------------------------------------------------------
354 dch_fill_fifo(struct IsdnCardState
*cs
)
360 if ((cs
->debug
&L1_DEB_ISAC
) && !(cs
->debug
&L1_DEB_ISAC_FIFO
))
361 debugl1(cs
, "dch_fill_fifo()");
363 if (!cs
->tx_skb
) return;
364 count
= cs
->tx_skb
->len
;
365 if (count
<= 0) return;
367 if (count
> D_FIFO_SIZE
) {
371 cmd
= 0x0A; // XTF | XME
374 spin_lock_irqsave(&ipacx_lock
, flags
);
375 ptr
= cs
->tx_skb
->data
;
376 skb_pull(cs
->tx_skb
, count
);
378 cs
->writeisacfifo(cs
, ptr
, count
);
379 cs
->writeisac(cs
, IPACX_CMDRD
, cmd
);
381 // set timeout for transmission contol
382 if (test_and_set_bit(FLG_DBUSY_TIMER
, &cs
->HW_Flags
)) {
383 debugl1(cs
, "dch_fill_fifo dbusytimer running");
384 del_timer(&cs
->dbusytimer
);
386 init_timer(&cs
->dbusytimer
);
387 cs
->dbusytimer
.expires
= jiffies
+ ((DBUSY_TIMER_VALUE
* HZ
)/1000);
388 add_timer(&cs
->dbusytimer
);
389 spin_unlock_irqrestore(&ipacx_lock
, flags
);
391 if (cs
->debug
&L1_DEB_ISAC_FIFO
) {
394 t
+= sprintf(t
, "dch_fill_fifo() cnt %d", count
);
395 QuickHex(t
, ptr
, count
);
396 debugl1(cs
, cs
->dlog
);
400 //----------------------------------------------------------
401 // D channel interrupt handler
402 //----------------------------------------------------------
404 dch_int(struct IsdnCardState
*cs
)
411 istad
= cs
->readisac(cs
, IPACX_ISTAD
);
413 if (istad
&0x80) { // RME
414 rstad
= cs
->readisac(cs
, IPACX_RSTAD
);
415 if ((rstad
&0xf0) != 0xa0) { // !(VFR && !RDO && CRC && !RAB)
417 if (cs
->debug
&L1_DEB_WARN
)
418 debugl1(cs
, "dch_int(): invalid frame");
420 if (cs
->debug
&L1_DEB_WARN
)
421 debugl1(cs
, "dch_int(): RDO");
423 if (cs
->debug
&L1_DEB_WARN
)
424 debugl1(cs
, "dch_int(): CRC error");
425 cs
->writeisac(cs
, IPACX_CMDRD
, 0x80); // RMC
426 } else { // received frame ok
427 count
= cs
->readisac(cs
, IPACX_RBCLD
);
428 if (count
) count
--; // RSTAB is last byte
429 count
&= D_FIFO_SIZE
-1;
430 if (count
== 0) count
= D_FIFO_SIZE
;
431 dch_empty_fifo(cs
, count
);
432 spin_lock_irqsave(&ipacx_lock
, flags
);
433 if ((count
= cs
->rcvidx
) > 0) {
435 if (!(skb
= dev_alloc_skb(count
)))
436 printk(KERN_WARNING
"HiSax dch_int(): receive out of memory\n");
438 memcpy(skb_put(skb
, count
), cs
->rcvbuf
, count
);
439 skb_queue_tail(&cs
->rq
, skb
);
442 spin_unlock_irqrestore(&ipacx_lock
, flags
);
445 dch_sched_event(cs
, D_RCVBUFREADY
);
448 if (istad
&0x40) { // RPF
449 dch_empty_fifo(cs
, D_FIFO_SIZE
);
452 if (istad
&0x20) { // RFO
453 if (cs
->debug
&L1_DEB_WARN
) debugl1(cs
, "dch_int(): RFO");
454 cs
->writeisac(cs
, IPACX_CMDRD
, 0x40); //RRES
457 if (istad
&0x10) { // XPR
458 if (test_and_clear_bit(FLG_DBUSY_TIMER
, &cs
->HW_Flags
))
459 del_timer(&cs
->dbusytimer
);
460 if (test_and_clear_bit(FLG_L1_DBUSY
, &cs
->HW_Flags
))
461 dch_sched_event(cs
, D_CLEARBUSY
);
463 if (cs
->tx_skb
->len
) {
468 dev_kfree_skb_irq(cs
->tx_skb
);
473 if ((cs
->tx_skb
= skb_dequeue(&cs
->sq
))) {
478 dch_sched_event(cs
, D_XMTBUFREADY
);
483 if (istad
&0x0C) { // XDU or XMR
484 if (cs
->debug
&L1_DEB_WARN
) debugl1(cs
, "dch_int(): XDU");
486 skb_push(cs
->tx_skb
, cs
->tx_cnt
); // retransmit
490 printk(KERN_WARNING
"HiSax: ISAC XDU no skb\n");
491 debugl1(cs
, "ISAC XDU no skb");
496 //----------------------------------------------------------
497 //----------------------------------------------------------
498 static void __devinit
499 dch_setstack(struct PStack
*st
, struct IsdnCardState
*cs
)
501 st
->l1
.l1hw
= dch_l2l1
;
504 //----------------------------------------------------------
505 //----------------------------------------------------------
506 static void __devinit
507 dch_init(struct IsdnCardState
*cs
)
509 printk(KERN_INFO
"HiSax: IPACX ISDN driver v0.1.0\n");
511 INIT_WORK(&cs
->work
, dch_bh
, cs
);
512 cs
->setstack_d
= dch_setstack
;
514 cs
->dbusytimer
.function
= (void *) dbusy_timer_handler
;
515 cs
->dbusytimer
.data
= (long) cs
;
516 init_timer(&cs
->dbusytimer
);
518 cs
->writeisac(cs
, IPACX_TR_CONF0
, 0x00); // clear LDD
519 cs
->writeisac(cs
, IPACX_TR_CONF2
, 0x00); // enable transmitter
520 cs
->writeisac(cs
, IPACX_MODED
, 0xC9); // transparent mode 0, RAC, stop/go
521 cs
->writeisac(cs
, IPACX_MON_CR
, 0x00); // disable monitor channel
525 //==========================================================
526 // B channel functions
527 //==========================================================
529 //----------------------------------------------------------
530 // Entry point for commands
531 //----------------------------------------------------------
533 bch_l2l1(struct PStack
*st
, int pr
, void *arg
)
535 struct sk_buff
*skb
= arg
;
539 case (PH_DATA
| REQUEST
):
540 spin_lock_irqsave(&ipacx_lock
, flags
);
541 if (st
->l1
.bcs
->tx_skb
) {
542 skb_queue_tail(&st
->l1
.bcs
->squeue
, skb
);
543 spin_unlock_irqrestore(&ipacx_lock
, flags
);
545 st
->l1
.bcs
->tx_skb
= skb
;
546 set_bit(BC_FLG_BUSY
, &st
->l1
.bcs
->Flag
);
547 st
->l1
.bcs
->hw
.hscx
.count
= 0;
548 spin_unlock_irqrestore(&ipacx_lock
, flags
);
549 bch_fill_fifo(st
->l1
.bcs
);
552 case (PH_PULL
| INDICATION
):
553 if (st
->l1
.bcs
->tx_skb
) {
554 printk(KERN_WARNING
"HiSax bch_l2l1(): this shouldn't happen\n");
557 set_bit(BC_FLG_BUSY
, &st
->l1
.bcs
->Flag
);
558 st
->l1
.bcs
->tx_skb
= skb
;
559 st
->l1
.bcs
->hw
.hscx
.count
= 0;
560 bch_fill_fifo(st
->l1
.bcs
);
562 case (PH_PULL
| REQUEST
):
563 if (!st
->l1
.bcs
->tx_skb
) {
564 clear_bit(FLG_L1_PULL_REQ
, &st
->l1
.Flags
);
565 st
->l2
.l1l2(st
, PH_PULL
| CONFIRM
, NULL
);
567 set_bit(FLG_L1_PULL_REQ
, &st
->l1
.Flags
);
569 case (PH_ACTIVATE
| REQUEST
):
570 set_bit(BC_FLG_ACTIV
, &st
->l1
.bcs
->Flag
);
571 bch_mode(st
->l1
.bcs
, st
->l1
.mode
, st
->l1
.bc
);
572 l1_msg_b(st
, pr
, arg
);
574 case (PH_DEACTIVATE
| REQUEST
):
575 l1_msg_b(st
, pr
, arg
);
577 case (PH_DEACTIVATE
| CONFIRM
):
578 clear_bit(BC_FLG_ACTIV
, &st
->l1
.bcs
->Flag
);
579 clear_bit(BC_FLG_BUSY
, &st
->l1
.bcs
->Flag
);
580 bch_mode(st
->l1
.bcs
, 0, st
->l1
.bc
);
581 st
->l2
.l1l2(st
, PH_DEACTIVATE
| CONFIRM
, NULL
);
586 //----------------------------------------------------------
587 // proceed with bottom half handler BChannel_bh()
588 //----------------------------------------------------------
590 bch_sched_event(struct BCState
*bcs
, int event
)
592 bcs
->event
|= 1 << event
;
593 schedule_work(&bcs
->work
);
596 //----------------------------------------------------------
597 // Read B channel fifo to receive buffer
598 //----------------------------------------------------------
600 bch_empty_fifo(struct BCState
*bcs
, int count
)
603 struct IsdnCardState
*cs
;
608 hscx
= bcs
->hw
.hscx
.hscx
;
609 if ((cs
->debug
&L1_DEB_HSCX
) && !(cs
->debug
&L1_DEB_HSCX_FIFO
))
610 debugl1(cs
, "bch_empty_fifo()");
612 // message too large, remove
613 if (bcs
->hw
.hscx
.rcvidx
+ count
> HSCX_BUFMAX
) {
614 if (cs
->debug
&L1_DEB_WARN
)
615 debugl1(cs
, "bch_empty_fifo() incoming packet too large");
616 cs
->BC_Write_Reg(cs
, hscx
, IPACX_CMDRB
, 0x80); // RMC
617 bcs
->hw
.hscx
.rcvidx
= 0;
621 // Read data uninterruptible
622 spin_lock_irqsave(&ipacx_lock
, flags
);
623 ptr
= bcs
->hw
.hscx
.rcvbuf
+ bcs
->hw
.hscx
.rcvidx
;
625 while (cnt
--) *ptr
++ = cs
->BC_Read_Reg(cs
, hscx
, IPACX_RFIFOB
);
626 cs
->BC_Write_Reg(cs
, hscx
, IPACX_CMDRB
, 0x80); // RMC
628 ptr
= bcs
->hw
.hscx
.rcvbuf
+ bcs
->hw
.hscx
.rcvidx
;
629 bcs
->hw
.hscx
.rcvidx
+= count
;
630 spin_unlock_irqrestore(&ipacx_lock
, flags
);
632 if (cs
->debug
&L1_DEB_HSCX_FIFO
) {
635 t
+= sprintf(t
, "bch_empty_fifo() B-%d cnt %d", hscx
, count
);
636 QuickHex(t
, ptr
, count
);
637 debugl1(cs
, bcs
->blog
);
641 //----------------------------------------------------------
642 // Fill buffer to transmit FIFO
643 //----------------------------------------------------------
645 bch_fill_fifo(struct BCState
*bcs
)
647 struct IsdnCardState
*cs
;
648 int more
, count
, cnt
;
649 u_char
*ptr
, *p
, hscx
;
653 if ((cs
->debug
&L1_DEB_HSCX
) && !(cs
->debug
&L1_DEB_HSCX_FIFO
))
654 debugl1(cs
, "bch_fill_fifo()");
656 if (!bcs
->tx_skb
) return;
657 if (bcs
->tx_skb
->len
<= 0) return;
659 hscx
= bcs
->hw
.hscx
.hscx
;
660 more
= (bcs
->mode
== L1_MODE_TRANS
) ? 1 : 0;
661 if (bcs
->tx_skb
->len
> B_FIFO_SIZE
) {
665 count
= bcs
->tx_skb
->len
;
669 spin_lock_irqsave(&ipacx_lock
, flags
);
670 p
= ptr
= bcs
->tx_skb
->data
;
671 skb_pull(bcs
->tx_skb
, count
);
672 bcs
->tx_cnt
-= count
;
673 bcs
->hw
.hscx
.count
+= count
;
674 while (cnt
--) cs
->BC_Write_Reg(cs
, hscx
, IPACX_XFIFOB
, *p
++);
675 cs
->BC_Write_Reg(cs
, hscx
, IPACX_CMDRB
, (more
? 0x08 : 0x0a));
676 spin_unlock_irqrestore(&ipacx_lock
, flags
);
678 if (cs
->debug
&L1_DEB_HSCX_FIFO
) {
681 t
+= sprintf(t
, "chb_fill_fifo() B-%d cnt %d", hscx
, count
);
682 QuickHex(t
, ptr
, count
);
683 debugl1(cs
, bcs
->blog
);
687 //----------------------------------------------------------
688 // B channel interrupt handler
689 //----------------------------------------------------------
691 bch_int(struct IsdnCardState
*cs
, u_char hscx
)
699 bcs
= cs
->bcs
+ hscx
;
700 istab
= cs
->BC_Read_Reg(cs
, hscx
, IPACX_ISTAB
);
701 if (!test_bit(BC_FLG_INIT
, &bcs
->Flag
)) return;
703 if (istab
&0x80) { // RME
704 rstab
= cs
->BC_Read_Reg(cs
, hscx
, IPACX_RSTAB
);
705 if ((rstab
&0xf0) != 0xa0) { // !(VFR && !RDO && CRC && !RAB)
707 if (cs
->debug
&L1_DEB_WARN
)
708 debugl1(cs
, "bch_int() B-%d: invalid frame", hscx
);
709 if ((rstab
&0x40) && (bcs
->mode
!= L1_MODE_NULL
))
710 if (cs
->debug
&L1_DEB_WARN
)
711 debugl1(cs
, "bch_int() B-%d: RDO mode=%d", hscx
, bcs
->mode
);
713 if (cs
->debug
&L1_DEB_WARN
)
714 debugl1(cs
, "bch_int() B-%d: CRC error", hscx
);
715 cs
->BC_Write_Reg(cs
, hscx
, IPACX_CMDRB
, 0x80); // RMC
717 else { // received frame ok
718 count
= cs
->BC_Read_Reg(cs
, hscx
, IPACX_RBCLB
) &(B_FIFO_SIZE
-1);
719 if (count
== 0) count
= B_FIFO_SIZE
;
720 bch_empty_fifo(bcs
, count
);
721 if ((count
= bcs
->hw
.hscx
.rcvidx
- 1) > 0) {
722 if (cs
->debug
&L1_DEB_HSCX_FIFO
)
723 debugl1(cs
, "bch_int Frame %d", count
);
724 if (!(skb
= dev_alloc_skb(count
)))
725 printk(KERN_WARNING
"HiSax bch_int(): receive frame out of memory\n");
727 memcpy(skb_put(skb
, count
), bcs
->hw
.hscx
.rcvbuf
, count
);
728 skb_queue_tail(&bcs
->rqueue
, skb
);
732 bcs
->hw
.hscx
.rcvidx
= 0;
733 bch_sched_event(bcs
, B_RCVBUFREADY
);
736 if (istab
&0x40) { // RPF
737 bch_empty_fifo(bcs
, B_FIFO_SIZE
);
739 if (bcs
->mode
== L1_MODE_TRANS
) { // queue every chunk
740 // receive transparent audio data
741 if (!(skb
= dev_alloc_skb(B_FIFO_SIZE
)))
742 printk(KERN_WARNING
"HiSax bch_int(): receive transparent out of memory\n");
744 memcpy(skb_put(skb
, B_FIFO_SIZE
), bcs
->hw
.hscx
.rcvbuf
, B_FIFO_SIZE
);
745 skb_queue_tail(&bcs
->rqueue
, skb
);
747 bcs
->hw
.hscx
.rcvidx
= 0;
748 bch_sched_event(bcs
, B_RCVBUFREADY
);
752 if (istab
&0x20) { // RFO
753 if (cs
->debug
&L1_DEB_WARN
)
754 debugl1(cs
, "bch_int() B-%d: RFO error", hscx
);
755 cs
->BC_Write_Reg(cs
, hscx
, IPACX_CMDRB
, 0x40); // RRES
758 if (istab
&0x10) { // XPR
760 if (bcs
->tx_skb
->len
) {
764 skb_queue_tail(&bcs
->cmpl_queue
, bcs
->tx_skb
);
765 bch_sched_event(bcs
, B_CMPLREADY
);
766 bcs
->hw
.hscx
.count
= 0;
768 if ((bcs
->tx_skb
= skb_dequeue(&bcs
->squeue
))) {
769 bcs
->hw
.hscx
.count
= 0;
770 set_bit(BC_FLG_BUSY
, &bcs
->Flag
);
773 clear_bit(BC_FLG_BUSY
, &bcs
->Flag
);
774 bch_sched_event(bcs
, B_XMTBUFREADY
);
779 if (istab
&0x04) { // XDU
780 if (bcs
->mode
== L1_MODE_TRANS
) {
784 if (bcs
->tx_skb
) { // restart transmitting the whole frame
785 skb_push(bcs
->tx_skb
, bcs
->hw
.hscx
.count
);
786 bcs
->tx_cnt
+= bcs
->hw
.hscx
.count
;
787 bcs
->hw
.hscx
.count
= 0;
789 cs
->BC_Write_Reg(cs
, hscx
, IPACX_CMDRB
, 0x01); // XRES
790 if (cs
->debug
&L1_DEB_WARN
)
791 debugl1(cs
, "bch_int() B-%d XDU error", hscx
);
796 //----------------------------------------------------------
797 //----------------------------------------------------------
799 bch_mode(struct BCState
*bcs
, int mode
, int bc
)
801 struct IsdnCardState
*cs
= bcs
->cs
;
802 int hscx
= bcs
->hw
.hscx
.hscx
;
804 bc
= bc
? 1 : 0; // in case bc is greater than 1
805 if (cs
->debug
& L1_DEB_HSCX
)
806 debugl1(cs
, "mode_bch() switch B-% mode %d chan %d", hscx
, mode
, bc
);
810 // map controller to according timeslot
813 cs
->writeisac(cs
, IPACX_BCHA_TSDP_BC1
, 0x80 | bc
);
814 cs
->writeisac(cs
, IPACX_BCHA_CR
, 0x88);
818 cs
->writeisac(cs
, IPACX_BCHB_TSDP_BC1
, 0x80 | bc
);
819 cs
->writeisac(cs
, IPACX_BCHB_CR
, 0x88);
824 cs
->BC_Write_Reg(cs
, hscx
, IPACX_MODEB
, 0xC0); // rec off
825 cs
->BC_Write_Reg(cs
, hscx
, IPACX_EXMB
, 0x30); // std adj.
826 cs
->BC_Write_Reg(cs
, hscx
, IPACX_MASKB
, 0xFF); // ints off
827 cs
->BC_Write_Reg(cs
, hscx
, IPACX_CMDRB
, 0x41); // validate adjustments
829 case (L1_MODE_TRANS
):
830 cs
->BC_Write_Reg(cs
, hscx
, IPACX_MODEB
, 0x88); // ext transp mode
831 cs
->BC_Write_Reg(cs
, hscx
, IPACX_EXMB
, 0x00); // xxx00000
832 cs
->BC_Write_Reg(cs
, hscx
, IPACX_CMDRB
, 0x41); // validate adjustments
833 cs
->BC_Write_Reg(cs
, hscx
, IPACX_MASKB
, _MASKB_IMASK
);
836 cs
->BC_Write_Reg(cs
, hscx
, IPACX_MODEB
, 0xC8); // transp mode 0
837 cs
->BC_Write_Reg(cs
, hscx
, IPACX_EXMB
, 0x01); // idle=hdlc flags crc enabled
838 cs
->BC_Write_Reg(cs
, hscx
, IPACX_CMDRB
, 0x41); // validate adjustments
839 cs
->BC_Write_Reg(cs
, hscx
, IPACX_MASKB
, _MASKB_IMASK
);
844 //----------------------------------------------------------
845 //----------------------------------------------------------
847 bch_close_state(struct BCState
*bcs
)
849 bch_mode(bcs
, 0, bcs
->channel
);
850 if (test_and_clear_bit(BC_FLG_INIT
, &bcs
->Flag
)) {
851 if (bcs
->hw
.hscx
.rcvbuf
) {
852 kfree(bcs
->hw
.hscx
.rcvbuf
);
853 bcs
->hw
.hscx
.rcvbuf
= NULL
;
859 skb_queue_purge(&bcs
->rqueue
);
860 skb_queue_purge(&bcs
->squeue
);
862 dev_kfree_skb_any(bcs
->tx_skb
);
864 clear_bit(BC_FLG_BUSY
, &bcs
->Flag
);
869 //----------------------------------------------------------
870 //----------------------------------------------------------
872 bch_open_state(struct IsdnCardState
*cs
, struct BCState
*bcs
)
874 if (!test_and_set_bit(BC_FLG_INIT
, &bcs
->Flag
)) {
875 if (!(bcs
->hw
.hscx
.rcvbuf
= kmalloc(HSCX_BUFMAX
, GFP_ATOMIC
))) {
877 "HiSax open_bchstate(): No memory for hscx.rcvbuf\n");
878 clear_bit(BC_FLG_INIT
, &bcs
->Flag
);
881 if (!(bcs
->blog
= kmalloc(MAX_BLOG_SPACE
, GFP_ATOMIC
))) {
883 "HiSax open_bchstate: No memory for bcs->blog\n");
884 clear_bit(BC_FLG_INIT
, &bcs
->Flag
);
885 kfree(bcs
->hw
.hscx
.rcvbuf
);
886 bcs
->hw
.hscx
.rcvbuf
= NULL
;
889 skb_queue_head_init(&bcs
->rqueue
);
890 skb_queue_head_init(&bcs
->squeue
);
893 clear_bit(BC_FLG_BUSY
, &bcs
->Flag
);
895 bcs
->hw
.hscx
.rcvidx
= 0;
900 //----------------------------------------------------------
901 //----------------------------------------------------------
903 bch_setstack(struct PStack
*st
, struct BCState
*bcs
)
905 bcs
->channel
= st
->l1
.bc
;
906 if (bch_open_state(st
->l1
.hardware
, bcs
)) return (-1);
908 st
->l1
.l2l1
= bch_l2l1
;
909 setstack_manager(st
);
915 //----------------------------------------------------------
916 //----------------------------------------------------------
917 static void __devinit
918 bch_init(struct IsdnCardState
*cs
, int hscx
)
920 cs
->bcs
[hscx
].BC_SetStack
= bch_setstack
;
921 cs
->bcs
[hscx
].BC_Close
= bch_close_state
;
922 cs
->bcs
[hscx
].hw
.hscx
.hscx
= hscx
;
923 cs
->bcs
[hscx
].cs
= cs
;
924 bch_mode(cs
->bcs
+ hscx
, 0, hscx
);
928 //==========================================================
930 //==========================================================
932 //----------------------------------------------------------
933 // Main interrupt handler
934 //----------------------------------------------------------
936 interrupt_ipacx(struct IsdnCardState
*cs
)
940 while ((ista
= cs
->readisac(cs
, IPACX_ISTA
))) {
941 if (ista
&0x80) bch_int(cs
, 0); // B channel interrupts
942 if (ista
&0x40) bch_int(cs
, 1);
943 if (ista
&0x01) dch_int(cs
); // D channel
944 if (ista
&0x10) cic_int(cs
); // Layer 1 state
948 //----------------------------------------------------------
949 // Clears chip interrupt status
950 //----------------------------------------------------------
952 clear_pending_ints(struct IsdnCardState
*cs
)
956 // all interrupts off
957 cs
->writeisac(cs
, IPACX_MASK
, 0xff);
958 cs
->writeisac(cs
, IPACX_MASKD
, 0xff);
959 cs
->BC_Write_Reg(cs
, 0, IPACX_MASKB
, 0xff);
960 cs
->BC_Write_Reg(cs
, 1, IPACX_MASKB
, 0xff);
962 ista
= cs
->readisac(cs
, IPACX_ISTA
);
963 if (ista
&0x80) cs
->BC_Read_Reg(cs
, 0, IPACX_ISTAB
);
964 if (ista
&0x40) cs
->BC_Read_Reg(cs
, 1, IPACX_ISTAB
);
965 if (ista
&0x10) cs
->readisac(cs
, IPACX_CIR0
);
966 if (ista
&0x01) cs
->readisac(cs
, IPACX_ISTAD
);
969 //----------------------------------------------------------
970 // Does chip configuration work
971 // Work to do depends on bit mask in part
972 //----------------------------------------------------------
974 init_ipacx(struct IsdnCardState
*cs
, int part
)
976 if (part
&1) { // initialise chip
977 clear_pending_ints(cs
);
982 if (part
&2) { // reenable all interrupts and start chip
983 cs
->BC_Write_Reg(cs
, 0, IPACX_MASKB
, _MASKB_IMASK
);
984 cs
->BC_Write_Reg(cs
, 1, IPACX_MASKB
, _MASKB_IMASK
);
985 cs
->writeisac(cs
, IPACX_MASKD
, _MASKD_IMASK
);
986 cs
->writeisac(cs
, IPACX_MASK
, _MASK_IMASK
); // global mask register
988 // reset HDLC Transmitters/receivers
989 cs
->writeisac(cs
, IPACX_CMDRD
, 0x41);
990 cs
->BC_Write_Reg(cs
, 0, IPACX_CMDRB
, 0x41);
991 cs
->BC_Write_Reg(cs
, 1, IPACX_CMDRB
, 0x41);
992 ph_command(cs
, IPACX_CMD_RES
);
996 //----------------- end of file -----------------------