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coccinelle release 0.2.5
[bpt/coccinelle.git] / tests / proto_ver2.c
CommitLineData
34e49164
C		 1/*
2 *
3 * IPACX specific routines
4 *
5 * Author Joerg Petersohn
6 * Derived from hisax_isac.c, isac.c, hscx.c and others
7 *
8 * This software may be used and distributed according to the terms
9 * of the GNU General Public License, incorporated herein by reference.
10 *
11 */
12#include <linux/kernel.h>
13#include <linux/config.h>
14#include <linux/init.h>
15#include <linux/workqueue.h>
16#include "hisax_if.h"
17#include "hisax.h"
18#include "isdnl1.h"
19#include "ipacx.h"
20
21#define DBUSY_TIMER_VALUE 80
22#define TIMER3_VALUE 7000
23#define MAX_DFRAME_LEN_L1 300
24#define B_FIFO_SIZE 64
25#define D_FIFO_SIZE 32
26static spinlock_t ipacx_lock = SPIN_LOCK_UNLOCKED;
27
28// ipacx interrupt mask values
29#define _MASK_IMASK 0x2E // global mask
30#define _MASKB_IMASK 0x0B
31#define _MASKD_IMASK 0x03 // all on
32
33//----------------------------------------------------------
34// local function declarations
35//----------------------------------------------------------
36static void ph_command(struct IsdnCardState *cs, unsigned int command);
37static inline void cic_int(struct IsdnCardState *cs);
38static void dch_l2l1(struct PStack *st, int pr, void *arg);
39static void dbusy_timer_handler(struct IsdnCardState *cs);
40static void ipacx_new_ph(struct IsdnCardState *cs);
41static void dch_bh(void *data);
42static void dch_sched_event(struct IsdnCardState *cs, int event);
43static void dch_empty_fifo(struct IsdnCardState *cs, int count);
44static void dch_fill_fifo(struct IsdnCardState *cs);
45static inline void dch_int(struct IsdnCardState *cs);
46static void __devinit dch_setstack(struct PStack *st, struct IsdnCardState *cs);
47static void __devinit dch_init(struct IsdnCardState *cs);
48static void bch_l2l1(struct PStack *st, int pr, void *arg);
49static void bch_sched_event(struct BCState *bcs, int event);
50static void bch_empty_fifo(struct BCState *bcs, int count);
51static void bch_fill_fifo(struct BCState *bcs);
52static void bch_int(struct IsdnCardState *cs, u_char hscx);
53static void bch_mode(struct BCState *bcs, int mode, int bc);
54static void bch_close_state(struct BCState *bcs);
55static int bch_open_state(struct IsdnCardState *cs, struct BCState *bcs);
56static int bch_setstack(struct PStack *st, struct BCState *bcs);
57static void __devinit bch_init(struct IsdnCardState *cs, int hscx);
58static void __init clear_pending_ints(struct IsdnCardState *cs);
59
60//----------------------------------------------------------
61// Issue Layer 1 command to chip
62//----------------------------------------------------------
63static void
64ph_command(struct IsdnCardState *cs, unsigned int command)
65{
66 if (cs->debug &L1_DEB_ISAC)
67 debugl1(cs, "ph_command (%#x) in (%#x)", command,
68 cs->dc.isac.ph_state);
69 cs->writeisac(cs, IPACX_CIX0, (command << 4) | 0x0E);
70}
71
72//----------------------------------------------------------
73// Transceiver interrupt handler
74//----------------------------------------------------------
75static inline void
76cic_int(struct IsdnCardState *cs)
77{
78 u_char event;
79
80 event = cs->readisac(cs, IPACX_CIR0) >> 4;
81 if (cs->debug &L1_DEB_ISAC) debugl1(cs, "cic_int(event=%#x)", event);
82 cs->dc.isac.ph_state = event;
83 dch_sched_event(cs, D_L1STATECHANGE);
84}
85
86//==========================================================
87// D channel functions
88//==========================================================
89
90//----------------------------------------------------------
91// Command entry point
92//----------------------------------------------------------
93static void
94dch_l2l1(struct PStack *st, int pr, void *arg)
95{
96 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware;
97 struct sk_buff *skb = arg;
98 u_char cda1_cr, cda2_cr;
99
100 switch (pr) {
101 case (PH_DATA |REQUEST):
102 if (cs->debug &DEB_DLOG_HEX) LogFrame(cs, skb->data, skb->len);
103 if (cs->debug &DEB_DLOG_VERBOSE) dlogframe(cs, skb, 0);
104 if (cs->tx_skb) {
105 skb_queue_tail(&cs->sq, skb);
106#ifdef L2FRAME_DEBUG
107 if (cs->debug &L1_DEB_LAPD) Logl2Frame(cs, skb, "PH_DATA Queued", 0);
108#endif
109 } else {
110 cs->tx_skb = skb;
111 cs->tx_cnt = 0;
112#ifdef L2FRAME_DEBUG
113 if (cs->debug &L1_DEB_LAPD) Logl2Frame(cs, skb, "PH_DATA", 0);
114#endif
115 dch_fill_fifo(cs);
116 }
117 break;
118
119 case (PH_PULL |INDICATION):
120 if (cs->tx_skb) {
121 if (cs->debug & L1_DEB_WARN)
122 debugl1(cs, " l2l1 tx_skb exist this shouldn't happen");
123 skb_queue_tail(&cs->sq, skb);
124 break;
125 }
126 if (cs->debug & DEB_DLOG_HEX) LogFrame(cs, skb->data, skb->len);
127 if (cs->debug & DEB_DLOG_VERBOSE) dlogframe(cs, skb, 0);
128 cs->tx_skb = skb;
129 cs->tx_cnt = 0;
130#ifdef L2FRAME_DEBUG
131 if (cs->debug & L1_DEB_LAPD) Logl2Frame(cs, skb, "PH_DATA_PULLED", 0);
132#endif
133 dch_fill_fifo(cs);
134 break;
135
136 case (PH_PULL | REQUEST):
137#ifdef L2FRAME_DEBUG
138 if (cs->debug & L1_DEB_LAPD) debugl1(cs, "-> PH_REQUEST_PULL");
139#endif
140 if (!cs->tx_skb) {
141 clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
142 st->l2.l1l2(st, PH_PULL | CONFIRM, NULL);
143 } else
144 set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
145 break;
146
147 case (HW_RESET | REQUEST):
148 case (HW_ENABLE | REQUEST):
149 ph_command(cs, IPACX_CMD_TIM);
150 break;
151
152 case (HW_INFO3 | REQUEST):
153 ph_command(cs, IPACX_CMD_AR8);
154 break;
155
156 case (HW_TESTLOOP | REQUEST):
157 cs->writeisac(cs, IPACX_CDA_TSDP10, 0x80); // Timeslot 0 is B1
158 cs->writeisac(cs, IPACX_CDA_TSDP11, 0x81); // Timeslot 0 is B1
159 cda1_cr = cs->readisac(cs, IPACX_CDA1_CR);
160 cda2_cr = cs->readisac(cs, IPACX_CDA2_CR);
161 if ((long)arg &1) { // loop B1
162 cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr |0x0a);
163 }
164 else { // B1 off
165 cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr &~0x0a);
166 }
167 if ((long)arg &2) { // loop B2
168 cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr |0x14);
169 }
170 else { // B2 off
171 cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr &~0x14);
172 }
173 break;
174
175 case (HW_DEACTIVATE | RESPONSE):
176 skb_queue_purge(&cs->rq);
177 skb_queue_purge(&cs->sq);
178 if (cs->tx_skb) {
179 dev_kfree_skb_any(cs->tx_skb);
180 cs->tx_skb = NULL;
181 }
182 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
183 del_timer(&cs->dbusytimer);
184 break;
185
186 default:
187 if (cs->debug &L1_DEB_WARN) debugl1(cs, "dch_l2l1 unknown %04x", pr);
188 break;
189 }
190}
191
192//----------------------------------------------------------
193//----------------------------------------------------------
194static void
195dbusy_timer_handler(struct IsdnCardState *cs)
196{
197 struct PStack *st;
198 int rbchd, stard;
199
200 if (test_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {
201 rbchd = cs->readisac(cs, IPACX_RBCHD);
202 stard = cs->readisac(cs, IPACX_STARD);
203 if (cs->debug)
204 debugl1(cs, "D-Channel Busy RBCHD %02x STARD %02x", rbchd, stard);
205 if (!(stard &0x40)) { // D-Channel Busy
206 set_bit(FLG_L1_DBUSY, &cs->HW_Flags);
207 for (st = cs->stlist; st; st = st->next) {
208 st->l2.l1l2(st, PH_PAUSE | INDICATION, NULL); // flow control on
209 }
210 } else {
211 // seems we lost an interrupt; reset transceiver */
212 clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags);
213 if (cs->tx_skb) {
214 dev_kfree_skb_any(cs->tx_skb);
215 cs->tx_cnt = 0;
216 cs->tx_skb = NULL;
217 } else {
218 printk(KERN_WARNING "HiSax: ISAC D-Channel Busy no skb\n");
219 debugl1(cs, "D-Channel Busy no skb");
220 }
221 cs->writeisac(cs, IPACX_CMDRD, 0x01); // Tx reset, generates XPR
222 }
223 }
224}
225
226//----------------------------------------------------------
227// L1 state machine intermediate layer to isdnl1 module
228//----------------------------------------------------------
229static void
230ipacx_new_ph(struct IsdnCardState *cs)
231{
232 switch (cs->dc.isac.ph_state) {
233 case (IPACX_IND_RES):
234 ph_command(cs, IPACX_CMD_DI);
235 l1_msg(cs, HW_RESET | INDICATION, NULL);
236 break;
237
238 case (IPACX_IND_DC):
239 l1_msg(cs, HW_DEACTIVATE | CONFIRM, NULL);
240 break;
241
242 case (IPACX_IND_DR):
243 l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL);
244 break;
245
246 case (IPACX_IND_PU):
247 l1_msg(cs, HW_POWERUP | CONFIRM, NULL);
248 break;
249
250 case (IPACX_IND_RSY):
251 l1_msg(cs, HW_RSYNC | INDICATION, NULL);
252 break;
253
254 case (IPACX_IND_AR):
255 l1_msg(cs, HW_INFO2 | INDICATION, NULL);
256 break;
257
258 case (IPACX_IND_AI8):
259 l1_msg(cs, HW_INFO4_P8 | INDICATION, NULL);
260 break;
261
262 case (IPACX_IND_AI10):
263 l1_msg(cs, HW_INFO4_P10 | INDICATION, NULL);
264 break;
265
266 default:
267 break;
268 }
269}
270
271//----------------------------------------------------------
272// bottom half handler for D channel
273//----------------------------------------------------------
274static void
275dch_bh(void *data)
276{
277 struct IsdnCardState *cs = data;
278 struct PStack *st;
279
280 if (!cs) return;
281
282 if (test_and_clear_bit(D_CLEARBUSY, &cs->event)) {
283 if (cs->debug) debugl1(cs, "D-Channel Busy cleared");
284 for (st = cs->stlist; st; st = st->next) {
285 st->l2.l1l2(st, PH_PAUSE | CONFIRM, NULL);
286 }
287 }
288
289 if (test_and_clear_bit(D_RCVBUFREADY, &cs->event)) {
290 DChannel_proc_rcv(cs);
291 }
292
293 if (test_and_clear_bit(D_XMTBUFREADY, &cs->event)) {
294 DChannel_proc_xmt(cs);
295 }
296
297 if (test_and_clear_bit(D_L1STATECHANGE, &cs->event)) {
298 ipacx_new_ph(cs);
299 }
300}
301
302//----------------------------------------------------------
303// proceed with bottom half handler dch_bh()
304//----------------------------------------------------------
305static void
306dch_sched_event(struct IsdnCardState *cs, int event)
307{
308 set_bit(event, &cs->event);
309 schedule_work(&cs->work);
310}
311
312//----------------------------------------------------------
313// Fill buffer from receive FIFO
314//----------------------------------------------------------
315static void
316dch_empty_fifo(struct IsdnCardState *cs, int count)
317{
318 unsigned long flags;
319 u_char *ptr;
320
321 if ((cs->debug &L1_DEB_ISAC) && !(cs->debug &L1_DEB_ISAC_FIFO))
322 debugl1(cs, "dch_empty_fifo()");
323
324 // message too large, remove
325 if ((cs->rcvidx + count) >= MAX_DFRAME_LEN_L1) {
326 if (cs->debug &L1_DEB_WARN)
327 debugl1(cs, "dch_empty_fifo() incoming message too large");
328 cs->writeisac(cs, IPACX_CMDRD, 0x80); // RMC
329 cs->rcvidx = 0;
330 return;
331 }
332
333 ptr = cs->rcvbuf + cs->rcvidx;
334 cs->rcvidx += count;
335
336 spin_lock_irqsave(&ipacx_lock, flags);
337 cs->readisacfifo(cs, ptr, count);
338 cs->writeisac(cs, IPACX_CMDRD, 0x80); // RMC
339 spin_unlock_irqrestore(&ipacx_lock, flags);
340
341 if (cs->debug &L1_DEB_ISAC_FIFO) {
342 char *t = cs->dlog;
343
344 t += sprintf(t, "dch_empty_fifo() cnt %d", count);
345 QuickHex(t, ptr, count);
346 debugl1(cs, cs->dlog);
347 }
348}
349
350//----------------------------------------------------------
351// Fill transmit FIFO
352//----------------------------------------------------------
353static void
354dch_fill_fifo(struct IsdnCardState *cs)
355{
356 unsigned long flags;
357 int count;
358 u_char cmd, *ptr;
359
360 if ((cs->debug &L1_DEB_ISAC) && !(cs->debug &L1_DEB_ISAC_FIFO))
361 debugl1(cs, "dch_fill_fifo()");
362
363 if (!cs->tx_skb) return;
364 count = cs->tx_skb->len;
365 if (count <= 0) return;
366
367 if (count > D_FIFO_SIZE) {
368 count = D_FIFO_SIZE;
369 cmd = 0x08; // XTF
370 } else {
371 cmd = 0x0A; // XTF | XME
372 }
373
374 spin_lock_irqsave(&ipacx_lock, flags);
375 ptr = cs->tx_skb->data;
376 skb_pull(cs->tx_skb, count);
377 cs->tx_cnt += count;
378 cs->writeisacfifo(cs, ptr, count);
379 cs->writeisac(cs, IPACX_CMDRD, cmd);
380
381 // set timeout for transmission contol
382 if (test_and_set_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {
383 debugl1(cs, "dch_fill_fifo dbusytimer running");
384 del_timer(&cs->dbusytimer);
385 }
386 init_timer(&cs->dbusytimer);
387 cs->dbusytimer.expires = jiffies + ((DBUSY_TIMER_VALUE * HZ)/1000);
388 add_timer(&cs->dbusytimer);
389 spin_unlock_irqrestore(&ipacx_lock, flags);
390
391 if (cs->debug &L1_DEB_ISAC_FIFO) {
392 char *t = cs->dlog;
393
394 t += sprintf(t, "dch_fill_fifo() cnt %d", count);
395 QuickHex(t, ptr, count);
396 debugl1(cs, cs->dlog);
397 }
398}
399
400//----------------------------------------------------------
401// D channel interrupt handler
402//----------------------------------------------------------
403static inline void
404dch_int(struct IsdnCardState *cs)
405{
406 struct sk_buff *skb;
407 u_char istad, rstad;
408 unsigned long flags;
409 int count;
410
411 istad = cs->readisac(cs, IPACX_ISTAD);
412
413 if (istad &0x80) { // RME
414 rstad = cs->readisac(cs, IPACX_RSTAD);
415 if ((rstad &0xf0) != 0xa0) { // !(VFR && !RDO && CRC && !RAB)
416 if (!(rstad &0x80))
417 if (cs->debug &L1_DEB_WARN)
418 debugl1(cs, "dch_int(): invalid frame");
419 if ((rstad &0x40))
420 if (cs->debug &L1_DEB_WARN)
421 debugl1(cs, "dch_int(): RDO");
422 if (!(rstad &0x20))
423 if (cs->debug &L1_DEB_WARN)
424 debugl1(cs, "dch_int(): CRC error");
425 cs->writeisac(cs, IPACX_CMDRD, 0x80); // RMC
426 } else { // received frame ok
427 count = cs->readisac(cs, IPACX_RBCLD);
428 if (count) count--; // RSTAB is last byte
429 count &= D_FIFO_SIZE-1;
430 if (count == 0) count = D_FIFO_SIZE;
431 dch_empty_fifo(cs, count);
432 spin_lock_irqsave(&ipacx_lock, flags);
433 if ((count = cs->rcvidx) > 0) {
434 cs->rcvidx = 0;
435 if (!(skb = dev_alloc_skb(count)))
436 printk(KERN_WARNING "HiSax dch_int(): receive out of memory\n");
437 else {
438 memcpy(skb_put(skb, count), cs->rcvbuf, count);
439 skb_queue_tail(&cs->rq, skb);
440 }
441 }
442 spin_unlock_irqrestore(&ipacx_lock, flags);
443 }
444 cs->rcvidx = 0;
445 dch_sched_event(cs, D_RCVBUFREADY);
446 }
447
448 if (istad &0x40) { // RPF
449 dch_empty_fifo(cs, D_FIFO_SIZE);
450 }
451
452 if (istad &0x20) { // RFO
453 if (cs->debug &L1_DEB_WARN) debugl1(cs, "dch_int(): RFO");
454 cs->writeisac(cs, IPACX_CMDRD, 0x40); //RRES
455 }
456
457 if (istad &0x10) { // XPR
458 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
459 del_timer(&cs->dbusytimer);
460 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
461 dch_sched_event(cs, D_CLEARBUSY);
462 if (cs->tx_skb) {
463 if (cs->tx_skb->len) {
464 dch_fill_fifo(cs);
465 goto afterXPR;
466 }
467 else {
468 dev_kfree_skb_irq(cs->tx_skb);
469 cs->tx_skb = NULL;
470 cs->tx_cnt = 0;
471 }
472 }
473 if ((cs->tx_skb = skb_dequeue(&cs->sq))) {
474 cs->tx_cnt = 0;
475 dch_fill_fifo(cs);
476 }
477 else {
478 dch_sched_event(cs, D_XMTBUFREADY);
479 }
480 }
481 afterXPR:
482
483 if (istad &0x0C) { // XDU or XMR
484 if (cs->debug &L1_DEB_WARN) debugl1(cs, "dch_int(): XDU");
485 if (cs->tx_skb) {
486 skb_push(cs->tx_skb, cs->tx_cnt); // retransmit
487 cs->tx_cnt = 0;
488 dch_fill_fifo(cs);
489 } else {
490 printk(KERN_WARNING "HiSax: ISAC XDU no skb\n");
491 debugl1(cs, "ISAC XDU no skb");
492 }
493 }
494}
495
496//----------------------------------------------------------
497//----------------------------------------------------------
498static void __devinit
499dch_setstack(struct PStack *st, struct IsdnCardState *cs)
500{
501 st->l1.l1hw = dch_l2l1;
502}
503
504//----------------------------------------------------------
505//----------------------------------------------------------
506static void __devinit
507dch_init(struct IsdnCardState *cs)
508{
509 printk(KERN_INFO "HiSax: IPACX ISDN driver v0.1.0\n");
510
511 INIT_WORK(&cs->work, dch_bh, cs);
512 cs->setstack_d = dch_setstack;
513
514 cs->dbusytimer.function = (void *) dbusy_timer_handler;
515 cs->dbusytimer.data = (long) cs;
516 init_timer(&cs->dbusytimer);
517
518 cs->writeisac(cs, IPACX_TR_CONF0, 0x00); // clear LDD
519 cs->writeisac(cs, IPACX_TR_CONF2, 0x00); // enable transmitter
520 cs->writeisac(cs, IPACX_MODED, 0xC9); // transparent mode 0, RAC, stop/go
521 cs->writeisac(cs, IPACX_MON_CR, 0x00); // disable monitor channel
522}
523
524
525//==========================================================
526// B channel functions
527//==========================================================
528
529//----------------------------------------------------------
530// Entry point for commands
531//----------------------------------------------------------
532static void
533bch_l2l1(struct PStack *st, int pr, void *arg)
534{
535 struct sk_buff *skb = arg;
536 unsigned long flags;
537
538 switch (pr) {
539 case (PH_DATA | REQUEST):
540 spin_lock_irqsave(&ipacx_lock, flags);
541 if (st->l1.bcs->tx_skb) {
542 skb_queue_tail(&st->l1.bcs->squeue, skb);
543 spin_unlock_irqrestore(&ipacx_lock, flags);
544 } else {
545 st->l1.bcs->tx_skb = skb;
546 set_bit(BC_FLG_BUSY, &st->l1.bcs->Flag);
547 st->l1.bcs->hw.hscx.count = 0;
548 spin_unlock_irqrestore(&ipacx_lock, flags);
549 bch_fill_fifo(st->l1.bcs);
550 }
551 break;
552 case (PH_PULL | INDICATION):
553 if (st->l1.bcs->tx_skb) {
554 printk(KERN_WARNING "HiSax bch_l2l1(): this shouldn't happen\n");
555 break;
556 }
557 set_bit(BC_FLG_BUSY, &st->l1.bcs->Flag);
558 st->l1.bcs->tx_skb = skb;
559 st->l1.bcs->hw.hscx.count = 0;
560 bch_fill_fifo(st->l1.bcs);
561 break;
562 case (PH_PULL | REQUEST):
563 if (!st->l1.bcs->tx_skb) {
564 clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
565 st->l2.l1l2(st, PH_PULL | CONFIRM, NULL);
566 } else
567 set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
568 break;
569 case (PH_ACTIVATE | REQUEST):
570 set_bit(BC_FLG_ACTIV, &st->l1.bcs->Flag);
571 bch_mode(st->l1.bcs, st->l1.mode, st->l1.bc);
572 l1_msg_b(st, pr, arg);
573 break;
574 case (PH_DEACTIVATE | REQUEST):
575 l1_msg_b(st, pr, arg);
576 break;
577 case (PH_DEACTIVATE | CONFIRM):
578 clear_bit(BC_FLG_ACTIV, &st->l1.bcs->Flag);
579 clear_bit(BC_FLG_BUSY, &st->l1.bcs->Flag);
580 bch_mode(st->l1.bcs, 0, st->l1.bc);
581 st->l2.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL);
582 break;
583 }
584}
585
586//----------------------------------------------------------
587// proceed with bottom half handler BChannel_bh()
588//----------------------------------------------------------
589static void
590bch_sched_event(struct BCState *bcs, int event)
591{
592 bcs->event |= 1 << event;
593 schedule_work(&bcs->work);
594}
595
596//----------------------------------------------------------
597// Read B channel fifo to receive buffer
598//----------------------------------------------------------
599static void
600bch_empty_fifo(struct BCState *bcs, int count)
601{
602 u_char *ptr, hscx;
603 struct IsdnCardState *cs;
604 unsigned long flags;
605 int cnt;
606
607 cs = bcs->cs;
608 hscx = bcs->hw.hscx.hscx;
609 if ((cs->debug &L1_DEB_HSCX) && !(cs->debug &L1_DEB_HSCX_FIFO))
610 debugl1(cs, "bch_empty_fifo()");
611
612 // message too large, remove
613 if (bcs->hw.hscx.rcvidx + count > HSCX_BUFMAX) {
614 if (cs->debug &L1_DEB_WARN)
615 debugl1(cs, "bch_empty_fifo() incoming packet too large");
616 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x80); // RMC
617 bcs->hw.hscx.rcvidx = 0;
618 return;
619 }
620
621 // Read data uninterruptible
622 spin_lock_irqsave(&ipacx_lock, flags);
623 ptr = bcs->hw.hscx.rcvbuf + bcs->hw.hscx.rcvidx;
624 cnt = count;
625 while (cnt--) *ptr++ = cs->BC_Read_Reg(cs, hscx, IPACX_RFIFOB);
626 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x80); // RMC
627
628 ptr = bcs->hw.hscx.rcvbuf + bcs->hw.hscx.rcvidx;
629 bcs->hw.hscx.rcvidx += count;
630 spin_unlock_irqrestore(&ipacx_lock, flags);
631
632 if (cs->debug &L1_DEB_HSCX_FIFO) {
633 char *t = bcs->blog;
634
635 t += sprintf(t, "bch_empty_fifo() B-%d cnt %d", hscx, count);
636 QuickHex(t, ptr, count);
637 debugl1(cs, bcs->blog);
638 }
639}
640
641//----------------------------------------------------------
642// Fill buffer to transmit FIFO
643//----------------------------------------------------------
644static void
645bch_fill_fifo(struct BCState *bcs)
646{
647 struct IsdnCardState *cs;
648 int more, count, cnt;
649 u_char *ptr, *p, hscx;
650 unsigned long flags;
651
652 cs = bcs->cs;
653 if ((cs->debug &L1_DEB_HSCX) && !(cs->debug &L1_DEB_HSCX_FIFO))
654 debugl1(cs, "bch_fill_fifo()");
655
656 if (!bcs->tx_skb) return;
657 if (bcs->tx_skb->len <= 0) return;
658
659 hscx = bcs->hw.hscx.hscx;
660 more = (bcs->mode == L1_MODE_TRANS) ? 1 : 0;
661 if (bcs->tx_skb->len > B_FIFO_SIZE) {
662 more = 1;
663 count = B_FIFO_SIZE;
664 } else {
665 count = bcs->tx_skb->len;
666 }
667 cnt = count;
668
669 spin_lock_irqsave(&ipacx_lock, flags);
670 p = ptr = bcs->tx_skb->data;
671 skb_pull(bcs->tx_skb, count);
672 bcs->tx_cnt -= count;
673 bcs->hw.hscx.count += count;
674 while (cnt--) cs->BC_Write_Reg(cs, hscx, IPACX_XFIFOB, *p++);
675 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, (more ? 0x08 : 0x0a));
676 spin_unlock_irqrestore(&ipacx_lock, flags);
677
678 if (cs->debug &L1_DEB_HSCX_FIFO) {
679 char *t = bcs->blog;
680
681 t += sprintf(t, "chb_fill_fifo() B-%d cnt %d", hscx, count);
682 QuickHex(t, ptr, count);
683 debugl1(cs, bcs->blog);
684 }
685}
686
687//----------------------------------------------------------
688// B channel interrupt handler
689//----------------------------------------------------------
690static void
691bch_int(struct IsdnCardState *cs, u_char hscx)
692{
693 u_char istab;
694 struct BCState *bcs;
695 struct sk_buff *skb;
696 int count;
697 u_char rstab;
698
699 bcs = cs->bcs + hscx;
700 istab = cs->BC_Read_Reg(cs, hscx, IPACX_ISTAB);
701 if (!test_bit(BC_FLG_INIT, &bcs->Flag)) return;
702
703 if (istab &0x80) { // RME
704 rstab = cs->BC_Read_Reg(cs, hscx, IPACX_RSTAB);
705 if ((rstab &0xf0) != 0xa0) { // !(VFR && !RDO && CRC && !RAB)
706 if (!(rstab &0x80))
707 if (cs->debug &L1_DEB_WARN)
708 debugl1(cs, "bch_int() B-%d: invalid frame", hscx);
709 if ((rstab &0x40) && (bcs->mode != L1_MODE_NULL))
710 if (cs->debug &L1_DEB_WARN)
711 debugl1(cs, "bch_int() B-%d: RDO mode=%d", hscx, bcs->mode);
712 if (!(rstab &0x20))
713 if (cs->debug &L1_DEB_WARN)
714 debugl1(cs, "bch_int() B-%d: CRC error", hscx);
715 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x80); // RMC
716 }
717 else { // received frame ok
718 count = cs->BC_Read_Reg(cs, hscx, IPACX_RBCLB) &(B_FIFO_SIZE-1);
719 if (count == 0) count = B_FIFO_SIZE;
720 bch_empty_fifo(bcs, count);
721 if ((count = bcs->hw.hscx.rcvidx - 1) > 0) {
722 if (cs->debug &L1_DEB_HSCX_FIFO)
723 debugl1(cs, "bch_int Frame %d", count);
724 if (!(skb = dev_alloc_skb(count)))
725 printk(KERN_WARNING "HiSax bch_int(): receive frame out of memory\n");
726 else {
727 memcpy(skb_put(skb, count), bcs->hw.hscx.rcvbuf, count);
728 skb_queue_tail(&bcs->rqueue, skb);
729 }
730 }
731 }
732 bcs->hw.hscx.rcvidx = 0;
733 bch_sched_event(bcs, B_RCVBUFREADY);
734 }
735
736 if (istab &0x40) { // RPF
737 bch_empty_fifo(bcs, B_FIFO_SIZE);
738
739 if (bcs->mode == L1_MODE_TRANS) { // queue every chunk
740 // receive transparent audio data
741 if (!(skb = dev_alloc_skb(B_FIFO_SIZE)))
742 printk(KERN_WARNING "HiSax bch_int(): receive transparent out of memory\n");
743 else {
744 memcpy(skb_put(skb, B_FIFO_SIZE), bcs->hw.hscx.rcvbuf, B_FIFO_SIZE);
745 skb_queue_tail(&bcs->rqueue, skb);
746 }
747 bcs->hw.hscx.rcvidx = 0;
748 bch_sched_event(bcs, B_RCVBUFREADY);
749 }
750 }
751
752 if (istab &0x20) { // RFO
753 if (cs->debug &L1_DEB_WARN)
754 debugl1(cs, "bch_int() B-%d: RFO error", hscx);
755 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x40); // RRES
756 }
757
758 if (istab &0x10) { // XPR
759 if (bcs->tx_skb) {
760 if (bcs->tx_skb->len) {
761 bch_fill_fifo(bcs);
762 goto afterXPR;
763 }
764 skb_queue_tail(&bcs->cmpl_queue, bcs->tx_skb);
765 bch_sched_event(bcs, B_CMPLREADY);
766 bcs->hw.hscx.count = 0;
767 }
768 if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
769 bcs->hw.hscx.count = 0;
770 set_bit(BC_FLG_BUSY, &bcs->Flag);
771 bch_fill_fifo(bcs);
772 } else {
773 clear_bit(BC_FLG_BUSY, &bcs->Flag);
774 bch_sched_event(bcs, B_XMTBUFREADY);
775 }
776 }
777 afterXPR:
778
779 if (istab &0x04) { // XDU
780 if (bcs->mode == L1_MODE_TRANS) {
781 bch_fill_fifo(bcs);
782 }
783 else {
784 if (bcs->tx_skb) { // restart transmitting the whole frame
785 skb_push(bcs->tx_skb, bcs->hw.hscx.count);
786 bcs->tx_cnt += bcs->hw.hscx.count;
787 bcs->hw.hscx.count = 0;
788 }
789 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x01); // XRES
790 if (cs->debug &L1_DEB_WARN)
791 debugl1(cs, "bch_int() B-%d XDU error", hscx);
792 }
793 }
794}
795
796//----------------------------------------------------------
797//----------------------------------------------------------
798static void
799bch_mode(struct BCState *bcs, int mode, int bc)
800{
801 struct IsdnCardState *cs = bcs->cs;
802 int hscx = bcs->hw.hscx.hscx;
803
804 bc = bc ? 1 : 0; // in case bc is greater than 1
805 if (cs->debug & L1_DEB_HSCX)
806 debugl1(cs, "mode_bch() switch B-% mode %d chan %d", hscx, mode, bc);
807 bcs->mode = mode;
808 bcs->channel = bc;
809
810 // map controller to according timeslot
811 if (!hscx)
812 {
813 cs->writeisac(cs, IPACX_BCHA_TSDP_BC1, 0x80 | bc);
814 cs->writeisac(cs, IPACX_BCHA_CR, 0x88);
815 }
816 else
817 {
818 cs->writeisac(cs, IPACX_BCHB_TSDP_BC1, 0x80 | bc);
819 cs->writeisac(cs, IPACX_BCHB_CR, 0x88);
820 }
821
822 switch (mode) {
823 case (L1_MODE_NULL):
824 cs->BC_Write_Reg(cs, hscx, IPACX_MODEB, 0xC0); // rec off
825 cs->BC_Write_Reg(cs, hscx, IPACX_EXMB, 0x30); // std adj.
826 cs->BC_Write_Reg(cs, hscx, IPACX_MASKB, 0xFF); // ints off
827 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x41); // validate adjustments
828 break;
829 case (L1_MODE_TRANS):
830 cs->BC_Write_Reg(cs, hscx, IPACX_MODEB, 0x88); // ext transp mode
831 cs->BC_Write_Reg(cs, hscx, IPACX_EXMB, 0x00); // xxx00000
832 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x41); // validate adjustments
833 cs->BC_Write_Reg(cs, hscx, IPACX_MASKB, _MASKB_IMASK);
834 break;
835 case (L1_MODE_HDLC):
836 cs->BC_Write_Reg(cs, hscx, IPACX_MODEB, 0xC8); // transp mode 0
837 cs->BC_Write_Reg(cs, hscx, IPACX_EXMB, 0x01); // idle=hdlc flags crc enabled
838 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x41); // validate adjustments
839 cs->BC_Write_Reg(cs, hscx, IPACX_MASKB, _MASKB_IMASK);
840 break;
841 }
842}
843
844//----------------------------------------------------------
845//----------------------------------------------------------
846static void
847bch_close_state(struct BCState *bcs)
848{
849 bch_mode(bcs, 0, bcs->channel);
850 if (test_and_clear_bit(BC_FLG_INIT, &bcs->Flag)) {
851 if (bcs->hw.hscx.rcvbuf) {
852 kfree(bcs->hw.hscx.rcvbuf);
853 bcs->hw.hscx.rcvbuf = NULL;
854 }
855 if (bcs->blog) {
856 kfree(bcs->blog);
857 bcs->blog = NULL;
858 }
859 skb_queue_purge(&bcs->rqueue);
860 skb_queue_purge(&bcs->squeue);
861 if (bcs->tx_skb) {
862 dev_kfree_skb_any(bcs->tx_skb);
863 bcs->tx_skb = NULL;
864 clear_bit(BC_FLG_BUSY, &bcs->Flag);
865 }
866 }
867}
868
869//----------------------------------------------------------
870//----------------------------------------------------------
871static int
872bch_open_state(struct IsdnCardState *cs, struct BCState *bcs)
873{
874 if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
875 if (!(bcs->hw.hscx.rcvbuf = kmalloc(HSCX_BUFMAX, GFP_ATOMIC))) {
876 printk(KERN_WARNING
877 "HiSax open_bchstate(): No memory for hscx.rcvbuf\n");
878 clear_bit(BC_FLG_INIT, &bcs->Flag);
879 return (1);
880 }
881 if (!(bcs->blog = kmalloc(MAX_BLOG_SPACE, GFP_ATOMIC))) {
882 printk(KERN_WARNING
883 "HiSax open_bchstate: No memory for bcs->blog\n");
884 clear_bit(BC_FLG_INIT, &bcs->Flag);
885 kfree(bcs->hw.hscx.rcvbuf);
886 bcs->hw.hscx.rcvbuf = NULL;
887 return (2);
888 }
889 skb_queue_head_init(&bcs->rqueue);
890 skb_queue_head_init(&bcs->squeue);
891 }
892 bcs->tx_skb = NULL;
893 clear_bit(BC_FLG_BUSY, &bcs->Flag);
894 bcs->event = 0;
895 bcs->hw.hscx.rcvidx = 0;
896 bcs->tx_cnt = 0;
897 return (0);
898}
899
900//----------------------------------------------------------
901//----------------------------------------------------------
902static int
903bch_setstack(struct PStack *st, struct BCState *bcs)
904{
905 bcs->channel = st->l1.bc;
906 if (bch_open_state(st->l1.hardware, bcs)) return (-1);
907 st->l1.bcs = bcs;
908 st->l1.l2l1 = bch_l2l1;
909 setstack_manager(st);
910 bcs->st = st;
911 setstack_l1_B(st);
912 return (0);
913}
914
915//----------------------------------------------------------
916//----------------------------------------------------------
917static void __devinit
918bch_init(struct IsdnCardState *cs, int hscx)
919{
920 cs->bcs[hscx].BC_SetStack = bch_setstack;
921 cs->bcs[hscx].BC_Close = bch_close_state;
922 cs->bcs[hscx].hw.hscx.hscx = hscx;
923 cs->bcs[hscx].cs = cs;
924 bch_mode(cs->bcs + hscx, 0, hscx);
925}
926
927
928//==========================================================
929// Shared functions
930//==========================================================
931
932//----------------------------------------------------------
933// Main interrupt handler
934//----------------------------------------------------------
935void
936interrupt_ipacx(struct IsdnCardState *cs)
937{
938 u_char ista;
939
940 while ((ista = cs->readisac(cs, IPACX_ISTA))) {
941 if (ista &0x80) bch_int(cs, 0); // B channel interrupts
942 if (ista &0x40) bch_int(cs, 1);
943 if (ista &0x01) dch_int(cs); // D channel
944 if (ista &0x10) cic_int(cs); // Layer 1 state
945 }
946}
947
948//----------------------------------------------------------
949// Clears chip interrupt status
950//----------------------------------------------------------
951static void __init
952clear_pending_ints(struct IsdnCardState *cs)
953{
954 int ista;
955
956 // all interrupts off
957 cs->writeisac(cs, IPACX_MASK, 0xff);
958 cs->writeisac(cs, IPACX_MASKD, 0xff);
959 cs->BC_Write_Reg(cs, 0, IPACX_MASKB, 0xff);
960 cs->BC_Write_Reg(cs, 1, IPACX_MASKB, 0xff);
961
962 ista = cs->readisac(cs, IPACX_ISTA);
963 if (ista &0x80) cs->BC_Read_Reg(cs, 0, IPACX_ISTAB);
964 if (ista &0x40) cs->BC_Read_Reg(cs, 1, IPACX_ISTAB);
965 if (ista &0x10) cs->readisac(cs, IPACX_CIR0);
966 if (ista &0x01) cs->readisac(cs, IPACX_ISTAD);
967}
968
969//----------------------------------------------------------
970// Does chip configuration work
971// Work to do depends on bit mask in part
972//----------------------------------------------------------
973void __init
974init_ipacx(struct IsdnCardState *cs, int part)
975{
976 if (part &1) { // initialise chip
977 clear_pending_ints(cs);
978 bch_init(cs, 0);
979 bch_init(cs, 1);
980 dch_init(cs);
981 }
982 if (part &2) { // reenable all interrupts and start chip
983 cs->BC_Write_Reg(cs, 0, IPACX_MASKB, _MASKB_IMASK);
984 cs->BC_Write_Reg(cs, 1, IPACX_MASKB, _MASKB_IMASK);
985 cs->writeisac(cs, IPACX_MASKD, _MASKD_IMASK);
986 cs->writeisac(cs, IPACX_MASK, _MASK_IMASK); // global mask register
987
988 // reset HDLC Transmitters/receivers
989 cs->writeisac(cs, IPACX_CMDRD, 0x41);
990 cs->BC_Write_Reg(cs, 0, IPACX_CMDRB, 0x41);
991 cs->BC_Write_Reg(cs, 1, IPACX_CMDRB, 0x41);
992 ph_command(cs, IPACX_CMD_RES);
993 }
994}
995
996//----------------- end of file -----------------------
997
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