1 These Binutils patches are from the ath9k-htc-firmware repository
2 (commit f6af791348b68ceadab375e4ed0f7bcda86cb3c0).
4 Not applying the first patch (apparently) leads to miscompiled firmware,
5 and loading it fails with a "Target is unresponsive" message from the
8 From dbca73446265ce01b8e11462c3346b25953e3399 Mon Sep 17 00:00:00 2001
9 From: Sujith Manoharan <c_manoha@qca.qualcomm.com>
10 Date: Mon, 7 Jan 2013 15:59:53 +0530
11 Subject: [PATCH] binutils: AR9271/AR7010 config
13 Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
15 bfd/xtensa-modules.c | 27121 +++++++++++++---------------------------------
16 include/xtensa-config.h | 36 +-
17 2 files changed, 7663 insertions(+), 19494 deletions(-)
19 diff --git a/bfd/xtensa-modules.c b/bfd/xtensa-modules.c
20 index 3a79fcd..4704645 100644
21 --- a/bfd/xtensa-modules.c
22 +++ b/bfd/xtensa-modules.c
23 @@ -29,14 +29,6 @@ static xtensa_sysreg_internal sysregs[] = {
34 - { "PTEVADDR", 83, 0 },
38 @@ -47,29 +39,21 @@ static xtensa_sysreg_internal sysregs[] = {
41 { "CCOMPARE0", 240, 0 },
42 - { "CCOMPARE1", 241, 0 },
43 - { "CCOMPARE2", 242, 0 },
44 { "VECBASE", 231, 0 },
52 { "EXCSAVE1", 209, 0 },
53 { "EXCSAVE2", 210, 0 },
54 { "EXCSAVE3", 211, 0 },
55 { "EXCSAVE4", 212, 0 },
56 { "EXCSAVE5", 213, 0 },
57 - { "EXCSAVE6", 214, 0 },
58 - { "EXCSAVE7", 215, 0 },
65 { "EXCCAUSE", 232, 0 },
67 { "EXCVADDR", 238, 0 },
68 @@ -80,8 +64,6 @@ static xtensa_sysreg_internal sysregs[] = {
72 - { "MISC2", 246, 0 },
73 - { "MISC3", 247, 0 },
74 { "INTENABLE", 228, 0 },
75 { "DBREAKA0", 144, 0 },
76 { "DBREAKC0", 160, 0 },
77 @@ -92,19 +74,13 @@ static xtensa_sysreg_internal sysregs[] = {
78 { "IBREAKENABLE", 96, 0 },
79 { "ICOUNTLEVEL", 237, 0 },
80 { "DEBUGCAUSE", 233, 0 },
82 - { "ITLBCFG", 91, 0 },
83 - { "DTLBCFG", 92, 0 },
84 - { "CPENABLE", 224, 0 },
85 { "SCOMPARE1", 12, 0 },
86 - { "THREADPTR", 231, 1 },
89 + { "THREADPTR", 231, 1 }
92 -#define NUM_SYSREGS 74
93 -#define MAX_SPECIAL_REG 247
94 -#define MAX_USER_REG 233
95 +#define NUM_SYSREGS 50
96 +#define MAX_SPECIAL_REG 245
97 +#define MAX_USER_REG 231
100 /* Processor states. */
101 @@ -114,40 +90,33 @@ static xtensa_state_internal states[] = {
105 - { "INTERRUPT", 32, 0 },
106 + { "INTERRUPT", 19, 0 },
109 - { "VECBASE", 22, 0 },
110 + { "VECBASE", 21, 0 },
118 { "EXCSAVE1", 32, 0 },
119 { "EXCSAVE2", 32, 0 },
120 { "EXCSAVE3", 32, 0 },
121 { "EXCSAVE4", 32, 0 },
122 { "EXCSAVE5", 32, 0 },
123 - { "EXCSAVE6", 32, 0 },
124 - { "EXCSAVE7", 32, 0 },
135 { "EXCCAUSE", 6, 0 },
136 { "PSINTLEVEL", 4, 0 },
139 - { "PSRING", 2, 0 },
142 { "EXCVADDR", 32, 0 },
143 - { "WindowBase", 4, 0 },
144 - { "WindowStart", 16, 0 },
145 + { "WindowBase", 3, 0 },
146 + { "WindowStart", 8, 0 },
147 { "PSCALLINC", 2, 0 },
150 @@ -158,11 +127,8 @@ static xtensa_state_internal states[] = {
154 - { "MISC2", 32, 0 },
155 - { "MISC3", 32, 0 },
157 { "InOCDMode", 1, 0 },
158 - { "INTENABLE", 32, 0 },
159 + { "INTENABLE", 19, 0 },
160 { "DBREAKA0", 32, 0 },
161 { "DBREAKC0", 8, 0 },
162 { "DBREAKA1", 32, 0 },
163 @@ -174,34 +140,10 @@ static xtensa_state_internal states[] = {
164 { "DEBUGCAUSE", 6, 0 },
166 { "CCOMPARE0", 32, 0 },
167 - { "CCOMPARE1", 32, 0 },
168 - { "CCOMPARE2", 32, 0 },
172 - { "INSTPGSZID4", 2, 0 },
173 - { "DATAPGSZID4", 2, 0 },
174 - { "PTBASE", 10, 0 },
175 - { "CPENABLE", 1, 0 },
176 - { "SCOMPARE1", 32, 0 },
177 - { "RoundMode", 2, 0 },
178 - { "InvalidEnable", 1, 0 },
179 - { "DivZeroEnable", 1, 0 },
180 - { "OverflowEnable", 1, 0 },
181 - { "UnderflowEnable", 1, 0 },
182 - { "InexactEnable", 1, 0 },
183 - { "InvalidFlag", 1, 0 },
184 - { "DivZeroFlag", 1, 0 },
185 - { "OverflowFlag", 1, 0 },
186 - { "UnderflowFlag", 1, 0 },
187 - { "InexactFlag", 1, 0 },
188 - { "FPreserved20", 20, 0 },
189 - { "FPreserved20a", 20, 0 },
190 - { "FPreserved5", 5, 0 },
191 - { "FPreserved7", 7, 0 }
194 -#define NUM_STATES 89
195 + { "SCOMPARE1", 32, 0 }
198 +#define NUM_STATES 55
200 /* Macros for xtensa_state numbers (for use in iclasses because the
201 state numbers are not available when the iclass table is generated). */
202 @@ -219,82 +161,48 @@ static xtensa_state_internal states[] = {
203 #define STATE_EPC3 10
204 #define STATE_EPC4 11
205 #define STATE_EPC5 12
206 -#define STATE_EPC6 13
207 -#define STATE_EPC7 14
208 -#define STATE_EXCSAVE1 15
209 -#define STATE_EXCSAVE2 16
210 -#define STATE_EXCSAVE3 17
211 -#define STATE_EXCSAVE4 18
212 -#define STATE_EXCSAVE5 19
213 -#define STATE_EXCSAVE6 20
214 -#define STATE_EXCSAVE7 21
215 -#define STATE_EPS2 22
216 -#define STATE_EPS3 23
217 -#define STATE_EPS4 24
218 -#define STATE_EPS5 25
219 -#define STATE_EPS6 26
220 -#define STATE_EPS7 27
221 -#define STATE_EXCCAUSE 28
222 -#define STATE_PSINTLEVEL 29
223 -#define STATE_PSUM 30
224 -#define STATE_PSWOE 31
225 -#define STATE_PSRING 32
226 -#define STATE_PSEXCM 33
227 -#define STATE_DEPC 34
228 -#define STATE_EXCVADDR 35
229 -#define STATE_WindowBase 36
230 -#define STATE_WindowStart 37
231 -#define STATE_PSCALLINC 38
232 -#define STATE_PSOWB 39
233 -#define STATE_LBEG 40
234 -#define STATE_LEND 41
235 -#define STATE_SAR 42
236 -#define STATE_THREADPTR 43
237 -#define STATE_LITBADDR 44
238 -#define STATE_LITBEN 45
239 -#define STATE_MISC0 46
240 -#define STATE_MISC1 47
241 -#define STATE_MISC2 48
242 -#define STATE_MISC3 49
243 -#define STATE_ACC 50
244 -#define STATE_InOCDMode 51
245 -#define STATE_INTENABLE 52
246 -#define STATE_DBREAKA0 53
247 -#define STATE_DBREAKC0 54
248 -#define STATE_DBREAKA1 55
249 -#define STATE_DBREAKC1 56
250 -#define STATE_IBREAKA0 57
251 -#define STATE_IBREAKA1 58
252 -#define STATE_IBREAKENABLE 59
253 -#define STATE_ICOUNTLEVEL 60
254 -#define STATE_DEBUGCAUSE 61
255 -#define STATE_DBNUM 62
256 -#define STATE_CCOMPARE0 63
257 -#define STATE_CCOMPARE1 64
258 -#define STATE_CCOMPARE2 65
259 -#define STATE_ASID3 66
260 -#define STATE_ASID2 67
261 -#define STATE_ASID1 68
262 -#define STATE_INSTPGSZID4 69
263 -#define STATE_DATAPGSZID4 70
264 -#define STATE_PTBASE 71
265 -#define STATE_CPENABLE 72
266 -#define STATE_SCOMPARE1 73
267 -#define STATE_RoundMode 74
268 -#define STATE_InvalidEnable 75
269 -#define STATE_DivZeroEnable 76
270 -#define STATE_OverflowEnable 77
271 -#define STATE_UnderflowEnable 78
272 -#define STATE_InexactEnable 79
273 -#define STATE_InvalidFlag 80
274 -#define STATE_DivZeroFlag 81
275 -#define STATE_OverflowFlag 82
276 -#define STATE_UnderflowFlag 83
277 -#define STATE_InexactFlag 84
278 -#define STATE_FPreserved20 85
279 -#define STATE_FPreserved20a 86
280 -#define STATE_FPreserved5 87
281 -#define STATE_FPreserved7 88
282 +#define STATE_EXCSAVE1 13
283 +#define STATE_EXCSAVE2 14
284 +#define STATE_EXCSAVE3 15
285 +#define STATE_EXCSAVE4 16
286 +#define STATE_EXCSAVE5 17
287 +#define STATE_EPS2 18
288 +#define STATE_EPS3 19
289 +#define STATE_EPS4 20
290 +#define STATE_EPS5 21
291 +#define STATE_EXCCAUSE 22
292 +#define STATE_PSINTLEVEL 23
293 +#define STATE_PSUM 24
294 +#define STATE_PSWOE 25
295 +#define STATE_PSEXCM 26
296 +#define STATE_DEPC 27
297 +#define STATE_EXCVADDR 28
298 +#define STATE_WindowBase 29
299 +#define STATE_WindowStart 30
300 +#define STATE_PSCALLINC 31
301 +#define STATE_PSOWB 32
302 +#define STATE_LBEG 33
303 +#define STATE_LEND 34
304 +#define STATE_SAR 35
305 +#define STATE_THREADPTR 36
306 +#define STATE_LITBADDR 37
307 +#define STATE_LITBEN 38
308 +#define STATE_MISC0 39
309 +#define STATE_MISC1 40
310 +#define STATE_InOCDMode 41
311 +#define STATE_INTENABLE 42
312 +#define STATE_DBREAKA0 43
313 +#define STATE_DBREAKC0 44
314 +#define STATE_DBREAKA1 45
315 +#define STATE_DBREAKC1 46
316 +#define STATE_IBREAKA0 47
317 +#define STATE_IBREAKA1 48
318 +#define STATE_IBREAKENABLE 49
319 +#define STATE_ICOUNTLEVEL 50
320 +#define STATE_DEBUGCAUSE 51
321 +#define STATE_DBNUM 52
322 +#define STATE_CCOMPARE0 53
323 +#define STATE_SCOMPARE1 54
326 /* Field definitions. */
327 @@ -303,7 +211,7 @@ static unsigned
328 Field_t_Slot_inst_get (const xtensa_insnbuf insn)
331 - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
332 + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
336 @@ -312,14 +220,14 @@ Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
339 tie_t = (val << 28) >> 28;
340 - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
341 + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
345 Field_t_Slot_inst16a_get (const xtensa_insnbuf insn)
348 - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
349 + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
353 @@ -328,14 +236,14 @@ Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
356 tie_t = (val << 28) >> 28;
357 - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
358 + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
362 Field_t_Slot_inst16b_get (const xtensa_insnbuf insn)
365 - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
366 + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
370 @@ -344,20491 +252,8868 @@ Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
373 tie_t = (val << 28) >> 28;
374 - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
375 + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
379 -Field_t_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
380 +Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn)
383 - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
384 + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
389 -Field_t_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
390 +Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
393 - tie_t = (val << 28) >> 28;
394 - insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
395 + tie_t = (val << 31) >> 31;
396 + insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
400 -Field_t_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
401 +Field_bbi_Slot_inst_get (const xtensa_insnbuf insn)
404 - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
405 + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
406 + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
411 -Field_t_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
412 +Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
415 tie_t = (val << 28) >> 28;
416 - insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
417 + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
418 + tie_t = (val << 27) >> 31;
419 + insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
423 -Field_t_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
424 +Field_imm12_Slot_inst_get (const xtensa_insnbuf insn)
427 - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
428 + tie_t = (tie_t << 12) | ((insn[0] << 20) >> 20);
433 -Field_t_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
434 +Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
437 - tie_t = (val << 28) >> 28;
438 - insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
439 + tie_t = (val << 20) >> 20;
440 + insn[0] = (insn[0] & ~0xfff) | (tie_t << 0);
444 -Field_t_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
445 +Field_imm8_Slot_inst_get (const xtensa_insnbuf insn)
448 - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
449 + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24);
454 -Field_t_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
455 +Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
458 - tie_t = (val << 28) >> 28;
459 - insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
460 + tie_t = (val << 24) >> 24;
461 + insn[0] = (insn[0] & ~0xff) | (tie_t << 0);
465 -Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn)
466 +Field_s_Slot_inst_get (const xtensa_insnbuf insn)
469 - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
470 + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
475 -Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
476 +Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
479 - tie_t = (val << 31) >> 31;
480 - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
481 + tie_t = (val << 28) >> 28;
482 + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
486 -Field_bbi_Slot_inst_get (const xtensa_insnbuf insn)
487 +Field_s_Slot_inst16a_get (const xtensa_insnbuf insn)
490 - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
491 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
496 -Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
497 +Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
500 tie_t = (val << 28) >> 28;
501 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
502 - tie_t = (val << 27) >> 31;
503 - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
507 -Field_bbi_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
508 +Field_s_Slot_inst16b_get (const xtensa_insnbuf insn)
511 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
512 - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
513 + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
518 -Field_bbi_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
519 +Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
522 tie_t = (val << 28) >> 28;
523 - insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
524 - tie_t = (val << 27) >> 31;
525 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
526 + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
530 -Field_imm12_Slot_inst_get (const xtensa_insnbuf insn)
531 +Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn)
534 - tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20);
535 + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
536 + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24);
541 -Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
542 +Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
545 - tie_t = (val << 20) >> 20;
546 - insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12);
547 + tie_t = (val << 24) >> 24;
548 + insn[0] = (insn[0] & ~0xff) | (tie_t << 0);
549 + tie_t = (val << 20) >> 28;
550 + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
554 -Field_imm8_Slot_inst_get (const xtensa_insnbuf insn)
555 +Field_imm16_Slot_inst_get (const xtensa_insnbuf insn)
558 - tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
559 + tie_t = (tie_t << 16) | ((insn[0] << 16) >> 16);
564 -Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
565 +Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
568 - tie_t = (val << 24) >> 24;
569 - insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
570 + tie_t = (val << 16) >> 16;
571 + insn[0] = (insn[0] & ~0xffff) | (tie_t << 0);
575 -Field_imm8_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
576 +Field_m_Slot_inst_get (const xtensa_insnbuf insn)
579 - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
580 + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30);
585 -Field_imm8_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
586 +Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
589 - tie_t = (val << 24) >> 24;
590 - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
591 + tie_t = (val << 30) >> 30;
592 + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16);
596 -Field_imm8_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
597 +Field_n_Slot_inst_get (const xtensa_insnbuf insn)
600 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
601 - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
602 + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30);
607 -Field_imm8_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
608 +Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
611 - tie_t = (val << 28) >> 28;
612 - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
613 - tie_t = (val << 24) >> 28;
614 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
615 + tie_t = (val << 30) >> 30;
616 + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18);
620 -Field_s_Slot_inst_get (const xtensa_insnbuf insn)
621 +Field_offset_Slot_inst_get (const xtensa_insnbuf insn)
624 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
625 + tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14);
630 -Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
631 +Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
634 - tie_t = (val << 28) >> 28;
635 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
636 + tie_t = (val << 14) >> 14;
637 + insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0);
641 -Field_s_Slot_inst16a_get (const xtensa_insnbuf insn)
642 +Field_op0_Slot_inst_get (const xtensa_insnbuf insn)
645 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
646 + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
651 -Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
652 +Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
655 tie_t = (val << 28) >> 28;
656 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
657 + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
661 -Field_s_Slot_inst16b_get (const xtensa_insnbuf insn)
662 +Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn)
665 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
666 + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
671 -Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
672 +Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
675 tie_t = (val << 28) >> 28;
676 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
677 + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
681 -Field_s_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
682 +Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn)
685 - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
686 + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
691 -Field_s_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
692 +Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
695 tie_t = (val << 28) >> 28;
696 - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
697 + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
701 -Field_s_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
702 +Field_op1_Slot_inst_get (const xtensa_insnbuf insn)
705 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
706 + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
711 -Field_s_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
712 +Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
715 tie_t = (val << 28) >> 28;
716 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
717 + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
721 -Field_s_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
722 +Field_op2_Slot_inst_get (const xtensa_insnbuf insn)
725 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
726 + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
731 -Field_s_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
732 +Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
735 tie_t = (val << 28) >> 28;
736 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
737 + insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
741 -Field_s_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
742 +Field_r_Slot_inst_get (const xtensa_insnbuf insn)
745 - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
746 + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
751 -Field_s_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
752 +Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
755 tie_t = (val << 28) >> 28;
756 - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
757 + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
761 -Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn)
762 +Field_r_Slot_inst16a_get (const xtensa_insnbuf insn)
765 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
766 - tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
767 + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
772 -Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
773 +Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
776 - tie_t = (val << 24) >> 24;
777 - insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
778 - tie_t = (val << 20) >> 28;
779 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
780 + tie_t = (val << 28) >> 28;
781 + insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
785 -Field_imm12b_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
786 +Field_r_Slot_inst16b_get (const xtensa_insnbuf insn)
789 - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
790 - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
791 + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
796 -Field_imm12b_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
797 +Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
800 - tie_t = (val << 24) >> 24;
801 - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
802 - tie_t = (val << 20) >> 28;
803 - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
804 + tie_t = (val << 28) >> 28;
805 + insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
809 -Field_imm12b_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
810 +Field_sa4_Slot_inst_get (const xtensa_insnbuf insn)
813 - tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20);
814 + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
819 -Field_imm12b_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
820 +Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
823 - tie_t = (val << 20) >> 20;
824 - insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4);
825 + tie_t = (val << 31) >> 31;
826 + insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
830 -Field_imm16_Slot_inst_get (const xtensa_insnbuf insn)
831 +Field_sae4_Slot_inst_get (const xtensa_insnbuf insn)
834 - tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16);
835 + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
840 -Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
841 +Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
844 - tie_t = (val << 16) >> 16;
845 - insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8);
846 + tie_t = (val << 31) >> 31;
847 + insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
851 -Field_imm16_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
852 +Field_sae_Slot_inst_get (const xtensa_insnbuf insn)
855 - tie_t = (tie_t << 16) | ((insn[0] << 12) >> 16);
856 + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
857 + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
862 -Field_imm16_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
863 +Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
866 - tie_t = (val << 16) >> 16;
867 - insn[0] = (insn[0] & ~0xffff0) | (tie_t << 4);
868 + tie_t = (val << 28) >> 28;
869 + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
870 + tie_t = (val << 27) >> 31;
871 + insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
875 -Field_m_Slot_inst_get (const xtensa_insnbuf insn)
876 +Field_sal_Slot_inst_get (const xtensa_insnbuf insn)
879 - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
880 + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
881 + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
886 -Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
887 +Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
890 - tie_t = (val << 30) >> 30;
891 - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
892 + tie_t = (val << 28) >> 28;
893 + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
894 + tie_t = (val << 27) >> 31;
895 + insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
899 -Field_m_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
900 +Field_sargt_Slot_inst_get (const xtensa_insnbuf insn)
903 - tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30);
904 + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
905 + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
910 -Field_m_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
911 +Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
914 - tie_t = (val << 30) >> 30;
915 - insn[0] = (insn[0] & ~0xc) | (tie_t << 2);
916 + tie_t = (val << 28) >> 28;
917 + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
918 + tie_t = (val << 27) >> 31;
919 + insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
923 -Field_n_Slot_inst_get (const xtensa_insnbuf insn)
924 +Field_sas4_Slot_inst_get (const xtensa_insnbuf insn)
927 - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
928 + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
933 -Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
934 +Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
937 - tie_t = (val << 30) >> 30;
938 - insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
939 + tie_t = (val << 31) >> 31;
940 + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
944 -Field_n_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
945 +Field_sas_Slot_inst_get (const xtensa_insnbuf insn)
948 - tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30);
949 + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
950 + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
955 -Field_n_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
956 +Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
959 - tie_t = (val << 30) >> 30;
960 - insn[0] = (insn[0] & ~0x3) | (tie_t << 0);
961 + tie_t = (val << 28) >> 28;
962 + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
963 + tie_t = (val << 27) >> 31;
964 + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
968 -Field_offset_Slot_inst_get (const xtensa_insnbuf insn)
969 +Field_sr_Slot_inst_get (const xtensa_insnbuf insn)
972 - tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
973 + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
974 + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
979 -Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
980 +Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
983 - tie_t = (val << 14) >> 14;
984 - insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
985 + tie_t = (val << 28) >> 28;
986 + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
987 + tie_t = (val << 24) >> 28;
988 + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
992 -Field_offset_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
993 +Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn)
996 - tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14);
997 + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
998 + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1003 -Field_offset_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
1004 +Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1007 - tie_t = (val << 14) >> 14;
1008 - insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0);
1009 + tie_t = (val << 28) >> 28;
1010 + insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1011 + tie_t = (val << 24) >> 28;
1012 + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1016 -Field_op0_Slot_inst_get (const xtensa_insnbuf insn)
1017 +Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn)
1020 + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1021 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1026 -Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1027 +Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1030 tie_t = (val << 28) >> 28;
1031 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1032 + tie_t = (val << 24) >> 28;
1033 + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1037 -Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn)
1038 +Field_st_Slot_inst_get (const xtensa_insnbuf insn)
1041 - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1042 + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1043 + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
1048 -Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1049 +Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1052 tie_t = (val << 28) >> 28;
1053 - insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1054 + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
1055 + tie_t = (val << 24) >> 28;
1056 + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1060 -Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn)
1061 +Field_st_Slot_inst16a_get (const xtensa_insnbuf insn)
1064 - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1065 + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1066 + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1071 -Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1072 +Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1075 tie_t = (val << 28) >> 28;
1076 - insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1077 + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1078 + tie_t = (val << 24) >> 28;
1079 + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1083 -Field_op1_Slot_inst_get (const xtensa_insnbuf insn)
1084 +Field_st_Slot_inst16b_get (const xtensa_insnbuf insn)
1087 - tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
1088 + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1089 + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1094 -Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1095 +Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1098 tie_t = (val << 28) >> 28;
1099 - insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
1100 + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1101 + tie_t = (val << 24) >> 28;
1102 + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1106 -Field_op1_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
1107 +Field_thi3_Slot_inst_get (const xtensa_insnbuf insn)
1110 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1111 + tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29);
1116 -Field_op1_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
1117 +Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1120 - tie_t = (val << 28) >> 28;
1121 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1122 + tie_t = (val << 29) >> 29;
1123 + insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
1127 -Field_op2_Slot_inst_get (const xtensa_insnbuf insn)
1128 +Field_imm4_Slot_inst_get (const xtensa_insnbuf insn)
1131 - tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
1132 + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1137 -Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1138 +Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1141 tie_t = (val << 28) >> 28;
1142 - insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
1143 + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1147 -Field_op2_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
1148 +Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn)
1151 - tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
1152 + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1157 -Field_op2_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
1158 +Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1161 tie_t = (val << 28) >> 28;
1162 - insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
1163 + insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1167 -Field_op2_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
1168 +Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn)
1171 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1172 + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1177 -Field_op2_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
1178 +Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1181 tie_t = (val << 28) >> 28;
1182 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1183 + insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1187 -Field_r_Slot_inst_get (const xtensa_insnbuf insn)
1188 +Field_mn_Slot_inst_get (const xtensa_insnbuf insn)
1191 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1192 + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30);
1193 + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30);
1198 -Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1199 +Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1202 - tie_t = (val << 28) >> 28;
1203 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1204 + tie_t = (val << 30) >> 30;
1205 + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16);
1206 + tie_t = (val << 28) >> 30;
1207 + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18);
1211 -Field_r_Slot_inst16a_get (const xtensa_insnbuf insn)
1212 +Field_i_Slot_inst16a_get (const xtensa_insnbuf insn)
1215 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1216 + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
1221 -Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1222 +Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1225 - tie_t = (val << 28) >> 28;
1226 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1227 + tie_t = (val << 31) >> 31;
1228 + insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
1232 -Field_r_Slot_inst16b_get (const xtensa_insnbuf insn)
1233 +Field_i_Slot_inst16b_get (const xtensa_insnbuf insn)
1236 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1237 + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
1242 -Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1243 +Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1246 - tie_t = (val << 28) >> 28;
1247 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1248 + tie_t = (val << 31) >> 31;
1249 + insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
1253 -Field_r_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
1254 +Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn)
1257 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1258 + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1263 -Field_r_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
1264 +Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1267 tie_t = (val << 28) >> 28;
1268 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1269 + insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1273 -Field_r_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
1274 +Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn)
1277 - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1278 + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1283 -Field_r_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
1284 +Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1287 tie_t = (val << 28) >> 28;
1288 - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1289 + insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1293 -Field_r_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
1294 +Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn)
1297 - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1298 + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
1303 -Field_r_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
1304 +Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1307 - tie_t = (val << 28) >> 28;
1308 - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1309 + tie_t = (val << 30) >> 30;
1310 + insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
1314 -Field_r_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
1315 +Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn)
1318 - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1319 + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
1324 -Field_r_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
1325 +Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1328 - tie_t = (val << 28) >> 28;
1329 - insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1330 + tie_t = (val << 30) >> 30;
1331 + insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
1335 -Field_sa4_Slot_inst_get (const xtensa_insnbuf insn)
1336 +Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn)
1339 - tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
1340 + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1345 -Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1346 +Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1349 - tie_t = (val << 31) >> 31;
1350 - insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
1351 + tie_t = (val << 28) >> 28;
1352 + insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1356 -Field_sae4_Slot_inst_get (const xtensa_insnbuf insn)
1357 +Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn)
1360 - tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
1361 + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1366 -Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1367 +Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1370 - tie_t = (val << 31) >> 31;
1371 - insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
1372 + tie_t = (val << 28) >> 28;
1373 + insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1377 -Field_sae4_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
1378 +Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn)
1381 - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
1382 + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
1387 -Field_sae4_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
1388 +Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1391 - tie_t = (val << 31) >> 31;
1392 - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
1393 + tie_t = (val << 29) >> 29;
1394 + insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
1398 -Field_sae_Slot_inst_get (const xtensa_insnbuf insn)
1399 +Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn)
1402 - tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
1403 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1404 + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
1409 -Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1410 +Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1413 - tie_t = (val << 28) >> 28;
1414 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1415 - tie_t = (val << 27) >> 31;
1416 - insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
1417 + tie_t = (val << 29) >> 29;
1418 + insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
1422 -Field_sae_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
1423 +Field_z_Slot_inst16a_get (const xtensa_insnbuf insn)
1426 - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
1427 - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1428 + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31);
1433 -Field_sae_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
1434 +Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1437 - tie_t = (val << 28) >> 28;
1438 - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1439 - tie_t = (val << 27) >> 31;
1440 - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
1441 + tie_t = (val << 31) >> 31;
1442 + insn[0] = (insn[0] & ~0x400) | (tie_t << 10);
1446 -Field_sae_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
1447 +Field_z_Slot_inst16b_get (const xtensa_insnbuf insn)
1450 - tie_t = (tie_t << 5) | ((insn[0] << 15) >> 27);
1451 + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31);
1456 -Field_sae_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
1457 +Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1460 - tie_t = (val << 27) >> 27;
1461 - insn[0] = (insn[0] & ~0x1f000) | (tie_t << 12);
1462 + tie_t = (val << 31) >> 31;
1463 + insn[0] = (insn[0] & ~0x400) | (tie_t << 10);
1467 -Field_sal_Slot_inst_get (const xtensa_insnbuf insn)
1468 +Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn)
1471 - tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
1472 - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1473 + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
1474 + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1479 -Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1480 +Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1483 tie_t = (val << 28) >> 28;
1484 - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1485 - tie_t = (val << 27) >> 31;
1486 - insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
1487 + insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1488 + tie_t = (val << 26) >> 30;
1489 + insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
1493 -Field_sal_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
1494 +Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn)
1497 - tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
1498 + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
1499 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1504 -Field_sal_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
1505 +Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1508 tie_t = (val << 28) >> 28;
1509 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1510 - tie_t = (val << 27) >> 31;
1511 - insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
1512 + tie_t = (val << 26) >> 30;
1513 + insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
1517 -Field_sal_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
1518 +Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn)
1521 - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
1522 + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
1523 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1528 -Field_sal_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
1529 +Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1532 tie_t = (val << 28) >> 28;
1533 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1534 - tie_t = (val << 27) >> 31;
1535 - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
1536 + tie_t = (val << 25) >> 29;
1537 + insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
1541 -Field_sargt_Slot_inst_get (const xtensa_insnbuf insn)
1542 +Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn)
1545 - tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
1546 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1547 + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
1548 + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1553 -Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1554 +Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1557 tie_t = (val << 28) >> 28;
1558 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1559 - tie_t = (val << 27) >> 31;
1560 - insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
1561 + insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1562 + tie_t = (val << 25) >> 29;
1563 + insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
1567 -Field_sargt_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
1568 +Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn)
1571 - tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
1572 - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1573 + tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17);
1578 -Field_sargt_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
1579 +Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1582 - tie_t = (val << 28) >> 28;
1583 - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1584 - tie_t = (val << 27) >> 31;
1585 - insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
1586 + tie_t = (val << 17) >> 17;
1587 + insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9);
1591 -Field_sargt_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
1592 +Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn)
1595 - tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27);
1596 + tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
1601 -Field_sargt_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
1602 +Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1605 - tie_t = (val << 27) >> 27;
1606 - insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8);
1607 + tie_t = (val << 14) >> 14;
1608 + insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
1612 -Field_sargt_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
1614 +Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED,
1615 + uint32 val ATTRIBUTE_UNUSED)
1617 - unsigned tie_t = 0;
1618 - tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27);
1624 -Field_sargt_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
1626 +Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1629 - tie_t = (val << 27) >> 27;
1630 - insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8);
1635 -Field_sas4_Slot_inst_get (const xtensa_insnbuf insn)
1636 +Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1638 - unsigned tie_t = 0;
1639 - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
1645 -Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1647 +Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1650 - tie_t = (val << 31) >> 31;
1651 - insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
1656 -Field_sas_Slot_inst_get (const xtensa_insnbuf insn)
1657 +Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1659 - unsigned tie_t = 0;
1660 - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
1661 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1667 -Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1669 +/* Functional units. */
1671 +static xtensa_funcUnit_internal funcUnits[] = {
1676 +/* Register files. */
1678 +static xtensa_regfile_internal regfiles[] = {
1679 + { "AR", "a", 0, 32, 32 }
1685 +static xtensa_interface_internal interfaces[] = {
1690 +/* Constant tables. */
1692 +/* constant table ai4c */
1693 +static const unsigned CONST_TBL_ai4c_0[] = {
1713 +/* constant table b4c */
1714 +static const unsigned CONST_TBL_b4c_0[] = {
1734 +/* constant table b4cu */
1735 +static const unsigned CONST_TBL_b4cu_0[] = {
1756 +/* Instruction operands. */
1759 +Operand_soffsetx4_decode (uint32 *valp)
1762 - tie_t = (val << 28) >> 28;
1763 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1764 - tie_t = (val << 27) >> 31;
1765 - insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
1766 + unsigned soffsetx4_0, offset_0;
1767 + offset_0 = *valp & 0x3ffff;
1768 + soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2);
1769 + *valp = soffsetx4_0;
1774 -Field_sas_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
1776 +Operand_soffsetx4_encode (uint32 *valp)
1778 - unsigned tie_t = 0;
1779 - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
1780 - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1782 + unsigned offset_0, soffsetx4_0;
1783 + soffsetx4_0 = *valp;
1784 + offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff;
1790 -Field_sas_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
1792 +Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
1795 - tie_t = (val << 28) >> 28;
1796 - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1797 - tie_t = (val << 27) >> 31;
1798 - insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
1799 + *valp -= (pc & ~0x3);
1804 -Field_sr_Slot_inst_get (const xtensa_insnbuf insn)
1806 +Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
1808 - unsigned tie_t = 0;
1809 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1810 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1812 + *valp += (pc & ~0x3);
1817 -Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1819 +Operand_uimm12x8_decode (uint32 *valp)
1822 - tie_t = (val << 28) >> 28;
1823 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1824 - tie_t = (val << 24) >> 28;
1825 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1826 + unsigned uimm12x8_0, imm12_0;
1827 + imm12_0 = *valp & 0xfff;
1828 + uimm12x8_0 = imm12_0 << 3;
1829 + *valp = uimm12x8_0;
1834 -Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn)
1836 +Operand_uimm12x8_encode (uint32 *valp)
1838 - unsigned tie_t = 0;
1839 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1840 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1842 + unsigned imm12_0, uimm12x8_0;
1843 + uimm12x8_0 = *valp;
1844 + imm12_0 = ((uimm12x8_0 >> 3) & 0xfff);
1850 -Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1852 +Operand_simm4_decode (uint32 *valp)
1855 - tie_t = (val << 28) >> 28;
1856 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1857 - tie_t = (val << 24) >> 28;
1858 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1859 + unsigned simm4_0, mn_0;
1860 + mn_0 = *valp & 0xf;
1861 + simm4_0 = ((int) mn_0 << 28) >> 28;
1867 -Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn)
1869 +Operand_simm4_encode (uint32 *valp)
1871 - unsigned tie_t = 0;
1872 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1873 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1875 + unsigned mn_0, simm4_0;
1877 + mn_0 = (simm4_0 & 0xf);
1883 -Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1885 +Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED)
1888 - tie_t = (val << 28) >> 28;
1889 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1890 - tie_t = (val << 24) >> 28;
1891 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1896 -Field_st_Slot_inst_get (const xtensa_insnbuf insn)
1898 +Operand_arr_encode (uint32 *valp)
1900 - unsigned tie_t = 0;
1901 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1902 - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1905 + error = (*valp & ~0xf) != 0;
1910 -Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1912 +Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED)
1915 - tie_t = (val << 28) >> 28;
1916 - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1917 - tie_t = (val << 24) >> 28;
1918 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1923 -Field_st_Slot_inst16a_get (const xtensa_insnbuf insn)
1925 +Operand_ars_encode (uint32 *valp)
1927 - unsigned tie_t = 0;
1928 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1929 - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1932 + error = (*valp & ~0xf) != 0;
1937 -Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1939 +Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED)
1942 - tie_t = (val << 28) >> 28;
1943 - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1944 - tie_t = (val << 24) >> 28;
1945 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1950 -Field_st_Slot_inst16b_get (const xtensa_insnbuf insn)
1952 +Operand_art_encode (uint32 *valp)
1954 - unsigned tie_t = 0;
1955 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1956 - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1959 + error = (*valp & ~0xf) != 0;
1964 -Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1967 - tie_t = (val << 28) >> 28;
1968 - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1969 - tie_t = (val << 24) >> 28;
1970 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1974 -Field_thi3_Slot_inst_get (const xtensa_insnbuf insn)
1976 +Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED)
1978 - unsigned tie_t = 0;
1979 - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
1985 -Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1987 +Operand_ar0_encode (uint32 *valp)
1990 - tie_t = (val << 29) >> 29;
1991 - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
1993 + error = (*valp & ~0x1f) != 0;
1998 -Field_thi3_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
2000 +Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED)
2002 - unsigned tie_t = 0;
2003 - tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29);
2009 -Field_thi3_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
2011 +Operand_ar4_encode (uint32 *valp)
2014 - tie_t = (val << 29) >> 29;
2015 - insn[0] = (insn[0] & ~0xe) | (tie_t << 1);
2017 + error = (*valp & ~0x1f) != 0;
2022 -Field_imm4_Slot_inst_get (const xtensa_insnbuf insn)
2024 +Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED)
2026 - unsigned tie_t = 0;
2027 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
2033 -Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2035 +Operand_ar8_encode (uint32 *valp)
2038 - tie_t = (val << 28) >> 28;
2039 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
2041 + error = (*valp & ~0x1f) != 0;
2046 -Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn)
2048 +Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED)
2050 - unsigned tie_t = 0;
2051 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
2057 -Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2059 +Operand_ar12_encode (uint32 *valp)
2062 - tie_t = (val << 28) >> 28;
2063 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
2065 + error = (*valp & ~0x1f) != 0;
2070 -Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn)
2072 +Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED)
2074 - unsigned tie_t = 0;
2075 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
2081 -Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2083 +Operand_ars_entry_encode (uint32 *valp)
2086 - tie_t = (val << 28) >> 28;
2087 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
2089 + error = (*valp & ~0x1f) != 0;
2094 -Field_mn_Slot_inst_get (const xtensa_insnbuf insn)
2096 +Operand_immrx4_decode (uint32 *valp)
2098 - unsigned tie_t = 0;
2099 - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
2100 - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
2102 + unsigned immrx4_0, r_0;
2103 + r_0 = *valp & 0xf;
2104 + immrx4_0 = (((0xfffffff) << 4) | r_0) << 2;
2110 -Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2112 +Operand_immrx4_encode (uint32 *valp)
2115 - tie_t = (val << 30) >> 30;
2116 - insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
2117 - tie_t = (val << 28) >> 30;
2118 - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
2119 + unsigned r_0, immrx4_0;
2121 + r_0 = ((immrx4_0 >> 2) & 0xf);
2127 -Field_i_Slot_inst16a_get (const xtensa_insnbuf insn)
2129 +Operand_lsi4x4_decode (uint32 *valp)
2131 - unsigned tie_t = 0;
2132 - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
2134 + unsigned lsi4x4_0, r_0;
2135 + r_0 = *valp & 0xf;
2136 + lsi4x4_0 = r_0 << 2;
2142 -Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2144 +Operand_lsi4x4_encode (uint32 *valp)
2147 - tie_t = (val << 31) >> 31;
2148 - insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
2149 + unsigned r_0, lsi4x4_0;
2151 + r_0 = ((lsi4x4_0 >> 2) & 0xf);
2157 -Field_i_Slot_inst16b_get (const xtensa_insnbuf insn)
2159 +Operand_simm7_decode (uint32 *valp)
2161 - unsigned tie_t = 0;
2162 - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
2164 + unsigned simm7_0, imm7_0;
2165 + imm7_0 = *valp & 0x7f;
2166 + simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0;
2172 -Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2174 +Operand_simm7_encode (uint32 *valp)
2177 - tie_t = (val << 31) >> 31;
2178 - insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
2179 + unsigned imm7_0, simm7_0;
2181 + imm7_0 = (simm7_0 & 0x7f);
2187 -Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn)
2189 +Operand_uimm6_decode (uint32 *valp)
2191 - unsigned tie_t = 0;
2192 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
2194 + unsigned uimm6_0, imm6_0;
2195 + imm6_0 = *valp & 0x3f;
2196 + uimm6_0 = 0x4 + (((0) << 6) | imm6_0);
2202 -Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2204 +Operand_uimm6_encode (uint32 *valp)
2207 - tie_t = (val << 28) >> 28;
2208 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
2209 + unsigned imm6_0, uimm6_0;
2211 + imm6_0 = (uimm6_0 - 0x4) & 0x3f;
2217 -Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn)
2219 +Operand_uimm6_ator (uint32 *valp, uint32 pc)
2221 - unsigned tie_t = 0;
2222 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
2229 -Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2231 +Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
2234 - tie_t = (val << 28) >> 28;
2235 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
2241 -Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn)
2243 +Operand_ai4const_decode (uint32 *valp)
2245 - unsigned tie_t = 0;
2246 - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
2248 + unsigned ai4const_0, t_0;
2249 + t_0 = *valp & 0xf;
2250 + ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf];
2251 + *valp = ai4const_0;
2256 -Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2258 +Operand_ai4const_encode (uint32 *valp)
2261 - tie_t = (val << 30) >> 30;
2262 - insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
2263 + unsigned t_0, ai4const_0;
2264 + ai4const_0 = *valp;
2265 + switch (ai4const_0)
2267 + case 0xffffffff: t_0 = 0; break;
2268 + case 0x1: t_0 = 0x1; break;
2269 + case 0x2: t_0 = 0x2; break;
2270 + case 0x3: t_0 = 0x3; break;
2271 + case 0x4: t_0 = 0x4; break;
2272 + case 0x5: t_0 = 0x5; break;
2273 + case 0x6: t_0 = 0x6; break;
2274 + case 0x7: t_0 = 0x7; break;
2275 + case 0x8: t_0 = 0x8; break;
2276 + case 0x9: t_0 = 0x9; break;
2277 + case 0xa: t_0 = 0xa; break;
2278 + case 0xb: t_0 = 0xb; break;
2279 + case 0xc: t_0 = 0xc; break;
2280 + case 0xd: t_0 = 0xd; break;
2281 + case 0xe: t_0 = 0xe; break;
2282 + default: t_0 = 0xf; break;
2289 -Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn)
2291 +Operand_b4const_decode (uint32 *valp)
2293 - unsigned tie_t = 0;
2294 - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
2296 + unsigned b4const_0, r_0;
2297 + r_0 = *valp & 0xf;
2298 + b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf];
2299 + *valp = b4const_0;
2304 -Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2306 +Operand_b4const_encode (uint32 *valp)
2309 - tie_t = (val << 30) >> 30;
2310 - insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
2312 + unsigned r_0, b4const_0;
2313 + b4const_0 = *valp;
2314 + switch (b4const_0)
2316 + case 0xffffffff: r_0 = 0; break;
2317 + case 0x1: r_0 = 0x1; break;
2318 + case 0x2: r_0 = 0x2; break;
2319 + case 0x3: r_0 = 0x3; break;
2320 + case 0x4: r_0 = 0x4; break;
2321 + case 0x5: r_0 = 0x5; break;
2322 + case 0x6: r_0 = 0x6; break;
2323 + case 0x7: r_0 = 0x7; break;
2324 + case 0x8: r_0 = 0x8; break;
2325 + case 0xa: r_0 = 0x9; break;
2326 + case 0xc: r_0 = 0xa; break;
2327 + case 0x10: r_0 = 0xb; break;
2328 + case 0x20: r_0 = 0xc; break;
2329 + case 0x40: r_0 = 0xd; break;
2330 + case 0x80: r_0 = 0xe; break;
2331 + default: r_0 = 0xf; break;
2338 -Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn)
2340 +Operand_b4constu_decode (uint32 *valp)
2342 - unsigned tie_t = 0;
2343 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
2345 + unsigned b4constu_0, r_0;
2346 + r_0 = *valp & 0xf;
2347 + b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf];
2348 + *valp = b4constu_0;
2353 -Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2355 +Operand_b4constu_encode (uint32 *valp)
2358 - tie_t = (val << 28) >> 28;
2359 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
2360 + unsigned r_0, b4constu_0;
2361 + b4constu_0 = *valp;
2362 + switch (b4constu_0)
2364 + case 0x8000: r_0 = 0; break;
2365 + case 0x10000: r_0 = 0x1; break;
2366 + case 0x2: r_0 = 0x2; break;
2367 + case 0x3: r_0 = 0x3; break;
2368 + case 0x4: r_0 = 0x4; break;
2369 + case 0x5: r_0 = 0x5; break;
2370 + case 0x6: r_0 = 0x6; break;
2371 + case 0x7: r_0 = 0x7; break;
2372 + case 0x8: r_0 = 0x8; break;
2373 + case 0xa: r_0 = 0x9; break;
2374 + case 0xc: r_0 = 0xa; break;
2375 + case 0x10: r_0 = 0xb; break;
2376 + case 0x20: r_0 = 0xc; break;
2377 + case 0x40: r_0 = 0xd; break;
2378 + case 0x80: r_0 = 0xe; break;
2379 + default: r_0 = 0xf; break;
2386 -Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn)
2388 +Operand_uimm8_decode (uint32 *valp)
2390 - unsigned tie_t = 0;
2391 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
2393 + unsigned uimm8_0, imm8_0;
2394 + imm8_0 = *valp & 0xff;
2401 -Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2403 +Operand_uimm8_encode (uint32 *valp)
2406 - tie_t = (val << 28) >> 28;
2407 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
2408 + unsigned imm8_0, uimm8_0;
2410 + imm8_0 = (uimm8_0 & 0xff);
2416 -Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn)
2418 +Operand_uimm8x2_decode (uint32 *valp)
2420 - unsigned tie_t = 0;
2421 - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
2423 + unsigned uimm8x2_0, imm8_0;
2424 + imm8_0 = *valp & 0xff;
2425 + uimm8x2_0 = imm8_0 << 1;
2426 + *valp = uimm8x2_0;
2431 -Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2433 +Operand_uimm8x2_encode (uint32 *valp)
2436 - tie_t = (val << 29) >> 29;
2437 - insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
2438 + unsigned imm8_0, uimm8x2_0;
2439 + uimm8x2_0 = *valp;
2440 + imm8_0 = ((uimm8x2_0 >> 1) & 0xff);
2446 -Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn)
2448 +Operand_uimm8x4_decode (uint32 *valp)
2450 - unsigned tie_t = 0;
2451 - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
2453 + unsigned uimm8x4_0, imm8_0;
2454 + imm8_0 = *valp & 0xff;
2455 + uimm8x4_0 = imm8_0 << 2;
2456 + *valp = uimm8x4_0;
2461 -Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2463 +Operand_uimm8x4_encode (uint32 *valp)
2466 - tie_t = (val << 29) >> 29;
2467 - insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
2468 + unsigned imm8_0, uimm8x4_0;
2469 + uimm8x4_0 = *valp;
2470 + imm8_0 = ((uimm8x4_0 >> 2) & 0xff);
2476 -Field_z_Slot_inst16a_get (const xtensa_insnbuf insn)
2478 +Operand_uimm4x16_decode (uint32 *valp)
2480 - unsigned tie_t = 0;
2481 - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
2483 + unsigned uimm4x16_0, op2_0;
2484 + op2_0 = *valp & 0xf;
2485 + uimm4x16_0 = op2_0 << 4;
2486 + *valp = uimm4x16_0;
2491 -Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2493 +Operand_uimm4x16_encode (uint32 *valp)
2496 - tie_t = (val << 31) >> 31;
2497 - insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
2498 + unsigned op2_0, uimm4x16_0;
2499 + uimm4x16_0 = *valp;
2500 + op2_0 = ((uimm4x16_0 >> 4) & 0xf);
2506 -Field_z_Slot_inst16b_get (const xtensa_insnbuf insn)
2508 +Operand_simm8_decode (uint32 *valp)
2510 - unsigned tie_t = 0;
2511 - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
2513 + unsigned simm8_0, imm8_0;
2514 + imm8_0 = *valp & 0xff;
2515 + simm8_0 = ((int) imm8_0 << 24) >> 24;
2521 -Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2523 +Operand_simm8_encode (uint32 *valp)
2526 - tie_t = (val << 31) >> 31;
2527 - insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
2528 + unsigned imm8_0, simm8_0;
2530 + imm8_0 = (simm8_0 & 0xff);
2536 -Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn)
2538 +Operand_simm8x256_decode (uint32 *valp)
2540 - unsigned tie_t = 0;
2541 - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
2542 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
2544 + unsigned simm8x256_0, imm8_0;
2545 + imm8_0 = *valp & 0xff;
2546 + simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8;
2547 + *valp = simm8x256_0;
2552 -Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2554 +Operand_simm8x256_encode (uint32 *valp)
2557 - tie_t = (val << 28) >> 28;
2558 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
2559 - tie_t = (val << 26) >> 30;
2560 - insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
2561 + unsigned imm8_0, simm8x256_0;
2562 + simm8x256_0 = *valp;
2563 + imm8_0 = ((simm8x256_0 >> 8) & 0xff);
2569 -Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn)
2571 +Operand_simm12b_decode (uint32 *valp)
2573 - unsigned tie_t = 0;
2574 - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
2575 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
2577 + unsigned simm12b_0, imm12b_0;
2578 + imm12b_0 = *valp & 0xfff;
2579 + simm12b_0 = ((int) imm12b_0 << 20) >> 20;
2580 + *valp = simm12b_0;
2585 -Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2587 +Operand_simm12b_encode (uint32 *valp)
2590 - tie_t = (val << 28) >> 28;
2591 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
2592 - tie_t = (val << 26) >> 30;
2593 - insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
2594 + unsigned imm12b_0, simm12b_0;
2595 + simm12b_0 = *valp;
2596 + imm12b_0 = (simm12b_0 & 0xfff);
2602 -Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn)
2604 +Operand_msalp32_decode (uint32 *valp)
2606 - unsigned tie_t = 0;
2607 - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
2608 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
2610 + unsigned msalp32_0, sal_0;
2611 + sal_0 = *valp & 0x1f;
2612 + msalp32_0 = 0x20 - sal_0;
2613 + *valp = msalp32_0;
2618 -Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2620 +Operand_msalp32_encode (uint32 *valp)
2623 - tie_t = (val << 28) >> 28;
2624 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
2625 - tie_t = (val << 25) >> 29;
2626 - insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
2627 + unsigned sal_0, msalp32_0;
2628 + msalp32_0 = *valp;
2629 + sal_0 = (0x20 - msalp32_0) & 0x1f;
2635 -Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn)
2637 - unsigned tie_t = 0;
2638 - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
2639 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
2642 +Operand_op2p1_decode (uint32 *valp)
2644 + unsigned op2p1_0, op2_0;
2645 + op2_0 = *valp & 0xf;
2646 + op2p1_0 = op2_0 + 0x1;
2652 -Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2654 +Operand_op2p1_encode (uint32 *valp)
2657 - tie_t = (val << 28) >> 28;
2658 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
2659 - tie_t = (val << 25) >> 29;
2660 - insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
2661 + unsigned op2_0, op2p1_0;
2663 + op2_0 = (op2p1_0 - 0x1) & 0xf;
2669 -Field_imm7_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
2671 +Operand_label8_decode (uint32 *valp)
2673 - unsigned tie_t = 0;
2674 - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
2676 + unsigned label8_0, imm8_0;
2677 + imm8_0 = *valp & 0xff;
2678 + label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24);
2684 -Field_imm7_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
2686 +Operand_label8_encode (uint32 *valp)
2689 - tie_t = (val << 25) >> 25;
2690 - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
2691 + unsigned imm8_0, label8_0;
2693 + imm8_0 = (label8_0 - 0x4) & 0xff;
2699 -Field_r3_Slot_inst_get (const xtensa_insnbuf insn)
2701 +Operand_label8_ator (uint32 *valp, uint32 pc)
2703 - unsigned tie_t = 0;
2704 - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
2711 -Field_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2713 +Operand_label8_rtoa (uint32 *valp, uint32 pc)
2716 - tie_t = (val << 31) >> 31;
2717 - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
2723 -Field_rbit2_Slot_inst_get (const xtensa_insnbuf insn)
2725 +Operand_ulabel8_decode (uint32 *valp)
2727 - unsigned tie_t = 0;
2728 - tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
2730 + unsigned ulabel8_0, imm8_0;
2731 + imm8_0 = *valp & 0xff;
2732 + ulabel8_0 = 0x4 + (((0) << 8) | imm8_0);
2733 + *valp = ulabel8_0;
2738 -Field_rbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2740 +Operand_ulabel8_encode (uint32 *valp)
2743 - tie_t = (val << 31) >> 31;
2744 - insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
2745 + unsigned imm8_0, ulabel8_0;
2746 + ulabel8_0 = *valp;
2747 + imm8_0 = (ulabel8_0 - 0x4) & 0xff;
2753 -Field_rhi_Slot_inst_get (const xtensa_insnbuf insn)
2755 +Operand_ulabel8_ator (uint32 *valp, uint32 pc)
2757 - unsigned tie_t = 0;
2758 - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2765 -Field_rhi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2767 +Operand_ulabel8_rtoa (uint32 *valp, uint32 pc)
2770 - tie_t = (val << 30) >> 30;
2771 - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2777 -Field_t3_Slot_inst_get (const xtensa_insnbuf insn)
2779 +Operand_label12_decode (uint32 *valp)
2781 - unsigned tie_t = 0;
2782 - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
2784 + unsigned label12_0, imm12_0;
2785 + imm12_0 = *valp & 0xfff;
2786 + label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20);
2787 + *valp = label12_0;
2792 -Field_t3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2794 +Operand_label12_encode (uint32 *valp)
2797 - tie_t = (val << 31) >> 31;
2798 - insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
2799 + unsigned imm12_0, label12_0;
2800 + label12_0 = *valp;
2801 + imm12_0 = (label12_0 - 0x4) & 0xfff;
2807 -Field_tbit2_Slot_inst_get (const xtensa_insnbuf insn)
2809 +Operand_label12_ator (uint32 *valp, uint32 pc)
2811 - unsigned tie_t = 0;
2812 - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
2819 -Field_tbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2821 +Operand_label12_rtoa (uint32 *valp, uint32 pc)
2824 - tie_t = (val << 31) >> 31;
2825 - insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
2831 -Field_tlo_Slot_inst_get (const xtensa_insnbuf insn)
2833 +Operand_soffset_decode (uint32 *valp)
2835 - unsigned tie_t = 0;
2836 - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
2838 + unsigned soffset_0, offset_0;
2839 + offset_0 = *valp & 0x3ffff;
2840 + soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14);
2841 + *valp = soffset_0;
2846 -Field_tlo_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2848 +Operand_soffset_encode (uint32 *valp)
2851 - tie_t = (val << 30) >> 30;
2852 - insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
2853 + unsigned offset_0, soffset_0;
2854 + soffset_0 = *valp;
2855 + offset_0 = (soffset_0 - 0x4) & 0x3ffff;
2861 -Field_w_Slot_inst_get (const xtensa_insnbuf insn)
2863 +Operand_soffset_ator (uint32 *valp, uint32 pc)
2865 - unsigned tie_t = 0;
2866 - tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
2873 -Field_w_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2875 +Operand_soffset_rtoa (uint32 *valp, uint32 pc)
2878 - tie_t = (val << 30) >> 30;
2879 - insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
2885 -Field_y_Slot_inst_get (const xtensa_insnbuf insn)
2887 +Operand_uimm16x4_decode (uint32 *valp)
2889 - unsigned tie_t = 0;
2890 - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
2892 + unsigned uimm16x4_0, imm16_0;
2893 + imm16_0 = *valp & 0xffff;
2894 + uimm16x4_0 = (((0xffff) << 16) | imm16_0) << 2;
2895 + *valp = uimm16x4_0;
2900 -Field_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2902 +Operand_uimm16x4_encode (uint32 *valp)
2905 - tie_t = (val << 31) >> 31;
2906 - insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
2907 + unsigned imm16_0, uimm16x4_0;
2908 + uimm16x4_0 = *valp;
2909 + imm16_0 = (uimm16x4_0 >> 2) & 0xffff;
2915 -Field_x_Slot_inst_get (const xtensa_insnbuf insn)
2917 +Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
2919 - unsigned tie_t = 0;
2920 - tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
2922 + *valp -= ((pc + 3) & ~0x3);
2927 -Field_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2929 +Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
2932 - tie_t = (val << 31) >> 31;
2933 - insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
2934 + *valp += ((pc + 3) & ~0x3);
2939 -Field_t2_Slot_inst_get (const xtensa_insnbuf insn)
2941 +Operand_immt_decode (uint32 *valp)
2943 - unsigned tie_t = 0;
2944 - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
2946 + unsigned immt_0, t_0;
2947 + t_0 = *valp & 0xf;
2954 -Field_t2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2956 +Operand_immt_encode (uint32 *valp)
2959 - tie_t = (val << 29) >> 29;
2960 - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
2961 + unsigned t_0, immt_0;
2963 + t_0 = immt_0 & 0xf;
2969 -Field_t2_Slot_inst16a_get (const xtensa_insnbuf insn)
2971 +Operand_imms_decode (uint32 *valp)
2973 - unsigned tie_t = 0;
2974 - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
2976 + unsigned imms_0, s_0;
2977 + s_0 = *valp & 0xf;
2984 -Field_t2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2986 +Operand_imms_encode (uint32 *valp)
2989 - tie_t = (val << 29) >> 29;
2990 - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
2991 + unsigned s_0, imms_0;
2993 + s_0 = imms_0 & 0xf;
2999 -Field_t2_Slot_inst16b_get (const xtensa_insnbuf insn)
3001 +Operand_tp7_decode (uint32 *valp)
3003 - unsigned tie_t = 0;
3004 - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
3006 + unsigned tp7_0, t_0;
3007 + t_0 = *valp & 0xf;
3008 + tp7_0 = t_0 + 0x7;
3014 -Field_t2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
3016 +Operand_tp7_encode (uint32 *valp)
3019 - tie_t = (val << 29) >> 29;
3020 - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
3021 + unsigned t_0, tp7_0;
3023 + t_0 = (tp7_0 - 0x7) & 0xf;
3029 -Field_s2_Slot_inst_get (const xtensa_insnbuf insn)
3031 +Operand_xt_wbr15_label_decode (uint32 *valp)
3033 - unsigned tie_t = 0;
3034 - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
3036 + unsigned xt_wbr15_label_0, xt_wbr15_imm_0;
3037 + xt_wbr15_imm_0 = *valp & 0x7fff;
3038 + xt_wbr15_label_0 = 0x4 + (((int) xt_wbr15_imm_0 << 17) >> 17);
3039 + *valp = xt_wbr15_label_0;
3044 -Field_s2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
3046 +Operand_xt_wbr15_label_encode (uint32 *valp)
3049 - tie_t = (val << 29) >> 29;
3050 - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
3051 + unsigned xt_wbr15_imm_0, xt_wbr15_label_0;
3052 + xt_wbr15_label_0 = *valp;
3053 + xt_wbr15_imm_0 = (xt_wbr15_label_0 - 0x4) & 0x7fff;
3054 + *valp = xt_wbr15_imm_0;
3059 -Field_s2_Slot_inst16a_get (const xtensa_insnbuf insn)
3061 +Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc)
3063 - unsigned tie_t = 0;
3064 - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
3071 -Field_s2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
3073 +Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc)
3076 - tie_t = (val << 29) >> 29;
3077 - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
3083 -Field_s2_Slot_inst16b_get (const xtensa_insnbuf insn)
3085 +Operand_xt_wbr18_label_decode (uint32 *valp)
3087 - unsigned tie_t = 0;
3088 - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
3090 + unsigned xt_wbr18_label_0, xt_wbr18_imm_0;
3091 + xt_wbr18_imm_0 = *valp & 0x3ffff;
3092 + xt_wbr18_label_0 = 0x4 + (((int) xt_wbr18_imm_0 << 14) >> 14);
3093 + *valp = xt_wbr18_label_0;
3098 -Field_s2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
3100 +Operand_xt_wbr18_label_encode (uint32 *valp)
3103 - tie_t = (val << 29) >> 29;
3104 - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
3105 + unsigned xt_wbr18_imm_0, xt_wbr18_label_0;
3106 + xt_wbr18_label_0 = *valp;
3107 + xt_wbr18_imm_0 = (xt_wbr18_label_0 - 0x4) & 0x3ffff;
3108 + *valp = xt_wbr18_imm_0;
3113 -Field_r2_Slot_inst_get (const xtensa_insnbuf insn)
3115 +Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc)
3117 - unsigned tie_t = 0;
3118 - tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
3125 -Field_r2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
3127 +Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc)
3130 - tie_t = (val << 29) >> 29;
3131 - insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
3137 -Field_r2_Slot_inst16a_get (const xtensa_insnbuf insn)
3139 - unsigned tie_t = 0;
3140 - tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
3143 +static xtensa_operand_internal operands[] = {
3144 + { "soffsetx4", 10, -1, 0,
3145 + XTENSA_OPERAND_IS_PCRELATIVE,
3146 + Operand_soffsetx4_encode, Operand_soffsetx4_decode,
3147 + Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
3148 + { "uimm12x8", 3, -1, 0,
3150 + Operand_uimm12x8_encode, Operand_uimm12x8_decode,
3152 + { "simm4", 26, -1, 0,
3154 + Operand_simm4_encode, Operand_simm4_decode,
3156 + { "arr", 14, 0, 1,
3157 + XTENSA_OPERAND_IS_REGISTER,
3158 + Operand_arr_encode, Operand_arr_decode,
3161 + XTENSA_OPERAND_IS_REGISTER,
3162 + Operand_ars_encode, Operand_ars_decode,
3164 + { "*ars_invisible", 5, 0, 1,
3165 + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
3166 + Operand_ars_encode, Operand_ars_decode,
3169 + XTENSA_OPERAND_IS_REGISTER,
3170 + Operand_art_encode, Operand_art_decode,
3172 + { "ar0", 37, 0, 1,
3173 + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
3174 + Operand_ar0_encode, Operand_ar0_decode,
3176 + { "ar4", 38, 0, 1,
3177 + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
3178 + Operand_ar4_encode, Operand_ar4_decode,
3180 + { "ar8", 39, 0, 1,
3181 + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
3182 + Operand_ar8_encode, Operand_ar8_decode,
3184 + { "ar12", 40, 0, 1,
3185 + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
3186 + Operand_ar12_encode, Operand_ar12_decode,
3188 + { "ars_entry", 5, 0, 1,
3189 + XTENSA_OPERAND_IS_REGISTER,
3190 + Operand_ars_entry_encode, Operand_ars_entry_decode,
3192 + { "immrx4", 14, -1, 0,
3194 + Operand_immrx4_encode, Operand_immrx4_decode,
3196 + { "lsi4x4", 14, -1, 0,
3198 + Operand_lsi4x4_encode, Operand_lsi4x4_decode,
3200 + { "simm7", 34, -1, 0,
3202 + Operand_simm7_encode, Operand_simm7_decode,
3204 + { "uimm6", 33, -1, 0,
3205 + XTENSA_OPERAND_IS_PCRELATIVE,
3206 + Operand_uimm6_encode, Operand_uimm6_decode,
3207 + Operand_uimm6_ator, Operand_uimm6_rtoa },
3208 + { "ai4const", 0, -1, 0,
3210 + Operand_ai4const_encode, Operand_ai4const_decode,
3212 + { "b4const", 14, -1, 0,
3214 + Operand_b4const_encode, Operand_b4const_decode,
3216 + { "b4constu", 14, -1, 0,
3218 + Operand_b4constu_encode, Operand_b4constu_decode,
3220 + { "uimm8", 4, -1, 0,
3222 + Operand_uimm8_encode, Operand_uimm8_decode,
3224 + { "uimm8x2", 4, -1, 0,
3226 + Operand_uimm8x2_encode, Operand_uimm8x2_decode,
3228 + { "uimm8x4", 4, -1, 0,
3230 + Operand_uimm8x4_encode, Operand_uimm8x4_decode,
3232 + { "uimm4x16", 13, -1, 0,
3234 + Operand_uimm4x16_encode, Operand_uimm4x16_decode,
3236 + { "simm8", 4, -1, 0,
3238 + Operand_simm8_encode, Operand_simm8_decode,
3240 + { "simm8x256", 4, -1, 0,
3242 + Operand_simm8x256_encode, Operand_simm8x256_decode,
3244 + { "simm12b", 6, -1, 0,
3246 + Operand_simm12b_encode, Operand_simm12b_decode,
3248 + { "msalp32", 18, -1, 0,
3250 + Operand_msalp32_encode, Operand_msalp32_decode,
3252 + { "op2p1", 13, -1, 0,
3254 + Operand_op2p1_encode, Operand_op2p1_decode,
3256 + { "label8", 4, -1, 0,
3257 + XTENSA_OPERAND_IS_PCRELATIVE,
3258 + Operand_label8_encode, Operand_label8_decode,
3259 + Operand_label8_ator, Operand_label8_rtoa },
3260 + { "ulabel8", 4, -1, 0,
3261 + XTENSA_OPERAND_IS_PCRELATIVE,
3262 + Operand_ulabel8_encode, Operand_ulabel8_decode,
3263 + Operand_ulabel8_ator, Operand_ulabel8_rtoa },
3264 + { "label12", 3, -1, 0,
3265 + XTENSA_OPERAND_IS_PCRELATIVE,
3266 + Operand_label12_encode, Operand_label12_decode,
3267 + Operand_label12_ator, Operand_label12_rtoa },
3268 + { "soffset", 10, -1, 0,
3269 + XTENSA_OPERAND_IS_PCRELATIVE,
3270 + Operand_soffset_encode, Operand_soffset_decode,
3271 + Operand_soffset_ator, Operand_soffset_rtoa },
3272 + { "uimm16x4", 7, -1, 0,
3273 + XTENSA_OPERAND_IS_PCRELATIVE,
3274 + Operand_uimm16x4_encode, Operand_uimm16x4_decode,
3275 + Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
3276 + { "immt", 0, -1, 0,
3278 + Operand_immt_encode, Operand_immt_decode,
3280 + { "imms", 5, -1, 0,
3282 + Operand_imms_encode, Operand_imms_decode,
3284 + { "tp7", 0, -1, 0,
3286 + Operand_tp7_encode, Operand_tp7_decode,
3288 + { "xt_wbr15_label", 35, -1, 0,
3289 + XTENSA_OPERAND_IS_PCRELATIVE,
3290 + Operand_xt_wbr15_label_encode, Operand_xt_wbr15_label_decode,
3291 + Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa },
3292 + { "xt_wbr18_label", 36, -1, 0,
3293 + XTENSA_OPERAND_IS_PCRELATIVE,
3294 + Operand_xt_wbr18_label_encode, Operand_xt_wbr18_label_decode,
3295 + Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa },
3296 + { "t", 0, -1, 0, 0, 0, 0, 0, 0 },
3297 + { "bbi4", 1, -1, 0, 0, 0, 0, 0, 0 },
3298 + { "bbi", 2, -1, 0, 0, 0, 0, 0, 0 },
3299 + { "imm12", 3, -1, 0, 0, 0, 0, 0, 0 },
3300 + { "imm8", 4, -1, 0, 0, 0, 0, 0, 0 },
3301 + { "s", 5, -1, 0, 0, 0, 0, 0, 0 },
3302 + { "imm12b", 6, -1, 0, 0, 0, 0, 0, 0 },
3303 + { "imm16", 7, -1, 0, 0, 0, 0, 0, 0 },
3304 + { "m", 8, -1, 0, 0, 0, 0, 0, 0 },
3305 + { "n", 9, -1, 0, 0, 0, 0, 0, 0 },
3306 + { "offset", 10, -1, 0, 0, 0, 0, 0, 0 },
3307 + { "op0", 11, -1, 0, 0, 0, 0, 0, 0 },
3308 + { "op1", 12, -1, 0, 0, 0, 0, 0, 0 },
3309 + { "op2", 13, -1, 0, 0, 0, 0, 0, 0 },
3310 + { "r", 14, -1, 0, 0, 0, 0, 0, 0 },
3311 + { "sa4", 15, -1, 0, 0, 0, 0, 0, 0 },
3312 + { "sae4", 16, -1, 0, 0, 0, 0, 0, 0 },
3313 + { "sae", 17, -1, 0, 0, 0, 0, 0, 0 },
3314 + { "sal", 18, -1, 0, 0, 0, 0, 0, 0 },
3315 + { "sargt", 19, -1, 0, 0, 0, 0, 0, 0 },
3316 + { "sas4", 20, -1, 0, 0, 0, 0, 0, 0 },
3317 + { "sas", 21, -1, 0, 0, 0, 0, 0, 0 },
3318 + { "sr", 22, -1, 0, 0, 0, 0, 0, 0 },
3319 + { "st", 23, -1, 0, 0, 0, 0, 0, 0 },
3320 + { "thi3", 24, -1, 0, 0, 0, 0, 0, 0 },
3321 + { "imm4", 25, -1, 0, 0, 0, 0, 0, 0 },
3322 + { "mn", 26, -1, 0, 0, 0, 0, 0, 0 },
3323 + { "i", 27, -1, 0, 0, 0, 0, 0, 0 },
3324 + { "imm6lo", 28, -1, 0, 0, 0, 0, 0, 0 },
3325 + { "imm6hi", 29, -1, 0, 0, 0, 0, 0, 0 },
3326 + { "imm7lo", 30, -1, 0, 0, 0, 0, 0, 0 },
3327 + { "imm7hi", 31, -1, 0, 0, 0, 0, 0, 0 },
3328 + { "z", 32, -1, 0, 0, 0, 0, 0, 0 },
3329 + { "imm6", 33, -1, 0, 0, 0, 0, 0, 0 },
3330 + { "imm7", 34, -1, 0, 0, 0, 0, 0, 0 },
3331 + { "xt_wbr15_imm", 35, -1, 0, 0, 0, 0, 0, 0 },
3332 + { "xt_wbr18_imm", 36, -1, 0, 0, 0, 0, 0, 0 }
3336 -Field_r2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
3339 - tie_t = (val << 29) >> 29;
3340 - insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
3343 +/* Iclass table. */
3346 -Field_r2_Slot_inst16b_get (const xtensa_insnbuf insn)
3348 - unsigned tie_t = 0;
3349 - tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
3352 +static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
3353 + { { STATE_PSEXCM }, 'o' },
3354 + { { STATE_EPC1 }, 'i' }
3358 -Field_r2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
3361 - tie_t = (val << 29) >> 29;
3362 - insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
3364 +static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
3365 + { { STATE_DEPC }, 'i' }
3369 -Field_t4_Slot_inst_get (const xtensa_insnbuf insn)
3371 - unsigned tie_t = 0;
3372 - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
3375 +static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
3376 + { { 0 /* soffsetx4 */ }, 'i' },
3377 + { { 10 /* ar12 */ }, 'o' }
3381 -Field_t4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
3384 - tie_t = (val << 30) >> 30;
3385 - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
3387 +static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
3388 + { { STATE_PSCALLINC }, 'o' }
3392 -Field_t4_Slot_inst16a_get (const xtensa_insnbuf insn)
3394 - unsigned tie_t = 0;
3395 - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
3398 +static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
3399 + { { 0 /* soffsetx4 */ }, 'i' },
3400 + { { 9 /* ar8 */ }, 'o' }
3404 -Field_t4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
3407 - tie_t = (val << 30) >> 30;
3408 - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
3410 +static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
3411 + { { STATE_PSCALLINC }, 'o' }
3415 -Field_t4_Slot_inst16b_get (const xtensa_insnbuf insn)
3417 - unsigned tie_t = 0;
3418 - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
3421 +static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
3422 + { { 0 /* soffsetx4 */ }, 'i' },
3423 + { { 8 /* ar4 */ }, 'o' }
3427 -Field_t4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
3430 - tie_t = (val << 30) >> 30;
3431 - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
3433 +static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
3434 + { { STATE_PSCALLINC }, 'o' }
3438 -Field_s4_Slot_inst_get (const xtensa_insnbuf insn)
3440 - unsigned tie_t = 0;
3441 - tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
3444 +static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
3445 + { { 4 /* ars */ }, 'i' },
3446 + { { 10 /* ar12 */ }, 'o' }
3450 -Field_s4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
3453 - tie_t = (val << 30) >> 30;
3454 - insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
3456 +static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
3457 + { { STATE_PSCALLINC }, 'o' }
3461 -Field_s4_Slot_inst16a_get (const xtensa_insnbuf insn)
3463 - unsigned tie_t = 0;
3464 - tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
3467 +static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
3468 + { { 4 /* ars */ }, 'i' },
3469 + { { 9 /* ar8 */ }, 'o' }
3473 -Field_s4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
3476 - tie_t = (val << 30) >> 30;
3477 - insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
3479 +static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
3480 + { { STATE_PSCALLINC }, 'o' }
3484 -Field_s4_Slot_inst16b_get (const xtensa_insnbuf insn)
3486 - unsigned tie_t = 0;
3487 - tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
3490 +static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
3491 + { { 4 /* ars */ }, 'i' },
3492 + { { 8 /* ar4 */ }, 'o' }
3496 -Field_s4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
3499 - tie_t = (val << 30) >> 30;
3500 - insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
3502 +static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
3503 + { { STATE_PSCALLINC }, 'o' }
3507 -Field_r4_Slot_inst_get (const xtensa_insnbuf insn)
3509 - unsigned tie_t = 0;
3510 - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3513 +static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
3514 + { { 11 /* ars_entry */ }, 's' },
3515 + { { 4 /* ars */ }, 'i' },
3516 + { { 1 /* uimm12x8 */ }, 'i' }
3520 -Field_r4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
3523 - tie_t = (val << 30) >> 30;
3524 - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3526 +static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
3527 + { { STATE_PSCALLINC }, 'i' },
3528 + { { STATE_PSEXCM }, 'i' },
3529 + { { STATE_PSWOE }, 'i' },
3530 + { { STATE_WindowBase }, 'm' },
3531 + { { STATE_WindowStart }, 'm' }
3535 -Field_r4_Slot_inst16a_get (const xtensa_insnbuf insn)
3537 - unsigned tie_t = 0;
3538 - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3541 +static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
3542 + { { 6 /* art */ }, 'o' },
3543 + { { 4 /* ars */ }, 'i' }
3547 -Field_r4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
3550 - tie_t = (val << 30) >> 30;
3551 - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3553 +static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
3554 + { { STATE_WindowBase }, 'i' },
3555 + { { STATE_WindowStart }, 'i' }
3559 -Field_r4_Slot_inst16b_get (const xtensa_insnbuf insn)
3561 - unsigned tie_t = 0;
3562 - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3565 +static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
3566 + { { 2 /* simm4 */ }, 'i' }
3570 -Field_r4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
3573 - tie_t = (val << 30) >> 30;
3574 - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3576 +static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
3577 + { { STATE_WindowBase }, 'm' }
3581 -Field_t8_Slot_inst_get (const xtensa_insnbuf insn)
3583 - unsigned tie_t = 0;
3584 - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
3587 +static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
3588 + { { 5 /* *ars_invisible */ }, 'i' }
3592 -Field_t8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
3595 - tie_t = (val << 31) >> 31;
3596 - insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
3598 +static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
3599 + { { STATE_WindowBase }, 'm' },
3600 + { { STATE_WindowStart }, 'm' },
3601 + { { STATE_PSEXCM }, 'i' },
3602 + { { STATE_PSWOE }, 'i' }
3606 -Field_t8_Slot_inst16a_get (const xtensa_insnbuf insn)
3608 - unsigned tie_t = 0;
3609 - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
3612 +static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
3613 + { { STATE_EPC1 }, 'i' },
3614 + { { STATE_PSEXCM }, 'o' },
3615 + { { STATE_WindowBase }, 'm' },
3616 + { { STATE_WindowStart }, 'm' },
3617 + { { STATE_PSOWB }, 'i' }
3621 -Field_t8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
3624 - tie_t = (val << 31) >> 31;
3625 - insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
3627 +static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
3628 + { { 6 /* art */ }, 'o' },
3629 + { { 4 /* ars */ }, 'i' },
3630 + { { 12 /* immrx4 */ }, 'i' }
3634 -Field_t8_Slot_inst16b_get (const xtensa_insnbuf insn)
3636 - unsigned tie_t = 0;
3637 - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
3640 +static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
3641 + { { 6 /* art */ }, 'i' },
3642 + { { 4 /* ars */ }, 'i' },
3643 + { { 12 /* immrx4 */ }, 'i' }
3647 -Field_t8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
3650 - tie_t = (val << 31) >> 31;
3651 - insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
3653 +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
3654 + { { 6 /* art */ }, 'o' }
3658 -Field_s8_Slot_inst_get (const xtensa_insnbuf insn)
3660 - unsigned tie_t = 0;
3661 - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
3664 +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
3665 + { { STATE_WindowBase }, 'i' }
3669 -Field_s8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
3672 - tie_t = (val << 31) >> 31;
3673 - insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
3675 +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
3676 + { { 6 /* art */ }, 'i' }
3680 -Field_s8_Slot_inst16a_get (const xtensa_insnbuf insn)
3682 - unsigned tie_t = 0;
3683 - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
3688 -Field_s8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
3691 - tie_t = (val << 31) >> 31;
3692 - insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
3694 +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
3695 + { { STATE_WindowBase }, 'o' }
3699 -Field_s8_Slot_inst16b_get (const xtensa_insnbuf insn)
3701 - unsigned tie_t = 0;
3702 - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
3705 +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
3706 + { { 6 /* art */ }, 'm' }
3710 -Field_s8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
3713 - tie_t = (val << 31) >> 31;
3714 - insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
3716 +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
3717 + { { STATE_WindowBase }, 'm' }
3721 -Field_r8_Slot_inst_get (const xtensa_insnbuf insn)
3723 - unsigned tie_t = 0;
3724 - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
3727 +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
3728 + { { 6 /* art */ }, 'o' }
3732 -Field_r8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
3735 - tie_t = (val << 31) >> 31;
3736 - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
3738 +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
3739 + { { STATE_WindowStart }, 'i' }
3743 -Field_r8_Slot_inst16a_get (const xtensa_insnbuf insn)
3745 - unsigned tie_t = 0;
3746 - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
3749 +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
3750 + { { 6 /* art */ }, 'i' }
3754 -Field_r8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
3757 - tie_t = (val << 31) >> 31;
3758 - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
3760 +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
3761 + { { STATE_WindowStart }, 'o' }
3765 -Field_r8_Slot_inst16b_get (const xtensa_insnbuf insn)
3767 - unsigned tie_t = 0;
3768 - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
3771 +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
3772 + { { 6 /* art */ }, 'm' }
3776 -Field_r8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
3779 - tie_t = (val << 31) >> 31;
3780 - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
3782 +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
3783 + { { STATE_WindowStart }, 'm' }
3787 -Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn)
3789 - unsigned tie_t = 0;
3790 - tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17);
3793 +static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
3794 + { { 3 /* arr */ }, 'o' },
3795 + { { 4 /* ars */ }, 'i' },
3796 + { { 6 /* art */ }, 'i' }
3800 -Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
3803 - tie_t = (val << 17) >> 17;
3804 - insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9);
3806 +static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
3807 + { { 3 /* arr */ }, 'o' },
3808 + { { 4 /* ars */ }, 'i' },
3809 + { { 16 /* ai4const */ }, 'i' }
3813 -Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn)
3815 - unsigned tie_t = 0;
3816 - tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
3819 +static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
3820 + { { 4 /* ars */ }, 'i' },
3821 + { { 15 /* uimm6 */ }, 'i' }
3825 -Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
3828 - tie_t = (val << 14) >> 14;
3829 - insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
3831 +static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
3832 + { { 6 /* art */ }, 'o' },
3833 + { { 4 /* ars */ }, 'i' },
3834 + { { 13 /* lsi4x4 */ }, 'i' }
3838 -Field_xt_wbr18_imm_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3840 - unsigned tie_t = 0;
3841 - tie_t = (tie_t << 18) | ((insn[0] << 6) >> 14);
3844 +static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
3845 + { { 6 /* art */ }, 'o' },
3846 + { { 4 /* ars */ }, 'i' }
3850 -Field_xt_wbr18_imm_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3853 - tie_t = (val << 14) >> 14;
3854 - insn[0] = (insn[0] & ~0x3ffff00) | (tie_t << 8);
3856 +static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
3857 + { { 4 /* ars */ }, 'o' },
3858 + { { 14 /* simm7 */ }, 'i' }
3862 -Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
3864 - unsigned tie_t = 0;
3865 - tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
3868 +static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
3869 + { { 5 /* *ars_invisible */ }, 'i' }
3873 -Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
3876 - tie_t = (val << 28) >> 28;
3877 - insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
3879 +static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
3880 + { { 6 /* art */ }, 'i' },
3881 + { { 4 /* ars */ }, 'i' },
3882 + { { 13 /* lsi4x4 */ }, 'i' }
3886 -Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
3888 - unsigned tie_t = 0;
3889 - tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
3892 +static xtensa_arg_internal Iclass_rur_threadptr_args[] = {
3893 + { { 3 /* arr */ }, 'o' }
3897 -Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
3900 - tie_t = (val << 29) >> 29;
3901 - insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
3903 +static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = {
3904 + { { STATE_THREADPTR }, 'i' }
3908 -Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
3910 - unsigned tie_t = 0;
3911 - tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
3914 +static xtensa_arg_internal Iclass_wur_threadptr_args[] = {
3915 + { { 6 /* art */ }, 'i' }
3919 -Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
3922 - tie_t = (val << 29) >> 29;
3923 - insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
3925 +static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = {
3926 + { { STATE_THREADPTR }, 'o' }
3930 -Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
3932 - unsigned tie_t = 0;
3933 - tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29);
3936 +static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
3937 + { { 6 /* art */ }, 'o' },
3938 + { { 4 /* ars */ }, 'i' },
3939 + { { 23 /* simm8 */ }, 'i' }
3943 -Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
3946 - tie_t = (val << 29) >> 29;
3947 - insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
3949 +static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
3950 + { { 6 /* art */ }, 'o' },
3951 + { { 4 /* ars */ }, 'i' },
3952 + { { 24 /* simm8x256 */ }, 'i' }
3956 -Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
3958 - unsigned tie_t = 0;
3959 - tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29);
3962 +static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
3963 + { { 3 /* arr */ }, 'o' },
3964 + { { 4 /* ars */ }, 'i' },
3965 + { { 6 /* art */ }, 'i' }
3969 -Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
3972 - tie_t = (val << 29) >> 29;
3973 - insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
3975 +static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
3976 + { { 3 /* arr */ }, 'o' },
3977 + { { 4 /* ars */ }, 'i' },
3978 + { { 6 /* art */ }, 'i' }
3982 -Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
3984 - unsigned tie_t = 0;
3985 - tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
3986 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
3989 +static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
3990 + { { 4 /* ars */ }, 'i' },
3991 + { { 17 /* b4const */ }, 'i' },
3992 + { { 28 /* label8 */ }, 'i' }
3996 -Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
3999 - tie_t = (val << 28) >> 28;
4000 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
4001 - tie_t = (val << 24) >> 28;
4002 - insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
4004 +static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
4005 + { { 4 /* ars */ }, 'i' },
4006 + { { 40 /* bbi */ }, 'i' },
4007 + { { 28 /* label8 */ }, 'i' }
4011 -Field_op0_s4_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4013 - unsigned tie_t = 0;
4014 - tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30);
4017 +static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
4018 + { { 4 /* ars */ }, 'i' },
4019 + { { 18 /* b4constu */ }, 'i' },
4020 + { { 28 /* label8 */ }, 'i' }
4024 -Field_op0_s4_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4027 - tie_t = (val << 30) >> 30;
4028 - insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18);
4030 +static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
4031 + { { 4 /* ars */ }, 'i' },
4032 + { { 6 /* art */ }, 'i' },
4033 + { { 28 /* label8 */ }, 'i' }
4037 -Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4039 - unsigned tie_t = 0;
4040 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
4043 +static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
4044 + { { 4 /* ars */ }, 'i' },
4045 + { { 30 /* label12 */ }, 'i' }
4049 -Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4052 - tie_t = (val << 28) >> 28;
4053 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
4055 +static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
4056 + { { 0 /* soffsetx4 */ }, 'i' },
4057 + { { 7 /* ar0 */ }, 'o' }
4061 -Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4063 - unsigned tie_t = 0;
4064 - tie_t = (tie_t << 1) | ((insn[0] << 14) >> 31);
4067 +static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
4068 + { { 4 /* ars */ }, 'i' },
4069 + { { 7 /* ar0 */ }, 'o' }
4073 -Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4076 - tie_t = (val << 31) >> 31;
4077 - insn[0] = (insn[0] & ~0x20000) | (tie_t << 17);
4079 +static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
4080 + { { 3 /* arr */ }, 'o' },
4081 + { { 6 /* art */ }, 'i' },
4082 + { { 55 /* sae */ }, 'i' },
4083 + { { 27 /* op2p1 */ }, 'i' }
4087 -Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4089 - unsigned tie_t = 0;
4090 - tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30);
4093 +static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
4094 + { { 31 /* soffset */ }, 'i' }
4098 -Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4101 - tie_t = (val << 30) >> 30;
4102 - insn[0] = (insn[0] & ~0x30000) | (tie_t << 16);
4104 +static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
4105 + { { 4 /* ars */ }, 'i' }
4109 -Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4111 - unsigned tie_t = 0;
4112 - tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27);
4115 +static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
4116 + { { 6 /* art */ }, 'o' },
4117 + { { 4 /* ars */ }, 'i' },
4118 + { { 20 /* uimm8x2 */ }, 'i' }
4122 -Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4125 - tie_t = (val << 27) >> 27;
4126 - insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13);
4128 +static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
4129 + { { 6 /* art */ }, 'o' },
4130 + { { 4 /* ars */ }, 'i' },
4131 + { { 20 /* uimm8x2 */ }, 'i' }
4135 -Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4137 - unsigned tie_t = 0;
4138 - tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26);
4141 +static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
4142 + { { 6 /* art */ }, 'o' },
4143 + { { 4 /* ars */ }, 'i' },
4144 + { { 21 /* uimm8x4 */ }, 'i' }
4148 -Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4151 - tie_t = (val << 26) >> 26;
4152 - insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
4154 +static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
4155 + { { 6 /* art */ }, 'o' },
4156 + { { 32 /* uimm16x4 */ }, 'i' }
4160 -Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4162 - unsigned tie_t = 0;
4163 - tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26);
4164 - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
4167 +static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = {
4168 + { { STATE_LITBADDR }, 'i' },
4169 + { { STATE_LITBEN }, 'i' }
4173 -Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4176 - tie_t = (val << 29) >> 29;
4177 - insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
4178 - tie_t = (val << 23) >> 26;
4179 - insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
4181 +static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
4182 + { { 6 /* art */ }, 'o' },
4183 + { { 4 /* ars */ }, 'i' },
4184 + { { 19 /* uimm8 */ }, 'i' }
4188 -Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4190 - unsigned tie_t = 0;
4191 - tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26);
4192 - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
4195 +static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = {
4196 + { { 4 /* ars */ }, 'i' },
4197 + { { 29 /* ulabel8 */ }, 'i' }
4201 -Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4204 - tie_t = (val << 29) >> 29;
4205 - insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
4206 - tie_t = (val << 23) >> 26;
4207 - insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
4209 +static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = {
4210 + { { STATE_LBEG }, 'o' },
4211 + { { STATE_LEND }, 'o' },
4212 + { { STATE_LCOUNT }, 'o' }
4216 -Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4218 - unsigned tie_t = 0;
4219 - tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26);
4220 - tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30);
4223 +static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = {
4224 + { { 4 /* ars */ }, 'i' },
4225 + { { 29 /* ulabel8 */ }, 'i' }
4229 -Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4232 - tie_t = (val << 30) >> 30;
4233 - insn[0] = (insn[0] & ~0x60) | (tie_t << 5);
4234 - tie_t = (val << 24) >> 26;
4235 - insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
4237 +static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = {
4238 + { { STATE_LBEG }, 'o' },
4239 + { { STATE_LEND }, 'o' },
4240 + { { STATE_LCOUNT }, 'o' }
4244 -Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4246 - unsigned tie_t = 0;
4247 - tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26);
4248 - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
4251 +static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
4252 + { { 6 /* art */ }, 'o' },
4253 + { { 25 /* simm12b */ }, 'i' }
4257 -Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4260 - tie_t = (val << 31) >> 31;
4261 - insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
4262 - tie_t = (val << 25) >> 26;
4263 - insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
4265 +static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
4266 + { { 3 /* arr */ }, 'm' },
4267 + { { 4 /* ars */ }, 'i' },
4268 + { { 6 /* art */ }, 'i' }
4272 -Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4274 - unsigned tie_t = 0;
4275 - tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26);
4276 - tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
4279 +static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
4280 + { { 3 /* arr */ }, 'o' },
4281 + { { 6 /* art */ }, 'i' }
4285 -Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4288 - tie_t = (val << 30) >> 30;
4289 - insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
4290 - tie_t = (val << 24) >> 26;
4291 - insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
4293 +static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
4294 + { { 5 /* *ars_invisible */ }, 'i' }
4298 -Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4300 - unsigned tie_t = 0;
4301 - tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26);
4302 - tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
4305 +static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
4306 + { { 6 /* art */ }, 'i' },
4307 + { { 4 /* ars */ }, 'i' },
4308 + { { 20 /* uimm8x2 */ }, 'i' }
4312 -Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4315 - tie_t = (val << 30) >> 30;
4316 - insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
4317 - tie_t = (val << 24) >> 26;
4318 - insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
4320 +static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
4321 + { { 6 /* art */ }, 'i' },
4322 + { { 4 /* ars */ }, 'i' },
4323 + { { 21 /* uimm8x4 */ }, 'i' }
4327 -Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4329 - unsigned tie_t = 0;
4330 - tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26);
4331 - tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31);
4334 +static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
4335 + { { 6 /* art */ }, 'i' },
4336 + { { 4 /* ars */ }, 'i' },
4337 + { { 19 /* uimm8 */ }, 'i' }
4341 -Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4344 - tie_t = (val << 31) >> 31;
4345 - insn[0] = (insn[0] & ~0x200) | (tie_t << 9);
4346 - tie_t = (val << 25) >> 26;
4347 - insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
4349 +static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
4350 + { { 4 /* ars */ }, 'i' }
4354 -Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4356 - unsigned tie_t = 0;
4357 - tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29);
4360 +static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
4361 + { { STATE_SAR }, 'o' }
4365 -Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4368 - tie_t = (val << 29) >> 29;
4369 - insn[0] = (insn[0] & ~0x38000) | (tie_t << 15);
4371 +static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
4372 + { { 59 /* sas */ }, 'i' }
4376 -Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4378 - unsigned tie_t = 0;
4379 - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
4382 +static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
4383 + { { STATE_SAR }, 'o' }
4387 -Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4390 - tie_t = (val << 31) >> 31;
4391 - insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
4393 +static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
4394 + { { 3 /* arr */ }, 'o' },
4395 + { { 4 /* ars */ }, 'i' }
4399 -Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4401 - unsigned tie_t = 0;
4402 - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
4403 - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4406 +static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
4407 + { { STATE_SAR }, 'i' }
4411 -Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4414 - tie_t = (val << 28) >> 28;
4415 - insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4416 - tie_t = (val << 27) >> 31;
4417 - insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
4419 +static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
4420 + { { 3 /* arr */ }, 'o' },
4421 + { { 4 /* ars */ }, 'i' },
4422 + { { 6 /* art */ }, 'i' }
4426 -Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4428 - unsigned tie_t = 0;
4429 - tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
4432 +static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
4433 + { { STATE_SAR }, 'i' }
4437 -Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4440 - tie_t = (val << 30) >> 30;
4441 - insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
4443 +static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
4444 + { { 3 /* arr */ }, 'o' },
4445 + { { 6 /* art */ }, 'i' }
4449 -Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4451 - unsigned tie_t = 0;
4452 - tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
4453 - tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26);
4456 +static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
4457 + { { STATE_SAR }, 'i' }
4461 -Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4464 - tie_t = (val << 26) >> 26;
4465 - insn[0] = (insn[0] & ~0x3f) | (tie_t << 0);
4466 - tie_t = (val << 21) >> 27;
4467 - insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
4469 +static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
4470 + { { 3 /* arr */ }, 'o' },
4471 + { { 4 /* ars */ }, 'i' },
4472 + { { 26 /* msalp32 */ }, 'i' }
4476 -Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4478 - unsigned tie_t = 0;
4479 - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
4480 - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4483 +static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
4484 + { { 3 /* arr */ }, 'o' },
4485 + { { 6 /* art */ }, 'i' },
4486 + { { 57 /* sargt */ }, 'i' }
4490 -Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4493 - tie_t = (val << 28) >> 28;
4494 - insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4495 - tie_t = (val << 27) >> 31;
4496 - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
4498 +static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
4499 + { { 3 /* arr */ }, 'o' },
4500 + { { 6 /* art */ }, 'i' },
4501 + { { 43 /* s */ }, 'i' }
4505 -Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4507 - unsigned tie_t = 0;
4508 - tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
4509 - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
4512 +static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
4513 + { { STATE_XTSYNC }, 'i' }
4517 -Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4520 - tie_t = (val << 31) >> 31;
4521 - insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
4522 - tie_t = (val << 29) >> 30;
4523 - insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
4525 +static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
4526 + { { 6 /* art */ }, 'o' },
4527 + { { 43 /* s */ }, 'i' }
4531 -Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4533 - unsigned tie_t = 0;
4534 - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
4535 - tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27);
4538 +static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
4539 + { { STATE_PSWOE }, 'i' },
4540 + { { STATE_PSCALLINC }, 'i' },
4541 + { { STATE_PSOWB }, 'i' },
4542 + { { STATE_PSUM }, 'i' },
4543 + { { STATE_PSEXCM }, 'i' },
4544 + { { STATE_PSINTLEVEL }, 'm' }
4548 -Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4551 - tie_t = (val << 27) >> 27;
4552 - insn[0] = (insn[0] & ~0x1f) | (tie_t << 0);
4553 - tie_t = (val << 26) >> 31;
4554 - insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
4556 +static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = {
4557 + { { 6 /* art */ }, 'o' }
4561 -Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4563 - unsigned tie_t = 0;
4564 - tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29);
4567 +static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = {
4568 + { { STATE_LEND }, 'i' }
4572 -Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4575 - tie_t = (val << 29) >> 29;
4576 - insn[0] = (insn[0] & ~0x7000) | (tie_t << 12);
4578 +static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = {
4579 + { { 6 /* art */ }, 'i' }
4583 -Field_op0_s5_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
4585 - unsigned tie_t = 0;
4586 - tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
4589 +static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = {
4590 + { { STATE_LEND }, 'o' }
4594 -Field_op0_s5_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
4597 - tie_t = (val << 29) >> 29;
4598 - insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
4600 +static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = {
4601 + { { 6 /* art */ }, 'm' }
4605 -Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
4607 - unsigned tie_t = 0;
4608 - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
4611 +static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = {
4612 + { { STATE_LEND }, 'm' }
4616 -Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
4619 - tie_t = (val << 31) >> 31;
4620 - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
4622 +static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = {
4623 + { { 6 /* art */ }, 'o' }
4627 -Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
4629 - unsigned tie_t = 0;
4630 - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
4631 - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
4634 +static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = {
4635 + { { STATE_LCOUNT }, 'i' }
4639 -Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
4642 - tie_t = (val << 31) >> 31;
4643 - insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
4644 - tie_t = (val << 30) >> 31;
4645 - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
4647 +static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = {
4648 + { { 6 /* art */ }, 'i' }
4652 -Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
4654 - unsigned tie_t = 0;
4655 - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
4656 - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
4657 - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
4660 +static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = {
4661 + { { STATE_XTSYNC }, 'o' },
4662 + { { STATE_LCOUNT }, 'o' }
4666 -Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
4669 - tie_t = (val << 31) >> 31;
4670 - insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
4671 - tie_t = (val << 30) >> 31;
4672 - insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
4673 - tie_t = (val << 29) >> 31;
4674 - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
4676 +static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = {
4677 + { { 6 /* art */ }, 'm' }
4681 -Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
4683 - unsigned tie_t = 0;
4684 - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
4685 - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
4686 - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
4689 +static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = {
4690 + { { STATE_XTSYNC }, 'o' },
4691 + { { STATE_LCOUNT }, 'm' }
4695 -Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
4698 - tie_t = (val << 31) >> 31;
4699 - insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
4700 - tie_t = (val << 30) >> 31;
4701 - insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
4702 - tie_t = (val << 29) >> 31;
4703 - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
4705 +static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = {
4706 + { { 6 /* art */ }, 'o' }
4710 -Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
4712 - unsigned tie_t = 0;
4713 - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
4714 - tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
4717 +static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = {
4718 + { { STATE_LBEG }, 'i' }
4722 -Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
4725 - tie_t = (val << 29) >> 29;
4726 - insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
4727 - tie_t = (val << 28) >> 31;
4728 - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
4730 +static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = {
4731 + { { 6 /* art */ }, 'i' }
4735 -Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
4737 - unsigned tie_t = 0;
4738 - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
4739 - tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
4742 +static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = {
4743 + { { STATE_LBEG }, 'o' }
4747 -Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
4750 - tie_t = (val << 29) >> 29;
4751 - insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
4752 - tie_t = (val << 28) >> 31;
4753 - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
4755 +static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = {
4756 + { { 6 /* art */ }, 'm' }
4760 -Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
4762 - unsigned tie_t = 0;
4763 - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
4764 - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
4767 +static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = {
4768 + { { STATE_LBEG }, 'm' }
4772 -Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
4775 - tie_t = (val << 30) >> 30;
4776 - insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
4777 - tie_t = (val << 29) >> 31;
4778 - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
4780 +static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
4781 + { { 6 /* art */ }, 'o' }
4785 -Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
4787 - unsigned tie_t = 0;
4788 - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
4789 - tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31);
4792 +static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
4793 + { { STATE_SAR }, 'i' }
4797 -Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
4800 - tie_t = (val << 31) >> 31;
4801 - insn[0] = (insn[0] & ~0x400) | (tie_t << 10);
4802 - tie_t = (val << 30) >> 31;
4803 - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
4805 +static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
4806 + { { 6 /* art */ }, 'i' }
4810 -Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
4812 - unsigned tie_t = 0;
4813 - tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30);
4816 +static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
4817 + { { STATE_SAR }, 'o' },
4818 + { { STATE_XTSYNC }, 'o' }
4822 -Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
4825 - tie_t = (val << 30) >> 30;
4826 - insn[0] = (insn[0] & ~0x60) | (tie_t << 5);
4828 +static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
4829 + { { 6 /* art */ }, 'm' }
4833 -Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
4835 - unsigned tie_t = 0;
4836 - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
4839 +static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
4840 + { { STATE_SAR }, 'm' }
4844 -Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
4847 - tie_t = (val << 31) >> 31;
4848 - insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
4850 +static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = {
4851 + { { 6 /* art */ }, 'o' }
4855 -Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
4857 - unsigned tie_t = 0;
4858 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
4859 - tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30);
4860 - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4863 +static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = {
4864 + { { STATE_LITBADDR }, 'i' },
4865 + { { STATE_LITBEN }, 'i' }
4869 -Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
4872 - tie_t = (val << 28) >> 28;
4873 - insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4874 - tie_t = (val << 26) >> 30;
4875 - insn[0] = (insn[0] & ~0x60) | (tie_t << 5);
4876 - tie_t = (val << 22) >> 28;
4877 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
4879 +static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = {
4880 + { { 6 /* art */ }, 'i' }
4884 -Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
4886 - unsigned tie_t = 0;
4887 - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
4888 - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
4891 +static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = {
4892 + { { STATE_LITBADDR }, 'o' },
4893 + { { STATE_LITBEN }, 'o' }
4897 -Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
4900 - tie_t = (val << 31) >> 31;
4901 - insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
4902 - tie_t = (val << 30) >> 31;
4903 - insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
4905 +static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = {
4906 + { { 6 /* art */ }, 'm' }
4910 -Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
4912 - unsigned tie_t = 0;
4913 - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
4914 - tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
4917 +static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = {
4918 + { { STATE_LITBADDR }, 'm' },
4919 + { { STATE_LITBEN }, 'm' }
4923 -Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
4926 - tie_t = (val << 30) >> 30;
4927 - insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
4928 - tie_t = (val << 29) >> 31;
4929 - insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
4931 +static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = {
4932 + { { 6 /* art */ }, 'o' }
4936 -Field_op0_s6_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
4938 - unsigned tie_t = 0;
4939 - tie_t = (tie_t << 5) | ((insn[0] << 0) >> 27);
4942 +static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = {
4943 + { { 6 /* art */ }, 'o' }
4947 -Field_op0_s6_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
4950 - tie_t = (val << 27) >> 27;
4951 - insn[0] = (insn[0] & ~0xf8000000) | (tie_t << 27);
4953 +static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
4954 + { { 6 /* art */ }, 'o' }
4958 -Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
4960 - unsigned tie_t = 0;
4961 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
4962 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
4963 - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4966 +static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
4967 + { { STATE_PSWOE }, 'i' },
4968 + { { STATE_PSCALLINC }, 'i' },
4969 + { { STATE_PSOWB }, 'i' },
4970 + { { STATE_PSUM }, 'i' },
4971 + { { STATE_PSEXCM }, 'i' },
4972 + { { STATE_PSINTLEVEL }, 'i' }
4976 -Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
4979 - tie_t = (val << 28) >> 28;
4980 - insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4981 - tie_t = (val << 27) >> 31;
4982 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
4983 - tie_t = (val << 24) >> 29;
4984 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
4986 +static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
4987 + { { 6 /* art */ }, 'i' }
4991 -Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
4993 - unsigned tie_t = 0;
4994 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
4997 +static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
4998 + { { STATE_PSWOE }, 'o' },
4999 + { { STATE_PSCALLINC }, 'o' },
5000 + { { STATE_PSOWB }, 'o' },
5001 + { { STATE_PSUM }, 'o' },
5002 + { { STATE_PSEXCM }, 'o' },
5003 + { { STATE_PSINTLEVEL }, 'o' }
5007 -Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5010 - tie_t = (val << 29) >> 29;
5011 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5013 +static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
5014 + { { 6 /* art */ }, 'm' }
5018 -Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5020 - unsigned tie_t = 0;
5021 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5022 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5023 - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
5026 +static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
5027 + { { STATE_PSWOE }, 'm' },
5028 + { { STATE_PSCALLINC }, 'm' },
5029 + { { STATE_PSOWB }, 'm' },
5030 + { { STATE_PSUM }, 'm' },
5031 + { { STATE_PSEXCM }, 'm' },
5032 + { { STATE_PSINTLEVEL }, 'm' }
5036 -Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5039 - tie_t = (val << 28) >> 28;
5040 - insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
5041 - tie_t = (val << 27) >> 31;
5042 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5043 - tie_t = (val << 24) >> 29;
5044 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5046 +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
5047 + { { 6 /* art */ }, 'o' }
5051 -Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5053 - unsigned tie_t = 0;
5054 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5055 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5056 - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
5061 -Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5064 - tie_t = (val << 28) >> 28;
5065 - insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
5066 - tie_t = (val << 27) >> 31;
5067 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5068 - tie_t = (val << 24) >> 29;
5069 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5071 +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
5072 + { { STATE_EPC1 }, 'i' }
5076 -Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5078 - unsigned tie_t = 0;
5079 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5080 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5081 - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
5084 +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
5085 + { { 6 /* art */ }, 'i' }
5089 -Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5092 - tie_t = (val << 28) >> 28;
5093 - insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
5094 - tie_t = (val << 27) >> 31;
5095 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5096 - tie_t = (val << 24) >> 29;
5097 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5099 +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
5100 + { { STATE_EPC1 }, 'o' }
5104 -Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5106 - unsigned tie_t = 0;
5107 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5108 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5111 +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
5112 + { { 6 /* art */ }, 'm' }
5116 -Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5119 - tie_t = (val << 31) >> 31;
5120 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5121 - tie_t = (val << 28) >> 29;
5122 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5124 +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
5125 + { { STATE_EPC1 }, 'm' }
5129 -Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5131 - unsigned tie_t = 0;
5132 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5133 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5136 +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
5137 + { { 6 /* art */ }, 'o' }
5141 -Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5144 - tie_t = (val << 31) >> 31;
5145 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5146 - tie_t = (val << 28) >> 29;
5147 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5149 +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
5150 + { { STATE_EXCSAVE1 }, 'i' }
5154 -Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5156 - unsigned tie_t = 0;
5157 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5158 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5161 +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
5162 + { { 6 /* art */ }, 'i' }
5166 -Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5169 - tie_t = (val << 31) >> 31;
5170 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5171 - tie_t = (val << 28) >> 29;
5172 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5174 +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
5175 + { { STATE_EXCSAVE1 }, 'o' }
5179 -Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5181 - unsigned tie_t = 0;
5182 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5183 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5186 +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
5187 + { { 6 /* art */ }, 'm' }
5191 -Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5194 - tie_t = (val << 31) >> 31;
5195 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5196 - tie_t = (val << 28) >> 29;
5197 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5199 +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
5200 + { { STATE_EXCSAVE1 }, 'm' }
5204 -Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5206 - unsigned tie_t = 0;
5207 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5208 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5211 +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
5212 + { { 6 /* art */ }, 'o' }
5216 -Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5219 - tie_t = (val << 31) >> 31;
5220 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5221 - tie_t = (val << 28) >> 29;
5222 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5224 +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
5225 + { { STATE_EPC2 }, 'i' }
5229 -Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5231 - unsigned tie_t = 0;
5232 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5233 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5236 +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
5237 + { { 6 /* art */ }, 'i' }
5241 -Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5244 - tie_t = (val << 31) >> 31;
5245 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5246 - tie_t = (val << 28) >> 29;
5247 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5249 +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
5250 + { { STATE_EPC2 }, 'o' }
5254 -Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5256 - unsigned tie_t = 0;
5257 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5258 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5261 +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
5262 + { { 6 /* art */ }, 'm' }
5266 -Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5269 - tie_t = (val << 31) >> 31;
5270 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5271 - tie_t = (val << 28) >> 29;
5272 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5274 +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
5275 + { { STATE_EPC2 }, 'm' }
5279 -Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5281 - unsigned tie_t = 0;
5282 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5283 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5286 +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
5287 + { { 6 /* art */ }, 'o' }
5291 -Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5294 - tie_t = (val << 31) >> 31;
5295 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5296 - tie_t = (val << 28) >> 29;
5297 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5299 +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
5300 + { { STATE_EXCSAVE2 }, 'i' }
5304 -Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5306 - unsigned tie_t = 0;
5307 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5308 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5311 +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
5312 + { { 6 /* art */ }, 'i' }
5316 -Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5319 - tie_t = (val << 31) >> 31;
5320 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5321 - tie_t = (val << 28) >> 29;
5322 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5324 +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
5325 + { { STATE_EXCSAVE2 }, 'o' }
5329 -Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5331 - unsigned tie_t = 0;
5332 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5333 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5336 +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
5337 + { { 6 /* art */ }, 'm' }
5341 -Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5344 - tie_t = (val << 31) >> 31;
5345 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5346 - tie_t = (val << 28) >> 29;
5347 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5349 +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
5350 + { { STATE_EXCSAVE2 }, 'm' }
5354 -Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5356 - unsigned tie_t = 0;
5357 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5358 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5361 +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = {
5362 + { { 6 /* art */ }, 'o' }
5366 -Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5369 - tie_t = (val << 31) >> 31;
5370 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5371 - tie_t = (val << 28) >> 29;
5372 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5374 +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = {
5375 + { { STATE_EPC3 }, 'i' }
5379 -Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5381 - unsigned tie_t = 0;
5382 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5383 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5386 +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = {
5387 + { { 6 /* art */ }, 'i' }
5391 -Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5394 - tie_t = (val << 31) >> 31;
5395 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5396 - tie_t = (val << 28) >> 29;
5397 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5399 +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = {
5400 + { { STATE_EPC3 }, 'o' }
5404 -Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5406 - unsigned tie_t = 0;
5407 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5408 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5411 +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = {
5412 + { { 6 /* art */ }, 'm' }
5416 -Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5419 - tie_t = (val << 31) >> 31;
5420 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5421 - tie_t = (val << 28) >> 29;
5422 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5424 +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = {
5425 + { { STATE_EPC3 }, 'm' }
5429 -Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5431 - unsigned tie_t = 0;
5432 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5433 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5436 +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = {
5437 + { { 6 /* art */ }, 'o' }
5441 -Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5444 - tie_t = (val << 31) >> 31;
5445 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5446 - tie_t = (val << 28) >> 29;
5447 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5449 +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = {
5450 + { { STATE_EXCSAVE3 }, 'i' }
5454 -Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5456 - unsigned tie_t = 0;
5457 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5458 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5461 +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = {
5462 + { { 6 /* art */ }, 'i' }
5466 -Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5469 - tie_t = (val << 31) >> 31;
5470 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5471 - tie_t = (val << 28) >> 29;
5472 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5474 +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = {
5475 + { { STATE_EXCSAVE3 }, 'o' }
5479 -Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5481 - unsigned tie_t = 0;
5482 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5483 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5486 +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = {
5487 + { { 6 /* art */ }, 'm' }
5491 -Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5494 - tie_t = (val << 31) >> 31;
5495 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5496 - tie_t = (val << 28) >> 29;
5497 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5499 +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = {
5500 + { { STATE_EXCSAVE3 }, 'm' }
5504 -Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5506 - unsigned tie_t = 0;
5507 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5508 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5511 +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = {
5512 + { { 6 /* art */ }, 'o' }
5516 -Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5519 - tie_t = (val << 31) >> 31;
5520 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5521 - tie_t = (val << 28) >> 29;
5522 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5524 +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = {
5525 + { { STATE_EPC4 }, 'i' }
5529 -Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5531 - unsigned tie_t = 0;
5532 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5533 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5536 +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = {
5537 + { { 6 /* art */ }, 'i' }
5541 -Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5544 - tie_t = (val << 31) >> 31;
5545 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5546 - tie_t = (val << 28) >> 29;
5547 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5549 +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = {
5550 + { { STATE_EPC4 }, 'o' }
5554 -Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5556 - unsigned tie_t = 0;
5557 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5558 - tie_t = (tie_t << 27) | ((insn[0] << 5) >> 5);
5561 +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = {
5562 + { { 6 /* art */ }, 'm' }
5566 -Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5569 - tie_t = (val << 5) >> 5;
5570 - insn[0] = (insn[0] & ~0x7ffffff) | (tie_t << 0);
5571 - tie_t = (val << 2) >> 29;
5572 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5574 +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = {
5575 + { { STATE_EPC4 }, 'm' }
5579 -Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
5581 - unsigned tie_t = 0;
5582 - tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
5585 +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = {
5586 + { { 6 /* art */ }, 'o' }
5590 -Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
5593 - tie_t = (val << 28) >> 28;
5594 - insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
5596 +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = {
5597 + { { STATE_EXCSAVE4 }, 'i' }
5601 -Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED,
5602 - uint32 val ATTRIBUTE_UNUSED)
5606 +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = {
5607 + { { 6 /* art */ }, 'i' }
5611 -Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
5615 +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = {
5616 + { { STATE_EXCSAVE4 }, 'o' }
5620 -Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
5624 +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = {
5625 + { { 6 /* art */ }, 'm' }
5629 -Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
5633 +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = {
5634 + { { STATE_EXCSAVE4 }, 'm' }
5638 -Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
5642 +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = {
5643 + { { 6 /* art */ }, 'o' }
5647 -Implicit_Field_mr0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
5651 +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = {
5652 + { { STATE_EPC5 }, 'i' }
5656 -Implicit_Field_mr1_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
5660 +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = {
5661 + { { 6 /* art */ }, 'i' }
5665 -Implicit_Field_mr2_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
5669 +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = {
5670 + { { STATE_EPC5 }, 'o' }
5674 -Implicit_Field_mr3_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
5678 +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = {
5679 + { { 6 /* art */ }, 'm' }
5683 -Implicit_Field_bt16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
5687 +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = {
5688 + { { STATE_EPC5 }, 'm' }
5692 -Implicit_Field_bs16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
5696 +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = {
5697 + { { 6 /* art */ }, 'o' }
5701 -Implicit_Field_br16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
5705 +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = {
5706 + { { STATE_EXCSAVE5 }, 'i' }
5710 -Implicit_Field_brall_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
5714 +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = {
5715 + { { 6 /* art */ }, 'i' }
5719 -/* Functional units. */
5720 +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = {
5721 + { { STATE_EXCSAVE5 }, 'o' }
5724 -static xtensa_funcUnit_internal funcUnits[] = {
5725 +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = {
5726 + { { 6 /* art */ }, 'm' }
5729 +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = {
5730 + { { STATE_EXCSAVE5 }, 'm' }
5734 -/* Register files. */
5735 +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
5736 + { { 6 /* art */ }, 'o' }
5739 -static xtensa_regfile_internal regfiles[] = {
5740 - { "AR", "a", 0, 32, 64 },
5741 - { "MR", "m", 1, 32, 4 },
5742 - { "BR", "b", 2, 1, 16 },
5743 - { "FR", "f", 3, 32, 16 },
5744 - { "BR2", "b", 2, 2, 8 },
5745 - { "BR4", "b", 2, 4, 4 },
5746 - { "BR8", "b", 2, 8, 2 },
5747 - { "BR16", "b", 2, 16, 1 }
5748 +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
5749 + { { STATE_EPS2 }, 'i' }
5754 +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
5755 + { { 6 /* art */ }, 'i' }
5758 -static xtensa_interface_internal interfaces[] = {
5759 +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
5760 + { { STATE_EPS2 }, 'o' }
5763 +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
5764 + { { 6 /* art */ }, 'm' }
5768 -/* Constant tables. */
5769 +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
5770 + { { STATE_EPS2 }, 'm' }
5773 -/* constant table ai4c */
5774 -static const unsigned CONST_TBL_ai4c_0[] = {
5792 +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = {
5793 + { { 6 /* art */ }, 'o' }
5796 -/* constant table b4c */
5797 -static const unsigned CONST_TBL_b4c_0[] = {
5815 +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = {
5816 + { { STATE_EPS3 }, 'i' }
5819 -/* constant table b4cu */
5820 -static const unsigned CONST_TBL_b4cu_0[] = {
5838 +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = {
5839 + { { 6 /* art */ }, 'i' }
5843 -/* Instruction operands. */
5846 -Operand_soffsetx4_decode (uint32 *valp)
5848 - unsigned soffsetx4_0, offset_0;
5849 - offset_0 = *valp & 0x3ffff;
5850 - soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2);
5851 - *valp = soffsetx4_0;
5854 +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = {
5855 + { { STATE_EPS3 }, 'o' }
5859 -Operand_soffsetx4_encode (uint32 *valp)
5861 - unsigned offset_0, soffsetx4_0;
5862 - soffsetx4_0 = *valp;
5863 - offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff;
5867 +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = {
5868 + { { 6 /* art */ }, 'm' }
5872 -Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
5874 - *valp -= (pc & ~0x3);
5877 +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = {
5878 + { { STATE_EPS3 }, 'm' }
5882 -Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
5884 - *valp += (pc & ~0x3);
5887 +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = {
5888 + { { 6 /* art */ }, 'o' }
5892 -Operand_uimm12x8_decode (uint32 *valp)
5894 - unsigned uimm12x8_0, imm12_0;
5895 - imm12_0 = *valp & 0xfff;
5896 - uimm12x8_0 = imm12_0 << 3;
5897 - *valp = uimm12x8_0;
5900 +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = {
5901 + { { STATE_EPS4 }, 'i' }
5905 -Operand_uimm12x8_encode (uint32 *valp)
5907 - unsigned imm12_0, uimm12x8_0;
5908 - uimm12x8_0 = *valp;
5909 - imm12_0 = ((uimm12x8_0 >> 3) & 0xfff);
5913 +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = {
5914 + { { 6 /* art */ }, 'i' }
5918 -Operand_simm4_decode (uint32 *valp)
5920 - unsigned simm4_0, mn_0;
5921 - mn_0 = *valp & 0xf;
5922 - simm4_0 = ((int) mn_0 << 28) >> 28;
5926 +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = {
5927 + { { STATE_EPS4 }, 'o' }
5931 -Operand_simm4_encode (uint32 *valp)
5933 - unsigned mn_0, simm4_0;
5935 - mn_0 = (simm4_0 & 0xf);
5939 +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = {
5940 + { { 6 /* art */ }, 'm' }
5944 -Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED)
5948 +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = {
5949 + { { STATE_EPS4 }, 'm' }
5953 -Operand_arr_encode (uint32 *valp)
5956 - error = (*valp & ~0xf) != 0;
5959 +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = {
5960 + { { 6 /* art */ }, 'o' }
5964 -Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED)
5968 +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = {
5969 + { { STATE_EPS5 }, 'i' }
5973 -Operand_ars_encode (uint32 *valp)
5976 - error = (*valp & ~0xf) != 0;
5979 +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = {
5980 + { { 6 /* art */ }, 'i' }
5984 -Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED)
5988 +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = {
5989 + { { STATE_EPS5 }, 'o' }
5993 -Operand_art_encode (uint32 *valp)
5996 - error = (*valp & ~0xf) != 0;
5999 +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = {
6000 + { { 6 /* art */ }, 'm' }
6004 -Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED)
6008 +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = {
6009 + { { STATE_EPS5 }, 'm' }
6013 -Operand_ar0_encode (uint32 *valp)
6016 - error = (*valp & ~0x3f) != 0;
6019 +static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
6020 + { { 6 /* art */ }, 'o' }
6024 -Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED)
6028 +static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
6029 + { { STATE_EXCVADDR }, 'i' }
6033 -Operand_ar4_encode (uint32 *valp)
6036 - error = (*valp & ~0x3f) != 0;
6039 +static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
6040 + { { 6 /* art */ }, 'i' }
6044 -Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED)
6048 +static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
6049 + { { STATE_EXCVADDR }, 'o' }
6053 -Operand_ar8_encode (uint32 *valp)
6056 - error = (*valp & ~0x3f) != 0;
6059 +static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
6060 + { { 6 /* art */ }, 'm' }
6064 -Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED)
6068 +static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
6069 + { { STATE_EXCVADDR }, 'm' }
6073 -Operand_ar12_encode (uint32 *valp)
6076 - error = (*valp & ~0x3f) != 0;
6079 +static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
6080 + { { 6 /* art */ }, 'o' }
6084 -Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED)
6088 +static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
6089 + { { STATE_DEPC }, 'i' }
6093 -Operand_ars_entry_encode (uint32 *valp)
6096 - error = (*valp & ~0x3f) != 0;
6099 +static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
6100 + { { 6 /* art */ }, 'i' }
6104 -Operand_immrx4_decode (uint32 *valp)
6106 - unsigned immrx4_0, r_0;
6107 - r_0 = *valp & 0xf;
6108 - immrx4_0 = (((0xfffffff) << 4) | r_0) << 2;
6112 +static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
6113 + { { STATE_DEPC }, 'o' }
6117 -Operand_immrx4_encode (uint32 *valp)
6119 - unsigned r_0, immrx4_0;
6121 - r_0 = ((immrx4_0 >> 2) & 0xf);
6125 +static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
6126 + { { 6 /* art */ }, 'm' }
6130 -Operand_lsi4x4_decode (uint32 *valp)
6132 - unsigned lsi4x4_0, r_0;
6133 - r_0 = *valp & 0xf;
6134 - lsi4x4_0 = r_0 << 2;
6138 +static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
6139 + { { STATE_DEPC }, 'm' }
6143 -Operand_lsi4x4_encode (uint32 *valp)
6145 - unsigned r_0, lsi4x4_0;
6147 - r_0 = ((lsi4x4_0 >> 2) & 0xf);
6151 +static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
6152 + { { 6 /* art */ }, 'o' }
6156 -Operand_simm7_decode (uint32 *valp)
6158 - unsigned simm7_0, imm7_0;
6159 - imm7_0 = *valp & 0x7f;
6160 - simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0;
6164 +static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
6165 + { { STATE_EXCCAUSE }, 'i' },
6166 + { { STATE_XTSYNC }, 'i' }
6170 -Operand_simm7_encode (uint32 *valp)
6172 - unsigned imm7_0, simm7_0;
6174 - imm7_0 = (simm7_0 & 0x7f);
6178 +static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
6179 + { { 6 /* art */ }, 'i' }
6183 -Operand_uimm6_decode (uint32 *valp)
6185 - unsigned uimm6_0, imm6_0;
6186 - imm6_0 = *valp & 0x3f;
6187 - uimm6_0 = 0x4 + (((0) << 6) | imm6_0);
6191 +static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
6192 + { { STATE_EXCCAUSE }, 'o' }
6196 -Operand_uimm6_encode (uint32 *valp)
6198 - unsigned imm6_0, uimm6_0;
6200 - imm6_0 = (uimm6_0 - 0x4) & 0x3f;
6204 +static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
6205 + { { 6 /* art */ }, 'm' }
6209 -Operand_uimm6_ator (uint32 *valp, uint32 pc)
6214 +static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
6215 + { { STATE_EXCCAUSE }, 'm' }
6219 -Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
6224 +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = {
6225 + { { 6 /* art */ }, 'o' }
6229 -Operand_ai4const_decode (uint32 *valp)
6231 - unsigned ai4const_0, t_0;
6232 - t_0 = *valp & 0xf;
6233 - ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf];
6234 - *valp = ai4const_0;
6237 +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = {
6238 + { { STATE_MISC0 }, 'i' }
6242 -Operand_ai4const_encode (uint32 *valp)
6244 - unsigned t_0, ai4const_0;
6245 - ai4const_0 = *valp;
6246 - switch (ai4const_0)
6248 - case 0xffffffff: t_0 = 0; break;
6249 - case 0x1: t_0 = 0x1; break;
6250 - case 0x2: t_0 = 0x2; break;
6251 - case 0x3: t_0 = 0x3; break;
6252 - case 0x4: t_0 = 0x4; break;
6253 - case 0x5: t_0 = 0x5; break;
6254 - case 0x6: t_0 = 0x6; break;
6255 - case 0x7: t_0 = 0x7; break;
6256 - case 0x8: t_0 = 0x8; break;
6257 - case 0x9: t_0 = 0x9; break;
6258 - case 0xa: t_0 = 0xa; break;
6259 - case 0xb: t_0 = 0xb; break;
6260 - case 0xc: t_0 = 0xc; break;
6261 - case 0xd: t_0 = 0xd; break;
6262 - case 0xe: t_0 = 0xe; break;
6263 - default: t_0 = 0xf; break;
6268 +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = {
6269 + { { 6 /* art */ }, 'i' }
6273 -Operand_b4const_decode (uint32 *valp)
6275 - unsigned b4const_0, r_0;
6276 - r_0 = *valp & 0xf;
6277 - b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf];
6278 - *valp = b4const_0;
6281 +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = {
6282 + { { STATE_MISC0 }, 'o' }
6286 -Operand_b4const_encode (uint32 *valp)
6288 - unsigned r_0, b4const_0;
6289 - b4const_0 = *valp;
6290 - switch (b4const_0)
6292 - case 0xffffffff: r_0 = 0; break;
6293 - case 0x1: r_0 = 0x1; break;
6294 - case 0x2: r_0 = 0x2; break;
6295 - case 0x3: r_0 = 0x3; break;
6296 - case 0x4: r_0 = 0x4; break;
6297 - case 0x5: r_0 = 0x5; break;
6298 - case 0x6: r_0 = 0x6; break;
6299 - case 0x7: r_0 = 0x7; break;
6300 - case 0x8: r_0 = 0x8; break;
6301 - case 0xa: r_0 = 0x9; break;
6302 - case 0xc: r_0 = 0xa; break;
6303 - case 0x10: r_0 = 0xb; break;
6304 - case 0x20: r_0 = 0xc; break;
6305 - case 0x40: r_0 = 0xd; break;
6306 - case 0x80: r_0 = 0xe; break;
6307 - default: r_0 = 0xf; break;
6312 +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = {
6313 + { { 6 /* art */ }, 'm' }
6317 -Operand_b4constu_decode (uint32 *valp)
6319 - unsigned b4constu_0, r_0;
6320 - r_0 = *valp & 0xf;
6321 - b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf];
6322 - *valp = b4constu_0;
6325 +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = {
6326 + { { STATE_MISC0 }, 'm' }
6330 -Operand_b4constu_encode (uint32 *valp)
6332 - unsigned r_0, b4constu_0;
6333 - b4constu_0 = *valp;
6334 - switch (b4constu_0)
6336 - case 0x8000: r_0 = 0; break;
6337 - case 0x10000: r_0 = 0x1; break;
6338 - case 0x2: r_0 = 0x2; break;
6339 - case 0x3: r_0 = 0x3; break;
6340 - case 0x4: r_0 = 0x4; break;
6341 - case 0x5: r_0 = 0x5; break;
6342 - case 0x6: r_0 = 0x6; break;
6343 - case 0x7: r_0 = 0x7; break;
6344 - case 0x8: r_0 = 0x8; break;
6345 - case 0xa: r_0 = 0x9; break;
6346 - case 0xc: r_0 = 0xa; break;
6347 - case 0x10: r_0 = 0xb; break;
6348 - case 0x20: r_0 = 0xc; break;
6349 - case 0x40: r_0 = 0xd; break;
6350 - case 0x80: r_0 = 0xe; break;
6351 - default: r_0 = 0xf; break;
6356 +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = {
6357 + { { 6 /* art */ }, 'o' }
6361 -Operand_uimm8_decode (uint32 *valp)
6363 - unsigned uimm8_0, imm8_0;
6364 - imm8_0 = *valp & 0xff;
6369 +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = {
6370 + { { STATE_MISC1 }, 'i' }
6374 -Operand_uimm8_encode (uint32 *valp)
6376 - unsigned imm8_0, uimm8_0;
6378 - imm8_0 = (uimm8_0 & 0xff);
6382 +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = {
6383 + { { 6 /* art */ }, 'i' }
6387 -Operand_uimm8x2_decode (uint32 *valp)
6389 - unsigned uimm8x2_0, imm8_0;
6390 - imm8_0 = *valp & 0xff;
6391 - uimm8x2_0 = imm8_0 << 1;
6392 - *valp = uimm8x2_0;
6395 +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = {
6396 + { { STATE_MISC1 }, 'o' }
6400 -Operand_uimm8x2_encode (uint32 *valp)
6402 - unsigned imm8_0, uimm8x2_0;
6403 - uimm8x2_0 = *valp;
6404 - imm8_0 = ((uimm8x2_0 >> 1) & 0xff);
6408 +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = {
6409 + { { 6 /* art */ }, 'm' }
6413 -Operand_uimm8x4_decode (uint32 *valp)
6415 - unsigned uimm8x4_0, imm8_0;
6416 - imm8_0 = *valp & 0xff;
6417 - uimm8x4_0 = imm8_0 << 2;
6418 - *valp = uimm8x4_0;
6421 +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = {
6422 + { { STATE_MISC1 }, 'm' }
6426 -Operand_uimm8x4_encode (uint32 *valp)
6428 - unsigned imm8_0, uimm8x4_0;
6429 - uimm8x4_0 = *valp;
6430 - imm8_0 = ((uimm8x4_0 >> 2) & 0xff);
6434 +static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
6435 + { { 6 /* art */ }, 'o' }
6439 -Operand_uimm4x16_decode (uint32 *valp)
6441 - unsigned uimm4x16_0, op2_0;
6442 - op2_0 = *valp & 0xf;
6443 - uimm4x16_0 = op2_0 << 4;
6444 - *valp = uimm4x16_0;
6447 +static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = {
6448 + { { 6 /* art */ }, 'o' }
6452 -Operand_uimm4x16_encode (uint32 *valp)
6454 - unsigned op2_0, uimm4x16_0;
6455 - uimm4x16_0 = *valp;
6456 - op2_0 = ((uimm4x16_0 >> 4) & 0xf);
6460 +static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = {
6461 + { { STATE_VECBASE }, 'i' }
6465 -Operand_simm8_decode (uint32 *valp)
6467 - unsigned simm8_0, imm8_0;
6468 - imm8_0 = *valp & 0xff;
6469 - simm8_0 = ((int) imm8_0 << 24) >> 24;
6473 +static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = {
6474 + { { 6 /* art */ }, 'i' }
6478 -Operand_simm8_encode (uint32 *valp)
6480 - unsigned imm8_0, simm8_0;
6482 - imm8_0 = (simm8_0 & 0xff);
6486 +static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = {
6487 + { { STATE_VECBASE }, 'o' }
6491 -Operand_simm8x256_decode (uint32 *valp)
6493 - unsigned simm8x256_0, imm8_0;
6494 - imm8_0 = *valp & 0xff;
6495 - simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8;
6496 - *valp = simm8x256_0;
6499 +static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = {
6500 + { { 6 /* art */ }, 'm' }
6504 -Operand_simm8x256_encode (uint32 *valp)
6506 - unsigned imm8_0, simm8x256_0;
6507 - simm8x256_0 = *valp;
6508 - imm8_0 = ((simm8x256_0 >> 8) & 0xff);
6512 +static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = {
6513 + { { STATE_VECBASE }, 'm' }
6517 -Operand_simm12b_decode (uint32 *valp)
6519 - unsigned simm12b_0, imm12b_0;
6520 - imm12b_0 = *valp & 0xfff;
6521 - simm12b_0 = ((int) imm12b_0 << 20) >> 20;
6522 - *valp = simm12b_0;
6525 +static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
6526 + { { 43 /* s */ }, 'i' }
6530 -Operand_simm12b_encode (uint32 *valp)
6532 - unsigned imm12b_0, simm12b_0;
6533 - simm12b_0 = *valp;
6534 - imm12b_0 = (simm12b_0 & 0xfff);
6538 +static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
6539 + { { STATE_PSWOE }, 'o' },
6540 + { { STATE_PSCALLINC }, 'o' },
6541 + { { STATE_PSOWB }, 'o' },
6542 + { { STATE_PSUM }, 'o' },
6543 + { { STATE_PSEXCM }, 'o' },
6544 + { { STATE_PSINTLEVEL }, 'o' },
6545 + { { STATE_EPC1 }, 'i' },
6546 + { { STATE_EPC2 }, 'i' },
6547 + { { STATE_EPC3 }, 'i' },
6548 + { { STATE_EPC4 }, 'i' },
6549 + { { STATE_EPC5 }, 'i' },
6550 + { { STATE_EPS2 }, 'i' },
6551 + { { STATE_EPS3 }, 'i' },
6552 + { { STATE_EPS4 }, 'i' },
6553 + { { STATE_EPS5 }, 'i' },
6554 + { { STATE_InOCDMode }, 'm' }
6558 -Operand_msalp32_decode (uint32 *valp)
6560 - unsigned msalp32_0, sal_0;
6561 - sal_0 = *valp & 0x1f;
6562 - msalp32_0 = 0x20 - sal_0;
6563 - *valp = msalp32_0;
6566 +static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
6567 + { { 43 /* s */ }, 'i' }
6571 -Operand_msalp32_encode (uint32 *valp)
6573 - unsigned sal_0, msalp32_0;
6574 - msalp32_0 = *valp;
6575 - sal_0 = (0x20 - msalp32_0) & 0x1f;
6579 +static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
6580 + { { STATE_PSINTLEVEL }, 'o' }
6584 -Operand_op2p1_decode (uint32 *valp)
6586 - unsigned op2p1_0, op2_0;
6587 - op2_0 = *valp & 0xf;
6588 - op2p1_0 = op2_0 + 0x1;
6592 +static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
6593 + { { 6 /* art */ }, 'o' }
6597 -Operand_op2p1_encode (uint32 *valp)
6599 - unsigned op2_0, op2p1_0;
6601 - op2_0 = (op2p1_0 - 0x1) & 0xf;
6605 +static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
6606 + { { STATE_INTERRUPT }, 'i' }
6610 -Operand_label8_decode (uint32 *valp)
6612 - unsigned label8_0, imm8_0;
6613 - imm8_0 = *valp & 0xff;
6614 - label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24);
6618 +static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
6619 + { { 6 /* art */ }, 'i' }
6623 -Operand_label8_encode (uint32 *valp)
6625 - unsigned imm8_0, label8_0;
6627 - imm8_0 = (label8_0 - 0x4) & 0xff;
6631 +static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
6632 + { { STATE_XTSYNC }, 'o' },
6633 + { { STATE_INTERRUPT }, 'm' }
6637 -Operand_label8_ator (uint32 *valp, uint32 pc)
6642 +static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
6643 + { { 6 /* art */ }, 'i' }
6647 -Operand_label8_rtoa (uint32 *valp, uint32 pc)
6654 -Operand_ulabel8_decode (uint32 *valp)
6656 - unsigned ulabel8_0, imm8_0;
6657 - imm8_0 = *valp & 0xff;
6658 - ulabel8_0 = 0x4 + (((0) << 8) | imm8_0);
6659 - *valp = ulabel8_0;
6662 +static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
6663 + { { STATE_XTSYNC }, 'o' },
6664 + { { STATE_INTERRUPT }, 'm' }
6668 -Operand_ulabel8_encode (uint32 *valp)
6670 - unsigned imm8_0, ulabel8_0;
6671 - ulabel8_0 = *valp;
6672 - imm8_0 = (ulabel8_0 - 0x4) & 0xff;
6676 +static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
6677 + { { 6 /* art */ }, 'o' }
6681 -Operand_ulabel8_ator (uint32 *valp, uint32 pc)
6686 +static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
6687 + { { STATE_INTENABLE }, 'i' }
6691 -Operand_ulabel8_rtoa (uint32 *valp, uint32 pc)
6696 +static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
6697 + { { 6 /* art */ }, 'i' }
6701 -Operand_label12_decode (uint32 *valp)
6703 - unsigned label12_0, imm12_0;
6704 - imm12_0 = *valp & 0xfff;
6705 - label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20);
6706 - *valp = label12_0;
6709 +static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
6710 + { { STATE_INTENABLE }, 'o' }
6714 -Operand_label12_encode (uint32 *valp)
6716 - unsigned imm12_0, label12_0;
6717 - label12_0 = *valp;
6718 - imm12_0 = (label12_0 - 0x4) & 0xfff;
6722 +static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
6723 + { { 6 /* art */ }, 'm' }
6727 -Operand_label12_ator (uint32 *valp, uint32 pc)
6732 +static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
6733 + { { STATE_INTENABLE }, 'm' }
6737 -Operand_label12_rtoa (uint32 *valp, uint32 pc)
6742 +static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
6743 + { { 34 /* imms */ }, 'i' },
6744 + { { 33 /* immt */ }, 'i' }
6748 -Operand_soffset_decode (uint32 *valp)
6750 - unsigned soffset_0, offset_0;
6751 - offset_0 = *valp & 0x3ffff;
6752 - soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14);
6753 - *valp = soffset_0;
6756 +static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
6757 + { { STATE_PSEXCM }, 'i' },
6758 + { { STATE_PSINTLEVEL }, 'i' }
6762 -Operand_soffset_encode (uint32 *valp)
6764 - unsigned offset_0, soffset_0;
6765 - soffset_0 = *valp;
6766 - offset_0 = (soffset_0 - 0x4) & 0x3ffff;
6770 +static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
6771 + { { 34 /* imms */ }, 'i' }
6775 -Operand_soffset_ator (uint32 *valp, uint32 pc)
6780 +static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
6781 + { { STATE_PSEXCM }, 'i' },
6782 + { { STATE_PSINTLEVEL }, 'i' }
6786 -Operand_soffset_rtoa (uint32 *valp, uint32 pc)
6791 +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = {
6792 + { { 6 /* art */ }, 'o' }
6796 -Operand_uimm16x4_decode (uint32 *valp)
6798 - unsigned uimm16x4_0, imm16_0;
6799 - imm16_0 = *valp & 0xffff;
6800 - uimm16x4_0 = (((0xffff) << 16) | imm16_0) << 2;
6801 - *valp = uimm16x4_0;
6804 +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = {
6805 + { { STATE_DBREAKA0 }, 'i' }
6809 -Operand_uimm16x4_encode (uint32 *valp)
6811 - unsigned imm16_0, uimm16x4_0;
6812 - uimm16x4_0 = *valp;
6813 - imm16_0 = (uimm16x4_0 >> 2) & 0xffff;
6817 +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = {
6818 + { { 6 /* art */ }, 'i' }
6822 -Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
6824 - *valp -= ((pc + 3) & ~0x3);
6827 +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = {
6828 + { { STATE_DBREAKA0 }, 'o' },
6829 + { { STATE_XTSYNC }, 'o' }
6833 -Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
6835 - *valp += ((pc + 3) & ~0x3);
6838 +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = {
6839 + { { 6 /* art */ }, 'm' }
6843 -Operand_mx_decode (uint32 *valp ATTRIBUTE_UNUSED)
6847 +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = {
6848 + { { STATE_DBREAKA0 }, 'm' },
6849 + { { STATE_XTSYNC }, 'o' }
6853 -Operand_mx_encode (uint32 *valp)
6856 - error = (*valp & ~0x3) != 0;
6859 +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = {
6860 + { { 6 /* art */ }, 'o' }
6864 -Operand_my_decode (uint32 *valp)
6869 +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = {
6870 + { { STATE_DBREAKC0 }, 'i' }
6874 -Operand_my_encode (uint32 *valp)
6877 - error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0);
6878 - *valp = *valp & 1;
6881 +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = {
6882 + { { 6 /* art */ }, 'i' }
6886 -Operand_mw_decode (uint32 *valp ATTRIBUTE_UNUSED)
6890 +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = {
6891 + { { STATE_DBREAKC0 }, 'o' },
6892 + { { STATE_XTSYNC }, 'o' }
6896 -Operand_mw_encode (uint32 *valp)
6899 - error = (*valp & ~0x3) != 0;
6902 +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = {
6903 + { { 6 /* art */ }, 'm' }
6907 -Operand_mr0_decode (uint32 *valp ATTRIBUTE_UNUSED)
6911 +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = {
6912 + { { STATE_DBREAKC0 }, 'm' },
6913 + { { STATE_XTSYNC }, 'o' }
6917 -Operand_mr0_encode (uint32 *valp)
6920 - error = (*valp & ~0x3) != 0;
6923 +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = {
6924 + { { 6 /* art */ }, 'o' }
6928 -Operand_mr1_decode (uint32 *valp ATTRIBUTE_UNUSED)
6932 +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = {
6933 + { { STATE_DBREAKA1 }, 'i' }
6937 -Operand_mr1_encode (uint32 *valp)
6940 - error = (*valp & ~0x3) != 0;
6943 +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = {
6944 + { { 6 /* art */ }, 'i' }
6948 -Operand_mr2_decode (uint32 *valp ATTRIBUTE_UNUSED)
6954 -Operand_mr2_encode (uint32 *valp)
6957 - error = (*valp & ~0x3) != 0;
6960 +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = {
6961 + { { STATE_DBREAKA1 }, 'o' },
6962 + { { STATE_XTSYNC }, 'o' }
6966 -Operand_mr3_decode (uint32 *valp ATTRIBUTE_UNUSED)
6970 +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = {
6971 + { { 6 /* art */ }, 'm' }
6975 -Operand_mr3_encode (uint32 *valp)
6978 - error = (*valp & ~0x3) != 0;
6981 +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = {
6982 + { { STATE_DBREAKA1 }, 'm' },
6983 + { { STATE_XTSYNC }, 'o' }
6987 -Operand_immt_decode (uint32 *valp)
6989 - unsigned immt_0, t_0;
6990 - t_0 = *valp & 0xf;
6995 +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = {
6996 + { { 6 /* art */ }, 'o' }
7000 -Operand_immt_encode (uint32 *valp)
7002 - unsigned t_0, immt_0;
7004 - t_0 = immt_0 & 0xf;
7008 +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = {
7009 + { { STATE_DBREAKC1 }, 'i' }
7013 -Operand_imms_decode (uint32 *valp)
7015 - unsigned imms_0, s_0;
7016 - s_0 = *valp & 0xf;
7021 +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = {
7022 + { { 6 /* art */ }, 'i' }
7026 -Operand_imms_encode (uint32 *valp)
7028 - unsigned s_0, imms_0;
7030 - s_0 = imms_0 & 0xf;
7034 +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = {
7035 + { { STATE_DBREAKC1 }, 'o' },
7036 + { { STATE_XTSYNC }, 'o' }
7040 -Operand_bt_decode (uint32 *valp ATTRIBUTE_UNUSED)
7044 +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = {
7045 + { { 6 /* art */ }, 'm' }
7049 -Operand_bt_encode (uint32 *valp)
7052 - error = (*valp & ~0xf) != 0;
7055 +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = {
7056 + { { STATE_DBREAKC1 }, 'm' },
7057 + { { STATE_XTSYNC }, 'o' }
7061 -Operand_bs_decode (uint32 *valp ATTRIBUTE_UNUSED)
7065 +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = {
7066 + { { 6 /* art */ }, 'o' }
7070 -Operand_bs_encode (uint32 *valp)
7073 - error = (*valp & ~0xf) != 0;
7076 +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = {
7077 + { { STATE_IBREAKA0 }, 'i' }
7081 -Operand_br_decode (uint32 *valp ATTRIBUTE_UNUSED)
7085 +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = {
7086 + { { 6 /* art */ }, 'i' }
7090 -Operand_br_encode (uint32 *valp)
7093 - error = (*valp & ~0xf) != 0;
7096 +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = {
7097 + { { STATE_IBREAKA0 }, 'o' }
7101 -Operand_bt2_decode (uint32 *valp)
7103 - *valp = *valp << 1;
7106 +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = {
7107 + { { 6 /* art */ }, 'm' }
7111 -Operand_bt2_encode (uint32 *valp)
7114 - error = (*valp & ~(0x7 << 1)) != 0;
7115 - *valp = *valp >> 1;
7118 +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = {
7119 + { { STATE_IBREAKA0 }, 'm' }
7123 -Operand_bs2_decode (uint32 *valp)
7125 - *valp = *valp << 1;
7128 +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = {
7129 + { { 6 /* art */ }, 'o' }
7133 -Operand_bs2_encode (uint32 *valp)
7136 - error = (*valp & ~(0x7 << 1)) != 0;
7137 - *valp = *valp >> 1;
7140 +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = {
7141 + { { STATE_IBREAKA1 }, 'i' }
7145 -Operand_br2_decode (uint32 *valp)
7147 - *valp = *valp << 1;
7150 +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = {
7151 + { { 6 /* art */ }, 'i' }
7155 -Operand_br2_encode (uint32 *valp)
7158 - error = (*valp & ~(0x7 << 1)) != 0;
7159 - *valp = *valp >> 1;
7162 +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = {
7163 + { { STATE_IBREAKA1 }, 'o' }
7167 -Operand_bt4_decode (uint32 *valp)
7169 - *valp = *valp << 2;
7172 +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = {
7173 + { { 6 /* art */ }, 'm' }
7177 -Operand_bt4_encode (uint32 *valp)
7180 - error = (*valp & ~(0x3 << 2)) != 0;
7181 - *valp = *valp >> 2;
7184 +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = {
7185 + { { STATE_IBREAKA1 }, 'm' }
7189 -Operand_bs4_decode (uint32 *valp)
7191 - *valp = *valp << 2;
7194 +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = {
7195 + { { 6 /* art */ }, 'o' }
7199 -Operand_bs4_encode (uint32 *valp)
7202 - error = (*valp & ~(0x3 << 2)) != 0;
7203 - *valp = *valp >> 2;
7206 +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = {
7207 + { { STATE_IBREAKENABLE }, 'i' }
7211 -Operand_br4_decode (uint32 *valp)
7213 - *valp = *valp << 2;
7216 +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = {
7217 + { { 6 /* art */ }, 'i' }
7221 -Operand_br4_encode (uint32 *valp)
7224 - error = (*valp & ~(0x3 << 2)) != 0;
7225 - *valp = *valp >> 2;
7228 +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = {
7229 + { { STATE_IBREAKENABLE }, 'o' }
7233 -Operand_bt8_decode (uint32 *valp)
7235 - *valp = *valp << 3;
7238 +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = {
7239 + { { 6 /* art */ }, 'm' }
7243 -Operand_bt8_encode (uint32 *valp)
7246 - error = (*valp & ~(0x1 << 3)) != 0;
7247 - *valp = *valp >> 3;
7250 +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = {
7251 + { { STATE_IBREAKENABLE }, 'm' }
7255 -Operand_bs8_decode (uint32 *valp)
7257 - *valp = *valp << 3;
7260 +static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = {
7261 + { { 6 /* art */ }, 'o' }
7265 -Operand_bs8_encode (uint32 *valp)
7268 - error = (*valp & ~(0x1 << 3)) != 0;
7269 - *valp = *valp >> 3;
7272 +static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = {
7273 + { { STATE_DEBUGCAUSE }, 'i' },
7274 + { { STATE_DBNUM }, 'i' }
7278 -Operand_br8_decode (uint32 *valp)
7280 - *valp = *valp << 3;
7283 +static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = {
7284 + { { 6 /* art */ }, 'i' }
7288 -Operand_br8_encode (uint32 *valp)
7291 - error = (*valp & ~(0x1 << 3)) != 0;
7292 - *valp = *valp >> 3;
7295 +static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = {
7296 + { { STATE_DEBUGCAUSE }, 'o' },
7297 + { { STATE_DBNUM }, 'o' }
7301 -Operand_bt16_decode (uint32 *valp)
7303 - *valp = *valp << 4;
7306 +static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = {
7307 + { { 6 /* art */ }, 'm' }
7311 -Operand_bt16_encode (uint32 *valp)
7314 - error = (*valp & ~(0 << 4)) != 0;
7315 - *valp = *valp >> 4;
7318 +static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = {
7319 + { { STATE_DEBUGCAUSE }, 'm' },
7320 + { { STATE_DBNUM }, 'm' }
7324 -Operand_bs16_decode (uint32 *valp)
7326 - *valp = *valp << 4;
7329 +static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = {
7330 + { { 6 /* art */ }, 'o' }
7334 -Operand_bs16_encode (uint32 *valp)
7337 - error = (*valp & ~(0 << 4)) != 0;
7338 - *valp = *valp >> 4;
7341 +static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = {
7342 + { { STATE_ICOUNT }, 'i' }
7346 -Operand_br16_decode (uint32 *valp)
7348 - *valp = *valp << 4;
7351 +static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = {
7352 + { { 6 /* art */ }, 'i' }
7356 -Operand_br16_encode (uint32 *valp)
7359 - error = (*valp & ~(0 << 4)) != 0;
7360 - *valp = *valp >> 4;
7363 +static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = {
7364 + { { STATE_XTSYNC }, 'o' },
7365 + { { STATE_ICOUNT }, 'o' }
7369 -Operand_brall_decode (uint32 *valp)
7371 - *valp = *valp << 4;
7374 +static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = {
7375 + { { 6 /* art */ }, 'm' }
7379 -Operand_brall_encode (uint32 *valp)
7382 - error = (*valp & ~(0 << 4)) != 0;
7383 - *valp = *valp >> 4;
7386 +static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = {
7387 + { { STATE_XTSYNC }, 'o' },
7388 + { { STATE_ICOUNT }, 'm' }
7392 -Operand_tp7_decode (uint32 *valp)
7394 - unsigned tp7_0, t_0;
7395 - t_0 = *valp & 0xf;
7396 - tp7_0 = t_0 + 0x7;
7400 +static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = {
7401 + { { 6 /* art */ }, 'o' }
7405 -Operand_tp7_encode (uint32 *valp)
7407 - unsigned t_0, tp7_0;
7409 - t_0 = (tp7_0 - 0x7) & 0xf;
7413 +static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = {
7414 + { { STATE_ICOUNTLEVEL }, 'i' }
7418 -Operand_xt_wbr15_label_decode (uint32 *valp)
7420 - unsigned xt_wbr15_label_0, xt_wbr15_imm_0;
7421 - xt_wbr15_imm_0 = *valp & 0x7fff;
7422 - xt_wbr15_label_0 = 0x4 + (((int) xt_wbr15_imm_0 << 17) >> 17);
7423 - *valp = xt_wbr15_label_0;
7426 +static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = {
7427 + { { 6 /* art */ }, 'i' }
7431 -Operand_xt_wbr15_label_encode (uint32 *valp)
7433 - unsigned xt_wbr15_imm_0, xt_wbr15_label_0;
7434 - xt_wbr15_label_0 = *valp;
7435 - xt_wbr15_imm_0 = (xt_wbr15_label_0 - 0x4) & 0x7fff;
7436 - *valp = xt_wbr15_imm_0;
7439 +static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = {
7440 + { { STATE_ICOUNTLEVEL }, 'o' }
7444 -Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc)
7449 +static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = {
7450 + { { 6 /* art */ }, 'm' }
7454 -Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc)
7459 +static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = {
7460 + { { STATE_ICOUNTLEVEL }, 'm' }
7464 -Operand_xt_wbr18_label_decode (uint32 *valp)
7466 - unsigned xt_wbr18_label_0, xt_wbr18_imm_0;
7467 - xt_wbr18_imm_0 = *valp & 0x3ffff;
7468 - xt_wbr18_label_0 = 0x4 + (((int) xt_wbr18_imm_0 << 14) >> 14);
7469 - *valp = xt_wbr18_label_0;
7472 +static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = {
7473 + { { 6 /* art */ }, 'o' }
7477 -Operand_xt_wbr18_label_encode (uint32 *valp)
7479 - unsigned xt_wbr18_imm_0, xt_wbr18_label_0;
7480 - xt_wbr18_label_0 = *valp;
7481 - xt_wbr18_imm_0 = (xt_wbr18_label_0 - 0x4) & 0x3ffff;
7482 - *valp = xt_wbr18_imm_0;
7485 +static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = {
7486 + { { STATE_DDR }, 'i' }
7490 -Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc)
7495 +static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = {
7496 + { { 6 /* art */ }, 'i' }
7500 -Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc)
7505 +static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = {
7506 + { { STATE_XTSYNC }, 'o' },
7507 + { { STATE_DDR }, 'o' }
7511 -Operand_cimm8x4_decode (uint32 *valp)
7513 - unsigned cimm8x4_0, imm8_0;
7514 - imm8_0 = *valp & 0xff;
7515 - cimm8x4_0 = (imm8_0 << 2) | 0;
7516 - *valp = cimm8x4_0;
7519 +static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = {
7520 + { { 6 /* art */ }, 'm' }
7524 -Operand_cimm8x4_encode (uint32 *valp)
7526 - unsigned imm8_0, cimm8x4_0;
7527 - cimm8x4_0 = *valp;
7528 - imm8_0 = (cimm8x4_0 >> 2) & 0xff;
7532 +static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = {
7533 + { { STATE_XTSYNC }, 'o' },
7534 + { { STATE_DDR }, 'm' }
7538 -Operand_frr_decode (uint32 *valp ATTRIBUTE_UNUSED)
7542 +static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = {
7543 + { { 34 /* imms */ }, 'i' }
7547 -Operand_frr_encode (uint32 *valp)
7550 - error = (*valp & ~0xf) != 0;
7553 +static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = {
7554 + { { STATE_InOCDMode }, 'm' },
7555 + { { STATE_EPC4 }, 'i' },
7556 + { { STATE_PSWOE }, 'o' },
7557 + { { STATE_PSCALLINC }, 'o' },
7558 + { { STATE_PSOWB }, 'o' },
7559 + { { STATE_PSUM }, 'o' },
7560 + { { STATE_PSEXCM }, 'o' },
7561 + { { STATE_PSINTLEVEL }, 'o' },
7562 + { { STATE_EPS4 }, 'i' }
7566 -Operand_frs_decode (uint32 *valp ATTRIBUTE_UNUSED)
7570 +static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = {
7571 + { { STATE_InOCDMode }, 'm' }
7575 -Operand_frs_encode (uint32 *valp)
7578 - error = (*valp & ~0xf) != 0;
7581 +static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = {
7582 + { { 6 /* art */ }, 'i' }
7586 -Operand_frt_decode (uint32 *valp ATTRIBUTE_UNUSED)
7590 +static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = {
7591 + { { STATE_XTSYNC }, 'o' }
7595 -Operand_frt_encode (uint32 *valp)
7598 - error = (*valp & ~0xf) != 0;
7601 +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = {
7602 + { { 6 /* art */ }, 'o' }
7605 -static xtensa_operand_internal operands[] = {
7606 - { "soffsetx4", 10, -1, 0,
7607 - XTENSA_OPERAND_IS_PCRELATIVE,
7608 - Operand_soffsetx4_encode, Operand_soffsetx4_decode,
7609 - Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
7610 - { "uimm12x8", 3, -1, 0,
7612 - Operand_uimm12x8_encode, Operand_uimm12x8_decode,
7614 - { "simm4", 26, -1, 0,
7616 - Operand_simm4_encode, Operand_simm4_decode,
7618 - { "arr", 14, 0, 1,
7619 - XTENSA_OPERAND_IS_REGISTER,
7620 - Operand_arr_encode, Operand_arr_decode,
7623 - XTENSA_OPERAND_IS_REGISTER,
7624 - Operand_ars_encode, Operand_ars_decode,
7626 - { "*ars_invisible", 5, 0, 1,
7627 - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
7628 - Operand_ars_encode, Operand_ars_decode,
7631 - XTENSA_OPERAND_IS_REGISTER,
7632 - Operand_art_encode, Operand_art_decode,
7634 - { "ar0", 123, 0, 1,
7635 - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
7636 - Operand_ar0_encode, Operand_ar0_decode,
7638 - { "ar4", 124, 0, 1,
7639 - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
7640 - Operand_ar4_encode, Operand_ar4_decode,
7642 - { "ar8", 125, 0, 1,
7643 - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
7644 - Operand_ar8_encode, Operand_ar8_decode,
7646 - { "ar12", 126, 0, 1,
7647 - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
7648 - Operand_ar12_encode, Operand_ar12_decode,
7650 - { "ars_entry", 5, 0, 1,
7651 - XTENSA_OPERAND_IS_REGISTER,
7652 - Operand_ars_entry_encode, Operand_ars_entry_decode,
7654 - { "immrx4", 14, -1, 0,
7656 - Operand_immrx4_encode, Operand_immrx4_decode,
7658 - { "lsi4x4", 14, -1, 0,
7660 - Operand_lsi4x4_encode, Operand_lsi4x4_decode,
7662 - { "simm7", 34, -1, 0,
7664 - Operand_simm7_encode, Operand_simm7_decode,
7666 - { "uimm6", 33, -1, 0,
7667 - XTENSA_OPERAND_IS_PCRELATIVE,
7668 - Operand_uimm6_encode, Operand_uimm6_decode,
7669 - Operand_uimm6_ator, Operand_uimm6_rtoa },
7670 - { "ai4const", 0, -1, 0,
7672 - Operand_ai4const_encode, Operand_ai4const_decode,
7674 - { "b4const", 14, -1, 0,
7676 - Operand_b4const_encode, Operand_b4const_decode,
7678 - { "b4constu", 14, -1, 0,
7680 - Operand_b4constu_encode, Operand_b4constu_decode,
7682 - { "uimm8", 4, -1, 0,
7684 - Operand_uimm8_encode, Operand_uimm8_decode,
7686 - { "uimm8x2", 4, -1, 0,
7688 - Operand_uimm8x2_encode, Operand_uimm8x2_decode,
7690 - { "uimm8x4", 4, -1, 0,
7692 - Operand_uimm8x4_encode, Operand_uimm8x4_decode,
7694 - { "uimm4x16", 13, -1, 0,
7696 - Operand_uimm4x16_encode, Operand_uimm4x16_decode,
7698 - { "simm8", 4, -1, 0,
7700 - Operand_simm8_encode, Operand_simm8_decode,
7702 - { "simm8x256", 4, -1, 0,
7704 - Operand_simm8x256_encode, Operand_simm8x256_decode,
7706 - { "simm12b", 6, -1, 0,
7708 - Operand_simm12b_encode, Operand_simm12b_decode,
7710 - { "msalp32", 18, -1, 0,
7712 - Operand_msalp32_encode, Operand_msalp32_decode,
7714 - { "op2p1", 13, -1, 0,
7716 - Operand_op2p1_encode, Operand_op2p1_decode,
7718 - { "label8", 4, -1, 0,
7719 - XTENSA_OPERAND_IS_PCRELATIVE,
7720 - Operand_label8_encode, Operand_label8_decode,
7721 - Operand_label8_ator, Operand_label8_rtoa },
7722 - { "ulabel8", 4, -1, 0,
7723 - XTENSA_OPERAND_IS_PCRELATIVE,
7724 - Operand_ulabel8_encode, Operand_ulabel8_decode,
7725 - Operand_ulabel8_ator, Operand_ulabel8_rtoa },
7726 - { "label12", 3, -1, 0,
7727 - XTENSA_OPERAND_IS_PCRELATIVE,
7728 - Operand_label12_encode, Operand_label12_decode,
7729 - Operand_label12_ator, Operand_label12_rtoa },
7730 - { "soffset", 10, -1, 0,
7731 - XTENSA_OPERAND_IS_PCRELATIVE,
7732 - Operand_soffset_encode, Operand_soffset_decode,
7733 - Operand_soffset_ator, Operand_soffset_rtoa },
7734 - { "uimm16x4", 7, -1, 0,
7735 - XTENSA_OPERAND_IS_PCRELATIVE,
7736 - Operand_uimm16x4_encode, Operand_uimm16x4_decode,
7737 - Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
7739 - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
7740 - Operand_mx_encode, Operand_mx_decode,
7743 - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
7744 - Operand_my_encode, Operand_my_decode,
7747 - XTENSA_OPERAND_IS_REGISTER,
7748 - Operand_mw_encode, Operand_mw_decode,
7750 - { "mr0", 127, 1, 1,
7751 - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
7752 - Operand_mr0_encode, Operand_mr0_decode,
7754 - { "mr1", 128, 1, 1,
7755 - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
7756 - Operand_mr1_encode, Operand_mr1_decode,
7758 - { "mr2", 129, 1, 1,
7759 - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
7760 - Operand_mr2_encode, Operand_mr2_decode,
7762 - { "mr3", 130, 1, 1,
7763 - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
7764 - Operand_mr3_encode, Operand_mr3_decode,
7766 - { "immt", 0, -1, 0,
7768 - Operand_immt_encode, Operand_immt_decode,
7770 - { "imms", 5, -1, 0,
7772 - Operand_imms_encode, Operand_imms_decode,
7775 - XTENSA_OPERAND_IS_REGISTER,
7776 - Operand_bt_encode, Operand_bt_decode,
7779 - XTENSA_OPERAND_IS_REGISTER,
7780 - Operand_bs_encode, Operand_bs_decode,
7783 - XTENSA_OPERAND_IS_REGISTER,
7784 - Operand_br_encode, Operand_br_decode,
7786 - { "bt2", 44, 2, 2,
7787 - XTENSA_OPERAND_IS_REGISTER,
7788 - Operand_bt2_encode, Operand_bt2_decode,
7790 - { "bs2", 45, 2, 2,
7791 - XTENSA_OPERAND_IS_REGISTER,
7792 - Operand_bs2_encode, Operand_bs2_decode,
7794 - { "br2", 46, 2, 2,
7795 - XTENSA_OPERAND_IS_REGISTER,
7796 - Operand_br2_encode, Operand_br2_decode,
7798 - { "bt4", 47, 2, 4,
7799 - XTENSA_OPERAND_IS_REGISTER,
7800 - Operand_bt4_encode, Operand_bt4_decode,
7802 - { "bs4", 48, 2, 4,
7803 - XTENSA_OPERAND_IS_REGISTER,
7804 - Operand_bs4_encode, Operand_bs4_decode,
7806 - { "br4", 49, 2, 4,
7807 - XTENSA_OPERAND_IS_REGISTER,
7808 - Operand_br4_encode, Operand_br4_decode,
7810 - { "bt8", 50, 2, 8,
7811 - XTENSA_OPERAND_IS_REGISTER,
7812 - Operand_bt8_encode, Operand_bt8_decode,
7814 - { "bs8", 51, 2, 8,
7815 - XTENSA_OPERAND_IS_REGISTER,
7816 - Operand_bs8_encode, Operand_bs8_decode,
7818 - { "br8", 52, 2, 8,
7819 - XTENSA_OPERAND_IS_REGISTER,
7820 - Operand_br8_encode, Operand_br8_decode,
7822 - { "bt16", 131, 2, 16,
7823 - XTENSA_OPERAND_IS_REGISTER,
7824 - Operand_bt16_encode, Operand_bt16_decode,
7826 - { "bs16", 132, 2, 16,
7827 - XTENSA_OPERAND_IS_REGISTER,
7828 - Operand_bs16_encode, Operand_bs16_decode,
7830 - { "br16", 133, 2, 16,
7831 - XTENSA_OPERAND_IS_REGISTER,
7832 - Operand_br16_encode, Operand_br16_decode,
7834 - { "brall", 134, 2, 16,
7835 - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
7836 - Operand_brall_encode, Operand_brall_decode,
7838 - { "tp7", 0, -1, 0,
7840 - Operand_tp7_encode, Operand_tp7_decode,
7842 - { "xt_wbr15_label", 53, -1, 0,
7843 - XTENSA_OPERAND_IS_PCRELATIVE,
7844 - Operand_xt_wbr15_label_encode, Operand_xt_wbr15_label_decode,
7845 - Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa },
7846 - { "xt_wbr18_label", 54, -1, 0,
7847 - XTENSA_OPERAND_IS_PCRELATIVE,
7848 - Operand_xt_wbr18_label_encode, Operand_xt_wbr18_label_decode,
7849 - Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa },
7850 - { "cimm8x4", 4, -1, 0,
7852 - Operand_cimm8x4_encode, Operand_cimm8x4_decode,
7854 - { "frr", 14, 3, 1,
7855 - XTENSA_OPERAND_IS_REGISTER,
7856 - Operand_frr_encode, Operand_frr_decode,
7859 - XTENSA_OPERAND_IS_REGISTER,
7860 - Operand_frs_encode, Operand_frs_decode,
7863 - XTENSA_OPERAND_IS_REGISTER,
7864 - Operand_frt_encode, Operand_frt_decode,
7866 - { "t", 0, -1, 0, 0, 0, 0, 0, 0 },
7867 - { "bbi4", 1, -1, 0, 0, 0, 0, 0, 0 },
7868 - { "bbi", 2, -1, 0, 0, 0, 0, 0, 0 },
7869 - { "imm12", 3, -1, 0, 0, 0, 0, 0, 0 },
7870 - { "imm8", 4, -1, 0, 0, 0, 0, 0, 0 },
7871 - { "s", 5, -1, 0, 0, 0, 0, 0, 0 },
7872 - { "imm12b", 6, -1, 0, 0, 0, 0, 0, 0 },
7873 - { "imm16", 7, -1, 0, 0, 0, 0, 0, 0 },
7874 - { "m", 8, -1, 0, 0, 0, 0, 0, 0 },
7875 - { "n", 9, -1, 0, 0, 0, 0, 0, 0 },
7876 - { "offset", 10, -1, 0, 0, 0, 0, 0, 0 },
7877 - { "op0", 11, -1, 0, 0, 0, 0, 0, 0 },
7878 - { "op1", 12, -1, 0, 0, 0, 0, 0, 0 },
7879 - { "op2", 13, -1, 0, 0, 0, 0, 0, 0 },
7880 - { "r", 14, -1, 0, 0, 0, 0, 0, 0 },
7881 - { "sa4", 15, -1, 0, 0, 0, 0, 0, 0 },
7882 - { "sae4", 16, -1, 0, 0, 0, 0, 0, 0 },
7883 - { "sae", 17, -1, 0, 0, 0, 0, 0, 0 },
7884 - { "sal", 18, -1, 0, 0, 0, 0, 0, 0 },
7885 - { "sargt", 19, -1, 0, 0, 0, 0, 0, 0 },
7886 - { "sas4", 20, -1, 0, 0, 0, 0, 0, 0 },
7887 - { "sas", 21, -1, 0, 0, 0, 0, 0, 0 },
7888 - { "sr", 22, -1, 0, 0, 0, 0, 0, 0 },
7889 - { "st", 23, -1, 0, 0, 0, 0, 0, 0 },
7890 - { "thi3", 24, -1, 0, 0, 0, 0, 0, 0 },
7891 - { "imm4", 25, -1, 0, 0, 0, 0, 0, 0 },
7892 - { "mn", 26, -1, 0, 0, 0, 0, 0, 0 },
7893 - { "i", 27, -1, 0, 0, 0, 0, 0, 0 },
7894 - { "imm6lo", 28, -1, 0, 0, 0, 0, 0, 0 },
7895 - { "imm6hi", 29, -1, 0, 0, 0, 0, 0, 0 },
7896 - { "imm7lo", 30, -1, 0, 0, 0, 0, 0, 0 },
7897 - { "imm7hi", 31, -1, 0, 0, 0, 0, 0, 0 },
7898 - { "z", 32, -1, 0, 0, 0, 0, 0, 0 },
7899 - { "imm6", 33, -1, 0, 0, 0, 0, 0, 0 },
7900 - { "imm7", 34, -1, 0, 0, 0, 0, 0, 0 },
7901 - { "r3", 35, -1, 0, 0, 0, 0, 0, 0 },
7902 - { "rbit2", 36, -1, 0, 0, 0, 0, 0, 0 },
7903 - { "rhi", 37, -1, 0, 0, 0, 0, 0, 0 },
7904 - { "t3", 38, -1, 0, 0, 0, 0, 0, 0 },
7905 - { "tbit2", 39, -1, 0, 0, 0, 0, 0, 0 },
7906 - { "tlo", 40, -1, 0, 0, 0, 0, 0, 0 },
7907 - { "w", 41, -1, 0, 0, 0, 0, 0, 0 },
7908 - { "y", 42, -1, 0, 0, 0, 0, 0, 0 },
7909 - { "x", 43, -1, 0, 0, 0, 0, 0, 0 },
7910 - { "t2", 44, -1, 0, 0, 0, 0, 0, 0 },
7911 - { "s2", 45, -1, 0, 0, 0, 0, 0, 0 },
7912 - { "r2", 46, -1, 0, 0, 0, 0, 0, 0 },
7913 - { "t4", 47, -1, 0, 0, 0, 0, 0, 0 },
7914 - { "s4", 48, -1, 0, 0, 0, 0, 0, 0 },
7915 - { "r4", 49, -1, 0, 0, 0, 0, 0, 0 },
7916 - { "t8", 50, -1, 0, 0, 0, 0, 0, 0 },
7917 - { "s8", 51, -1, 0, 0, 0, 0, 0, 0 },
7918 - { "r8", 52, -1, 0, 0, 0, 0, 0, 0 },
7919 - { "xt_wbr15_imm", 53, -1, 0, 0, 0, 0, 0, 0 },
7920 - { "xt_wbr18_imm", 54, -1, 0, 0, 0, 0, 0, 0 },
7921 - { "op0_xt_flix64_slot0_s3", 55, -1, 0, 0, 0, 0, 0, 0 },
7922 - { "combined3e2c5767_fld7", 56, -1, 0, 0, 0, 0, 0, 0 },
7923 - { "combined3e2c5767_fld8", 57, -1, 0, 0, 0, 0, 0, 0 },
7924 - { "combined3e2c5767_fld9", 58, -1, 0, 0, 0, 0, 0, 0 },
7925 - { "combined3e2c5767_fld11", 59, -1, 0, 0, 0, 0, 0, 0 },
7926 - { "combined3e2c5767_fld49xt_flix64_slot0", 60, -1, 0, 0, 0, 0, 0, 0 },
7927 - { "op0_s4", 61, -1, 0, 0, 0, 0, 0, 0 },
7928 - { "combined3e2c5767_fld16", 62, -1, 0, 0, 0, 0, 0, 0 },
7929 - { "combined3e2c5767_fld19xt_flix64_slot1", 63, -1, 0, 0, 0, 0, 0, 0 },
7930 - { "combined3e2c5767_fld20xt_flix64_slot1", 64, -1, 0, 0, 0, 0, 0, 0 },
7931 - { "combined3e2c5767_fld21xt_flix64_slot1", 65, -1, 0, 0, 0, 0, 0, 0 },
7932 - { "combined3e2c5767_fld22xt_flix64_slot1", 66, -1, 0, 0, 0, 0, 0, 0 },
7933 - { "combined3e2c5767_fld23xt_flix64_slot1", 67, -1, 0, 0, 0, 0, 0, 0 },
7934 - { "combined3e2c5767_fld25xt_flix64_slot1", 68, -1, 0, 0, 0, 0, 0, 0 },
7935 - { "combined3e2c5767_fld26xt_flix64_slot1", 69, -1, 0, 0, 0, 0, 0, 0 },
7936 - { "combined3e2c5767_fld28xt_flix64_slot1", 70, -1, 0, 0, 0, 0, 0, 0 },
7937 - { "combined3e2c5767_fld30xt_flix64_slot1", 71, -1, 0, 0, 0, 0, 0, 0 },
7938 - { "combined3e2c5767_fld32xt_flix64_slot1", 72, -1, 0, 0, 0, 0, 0, 0 },
7939 - { "combined3e2c5767_fld33xt_flix64_slot1", 73, -1, 0, 0, 0, 0, 0, 0 },
7940 - { "combined3e2c5767_fld35xt_flix64_slot1", 74, -1, 0, 0, 0, 0, 0, 0 },
7941 - { "combined3e2c5767_fld51xt_flix64_slot1", 75, -1, 0, 0, 0, 0, 0, 0 },
7942 - { "combined3e2c5767_fld52xt_flix64_slot1", 76, -1, 0, 0, 0, 0, 0, 0 },
7943 - { "combined3e2c5767_fld53xt_flix64_slot1", 77, -1, 0, 0, 0, 0, 0, 0 },
7944 - { "combined3e2c5767_fld54xt_flix64_slot1", 78, -1, 0, 0, 0, 0, 0, 0 },
7945 - { "combined3e2c5767_fld57xt_flix64_slot1", 79, -1, 0, 0, 0, 0, 0, 0 },
7946 - { "combined3e2c5767_fld58xt_flix64_slot1", 80, -1, 0, 0, 0, 0, 0, 0 },
7947 - { "combined3e2c5767_fld60xt_flix64_slot1", 81, -1, 0, 0, 0, 0, 0, 0 },
7948 - { "combined3e2c5767_fld62xt_flix64_slot1", 82, -1, 0, 0, 0, 0, 0, 0 },
7949 - { "op0_s5", 83, -1, 0, 0, 0, 0, 0, 0 },
7950 - { "combined3e2c5767_fld36xt_flix64_slot2", 84, -1, 0, 0, 0, 0, 0, 0 },
7951 - { "combined3e2c5767_fld37xt_flix64_slot2", 85, -1, 0, 0, 0, 0, 0, 0 },
7952 - { "combined3e2c5767_fld39xt_flix64_slot2", 86, -1, 0, 0, 0, 0, 0, 0 },
7953 - { "combined3e2c5767_fld41xt_flix64_slot2", 87, -1, 0, 0, 0, 0, 0, 0 },
7954 - { "combined3e2c5767_fld42xt_flix64_slot2", 88, -1, 0, 0, 0, 0, 0, 0 },
7955 - { "combined3e2c5767_fld44xt_flix64_slot2", 89, -1, 0, 0, 0, 0, 0, 0 },
7956 - { "combined3e2c5767_fld45xt_flix64_slot2", 90, -1, 0, 0, 0, 0, 0, 0 },
7957 - { "combined3e2c5767_fld47xt_flix64_slot2", 91, -1, 0, 0, 0, 0, 0, 0 },
7958 - { "combined3e2c5767_fld63xt_flix64_slot2", 92, -1, 0, 0, 0, 0, 0, 0 },
7959 - { "combined3e2c5767_fld64xt_flix64_slot2", 93, -1, 0, 0, 0, 0, 0, 0 },
7960 - { "combined3e2c5767_fld65xt_flix64_slot2", 94, -1, 0, 0, 0, 0, 0, 0 },
7961 - { "combined3e2c5767_fld66xt_flix64_slot2", 95, -1, 0, 0, 0, 0, 0, 0 },
7962 - { "combined3e2c5767_fld68xt_flix64_slot2", 96, -1, 0, 0, 0, 0, 0, 0 },
7963 - { "op0_s6", 97, -1, 0, 0, 0, 0, 0, 0 },
7964 - { "combined3e2c5767_fld70xt_flix64_slot3", 98, -1, 0, 0, 0, 0, 0, 0 },
7965 - { "combined3e2c5767_fld71", 99, -1, 0, 0, 0, 0, 0, 0 },
7966 - { "combined3e2c5767_fld72xt_flix64_slot3", 100, -1, 0, 0, 0, 0, 0, 0 },
7967 - { "combined3e2c5767_fld73xt_flix64_slot3", 101, -1, 0, 0, 0, 0, 0, 0 },
7968 - { "combined3e2c5767_fld74xt_flix64_slot3", 102, -1, 0, 0, 0, 0, 0, 0 },
7969 - { "combined3e2c5767_fld75xt_flix64_slot3", 103, -1, 0, 0, 0, 0, 0, 0 },
7970 - { "combined3e2c5767_fld76xt_flix64_slot3", 104, -1, 0, 0, 0, 0, 0, 0 },
7971 - { "combined3e2c5767_fld77xt_flix64_slot3", 105, -1, 0, 0, 0, 0, 0, 0 },
7972 - { "combined3e2c5767_fld78xt_flix64_slot3", 106, -1, 0, 0, 0, 0, 0, 0 },
7973 - { "combined3e2c5767_fld79xt_flix64_slot3", 107, -1, 0, 0, 0, 0, 0, 0 },
7974 - { "combined3e2c5767_fld80xt_flix64_slot3", 108, -1, 0, 0, 0, 0, 0, 0 },
7975 - { "combined3e2c5767_fld81xt_flix64_slot3", 109, -1, 0, 0, 0, 0, 0, 0 },
7976 - { "combined3e2c5767_fld82xt_flix64_slot3", 110, -1, 0, 0, 0, 0, 0, 0 },
7977 - { "combined3e2c5767_fld83xt_flix64_slot3", 111, -1, 0, 0, 0, 0, 0, 0 },
7978 - { "combined3e2c5767_fld84xt_flix64_slot3", 112, -1, 0, 0, 0, 0, 0, 0 },
7979 - { "combined3e2c5767_fld85xt_flix64_slot3", 113, -1, 0, 0, 0, 0, 0, 0 },
7980 - { "combined3e2c5767_fld86xt_flix64_slot3", 114, -1, 0, 0, 0, 0, 0, 0 },
7981 - { "combined3e2c5767_fld87xt_flix64_slot3", 115, -1, 0, 0, 0, 0, 0, 0 },
7982 - { "combined3e2c5767_fld88xt_flix64_slot3", 116, -1, 0, 0, 0, 0, 0, 0 },
7983 - { "combined3e2c5767_fld89xt_flix64_slot3", 117, -1, 0, 0, 0, 0, 0, 0 },
7984 - { "combined3e2c5767_fld90xt_flix64_slot3", 118, -1, 0, 0, 0, 0, 0, 0 },
7985 - { "combined3e2c5767_fld91xt_flix64_slot3", 119, -1, 0, 0, 0, 0, 0, 0 },
7986 - { "combined3e2c5767_fld92xt_flix64_slot3", 120, -1, 0, 0, 0, 0, 0, 0 },
7987 - { "combined3e2c5767_fld93xt_flix64_slot3", 121, -1, 0, 0, 0, 0, 0, 0 },
7988 - { "op0_xt_flix64_slot0", 122, -1, 0, 0, 0, 0, 0, 0 }
7989 +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = {
7990 + { { STATE_CCOUNT }, 'i' }
7994 -/* Iclass table. */
7996 -static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
7997 - { { STATE_PSRING }, 'i' },
7998 - { { STATE_PSEXCM }, 'm' },
7999 - { { STATE_EPC1 }, 'i' }
8000 +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = {
8001 + { { 6 /* art */ }, 'i' }
8004 -static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
8005 - { { STATE_PSEXCM }, 'i' },
8006 - { { STATE_PSRING }, 'i' },
8007 - { { STATE_DEPC }, 'i' }
8008 +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = {
8009 + { { STATE_XTSYNC }, 'o' },
8010 + { { STATE_CCOUNT }, 'o' }
8013 -static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
8014 - { { 0 /* soffsetx4 */ }, 'i' },
8015 - { { 10 /* ar12 */ }, 'o' }
8016 +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = {
8017 + { { 6 /* art */ }, 'm' }
8020 -static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
8021 - { { STATE_PSCALLINC }, 'o' }
8022 +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = {
8023 + { { STATE_XTSYNC }, 'o' },
8024 + { { STATE_CCOUNT }, 'm' }
8027 -static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
8028 - { { 0 /* soffsetx4 */ }, 'i' },
8029 - { { 9 /* ar8 */ }, 'o' }
8032 -static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
8033 - { { STATE_PSCALLINC }, 'o' }
8036 -static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
8037 - { { 0 /* soffsetx4 */ }, 'i' },
8038 - { { 8 /* ar4 */ }, 'o' }
8041 -static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
8042 - { { STATE_PSCALLINC }, 'o' }
8045 -static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
8046 - { { 4 /* ars */ }, 'i' },
8047 - { { 10 /* ar12 */ }, 'o' }
8048 +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = {
8049 + { { 6 /* art */ }, 'o' }
8052 -static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
8053 - { { STATE_PSCALLINC }, 'o' }
8054 +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = {
8055 + { { STATE_CCOMPARE0 }, 'i' }
8058 -static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
8059 - { { 4 /* ars */ }, 'i' },
8060 - { { 9 /* ar8 */ }, 'o' }
8061 +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = {
8062 + { { 6 /* art */ }, 'i' }
8065 -static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
8066 - { { STATE_PSCALLINC }, 'o' }
8067 +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = {
8068 + { { STATE_CCOMPARE0 }, 'o' },
8069 + { { STATE_INTERRUPT }, 'm' }
8072 -static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
8073 - { { 4 /* ars */ }, 'i' },
8074 - { { 8 /* ar4 */ }, 'o' }
8075 +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = {
8076 + { { 6 /* art */ }, 'm' }
8079 -static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
8080 - { { STATE_PSCALLINC }, 'o' }
8081 +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = {
8082 + { { STATE_CCOMPARE0 }, 'm' },
8083 + { { STATE_INTERRUPT }, 'm' }
8086 -static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
8087 - { { 11 /* ars_entry */ }, 's' },
8088 - { { 4 /* ars */ }, 'i' },
8089 - { { 1 /* uimm12x8 */ }, 'i' }
8090 +static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = {
8091 + { { 4 /* ars */ }, 'i' }
8094 -static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
8095 - { { STATE_PSCALLINC }, 'i' },
8096 - { { STATE_PSEXCM }, 'i' },
8097 - { { STATE_PSWOE }, 'i' },
8098 - { { STATE_WindowBase }, 'm' },
8099 - { { STATE_WindowStart }, 'm' }
8100 +static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = {
8101 + { { STATE_XTSYNC }, 'o' }
8104 -static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
8105 +static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = {
8106 { { 6 /* art */ }, 'o' },
8107 { { 4 /* ars */ }, 'i' }
8110 -static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
8111 - { { STATE_WindowBase }, 'i' },
8112 - { { STATE_WindowStart }, 'i' }
8115 -static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
8116 - { { 2 /* simm4 */ }, 'i' }
8119 -static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
8120 - { { STATE_PSEXCM }, 'i' },
8121 - { { STATE_PSRING }, 'i' },
8122 - { { STATE_WindowBase }, 'm' }
8125 -static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
8126 - { { 5 /* *ars_invisible */ }, 'i' }
8127 +static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = {
8128 + { { 6 /* art */ }, 'i' },
8129 + { { 4 /* ars */ }, 'i' }
8132 -static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
8133 - { { STATE_WindowBase }, 'm' },
8134 - { { STATE_WindowStart }, 'm' },
8135 - { { STATE_PSEXCM }, 'i' },
8136 - { { STATE_PSWOE }, 'i' }
8137 +static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = {
8138 + { { STATE_XTSYNC }, 'o' }
8141 -static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
8142 - { { STATE_EPC1 }, 'i' },
8143 - { { STATE_PSEXCM }, 'm' },
8144 - { { STATE_PSRING }, 'i' },
8145 - { { STATE_WindowBase }, 'm' },
8146 - { { STATE_WindowStart }, 'm' },
8147 - { { STATE_PSOWB }, 'i' }
8148 +static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = {
8149 + { { 4 /* ars */ }, 'i' }
8152 -static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
8153 +static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = {
8154 { { 6 /* art */ }, 'o' },
8155 - { { 4 /* ars */ }, 'i' },
8156 - { { 12 /* immrx4 */ }, 'i' }
8159 -static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = {
8160 - { { STATE_PSEXCM }, 'i' },
8161 - { { STATE_PSRING }, 'i' }
8162 + { { 4 /* ars */ }, 'i' }
8165 -static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
8166 +static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = {
8167 { { 6 /* art */ }, 'i' },
8168 - { { 4 /* ars */ }, 'i' },
8169 - { { 12 /* immrx4 */ }, 'i' }
8172 -static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = {
8173 - { { STATE_PSEXCM }, 'i' },
8174 - { { STATE_PSRING }, 'i' }
8177 -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
8178 - { { 6 /* art */ }, 'o' }
8181 -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
8182 - { { STATE_PSEXCM }, 'i' },
8183 - { { STATE_PSRING }, 'i' },
8184 - { { STATE_WindowBase }, 'i' }
8187 -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
8188 - { { 6 /* art */ }, 'i' }
8191 -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
8192 - { { STATE_PSEXCM }, 'i' },
8193 - { { STATE_PSRING }, 'i' },
8194 - { { STATE_WindowBase }, 'o' }
8197 -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
8198 - { { 6 /* art */ }, 'm' }
8201 -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
8202 - { { STATE_PSEXCM }, 'i' },
8203 - { { STATE_PSRING }, 'i' },
8204 - { { STATE_WindowBase }, 'm' }
8207 -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
8208 - { { 6 /* art */ }, 'o' }
8211 -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
8212 - { { STATE_PSEXCM }, 'i' },
8213 - { { STATE_PSRING }, 'i' },
8214 - { { STATE_WindowStart }, 'i' }
8217 -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
8218 - { { 6 /* art */ }, 'i' }
8221 -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
8222 - { { STATE_PSEXCM }, 'i' },
8223 - { { STATE_PSRING }, 'i' },
8224 - { { STATE_WindowStart }, 'o' }
8227 -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
8228 - { { 6 /* art */ }, 'm' }
8231 -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
8232 - { { STATE_PSEXCM }, 'i' },
8233 - { { STATE_PSRING }, 'i' },
8234 - { { STATE_WindowStart }, 'm' }
8235 + { { 4 /* ars */ }, 'i' }
8238 -static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
8239 +static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = {
8240 { { 3 /* arr */ }, 'o' },
8241 { { 4 /* ars */ }, 'i' },
8242 { { 6 /* art */ }, 'i' }
8245 -static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
8246 - { { 3 /* arr */ }, 'o' },
8247 - { { 4 /* ars */ }, 'i' },
8248 - { { 16 /* ai4const */ }, 'i' }
8249 +static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = {
8250 + { { 6 /* art */ }, 'o' },
8251 + { { 4 /* ars */ }, 'i' }
8254 -static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
8255 +static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = {
8256 + { { 3 /* arr */ }, 'o' },
8257 { { 4 /* ars */ }, 'i' },
8258 - { { 15 /* uimm6 */ }, 'i' }
8259 + { { 35 /* tp7 */ }, 'i' }
8262 -static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
8263 +static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = {
8264 { { 6 /* art */ }, 'o' },
8265 { { 4 /* ars */ }, 'i' },
8266 - { { 13 /* lsi4x4 */ }, 'i' }
8269 -static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
8270 - { { 6 /* art */ }, 'o' },
8271 - { { 4 /* ars */ }, 'i' }
8274 -static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
8275 - { { 4 /* ars */ }, 'o' },
8276 - { { 14 /* simm7 */ }, 'i' }
8277 + { { 21 /* uimm8x4 */ }, 'i' }
8280 -static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
8281 - { { 5 /* *ars_invisible */ }, 'i' }
8282 +static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = {
8283 + { { 6 /* art */ }, 'i' },
8284 + { { 4 /* ars */ }, 'i' },
8285 + { { 21 /* uimm8x4 */ }, 'i' }
8288 -static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
8289 - { { 6 /* art */ }, 'i' },
8290 +static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = {
8291 + { { 6 /* art */ }, 'm' },
8292 { { 4 /* ars */ }, 'i' },
8293 - { { 13 /* lsi4x4 */ }, 'i' }
8294 + { { 21 /* uimm8x4 */ }, 'i' }
8297 -static xtensa_arg_internal Iclass_rur_threadptr_args[] = {
8298 - { { 3 /* arr */ }, 'o' }
8299 +static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = {
8300 + { { STATE_SCOMPARE1 }, 'i' },
8301 + { { STATE_SCOMPARE1 }, 'i' }
8304 -static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = {
8305 - { { STATE_THREADPTR }, 'i' }
8306 +static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = {
8307 + { { 6 /* art */ }, 'o' }
8310 -static xtensa_arg_internal Iclass_wur_threadptr_args[] = {
8311 - { { 6 /* art */ }, 'i' }
8312 +static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = {
8313 + { { STATE_SCOMPARE1 }, 'i' }
8316 -static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = {
8317 - { { STATE_THREADPTR }, 'o' }
8318 +static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = {
8319 + { { 6 /* art */ }, 'i' }
8322 -static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
8323 - { { 6 /* art */ }, 'o' },
8324 - { { 4 /* ars */ }, 'i' },
8325 - { { 23 /* simm8 */ }, 'i' }
8326 +static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = {
8327 + { { STATE_SCOMPARE1 }, 'o' }
8330 -static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
8331 - { { 6 /* art */ }, 'o' },
8332 - { { 4 /* ars */ }, 'i' },
8333 - { { 24 /* simm8x256 */ }, 'i' }
8334 +static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = {
8335 + { { 6 /* art */ }, 'm' }
8338 -static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
8339 - { { 3 /* arr */ }, 'o' },
8340 - { { 4 /* ars */ }, 'i' },
8341 - { { 6 /* art */ }, 'i' }
8342 +static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = {
8343 + { { STATE_SCOMPARE1 }, 'm' }
8346 -static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
8347 +static xtensa_arg_internal Iclass_xt_mul32_args[] = {
8348 { { 3 /* arr */ }, 'o' },
8349 { { 4 /* ars */ }, 'i' },
8350 { { 6 /* art */ }, 'i' }
8353 -static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
8354 - { { 4 /* ars */ }, 'i' },
8355 - { { 17 /* b4const */ }, 'i' },
8356 - { { 28 /* label8 */ }, 'i' }
8359 -static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
8360 - { { 4 /* ars */ }, 'i' },
8361 - { { 67 /* bbi */ }, 'i' },
8362 - { { 28 /* label8 */ }, 'i' }
8365 -static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
8366 - { { 4 /* ars */ }, 'i' },
8367 - { { 18 /* b4constu */ }, 'i' },
8368 - { { 28 /* label8 */ }, 'i' }
8371 -static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
8372 - { { 4 /* ars */ }, 'i' },
8373 - { { 6 /* art */ }, 'i' },
8374 - { { 28 /* label8 */ }, 'i' }
8377 -static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
8378 - { { 4 /* ars */ }, 'i' },
8379 - { { 30 /* label12 */ }, 'i' }
8382 -static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
8383 - { { 0 /* soffsetx4 */ }, 'i' },
8384 - { { 7 /* ar0 */ }, 'o' }
8387 -static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
8388 - { { 4 /* ars */ }, 'i' },
8389 - { { 7 /* ar0 */ }, 'o' }
8392 -static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
8393 - { { 3 /* arr */ }, 'o' },
8394 - { { 6 /* art */ }, 'i' },
8395 - { { 82 /* sae */ }, 'i' },
8396 - { { 27 /* op2p1 */ }, 'i' }
8399 -static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
8400 - { { 31 /* soffset */ }, 'i' }
8403 -static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
8404 - { { 4 /* ars */ }, 'i' }
8407 -static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
8408 - { { 6 /* art */ }, 'o' },
8409 - { { 4 /* ars */ }, 'i' },
8410 - { { 20 /* uimm8x2 */ }, 'i' }
8413 -static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
8414 - { { 6 /* art */ }, 'o' },
8415 - { { 4 /* ars */ }, 'i' },
8416 - { { 20 /* uimm8x2 */ }, 'i' }
8419 -static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
8420 - { { 6 /* art */ }, 'o' },
8421 - { { 4 /* ars */ }, 'i' },
8422 - { { 21 /* uimm8x4 */ }, 'i' }
8425 -static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
8426 - { { 6 /* art */ }, 'o' },
8427 - { { 32 /* uimm16x4 */ }, 'i' }
8430 -static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = {
8431 - { { STATE_LITBADDR }, 'i' },
8432 - { { STATE_LITBEN }, 'i' }
8435 -static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
8436 - { { 6 /* art */ }, 'o' },
8437 - { { 4 /* ars */ }, 'i' },
8438 - { { 19 /* uimm8 */ }, 'i' }
8441 -static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = {
8442 - { { 4 /* ars */ }, 'i' },
8443 - { { 29 /* ulabel8 */ }, 'i' }
8446 -static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = {
8447 - { { STATE_LBEG }, 'o' },
8448 - { { STATE_LEND }, 'o' },
8449 - { { STATE_LCOUNT }, 'o' }
8452 -static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = {
8453 - { { 4 /* ars */ }, 'i' },
8454 - { { 29 /* ulabel8 */ }, 'i' }
8457 -static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = {
8458 - { { STATE_LBEG }, 'o' },
8459 - { { STATE_LEND }, 'o' },
8460 - { { STATE_LCOUNT }, 'o' }
8463 -static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
8464 - { { 6 /* art */ }, 'o' },
8465 - { { 25 /* simm12b */ }, 'i' }
8468 -static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
8469 - { { 3 /* arr */ }, 'm' },
8470 - { { 4 /* ars */ }, 'i' },
8471 - { { 6 /* art */ }, 'i' }
8474 -static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
8475 - { { 3 /* arr */ }, 'o' },
8476 - { { 6 /* art */ }, 'i' }
8479 -static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
8480 - { { 5 /* *ars_invisible */ }, 'i' }
8483 -static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
8484 - { { 6 /* art */ }, 'i' },
8485 - { { 4 /* ars */ }, 'i' },
8486 - { { 20 /* uimm8x2 */ }, 'i' }
8489 -static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
8490 - { { 6 /* art */ }, 'i' },
8491 - { { 4 /* ars */ }, 'i' },
8492 - { { 21 /* uimm8x4 */ }, 'i' }
8495 -static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
8496 - { { 6 /* art */ }, 'i' },
8497 - { { 4 /* ars */ }, 'i' },
8498 - { { 19 /* uimm8 */ }, 'i' }
8501 -static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
8502 - { { 4 /* ars */ }, 'i' }
8505 -static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
8506 - { { STATE_SAR }, 'o' }
8509 -static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
8510 - { { 86 /* sas */ }, 'i' }
8513 -static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
8514 - { { STATE_SAR }, 'o' }
8517 -static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
8518 - { { 3 /* arr */ }, 'o' },
8519 - { { 4 /* ars */ }, 'i' }
8522 -static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
8523 - { { STATE_SAR }, 'i' }
8526 -static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
8527 - { { 3 /* arr */ }, 'o' },
8528 - { { 4 /* ars */ }, 'i' },
8529 - { { 6 /* art */ }, 'i' }
8532 -static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
8533 - { { STATE_SAR }, 'i' }
8536 -static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
8537 - { { 3 /* arr */ }, 'o' },
8538 - { { 6 /* art */ }, 'i' }
8541 -static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
8542 - { { STATE_SAR }, 'i' }
8545 -static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
8546 - { { 3 /* arr */ }, 'o' },
8547 - { { 4 /* ars */ }, 'i' },
8548 - { { 26 /* msalp32 */ }, 'i' }
8551 -static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
8552 - { { 3 /* arr */ }, 'o' },
8553 - { { 6 /* art */ }, 'i' },
8554 - { { 84 /* sargt */ }, 'i' }
8557 -static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
8558 - { { 3 /* arr */ }, 'o' },
8559 - { { 6 /* art */ }, 'i' },
8560 - { { 70 /* s */ }, 'i' }
8563 -static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
8564 - { { STATE_XTSYNC }, 'i' }
8567 -static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
8568 - { { 6 /* art */ }, 'o' },
8569 - { { 70 /* s */ }, 'i' }
8572 -static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
8573 - { { STATE_PSWOE }, 'i' },
8574 - { { STATE_PSCALLINC }, 'i' },
8575 - { { STATE_PSOWB }, 'i' },
8576 - { { STATE_PSRING }, 'i' },
8577 - { { STATE_PSUM }, 'i' },
8578 - { { STATE_PSEXCM }, 'i' },
8579 - { { STATE_PSINTLEVEL }, 'm' }
8582 -static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = {
8583 - { { 6 /* art */ }, 'o' }
8586 -static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = {
8587 - { { STATE_LEND }, 'i' }
8590 -static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = {
8591 - { { 6 /* art */ }, 'i' }
8594 -static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = {
8595 - { { STATE_LEND }, 'o' }
8598 -static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = {
8599 - { { 6 /* art */ }, 'm' }
8602 -static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = {
8603 - { { STATE_LEND }, 'm' }
8606 -static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = {
8607 - { { 6 /* art */ }, 'o' }
8610 -static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = {
8611 - { { STATE_LCOUNT }, 'i' }
8614 -static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = {
8615 - { { 6 /* art */ }, 'i' }
8618 -static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = {
8619 - { { STATE_XTSYNC }, 'o' },
8620 - { { STATE_LCOUNT }, 'o' }
8623 -static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = {
8624 - { { 6 /* art */ }, 'm' }
8627 -static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = {
8628 - { { STATE_XTSYNC }, 'o' },
8629 - { { STATE_LCOUNT }, 'm' }
8632 -static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = {
8633 - { { 6 /* art */ }, 'o' }
8636 -static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = {
8637 - { { STATE_LBEG }, 'i' }
8640 -static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = {
8641 - { { 6 /* art */ }, 'i' }
8644 -static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = {
8645 - { { STATE_LBEG }, 'o' }
8648 -static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = {
8649 - { { 6 /* art */ }, 'm' }
8652 -static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = {
8653 - { { STATE_LBEG }, 'm' }
8656 -static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
8657 - { { 6 /* art */ }, 'o' }
8660 -static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
8661 - { { STATE_SAR }, 'i' }
8664 -static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
8665 - { { 6 /* art */ }, 'i' }
8668 -static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
8669 - { { STATE_SAR }, 'o' },
8670 - { { STATE_XTSYNC }, 'o' }
8673 -static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
8674 - { { 6 /* art */ }, 'm' }
8677 -static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
8678 - { { STATE_SAR }, 'm' }
8681 -static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = {
8682 - { { 6 /* art */ }, 'o' }
8685 -static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = {
8686 - { { STATE_LITBADDR }, 'i' },
8687 - { { STATE_LITBEN }, 'i' }
8690 -static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = {
8691 - { { 6 /* art */ }, 'i' }
8694 -static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = {
8695 - { { STATE_LITBADDR }, 'o' },
8696 - { { STATE_LITBEN }, 'o' }
8699 -static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = {
8700 - { { 6 /* art */ }, 'm' }
8703 -static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = {
8704 - { { STATE_LITBADDR }, 'm' },
8705 - { { STATE_LITBEN }, 'm' }
8708 -static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = {
8709 - { { 6 /* art */ }, 'o' }
8712 -static xtensa_arg_internal Iclass_xt_iclass_rsr_176_stateArgs[] = {
8713 - { { STATE_PSEXCM }, 'i' },
8714 - { { STATE_PSRING }, 'i' }
8717 -static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = {
8718 - { { 6 /* art */ }, 'o' }
8721 -static xtensa_arg_internal Iclass_xt_iclass_rsr_208_stateArgs[] = {
8722 - { { STATE_PSEXCM }, 'i' },
8723 - { { STATE_PSRING }, 'i' }
8726 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
8727 - { { 6 /* art */ }, 'o' }
8730 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
8731 - { { STATE_PSWOE }, 'i' },
8732 - { { STATE_PSCALLINC }, 'i' },
8733 - { { STATE_PSOWB }, 'i' },
8734 - { { STATE_PSRING }, 'i' },
8735 - { { STATE_PSUM }, 'i' },
8736 - { { STATE_PSEXCM }, 'i' },
8737 - { { STATE_PSINTLEVEL }, 'i' }
8740 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
8741 - { { 6 /* art */ }, 'i' }
8744 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
8745 - { { STATE_PSWOE }, 'o' },
8746 - { { STATE_PSCALLINC }, 'o' },
8747 - { { STATE_PSOWB }, 'o' },
8748 - { { STATE_PSRING }, 'm' },
8749 - { { STATE_PSUM }, 'o' },
8750 - { { STATE_PSEXCM }, 'm' },
8751 - { { STATE_PSINTLEVEL }, 'o' }
8754 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
8755 - { { 6 /* art */ }, 'm' }
8758 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
8759 - { { STATE_PSWOE }, 'm' },
8760 - { { STATE_PSCALLINC }, 'm' },
8761 - { { STATE_PSOWB }, 'm' },
8762 - { { STATE_PSRING }, 'm' },
8763 - { { STATE_PSUM }, 'm' },
8764 - { { STATE_PSEXCM }, 'm' },
8765 - { { STATE_PSINTLEVEL }, 'm' }
8768 -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
8769 - { { 6 /* art */ }, 'o' }
8772 -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
8773 - { { STATE_PSEXCM }, 'i' },
8774 - { { STATE_PSRING }, 'i' },
8775 - { { STATE_EPC1 }, 'i' }
8778 -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
8779 - { { 6 /* art */ }, 'i' }
8782 -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
8783 - { { STATE_PSEXCM }, 'i' },
8784 - { { STATE_PSRING }, 'i' },
8785 - { { STATE_EPC1 }, 'o' }
8788 -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
8789 - { { 6 /* art */ }, 'm' }
8792 -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
8793 - { { STATE_PSEXCM }, 'i' },
8794 - { { STATE_PSRING }, 'i' },
8795 - { { STATE_EPC1 }, 'm' }
8798 -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
8799 - { { 6 /* art */ }, 'o' }
8802 -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
8803 - { { STATE_PSEXCM }, 'i' },
8804 - { { STATE_PSRING }, 'i' },
8805 - { { STATE_EXCSAVE1 }, 'i' }
8808 -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
8809 - { { 6 /* art */ }, 'i' }
8812 -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
8813 - { { STATE_PSEXCM }, 'i' },
8814 - { { STATE_PSRING }, 'i' },
8815 - { { STATE_EXCSAVE1 }, 'o' }
8818 -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
8819 - { { 6 /* art */ }, 'm' }
8822 -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
8823 - { { STATE_PSEXCM }, 'i' },
8824 - { { STATE_PSRING }, 'i' },
8825 - { { STATE_EXCSAVE1 }, 'm' }
8828 -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
8829 - { { 6 /* art */ }, 'o' }
8832 -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
8833 - { { STATE_PSEXCM }, 'i' },
8834 - { { STATE_PSRING }, 'i' },
8835 - { { STATE_EPC2 }, 'i' }
8838 -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
8839 - { { 6 /* art */ }, 'i' }
8842 -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
8843 - { { STATE_PSEXCM }, 'i' },
8844 - { { STATE_PSRING }, 'i' },
8845 - { { STATE_EPC2 }, 'o' }
8848 -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
8849 - { { 6 /* art */ }, 'm' }
8852 -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
8853 - { { STATE_PSEXCM }, 'i' },
8854 - { { STATE_PSRING }, 'i' },
8855 - { { STATE_EPC2 }, 'm' }
8858 -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
8859 - { { 6 /* art */ }, 'o' }
8862 -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
8863 - { { STATE_PSEXCM }, 'i' },
8864 - { { STATE_PSRING }, 'i' },
8865 - { { STATE_EXCSAVE2 }, 'i' }
8868 -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
8869 - { { 6 /* art */ }, 'i' }
8872 -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
8873 - { { STATE_PSEXCM }, 'i' },
8874 - { { STATE_PSRING }, 'i' },
8875 - { { STATE_EXCSAVE2 }, 'o' }
8878 -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
8879 - { { 6 /* art */ }, 'm' }
8882 -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
8883 - { { STATE_PSEXCM }, 'i' },
8884 - { { STATE_PSRING }, 'i' },
8885 - { { STATE_EXCSAVE2 }, 'm' }
8888 -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = {
8889 - { { 6 /* art */ }, 'o' }
8892 -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = {
8893 - { { STATE_PSEXCM }, 'i' },
8894 - { { STATE_PSRING }, 'i' },
8895 - { { STATE_EPC3 }, 'i' }
8898 -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = {
8899 - { { 6 /* art */ }, 'i' }
8902 -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = {
8903 - { { STATE_PSEXCM }, 'i' },
8904 - { { STATE_PSRING }, 'i' },
8905 - { { STATE_EPC3 }, 'o' }
8908 -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = {
8909 - { { 6 /* art */ }, 'm' }
8912 -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = {
8913 - { { STATE_PSEXCM }, 'i' },
8914 - { { STATE_PSRING }, 'i' },
8915 - { { STATE_EPC3 }, 'm' }
8918 -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = {
8919 - { { 6 /* art */ }, 'o' }
8922 -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = {
8923 - { { STATE_PSEXCM }, 'i' },
8924 - { { STATE_PSRING }, 'i' },
8925 - { { STATE_EXCSAVE3 }, 'i' }
8928 -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = {
8929 - { { 6 /* art */ }, 'i' }
8932 -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = {
8933 - { { STATE_PSEXCM }, 'i' },
8934 - { { STATE_PSRING }, 'i' },
8935 - { { STATE_EXCSAVE3 }, 'o' }
8938 -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = {
8939 - { { 6 /* art */ }, 'm' }
8942 -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = {
8943 - { { STATE_PSEXCM }, 'i' },
8944 - { { STATE_PSRING }, 'i' },
8945 - { { STATE_EXCSAVE3 }, 'm' }
8948 -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = {
8949 - { { 6 /* art */ }, 'o' }
8952 -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = {
8953 - { { STATE_PSEXCM }, 'i' },
8954 - { { STATE_PSRING }, 'i' },
8955 - { { STATE_EPC4 }, 'i' }
8958 -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = {
8959 - { { 6 /* art */ }, 'i' }
8962 -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = {
8963 - { { STATE_PSEXCM }, 'i' },
8964 - { { STATE_PSRING }, 'i' },
8965 - { { STATE_EPC4 }, 'o' }
8968 -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = {
8969 - { { 6 /* art */ }, 'm' }
8972 -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = {
8973 - { { STATE_PSEXCM }, 'i' },
8974 - { { STATE_PSRING }, 'i' },
8975 - { { STATE_EPC4 }, 'm' }
8978 -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = {
8979 - { { 6 /* art */ }, 'o' }
8982 -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = {
8983 - { { STATE_PSEXCM }, 'i' },
8984 - { { STATE_PSRING }, 'i' },
8985 - { { STATE_EXCSAVE4 }, 'i' }
8988 -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = {
8989 - { { 6 /* art */ }, 'i' }
8992 -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = {
8993 - { { STATE_PSEXCM }, 'i' },
8994 - { { STATE_PSRING }, 'i' },
8995 - { { STATE_EXCSAVE4 }, 'o' }
8998 -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = {
8999 - { { 6 /* art */ }, 'm' }
9002 -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = {
9003 - { { STATE_PSEXCM }, 'i' },
9004 - { { STATE_PSRING }, 'i' },
9005 - { { STATE_EXCSAVE4 }, 'm' }
9008 -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = {
9009 - { { 6 /* art */ }, 'o' }
9012 -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = {
9013 - { { STATE_PSEXCM }, 'i' },
9014 - { { STATE_PSRING }, 'i' },
9015 - { { STATE_EPC5 }, 'i' }
9018 -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = {
9019 - { { 6 /* art */ }, 'i' }
9022 -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = {
9023 - { { STATE_PSEXCM }, 'i' },
9024 - { { STATE_PSRING }, 'i' },
9025 - { { STATE_EPC5 }, 'o' }
9028 -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = {
9029 - { { 6 /* art */ }, 'm' }
9032 -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = {
9033 - { { STATE_PSEXCM }, 'i' },
9034 - { { STATE_PSRING }, 'i' },
9035 - { { STATE_EPC5 }, 'm' }
9038 -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = {
9039 - { { 6 /* art */ }, 'o' }
9042 -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = {
9043 - { { STATE_PSEXCM }, 'i' },
9044 - { { STATE_PSRING }, 'i' },
9045 - { { STATE_EXCSAVE5 }, 'i' }
9048 -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = {
9049 - { { 6 /* art */ }, 'i' }
9052 -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = {
9053 - { { STATE_PSEXCM }, 'i' },
9054 - { { STATE_PSRING }, 'i' },
9055 - { { STATE_EXCSAVE5 }, 'o' }
9058 -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = {
9059 - { { 6 /* art */ }, 'm' }
9062 -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = {
9063 - { { STATE_PSEXCM }, 'i' },
9064 - { { STATE_PSRING }, 'i' },
9065 - { { STATE_EXCSAVE5 }, 'm' }
9068 -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = {
9069 - { { 6 /* art */ }, 'o' }
9072 -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = {
9073 - { { STATE_PSEXCM }, 'i' },
9074 - { { STATE_PSRING }, 'i' },
9075 - { { STATE_EPC6 }, 'i' }
9078 -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = {
9079 - { { 6 /* art */ }, 'i' }
9082 -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = {
9083 - { { STATE_PSEXCM }, 'i' },
9084 - { { STATE_PSRING }, 'i' },
9085 - { { STATE_EPC6 }, 'o' }
9088 -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = {
9089 - { { 6 /* art */ }, 'm' }
9092 -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = {
9093 - { { STATE_PSEXCM }, 'i' },
9094 - { { STATE_PSRING }, 'i' },
9095 - { { STATE_EPC6 }, 'm' }
9098 -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = {
9099 - { { 6 /* art */ }, 'o' }
9102 -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = {
9103 - { { STATE_PSEXCM }, 'i' },
9104 - { { STATE_PSRING }, 'i' },
9105 - { { STATE_EXCSAVE6 }, 'i' }
9108 -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = {
9109 - { { 6 /* art */ }, 'i' }
9112 -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = {
9113 - { { STATE_PSEXCM }, 'i' },
9114 - { { STATE_PSRING }, 'i' },
9115 - { { STATE_EXCSAVE6 }, 'o' }
9118 -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = {
9119 - { { 6 /* art */ }, 'm' }
9122 -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = {
9123 - { { STATE_PSEXCM }, 'i' },
9124 - { { STATE_PSRING }, 'i' },
9125 - { { STATE_EXCSAVE6 }, 'm' }
9128 -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = {
9129 - { { 6 /* art */ }, 'o' }
9132 -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = {
9133 - { { STATE_PSEXCM }, 'i' },
9134 - { { STATE_PSRING }, 'i' },
9135 - { { STATE_EPC7 }, 'i' }
9138 -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = {
9139 - { { 6 /* art */ }, 'i' }
9142 -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = {
9143 - { { STATE_PSEXCM }, 'i' },
9144 - { { STATE_PSRING }, 'i' },
9145 - { { STATE_EPC7 }, 'o' }
9148 -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = {
9149 - { { 6 /* art */ }, 'm' }
9152 -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = {
9153 - { { STATE_PSEXCM }, 'i' },
9154 - { { STATE_PSRING }, 'i' },
9155 - { { STATE_EPC7 }, 'm' }
9158 -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = {
9159 - { { 6 /* art */ }, 'o' }
9162 -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = {
9163 - { { STATE_PSEXCM }, 'i' },
9164 - { { STATE_PSRING }, 'i' },
9165 - { { STATE_EXCSAVE7 }, 'i' }
9168 -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = {
9169 - { { 6 /* art */ }, 'i' }
9172 -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = {
9173 - { { STATE_PSEXCM }, 'i' },
9174 - { { STATE_PSRING }, 'i' },
9175 - { { STATE_EXCSAVE7 }, 'o' }
9178 -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = {
9179 - { { 6 /* art */ }, 'm' }
9182 -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = {
9183 - { { STATE_PSEXCM }, 'i' },
9184 - { { STATE_PSRING }, 'i' },
9185 - { { STATE_EXCSAVE7 }, 'm' }
9188 -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
9189 - { { 6 /* art */ }, 'o' }
9192 -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
9193 - { { STATE_PSEXCM }, 'i' },
9194 - { { STATE_PSRING }, 'i' },
9195 - { { STATE_EPS2 }, 'i' }
9198 -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
9199 - { { 6 /* art */ }, 'i' }
9202 -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
9203 - { { STATE_PSEXCM }, 'i' },
9204 - { { STATE_PSRING }, 'i' },
9205 - { { STATE_EPS2 }, 'o' }
9208 -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
9209 - { { 6 /* art */ }, 'm' }
9212 -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
9213 - { { STATE_PSEXCM }, 'i' },
9214 - { { STATE_PSRING }, 'i' },
9215 - { { STATE_EPS2 }, 'm' }
9218 -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = {
9219 - { { 6 /* art */ }, 'o' }
9222 -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = {
9223 - { { STATE_PSEXCM }, 'i' },
9224 - { { STATE_PSRING }, 'i' },
9225 - { { STATE_EPS3 }, 'i' }
9228 -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = {
9229 - { { 6 /* art */ }, 'i' }
9232 -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = {
9233 - { { STATE_PSEXCM }, 'i' },
9234 - { { STATE_PSRING }, 'i' },
9235 - { { STATE_EPS3 }, 'o' }
9238 -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = {
9239 - { { 6 /* art */ }, 'm' }
9242 -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = {
9243 - { { STATE_PSEXCM }, 'i' },
9244 - { { STATE_PSRING }, 'i' },
9245 - { { STATE_EPS3 }, 'm' }
9248 -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = {
9249 - { { 6 /* art */ }, 'o' }
9252 -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = {
9253 - { { STATE_PSEXCM }, 'i' },
9254 - { { STATE_PSRING }, 'i' },
9255 - { { STATE_EPS4 }, 'i' }
9258 -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = {
9259 - { { 6 /* art */ }, 'i' }
9262 -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = {
9263 - { { STATE_PSEXCM }, 'i' },
9264 - { { STATE_PSRING }, 'i' },
9265 - { { STATE_EPS4 }, 'o' }
9268 -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = {
9269 - { { 6 /* art */ }, 'm' }
9272 -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = {
9273 - { { STATE_PSEXCM }, 'i' },
9274 - { { STATE_PSRING }, 'i' },
9275 - { { STATE_EPS4 }, 'm' }
9278 -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = {
9279 - { { 6 /* art */ }, 'o' }
9282 -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = {
9283 - { { STATE_PSEXCM }, 'i' },
9284 - { { STATE_PSRING }, 'i' },
9285 - { { STATE_EPS5 }, 'i' }
9288 -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = {
9289 - { { 6 /* art */ }, 'i' }
9292 -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = {
9293 - { { STATE_PSEXCM }, 'i' },
9294 - { { STATE_PSRING }, 'i' },
9295 - { { STATE_EPS5 }, 'o' }
9298 -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = {
9299 - { { 6 /* art */ }, 'm' }
9302 -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = {
9303 - { { STATE_PSEXCM }, 'i' },
9304 - { { STATE_PSRING }, 'i' },
9305 - { { STATE_EPS5 }, 'm' }
9308 -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = {
9309 - { { 6 /* art */ }, 'o' }
9312 -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = {
9313 - { { STATE_PSEXCM }, 'i' },
9314 - { { STATE_PSRING }, 'i' },
9315 - { { STATE_EPS6 }, 'i' }
9318 -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = {
9319 - { { 6 /* art */ }, 'i' }
9322 -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = {
9323 - { { STATE_PSEXCM }, 'i' },
9324 - { { STATE_PSRING }, 'i' },
9325 - { { STATE_EPS6 }, 'o' }
9328 -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = {
9329 - { { 6 /* art */ }, 'm' }
9332 -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = {
9333 - { { STATE_PSEXCM }, 'i' },
9334 - { { STATE_PSRING }, 'i' },
9335 - { { STATE_EPS6 }, 'm' }
9338 -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = {
9339 - { { 6 /* art */ }, 'o' }
9342 -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = {
9343 - { { STATE_PSEXCM }, 'i' },
9344 - { { STATE_PSRING }, 'i' },
9345 - { { STATE_EPS7 }, 'i' }
9348 -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = {
9349 - { { 6 /* art */ }, 'i' }
9352 -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = {
9353 - { { STATE_PSEXCM }, 'i' },
9354 - { { STATE_PSRING }, 'i' },
9355 - { { STATE_EPS7 }, 'o' }
9358 -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = {
9359 - { { 6 /* art */ }, 'm' }
9362 -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = {
9363 - { { STATE_PSEXCM }, 'i' },
9364 - { { STATE_PSRING }, 'i' },
9365 - { { STATE_EPS7 }, 'm' }
9368 -static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
9369 - { { 6 /* art */ }, 'o' }
9372 -static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
9373 - { { STATE_PSEXCM }, 'i' },
9374 - { { STATE_PSRING }, 'i' },
9375 - { { STATE_EXCVADDR }, 'i' }
9378 -static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
9379 - { { 6 /* art */ }, 'i' }
9382 -static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
9383 - { { STATE_PSEXCM }, 'i' },
9384 - { { STATE_PSRING }, 'i' },
9385 - { { STATE_EXCVADDR }, 'o' }
9388 -static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
9389 - { { 6 /* art */ }, 'm' }
9392 -static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
9393 - { { STATE_PSEXCM }, 'i' },
9394 - { { STATE_PSRING }, 'i' },
9395 - { { STATE_EXCVADDR }, 'm' }
9398 -static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
9399 - { { 6 /* art */ }, 'o' }
9402 -static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
9403 - { { STATE_PSEXCM }, 'i' },
9404 - { { STATE_PSRING }, 'i' },
9405 - { { STATE_DEPC }, 'i' }
9408 -static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
9409 - { { 6 /* art */ }, 'i' }
9412 -static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
9413 - { { STATE_PSEXCM }, 'i' },
9414 - { { STATE_PSRING }, 'i' },
9415 - { { STATE_DEPC }, 'o' }
9418 -static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
9419 - { { 6 /* art */ }, 'm' }
9422 -static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
9423 - { { STATE_PSEXCM }, 'i' },
9424 - { { STATE_PSRING }, 'i' },
9425 - { { STATE_DEPC }, 'm' }
9428 -static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
9429 - { { 6 /* art */ }, 'o' }
9432 -static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
9433 - { { STATE_PSEXCM }, 'i' },
9434 - { { STATE_PSRING }, 'i' },
9435 - { { STATE_EXCCAUSE }, 'i' },
9436 - { { STATE_XTSYNC }, 'i' }
9439 -static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
9440 - { { 6 /* art */ }, 'i' }
9443 -static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
9444 - { { STATE_PSEXCM }, 'i' },
9445 - { { STATE_PSRING }, 'i' },
9446 - { { STATE_EXCCAUSE }, 'o' }
9449 -static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
9450 - { { 6 /* art */ }, 'm' }
9453 -static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
9454 - { { STATE_PSEXCM }, 'i' },
9455 - { { STATE_PSRING }, 'i' },
9456 - { { STATE_EXCCAUSE }, 'm' }
9459 -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = {
9460 - { { 6 /* art */ }, 'o' }
9463 -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = {
9464 - { { STATE_PSEXCM }, 'i' },
9465 - { { STATE_PSRING }, 'i' },
9466 - { { STATE_MISC0 }, 'i' }
9469 -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = {
9470 - { { 6 /* art */ }, 'i' }
9473 -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = {
9474 - { { STATE_PSEXCM }, 'i' },
9475 - { { STATE_PSRING }, 'i' },
9476 - { { STATE_MISC0 }, 'o' }
9479 -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = {
9480 - { { 6 /* art */ }, 'm' }
9483 -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = {
9484 - { { STATE_PSEXCM }, 'i' },
9485 - { { STATE_PSRING }, 'i' },
9486 - { { STATE_MISC0 }, 'm' }
9489 -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = {
9490 - { { 6 /* art */ }, 'o' }
9493 -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = {
9494 - { { STATE_PSEXCM }, 'i' },
9495 - { { STATE_PSRING }, 'i' },
9496 - { { STATE_MISC1 }, 'i' }
9499 -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = {
9500 - { { 6 /* art */ }, 'i' }
9503 -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = {
9504 - { { STATE_PSEXCM }, 'i' },
9505 - { { STATE_PSRING }, 'i' },
9506 - { { STATE_MISC1 }, 'o' }
9509 -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = {
9510 - { { 6 /* art */ }, 'm' }
9513 -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = {
9514 - { { STATE_PSEXCM }, 'i' },
9515 - { { STATE_PSRING }, 'i' },
9516 - { { STATE_MISC1 }, 'm' }
9519 -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc2_args[] = {
9520 - { { 6 /* art */ }, 'o' }
9523 -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc2_stateArgs[] = {
9524 - { { STATE_PSEXCM }, 'i' },
9525 - { { STATE_PSRING }, 'i' },
9526 - { { STATE_MISC2 }, 'i' }
9529 -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc2_args[] = {
9530 - { { 6 /* art */ }, 'i' }
9533 -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc2_stateArgs[] = {
9534 - { { STATE_PSEXCM }, 'i' },
9535 - { { STATE_PSRING }, 'i' },
9536 - { { STATE_MISC2 }, 'o' }
9539 -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc2_args[] = {
9540 - { { 6 /* art */ }, 'm' }
9543 -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc2_stateArgs[] = {
9544 - { { STATE_PSEXCM }, 'i' },
9545 - { { STATE_PSRING }, 'i' },
9546 - { { STATE_MISC2 }, 'm' }
9549 -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc3_args[] = {
9550 - { { 6 /* art */ }, 'o' }
9553 -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc3_stateArgs[] = {
9554 - { { STATE_PSEXCM }, 'i' },
9555 - { { STATE_PSRING }, 'i' },
9556 - { { STATE_MISC3 }, 'i' }
9559 -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc3_args[] = {
9560 - { { 6 /* art */ }, 'i' }
9563 -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc3_stateArgs[] = {
9564 - { { STATE_PSEXCM }, 'i' },
9565 - { { STATE_PSRING }, 'i' },
9566 - { { STATE_MISC3 }, 'o' }
9569 -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc3_args[] = {
9570 - { { 6 /* art */ }, 'm' }
9573 -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc3_stateArgs[] = {
9574 - { { STATE_PSEXCM }, 'i' },
9575 - { { STATE_PSRING }, 'i' },
9576 - { { STATE_MISC3 }, 'm' }
9579 -static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
9580 - { { 6 /* art */ }, 'o' }
9583 -static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = {
9584 - { { STATE_PSEXCM }, 'i' },
9585 - { { STATE_PSRING }, 'i' }
9588 -static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = {
9589 - { { 6 /* art */ }, 'o' }
9592 -static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = {
9593 - { { STATE_PSEXCM }, 'i' },
9594 - { { STATE_PSRING }, 'i' },
9595 - { { STATE_VECBASE }, 'i' }
9598 -static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = {
9599 - { { 6 /* art */ }, 'i' }
9602 -static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = {
9603 - { { STATE_PSEXCM }, 'i' },
9604 - { { STATE_PSRING }, 'i' },
9605 - { { STATE_VECBASE }, 'o' }
9608 -static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = {
9609 - { { 6 /* art */ }, 'm' }
9612 -static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = {
9613 - { { STATE_PSEXCM }, 'i' },
9614 - { { STATE_PSRING }, 'i' },
9615 - { { STATE_VECBASE }, 'm' }
9618 -static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_args[] = {
9619 - { { 4 /* ars */ }, 'i' },
9620 - { { 6 /* art */ }, 'i' }
9623 -static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_stateArgs[] = {
9624 - { { STATE_ACC }, 'o' }
9627 -static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_args[] = {
9628 - { { 4 /* ars */ }, 'i' },
9629 - { { 34 /* my */ }, 'i' }
9632 -static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_stateArgs[] = {
9633 - { { STATE_ACC }, 'o' }
9636 -static xtensa_arg_internal Iclass_xt_iclass_mac16_da_args[] = {
9637 - { { 33 /* mx */ }, 'i' },
9638 - { { 6 /* art */ }, 'i' }
9641 -static xtensa_arg_internal Iclass_xt_iclass_mac16_da_stateArgs[] = {
9642 - { { STATE_ACC }, 'o' }
9645 -static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_args[] = {
9646 - { { 33 /* mx */ }, 'i' },
9647 - { { 34 /* my */ }, 'i' }
9650 -static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_stateArgs[] = {
9651 - { { STATE_ACC }, 'o' }
9654 -static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_args[] = {
9655 - { { 4 /* ars */ }, 'i' },
9656 - { { 6 /* art */ }, 'i' }
9659 -static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_stateArgs[] = {
9660 - { { STATE_ACC }, 'm' }
9663 -static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_args[] = {
9664 - { { 4 /* ars */ }, 'i' },
9665 - { { 34 /* my */ }, 'i' }
9668 -static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_stateArgs[] = {
9669 - { { STATE_ACC }, 'm' }
9672 -static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_args[] = {
9673 - { { 33 /* mx */ }, 'i' },
9674 - { { 6 /* art */ }, 'i' }
9677 -static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_stateArgs[] = {
9678 - { { STATE_ACC }, 'm' }
9681 -static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_args[] = {
9682 - { { 33 /* mx */ }, 'i' },
9683 - { { 34 /* my */ }, 'i' }
9686 -static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_stateArgs[] = {
9687 - { { STATE_ACC }, 'm' }
9690 -static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_args[] = {
9691 - { { 35 /* mw */ }, 'o' },
9692 - { { 4 /* ars */ }, 'm' },
9693 - { { 33 /* mx */ }, 'i' },
9694 - { { 6 /* art */ }, 'i' }
9697 -static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_stateArgs[] = {
9698 - { { STATE_ACC }, 'm' }
9701 -static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_args[] = {
9702 - { { 35 /* mw */ }, 'o' },
9703 - { { 4 /* ars */ }, 'm' },
9704 - { { 33 /* mx */ }, 'i' },
9705 - { { 34 /* my */ }, 'i' }
9708 -static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_stateArgs[] = {
9709 - { { STATE_ACC }, 'm' }
9712 -static xtensa_arg_internal Iclass_xt_iclass_mac16_l_args[] = {
9713 - { { 35 /* mw */ }, 'o' },
9714 - { { 4 /* ars */ }, 'm' }
9717 -static xtensa_arg_internal Iclass_xt_iclass_mul16_args[] = {
9718 - { { 3 /* arr */ }, 'o' },
9719 - { { 4 /* ars */ }, 'i' },
9720 - { { 6 /* art */ }, 'i' }
9723 -static xtensa_arg_internal Iclass_xt_iclass_rsr_m0_args[] = {
9724 - { { 6 /* art */ }, 'o' },
9725 - { { 36 /* mr0 */ }, 'i' }
9728 -static xtensa_arg_internal Iclass_xt_iclass_wsr_m0_args[] = {
9729 - { { 6 /* art */ }, 'i' },
9730 - { { 36 /* mr0 */ }, 'o' }
9733 -static xtensa_arg_internal Iclass_xt_iclass_xsr_m0_args[] = {
9734 - { { 6 /* art */ }, 'm' },
9735 - { { 36 /* mr0 */ }, 'm' }
9738 -static xtensa_arg_internal Iclass_xt_iclass_rsr_m1_args[] = {
9739 - { { 6 /* art */ }, 'o' },
9740 - { { 37 /* mr1 */ }, 'i' }
9743 -static xtensa_arg_internal Iclass_xt_iclass_wsr_m1_args[] = {
9744 - { { 6 /* art */ }, 'i' },
9745 - { { 37 /* mr1 */ }, 'o' }
9748 -static xtensa_arg_internal Iclass_xt_iclass_xsr_m1_args[] = {
9749 - { { 6 /* art */ }, 'm' },
9750 - { { 37 /* mr1 */ }, 'm' }
9753 -static xtensa_arg_internal Iclass_xt_iclass_rsr_m2_args[] = {
9754 - { { 6 /* art */ }, 'o' },
9755 - { { 38 /* mr2 */ }, 'i' }
9758 -static xtensa_arg_internal Iclass_xt_iclass_wsr_m2_args[] = {
9759 - { { 6 /* art */ }, 'i' },
9760 - { { 38 /* mr2 */ }, 'o' }
9763 -static xtensa_arg_internal Iclass_xt_iclass_xsr_m2_args[] = {
9764 - { { 6 /* art */ }, 'm' },
9765 - { { 38 /* mr2 */ }, 'm' }
9768 -static xtensa_arg_internal Iclass_xt_iclass_rsr_m3_args[] = {
9769 - { { 6 /* art */ }, 'o' },
9770 - { { 39 /* mr3 */ }, 'i' }
9773 -static xtensa_arg_internal Iclass_xt_iclass_wsr_m3_args[] = {
9774 - { { 6 /* art */ }, 'i' },
9775 - { { 39 /* mr3 */ }, 'o' }
9778 -static xtensa_arg_internal Iclass_xt_iclass_xsr_m3_args[] = {
9779 - { { 6 /* art */ }, 'm' },
9780 - { { 39 /* mr3 */ }, 'm' }
9783 -static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = {
9784 - { { 6 /* art */ }, 'o' }
9787 -static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_stateArgs[] = {
9788 - { { STATE_ACC }, 'i' }
9791 -static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = {
9792 - { { 6 /* art */ }, 'i' }
9795 -static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_stateArgs[] = {
9796 - { { STATE_ACC }, 'm' }
9799 -static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = {
9800 - { { 6 /* art */ }, 'm' }
9803 -static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_stateArgs[] = {
9804 - { { STATE_ACC }, 'm' }
9807 -static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = {
9808 - { { 6 /* art */ }, 'o' }
9811 -static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_stateArgs[] = {
9812 - { { STATE_ACC }, 'i' }
9815 -static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = {
9816 - { { 6 /* art */ }, 'i' }
9819 -static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_stateArgs[] = {
9820 - { { STATE_ACC }, 'm' }
9823 -static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = {
9824 - { { 6 /* art */ }, 'm' }
9827 -static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_stateArgs[] = {
9828 - { { STATE_ACC }, 'm' }
9831 -static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
9832 - { { 70 /* s */ }, 'i' }
9835 -static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
9836 - { { STATE_PSWOE }, 'o' },
9837 - { { STATE_PSCALLINC }, 'o' },
9838 - { { STATE_PSOWB }, 'o' },
9839 - { { STATE_PSRING }, 'm' },
9840 - { { STATE_PSUM }, 'o' },
9841 - { { STATE_PSEXCM }, 'm' },
9842 - { { STATE_PSINTLEVEL }, 'o' },
9843 - { { STATE_EPC1 }, 'i' },
9844 - { { STATE_EPC2 }, 'i' },
9845 - { { STATE_EPC3 }, 'i' },
9846 - { { STATE_EPC4 }, 'i' },
9847 - { { STATE_EPC5 }, 'i' },
9848 - { { STATE_EPC6 }, 'i' },
9849 - { { STATE_EPC7 }, 'i' },
9850 - { { STATE_EPS2 }, 'i' },
9851 - { { STATE_EPS3 }, 'i' },
9852 - { { STATE_EPS4 }, 'i' },
9853 - { { STATE_EPS5 }, 'i' },
9854 - { { STATE_EPS6 }, 'i' },
9855 - { { STATE_EPS7 }, 'i' },
9856 - { { STATE_InOCDMode }, 'm' }
9859 -static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
9860 - { { 70 /* s */ }, 'i' }
9863 -static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
9864 - { { STATE_PSEXCM }, 'i' },
9865 - { { STATE_PSRING }, 'i' },
9866 - { { STATE_PSINTLEVEL }, 'o' }
9869 -static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
9870 - { { 6 /* art */ }, 'o' }
9873 -static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
9874 - { { STATE_PSEXCM }, 'i' },
9875 - { { STATE_PSRING }, 'i' },
9876 - { { STATE_INTERRUPT }, 'i' }
9879 -static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
9880 - { { 6 /* art */ }, 'i' }
9883 -static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
9884 - { { STATE_PSEXCM }, 'i' },
9885 - { { STATE_PSRING }, 'i' },
9886 - { { STATE_XTSYNC }, 'o' },
9887 - { { STATE_INTERRUPT }, 'm' }
9890 -static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
9891 - { { 6 /* art */ }, 'i' }
9894 -static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
9895 - { { STATE_PSEXCM }, 'i' },
9896 - { { STATE_PSRING }, 'i' },
9897 - { { STATE_XTSYNC }, 'o' },
9898 - { { STATE_INTERRUPT }, 'm' }
9901 -static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
9902 - { { 6 /* art */ }, 'o' }
9905 -static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
9906 - { { STATE_PSEXCM }, 'i' },
9907 - { { STATE_PSRING }, 'i' },
9908 - { { STATE_INTENABLE }, 'i' }
9911 -static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
9912 - { { 6 /* art */ }, 'i' }
9915 -static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
9916 - { { STATE_PSEXCM }, 'i' },
9917 - { { STATE_PSRING }, 'i' },
9918 - { { STATE_INTENABLE }, 'o' }
9921 -static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
9922 - { { 6 /* art */ }, 'm' }
9925 -static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
9926 - { { STATE_PSEXCM }, 'i' },
9927 - { { STATE_PSRING }, 'i' },
9928 - { { STATE_INTENABLE }, 'm' }
9931 -static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
9932 - { { 41 /* imms */ }, 'i' },
9933 - { { 40 /* immt */ }, 'i' }
9936 -static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
9937 - { { STATE_PSEXCM }, 'i' },
9938 - { { STATE_PSINTLEVEL }, 'i' }
9941 -static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
9942 - { { 41 /* imms */ }, 'i' }
9945 -static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
9946 - { { STATE_PSEXCM }, 'i' },
9947 - { { STATE_PSINTLEVEL }, 'i' }
9950 -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = {
9951 - { { 6 /* art */ }, 'o' }
9954 -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = {
9955 - { { STATE_PSEXCM }, 'i' },
9956 - { { STATE_PSRING }, 'i' },
9957 - { { STATE_DBREAKA0 }, 'i' }
9960 -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = {
9961 - { { 6 /* art */ }, 'i' }
9964 -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = {
9965 - { { STATE_PSEXCM }, 'i' },
9966 - { { STATE_PSRING }, 'i' },
9967 - { { STATE_DBREAKA0 }, 'o' },
9968 - { { STATE_XTSYNC }, 'o' }
9971 -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = {
9972 - { { 6 /* art */ }, 'm' }
9975 -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = {
9976 - { { STATE_PSEXCM }, 'i' },
9977 - { { STATE_PSRING }, 'i' },
9978 - { { STATE_DBREAKA0 }, 'm' },
9979 - { { STATE_XTSYNC }, 'o' }
9982 -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = {
9983 - { { 6 /* art */ }, 'o' }
9986 -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = {
9987 - { { STATE_PSEXCM }, 'i' },
9988 - { { STATE_PSRING }, 'i' },
9989 - { { STATE_DBREAKC0 }, 'i' }
9992 -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = {
9993 - { { 6 /* art */ }, 'i' }
9996 -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = {
9997 - { { STATE_PSEXCM }, 'i' },
9998 - { { STATE_PSRING }, 'i' },
9999 - { { STATE_DBREAKC0 }, 'o' },
10000 - { { STATE_XTSYNC }, 'o' }
10003 -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = {
10004 - { { 6 /* art */ }, 'm' }
10007 -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = {
10008 - { { STATE_PSEXCM }, 'i' },
10009 - { { STATE_PSRING }, 'i' },
10010 - { { STATE_DBREAKC0 }, 'm' },
10011 - { { STATE_XTSYNC }, 'o' }
10014 -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = {
10015 - { { 6 /* art */ }, 'o' }
10018 -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = {
10019 - { { STATE_PSEXCM }, 'i' },
10020 - { { STATE_PSRING }, 'i' },
10021 - { { STATE_DBREAKA1 }, 'i' }
10024 -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = {
10025 - { { 6 /* art */ }, 'i' }
10028 -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = {
10029 - { { STATE_PSEXCM }, 'i' },
10030 - { { STATE_PSRING }, 'i' },
10031 - { { STATE_DBREAKA1 }, 'o' },
10032 - { { STATE_XTSYNC }, 'o' }
10035 -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = {
10036 - { { 6 /* art */ }, 'm' }
10039 -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = {
10040 - { { STATE_PSEXCM }, 'i' },
10041 - { { STATE_PSRING }, 'i' },
10042 - { { STATE_DBREAKA1 }, 'm' },
10043 - { { STATE_XTSYNC }, 'o' }
10046 -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = {
10047 - { { 6 /* art */ }, 'o' }
10050 -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = {
10051 - { { STATE_PSEXCM }, 'i' },
10052 - { { STATE_PSRING }, 'i' },
10053 - { { STATE_DBREAKC1 }, 'i' }
10056 -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = {
10057 - { { 6 /* art */ }, 'i' }
10060 -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = {
10061 - { { STATE_PSEXCM }, 'i' },
10062 - { { STATE_PSRING }, 'i' },
10063 - { { STATE_DBREAKC1 }, 'o' },
10064 - { { STATE_XTSYNC }, 'o' }
10067 -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = {
10068 - { { 6 /* art */ }, 'm' }
10071 -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = {
10072 - { { STATE_PSEXCM }, 'i' },
10073 - { { STATE_PSRING }, 'i' },
10074 - { { STATE_DBREAKC1 }, 'm' },
10075 - { { STATE_XTSYNC }, 'o' }
10078 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = {
10079 - { { 6 /* art */ }, 'o' }
10082 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = {
10083 - { { STATE_PSEXCM }, 'i' },
10084 - { { STATE_PSRING }, 'i' },
10085 - { { STATE_IBREAKA0 }, 'i' }
10088 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = {
10089 - { { 6 /* art */ }, 'i' }
10092 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = {
10093 - { { STATE_PSEXCM }, 'i' },
10094 - { { STATE_PSRING }, 'i' },
10095 - { { STATE_IBREAKA0 }, 'o' }
10098 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = {
10099 - { { 6 /* art */ }, 'm' }
10102 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = {
10103 - { { STATE_PSEXCM }, 'i' },
10104 - { { STATE_PSRING }, 'i' },
10105 - { { STATE_IBREAKA0 }, 'm' }
10108 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = {
10109 - { { 6 /* art */ }, 'o' }
10112 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = {
10113 - { { STATE_PSEXCM }, 'i' },
10114 - { { STATE_PSRING }, 'i' },
10115 - { { STATE_IBREAKA1 }, 'i' }
10118 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = {
10119 - { { 6 /* art */ }, 'i' }
10122 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = {
10123 - { { STATE_PSEXCM }, 'i' },
10124 - { { STATE_PSRING }, 'i' },
10125 - { { STATE_IBREAKA1 }, 'o' }
10128 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = {
10129 - { { 6 /* art */ }, 'm' }
10132 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = {
10133 - { { STATE_PSEXCM }, 'i' },
10134 - { { STATE_PSRING }, 'i' },
10135 - { { STATE_IBREAKA1 }, 'm' }
10138 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = {
10139 - { { 6 /* art */ }, 'o' }
10142 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = {
10143 - { { STATE_PSEXCM }, 'i' },
10144 - { { STATE_PSRING }, 'i' },
10145 - { { STATE_IBREAKENABLE }, 'i' }
10148 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = {
10149 - { { 6 /* art */ }, 'i' }
10152 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = {
10153 - { { STATE_PSEXCM }, 'i' },
10154 - { { STATE_PSRING }, 'i' },
10155 - { { STATE_IBREAKENABLE }, 'o' }
10158 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = {
10159 - { { 6 /* art */ }, 'm' }
10162 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = {
10163 - { { STATE_PSEXCM }, 'i' },
10164 - { { STATE_PSRING }, 'i' },
10165 - { { STATE_IBREAKENABLE }, 'm' }
10168 -static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = {
10169 - { { 6 /* art */ }, 'o' }
10172 -static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = {
10173 - { { STATE_PSEXCM }, 'i' },
10174 - { { STATE_PSRING }, 'i' },
10175 - { { STATE_DEBUGCAUSE }, 'i' },
10176 - { { STATE_DBNUM }, 'i' }
10179 -static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = {
10180 - { { 6 /* art */ }, 'i' }
10183 -static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = {
10184 - { { STATE_PSEXCM }, 'i' },
10185 - { { STATE_PSRING }, 'i' },
10186 - { { STATE_DEBUGCAUSE }, 'o' },
10187 - { { STATE_DBNUM }, 'o' }
10190 -static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = {
10191 - { { 6 /* art */ }, 'm' }
10194 -static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = {
10195 - { { STATE_PSEXCM }, 'i' },
10196 - { { STATE_PSRING }, 'i' },
10197 - { { STATE_DEBUGCAUSE }, 'm' },
10198 - { { STATE_DBNUM }, 'm' }
10201 -static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = {
10202 - { { 6 /* art */ }, 'o' }
10205 -static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = {
10206 - { { STATE_PSEXCM }, 'i' },
10207 - { { STATE_PSRING }, 'i' },
10208 - { { STATE_ICOUNT }, 'i' }
10211 -static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = {
10212 - { { 6 /* art */ }, 'i' }
10215 -static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = {
10216 - { { STATE_PSEXCM }, 'i' },
10217 - { { STATE_PSRING }, 'i' },
10218 - { { STATE_XTSYNC }, 'o' },
10219 - { { STATE_ICOUNT }, 'o' }
10222 -static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = {
10223 - { { 6 /* art */ }, 'm' }
10226 -static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = {
10227 - { { STATE_PSEXCM }, 'i' },
10228 - { { STATE_PSRING }, 'i' },
10229 - { { STATE_XTSYNC }, 'o' },
10230 - { { STATE_ICOUNT }, 'm' }
10233 -static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = {
10234 - { { 6 /* art */ }, 'o' }
10237 -static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = {
10238 - { { STATE_PSEXCM }, 'i' },
10239 - { { STATE_PSRING }, 'i' },
10240 - { { STATE_ICOUNTLEVEL }, 'i' }
10243 -static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = {
10244 - { { 6 /* art */ }, 'i' }
10247 -static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = {
10248 - { { STATE_PSEXCM }, 'i' },
10249 - { { STATE_PSRING }, 'i' },
10250 - { { STATE_ICOUNTLEVEL }, 'o' }
10253 -static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = {
10254 - { { 6 /* art */ }, 'm' }
10257 -static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = {
10258 - { { STATE_PSEXCM }, 'i' },
10259 - { { STATE_PSRING }, 'i' },
10260 - { { STATE_ICOUNTLEVEL }, 'm' }
10263 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = {
10264 - { { 6 /* art */ }, 'o' }
10267 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = {
10268 - { { STATE_PSEXCM }, 'i' },
10269 - { { STATE_PSRING }, 'i' },
10270 - { { STATE_DDR }, 'i' }
10273 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = {
10274 - { { 6 /* art */ }, 'i' }
10277 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = {
10278 - { { STATE_PSEXCM }, 'i' },
10279 - { { STATE_PSRING }, 'i' },
10280 - { { STATE_XTSYNC }, 'o' },
10281 - { { STATE_DDR }, 'o' }
10284 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = {
10285 - { { 6 /* art */ }, 'm' }
10288 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = {
10289 - { { STATE_PSEXCM }, 'i' },
10290 - { { STATE_PSRING }, 'i' },
10291 - { { STATE_XTSYNC }, 'o' },
10292 - { { STATE_DDR }, 'm' }
10295 -static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = {
10296 - { { 41 /* imms */ }, 'i' }
10299 -static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = {
10300 - { { STATE_InOCDMode }, 'm' },
10301 - { { STATE_EPC6 }, 'i' },
10302 - { { STATE_PSWOE }, 'o' },
10303 - { { STATE_PSCALLINC }, 'o' },
10304 - { { STATE_PSOWB }, 'o' },
10305 - { { STATE_PSRING }, 'o' },
10306 - { { STATE_PSUM }, 'o' },
10307 - { { STATE_PSEXCM }, 'o' },
10308 - { { STATE_PSINTLEVEL }, 'o' },
10309 - { { STATE_EPS6 }, 'i' }
10312 -static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = {
10313 - { { STATE_InOCDMode }, 'm' }
10316 -static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = {
10317 - { { 6 /* art */ }, 'i' }
10320 -static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = {
10321 - { { STATE_PSEXCM }, 'i' },
10322 - { { STATE_PSRING }, 'i' },
10323 - { { STATE_XTSYNC }, 'o' }
10326 -static xtensa_arg_internal Iclass_xt_iclass_bbool1_args[] = {
10327 - { { 44 /* br */ }, 'o' },
10328 - { { 43 /* bs */ }, 'i' },
10329 - { { 42 /* bt */ }, 'i' }
10332 -static xtensa_arg_internal Iclass_xt_iclass_bbool4_args[] = {
10333 - { { 42 /* bt */ }, 'o' },
10334 - { { 49 /* bs4 */ }, 'i' }
10337 -static xtensa_arg_internal Iclass_xt_iclass_bbool8_args[] = {
10338 - { { 42 /* bt */ }, 'o' },
10339 - { { 52 /* bs8 */ }, 'i' }
10342 -static xtensa_arg_internal Iclass_xt_iclass_bbranch_args[] = {
10343 - { { 43 /* bs */ }, 'i' },
10344 - { { 28 /* label8 */ }, 'i' }
10347 -static xtensa_arg_internal Iclass_xt_iclass_bmove_args[] = {
10348 - { { 3 /* arr */ }, 'm' },
10349 - { { 4 /* ars */ }, 'i' },
10350 - { { 42 /* bt */ }, 'i' }
10353 -static xtensa_arg_internal Iclass_xt_iclass_RSR_BR_args[] = {
10354 - { { 6 /* art */ }, 'o' },
10355 - { { 57 /* brall */ }, 'i' }
10358 -static xtensa_arg_internal Iclass_xt_iclass_WSR_BR_args[] = {
10359 - { { 6 /* art */ }, 'i' },
10360 - { { 57 /* brall */ }, 'o' }
10363 -static xtensa_arg_internal Iclass_xt_iclass_XSR_BR_args[] = {
10364 - { { 6 /* art */ }, 'm' },
10365 - { { 57 /* brall */ }, 'm' }
10368 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = {
10369 - { { 6 /* art */ }, 'o' }
10372 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = {
10373 - { { STATE_PSEXCM }, 'i' },
10374 - { { STATE_PSRING }, 'i' },
10375 - { { STATE_CCOUNT }, 'i' }
10378 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = {
10379 - { { 6 /* art */ }, 'i' }
10382 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = {
10383 - { { STATE_PSEXCM }, 'i' },
10384 - { { STATE_PSRING }, 'i' },
10385 - { { STATE_XTSYNC }, 'o' },
10386 - { { STATE_CCOUNT }, 'o' }
10389 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = {
10390 - { { 6 /* art */ }, 'm' }
10393 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = {
10394 - { { STATE_PSEXCM }, 'i' },
10395 - { { STATE_PSRING }, 'i' },
10396 - { { STATE_XTSYNC }, 'o' },
10397 - { { STATE_CCOUNT }, 'm' }
10400 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = {
10401 - { { 6 /* art */ }, 'o' }
10404 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = {
10405 - { { STATE_PSEXCM }, 'i' },
10406 - { { STATE_PSRING }, 'i' },
10407 - { { STATE_CCOMPARE0 }, 'i' }
10410 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = {
10411 - { { 6 /* art */ }, 'i' }
10414 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = {
10415 - { { STATE_PSEXCM }, 'i' },
10416 - { { STATE_PSRING }, 'i' },
10417 - { { STATE_CCOMPARE0 }, 'o' },
10418 - { { STATE_INTERRUPT }, 'm' }
10421 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = {
10422 - { { 6 /* art */ }, 'm' }
10425 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = {
10426 - { { STATE_PSEXCM }, 'i' },
10427 - { { STATE_PSRING }, 'i' },
10428 - { { STATE_CCOMPARE0 }, 'm' },
10429 - { { STATE_INTERRUPT }, 'm' }
10432 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = {
10433 - { { 6 /* art */ }, 'o' }
10436 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = {
10437 - { { STATE_PSEXCM }, 'i' },
10438 - { { STATE_PSRING }, 'i' },
10439 - { { STATE_CCOMPARE1 }, 'i' }
10442 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = {
10443 - { { 6 /* art */ }, 'i' }
10446 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = {
10447 - { { STATE_PSEXCM }, 'i' },
10448 - { { STATE_PSRING }, 'i' },
10449 - { { STATE_CCOMPARE1 }, 'o' },
10450 - { { STATE_INTERRUPT }, 'm' }
10453 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = {
10454 - { { 6 /* art */ }, 'm' }
10457 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = {
10458 - { { STATE_PSEXCM }, 'i' },
10459 - { { STATE_PSRING }, 'i' },
10460 - { { STATE_CCOMPARE1 }, 'm' },
10461 - { { STATE_INTERRUPT }, 'm' }
10464 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = {
10465 - { { 6 /* art */ }, 'o' }
10468 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = {
10469 - { { STATE_PSEXCM }, 'i' },
10470 - { { STATE_PSRING }, 'i' },
10471 - { { STATE_CCOMPARE2 }, 'i' }
10474 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = {
10475 - { { 6 /* art */ }, 'i' }
10478 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = {
10479 - { { STATE_PSEXCM }, 'i' },
10480 - { { STATE_PSRING }, 'i' },
10481 - { { STATE_CCOMPARE2 }, 'o' },
10482 - { { STATE_INTERRUPT }, 'm' }
10485 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = {
10486 - { { 6 /* art */ }, 'm' }
10489 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = {
10490 - { { STATE_PSEXCM }, 'i' },
10491 - { { STATE_PSRING }, 'i' },
10492 - { { STATE_CCOMPARE2 }, 'm' },
10493 - { { STATE_INTERRUPT }, 'm' }
10496 -static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = {
10497 - { { 4 /* ars */ }, 'i' },
10498 - { { 21 /* uimm8x4 */ }, 'i' }
10501 -static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = {
10502 - { { 4 /* ars */ }, 'i' },
10503 - { { 22 /* uimm4x16 */ }, 'i' }
10506 -static xtensa_arg_internal Iclass_xt_iclass_icache_lock_stateArgs[] = {
10507 - { { STATE_PSEXCM }, 'i' },
10508 - { { STATE_PSRING }, 'i' }
10511 -static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = {
10512 - { { 4 /* ars */ }, 'i' },
10513 - { { 21 /* uimm8x4 */ }, 'i' }
10516 -static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = {
10517 - { { STATE_PSEXCM }, 'i' },
10518 - { { STATE_PSRING }, 'i' }
10521 -static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = {
10522 - { { 6 /* art */ }, 'o' },
10523 - { { 4 /* ars */ }, 'i' }
10526 -static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = {
10527 - { { STATE_PSEXCM }, 'i' },
10528 - { { STATE_PSRING }, 'i' }
10531 -static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = {
10532 - { { 6 /* art */ }, 'i' },
10533 - { { 4 /* ars */ }, 'i' }
10536 -static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = {
10537 - { { STATE_PSEXCM }, 'i' },
10538 - { { STATE_PSRING }, 'i' }
10541 -static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = {
10542 - { { 4 /* ars */ }, 'i' },
10543 - { { 21 /* uimm8x4 */ }, 'i' }
10546 -static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = {
10547 - { { 4 /* ars */ }, 'i' },
10548 - { { 22 /* uimm4x16 */ }, 'i' }
10551 -static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = {
10552 - { { STATE_PSEXCM }, 'i' },
10553 - { { STATE_PSRING }, 'i' }
10556 -static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = {
10557 - { { 4 /* ars */ }, 'i' },
10558 - { { 21 /* uimm8x4 */ }, 'i' }
10561 -static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = {
10562 - { { STATE_PSEXCM }, 'i' },
10563 - { { STATE_PSRING }, 'i' }
10566 -static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = {
10567 - { { 4 /* ars */ }, 'i' },
10568 - { { 21 /* uimm8x4 */ }, 'i' }
10571 -static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = {
10572 - { { 4 /* ars */ }, 'i' },
10573 - { { 22 /* uimm4x16 */ }, 'i' }
10576 -static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_stateArgs[] = {
10577 - { { STATE_PSEXCM }, 'i' },
10578 - { { STATE_PSRING }, 'i' }
10581 -static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = {
10582 - { { 6 /* art */ }, 'i' },
10583 - { { 4 /* ars */ }, 'i' }
10586 -static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = {
10587 - { { STATE_PSEXCM }, 'i' },
10588 - { { STATE_PSRING }, 'i' }
10591 -static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = {
10592 - { { 6 /* art */ }, 'o' },
10593 - { { 4 /* ars */ }, 'i' }
10596 -static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = {
10597 - { { STATE_PSEXCM }, 'i' },
10598 - { { STATE_PSRING }, 'i' }
10601 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = {
10602 - { { 6 /* art */ }, 'i' }
10605 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = {
10606 - { { STATE_PSEXCM }, 'i' },
10607 - { { STATE_PSRING }, 'i' },
10608 - { { STATE_PTBASE }, 'o' },
10609 - { { STATE_XTSYNC }, 'o' }
10612 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = {
10613 - { { 6 /* art */ }, 'o' }
10616 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = {
10617 - { { STATE_PSEXCM }, 'i' },
10618 - { { STATE_PSRING }, 'i' },
10619 - { { STATE_PTBASE }, 'i' },
10620 - { { STATE_EXCVADDR }, 'i' }
10623 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = {
10624 - { { 6 /* art */ }, 'm' }
10627 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = {
10628 - { { STATE_PSEXCM }, 'i' },
10629 - { { STATE_PSRING }, 'i' },
10630 - { { STATE_PTBASE }, 'm' },
10631 - { { STATE_EXCVADDR }, 'i' },
10632 - { { STATE_XTSYNC }, 'o' }
10635 -static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = {
10636 - { { 6 /* art */ }, 'o' }
10639 -static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = {
10640 - { { STATE_PSEXCM }, 'i' },
10641 - { { STATE_PSRING }, 'i' },
10642 - { { STATE_ASID3 }, 'i' },
10643 - { { STATE_ASID2 }, 'i' },
10644 - { { STATE_ASID1 }, 'i' }
10647 -static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = {
10648 - { { 6 /* art */ }, 'i' }
10651 -static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = {
10652 - { { STATE_XTSYNC }, 'o' },
10653 - { { STATE_PSEXCM }, 'i' },
10654 - { { STATE_PSRING }, 'i' },
10655 - { { STATE_ASID3 }, 'o' },
10656 - { { STATE_ASID2 }, 'o' },
10657 - { { STATE_ASID1 }, 'o' }
10660 -static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = {
10661 - { { 6 /* art */ }, 'm' }
10664 -static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = {
10665 - { { STATE_XTSYNC }, 'o' },
10666 - { { STATE_PSEXCM }, 'i' },
10667 - { { STATE_PSRING }, 'i' },
10668 - { { STATE_ASID3 }, 'm' },
10669 - { { STATE_ASID2 }, 'm' },
10670 - { { STATE_ASID1 }, 'm' }
10673 -static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = {
10674 - { { 6 /* art */ }, 'o' }
10677 -static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = {
10678 - { { STATE_PSEXCM }, 'i' },
10679 - { { STATE_PSRING }, 'i' },
10680 - { { STATE_INSTPGSZID4 }, 'i' }
10683 -static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = {
10684 - { { 6 /* art */ }, 'i' }
10687 -static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = {
10688 - { { STATE_XTSYNC }, 'o' },
10689 - { { STATE_PSEXCM }, 'i' },
10690 - { { STATE_PSRING }, 'i' },
10691 - { { STATE_INSTPGSZID4 }, 'o' }
10694 -static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = {
10695 - { { 6 /* art */ }, 'm' }
10698 -static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = {
10699 - { { STATE_XTSYNC }, 'o' },
10700 - { { STATE_PSEXCM }, 'i' },
10701 - { { STATE_PSRING }, 'i' },
10702 - { { STATE_INSTPGSZID4 }, 'm' }
10705 -static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = {
10706 - { { 6 /* art */ }, 'o' }
10709 -static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = {
10710 - { { STATE_PSEXCM }, 'i' },
10711 - { { STATE_PSRING }, 'i' },
10712 - { { STATE_DATAPGSZID4 }, 'i' }
10715 -static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = {
10716 - { { 6 /* art */ }, 'i' }
10719 -static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = {
10720 - { { STATE_XTSYNC }, 'o' },
10721 - { { STATE_PSEXCM }, 'i' },
10722 - { { STATE_PSRING }, 'i' },
10723 - { { STATE_DATAPGSZID4 }, 'o' }
10726 -static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = {
10727 - { { 6 /* art */ }, 'm' }
10730 -static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = {
10731 - { { STATE_XTSYNC }, 'o' },
10732 - { { STATE_PSEXCM }, 'i' },
10733 - { { STATE_PSRING }, 'i' },
10734 - { { STATE_DATAPGSZID4 }, 'm' }
10737 -static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = {
10738 - { { 4 /* ars */ }, 'i' }
10741 -static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = {
10742 - { { STATE_PSEXCM }, 'i' },
10743 - { { STATE_PSRING }, 'i' },
10744 - { { STATE_XTSYNC }, 'o' }
10747 -static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = {
10748 - { { 6 /* art */ }, 'o' },
10749 - { { 4 /* ars */ }, 'i' }
10752 -static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = {
10753 - { { STATE_PSEXCM }, 'i' },
10754 - { { STATE_PSRING }, 'i' }
10757 -static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = {
10758 - { { 6 /* art */ }, 'i' },
10759 - { { 4 /* ars */ }, 'i' }
10762 -static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = {
10763 - { { STATE_PSEXCM }, 'i' },
10764 - { { STATE_PSRING }, 'i' },
10765 - { { STATE_XTSYNC }, 'o' }
10768 -static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = {
10769 - { { 4 /* ars */ }, 'i' }
10772 -static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = {
10773 - { { STATE_PSEXCM }, 'i' },
10774 - { { STATE_PSRING }, 'i' }
10777 -static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = {
10778 - { { 6 /* art */ }, 'o' },
10779 - { { 4 /* ars */ }, 'i' }
10782 -static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = {
10783 - { { STATE_PSEXCM }, 'i' },
10784 - { { STATE_PSRING }, 'i' }
10787 -static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = {
10788 - { { 6 /* art */ }, 'i' },
10789 - { { 4 /* ars */ }, 'i' }
10792 -static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = {
10793 - { { STATE_PSEXCM }, 'i' },
10794 - { { STATE_PSRING }, 'i' }
10797 -static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = {
10798 - { { STATE_PTBASE }, 'i' },
10799 - { { STATE_EXCVADDR }, 'i' }
10802 -static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = {
10803 - { { STATE_EXCVADDR }, 'i' }
10806 -static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = {
10807 - { { STATE_EXCVADDR }, 'i' }
10810 -static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = {
10811 - { { 6 /* art */ }, 'o' }
10814 -static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = {
10815 - { { STATE_PSEXCM }, 'i' },
10816 - { { STATE_PSRING }, 'i' },
10817 - { { STATE_CPENABLE }, 'i' }
10820 -static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = {
10821 - { { 6 /* art */ }, 'i' }
10824 -static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = {
10825 - { { STATE_PSEXCM }, 'i' },
10826 - { { STATE_PSRING }, 'i' },
10827 - { { STATE_CPENABLE }, 'o' }
10830 -static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = {
10831 - { { 6 /* art */ }, 'm' }
10834 -static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = {
10835 - { { STATE_PSEXCM }, 'i' },
10836 - { { STATE_PSRING }, 'i' },
10837 - { { STATE_CPENABLE }, 'm' }
10840 -static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = {
10841 - { { 3 /* arr */ }, 'o' },
10842 - { { 4 /* ars */ }, 'i' },
10843 - { { 58 /* tp7 */ }, 'i' }
10846 -static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = {
10847 - { { 3 /* arr */ }, 'o' },
10848 - { { 4 /* ars */ }, 'i' },
10849 - { { 6 /* art */ }, 'i' }
10852 -static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = {
10853 - { { 6 /* art */ }, 'o' },
10854 - { { 4 /* ars */ }, 'i' }
10857 -static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = {
10858 - { { 3 /* arr */ }, 'o' },
10859 - { { 4 /* ars */ }, 'i' },
10860 - { { 58 /* tp7 */ }, 'i' }
10863 -static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = {
10864 - { { 6 /* art */ }, 'o' },
10865 - { { 4 /* ars */ }, 'i' },
10866 - { { 21 /* uimm8x4 */ }, 'i' }
10869 -static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = {
10870 - { { 6 /* art */ }, 'i' },
10871 - { { 4 /* ars */ }, 'i' },
10872 - { { 21 /* uimm8x4 */ }, 'i' }
10875 -static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = {
10876 - { { 6 /* art */ }, 'm' },
10877 - { { 4 /* ars */ }, 'i' },
10878 - { { 21 /* uimm8x4 */ }, 'i' }
10881 -static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = {
10882 - { { STATE_SCOMPARE1 }, 'i' },
10883 - { { STATE_SCOMPARE1 }, 'i' }
10886 -static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = {
10887 - { { 6 /* art */ }, 'o' }
10890 -static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = {
10891 - { { STATE_SCOMPARE1 }, 'i' }
10894 -static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = {
10895 - { { 6 /* art */ }, 'i' }
10898 -static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = {
10899 - { { STATE_SCOMPARE1 }, 'o' }
10902 -static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = {
10903 - { { 6 /* art */ }, 'm' }
10906 -static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = {
10907 - { { STATE_SCOMPARE1 }, 'm' }
10910 -static xtensa_arg_internal Iclass_xt_iclass_div_args[] = {
10911 - { { 3 /* arr */ }, 'o' },
10912 - { { 4 /* ars */ }, 'i' },
10913 - { { 6 /* art */ }, 'i' }
10916 -static xtensa_arg_internal Iclass_xt_mul32_args[] = {
10917 - { { 3 /* arr */ }, 'o' },
10918 - { { 4 /* ars */ }, 'i' },
10919 - { { 6 /* art */ }, 'i' }
10922 -static xtensa_arg_internal Iclass_rur_fcr_args[] = {
10923 - { { 3 /* arr */ }, 'o' }
10926 -static xtensa_arg_internal Iclass_rur_fcr_stateArgs[] = {
10927 - { { STATE_RoundMode }, 'i' },
10928 - { { STATE_InvalidEnable }, 'i' },
10929 - { { STATE_DivZeroEnable }, 'i' },
10930 - { { STATE_OverflowEnable }, 'i' },
10931 - { { STATE_UnderflowEnable }, 'i' },
10932 - { { STATE_InexactEnable }, 'i' },
10933 - { { STATE_FPreserved20 }, 'i' },
10934 - { { STATE_FPreserved5 }, 'i' },
10935 - { { STATE_CPENABLE }, 'i' }
10938 -static xtensa_arg_internal Iclass_wur_fcr_args[] = {
10939 - { { 6 /* art */ }, 'i' }
10942 -static xtensa_arg_internal Iclass_wur_fcr_stateArgs[] = {
10943 - { { STATE_RoundMode }, 'o' },
10944 - { { STATE_InvalidEnable }, 'o' },
10945 - { { STATE_DivZeroEnable }, 'o' },
10946 - { { STATE_OverflowEnable }, 'o' },
10947 - { { STATE_UnderflowEnable }, 'o' },
10948 - { { STATE_InexactEnable }, 'o' },
10949 - { { STATE_FPreserved20 }, 'o' },
10950 - { { STATE_FPreserved5 }, 'o' },
10951 - { { STATE_CPENABLE }, 'i' }
10954 -static xtensa_arg_internal Iclass_rur_fsr_args[] = {
10955 - { { 3 /* arr */ }, 'o' }
10958 -static xtensa_arg_internal Iclass_rur_fsr_stateArgs[] = {
10959 - { { STATE_InvalidFlag }, 'i' },
10960 - { { STATE_DivZeroFlag }, 'i' },
10961 - { { STATE_OverflowFlag }, 'i' },
10962 - { { STATE_UnderflowFlag }, 'i' },
10963 - { { STATE_InexactFlag }, 'i' },
10964 - { { STATE_FPreserved20a }, 'i' },
10965 - { { STATE_FPreserved7 }, 'i' },
10966 - { { STATE_CPENABLE }, 'i' }
10969 -static xtensa_arg_internal Iclass_wur_fsr_args[] = {
10970 - { { 6 /* art */ }, 'i' }
10973 -static xtensa_arg_internal Iclass_wur_fsr_stateArgs[] = {
10974 - { { STATE_InvalidFlag }, 'o' },
10975 - { { STATE_DivZeroFlag }, 'o' },
10976 - { { STATE_OverflowFlag }, 'o' },
10977 - { { STATE_UnderflowFlag }, 'o' },
10978 - { { STATE_InexactFlag }, 'o' },
10979 - { { STATE_FPreserved20a }, 'o' },
10980 - { { STATE_FPreserved7 }, 'o' },
10981 - { { STATE_CPENABLE }, 'i' }
10984 -static xtensa_arg_internal Iclass_fp_args[] = {
10985 - { { 62 /* frr */ }, 'o' },
10986 - { { 63 /* frs */ }, 'i' },
10987 - { { 64 /* frt */ }, 'i' }
10990 -static xtensa_arg_internal Iclass_fp_stateArgs[] = {
10991 - { { STATE_RoundMode }, 'i' },
10992 - { { STATE_CPENABLE }, 'i' }
10995 -static xtensa_arg_internal Iclass_fp_mac_args[] = {
10996 - { { 62 /* frr */ }, 'm' },
10997 - { { 63 /* frs */ }, 'i' },
10998 - { { 64 /* frt */ }, 'i' }
11001 -static xtensa_arg_internal Iclass_fp_mac_stateArgs[] = {
11002 - { { STATE_RoundMode }, 'i' },
11003 - { { STATE_CPENABLE }, 'i' }
11006 -static xtensa_arg_internal Iclass_fp_cmov_args[] = {
11007 - { { 62 /* frr */ }, 'm' },
11008 - { { 63 /* frs */ }, 'i' },
11009 - { { 42 /* bt */ }, 'i' }
11012 -static xtensa_arg_internal Iclass_fp_cmov_stateArgs[] = {
11013 - { { STATE_CPENABLE }, 'i' }
11016 -static xtensa_arg_internal Iclass_fp_mov_args[] = {
11017 - { { 62 /* frr */ }, 'm' },
11018 - { { 63 /* frs */ }, 'i' },
11019 - { { 6 /* art */ }, 'i' }
11022 -static xtensa_arg_internal Iclass_fp_mov_stateArgs[] = {
11023 - { { STATE_CPENABLE }, 'i' }
11026 -static xtensa_arg_internal Iclass_fp_mov2_args[] = {
11027 - { { 62 /* frr */ }, 'o' },
11028 - { { 63 /* frs */ }, 'i' }
11031 -static xtensa_arg_internal Iclass_fp_mov2_stateArgs[] = {
11032 - { { STATE_CPENABLE }, 'i' }
11035 -static xtensa_arg_internal Iclass_fp_cmp_args[] = {
11036 - { { 44 /* br */ }, 'o' },
11037 - { { 63 /* frs */ }, 'i' },
11038 - { { 64 /* frt */ }, 'i' }
11041 -static xtensa_arg_internal Iclass_fp_cmp_stateArgs[] = {
11042 - { { STATE_CPENABLE }, 'i' }
11045 -static xtensa_arg_internal Iclass_fp_float_args[] = {
11046 - { { 62 /* frr */ }, 'o' },
11047 - { { 4 /* ars */ }, 'i' },
11048 - { { 65 /* t */ }, 'i' }
11051 -static xtensa_arg_internal Iclass_fp_float_stateArgs[] = {
11052 - { { STATE_RoundMode }, 'i' },
11053 - { { STATE_CPENABLE }, 'i' }
11056 -static xtensa_arg_internal Iclass_fp_int_args[] = {
11057 - { { 3 /* arr */ }, 'o' },
11058 - { { 63 /* frs */ }, 'i' },
11059 - { { 65 /* t */ }, 'i' }
11062 -static xtensa_arg_internal Iclass_fp_int_stateArgs[] = {
11063 - { { STATE_CPENABLE }, 'i' }
11066 -static xtensa_arg_internal Iclass_fp_rfr_args[] = {
11067 - { { 3 /* arr */ }, 'o' },
11068 - { { 63 /* frs */ }, 'i' }
11071 -static xtensa_arg_internal Iclass_fp_rfr_stateArgs[] = {
11072 - { { STATE_CPENABLE }, 'i' }
11075 -static xtensa_arg_internal Iclass_fp_wfr_args[] = {
11076 - { { 62 /* frr */ }, 'o' },
11077 - { { 4 /* ars */ }, 'i' }
11080 -static xtensa_arg_internal Iclass_fp_wfr_stateArgs[] = {
11081 - { { STATE_CPENABLE }, 'i' }
11084 -static xtensa_arg_internal Iclass_fp_lsi_args[] = {
11085 - { { 64 /* frt */ }, 'o' },
11086 - { { 4 /* ars */ }, 'i' },
11087 - { { 61 /* cimm8x4 */ }, 'i' }
11090 -static xtensa_arg_internal Iclass_fp_lsi_stateArgs[] = {
11091 - { { STATE_CPENABLE }, 'i' }
11094 -static xtensa_arg_internal Iclass_fp_lsiu_args[] = {
11095 - { { 64 /* frt */ }, 'o' },
11096 - { { 4 /* ars */ }, 'm' },
11097 - { { 61 /* cimm8x4 */ }, 'i' }
11100 -static xtensa_arg_internal Iclass_fp_lsiu_stateArgs[] = {
11101 - { { STATE_CPENABLE }, 'i' }
11104 -static xtensa_arg_internal Iclass_fp_lsx_args[] = {
11105 - { { 62 /* frr */ }, 'o' },
11106 - { { 4 /* ars */ }, 'i' },
11107 - { { 6 /* art */ }, 'i' }
11110 -static xtensa_arg_internal Iclass_fp_lsx_stateArgs[] = {
11111 - { { STATE_CPENABLE }, 'i' }
11114 -static xtensa_arg_internal Iclass_fp_lsxu_args[] = {
11115 - { { 62 /* frr */ }, 'o' },
11116 - { { 4 /* ars */ }, 'm' },
11117 - { { 6 /* art */ }, 'i' }
11120 -static xtensa_arg_internal Iclass_fp_lsxu_stateArgs[] = {
11121 - { { STATE_CPENABLE }, 'i' }
11124 -static xtensa_arg_internal Iclass_fp_ssi_args[] = {
11125 - { { 64 /* frt */ }, 'i' },
11126 - { { 4 /* ars */ }, 'i' },
11127 - { { 61 /* cimm8x4 */ }, 'i' }
11130 -static xtensa_arg_internal Iclass_fp_ssi_stateArgs[] = {
11131 - { { STATE_CPENABLE }, 'i' }
11134 -static xtensa_arg_internal Iclass_fp_ssiu_args[] = {
11135 - { { 64 /* frt */ }, 'i' },
11136 - { { 4 /* ars */ }, 'm' },
11137 - { { 61 /* cimm8x4 */ }, 'i' }
11140 -static xtensa_arg_internal Iclass_fp_ssiu_stateArgs[] = {
11141 - { { STATE_CPENABLE }, 'i' }
11144 -static xtensa_arg_internal Iclass_fp_ssx_args[] = {
11145 - { { 62 /* frr */ }, 'i' },
11146 - { { 4 /* ars */ }, 'i' },
11147 - { { 6 /* art */ }, 'i' }
11150 -static xtensa_arg_internal Iclass_fp_ssx_stateArgs[] = {
11151 - { { STATE_CPENABLE }, 'i' }
11154 -static xtensa_arg_internal Iclass_fp_ssxu_args[] = {
11155 - { { 62 /* frr */ }, 'i' },
11156 - { { 4 /* ars */ }, 'm' },
11157 - { { 6 /* art */ }, 'i' }
11160 -static xtensa_arg_internal Iclass_fp_ssxu_stateArgs[] = {
11161 - { { STATE_CPENABLE }, 'i' }
11164 -static xtensa_arg_internal Iclass_xt_iclass_wb18_0_args[] = {
11165 - { { 4 /* ars */ }, 'i' },
11166 - { { 60 /* xt_wbr18_label */ }, 'i' }
11169 -static xtensa_arg_internal Iclass_xt_iclass_wb18_1_args[] = {
11170 - { { 4 /* ars */ }, 'i' },
11171 - { { 17 /* b4const */ }, 'i' },
11172 - { { 60 /* xt_wbr18_label */ }, 'i' }
11175 -static xtensa_arg_internal Iclass_xt_iclass_wb18_2_args[] = {
11176 - { { 4 /* ars */ }, 'i' },
11177 - { { 18 /* b4constu */ }, 'i' },
11178 - { { 60 /* xt_wbr18_label */ }, 'i' }
11181 -static xtensa_arg_internal Iclass_xt_iclass_wb18_3_args[] = {
11182 - { { 4 /* ars */ }, 'i' },
11183 - { { 67 /* bbi */ }, 'i' },
11184 - { { 60 /* xt_wbr18_label */ }, 'i' }
11187 -static xtensa_arg_internal Iclass_xt_iclass_wb18_4_args[] = {
11188 - { { 4 /* ars */ }, 'i' },
11189 - { { 6 /* art */ }, 'i' },
11190 - { { 60 /* xt_wbr18_label */ }, 'i' }
11193 -static xtensa_iclass_internal iclasses[] = {
11194 - { 0, 0 /* xt_iclass_excw */,
11196 - { 0, 0 /* xt_iclass_rfe */,
11197 - 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
11198 - { 0, 0 /* xt_iclass_rfde */,
11199 - 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
11200 - { 0, 0 /* xt_iclass_syscall */,
11202 - { 0, 0 /* xt_iclass_simcall */,
11204 - { 2, Iclass_xt_iclass_call12_args,
11205 - 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
11206 - { 2, Iclass_xt_iclass_call8_args,
11207 - 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 },
11208 - { 2, Iclass_xt_iclass_call4_args,
11209 - 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 },
11210 - { 2, Iclass_xt_iclass_callx12_args,
11211 - 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 },
11212 - { 2, Iclass_xt_iclass_callx8_args,
11213 - 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 },
11214 - { 2, Iclass_xt_iclass_callx4_args,
11215 - 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 },
11216 - { 3, Iclass_xt_iclass_entry_args,
11217 - 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 },
11218 - { 2, Iclass_xt_iclass_movsp_args,
11219 - 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 },
11220 - { 1, Iclass_xt_iclass_rotw_args,
11221 - 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 },
11222 - { 1, Iclass_xt_iclass_retw_args,
11223 - 4, Iclass_xt_iclass_retw_stateArgs, 0, 0 },
11224 - { 0, 0 /* xt_iclass_rfwou */,
11225 - 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 },
11226 - { 3, Iclass_xt_iclass_l32e_args,
11227 - 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 },
11228 - { 3, Iclass_xt_iclass_s32e_args,
11229 - 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 },
11230 - { 1, Iclass_xt_iclass_rsr_windowbase_args,
11231 - 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 },
11232 - { 1, Iclass_xt_iclass_wsr_windowbase_args,
11233 - 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 },
11234 - { 1, Iclass_xt_iclass_xsr_windowbase_args,
11235 - 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 },
11236 - { 1, Iclass_xt_iclass_rsr_windowstart_args,
11237 - 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 },
11238 - { 1, Iclass_xt_iclass_wsr_windowstart_args,
11239 - 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 },
11240 - { 1, Iclass_xt_iclass_xsr_windowstart_args,
11241 - 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 },
11242 - { 3, Iclass_xt_iclass_add_n_args,
11244 - { 3, Iclass_xt_iclass_addi_n_args,
11246 - { 2, Iclass_xt_iclass_bz6_args,
11248 - { 0, 0 /* xt_iclass_ill_n */,
11250 - { 3, Iclass_xt_iclass_loadi4_args,
11252 - { 2, Iclass_xt_iclass_mov_n_args,
11254 - { 2, Iclass_xt_iclass_movi_n_args,
11256 - { 0, 0 /* xt_iclass_nopn */,
11258 - { 1, Iclass_xt_iclass_retn_args,
11260 - { 3, Iclass_xt_iclass_storei4_args,
11262 - { 1, Iclass_rur_threadptr_args,
11263 - 1, Iclass_rur_threadptr_stateArgs, 0, 0 },
11264 - { 1, Iclass_wur_threadptr_args,
11265 - 1, Iclass_wur_threadptr_stateArgs, 0, 0 },
11266 - { 3, Iclass_xt_iclass_addi_args,
11268 - { 3, Iclass_xt_iclass_addmi_args,
11270 - { 3, Iclass_xt_iclass_addsub_args,
11272 - { 3, Iclass_xt_iclass_bit_args,
11274 - { 3, Iclass_xt_iclass_bsi8_args,
11276 - { 3, Iclass_xt_iclass_bsi8b_args,
11278 - { 3, Iclass_xt_iclass_bsi8u_args,
11280 - { 3, Iclass_xt_iclass_bst8_args,
11282 - { 2, Iclass_xt_iclass_bsz12_args,
11284 - { 2, Iclass_xt_iclass_call0_args,
11286 - { 2, Iclass_xt_iclass_callx0_args,
11288 - { 4, Iclass_xt_iclass_exti_args,
11290 - { 0, 0 /* xt_iclass_ill */,
11292 - { 1, Iclass_xt_iclass_jump_args,
11294 - { 1, Iclass_xt_iclass_jumpx_args,
11296 - { 3, Iclass_xt_iclass_l16ui_args,
11298 - { 3, Iclass_xt_iclass_l16si_args,
11300 - { 3, Iclass_xt_iclass_l32i_args,
11302 - { 2, Iclass_xt_iclass_l32r_args,
11303 - 2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 },
11304 - { 3, Iclass_xt_iclass_l8i_args,
11306 - { 2, Iclass_xt_iclass_loop_args,
11307 - 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 },
11308 - { 2, Iclass_xt_iclass_loopz_args,
11309 - 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 },
11310 - { 2, Iclass_xt_iclass_movi_args,
11312 - { 3, Iclass_xt_iclass_movz_args,
11314 - { 2, Iclass_xt_iclass_neg_args,
11316 - { 0, 0 /* xt_iclass_nop */,
11318 - { 1, Iclass_xt_iclass_return_args,
11320 - { 3, Iclass_xt_iclass_s16i_args,
11322 - { 3, Iclass_xt_iclass_s32i_args,
11324 - { 3, Iclass_xt_iclass_s8i_args,
11326 - { 1, Iclass_xt_iclass_sar_args,
11327 - 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
11328 - { 1, Iclass_xt_iclass_sari_args,
11329 - 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
11330 - { 2, Iclass_xt_iclass_shifts_args,
11331 - 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
11332 - { 3, Iclass_xt_iclass_shiftst_args,
11333 - 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
11334 - { 2, Iclass_xt_iclass_shiftt_args,
11335 - 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
11336 - { 3, Iclass_xt_iclass_slli_args,
11338 - { 3, Iclass_xt_iclass_srai_args,
11340 - { 3, Iclass_xt_iclass_srli_args,
11342 - { 0, 0 /* xt_iclass_memw */,
11344 - { 0, 0 /* xt_iclass_extw */,
11346 - { 0, 0 /* xt_iclass_isync */,
11348 - { 0, 0 /* xt_iclass_sync */,
11349 - 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
11350 - { 2, Iclass_xt_iclass_rsil_args,
11351 - 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
11352 - { 1, Iclass_xt_iclass_rsr_lend_args,
11353 - 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 },
11354 - { 1, Iclass_xt_iclass_wsr_lend_args,
11355 - 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 },
11356 - { 1, Iclass_xt_iclass_xsr_lend_args,
11357 - 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 },
11358 - { 1, Iclass_xt_iclass_rsr_lcount_args,
11359 - 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 },
11360 - { 1, Iclass_xt_iclass_wsr_lcount_args,
11361 - 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 },
11362 - { 1, Iclass_xt_iclass_xsr_lcount_args,
11363 - 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 },
11364 - { 1, Iclass_xt_iclass_rsr_lbeg_args,
11365 - 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 },
11366 - { 1, Iclass_xt_iclass_wsr_lbeg_args,
11367 - 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 },
11368 - { 1, Iclass_xt_iclass_xsr_lbeg_args,
11369 - 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 },
11370 - { 1, Iclass_xt_iclass_rsr_sar_args,
11371 - 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
11372 - { 1, Iclass_xt_iclass_wsr_sar_args,
11373 - 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
11374 - { 1, Iclass_xt_iclass_xsr_sar_args,
11375 - 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
11376 - { 1, Iclass_xt_iclass_rsr_litbase_args,
11377 - 2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 },
11378 - { 1, Iclass_xt_iclass_wsr_litbase_args,
11379 - 2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 },
11380 - { 1, Iclass_xt_iclass_xsr_litbase_args,
11381 - 2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 },
11382 - { 1, Iclass_xt_iclass_rsr_176_args,
11383 - 2, Iclass_xt_iclass_rsr_176_stateArgs, 0, 0 },
11384 - { 1, Iclass_xt_iclass_rsr_208_args,
11385 - 2, Iclass_xt_iclass_rsr_208_stateArgs, 0, 0 },
11386 - { 1, Iclass_xt_iclass_rsr_ps_args,
11387 - 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
11388 - { 1, Iclass_xt_iclass_wsr_ps_args,
11389 - 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
11390 - { 1, Iclass_xt_iclass_xsr_ps_args,
11391 - 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
11392 - { 1, Iclass_xt_iclass_rsr_epc1_args,
11393 - 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
11394 - { 1, Iclass_xt_iclass_wsr_epc1_args,
11395 - 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
11396 - { 1, Iclass_xt_iclass_xsr_epc1_args,
11397 - 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
11398 - { 1, Iclass_xt_iclass_rsr_excsave1_args,
11399 - 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
11400 - { 1, Iclass_xt_iclass_wsr_excsave1_args,
11401 - 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
11402 - { 1, Iclass_xt_iclass_xsr_excsave1_args,
11403 - 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
11404 - { 1, Iclass_xt_iclass_rsr_epc2_args,
11405 - 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
11406 - { 1, Iclass_xt_iclass_wsr_epc2_args,
11407 - 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
11408 - { 1, Iclass_xt_iclass_xsr_epc2_args,
11409 - 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
11410 - { 1, Iclass_xt_iclass_rsr_excsave2_args,
11411 - 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
11412 - { 1, Iclass_xt_iclass_wsr_excsave2_args,
11413 - 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
11414 - { 1, Iclass_xt_iclass_xsr_excsave2_args,
11415 - 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
11416 - { 1, Iclass_xt_iclass_rsr_epc3_args,
11417 - 3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 },
11418 - { 1, Iclass_xt_iclass_wsr_epc3_args,
11419 - 3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 },
11420 - { 1, Iclass_xt_iclass_xsr_epc3_args,
11421 - 3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 },
11422 - { 1, Iclass_xt_iclass_rsr_excsave3_args,
11423 - 3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 },
11424 - { 1, Iclass_xt_iclass_wsr_excsave3_args,
11425 - 3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 },
11426 - { 1, Iclass_xt_iclass_xsr_excsave3_args,
11427 - 3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 },
11428 - { 1, Iclass_xt_iclass_rsr_epc4_args,
11429 - 3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 },
11430 - { 1, Iclass_xt_iclass_wsr_epc4_args,
11431 - 3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 },
11432 - { 1, Iclass_xt_iclass_xsr_epc4_args,
11433 - 3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 },
11434 - { 1, Iclass_xt_iclass_rsr_excsave4_args,
11435 - 3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 },
11436 - { 1, Iclass_xt_iclass_wsr_excsave4_args,
11437 - 3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 },
11438 - { 1, Iclass_xt_iclass_xsr_excsave4_args,
11439 - 3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 },
11440 - { 1, Iclass_xt_iclass_rsr_epc5_args,
11441 - 3, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 },
11442 - { 1, Iclass_xt_iclass_wsr_epc5_args,
11443 - 3, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 },
11444 - { 1, Iclass_xt_iclass_xsr_epc5_args,
11445 - 3, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 },
11446 - { 1, Iclass_xt_iclass_rsr_excsave5_args,
11447 - 3, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 },
11448 - { 1, Iclass_xt_iclass_wsr_excsave5_args,
11449 - 3, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 },
11450 - { 1, Iclass_xt_iclass_xsr_excsave5_args,
11451 - 3, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 },
11452 - { 1, Iclass_xt_iclass_rsr_epc6_args,
11453 - 3, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 },
11454 - { 1, Iclass_xt_iclass_wsr_epc6_args,
11455 - 3, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 },
11456 - { 1, Iclass_xt_iclass_xsr_epc6_args,
11457 - 3, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 },
11458 - { 1, Iclass_xt_iclass_rsr_excsave6_args,
11459 - 3, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 },
11460 - { 1, Iclass_xt_iclass_wsr_excsave6_args,
11461 - 3, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 },
11462 - { 1, Iclass_xt_iclass_xsr_excsave6_args,
11463 - 3, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 },
11464 - { 1, Iclass_xt_iclass_rsr_epc7_args,
11465 - 3, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 },
11466 - { 1, Iclass_xt_iclass_wsr_epc7_args,
11467 - 3, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 },
11468 - { 1, Iclass_xt_iclass_xsr_epc7_args,
11469 - 3, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 },
11470 - { 1, Iclass_xt_iclass_rsr_excsave7_args,
11471 - 3, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 },
11472 - { 1, Iclass_xt_iclass_wsr_excsave7_args,
11473 - 3, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 },
11474 - { 1, Iclass_xt_iclass_xsr_excsave7_args,
11475 - 3, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 },
11476 - { 1, Iclass_xt_iclass_rsr_eps2_args,
11477 - 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
11478 - { 1, Iclass_xt_iclass_wsr_eps2_args,
11479 - 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
11480 - { 1, Iclass_xt_iclass_xsr_eps2_args,
11481 - 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
11482 - { 1, Iclass_xt_iclass_rsr_eps3_args,
11483 - 3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 },
11484 - { 1, Iclass_xt_iclass_wsr_eps3_args,
11485 - 3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 },
11486 - { 1, Iclass_xt_iclass_xsr_eps3_args,
11487 - 3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 },
11488 - { 1, Iclass_xt_iclass_rsr_eps4_args,
11489 - 3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 },
11490 - { 1, Iclass_xt_iclass_wsr_eps4_args,
11491 - 3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 },
11492 - { 1, Iclass_xt_iclass_xsr_eps4_args,
11493 - 3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 },
11494 - { 1, Iclass_xt_iclass_rsr_eps5_args,
11495 - 3, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 },
11496 - { 1, Iclass_xt_iclass_wsr_eps5_args,
11497 - 3, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 },
11498 - { 1, Iclass_xt_iclass_xsr_eps5_args,
11499 - 3, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 },
11500 - { 1, Iclass_xt_iclass_rsr_eps6_args,
11501 - 3, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 },
11502 - { 1, Iclass_xt_iclass_wsr_eps6_args,
11503 - 3, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 },
11504 - { 1, Iclass_xt_iclass_xsr_eps6_args,
11505 - 3, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 },
11506 - { 1, Iclass_xt_iclass_rsr_eps7_args,
11507 - 3, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 },
11508 - { 1, Iclass_xt_iclass_wsr_eps7_args,
11509 - 3, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 },
11510 - { 1, Iclass_xt_iclass_xsr_eps7_args,
11511 - 3, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 },
11512 - { 1, Iclass_xt_iclass_rsr_excvaddr_args,
11513 - 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
11514 - { 1, Iclass_xt_iclass_wsr_excvaddr_args,
11515 - 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
11516 - { 1, Iclass_xt_iclass_xsr_excvaddr_args,
11517 - 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
11518 - { 1, Iclass_xt_iclass_rsr_depc_args,
11519 - 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
11520 - { 1, Iclass_xt_iclass_wsr_depc_args,
11521 - 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
11522 - { 1, Iclass_xt_iclass_xsr_depc_args,
11523 - 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
11524 - { 1, Iclass_xt_iclass_rsr_exccause_args,
11525 - 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
11526 - { 1, Iclass_xt_iclass_wsr_exccause_args,
11527 - 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
11528 - { 1, Iclass_xt_iclass_xsr_exccause_args,
11529 - 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
11530 - { 1, Iclass_xt_iclass_rsr_misc0_args,
11531 - 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 },
11532 - { 1, Iclass_xt_iclass_wsr_misc0_args,
11533 - 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 },
11534 - { 1, Iclass_xt_iclass_xsr_misc0_args,
11535 - 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 },
11536 - { 1, Iclass_xt_iclass_rsr_misc1_args,
11537 - 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 },
11538 - { 1, Iclass_xt_iclass_wsr_misc1_args,
11539 - 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 },
11540 - { 1, Iclass_xt_iclass_xsr_misc1_args,
11541 - 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 },
11542 - { 1, Iclass_xt_iclass_rsr_misc2_args,
11543 - 3, Iclass_xt_iclass_rsr_misc2_stateArgs, 0, 0 },
11544 - { 1, Iclass_xt_iclass_wsr_misc2_args,
11545 - 3, Iclass_xt_iclass_wsr_misc2_stateArgs, 0, 0 },
11546 - { 1, Iclass_xt_iclass_xsr_misc2_args,
11547 - 3, Iclass_xt_iclass_xsr_misc2_stateArgs, 0, 0 },
11548 - { 1, Iclass_xt_iclass_rsr_misc3_args,
11549 - 3, Iclass_xt_iclass_rsr_misc3_stateArgs, 0, 0 },
11550 - { 1, Iclass_xt_iclass_wsr_misc3_args,
11551 - 3, Iclass_xt_iclass_wsr_misc3_stateArgs, 0, 0 },
11552 - { 1, Iclass_xt_iclass_xsr_misc3_args,
11553 - 3, Iclass_xt_iclass_xsr_misc3_stateArgs, 0, 0 },
11554 - { 1, Iclass_xt_iclass_rsr_prid_args,
11555 - 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 },
11556 - { 1, Iclass_xt_iclass_rsr_vecbase_args,
11557 - 3, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 },
11558 - { 1, Iclass_xt_iclass_wsr_vecbase_args,
11559 - 3, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 },
11560 - { 1, Iclass_xt_iclass_xsr_vecbase_args,
11561 - 3, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 },
11562 - { 2, Iclass_xt_iclass_mac16_aa_args,
11563 - 1, Iclass_xt_iclass_mac16_aa_stateArgs, 0, 0 },
11564 - { 2, Iclass_xt_iclass_mac16_ad_args,
11565 - 1, Iclass_xt_iclass_mac16_ad_stateArgs, 0, 0 },
11566 - { 2, Iclass_xt_iclass_mac16_da_args,
11567 - 1, Iclass_xt_iclass_mac16_da_stateArgs, 0, 0 },
11568 - { 2, Iclass_xt_iclass_mac16_dd_args,
11569 - 1, Iclass_xt_iclass_mac16_dd_stateArgs, 0, 0 },
11570 - { 2, Iclass_xt_iclass_mac16a_aa_args,
11571 - 1, Iclass_xt_iclass_mac16a_aa_stateArgs, 0, 0 },
11572 - { 2, Iclass_xt_iclass_mac16a_ad_args,
11573 - 1, Iclass_xt_iclass_mac16a_ad_stateArgs, 0, 0 },
11574 - { 2, Iclass_xt_iclass_mac16a_da_args,
11575 - 1, Iclass_xt_iclass_mac16a_da_stateArgs, 0, 0 },
11576 - { 2, Iclass_xt_iclass_mac16a_dd_args,
11577 - 1, Iclass_xt_iclass_mac16a_dd_stateArgs, 0, 0 },
11578 - { 4, Iclass_xt_iclass_mac16al_da_args,
11579 - 1, Iclass_xt_iclass_mac16al_da_stateArgs, 0, 0 },
11580 - { 4, Iclass_xt_iclass_mac16al_dd_args,
11581 - 1, Iclass_xt_iclass_mac16al_dd_stateArgs, 0, 0 },
11582 - { 2, Iclass_xt_iclass_mac16_l_args,
11584 - { 3, Iclass_xt_iclass_mul16_args,
11586 - { 2, Iclass_xt_iclass_rsr_m0_args,
11588 - { 2, Iclass_xt_iclass_wsr_m0_args,
11590 - { 2, Iclass_xt_iclass_xsr_m0_args,
11592 - { 2, Iclass_xt_iclass_rsr_m1_args,
11594 - { 2, Iclass_xt_iclass_wsr_m1_args,
11596 - { 2, Iclass_xt_iclass_xsr_m1_args,
11598 - { 2, Iclass_xt_iclass_rsr_m2_args,
11600 - { 2, Iclass_xt_iclass_wsr_m2_args,
11602 - { 2, Iclass_xt_iclass_xsr_m2_args,
11604 - { 2, Iclass_xt_iclass_rsr_m3_args,
11606 - { 2, Iclass_xt_iclass_wsr_m3_args,
11608 - { 2, Iclass_xt_iclass_xsr_m3_args,
11610 - { 1, Iclass_xt_iclass_rsr_acclo_args,
11611 - 1, Iclass_xt_iclass_rsr_acclo_stateArgs, 0, 0 },
11612 - { 1, Iclass_xt_iclass_wsr_acclo_args,
11613 - 1, Iclass_xt_iclass_wsr_acclo_stateArgs, 0, 0 },
11614 - { 1, Iclass_xt_iclass_xsr_acclo_args,
11615 - 1, Iclass_xt_iclass_xsr_acclo_stateArgs, 0, 0 },
11616 - { 1, Iclass_xt_iclass_rsr_acchi_args,
11617 - 1, Iclass_xt_iclass_rsr_acchi_stateArgs, 0, 0 },
11618 - { 1, Iclass_xt_iclass_wsr_acchi_args,
11619 - 1, Iclass_xt_iclass_wsr_acchi_stateArgs, 0, 0 },
11620 - { 1, Iclass_xt_iclass_xsr_acchi_args,
11621 - 1, Iclass_xt_iclass_xsr_acchi_stateArgs, 0, 0 },
11622 - { 1, Iclass_xt_iclass_rfi_args,
11623 - 21, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
11624 - { 1, Iclass_xt_iclass_wait_args,
11625 - 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
11626 - { 1, Iclass_xt_iclass_rsr_interrupt_args,
11627 - 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
11628 - { 1, Iclass_xt_iclass_wsr_intset_args,
11629 - 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
11630 - { 1, Iclass_xt_iclass_wsr_intclear_args,
11631 - 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
11632 - { 1, Iclass_xt_iclass_rsr_intenable_args,
11633 - 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
11634 - { 1, Iclass_xt_iclass_wsr_intenable_args,
11635 - 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
11636 - { 1, Iclass_xt_iclass_xsr_intenable_args,
11637 - 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
11638 - { 2, Iclass_xt_iclass_break_args,
11639 - 2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
11640 - { 1, Iclass_xt_iclass_break_n_args,
11641 - 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
11642 - { 1, Iclass_xt_iclass_rsr_dbreaka0_args,
11643 - 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 },
11644 - { 1, Iclass_xt_iclass_wsr_dbreaka0_args,
11645 - 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 },
11646 - { 1, Iclass_xt_iclass_xsr_dbreaka0_args,
11647 - 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 },
11648 - { 1, Iclass_xt_iclass_rsr_dbreakc0_args,
11649 - 3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 },
11650 - { 1, Iclass_xt_iclass_wsr_dbreakc0_args,
11651 - 4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 },
11652 - { 1, Iclass_xt_iclass_xsr_dbreakc0_args,
11653 - 4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 },
11654 - { 1, Iclass_xt_iclass_rsr_dbreaka1_args,
11655 - 3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 },
11656 - { 1, Iclass_xt_iclass_wsr_dbreaka1_args,
11657 - 4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 },
11658 - { 1, Iclass_xt_iclass_xsr_dbreaka1_args,
11659 - 4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 },
11660 - { 1, Iclass_xt_iclass_rsr_dbreakc1_args,
11661 - 3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 },
11662 - { 1, Iclass_xt_iclass_wsr_dbreakc1_args,
11663 - 4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 },
11664 - { 1, Iclass_xt_iclass_xsr_dbreakc1_args,
11665 - 4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 },
11666 - { 1, Iclass_xt_iclass_rsr_ibreaka0_args,
11667 - 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 },
11668 - { 1, Iclass_xt_iclass_wsr_ibreaka0_args,
11669 - 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 },
11670 - { 1, Iclass_xt_iclass_xsr_ibreaka0_args,
11671 - 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 },
11672 - { 1, Iclass_xt_iclass_rsr_ibreaka1_args,
11673 - 3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 },
11674 - { 1, Iclass_xt_iclass_wsr_ibreaka1_args,
11675 - 3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 },
11676 - { 1, Iclass_xt_iclass_xsr_ibreaka1_args,
11677 - 3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 },
11678 - { 1, Iclass_xt_iclass_rsr_ibreakenable_args,
11679 - 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 },
11680 - { 1, Iclass_xt_iclass_wsr_ibreakenable_args,
11681 - 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 },
11682 - { 1, Iclass_xt_iclass_xsr_ibreakenable_args,
11683 - 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 },
11684 - { 1, Iclass_xt_iclass_rsr_debugcause_args,
11685 - 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
11686 - { 1, Iclass_xt_iclass_wsr_debugcause_args,
11687 - 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
11688 - { 1, Iclass_xt_iclass_xsr_debugcause_args,
11689 - 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
11690 - { 1, Iclass_xt_iclass_rsr_icount_args,
11691 - 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
11692 - { 1, Iclass_xt_iclass_wsr_icount_args,
11693 - 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
11694 - { 1, Iclass_xt_iclass_xsr_icount_args,
11695 - 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
11696 - { 1, Iclass_xt_iclass_rsr_icountlevel_args,
11697 - 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
11698 - { 1, Iclass_xt_iclass_wsr_icountlevel_args,
11699 - 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
11700 - { 1, Iclass_xt_iclass_xsr_icountlevel_args,
11701 - 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
11702 - { 1, Iclass_xt_iclass_rsr_ddr_args,
11703 - 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
11704 - { 1, Iclass_xt_iclass_wsr_ddr_args,
11705 - 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
11706 - { 1, Iclass_xt_iclass_xsr_ddr_args,
11707 - 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
11708 - { 1, Iclass_xt_iclass_rfdo_args,
11709 - 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
11710 - { 0, 0 /* xt_iclass_rfdd */,
11711 - 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
11712 - { 1, Iclass_xt_iclass_wsr_mmid_args,
11713 - 3, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 },
11714 - { 3, Iclass_xt_iclass_bbool1_args,
11716 - { 2, Iclass_xt_iclass_bbool4_args,
11718 - { 2, Iclass_xt_iclass_bbool8_args,
11720 - { 2, Iclass_xt_iclass_bbranch_args,
11722 - { 3, Iclass_xt_iclass_bmove_args,
11724 - { 2, Iclass_xt_iclass_RSR_BR_args,
11726 - { 2, Iclass_xt_iclass_WSR_BR_args,
11728 - { 2, Iclass_xt_iclass_XSR_BR_args,
11730 - { 1, Iclass_xt_iclass_rsr_ccount_args,
11731 - 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
11732 - { 1, Iclass_xt_iclass_wsr_ccount_args,
11733 - 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
11734 - { 1, Iclass_xt_iclass_xsr_ccount_args,
11735 - 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
11736 - { 1, Iclass_xt_iclass_rsr_ccompare0_args,
11737 - 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
11738 - { 1, Iclass_xt_iclass_wsr_ccompare0_args,
11739 - 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
11740 - { 1, Iclass_xt_iclass_xsr_ccompare0_args,
11741 - 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
11742 - { 1, Iclass_xt_iclass_rsr_ccompare1_args,
11743 - 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 },
11744 - { 1, Iclass_xt_iclass_wsr_ccompare1_args,
11745 - 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 },
11746 - { 1, Iclass_xt_iclass_xsr_ccompare1_args,
11747 - 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 },
11748 - { 1, Iclass_xt_iclass_rsr_ccompare2_args,
11749 - 3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 },
11750 - { 1, Iclass_xt_iclass_wsr_ccompare2_args,
11751 - 4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 },
11752 - { 1, Iclass_xt_iclass_xsr_ccompare2_args,
11753 - 4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 },
11754 - { 2, Iclass_xt_iclass_icache_args,
11756 - { 2, Iclass_xt_iclass_icache_lock_args,
11757 - 2, Iclass_xt_iclass_icache_lock_stateArgs, 0, 0 },
11758 - { 2, Iclass_xt_iclass_icache_inv_args,
11759 - 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 },
11760 - { 2, Iclass_xt_iclass_licx_args,
11761 - 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 },
11762 - { 2, Iclass_xt_iclass_sicx_args,
11763 - 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 },
11764 - { 2, Iclass_xt_iclass_dcache_args,
11766 - { 2, Iclass_xt_iclass_dcache_ind_args,
11767 - 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 },
11768 - { 2, Iclass_xt_iclass_dcache_inv_args,
11769 - 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 },
11770 - { 2, Iclass_xt_iclass_dpf_args,
11772 - { 2, Iclass_xt_iclass_dcache_lock_args,
11773 - 2, Iclass_xt_iclass_dcache_lock_stateArgs, 0, 0 },
11774 - { 2, Iclass_xt_iclass_sdct_args,
11775 - 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 },
11776 - { 2, Iclass_xt_iclass_ldct_args,
11777 - 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 },
11778 - { 1, Iclass_xt_iclass_wsr_ptevaddr_args,
11779 - 4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 },
11780 - { 1, Iclass_xt_iclass_rsr_ptevaddr_args,
11781 - 4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 },
11782 - { 1, Iclass_xt_iclass_xsr_ptevaddr_args,
11783 - 5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 },
11784 - { 1, Iclass_xt_iclass_rsr_rasid_args,
11785 - 5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 },
11786 - { 1, Iclass_xt_iclass_wsr_rasid_args,
11787 - 6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 },
11788 - { 1, Iclass_xt_iclass_xsr_rasid_args,
11789 - 6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 },
11790 - { 1, Iclass_xt_iclass_rsr_itlbcfg_args,
11791 - 3, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 },
11792 - { 1, Iclass_xt_iclass_wsr_itlbcfg_args,
11793 - 4, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 },
11794 - { 1, Iclass_xt_iclass_xsr_itlbcfg_args,
11795 - 4, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 },
11796 - { 1, Iclass_xt_iclass_rsr_dtlbcfg_args,
11797 - 3, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 },
11798 - { 1, Iclass_xt_iclass_wsr_dtlbcfg_args,
11799 - 4, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 },
11800 - { 1, Iclass_xt_iclass_xsr_dtlbcfg_args,
11801 - 4, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 },
11802 - { 1, Iclass_xt_iclass_idtlb_args,
11803 - 3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
11804 - { 2, Iclass_xt_iclass_rdtlb_args,
11805 - 2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 },
11806 - { 2, Iclass_xt_iclass_wdtlb_args,
11807 - 3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
11808 - { 1, Iclass_xt_iclass_iitlb_args,
11809 - 2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 },
11810 - { 2, Iclass_xt_iclass_ritlb_args,
11811 - 2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 },
11812 - { 2, Iclass_xt_iclass_witlb_args,
11813 - 2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 },
11814 - { 0, 0 /* xt_iclass_ldpte */,
11815 - 2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 },
11816 - { 0, 0 /* xt_iclass_hwwitlba */,
11817 - 1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 },
11818 - { 0, 0 /* xt_iclass_hwwdtlba */,
11819 - 1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 },
11820 - { 1, Iclass_xt_iclass_rsr_cpenable_args,
11821 - 3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 },
11822 - { 1, Iclass_xt_iclass_wsr_cpenable_args,
11823 - 3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 },
11824 - { 1, Iclass_xt_iclass_xsr_cpenable_args,
11825 - 3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 },
11826 - { 3, Iclass_xt_iclass_clamp_args,
11828 - { 3, Iclass_xt_iclass_minmax_args,
11830 - { 2, Iclass_xt_iclass_nsa_args,
11832 - { 3, Iclass_xt_iclass_sx_args,
11834 - { 3, Iclass_xt_iclass_l32ai_args,
11836 - { 3, Iclass_xt_iclass_s32ri_args,
11838 - { 3, Iclass_xt_iclass_s32c1i_args,
11839 - 2, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 },
11840 - { 1, Iclass_xt_iclass_rsr_scompare1_args,
11841 - 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 },
11842 - { 1, Iclass_xt_iclass_wsr_scompare1_args,
11843 - 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 },
11844 - { 1, Iclass_xt_iclass_xsr_scompare1_args,
11845 - 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 },
11846 - { 3, Iclass_xt_iclass_div_args,
11848 - { 3, Iclass_xt_mul32_args,
11850 - { 1, Iclass_rur_fcr_args,
11851 - 9, Iclass_rur_fcr_stateArgs, 0, 0 },
11852 - { 1, Iclass_wur_fcr_args,
11853 - 9, Iclass_wur_fcr_stateArgs, 0, 0 },
11854 - { 1, Iclass_rur_fsr_args,
11855 - 8, Iclass_rur_fsr_stateArgs, 0, 0 },
11856 - { 1, Iclass_wur_fsr_args,
11857 - 8, Iclass_wur_fsr_stateArgs, 0, 0 },
11858 - { 3, Iclass_fp_args,
11859 - 2, Iclass_fp_stateArgs, 0, 0 },
11860 - { 3, Iclass_fp_mac_args,
11861 - 2, Iclass_fp_mac_stateArgs, 0, 0 },
11862 - { 3, Iclass_fp_cmov_args,
11863 - 1, Iclass_fp_cmov_stateArgs, 0, 0 },
11864 - { 3, Iclass_fp_mov_args,
11865 - 1, Iclass_fp_mov_stateArgs, 0, 0 },
11866 - { 2, Iclass_fp_mov2_args,
11867 - 1, Iclass_fp_mov2_stateArgs, 0, 0 },
11868 - { 3, Iclass_fp_cmp_args,
11869 - 1, Iclass_fp_cmp_stateArgs, 0, 0 },
11870 - { 3, Iclass_fp_float_args,
11871 - 2, Iclass_fp_float_stateArgs, 0, 0 },
11872 - { 3, Iclass_fp_int_args,
11873 - 1, Iclass_fp_int_stateArgs, 0, 0 },
11874 - { 2, Iclass_fp_rfr_args,
11875 - 1, Iclass_fp_rfr_stateArgs, 0, 0 },
11876 - { 2, Iclass_fp_wfr_args,
11877 - 1, Iclass_fp_wfr_stateArgs, 0, 0 },
11878 - { 3, Iclass_fp_lsi_args,
11879 - 1, Iclass_fp_lsi_stateArgs, 0, 0 },
11880 - { 3, Iclass_fp_lsiu_args,
11881 - 1, Iclass_fp_lsiu_stateArgs, 0, 0 },
11882 - { 3, Iclass_fp_lsx_args,
11883 - 1, Iclass_fp_lsx_stateArgs, 0, 0 },
11884 - { 3, Iclass_fp_lsxu_args,
11885 - 1, Iclass_fp_lsxu_stateArgs, 0, 0 },
11886 - { 3, Iclass_fp_ssi_args,
11887 - 1, Iclass_fp_ssi_stateArgs, 0, 0 },
11888 - { 3, Iclass_fp_ssiu_args,
11889 - 1, Iclass_fp_ssiu_stateArgs, 0, 0 },
11890 - { 3, Iclass_fp_ssx_args,
11891 - 1, Iclass_fp_ssx_stateArgs, 0, 0 },
11892 - { 3, Iclass_fp_ssxu_args,
11893 - 1, Iclass_fp_ssxu_stateArgs, 0, 0 },
11894 - { 2, Iclass_xt_iclass_wb18_0_args,
11896 - { 3, Iclass_xt_iclass_wb18_1_args,
11898 - { 3, Iclass_xt_iclass_wb18_2_args,
11900 - { 3, Iclass_xt_iclass_wb18_3_args,
11902 - { 3, Iclass_xt_iclass_wb18_4_args,
11907 -/* Opcode encodings. */
11910 -Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf)
11912 - slotbuf[0] = 0x2080;
11916 -Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf)
11918 - slotbuf[0] = 0x3000;
11922 -Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf)
11924 - slotbuf[0] = 0x3200;
11928 -Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf)
11930 - slotbuf[0] = 0x5000;
11934 -Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf)
11936 - slotbuf[0] = 0x5100;
11940 -Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf)
11942 - slotbuf[0] = 0x35;
11946 -Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf)
11948 - slotbuf[0] = 0x25;
11952 -Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf)
11954 - slotbuf[0] = 0x15;
11958 -Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf)
11960 - slotbuf[0] = 0xf0;
11964 -Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
11966 - slotbuf[0] = 0xe0;
11970 -Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
11972 - slotbuf[0] = 0xd0;
11976 -Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf)
11978 - slotbuf[0] = 0x36;
11982 -Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf)
11984 - slotbuf[0] = 0x1000;
11988 -Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf)
11990 - slotbuf[0] = 0x408000;
11994 -Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf)
11996 - slotbuf[0] = 0x90;
12000 -Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
12002 - slotbuf[0] = 0xf01d;
12006 -Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
12008 - slotbuf[0] = 0x3400;
12012 -Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf)
12014 - slotbuf[0] = 0x3500;
12018 -Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
12020 - slotbuf[0] = 0x90000;
12024 -Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
12026 - slotbuf[0] = 0x490000;
12030 -Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
12032 - slotbuf[0] = 0x34800;
12036 -Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
12038 - slotbuf[0] = 0x134800;
12042 -Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
12044 - slotbuf[0] = 0x614800;
12048 -Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
12050 - slotbuf[0] = 0x34900;
12054 -Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
12056 - slotbuf[0] = 0x134900;
12060 -Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
12062 - slotbuf[0] = 0x614900;
12066 -Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
12068 - slotbuf[0] = 0xa;
12072 -Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
12074 - slotbuf[0] = 0xb;
12078 -Opcode_addi_n_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
12080 - slotbuf[0] = 0x3000;
12084 -Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
12086 - slotbuf[0] = 0x8c;
12090 -Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
12092 - slotbuf[0] = 0xcc;
12096 -Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
12098 - slotbuf[0] = 0xf06d;
12102 -Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
12104 - slotbuf[0] = 0x8;
12108 -Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
12110 - slotbuf[0] = 0xd;
12114 -Opcode_mov_n_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12116 - slotbuf[0] = 0x6000;
12120 -Opcode_mov_n_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12122 - slotbuf[0] = 0xa3000;
12126 -Opcode_mov_n_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
12128 - slotbuf[0] = 0xc080;
12132 -Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
12134 - slotbuf[0] = 0xc;
12138 -Opcode_movi_n_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
12140 - slotbuf[0] = 0xc000;
12144 -Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
12146 - slotbuf[0] = 0xf03d;
12150 -Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
12152 - slotbuf[0] = 0xf00d;
12156 -Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
12158 - slotbuf[0] = 0x9;
12162 -Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
12164 - slotbuf[0] = 0xe30e70;
12168 -Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
12170 - slotbuf[0] = 0xf3e700;
12174 -Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf)
12176 - slotbuf[0] = 0xc002;
12180 -Opcode_addi_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12182 - slotbuf[0] = 0x60000;
12186 -Opcode_addi_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12188 - slotbuf[0] = 0x200c00;
12192 -Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf)
12194 - slotbuf[0] = 0xd002;
12198 -Opcode_addmi_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12200 - slotbuf[0] = 0x70000;
12204 -Opcode_addmi_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12206 - slotbuf[0] = 0x200d00;
12210 -Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf)
12212 - slotbuf[0] = 0x800000;
12216 -Opcode_add_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12218 - slotbuf[0] = 0x92000;
12222 -Opcode_add_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
12224 - slotbuf[0] = 0x2000;
12228 -Opcode_add_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12230 - slotbuf[0] = 0x80000;
12234 -Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf)
12236 - slotbuf[0] = 0xc00000;
12240 -Opcode_sub_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12242 - slotbuf[0] = 0xa8000;
12246 -Opcode_sub_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
12248 - slotbuf[0] = 0xa000;
12252 -Opcode_sub_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12254 - slotbuf[0] = 0xc0000;
12258 -Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
12260 - slotbuf[0] = 0x900000;
12264 -Opcode_addx2_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12266 - slotbuf[0] = 0x94000;
12270 -Opcode_addx2_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
12272 - slotbuf[0] = 0x4000;
12276 -Opcode_addx2_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12278 - slotbuf[0] = 0x90000;
12282 -Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
12284 - slotbuf[0] = 0xa00000;
12288 -Opcode_addx4_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12290 - slotbuf[0] = 0x98000;
12294 -Opcode_addx4_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
12296 - slotbuf[0] = 0x5000;
12300 -Opcode_addx4_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12302 - slotbuf[0] = 0xa0000;
12306 -Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
12308 - slotbuf[0] = 0xb00000;
12312 -Opcode_addx8_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12314 - slotbuf[0] = 0x93000;
12318 -Opcode_addx8_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12320 - slotbuf[0] = 0xb0000;
12324 -Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
12326 - slotbuf[0] = 0xd00000;
12330 -Opcode_subx2_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12332 - slotbuf[0] = 0xd0000;
12336 -Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
12338 - slotbuf[0] = 0xe00000;
12342 -Opcode_subx4_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12344 - slotbuf[0] = 0xe0000;
12348 -Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
12350 - slotbuf[0] = 0xf00000;
12354 -Opcode_subx8_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12356 - slotbuf[0] = 0xf0000;
12360 -Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf)
12362 - slotbuf[0] = 0x100000;
12366 -Opcode_and_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12368 - slotbuf[0] = 0x95000;
12372 -Opcode_and_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
12374 - slotbuf[0] = 0x6000;
12378 -Opcode_and_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12380 - slotbuf[0] = 0x10000;
12384 -Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf)
12386 - slotbuf[0] = 0x200000;
12390 -Opcode_or_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12392 - slotbuf[0] = 0x9e000;
12396 -Opcode_or_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
12398 - slotbuf[0] = 0x7000;
12402 -Opcode_or_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12404 - slotbuf[0] = 0x20000;
12408 -Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf)
12410 - slotbuf[0] = 0x300000;
12414 -Opcode_xor_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12416 - slotbuf[0] = 0xb0000;
12420 -Opcode_xor_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
12422 - slotbuf[0] = 0xb000;
12426 -Opcode_xor_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12428 - slotbuf[0] = 0x30000;
12432 -Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf)
12434 - slotbuf[0] = 0x26;
12438 -Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf)
12440 - slotbuf[0] = 0x66;
12444 -Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf)
12446 - slotbuf[0] = 0xe6;
12450 -Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf)
12452 - slotbuf[0] = 0xa6;
12456 -Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf)
12458 - slotbuf[0] = 0x6007;
12462 -Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
12464 - slotbuf[0] = 0xe007;
12468 -Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf)
12470 - slotbuf[0] = 0xf6;
12474 -Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf)
12476 - slotbuf[0] = 0xb6;
12480 -Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf)
12482 - slotbuf[0] = 0x1007;
12486 -Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf)
12488 - slotbuf[0] = 0x9007;
12492 -Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf)
12494 - slotbuf[0] = 0xa007;
12498 -Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf)
12500 - slotbuf[0] = 0x2007;
12504 -Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf)
12506 - slotbuf[0] = 0xb007;
12510 -Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
12512 - slotbuf[0] = 0x3007;
12516 -Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf)
12518 - slotbuf[0] = 0x8007;
12522 -Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf)
12524 - slotbuf[0] = 0x7;
12528 -Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf)
12530 - slotbuf[0] = 0x4007;
12534 -Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf)
12536 - slotbuf[0] = 0xc007;
12540 -Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
12542 - slotbuf[0] = 0x5007;
12546 -Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf)
12548 - slotbuf[0] = 0xd007;
12552 -Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
12554 - slotbuf[0] = 0x16;
12558 -Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
12560 - slotbuf[0] = 0x56;
12564 -Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
12566 - slotbuf[0] = 0xd6;
12570 -Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
12572 - slotbuf[0] = 0x96;
12576 -Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf)
12578 - slotbuf[0] = 0x5;
12582 -Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf)
12584 - slotbuf[0] = 0xc0;
12588 -Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf)
12590 - slotbuf[0] = 0x40000;
12594 -Opcode_extui_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12596 - slotbuf[0] = 0x40000;
12600 -Opcode_extui_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12602 - slotbuf[0] = 0x4000;
12606 -Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf)
12612 -Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf)
12614 - slotbuf[0] = 0x6;
12618 -Opcode_j_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12620 - slotbuf[0] = 0xc0000;
12624 -Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf)
12626 - slotbuf[0] = 0xa0;
12630 -Opcode_jx_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12632 - slotbuf[0] = 0xa3010;
12636 -Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
12638 - slotbuf[0] = 0x1002;
12642 -Opcode_l16ui_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12644 - slotbuf[0] = 0x200100;
12648 -Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf)
12650 - slotbuf[0] = 0x9002;
12654 -Opcode_l16si_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12656 - slotbuf[0] = 0x200900;
12660 -Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
12662 - slotbuf[0] = 0x2002;
12666 -Opcode_l32i_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12668 - slotbuf[0] = 0x200200;
12672 -Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf)
12674 - slotbuf[0] = 0x1;
12678 -Opcode_l32r_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12680 - slotbuf[0] = 0x100000;
12684 -Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
12686 - slotbuf[0] = 0x2;
12690 -Opcode_l8ui_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12692 - slotbuf[0] = 0x200000;
12696 -Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf)
12698 - slotbuf[0] = 0x8076;
12702 -Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
12704 - slotbuf[0] = 0x9076;
12708 -Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf)
12710 - slotbuf[0] = 0xa076;
12714 -Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf)
12716 - slotbuf[0] = 0xa002;
12720 -Opcode_movi_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12722 - slotbuf[0] = 0x80000;
12726 -Opcode_movi_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12728 - slotbuf[0] = 0x200a00;
12732 -Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
12734 - slotbuf[0] = 0x830000;
12738 -Opcode_moveqz_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12740 - slotbuf[0] = 0x96000;
12744 -Opcode_moveqz_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12746 - slotbuf[0] = 0x83000;
12750 -Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
12752 - slotbuf[0] = 0x930000;
12756 -Opcode_movnez_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12758 - slotbuf[0] = 0x9a000;
12762 -Opcode_movnez_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12764 - slotbuf[0] = 0x93000;
12768 -Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
12770 - slotbuf[0] = 0xa30000;
12774 -Opcode_movltz_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12776 - slotbuf[0] = 0x99000;
12780 -Opcode_movltz_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12782 - slotbuf[0] = 0xa3000;
12786 -Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
12788 - slotbuf[0] = 0xb30000;
12792 -Opcode_movgez_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12794 - slotbuf[0] = 0x97000;
12798 -Opcode_movgez_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12800 - slotbuf[0] = 0xb3000;
12804 -Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf)
12806 - slotbuf[0] = 0x600000;
12810 -Opcode_neg_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12812 - slotbuf[0] = 0xa5000;
12816 -Opcode_neg_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
12818 - slotbuf[0] = 0xd100;
12822 -Opcode_neg_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12824 - slotbuf[0] = 0x60000;
12828 -Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf)
12830 - slotbuf[0] = 0x600100;
12834 -Opcode_abs_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
12836 - slotbuf[0] = 0xd000;
12840 -Opcode_abs_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12842 - slotbuf[0] = 0x60010;
12846 -Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf)
12848 - slotbuf[0] = 0x20f0;
12852 -Opcode_nop_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12854 - slotbuf[0] = 0xa3040;
12858 -Opcode_nop_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
12860 - slotbuf[0] = 0xc090;
12864 -Opcode_nop_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
12866 - slotbuf[0] = 0xc8000000;
12871 -Opcode_nop_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12873 - slotbuf[0] = 0x20f;
12877 -Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf)
12879 - slotbuf[0] = 0x80;
12883 -Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf)
12885 - slotbuf[0] = 0x5002;
12889 -Opcode_s16i_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12891 - slotbuf[0] = 0x200500;
12895 -Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
12897 - slotbuf[0] = 0x6002;
12901 -Opcode_s32i_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12903 - slotbuf[0] = 0x200600;
12907 -Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf)
12909 - slotbuf[0] = 0x4002;
12913 -Opcode_s8i_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12915 - slotbuf[0] = 0x200400;
12919 -Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf)
12921 - slotbuf[0] = 0x400000;
12925 -Opcode_ssr_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12927 - slotbuf[0] = 0x40000;
12931 -Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf)
12933 - slotbuf[0] = 0x401000;
12937 -Opcode_ssl_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12939 - slotbuf[0] = 0xa3020;
12943 -Opcode_ssl_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12945 - slotbuf[0] = 0x40100;
12949 -Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf)
12951 - slotbuf[0] = 0x402000;
12955 -Opcode_ssa8l_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12957 - slotbuf[0] = 0x40200;
12961 -Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf)
12963 - slotbuf[0] = 0x403000;
12967 -Opcode_ssa8b_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12969 - slotbuf[0] = 0x40300;
12973 -Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf)
12975 - slotbuf[0] = 0x404000;
12979 -Opcode_ssai_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12981 - slotbuf[0] = 0x40400;
12985 -Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf)
12987 - slotbuf[0] = 0xa10000;
12991 -Opcode_sll_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12993 - slotbuf[0] = 0xa6000;
12997 -Opcode_sll_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12999 - slotbuf[0] = 0xa1000;
13003 -Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf)
13005 - slotbuf[0] = 0x810000;
13009 -Opcode_src_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
13011 - slotbuf[0] = 0xa2000;
13015 -Opcode_src_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
13017 - slotbuf[0] = 0x81000;
13021 -Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf)
13023 - slotbuf[0] = 0x910000;
13027 -Opcode_srl_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
13029 - slotbuf[0] = 0xa5200;
13033 -Opcode_srl_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
13035 - slotbuf[0] = 0xd400;
13039 -Opcode_srl_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
13041 - slotbuf[0] = 0x91000;
13045 -Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf)
13047 - slotbuf[0] = 0xb10000;
13051 -Opcode_sra_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
13053 - slotbuf[0] = 0xa5100;
13057 -Opcode_sra_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
13059 - slotbuf[0] = 0xd200;
13063 -Opcode_sra_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
13065 - slotbuf[0] = 0xb1000;
13069 -Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf)
13071 - slotbuf[0] = 0x10000;
13075 -Opcode_slli_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
13077 - slotbuf[0] = 0x90000;
13081 -Opcode_slli_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
13083 - slotbuf[0] = 0x1000;
13087 -Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf)
13089 - slotbuf[0] = 0x210000;
13093 -Opcode_srai_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
13095 - slotbuf[0] = 0xa0000;
13099 -Opcode_srai_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
13101 - slotbuf[0] = 0xe000;
13105 -Opcode_srai_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
13107 - slotbuf[0] = 0x21000;
13111 -Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf)
13113 - slotbuf[0] = 0x410000;
13117 -Opcode_srli_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
13119 - slotbuf[0] = 0xa4000;
13123 -Opcode_srli_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
13125 - slotbuf[0] = 0x9000;
13129 -Opcode_srli_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
13131 - slotbuf[0] = 0x41000;
13135 -Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf)
13137 - slotbuf[0] = 0x20c0;
13141 -Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf)
13143 - slotbuf[0] = 0x20d0;
13147 -Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf)
13149 - slotbuf[0] = 0x2000;
13153 -Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
13155 - slotbuf[0] = 0x2010;
13159 -Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf)
13161 - slotbuf[0] = 0x2020;
13165 -Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
13167 - slotbuf[0] = 0x2030;
13171 -Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf)
13173 - slotbuf[0] = 0x6000;
13177 -Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
13179 - slotbuf[0] = 0x30100;
13183 -Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
13185 - slotbuf[0] = 0x130100;
13189 -Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
13191 - slotbuf[0] = 0x610100;
13195 -Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
13197 - slotbuf[0] = 0x30200;
13201 -Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
13203 - slotbuf[0] = 0x130200;
13207 -Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
13209 - slotbuf[0] = 0x610200;
13213 -Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
13215 - slotbuf[0] = 0x30000;
13219 -Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
13221 - slotbuf[0] = 0x130000;
13225 -Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
13227 - slotbuf[0] = 0x610000;
13231 -Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
13233 - slotbuf[0] = 0x30300;
13237 -Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
13239 - slotbuf[0] = 0x130300;
13243 -Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
13245 - slotbuf[0] = 0x610300;
13249 -Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
13251 - slotbuf[0] = 0x30500;
13255 -Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
13257 - slotbuf[0] = 0x130500;
13261 -Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
13263 - slotbuf[0] = 0x610500;
13267 -Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf)
13269 - slotbuf[0] = 0x3b000;
13273 -Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf)
13275 - slotbuf[0] = 0x3d000;
13279 -Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
13281 - slotbuf[0] = 0x3e600;
13285 -Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
13287 - slotbuf[0] = 0x13e600;
13291 -Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
13293 - slotbuf[0] = 0x61e600;
13297 -Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
13299 - slotbuf[0] = 0x3b100;
13303 -Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
13305 - slotbuf[0] = 0x13b100;
13309 -Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
13311 - slotbuf[0] = 0x61b100;
13315 -Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
13317 - slotbuf[0] = 0x3d100;
13321 -Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
13323 - slotbuf[0] = 0x13d100;
13327 -Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
13329 - slotbuf[0] = 0x61d100;
13333 -Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
13335 - slotbuf[0] = 0x3b200;
13339 -Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
13341 - slotbuf[0] = 0x13b200;
13345 -Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
13347 - slotbuf[0] = 0x61b200;
13351 -Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
13353 - slotbuf[0] = 0x3d200;
13357 -Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
13359 - slotbuf[0] = 0x13d200;
13363 -Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
13365 - slotbuf[0] = 0x61d200;
13369 -Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
13371 - slotbuf[0] = 0x3b300;
13375 -Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
13377 - slotbuf[0] = 0x13b300;
13381 -Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
13383 - slotbuf[0] = 0x61b300;
13387 -Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
13389 - slotbuf[0] = 0x3d300;
13393 -Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
13395 - slotbuf[0] = 0x13d300;
13399 -Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
13401 - slotbuf[0] = 0x61d300;
13405 -Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
13407 - slotbuf[0] = 0x3b400;
13411 -Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
13413 - slotbuf[0] = 0x13b400;
13417 -Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
13419 - slotbuf[0] = 0x61b400;
13423 -Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
13425 - slotbuf[0] = 0x3d400;
13429 -Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
13431 - slotbuf[0] = 0x13d400;
13435 -Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
13437 - slotbuf[0] = 0x61d400;
13441 -Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
13443 - slotbuf[0] = 0x3b500;
13447 -Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
13449 - slotbuf[0] = 0x13b500;
13453 -Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
13455 - slotbuf[0] = 0x61b500;
13459 -Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
13461 - slotbuf[0] = 0x3d500;
13465 -Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
13467 - slotbuf[0] = 0x13d500;
13471 -Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
13473 - slotbuf[0] = 0x61d500;
13477 -Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
13479 - slotbuf[0] = 0x3b600;
13483 -Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
13485 - slotbuf[0] = 0x13b600;
13489 -Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
13491 - slotbuf[0] = 0x61b600;
13495 -Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
13497 - slotbuf[0] = 0x3d600;
13501 -Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
13503 - slotbuf[0] = 0x13d600;
13507 -Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
13509 - slotbuf[0] = 0x61d600;
13513 -Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
13515 - slotbuf[0] = 0x3b700;
13519 -Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
13521 - slotbuf[0] = 0x13b700;
13525 -Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
13527 - slotbuf[0] = 0x61b700;
13531 -Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
13533 - slotbuf[0] = 0x3d700;
13537 -Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
13539 - slotbuf[0] = 0x13d700;
13543 -Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
13545 - slotbuf[0] = 0x61d700;
13549 -Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
13551 - slotbuf[0] = 0x3c200;
13555 -Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
13557 - slotbuf[0] = 0x13c200;
13561 -Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
13563 - slotbuf[0] = 0x61c200;
13567 -Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
13569 - slotbuf[0] = 0x3c300;
13573 -Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
13575 - slotbuf[0] = 0x13c300;
13579 -Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
13581 - slotbuf[0] = 0x61c300;
13585 -Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
13587 - slotbuf[0] = 0x3c400;
13591 -Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
13593 - slotbuf[0] = 0x13c400;
13597 -Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
13599 - slotbuf[0] = 0x61c400;
13603 -Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
13605 - slotbuf[0] = 0x3c500;
13609 -Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
13611 - slotbuf[0] = 0x13c500;
13615 -Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
13617 - slotbuf[0] = 0x61c500;
13621 -Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
13623 - slotbuf[0] = 0x3c600;
13627 -Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
13629 - slotbuf[0] = 0x13c600;
13633 -Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
13635 - slotbuf[0] = 0x61c600;
13639 -Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
13641 - slotbuf[0] = 0x3c700;
13645 -Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
13647 - slotbuf[0] = 0x13c700;
13651 -Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
13653 - slotbuf[0] = 0x61c700;
13657 -Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
13659 - slotbuf[0] = 0x3ee00;
13663 -Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
13665 - slotbuf[0] = 0x13ee00;
13669 -Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
13671 - slotbuf[0] = 0x61ee00;
13675 -Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
13677 - slotbuf[0] = 0x3c000;
13681 -Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
13683 - slotbuf[0] = 0x13c000;
13687 -Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
13689 - slotbuf[0] = 0x61c000;
13693 -Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
13695 - slotbuf[0] = 0x3e800;
13699 -Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
13701 - slotbuf[0] = 0x13e800;
13705 -Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
13707 - slotbuf[0] = 0x61e800;
13711 -Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
13713 - slotbuf[0] = 0x3f400;
13717 -Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
13719 - slotbuf[0] = 0x13f400;
13723 -Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
13725 - slotbuf[0] = 0x61f400;
13729 -Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
13731 - slotbuf[0] = 0x3f500;
13735 -Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
13737 - slotbuf[0] = 0x13f500;
13741 -Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
13743 - slotbuf[0] = 0x61f500;
13747 -Opcode_rsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
13749 - slotbuf[0] = 0x3f600;
13753 -Opcode_wsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
13755 - slotbuf[0] = 0x13f600;
13759 -Opcode_xsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
13761 - slotbuf[0] = 0x61f600;
13765 -Opcode_rsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
13767 - slotbuf[0] = 0x3f700;
13771 -Opcode_wsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
13773 - slotbuf[0] = 0x13f700;
13777 -Opcode_xsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
13779 - slotbuf[0] = 0x61f700;
13783 -Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf)
13785 - slotbuf[0] = 0x3eb00;
13789 -Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
13791 - slotbuf[0] = 0x3e700;
13795 -Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
13797 - slotbuf[0] = 0x13e700;
13801 -Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
13803 - slotbuf[0] = 0x61e700;
13807 -Opcode_mul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
13809 - slotbuf[0] = 0x740004;
13813 -Opcode_mul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
13815 - slotbuf[0] = 0x750004;
13819 -Opcode_mul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
13821 - slotbuf[0] = 0x760004;
13825 -Opcode_mul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
13827 - slotbuf[0] = 0x770004;
13831 -Opcode_umul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
13833 - slotbuf[0] = 0x700004;
13837 -Opcode_umul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
13839 - slotbuf[0] = 0x710004;
13843 -Opcode_umul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
13845 - slotbuf[0] = 0x720004;
13849 -Opcode_umul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
13851 - slotbuf[0] = 0x730004;
13855 -Opcode_mul_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
13857 - slotbuf[0] = 0x340004;
13861 -Opcode_mul_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
13863 - slotbuf[0] = 0x350004;
13867 -Opcode_mul_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
13869 - slotbuf[0] = 0x360004;
13873 -Opcode_mul_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
13875 - slotbuf[0] = 0x370004;
13879 -Opcode_mul_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
13881 - slotbuf[0] = 0x640004;
13885 -Opcode_mul_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
13887 - slotbuf[0] = 0x650004;
13891 -Opcode_mul_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
13893 - slotbuf[0] = 0x660004;
13897 -Opcode_mul_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
13899 - slotbuf[0] = 0x670004;
13903 -Opcode_mul_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
13905 - slotbuf[0] = 0x240004;
13909 -Opcode_mul_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
13911 - slotbuf[0] = 0x250004;
13915 -Opcode_mul_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
13917 - slotbuf[0] = 0x260004;
13921 -Opcode_mul_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
13923 - slotbuf[0] = 0x270004;
13927 -Opcode_mula_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
13929 - slotbuf[0] = 0x780004;
13933 -Opcode_mula_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
13935 - slotbuf[0] = 0x790004;
13939 -Opcode_mula_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
13941 - slotbuf[0] = 0x7a0004;
13945 -Opcode_mula_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
13947 - slotbuf[0] = 0x7b0004;
13951 -Opcode_muls_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
13953 - slotbuf[0] = 0x7c0004;
13957 -Opcode_muls_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
13959 - slotbuf[0] = 0x7d0004;
13963 -Opcode_muls_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
13965 - slotbuf[0] = 0x7e0004;
13969 -Opcode_muls_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
13971 - slotbuf[0] = 0x7f0004;
13975 -Opcode_mula_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
13977 - slotbuf[0] = 0x380004;
13981 -Opcode_mula_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
13983 - slotbuf[0] = 0x390004;
13987 -Opcode_mula_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
13989 - slotbuf[0] = 0x3a0004;
13993 -Opcode_mula_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
13995 - slotbuf[0] = 0x3b0004;
13999 -Opcode_muls_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
14001 - slotbuf[0] = 0x3c0004;
14005 -Opcode_muls_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
14007 - slotbuf[0] = 0x3d0004;
14011 -Opcode_muls_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
14013 - slotbuf[0] = 0x3e0004;
14017 -Opcode_muls_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
14019 - slotbuf[0] = 0x3f0004;
14023 -Opcode_mula_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
14025 - slotbuf[0] = 0x680004;
14029 -Opcode_mula_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
14031 - slotbuf[0] = 0x690004;
14035 -Opcode_mula_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
14037 - slotbuf[0] = 0x6a0004;
14041 -Opcode_mula_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
14043 - slotbuf[0] = 0x6b0004;
14047 -Opcode_muls_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
14049 - slotbuf[0] = 0x6c0004;
14053 -Opcode_muls_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
14055 - slotbuf[0] = 0x6d0004;
14059 -Opcode_muls_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
14061 - slotbuf[0] = 0x6e0004;
14065 -Opcode_muls_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
14067 - slotbuf[0] = 0x6f0004;
14071 -Opcode_mula_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
14073 - slotbuf[0] = 0x280004;
14077 -Opcode_mula_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
14079 - slotbuf[0] = 0x290004;
14083 -Opcode_mula_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
14085 - slotbuf[0] = 0x2a0004;
14089 -Opcode_mula_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
14091 - slotbuf[0] = 0x2b0004;
14095 -Opcode_muls_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
14097 - slotbuf[0] = 0x2c0004;
14101 -Opcode_muls_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
14103 - slotbuf[0] = 0x2d0004;
14107 -Opcode_muls_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
14109 - slotbuf[0] = 0x2e0004;
14113 -Opcode_muls_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
14115 - slotbuf[0] = 0x2f0004;
14119 -Opcode_mula_da_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
14121 - slotbuf[0] = 0x580004;
14125 -Opcode_mula_da_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
14127 - slotbuf[0] = 0x480004;
14131 -Opcode_mula_da_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
14133 - slotbuf[0] = 0x590004;
14137 -Opcode_mula_da_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
14139 - slotbuf[0] = 0x490004;
14143 -Opcode_mula_da_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
14145 - slotbuf[0] = 0x5a0004;
14149 -Opcode_mula_da_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
14151 - slotbuf[0] = 0x4a0004;
14155 -Opcode_mula_da_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
14157 - slotbuf[0] = 0x5b0004;
14161 -Opcode_mula_da_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
14163 - slotbuf[0] = 0x4b0004;
14167 -Opcode_mula_dd_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
14169 - slotbuf[0] = 0x180004;
14173 -Opcode_mula_dd_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
14175 - slotbuf[0] = 0x80004;
14179 -Opcode_mula_dd_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
14181 - slotbuf[0] = 0x190004;
14185 -Opcode_mula_dd_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
14187 - slotbuf[0] = 0x90004;
14191 -Opcode_mula_dd_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
14193 - slotbuf[0] = 0x1a0004;
14197 -Opcode_mula_dd_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
14199 - slotbuf[0] = 0xa0004;
14203 -Opcode_mula_dd_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
14205 - slotbuf[0] = 0x1b0004;
14209 -Opcode_mula_dd_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
14211 - slotbuf[0] = 0xb0004;
14215 -Opcode_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
14217 - slotbuf[0] = 0x900004;
14221 -Opcode_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
14223 - slotbuf[0] = 0x800004;
14227 -Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf)
14229 - slotbuf[0] = 0xc10000;
14233 -Opcode_mul16u_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
14235 - slotbuf[0] = 0x9b000;
14239 -Opcode_mul16u_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
14241 - slotbuf[0] = 0xc1000;
14245 -Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf)
14247 - slotbuf[0] = 0xd10000;
14251 -Opcode_mul16s_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
14253 - slotbuf[0] = 0x9c000;
14257 -Opcode_mul16s_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
14259 - slotbuf[0] = 0xd1000;
14263 -Opcode_rsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
14265 - slotbuf[0] = 0x32000;
14269 -Opcode_wsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
14271 - slotbuf[0] = 0x132000;
14275 -Opcode_xsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
14277 - slotbuf[0] = 0x612000;
14281 -Opcode_rsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
14283 - slotbuf[0] = 0x32100;
14287 -Opcode_wsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
14289 - slotbuf[0] = 0x132100;
14293 -Opcode_xsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
14295 - slotbuf[0] = 0x612100;
14299 -Opcode_rsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
14301 - slotbuf[0] = 0x32200;
14305 -Opcode_wsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
14307 - slotbuf[0] = 0x132200;
14311 -Opcode_xsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
14313 - slotbuf[0] = 0x612200;
14317 -Opcode_rsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
14319 - slotbuf[0] = 0x32300;
14323 -Opcode_wsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
14325 - slotbuf[0] = 0x132300;
14329 -Opcode_xsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
14331 - slotbuf[0] = 0x612300;
14335 -Opcode_rsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
14337 - slotbuf[0] = 0x31000;
14341 -Opcode_wsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
14343 - slotbuf[0] = 0x131000;
14347 -Opcode_xsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
14349 - slotbuf[0] = 0x611000;
14353 -Opcode_rsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
14355 - slotbuf[0] = 0x31100;
14359 -Opcode_wsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
14361 - slotbuf[0] = 0x131100;
14365 -Opcode_xsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
14367 - slotbuf[0] = 0x611100;
14371 -Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf)
14373 - slotbuf[0] = 0x3010;
14377 -Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf)
14379 - slotbuf[0] = 0x7000;
14383 -Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf)
14385 - slotbuf[0] = 0x3e200;
14389 -Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf)
14391 - slotbuf[0] = 0x13e200;
14395 -Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf)
14397 - slotbuf[0] = 0x13e300;
14401 -Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
14403 - slotbuf[0] = 0x3e400;
14407 -Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
14409 - slotbuf[0] = 0x13e400;
14413 -Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
14415 - slotbuf[0] = 0x61e400;
14419 -Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf)
14421 - slotbuf[0] = 0x4000;
14425 -Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
14427 - slotbuf[0] = 0xf02d;
14431 -Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
14433 - slotbuf[0] = 0x39000;
14437 -Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
14439 - slotbuf[0] = 0x139000;
14443 -Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
14445 - slotbuf[0] = 0x619000;
14449 -Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
14451 - slotbuf[0] = 0x3a000;
14455 -Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
14457 - slotbuf[0] = 0x13a000;
14461 -Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
14463 - slotbuf[0] = 0x61a000;
14467 -Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
14469 - slotbuf[0] = 0x39100;
14473 -Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
14475 - slotbuf[0] = 0x139100;
14479 -Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
14481 - slotbuf[0] = 0x619100;
14485 -Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
14487 - slotbuf[0] = 0x3a100;
14491 -Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
14493 - slotbuf[0] = 0x13a100;
14497 -Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
14499 - slotbuf[0] = 0x61a100;
14503 -Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
14505 - slotbuf[0] = 0x38000;
14509 -Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
14511 - slotbuf[0] = 0x138000;
14515 -Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
14517 - slotbuf[0] = 0x618000;
14521 -Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
14523 - slotbuf[0] = 0x38100;
14527 -Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
14529 - slotbuf[0] = 0x138100;
14533 -Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
14535 - slotbuf[0] = 0x618100;
14539 -Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
14541 - slotbuf[0] = 0x36000;
14545 -Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
14547 - slotbuf[0] = 0x136000;
14551 -Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
14553 - slotbuf[0] = 0x616000;
14557 -Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
14559 - slotbuf[0] = 0x3e900;
14563 -Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
14565 - slotbuf[0] = 0x13e900;
14569 -Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
14571 - slotbuf[0] = 0x61e900;
14575 -Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
14577 - slotbuf[0] = 0x3ec00;
14581 -Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
14583 - slotbuf[0] = 0x13ec00;
14587 -Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
14589 - slotbuf[0] = 0x61ec00;
14593 -Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
14595 - slotbuf[0] = 0x3ed00;
14599 -Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
14601 - slotbuf[0] = 0x13ed00;
14605 -Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
14607 - slotbuf[0] = 0x61ed00;
14611 -Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
14613 - slotbuf[0] = 0x36800;
14617 -Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
14619 - slotbuf[0] = 0x136800;
14623 -Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
14625 - slotbuf[0] = 0x616800;
14629 -Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf)
14631 - slotbuf[0] = 0xf1e000;
14635 -Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf)
14637 - slotbuf[0] = 0xf1e010;
14641 -Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf)
14643 - slotbuf[0] = 0x135900;
14647 -Opcode_andb_Slot_inst_encode (xtensa_insnbuf slotbuf)
14649 - slotbuf[0] = 0x20000;
14653 -Opcode_andbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
14655 - slotbuf[0] = 0x120000;
14659 -Opcode_orb_Slot_inst_encode (xtensa_insnbuf slotbuf)
14661 - slotbuf[0] = 0x220000;
14665 -Opcode_orbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
14667 - slotbuf[0] = 0x320000;
14671 -Opcode_xorb_Slot_inst_encode (xtensa_insnbuf slotbuf)
14673 - slotbuf[0] = 0x420000;
14677 -Opcode_any4_Slot_inst_encode (xtensa_insnbuf slotbuf)
14679 - slotbuf[0] = 0x8000;
14683 -Opcode_all4_Slot_inst_encode (xtensa_insnbuf slotbuf)
14685 - slotbuf[0] = 0x9000;
14689 -Opcode_any8_Slot_inst_encode (xtensa_insnbuf slotbuf)
14691 - slotbuf[0] = 0xa000;
14695 -Opcode_all8_Slot_inst_encode (xtensa_insnbuf slotbuf)
14697 - slotbuf[0] = 0xb000;
14701 -Opcode_bf_Slot_inst_encode (xtensa_insnbuf slotbuf)
14703 - slotbuf[0] = 0x76;
14707 -Opcode_bt_Slot_inst_encode (xtensa_insnbuf slotbuf)
14709 - slotbuf[0] = 0x1076;
14713 -Opcode_movf_Slot_inst_encode (xtensa_insnbuf slotbuf)
14715 - slotbuf[0] = 0xc30000;
14719 -Opcode_movt_Slot_inst_encode (xtensa_insnbuf slotbuf)
14721 - slotbuf[0] = 0xd30000;
14725 -Opcode_rsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
14727 - slotbuf[0] = 0x30400;
14731 -Opcode_wsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
14733 - slotbuf[0] = 0x130400;
14737 -Opcode_xsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
14739 - slotbuf[0] = 0x610400;
14743 -Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
14745 - slotbuf[0] = 0x3ea00;
14749 -Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
14751 - slotbuf[0] = 0x13ea00;
14755 -Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
14757 - slotbuf[0] = 0x61ea00;
14761 -Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
14763 - slotbuf[0] = 0x3f000;
14767 -Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
14769 - slotbuf[0] = 0x13f000;
14773 -Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
14775 - slotbuf[0] = 0x61f000;
14779 -Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
14781 - slotbuf[0] = 0x3f100;
14785 -Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
14787 - slotbuf[0] = 0x13f100;
14791 -Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
14793 - slotbuf[0] = 0x61f100;
14797 -Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
14799 - slotbuf[0] = 0x3f200;
14803 -Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
14805 - slotbuf[0] = 0x13f200;
14809 -Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
14811 - slotbuf[0] = 0x61f200;
14815 -Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf)
14817 - slotbuf[0] = 0x70c2;
14821 -Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf)
14823 - slotbuf[0] = 0x70e2;
14827 -Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf)
14829 - slotbuf[0] = 0x70d2;
14833 -Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf)
14835 - slotbuf[0] = 0x270d2;
14839 -Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf)
14841 - slotbuf[0] = 0x370d2;
14845 -Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf)
14847 - slotbuf[0] = 0x70f2;
14851 -Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf)
14853 - slotbuf[0] = 0xf10000;
14857 -Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf)
14859 - slotbuf[0] = 0xf12000;
14863 -Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf)
14865 - slotbuf[0] = 0xf11000;
14869 -Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf)
14871 - slotbuf[0] = 0xf13000;
14875 -Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
14877 - slotbuf[0] = 0x7042;
14881 -Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
14883 - slotbuf[0] = 0x7052;
14887 -Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
14889 - slotbuf[0] = 0x47082;
14893 -Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
14895 - slotbuf[0] = 0x57082;
14899 -Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf)
14901 - slotbuf[0] = 0x7062;
14905 -Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf)
14907 - slotbuf[0] = 0x7072;
14911 -Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
14913 - slotbuf[0] = 0x7002;
14917 -Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf)
14919 - slotbuf[0] = 0x7012;
14923 -Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf)
14925 - slotbuf[0] = 0x7022;
14929 -Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
14931 - slotbuf[0] = 0x7032;
14935 -Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf)
14937 - slotbuf[0] = 0x7082;
14941 -Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf)
14943 - slotbuf[0] = 0x27082;
14947 -Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf)
14949 - slotbuf[0] = 0x37082;
14953 -Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf)
14955 - slotbuf[0] = 0xf19000;
14959 -Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf)
14961 - slotbuf[0] = 0xf18000;
14965 -Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
14967 - slotbuf[0] = 0x135300;
14971 -Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
14973 - slotbuf[0] = 0x35300;
14977 -Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
14979 - slotbuf[0] = 0x615300;
14983 -Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
14985 - slotbuf[0] = 0x35a00;
14989 -Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
14991 - slotbuf[0] = 0x135a00;
14995 -Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
14997 - slotbuf[0] = 0x615a00;
15001 -Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
15003 - slotbuf[0] = 0x35b00;
15007 -Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
15009 - slotbuf[0] = 0x135b00;
15013 -Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
15015 - slotbuf[0] = 0x615b00;
15019 -Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
15021 - slotbuf[0] = 0x35c00;
15025 -Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
15027 - slotbuf[0] = 0x135c00;
15031 -Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
15033 - slotbuf[0] = 0x615c00;
15037 -Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
15039 - slotbuf[0] = 0x50c000;
15043 -Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
15045 - slotbuf[0] = 0x50d000;
15049 -Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
15051 - slotbuf[0] = 0x50b000;
15055 -Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
15057 - slotbuf[0] = 0x50f000;
15061 -Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
15063 - slotbuf[0] = 0x50e000;
15067 -Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
15069 - slotbuf[0] = 0x504000;
15073 -Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
15075 - slotbuf[0] = 0x505000;
15079 -Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
15081 - slotbuf[0] = 0x503000;
15085 -Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
15087 - slotbuf[0] = 0x507000;
15091 -Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
15093 - slotbuf[0] = 0x506000;
15097 -Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf)
15099 - slotbuf[0] = 0xf1f000;
15103 -Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
15105 - slotbuf[0] = 0x501000;
15109 -Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
15111 - slotbuf[0] = 0x509000;
15115 -Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
15117 - slotbuf[0] = 0x3e000;
15121 -Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
15123 - slotbuf[0] = 0x13e000;
15127 -Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
15129 - slotbuf[0] = 0x61e000;
15133 -Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf)
15135 - slotbuf[0] = 0x330000;
15139 -Opcode_clamps_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
15141 - slotbuf[0] = 0x33000;
15145 -Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf)
15147 - slotbuf[0] = 0x430000;
15151 -Opcode_min_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
15153 - slotbuf[0] = 0x43000;
15157 -Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf)
15159 - slotbuf[0] = 0x530000;
15163 -Opcode_max_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
15165 - slotbuf[0] = 0x53000;
15169 -Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf)
15171 - slotbuf[0] = 0x630000;
15175 -Opcode_minu_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
15177 - slotbuf[0] = 0x63000;
15181 -Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
15183 - slotbuf[0] = 0x730000;
15187 -Opcode_maxu_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
15189 - slotbuf[0] = 0x73000;
15193 -Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf)
15195 - slotbuf[0] = 0x40e000;
15199 -Opcode_nsa_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
15201 - slotbuf[0] = 0x40e00;
15205 -Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf)
15207 - slotbuf[0] = 0x40f000;
15211 -Opcode_nsau_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
15213 - slotbuf[0] = 0x40f00;
15217 -Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf)
15219 - slotbuf[0] = 0x230000;
15223 -Opcode_sext_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
15225 - slotbuf[0] = 0x9f000;
15229 -Opcode_sext_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
15231 - slotbuf[0] = 0x8000;
15235 -Opcode_sext_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
15237 - slotbuf[0] = 0x23000;
15241 -Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf)
15243 - slotbuf[0] = 0xb002;
15247 -Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf)
15249 - slotbuf[0] = 0xf002;
15253 -Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf)
15255 - slotbuf[0] = 0xe002;
15259 -Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
15261 - slotbuf[0] = 0x30c00;
15265 -Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
15267 - slotbuf[0] = 0x130c00;
15271 -Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
15273 - slotbuf[0] = 0x610c00;
15277 -Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf)
15279 - slotbuf[0] = 0xc20000;
15283 -Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf)
15285 - slotbuf[0] = 0xd20000;
15289 -Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf)
15291 - slotbuf[0] = 0xe20000;
15295 -Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf)
15297 - slotbuf[0] = 0xf20000;
15301 -Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf)
15303 - slotbuf[0] = 0x820000;
15307 -Opcode_mull_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
15309 - slotbuf[0] = 0x9d000;
15313 -Opcode_mull_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
15315 - slotbuf[0] = 0x82000;
15319 -Opcode_muluh_Slot_inst_encode (xtensa_insnbuf slotbuf)
15321 - slotbuf[0] = 0xa20000;
15325 -Opcode_mulsh_Slot_inst_encode (xtensa_insnbuf slotbuf)
15327 - slotbuf[0] = 0xb20000;
15331 -Opcode_rur_fcr_Slot_inst_encode (xtensa_insnbuf slotbuf)
15333 - slotbuf[0] = 0xe30e80;
15337 -Opcode_wur_fcr_Slot_inst_encode (xtensa_insnbuf slotbuf)
15339 - slotbuf[0] = 0xf3e800;
15343 -Opcode_rur_fsr_Slot_inst_encode (xtensa_insnbuf slotbuf)
15345 - slotbuf[0] = 0xe30e90;
15349 -Opcode_wur_fsr_Slot_inst_encode (xtensa_insnbuf slotbuf)
15351 - slotbuf[0] = 0xf3e900;
15355 -Opcode_add_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15357 - slotbuf[0] = 0xa0000;
15361 -Opcode_sub_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15363 - slotbuf[0] = 0x1a0000;
15367 -Opcode_mul_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15369 - slotbuf[0] = 0x2a0000;
15373 -Opcode_madd_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15375 - slotbuf[0] = 0x4a0000;
15379 -Opcode_msub_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15381 - slotbuf[0] = 0x5a0000;
15385 -Opcode_movf_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15387 - slotbuf[0] = 0xcb0000;
15391 -Opcode_movt_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15393 - slotbuf[0] = 0xdb0000;
15397 -Opcode_moveqz_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15399 - slotbuf[0] = 0x8b0000;
15403 -Opcode_movnez_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15405 - slotbuf[0] = 0x9b0000;
15409 -Opcode_movltz_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15411 - slotbuf[0] = 0xab0000;
15415 -Opcode_movgez_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15417 - slotbuf[0] = 0xbb0000;
15421 -Opcode_abs_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15423 - slotbuf[0] = 0xfa0010;
15427 -Opcode_mov_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15429 - slotbuf[0] = 0xfa0000;
15433 -Opcode_neg_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15435 - slotbuf[0] = 0xfa0060;
15439 -Opcode_un_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15441 - slotbuf[0] = 0x1b0000;
15445 -Opcode_oeq_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15447 - slotbuf[0] = 0x2b0000;
15451 -Opcode_ueq_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15453 - slotbuf[0] = 0x3b0000;
15457 -Opcode_olt_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15459 - slotbuf[0] = 0x4b0000;
15463 -Opcode_ult_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15465 - slotbuf[0] = 0x5b0000;
15469 -Opcode_ole_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15471 - slotbuf[0] = 0x6b0000;
15475 -Opcode_ule_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15477 - slotbuf[0] = 0x7b0000;
15481 -Opcode_float_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15483 - slotbuf[0] = 0xca0000;
15487 -Opcode_ufloat_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15489 - slotbuf[0] = 0xda0000;
15493 -Opcode_round_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15495 - slotbuf[0] = 0x8a0000;
15499 -Opcode_ceil_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15501 - slotbuf[0] = 0xba0000;
15505 -Opcode_floor_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15507 - slotbuf[0] = 0xaa0000;
15511 -Opcode_trunc_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15513 - slotbuf[0] = 0x9a0000;
15517 -Opcode_utrunc_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15519 - slotbuf[0] = 0xea0000;
15523 -Opcode_rfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
15525 - slotbuf[0] = 0xfa0040;
15529 -Opcode_wfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
15531 - slotbuf[0] = 0xfa0050;
15535 -Opcode_lsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
15537 - slotbuf[0] = 0x3;
15541 -Opcode_lsiu_Slot_inst_encode (xtensa_insnbuf slotbuf)
15543 - slotbuf[0] = 0x8003;
15547 -Opcode_lsx_Slot_inst_encode (xtensa_insnbuf slotbuf)
15549 - slotbuf[0] = 0x80000;
15553 -Opcode_lsxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
15555 - slotbuf[0] = 0x180000;
15559 -Opcode_ssi_Slot_inst_encode (xtensa_insnbuf slotbuf)
15561 - slotbuf[0] = 0x4003;
15565 -Opcode_ssiu_Slot_inst_encode (xtensa_insnbuf slotbuf)
15567 - slotbuf[0] = 0xc003;
15571 -Opcode_ssx_Slot_inst_encode (xtensa_insnbuf slotbuf)
15573 - slotbuf[0] = 0x480000;
15577 -Opcode_ssxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
15579 - slotbuf[0] = 0x580000;
15583 -Opcode_beqz_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15585 - slotbuf[0] = 0xa8000000;
15590 -Opcode_bnez_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15592 - slotbuf[0] = 0xc0000000;
15597 -Opcode_bgez_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15599 - slotbuf[0] = 0xb0000000;
15604 -Opcode_bltz_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15606 - slotbuf[0] = 0xb8000000;
15611 -Opcode_beqi_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15613 - slotbuf[0] = 0x40000000;
15618 -Opcode_bnei_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15620 - slotbuf[0] = 0x98000000;
15625 -Opcode_bgei_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15627 - slotbuf[0] = 0x50000000;
15632 -Opcode_blti_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15634 - slotbuf[0] = 0x70000000;
15639 -Opcode_bgeui_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15641 - slotbuf[0] = 0x60000000;
15646 -Opcode_bltui_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15648 - slotbuf[0] = 0x80000000;
15653 -Opcode_bbci_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15655 - slotbuf[0] = 0x8000000;
15660 -Opcode_bbsi_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15662 - slotbuf[0] = 0x10000000;
15667 -Opcode_beq_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15669 - slotbuf[0] = 0x38000000;
15674 -Opcode_bne_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15676 - slotbuf[0] = 0x90000000;
15681 -Opcode_bge_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15683 - slotbuf[0] = 0x48000000;
15688 -Opcode_blt_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15690 - slotbuf[0] = 0x68000000;
15695 -Opcode_bgeu_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15697 - slotbuf[0] = 0x58000000;
15702 -Opcode_bltu_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15704 - slotbuf[0] = 0x78000000;
15709 -Opcode_bany_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15711 - slotbuf[0] = 0x20000000;
15716 -Opcode_bnone_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15718 - slotbuf[0] = 0xa0000000;
15723 -Opcode_ball_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15725 - slotbuf[0] = 0x18000000;
15730 -Opcode_bnall_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15732 - slotbuf[0] = 0x88000000;
15737 -Opcode_bbc_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15739 - slotbuf[0] = 0x28000000;
15744 -Opcode_bbs_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15746 - slotbuf[0] = 0x30000000;
15750 -xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = {
15751 - Opcode_excw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15754 -xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = {
15755 - Opcode_rfe_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15758 -xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = {
15759 - Opcode_rfde_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15762 -xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = {
15763 - Opcode_syscall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15766 -xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = {
15767 - Opcode_simcall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15770 -xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = {
15771 - Opcode_call12_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15774 -xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = {
15775 - Opcode_call8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15778 -xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = {
15779 - Opcode_call4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15782 -xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = {
15783 - Opcode_callx12_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15786 -xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = {
15787 - Opcode_callx8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15790 -xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = {
15791 - Opcode_callx4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15794 -xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = {
15795 - Opcode_entry_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15798 -xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = {
15799 - Opcode_movsp_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15802 -xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = {
15803 - Opcode_rotw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15806 -xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = {
15807 - Opcode_retw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15810 -xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = {
15811 - 0, 0, Opcode_retw_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
15814 -xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = {
15815 - Opcode_rfwo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15818 -xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = {
15819 - Opcode_rfwu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15822 -xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = {
15823 - Opcode_l32e_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15826 -xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = {
15827 - Opcode_s32e_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15830 -xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = {
15831 - Opcode_rsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15834 -xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = {
15835 - Opcode_wsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15838 -xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = {
15839 - Opcode_xsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15842 -xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = {
15843 - Opcode_rsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15846 -xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = {
15847 - Opcode_wsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15850 -xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = {
15851 - Opcode_xsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15854 -xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = {
15855 - 0, Opcode_add_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0
15858 -xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = {
15859 - 0, Opcode_addi_n_Slot_inst16a_encode, 0, 0, 0, 0, Opcode_addi_n_Slot_xt_flix64_slot2_encode, 0
15862 -xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = {
15863 - 0, 0, Opcode_beqz_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
15866 -xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = {
15867 - 0, 0, Opcode_bnez_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
15870 -xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = {
15871 - 0, 0, Opcode_ill_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
15874 -xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = {
15875 - 0, Opcode_l32i_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0
15878 -xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = {
15879 - 0, 0, Opcode_mov_n_Slot_inst16b_encode, Opcode_mov_n_Slot_xt_flix64_slot0_encode, Opcode_mov_n_Slot_xt_flix64_slot0_encode, Opcode_mov_n_Slot_xt_flix64_slot1_encode, Opcode_mov_n_Slot_xt_flix64_slot2_encode, 0
15882 -xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = {
15883 - 0, 0, Opcode_movi_n_Slot_inst16b_encode, 0, 0, 0, Opcode_movi_n_Slot_xt_flix64_slot2_encode, 0
15886 -xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = {
15887 - 0, 0, Opcode_nop_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
15890 -xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = {
15891 - 0, 0, Opcode_ret_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
15894 -xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = {
15895 - 0, Opcode_s32i_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0
15898 -xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = {
15899 - Opcode_rur_threadptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15902 -xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = {
15903 - Opcode_wur_threadptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15906 -xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = {
15907 - Opcode_addi_Slot_inst_encode, 0, 0, Opcode_addi_Slot_xt_flix64_slot0_encode, Opcode_addi_Slot_xt_flix64_slot0_encode, Opcode_addi_Slot_xt_flix64_slot1_encode, 0, 0
15910 -xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = {
15911 - Opcode_addmi_Slot_inst_encode, 0, 0, Opcode_addmi_Slot_xt_flix64_slot0_encode, Opcode_addmi_Slot_xt_flix64_slot0_encode, Opcode_addmi_Slot_xt_flix64_slot1_encode, 0, 0
15914 -xtensa_opcode_encode_fn Opcode_add_encode_fns[] = {
15915 - Opcode_add_Slot_inst_encode, 0, 0, Opcode_add_Slot_xt_flix64_slot0_encode, Opcode_add_Slot_xt_flix64_slot0_encode, Opcode_add_Slot_xt_flix64_slot1_encode, Opcode_add_Slot_xt_flix64_slot2_encode, 0
15918 -xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = {
15919 - Opcode_sub_Slot_inst_encode, 0, 0, Opcode_sub_Slot_xt_flix64_slot0_encode, Opcode_sub_Slot_xt_flix64_slot0_encode, Opcode_sub_Slot_xt_flix64_slot1_encode, Opcode_sub_Slot_xt_flix64_slot2_encode, 0
15922 -xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = {
15923 - Opcode_addx2_Slot_inst_encode, 0, 0, Opcode_addx2_Slot_xt_flix64_slot0_encode, Opcode_addx2_Slot_xt_flix64_slot0_encode, Opcode_addx2_Slot_xt_flix64_slot1_encode, Opcode_addx2_Slot_xt_flix64_slot2_encode, 0
15926 -xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = {
15927 - Opcode_addx4_Slot_inst_encode, 0, 0, Opcode_addx4_Slot_xt_flix64_slot0_encode, Opcode_addx4_Slot_xt_flix64_slot0_encode, Opcode_addx4_Slot_xt_flix64_slot1_encode, Opcode_addx4_Slot_xt_flix64_slot2_encode, 0
15930 -xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = {
15931 - Opcode_addx8_Slot_inst_encode, 0, 0, Opcode_addx8_Slot_xt_flix64_slot0_encode, Opcode_addx8_Slot_xt_flix64_slot0_encode, Opcode_addx8_Slot_xt_flix64_slot1_encode, 0, 0
15934 -xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = {
15935 - Opcode_subx2_Slot_inst_encode, 0, 0, Opcode_subx2_Slot_xt_flix64_slot0_encode, Opcode_subx2_Slot_xt_flix64_slot0_encode, 0, 0, 0
15938 -xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = {
15939 - Opcode_subx4_Slot_inst_encode, 0, 0, Opcode_subx4_Slot_xt_flix64_slot0_encode, Opcode_subx4_Slot_xt_flix64_slot0_encode, 0, 0, 0
15942 -xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = {
15943 - Opcode_subx8_Slot_inst_encode, 0, 0, Opcode_subx8_Slot_xt_flix64_slot0_encode, Opcode_subx8_Slot_xt_flix64_slot0_encode, 0, 0, 0
15946 -xtensa_opcode_encode_fn Opcode_and_encode_fns[] = {
15947 - Opcode_and_Slot_inst_encode, 0, 0, Opcode_and_Slot_xt_flix64_slot0_encode, Opcode_and_Slot_xt_flix64_slot0_encode, Opcode_and_Slot_xt_flix64_slot1_encode, Opcode_and_Slot_xt_flix64_slot2_encode, 0
15950 -xtensa_opcode_encode_fn Opcode_or_encode_fns[] = {
15951 - Opcode_or_Slot_inst_encode, 0, 0, Opcode_or_Slot_xt_flix64_slot0_encode, Opcode_or_Slot_xt_flix64_slot0_encode, Opcode_or_Slot_xt_flix64_slot1_encode, Opcode_or_Slot_xt_flix64_slot2_encode, 0
15954 -xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = {
15955 - Opcode_xor_Slot_inst_encode, 0, 0, Opcode_xor_Slot_xt_flix64_slot0_encode, Opcode_xor_Slot_xt_flix64_slot0_encode, Opcode_xor_Slot_xt_flix64_slot1_encode, Opcode_xor_Slot_xt_flix64_slot2_encode, 0
15958 -xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = {
15959 - Opcode_beqi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15962 -xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = {
15963 - Opcode_bnei_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15966 -xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = {
15967 - Opcode_bgei_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15970 -xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = {
15971 - Opcode_blti_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15974 -xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = {
15975 - Opcode_bbci_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15978 -xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = {
15979 - Opcode_bbsi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15982 -xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = {
15983 - Opcode_bgeui_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15986 -xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = {
15987 - Opcode_bltui_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15990 -xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = {
15991 - Opcode_beq_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15994 -xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = {
15995 - Opcode_bne_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15998 -xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = {
15999 - Opcode_bge_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16002 -xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = {
16003 - Opcode_blt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16006 -xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = {
16007 - Opcode_bgeu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16010 -xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = {
16011 - Opcode_bltu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16014 -xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = {
16015 - Opcode_bany_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16018 -xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = {
16019 - Opcode_bnone_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16022 -xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = {
16023 - Opcode_ball_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16026 -xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = {
16027 - Opcode_bnall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16030 -xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = {
16031 - Opcode_bbc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16034 -xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = {
16035 - Opcode_bbs_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16038 -xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = {
16039 - Opcode_beqz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16042 -xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = {
16043 - Opcode_bnez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16046 -xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = {
16047 - Opcode_bgez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16050 -xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = {
16051 - Opcode_bltz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16054 -xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = {
16055 - Opcode_call0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16058 -xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = {
16059 - Opcode_callx0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16062 -xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = {
16063 - Opcode_extui_Slot_inst_encode, 0, 0, Opcode_extui_Slot_xt_flix64_slot0_encode, Opcode_extui_Slot_xt_flix64_slot0_encode, Opcode_extui_Slot_xt_flix64_slot1_encode, 0, 0
16066 -xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = {
16067 - Opcode_ill_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16070 -xtensa_opcode_encode_fn Opcode_j_encode_fns[] = {
16071 - Opcode_j_Slot_inst_encode, 0, 0, 0, 0, Opcode_j_Slot_xt_flix64_slot1_encode, 0, 0
16074 -xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = {
16075 - Opcode_jx_Slot_inst_encode, 0, 0, 0, 0, Opcode_jx_Slot_xt_flix64_slot1_encode, 0, 0
16078 -xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = {
16079 - Opcode_l16ui_Slot_inst_encode, 0, 0, Opcode_l16ui_Slot_xt_flix64_slot0_encode, Opcode_l16ui_Slot_xt_flix64_slot0_encode, 0, 0, 0
16082 -xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = {
16083 - Opcode_l16si_Slot_inst_encode, 0, 0, Opcode_l16si_Slot_xt_flix64_slot0_encode, Opcode_l16si_Slot_xt_flix64_slot0_encode, 0, 0, 0
16086 -xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = {
16087 - Opcode_l32i_Slot_inst_encode, 0, 0, Opcode_l32i_Slot_xt_flix64_slot0_encode, Opcode_l32i_Slot_xt_flix64_slot0_encode, 0, 0, 0
16090 -xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = {
16091 - Opcode_l32r_Slot_inst_encode, 0, 0, Opcode_l32r_Slot_xt_flix64_slot0_encode, Opcode_l32r_Slot_xt_flix64_slot0_encode, 0, 0, 0
16094 -xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = {
16095 - Opcode_l8ui_Slot_inst_encode, 0, 0, Opcode_l8ui_Slot_xt_flix64_slot0_encode, Opcode_l8ui_Slot_xt_flix64_slot0_encode, 0, 0, 0
16098 -xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = {
16099 - Opcode_loop_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16102 -xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = {
16103 - Opcode_loopnez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16106 -xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = {
16107 - Opcode_loopgtz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16110 -xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = {
16111 - Opcode_movi_Slot_inst_encode, 0, 0, Opcode_movi_Slot_xt_flix64_slot0_encode, Opcode_movi_Slot_xt_flix64_slot0_encode, Opcode_movi_Slot_xt_flix64_slot1_encode, 0, 0
16114 -xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = {
16115 - Opcode_moveqz_Slot_inst_encode, 0, 0, Opcode_moveqz_Slot_xt_flix64_slot0_encode, Opcode_moveqz_Slot_xt_flix64_slot0_encode, Opcode_moveqz_Slot_xt_flix64_slot1_encode, 0, 0
16118 -xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = {
16119 - Opcode_movnez_Slot_inst_encode, 0, 0, Opcode_movnez_Slot_xt_flix64_slot0_encode, Opcode_movnez_Slot_xt_flix64_slot0_encode, Opcode_movnez_Slot_xt_flix64_slot1_encode, 0, 0
16122 -xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = {
16123 - Opcode_movltz_Slot_inst_encode, 0, 0, Opcode_movltz_Slot_xt_flix64_slot0_encode, Opcode_movltz_Slot_xt_flix64_slot0_encode, Opcode_movltz_Slot_xt_flix64_slot1_encode, 0, 0
16126 -xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = {
16127 - Opcode_movgez_Slot_inst_encode, 0, 0, Opcode_movgez_Slot_xt_flix64_slot0_encode, Opcode_movgez_Slot_xt_flix64_slot0_encode, Opcode_movgez_Slot_xt_flix64_slot1_encode, 0, 0
16130 -xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = {
16131 - Opcode_neg_Slot_inst_encode, 0, 0, Opcode_neg_Slot_xt_flix64_slot0_encode, Opcode_neg_Slot_xt_flix64_slot0_encode, Opcode_neg_Slot_xt_flix64_slot1_encode, Opcode_neg_Slot_xt_flix64_slot2_encode, 0
16134 -xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = {
16135 - Opcode_abs_Slot_inst_encode, 0, 0, Opcode_abs_Slot_xt_flix64_slot0_encode, Opcode_abs_Slot_xt_flix64_slot0_encode, 0, Opcode_abs_Slot_xt_flix64_slot2_encode, 0
16138 -xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = {
16139 - Opcode_nop_Slot_inst_encode, 0, 0, Opcode_nop_Slot_xt_flix64_slot0_encode, Opcode_nop_Slot_xt_flix64_slot0_encode, Opcode_nop_Slot_xt_flix64_slot1_encode, Opcode_nop_Slot_xt_flix64_slot2_encode, Opcode_nop_Slot_xt_flix64_slot3_encode
16142 -xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = {
16143 - Opcode_ret_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16146 -xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = {
16147 - Opcode_s16i_Slot_inst_encode, 0, 0, Opcode_s16i_Slot_xt_flix64_slot0_encode, Opcode_s16i_Slot_xt_flix64_slot0_encode, 0, 0, 0
16150 -xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = {
16151 - Opcode_s32i_Slot_inst_encode, 0, 0, Opcode_s32i_Slot_xt_flix64_slot0_encode, Opcode_s32i_Slot_xt_flix64_slot0_encode, 0, 0, 0
16154 -xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = {
16155 - Opcode_s8i_Slot_inst_encode, 0, 0, Opcode_s8i_Slot_xt_flix64_slot0_encode, Opcode_s8i_Slot_xt_flix64_slot0_encode, 0, 0, 0
16158 -xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = {
16159 - Opcode_ssr_Slot_inst_encode, 0, 0, Opcode_ssr_Slot_xt_flix64_slot0_encode, Opcode_ssr_Slot_xt_flix64_slot0_encode, 0, 0, 0
16162 -xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = {
16163 - Opcode_ssl_Slot_inst_encode, 0, 0, Opcode_ssl_Slot_xt_flix64_slot0_encode, Opcode_ssl_Slot_xt_flix64_slot0_encode, Opcode_ssl_Slot_xt_flix64_slot1_encode, 0, 0
16166 -xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = {
16167 - Opcode_ssa8l_Slot_inst_encode, 0, 0, Opcode_ssa8l_Slot_xt_flix64_slot0_encode, Opcode_ssa8l_Slot_xt_flix64_slot0_encode, 0, 0, 0
16170 -xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = {
16171 - Opcode_ssa8b_Slot_inst_encode, 0, 0, Opcode_ssa8b_Slot_xt_flix64_slot0_encode, Opcode_ssa8b_Slot_xt_flix64_slot0_encode, 0, 0, 0
16174 -xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = {
16175 - Opcode_ssai_Slot_inst_encode, 0, 0, Opcode_ssai_Slot_xt_flix64_slot0_encode, Opcode_ssai_Slot_xt_flix64_slot0_encode, 0, 0, 0
16178 -xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = {
16179 - Opcode_sll_Slot_inst_encode, 0, 0, Opcode_sll_Slot_xt_flix64_slot0_encode, Opcode_sll_Slot_xt_flix64_slot0_encode, Opcode_sll_Slot_xt_flix64_slot1_encode, 0, 0
16182 -xtensa_opcode_encode_fn Opcode_src_encode_fns[] = {
16183 - Opcode_src_Slot_inst_encode, 0, 0, Opcode_src_Slot_xt_flix64_slot0_encode, Opcode_src_Slot_xt_flix64_slot0_encode, Opcode_src_Slot_xt_flix64_slot1_encode, 0, 0
16186 -xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = {
16187 - Opcode_srl_Slot_inst_encode, 0, 0, Opcode_srl_Slot_xt_flix64_slot0_encode, Opcode_srl_Slot_xt_flix64_slot0_encode, Opcode_srl_Slot_xt_flix64_slot1_encode, Opcode_srl_Slot_xt_flix64_slot2_encode, 0
16190 -xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = {
16191 - Opcode_sra_Slot_inst_encode, 0, 0, Opcode_sra_Slot_xt_flix64_slot0_encode, Opcode_sra_Slot_xt_flix64_slot0_encode, Opcode_sra_Slot_xt_flix64_slot1_encode, Opcode_sra_Slot_xt_flix64_slot2_encode, 0
16194 -xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = {
16195 - Opcode_slli_Slot_inst_encode, 0, 0, Opcode_slli_Slot_xt_flix64_slot0_encode, Opcode_slli_Slot_xt_flix64_slot0_encode, Opcode_slli_Slot_xt_flix64_slot1_encode, 0, 0
16198 -xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = {
16199 - Opcode_srai_Slot_inst_encode, 0, 0, Opcode_srai_Slot_xt_flix64_slot0_encode, Opcode_srai_Slot_xt_flix64_slot0_encode, Opcode_srai_Slot_xt_flix64_slot1_encode, Opcode_srai_Slot_xt_flix64_slot2_encode, 0
16202 -xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = {
16203 - Opcode_srli_Slot_inst_encode, 0, 0, Opcode_srli_Slot_xt_flix64_slot0_encode, Opcode_srli_Slot_xt_flix64_slot0_encode, Opcode_srli_Slot_xt_flix64_slot1_encode, Opcode_srli_Slot_xt_flix64_slot2_encode, 0
16206 -xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = {
16207 - Opcode_memw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16210 -xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = {
16211 - Opcode_extw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16214 -xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = {
16215 - Opcode_isync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16218 -xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = {
16219 - Opcode_rsync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16222 -xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = {
16223 - Opcode_esync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16226 -xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = {
16227 - Opcode_dsync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16230 -xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = {
16231 - Opcode_rsil_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16234 -xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = {
16235 - Opcode_rsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16238 -xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = {
16239 - Opcode_wsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16242 -xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = {
16243 - Opcode_xsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16246 -xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = {
16247 - Opcode_rsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16250 -xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = {
16251 - Opcode_wsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16254 -xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = {
16255 - Opcode_xsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16258 -xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = {
16259 - Opcode_rsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16262 -xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = {
16263 - Opcode_wsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16266 -xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = {
16267 - Opcode_xsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16270 -xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = {
16271 - Opcode_rsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16274 -xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = {
16275 - Opcode_wsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16278 -xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = {
16279 - Opcode_xsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16282 -xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = {
16283 - Opcode_rsr_litbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16286 -xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = {
16287 - Opcode_wsr_litbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16290 -xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = {
16291 - Opcode_xsr_litbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16294 -xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = {
16295 - Opcode_rsr_176_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16298 -xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = {
16299 - Opcode_rsr_208_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16302 -xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = {
16303 - Opcode_rsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16306 -xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = {
16307 - Opcode_wsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16310 -xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = {
16311 - Opcode_xsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16314 -xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = {
16315 - Opcode_rsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16318 -xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = {
16319 - Opcode_wsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16322 -xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = {
16323 - Opcode_xsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16326 -xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = {
16327 - Opcode_rsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16330 -xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = {
16331 - Opcode_wsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16334 -xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = {
16335 - Opcode_xsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16338 -xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = {
16339 - Opcode_rsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16342 -xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = {
16343 - Opcode_wsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16346 -xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = {
16347 - Opcode_xsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16350 -xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = {
16351 - Opcode_rsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16354 -xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = {
16355 - Opcode_wsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16358 -xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = {
16359 - Opcode_xsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16362 -xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = {
16363 - Opcode_rsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16366 -xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = {
16367 - Opcode_wsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16370 -xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = {
16371 - Opcode_xsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16374 -xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = {
16375 - Opcode_rsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16378 -xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = {
16379 - Opcode_wsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16382 -xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = {
16383 - Opcode_xsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16386 -xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = {
16387 - Opcode_rsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16390 -xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = {
16391 - Opcode_wsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16394 -xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = {
16395 - Opcode_xsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16398 -xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = {
16399 - Opcode_rsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16402 -xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = {
16403 - Opcode_wsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16406 -xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = {
16407 - Opcode_xsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16410 -xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = {
16411 - Opcode_rsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16414 -xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = {
16415 - Opcode_wsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16418 -xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = {
16419 - Opcode_xsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16422 -xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = {
16423 - Opcode_rsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16426 -xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = {
16427 - Opcode_wsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16430 -xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = {
16431 - Opcode_xsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16434 -xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = {
16435 - Opcode_rsr_epc6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16438 -xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = {
16439 - Opcode_wsr_epc6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16442 -xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = {
16443 - Opcode_xsr_epc6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16446 -xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = {
16447 - Opcode_rsr_excsave6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16450 -xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = {
16451 - Opcode_wsr_excsave6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16454 -xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = {
16455 - Opcode_xsr_excsave6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16458 -xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = {
16459 - Opcode_rsr_epc7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16462 -xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = {
16463 - Opcode_wsr_epc7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16466 -xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = {
16467 - Opcode_xsr_epc7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16470 -xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = {
16471 - Opcode_rsr_excsave7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16474 -xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = {
16475 - Opcode_wsr_excsave7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16478 -xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = {
16479 - Opcode_xsr_excsave7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16482 -xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = {
16483 - Opcode_rsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16486 -xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = {
16487 - Opcode_wsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16490 -xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = {
16491 - Opcode_xsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16494 -xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = {
16495 - Opcode_rsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16498 -xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = {
16499 - Opcode_wsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16502 -xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = {
16503 - Opcode_xsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16506 -xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = {
16507 - Opcode_rsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16510 -xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = {
16511 - Opcode_wsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16514 -xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = {
16515 - Opcode_xsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16518 -xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = {
16519 - Opcode_rsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16522 -xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = {
16523 - Opcode_wsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16526 -xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = {
16527 - Opcode_xsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16530 -xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = {
16531 - Opcode_rsr_eps6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16534 -xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = {
16535 - Opcode_wsr_eps6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16538 -xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = {
16539 - Opcode_xsr_eps6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16542 -xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = {
16543 - Opcode_rsr_eps7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16546 -xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = {
16547 - Opcode_wsr_eps7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16550 -xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = {
16551 - Opcode_xsr_eps7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16554 -xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = {
16555 - Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16558 -xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = {
16559 - Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16562 -xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = {
16563 - Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16566 -xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = {
16567 - Opcode_rsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16570 -xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = {
16571 - Opcode_wsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16574 -xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = {
16575 - Opcode_xsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16578 -xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = {
16579 - Opcode_rsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16582 -xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = {
16583 - Opcode_wsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16586 -xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = {
16587 - Opcode_xsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16590 -xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = {
16591 - Opcode_rsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16594 -xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = {
16595 - Opcode_wsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16598 -xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = {
16599 - Opcode_xsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16602 -xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = {
16603 - Opcode_rsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16606 -xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = {
16607 - Opcode_wsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16610 -xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = {
16611 - Opcode_xsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16614 -xtensa_opcode_encode_fn Opcode_rsr_misc2_encode_fns[] = {
16615 - Opcode_rsr_misc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16618 -xtensa_opcode_encode_fn Opcode_wsr_misc2_encode_fns[] = {
16619 - Opcode_wsr_misc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16622 -xtensa_opcode_encode_fn Opcode_xsr_misc2_encode_fns[] = {
16623 - Opcode_xsr_misc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16626 -xtensa_opcode_encode_fn Opcode_rsr_misc3_encode_fns[] = {
16627 - Opcode_rsr_misc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16630 -xtensa_opcode_encode_fn Opcode_wsr_misc3_encode_fns[] = {
16631 - Opcode_wsr_misc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16634 -xtensa_opcode_encode_fn Opcode_xsr_misc3_encode_fns[] = {
16635 - Opcode_xsr_misc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16638 -xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = {
16639 - Opcode_rsr_prid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16642 -xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = {
16643 - Opcode_rsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16646 -xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = {
16647 - Opcode_wsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16650 -xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = {
16651 - Opcode_xsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16654 -xtensa_opcode_encode_fn Opcode_mul_aa_ll_encode_fns[] = {
16655 - Opcode_mul_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16658 -xtensa_opcode_encode_fn Opcode_mul_aa_hl_encode_fns[] = {
16659 - Opcode_mul_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16662 -xtensa_opcode_encode_fn Opcode_mul_aa_lh_encode_fns[] = {
16663 - Opcode_mul_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16666 -xtensa_opcode_encode_fn Opcode_mul_aa_hh_encode_fns[] = {
16667 - Opcode_mul_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16670 -xtensa_opcode_encode_fn Opcode_umul_aa_ll_encode_fns[] = {
16671 - Opcode_umul_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16674 -xtensa_opcode_encode_fn Opcode_umul_aa_hl_encode_fns[] = {
16675 - Opcode_umul_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16678 -xtensa_opcode_encode_fn Opcode_umul_aa_lh_encode_fns[] = {
16679 - Opcode_umul_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16682 -xtensa_opcode_encode_fn Opcode_umul_aa_hh_encode_fns[] = {
16683 - Opcode_umul_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16686 -xtensa_opcode_encode_fn Opcode_mul_ad_ll_encode_fns[] = {
16687 - Opcode_mul_ad_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16690 -xtensa_opcode_encode_fn Opcode_mul_ad_hl_encode_fns[] = {
16691 - Opcode_mul_ad_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16694 -xtensa_opcode_encode_fn Opcode_mul_ad_lh_encode_fns[] = {
16695 - Opcode_mul_ad_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16698 -xtensa_opcode_encode_fn Opcode_mul_ad_hh_encode_fns[] = {
16699 - Opcode_mul_ad_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16702 -xtensa_opcode_encode_fn Opcode_mul_da_ll_encode_fns[] = {
16703 - Opcode_mul_da_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16706 -xtensa_opcode_encode_fn Opcode_mul_da_hl_encode_fns[] = {
16707 - Opcode_mul_da_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16710 -xtensa_opcode_encode_fn Opcode_mul_da_lh_encode_fns[] = {
16711 - Opcode_mul_da_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16714 -xtensa_opcode_encode_fn Opcode_mul_da_hh_encode_fns[] = {
16715 - Opcode_mul_da_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16718 -xtensa_opcode_encode_fn Opcode_mul_dd_ll_encode_fns[] = {
16719 - Opcode_mul_dd_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16722 -xtensa_opcode_encode_fn Opcode_mul_dd_hl_encode_fns[] = {
16723 - Opcode_mul_dd_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16726 -xtensa_opcode_encode_fn Opcode_mul_dd_lh_encode_fns[] = {
16727 - Opcode_mul_dd_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16730 -xtensa_opcode_encode_fn Opcode_mul_dd_hh_encode_fns[] = {
16731 - Opcode_mul_dd_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16734 -xtensa_opcode_encode_fn Opcode_mula_aa_ll_encode_fns[] = {
16735 - Opcode_mula_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16738 -xtensa_opcode_encode_fn Opcode_mula_aa_hl_encode_fns[] = {
16739 - Opcode_mula_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16742 -xtensa_opcode_encode_fn Opcode_mula_aa_lh_encode_fns[] = {
16743 - Opcode_mula_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16746 -xtensa_opcode_encode_fn Opcode_mula_aa_hh_encode_fns[] = {
16747 - Opcode_mula_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16750 -xtensa_opcode_encode_fn Opcode_muls_aa_ll_encode_fns[] = {
16751 - Opcode_muls_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16754 -xtensa_opcode_encode_fn Opcode_muls_aa_hl_encode_fns[] = {
16755 - Opcode_muls_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16758 -xtensa_opcode_encode_fn Opcode_muls_aa_lh_encode_fns[] = {
16759 - Opcode_muls_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16762 -xtensa_opcode_encode_fn Opcode_muls_aa_hh_encode_fns[] = {
16763 - Opcode_muls_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16766 -xtensa_opcode_encode_fn Opcode_mula_ad_ll_encode_fns[] = {
16767 - Opcode_mula_ad_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16770 -xtensa_opcode_encode_fn Opcode_mula_ad_hl_encode_fns[] = {
16771 - Opcode_mula_ad_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16774 -xtensa_opcode_encode_fn Opcode_mula_ad_lh_encode_fns[] = {
16775 - Opcode_mula_ad_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16778 -xtensa_opcode_encode_fn Opcode_mula_ad_hh_encode_fns[] = {
16779 - Opcode_mula_ad_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16782 -xtensa_opcode_encode_fn Opcode_muls_ad_ll_encode_fns[] = {
16783 - Opcode_muls_ad_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16786 -xtensa_opcode_encode_fn Opcode_muls_ad_hl_encode_fns[] = {
16787 - Opcode_muls_ad_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16790 -xtensa_opcode_encode_fn Opcode_muls_ad_lh_encode_fns[] = {
16791 - Opcode_muls_ad_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16794 -xtensa_opcode_encode_fn Opcode_muls_ad_hh_encode_fns[] = {
16795 - Opcode_muls_ad_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16798 -xtensa_opcode_encode_fn Opcode_mula_da_ll_encode_fns[] = {
16799 - Opcode_mula_da_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16802 -xtensa_opcode_encode_fn Opcode_mula_da_hl_encode_fns[] = {
16803 - Opcode_mula_da_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16806 -xtensa_opcode_encode_fn Opcode_mula_da_lh_encode_fns[] = {
16807 - Opcode_mula_da_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16810 -xtensa_opcode_encode_fn Opcode_mula_da_hh_encode_fns[] = {
16811 - Opcode_mula_da_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16814 -xtensa_opcode_encode_fn Opcode_muls_da_ll_encode_fns[] = {
16815 - Opcode_muls_da_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16818 -xtensa_opcode_encode_fn Opcode_muls_da_hl_encode_fns[] = {
16819 - Opcode_muls_da_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16822 -xtensa_opcode_encode_fn Opcode_muls_da_lh_encode_fns[] = {
16823 - Opcode_muls_da_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16826 -xtensa_opcode_encode_fn Opcode_muls_da_hh_encode_fns[] = {
16827 - Opcode_muls_da_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16830 -xtensa_opcode_encode_fn Opcode_mula_dd_ll_encode_fns[] = {
16831 - Opcode_mula_dd_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16834 -xtensa_opcode_encode_fn Opcode_mula_dd_hl_encode_fns[] = {
16835 - Opcode_mula_dd_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16838 -xtensa_opcode_encode_fn Opcode_mula_dd_lh_encode_fns[] = {
16839 - Opcode_mula_dd_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16842 -xtensa_opcode_encode_fn Opcode_mula_dd_hh_encode_fns[] = {
16843 - Opcode_mula_dd_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16846 -xtensa_opcode_encode_fn Opcode_muls_dd_ll_encode_fns[] = {
16847 - Opcode_muls_dd_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16850 -xtensa_opcode_encode_fn Opcode_muls_dd_hl_encode_fns[] = {
16851 - Opcode_muls_dd_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16854 -xtensa_opcode_encode_fn Opcode_muls_dd_lh_encode_fns[] = {
16855 - Opcode_muls_dd_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16858 -xtensa_opcode_encode_fn Opcode_muls_dd_hh_encode_fns[] = {
16859 - Opcode_muls_dd_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16862 -xtensa_opcode_encode_fn Opcode_mula_da_ll_lddec_encode_fns[] = {
16863 - Opcode_mula_da_ll_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16866 -xtensa_opcode_encode_fn Opcode_mula_da_ll_ldinc_encode_fns[] = {
16867 - Opcode_mula_da_ll_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16870 -xtensa_opcode_encode_fn Opcode_mula_da_hl_lddec_encode_fns[] = {
16871 - Opcode_mula_da_hl_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16874 -xtensa_opcode_encode_fn Opcode_mula_da_hl_ldinc_encode_fns[] = {
16875 - Opcode_mula_da_hl_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16878 -xtensa_opcode_encode_fn Opcode_mula_da_lh_lddec_encode_fns[] = {
16879 - Opcode_mula_da_lh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16882 -xtensa_opcode_encode_fn Opcode_mula_da_lh_ldinc_encode_fns[] = {
16883 - Opcode_mula_da_lh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16886 -xtensa_opcode_encode_fn Opcode_mula_da_hh_lddec_encode_fns[] = {
16887 - Opcode_mula_da_hh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16890 -xtensa_opcode_encode_fn Opcode_mula_da_hh_ldinc_encode_fns[] = {
16891 - Opcode_mula_da_hh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16894 -xtensa_opcode_encode_fn Opcode_mula_dd_ll_lddec_encode_fns[] = {
16895 - Opcode_mula_dd_ll_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16898 -xtensa_opcode_encode_fn Opcode_mula_dd_ll_ldinc_encode_fns[] = {
16899 - Opcode_mula_dd_ll_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16902 -xtensa_opcode_encode_fn Opcode_mula_dd_hl_lddec_encode_fns[] = {
16903 - Opcode_mula_dd_hl_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16906 -xtensa_opcode_encode_fn Opcode_mula_dd_hl_ldinc_encode_fns[] = {
16907 - Opcode_mula_dd_hl_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16910 -xtensa_opcode_encode_fn Opcode_mula_dd_lh_lddec_encode_fns[] = {
16911 - Opcode_mula_dd_lh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16914 -xtensa_opcode_encode_fn Opcode_mula_dd_lh_ldinc_encode_fns[] = {
16915 - Opcode_mula_dd_lh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16918 -xtensa_opcode_encode_fn Opcode_mula_dd_hh_lddec_encode_fns[] = {
16919 - Opcode_mula_dd_hh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16922 -xtensa_opcode_encode_fn Opcode_mula_dd_hh_ldinc_encode_fns[] = {
16923 - Opcode_mula_dd_hh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16926 -xtensa_opcode_encode_fn Opcode_lddec_encode_fns[] = {
16927 - Opcode_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16930 -xtensa_opcode_encode_fn Opcode_ldinc_encode_fns[] = {
16931 - Opcode_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16934 -xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = {
16935 - Opcode_mul16u_Slot_inst_encode, 0, 0, Opcode_mul16u_Slot_xt_flix64_slot0_encode, Opcode_mul16u_Slot_xt_flix64_slot0_encode, Opcode_mul16u_Slot_xt_flix64_slot1_encode, 0, 0
16938 -xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = {
16939 - Opcode_mul16s_Slot_inst_encode, 0, 0, Opcode_mul16s_Slot_xt_flix64_slot0_encode, Opcode_mul16s_Slot_xt_flix64_slot0_encode, Opcode_mul16s_Slot_xt_flix64_slot1_encode, 0, 0
16942 -xtensa_opcode_encode_fn Opcode_rsr_m0_encode_fns[] = {
16943 - Opcode_rsr_m0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16946 -xtensa_opcode_encode_fn Opcode_wsr_m0_encode_fns[] = {
16947 - Opcode_wsr_m0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16950 -xtensa_opcode_encode_fn Opcode_xsr_m0_encode_fns[] = {
16951 - Opcode_xsr_m0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16954 -xtensa_opcode_encode_fn Opcode_rsr_m1_encode_fns[] = {
16955 - Opcode_rsr_m1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16958 -xtensa_opcode_encode_fn Opcode_wsr_m1_encode_fns[] = {
16959 - Opcode_wsr_m1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16962 -xtensa_opcode_encode_fn Opcode_xsr_m1_encode_fns[] = {
16963 - Opcode_xsr_m1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16966 -xtensa_opcode_encode_fn Opcode_rsr_m2_encode_fns[] = {
16967 - Opcode_rsr_m2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16970 -xtensa_opcode_encode_fn Opcode_wsr_m2_encode_fns[] = {
16971 - Opcode_wsr_m2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16974 -xtensa_opcode_encode_fn Opcode_xsr_m2_encode_fns[] = {
16975 - Opcode_xsr_m2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16978 -xtensa_opcode_encode_fn Opcode_rsr_m3_encode_fns[] = {
16979 - Opcode_rsr_m3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16982 -xtensa_opcode_encode_fn Opcode_wsr_m3_encode_fns[] = {
16983 - Opcode_wsr_m3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16986 -xtensa_opcode_encode_fn Opcode_xsr_m3_encode_fns[] = {
16987 - Opcode_xsr_m3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16990 -xtensa_opcode_encode_fn Opcode_rsr_acclo_encode_fns[] = {
16991 - Opcode_rsr_acclo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16994 -xtensa_opcode_encode_fn Opcode_wsr_acclo_encode_fns[] = {
16995 - Opcode_wsr_acclo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16998 -xtensa_opcode_encode_fn Opcode_xsr_acclo_encode_fns[] = {
16999 - Opcode_xsr_acclo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17002 -xtensa_opcode_encode_fn Opcode_rsr_acchi_encode_fns[] = {
17003 - Opcode_rsr_acchi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17006 -xtensa_opcode_encode_fn Opcode_wsr_acchi_encode_fns[] = {
17007 - Opcode_wsr_acchi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17010 -xtensa_opcode_encode_fn Opcode_xsr_acchi_encode_fns[] = {
17011 - Opcode_xsr_acchi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17014 -xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = {
17015 - Opcode_rfi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17018 -xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = {
17019 - Opcode_waiti_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17022 -xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = {
17023 - Opcode_rsr_interrupt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17026 -xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = {
17027 - Opcode_wsr_intset_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17030 -xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = {
17031 - Opcode_wsr_intclear_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17034 -xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = {
17035 - Opcode_rsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17038 -xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = {
17039 - Opcode_wsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17042 -xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = {
17043 - Opcode_xsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17046 -xtensa_opcode_encode_fn Opcode_break_encode_fns[] = {
17047 - Opcode_break_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17050 -xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = {
17051 - 0, 0, Opcode_break_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
17054 -xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = {
17055 - Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17058 -xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = {
17059 - Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17062 -xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = {
17063 - Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17066 -xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = {
17067 - Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17070 -xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = {
17071 - Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17074 -xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = {
17075 - Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17078 -xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = {
17079 - Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17082 -xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = {
17083 - Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17086 -xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = {
17087 - Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17090 -xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = {
17091 - Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17094 -xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = {
17095 - Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17098 -xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = {
17099 - Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17102 -xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = {
17103 - Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17106 -xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = {
17107 - Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17110 -xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = {
17111 - Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17114 -xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = {
17115 - Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17118 -xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = {
17119 - Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17122 -xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = {
17123 - Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17126 -xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = {
17127 - Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17130 -xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = {
17131 - Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17134 -xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = {
17135 - Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17138 -xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = {
17139 - Opcode_rsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17142 -xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = {
17143 - Opcode_wsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17146 -xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = {
17147 - Opcode_xsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17150 -xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = {
17151 - Opcode_rsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17154 -xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = {
17155 - Opcode_wsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17158 -xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = {
17159 - Opcode_xsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17162 -xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = {
17163 - Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17166 -xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = {
17167 - Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17170 -xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = {
17171 - Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17174 -xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = {
17175 - Opcode_rsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17178 -xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = {
17179 - Opcode_wsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17182 -xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = {
17183 - Opcode_xsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17186 -xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = {
17187 - Opcode_rfdo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17190 -xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = {
17191 - Opcode_rfdd_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17194 -xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = {
17195 - Opcode_wsr_mmid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17198 -xtensa_opcode_encode_fn Opcode_andb_encode_fns[] = {
17199 - Opcode_andb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17202 -xtensa_opcode_encode_fn Opcode_andbc_encode_fns[] = {
17203 - Opcode_andbc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17206 -xtensa_opcode_encode_fn Opcode_orb_encode_fns[] = {
17207 - Opcode_orb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17210 -xtensa_opcode_encode_fn Opcode_orbc_encode_fns[] = {
17211 - Opcode_orbc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17214 -xtensa_opcode_encode_fn Opcode_xorb_encode_fns[] = {
17215 - Opcode_xorb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17218 -xtensa_opcode_encode_fn Opcode_any4_encode_fns[] = {
17219 - Opcode_any4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17222 -xtensa_opcode_encode_fn Opcode_all4_encode_fns[] = {
17223 - Opcode_all4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17226 -xtensa_opcode_encode_fn Opcode_any8_encode_fns[] = {
17227 - Opcode_any8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17230 -xtensa_opcode_encode_fn Opcode_all8_encode_fns[] = {
17231 - Opcode_all8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17234 -xtensa_opcode_encode_fn Opcode_bf_encode_fns[] = {
17235 - Opcode_bf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17238 -xtensa_opcode_encode_fn Opcode_bt_encode_fns[] = {
17239 - Opcode_bt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17242 -xtensa_opcode_encode_fn Opcode_movf_encode_fns[] = {
17243 - Opcode_movf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17246 -xtensa_opcode_encode_fn Opcode_movt_encode_fns[] = {
17247 - Opcode_movt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17250 -xtensa_opcode_encode_fn Opcode_rsr_br_encode_fns[] = {
17251 - Opcode_rsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17254 -xtensa_opcode_encode_fn Opcode_wsr_br_encode_fns[] = {
17255 - Opcode_wsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17258 -xtensa_opcode_encode_fn Opcode_xsr_br_encode_fns[] = {
17259 - Opcode_xsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17262 -xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = {
17263 - Opcode_rsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17266 -xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = {
17267 - Opcode_wsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17270 -xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = {
17271 - Opcode_xsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17274 -xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = {
17275 - Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17278 -xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = {
17279 - Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17282 -xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = {
17283 - Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17286 -xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = {
17287 - Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17290 -xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = {
17291 - Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17294 -xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = {
17295 - Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17298 -xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = {
17299 - Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17302 -xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = {
17303 - Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17306 -xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = {
17307 - Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17310 -xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = {
17311 - Opcode_ipf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17314 -xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = {
17315 - Opcode_ihi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17318 -xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = {
17319 - Opcode_ipfl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17322 -xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = {
17323 - Opcode_ihu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17326 -xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = {
17327 - Opcode_iiu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17330 -xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = {
17331 - Opcode_iii_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17334 -xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = {
17335 - Opcode_lict_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17338 -xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = {
17339 - Opcode_licw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17342 -xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = {
17343 - Opcode_sict_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17346 -xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = {
17347 - Opcode_sicw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17350 -xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = {
17351 - Opcode_dhwb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17354 -xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = {
17355 - Opcode_dhwbi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17358 -xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = {
17359 - Opcode_diwb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17362 -xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = {
17363 - Opcode_diwbi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17366 -xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = {
17367 - Opcode_dhi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17370 -xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = {
17371 - Opcode_dii_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17374 -xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = {
17375 - Opcode_dpfr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17378 -xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = {
17379 - Opcode_dpfw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17382 -xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = {
17383 - Opcode_dpfro_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17386 -xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = {
17387 - Opcode_dpfwo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17390 -xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = {
17391 - Opcode_dpfl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17394 -xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = {
17395 - Opcode_dhu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17398 -xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = {
17399 - Opcode_diu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17402 -xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = {
17403 - Opcode_sdct_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17406 -xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = {
17407 - Opcode_ldct_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17410 -xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = {
17411 - Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17414 -xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = {
17415 - Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17418 -xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = {
17419 - Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17422 -xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = {
17423 - Opcode_rsr_rasid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17426 -xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = {
17427 - Opcode_wsr_rasid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17430 -xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = {
17431 - Opcode_xsr_rasid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17434 -xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = {
17435 - Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17438 -xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = {
17439 - Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17442 -xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = {
17443 - Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17446 -xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = {
17447 - Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17450 -xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = {
17451 - Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17454 -xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = {
17455 - Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17458 -xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = {
17459 - Opcode_idtlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17462 -xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = {
17463 - Opcode_pdtlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17466 -xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = {
17467 - Opcode_rdtlb0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17470 -xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = {
17471 - Opcode_rdtlb1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17474 -xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = {
17475 - Opcode_wdtlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17478 -xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = {
17479 - Opcode_iitlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17482 -xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = {
17483 - Opcode_pitlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17486 -xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = {
17487 - Opcode_ritlb0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17490 -xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = {
17491 - Opcode_ritlb1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17494 -xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = {
17495 - Opcode_witlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17498 -xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = {
17499 - Opcode_ldpte_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17502 -xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = {
17503 - Opcode_hwwitlba_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17506 -xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = {
17507 - Opcode_hwwdtlba_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17510 -xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = {
17511 - Opcode_rsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17514 -xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = {
17515 - Opcode_wsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17518 -xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = {
17519 - Opcode_xsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17522 -xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = {
17523 - Opcode_clamps_Slot_inst_encode, 0, 0, Opcode_clamps_Slot_xt_flix64_slot0_encode, Opcode_clamps_Slot_xt_flix64_slot0_encode, 0, 0, 0
17526 -xtensa_opcode_encode_fn Opcode_min_encode_fns[] = {
17527 - Opcode_min_Slot_inst_encode, 0, 0, Opcode_min_Slot_xt_flix64_slot0_encode, Opcode_min_Slot_xt_flix64_slot0_encode, 0, 0, 0
17530 -xtensa_opcode_encode_fn Opcode_max_encode_fns[] = {
17531 - Opcode_max_Slot_inst_encode, 0, 0, Opcode_max_Slot_xt_flix64_slot0_encode, Opcode_max_Slot_xt_flix64_slot0_encode, 0, 0, 0
17534 -xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = {
17535 - Opcode_minu_Slot_inst_encode, 0, 0, Opcode_minu_Slot_xt_flix64_slot0_encode, Opcode_minu_Slot_xt_flix64_slot0_encode, 0, 0, 0
17538 -xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = {
17539 - Opcode_maxu_Slot_inst_encode, 0, 0, Opcode_maxu_Slot_xt_flix64_slot0_encode, Opcode_maxu_Slot_xt_flix64_slot0_encode, 0, 0, 0
17542 -xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = {
17543 - Opcode_nsa_Slot_inst_encode, 0, 0, Opcode_nsa_Slot_xt_flix64_slot0_encode, Opcode_nsa_Slot_xt_flix64_slot0_encode, 0, 0, 0
17546 -xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = {
17547 - Opcode_nsau_Slot_inst_encode, 0, 0, Opcode_nsau_Slot_xt_flix64_slot0_encode, Opcode_nsau_Slot_xt_flix64_slot0_encode, 0, 0, 0
17550 -xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = {
17551 - Opcode_sext_Slot_inst_encode, 0, 0, Opcode_sext_Slot_xt_flix64_slot0_encode, Opcode_sext_Slot_xt_flix64_slot0_encode, Opcode_sext_Slot_xt_flix64_slot1_encode, Opcode_sext_Slot_xt_flix64_slot2_encode, 0
17554 -xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = {
17555 - Opcode_l32ai_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17558 -xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = {
17559 - Opcode_s32ri_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17562 -xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = {
17563 - Opcode_s32c1i_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17566 -xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = {
17567 - Opcode_rsr_scompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17570 -xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = {
17571 - Opcode_wsr_scompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17574 -xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = {
17575 - Opcode_xsr_scompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17578 -xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = {
17579 - Opcode_quou_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17582 -xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = {
17583 - Opcode_quos_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17586 -xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = {
17587 - Opcode_remu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17590 -xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = {
17591 - Opcode_rems_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17594 -xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = {
17595 - Opcode_mull_Slot_inst_encode, 0, 0, Opcode_mull_Slot_xt_flix64_slot0_encode, Opcode_mull_Slot_xt_flix64_slot0_encode, Opcode_mull_Slot_xt_flix64_slot1_encode, 0, 0
17598 -xtensa_opcode_encode_fn Opcode_muluh_encode_fns[] = {
17599 - Opcode_muluh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17602 -xtensa_opcode_encode_fn Opcode_mulsh_encode_fns[] = {
17603 - Opcode_mulsh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17606 -xtensa_opcode_encode_fn Opcode_rur_fcr_encode_fns[] = {
17607 - Opcode_rur_fcr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17610 -xtensa_opcode_encode_fn Opcode_wur_fcr_encode_fns[] = {
17611 - Opcode_wur_fcr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17614 -xtensa_opcode_encode_fn Opcode_rur_fsr_encode_fns[] = {
17615 - Opcode_rur_fsr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17618 -xtensa_opcode_encode_fn Opcode_wur_fsr_encode_fns[] = {
17619 - Opcode_wur_fsr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17622 -xtensa_opcode_encode_fn Opcode_add_s_encode_fns[] = {
17623 - Opcode_add_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17626 -xtensa_opcode_encode_fn Opcode_sub_s_encode_fns[] = {
17627 - Opcode_sub_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17630 -xtensa_opcode_encode_fn Opcode_mul_s_encode_fns[] = {
17631 - Opcode_mul_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17634 -xtensa_opcode_encode_fn Opcode_madd_s_encode_fns[] = {
17635 - Opcode_madd_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17638 -xtensa_opcode_encode_fn Opcode_msub_s_encode_fns[] = {
17639 - Opcode_msub_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17642 -xtensa_opcode_encode_fn Opcode_movf_s_encode_fns[] = {
17643 - Opcode_movf_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17646 -xtensa_opcode_encode_fn Opcode_movt_s_encode_fns[] = {
17647 - Opcode_movt_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17650 -xtensa_opcode_encode_fn Opcode_moveqz_s_encode_fns[] = {
17651 - Opcode_moveqz_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17654 -xtensa_opcode_encode_fn Opcode_movnez_s_encode_fns[] = {
17655 - Opcode_movnez_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17658 -xtensa_opcode_encode_fn Opcode_movltz_s_encode_fns[] = {
17659 - Opcode_movltz_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17662 -xtensa_opcode_encode_fn Opcode_movgez_s_encode_fns[] = {
17663 - Opcode_movgez_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17666 -xtensa_opcode_encode_fn Opcode_abs_s_encode_fns[] = {
17667 - Opcode_abs_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17670 -xtensa_opcode_encode_fn Opcode_mov_s_encode_fns[] = {
17671 - Opcode_mov_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17674 -xtensa_opcode_encode_fn Opcode_neg_s_encode_fns[] = {
17675 - Opcode_neg_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17678 -xtensa_opcode_encode_fn Opcode_un_s_encode_fns[] = {
17679 - Opcode_un_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17682 -xtensa_opcode_encode_fn Opcode_oeq_s_encode_fns[] = {
17683 - Opcode_oeq_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17686 -xtensa_opcode_encode_fn Opcode_ueq_s_encode_fns[] = {
17687 - Opcode_ueq_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17690 -xtensa_opcode_encode_fn Opcode_olt_s_encode_fns[] = {
17691 - Opcode_olt_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17694 -xtensa_opcode_encode_fn Opcode_ult_s_encode_fns[] = {
17695 - Opcode_ult_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17698 -xtensa_opcode_encode_fn Opcode_ole_s_encode_fns[] = {
17699 - Opcode_ole_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17702 -xtensa_opcode_encode_fn Opcode_ule_s_encode_fns[] = {
17703 - Opcode_ule_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17706 -xtensa_opcode_encode_fn Opcode_float_s_encode_fns[] = {
17707 - Opcode_float_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17710 -xtensa_opcode_encode_fn Opcode_ufloat_s_encode_fns[] = {
17711 - Opcode_ufloat_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17714 -xtensa_opcode_encode_fn Opcode_round_s_encode_fns[] = {
17715 - Opcode_round_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17718 -xtensa_opcode_encode_fn Opcode_ceil_s_encode_fns[] = {
17719 - Opcode_ceil_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17722 -xtensa_opcode_encode_fn Opcode_floor_s_encode_fns[] = {
17723 - Opcode_floor_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17726 -xtensa_opcode_encode_fn Opcode_trunc_s_encode_fns[] = {
17727 - Opcode_trunc_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17730 -xtensa_opcode_encode_fn Opcode_utrunc_s_encode_fns[] = {
17731 - Opcode_utrunc_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17734 -xtensa_opcode_encode_fn Opcode_rfr_encode_fns[] = {
17735 - Opcode_rfr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17738 -xtensa_opcode_encode_fn Opcode_wfr_encode_fns[] = {
17739 - Opcode_wfr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17742 -xtensa_opcode_encode_fn Opcode_lsi_encode_fns[] = {
17743 - Opcode_lsi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17746 -xtensa_opcode_encode_fn Opcode_lsiu_encode_fns[] = {
17747 - Opcode_lsiu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17750 -xtensa_opcode_encode_fn Opcode_lsx_encode_fns[] = {
17751 - Opcode_lsx_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17754 -xtensa_opcode_encode_fn Opcode_lsxu_encode_fns[] = {
17755 - Opcode_lsxu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17758 -xtensa_opcode_encode_fn Opcode_ssi_encode_fns[] = {
17759 - Opcode_ssi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17762 -xtensa_opcode_encode_fn Opcode_ssiu_encode_fns[] = {
17763 - Opcode_ssiu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17766 -xtensa_opcode_encode_fn Opcode_ssx_encode_fns[] = {
17767 - Opcode_ssx_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17770 -xtensa_opcode_encode_fn Opcode_ssxu_encode_fns[] = {
17771 - Opcode_ssxu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17774 -xtensa_opcode_encode_fn Opcode_beqz_w18_encode_fns[] = {
17775 - 0, 0, 0, 0, 0, 0, 0, Opcode_beqz_w18_Slot_xt_flix64_slot3_encode
17778 -xtensa_opcode_encode_fn Opcode_bnez_w18_encode_fns[] = {
17779 - 0, 0, 0, 0, 0, 0, 0, Opcode_bnez_w18_Slot_xt_flix64_slot3_encode
17782 -xtensa_opcode_encode_fn Opcode_bgez_w18_encode_fns[] = {
17783 - 0, 0, 0, 0, 0, 0, 0, Opcode_bgez_w18_Slot_xt_flix64_slot3_encode
17786 -xtensa_opcode_encode_fn Opcode_bltz_w18_encode_fns[] = {
17787 - 0, 0, 0, 0, 0, 0, 0, Opcode_bltz_w18_Slot_xt_flix64_slot3_encode
17790 -xtensa_opcode_encode_fn Opcode_beqi_w18_encode_fns[] = {
17791 - 0, 0, 0, 0, 0, 0, 0, Opcode_beqi_w18_Slot_xt_flix64_slot3_encode
17794 -xtensa_opcode_encode_fn Opcode_bnei_w18_encode_fns[] = {
17795 - 0, 0, 0, 0, 0, 0, 0, Opcode_bnei_w18_Slot_xt_flix64_slot3_encode
17798 -xtensa_opcode_encode_fn Opcode_bgei_w18_encode_fns[] = {
17799 - 0, 0, 0, 0, 0, 0, 0, Opcode_bgei_w18_Slot_xt_flix64_slot3_encode
17802 -xtensa_opcode_encode_fn Opcode_blti_w18_encode_fns[] = {
17803 - 0, 0, 0, 0, 0, 0, 0, Opcode_blti_w18_Slot_xt_flix64_slot3_encode
17806 -xtensa_opcode_encode_fn Opcode_bgeui_w18_encode_fns[] = {
17807 - 0, 0, 0, 0, 0, 0, 0, Opcode_bgeui_w18_Slot_xt_flix64_slot3_encode
17810 -xtensa_opcode_encode_fn Opcode_bltui_w18_encode_fns[] = {
17811 - 0, 0, 0, 0, 0, 0, 0, Opcode_bltui_w18_Slot_xt_flix64_slot3_encode
17814 -xtensa_opcode_encode_fn Opcode_bbci_w18_encode_fns[] = {
17815 - 0, 0, 0, 0, 0, 0, 0, Opcode_bbci_w18_Slot_xt_flix64_slot3_encode
17818 -xtensa_opcode_encode_fn Opcode_bbsi_w18_encode_fns[] = {
17819 - 0, 0, 0, 0, 0, 0, 0, Opcode_bbsi_w18_Slot_xt_flix64_slot3_encode
17822 -xtensa_opcode_encode_fn Opcode_beq_w18_encode_fns[] = {
17823 - 0, 0, 0, 0, 0, 0, 0, Opcode_beq_w18_Slot_xt_flix64_slot3_encode
17826 -xtensa_opcode_encode_fn Opcode_bne_w18_encode_fns[] = {
17827 - 0, 0, 0, 0, 0, 0, 0, Opcode_bne_w18_Slot_xt_flix64_slot3_encode
17830 -xtensa_opcode_encode_fn Opcode_bge_w18_encode_fns[] = {
17831 - 0, 0, 0, 0, 0, 0, 0, Opcode_bge_w18_Slot_xt_flix64_slot3_encode
17834 -xtensa_opcode_encode_fn Opcode_blt_w18_encode_fns[] = {
17835 - 0, 0, 0, 0, 0, 0, 0, Opcode_blt_w18_Slot_xt_flix64_slot3_encode
17838 -xtensa_opcode_encode_fn Opcode_bgeu_w18_encode_fns[] = {
17839 - 0, 0, 0, 0, 0, 0, 0, Opcode_bgeu_w18_Slot_xt_flix64_slot3_encode
17842 -xtensa_opcode_encode_fn Opcode_bltu_w18_encode_fns[] = {
17843 - 0, 0, 0, 0, 0, 0, 0, Opcode_bltu_w18_Slot_xt_flix64_slot3_encode
17846 -xtensa_opcode_encode_fn Opcode_bany_w18_encode_fns[] = {
17847 - 0, 0, 0, 0, 0, 0, 0, Opcode_bany_w18_Slot_xt_flix64_slot3_encode
17850 -xtensa_opcode_encode_fn Opcode_bnone_w18_encode_fns[] = {
17851 - 0, 0, 0, 0, 0, 0, 0, Opcode_bnone_w18_Slot_xt_flix64_slot3_encode
17854 -xtensa_opcode_encode_fn Opcode_ball_w18_encode_fns[] = {
17855 - 0, 0, 0, 0, 0, 0, 0, Opcode_ball_w18_Slot_xt_flix64_slot3_encode
17858 -xtensa_opcode_encode_fn Opcode_bnall_w18_encode_fns[] = {
17859 - 0, 0, 0, 0, 0, 0, 0, Opcode_bnall_w18_Slot_xt_flix64_slot3_encode
17862 -xtensa_opcode_encode_fn Opcode_bbc_w18_encode_fns[] = {
17863 - 0, 0, 0, 0, 0, 0, 0, Opcode_bbc_w18_Slot_xt_flix64_slot3_encode
17866 -xtensa_opcode_encode_fn Opcode_bbs_w18_encode_fns[] = {
17867 - 0, 0, 0, 0, 0, 0, 0, Opcode_bbs_w18_Slot_xt_flix64_slot3_encode
17871 -/* Opcode table. */
17873 -static xtensa_opcode_internal opcodes[] = {
17874 - { "excw", 0 /* xt_iclass_excw */,
17876 - Opcode_excw_encode_fns, 0, 0 },
17877 - { "rfe", 1 /* xt_iclass_rfe */,
17878 - XTENSA_OPCODE_IS_JUMP,
17879 - Opcode_rfe_encode_fns, 0, 0 },
17880 - { "rfde", 2 /* xt_iclass_rfde */,
17881 - XTENSA_OPCODE_IS_JUMP,
17882 - Opcode_rfde_encode_fns, 0, 0 },
17883 - { "syscall", 3 /* xt_iclass_syscall */,
17885 - Opcode_syscall_encode_fns, 0, 0 },
17886 - { "simcall", 4 /* xt_iclass_simcall */,
17888 - Opcode_simcall_encode_fns, 0, 0 },
17889 - { "call12", 5 /* xt_iclass_call12 */,
17890 - XTENSA_OPCODE_IS_CALL,
17891 - Opcode_call12_encode_fns, 0, 0 },
17892 - { "call8", 6 /* xt_iclass_call8 */,
17893 - XTENSA_OPCODE_IS_CALL,
17894 - Opcode_call8_encode_fns, 0, 0 },
17895 - { "call4", 7 /* xt_iclass_call4 */,
17896 - XTENSA_OPCODE_IS_CALL,
17897 - Opcode_call4_encode_fns, 0, 0 },
17898 - { "callx12", 8 /* xt_iclass_callx12 */,
17899 - XTENSA_OPCODE_IS_CALL,
17900 - Opcode_callx12_encode_fns, 0, 0 },
17901 - { "callx8", 9 /* xt_iclass_callx8 */,
17902 - XTENSA_OPCODE_IS_CALL,
17903 - Opcode_callx8_encode_fns, 0, 0 },
17904 - { "callx4", 10 /* xt_iclass_callx4 */,
17905 - XTENSA_OPCODE_IS_CALL,
17906 - Opcode_callx4_encode_fns, 0, 0 },
17907 - { "entry", 11 /* xt_iclass_entry */,
17909 - Opcode_entry_encode_fns, 0, 0 },
17910 - { "movsp", 12 /* xt_iclass_movsp */,
17912 - Opcode_movsp_encode_fns, 0, 0 },
17913 - { "rotw", 13 /* xt_iclass_rotw */,
17915 - Opcode_rotw_encode_fns, 0, 0 },
17916 - { "retw", 14 /* xt_iclass_retw */,
17917 - XTENSA_OPCODE_IS_JUMP,
17918 - Opcode_retw_encode_fns, 0, 0 },
17919 - { "retw.n", 14 /* xt_iclass_retw */,
17920 - XTENSA_OPCODE_IS_JUMP,
17921 - Opcode_retw_n_encode_fns, 0, 0 },
17922 - { "rfwo", 15 /* xt_iclass_rfwou */,
17923 - XTENSA_OPCODE_IS_JUMP,
17924 - Opcode_rfwo_encode_fns, 0, 0 },
17925 - { "rfwu", 15 /* xt_iclass_rfwou */,
17926 - XTENSA_OPCODE_IS_JUMP,
17927 - Opcode_rfwu_encode_fns, 0, 0 },
17928 - { "l32e", 16 /* xt_iclass_l32e */,
17930 - Opcode_l32e_encode_fns, 0, 0 },
17931 - { "s32e", 17 /* xt_iclass_s32e */,
17933 - Opcode_s32e_encode_fns, 0, 0 },
17934 - { "rsr.windowbase", 18 /* xt_iclass_rsr.windowbase */,
17936 - Opcode_rsr_windowbase_encode_fns, 0, 0 },
17937 - { "wsr.windowbase", 19 /* xt_iclass_wsr.windowbase */,
17939 - Opcode_wsr_windowbase_encode_fns, 0, 0 },
17940 - { "xsr.windowbase", 20 /* xt_iclass_xsr.windowbase */,
17942 - Opcode_xsr_windowbase_encode_fns, 0, 0 },
17943 - { "rsr.windowstart", 21 /* xt_iclass_rsr.windowstart */,
17945 - Opcode_rsr_windowstart_encode_fns, 0, 0 },
17946 - { "wsr.windowstart", 22 /* xt_iclass_wsr.windowstart */,
17948 - Opcode_wsr_windowstart_encode_fns, 0, 0 },
17949 - { "xsr.windowstart", 23 /* xt_iclass_xsr.windowstart */,
17951 - Opcode_xsr_windowstart_encode_fns, 0, 0 },
17952 - { "add.n", 24 /* xt_iclass_add.n */,
17954 - Opcode_add_n_encode_fns, 0, 0 },
17955 - { "addi.n", 25 /* xt_iclass_addi.n */,
17957 - Opcode_addi_n_encode_fns, 0, 0 },
17958 - { "beqz.n", 26 /* xt_iclass_bz6 */,
17959 - XTENSA_OPCODE_IS_BRANCH,
17960 - Opcode_beqz_n_encode_fns, 0, 0 },
17961 - { "bnez.n", 26 /* xt_iclass_bz6 */,
17962 - XTENSA_OPCODE_IS_BRANCH,
17963 - Opcode_bnez_n_encode_fns, 0, 0 },
17964 - { "ill.n", 27 /* xt_iclass_ill.n */,
17966 - Opcode_ill_n_encode_fns, 0, 0 },
17967 - { "l32i.n", 28 /* xt_iclass_loadi4 */,
17969 - Opcode_l32i_n_encode_fns, 0, 0 },
17970 - { "mov.n", 29 /* xt_iclass_mov.n */,
17972 - Opcode_mov_n_encode_fns, 0, 0 },
17973 - { "movi.n", 30 /* xt_iclass_movi.n */,
17975 - Opcode_movi_n_encode_fns, 0, 0 },
17976 - { "nop.n", 31 /* xt_iclass_nopn */,
17978 - Opcode_nop_n_encode_fns, 0, 0 },
17979 - { "ret.n", 32 /* xt_iclass_retn */,
17980 - XTENSA_OPCODE_IS_JUMP,
17981 - Opcode_ret_n_encode_fns, 0, 0 },
17982 - { "s32i.n", 33 /* xt_iclass_storei4 */,
17984 - Opcode_s32i_n_encode_fns, 0, 0 },
17985 - { "rur.threadptr", 34 /* rur_threadptr */,
17987 - Opcode_rur_threadptr_encode_fns, 0, 0 },
17988 - { "wur.threadptr", 35 /* wur_threadptr */,
17990 - Opcode_wur_threadptr_encode_fns, 0, 0 },
17991 - { "addi", 36 /* xt_iclass_addi */,
17993 - Opcode_addi_encode_fns, 0, 0 },
17994 - { "addmi", 37 /* xt_iclass_addmi */,
17996 - Opcode_addmi_encode_fns, 0, 0 },
17997 - { "add", 38 /* xt_iclass_addsub */,
17999 - Opcode_add_encode_fns, 0, 0 },
18000 - { "sub", 38 /* xt_iclass_addsub */,
18002 - Opcode_sub_encode_fns, 0, 0 },
18003 - { "addx2", 38 /* xt_iclass_addsub */,
18005 - Opcode_addx2_encode_fns, 0, 0 },
18006 - { "addx4", 38 /* xt_iclass_addsub */,
18008 - Opcode_addx4_encode_fns, 0, 0 },
18009 - { "addx8", 38 /* xt_iclass_addsub */,
18011 - Opcode_addx8_encode_fns, 0, 0 },
18012 - { "subx2", 38 /* xt_iclass_addsub */,
18014 - Opcode_subx2_encode_fns, 0, 0 },
18015 - { "subx4", 38 /* xt_iclass_addsub */,
18017 - Opcode_subx4_encode_fns, 0, 0 },
18018 - { "subx8", 38 /* xt_iclass_addsub */,
18020 - Opcode_subx8_encode_fns, 0, 0 },
18021 - { "and", 39 /* xt_iclass_bit */,
18023 - Opcode_and_encode_fns, 0, 0 },
18024 - { "or", 39 /* xt_iclass_bit */,
18026 - Opcode_or_encode_fns, 0, 0 },
18027 - { "xor", 39 /* xt_iclass_bit */,
18029 - Opcode_xor_encode_fns, 0, 0 },
18030 - { "beqi", 40 /* xt_iclass_bsi8 */,
18031 - XTENSA_OPCODE_IS_BRANCH,
18032 - Opcode_beqi_encode_fns, 0, 0 },
18033 - { "bnei", 40 /* xt_iclass_bsi8 */,
18034 - XTENSA_OPCODE_IS_BRANCH,
18035 - Opcode_bnei_encode_fns, 0, 0 },
18036 - { "bgei", 40 /* xt_iclass_bsi8 */,
18037 - XTENSA_OPCODE_IS_BRANCH,
18038 - Opcode_bgei_encode_fns, 0, 0 },
18039 - { "blti", 40 /* xt_iclass_bsi8 */,
18040 - XTENSA_OPCODE_IS_BRANCH,
18041 - Opcode_blti_encode_fns, 0, 0 },
18042 - { "bbci", 41 /* xt_iclass_bsi8b */,
18043 - XTENSA_OPCODE_IS_BRANCH,
18044 - Opcode_bbci_encode_fns, 0, 0 },
18045 - { "bbsi", 41 /* xt_iclass_bsi8b */,
18046 - XTENSA_OPCODE_IS_BRANCH,
18047 - Opcode_bbsi_encode_fns, 0, 0 },
18048 - { "bgeui", 42 /* xt_iclass_bsi8u */,
18049 - XTENSA_OPCODE_IS_BRANCH,
18050 - Opcode_bgeui_encode_fns, 0, 0 },
18051 - { "bltui", 42 /* xt_iclass_bsi8u */,
18052 - XTENSA_OPCODE_IS_BRANCH,
18053 - Opcode_bltui_encode_fns, 0, 0 },
18054 - { "beq", 43 /* xt_iclass_bst8 */,
18055 - XTENSA_OPCODE_IS_BRANCH,
18056 - Opcode_beq_encode_fns, 0, 0 },
18057 - { "bne", 43 /* xt_iclass_bst8 */,
18058 - XTENSA_OPCODE_IS_BRANCH,
18059 - Opcode_bne_encode_fns, 0, 0 },
18060 - { "bge", 43 /* xt_iclass_bst8 */,
18061 - XTENSA_OPCODE_IS_BRANCH,
18062 - Opcode_bge_encode_fns, 0, 0 },
18063 - { "blt", 43 /* xt_iclass_bst8 */,
18064 - XTENSA_OPCODE_IS_BRANCH,
18065 - Opcode_blt_encode_fns, 0, 0 },
18066 - { "bgeu", 43 /* xt_iclass_bst8 */,
18067 - XTENSA_OPCODE_IS_BRANCH,
18068 - Opcode_bgeu_encode_fns, 0, 0 },
18069 - { "bltu", 43 /* xt_iclass_bst8 */,
18070 - XTENSA_OPCODE_IS_BRANCH,
18071 - Opcode_bltu_encode_fns, 0, 0 },
18072 - { "bany", 43 /* xt_iclass_bst8 */,
18073 - XTENSA_OPCODE_IS_BRANCH,
18074 - Opcode_bany_encode_fns, 0, 0 },
18075 - { "bnone", 43 /* xt_iclass_bst8 */,
18076 - XTENSA_OPCODE_IS_BRANCH,
18077 - Opcode_bnone_encode_fns, 0, 0 },
18078 - { "ball", 43 /* xt_iclass_bst8 */,
18079 - XTENSA_OPCODE_IS_BRANCH,
18080 - Opcode_ball_encode_fns, 0, 0 },
18081 - { "bnall", 43 /* xt_iclass_bst8 */,
18082 - XTENSA_OPCODE_IS_BRANCH,
18083 - Opcode_bnall_encode_fns, 0, 0 },
18084 - { "bbc", 43 /* xt_iclass_bst8 */,
18085 - XTENSA_OPCODE_IS_BRANCH,
18086 - Opcode_bbc_encode_fns, 0, 0 },
18087 - { "bbs", 43 /* xt_iclass_bst8 */,
18088 - XTENSA_OPCODE_IS_BRANCH,
18089 - Opcode_bbs_encode_fns, 0, 0 },
18090 - { "beqz", 44 /* xt_iclass_bsz12 */,
18091 - XTENSA_OPCODE_IS_BRANCH,
18092 - Opcode_beqz_encode_fns, 0, 0 },
18093 - { "bnez", 44 /* xt_iclass_bsz12 */,
18094 - XTENSA_OPCODE_IS_BRANCH,
18095 - Opcode_bnez_encode_fns, 0, 0 },
18096 - { "bgez", 44 /* xt_iclass_bsz12 */,
18097 - XTENSA_OPCODE_IS_BRANCH,
18098 - Opcode_bgez_encode_fns, 0, 0 },
18099 - { "bltz", 44 /* xt_iclass_bsz12 */,
18100 - XTENSA_OPCODE_IS_BRANCH,
18101 - Opcode_bltz_encode_fns, 0, 0 },
18102 - { "call0", 45 /* xt_iclass_call0 */,
18103 - XTENSA_OPCODE_IS_CALL,
18104 - Opcode_call0_encode_fns, 0, 0 },
18105 - { "callx0", 46 /* xt_iclass_callx0 */,
18106 - XTENSA_OPCODE_IS_CALL,
18107 - Opcode_callx0_encode_fns, 0, 0 },
18108 - { "extui", 47 /* xt_iclass_exti */,
18110 - Opcode_extui_encode_fns, 0, 0 },
18111 - { "ill", 48 /* xt_iclass_ill */,
18113 - Opcode_ill_encode_fns, 0, 0 },
18114 - { "j", 49 /* xt_iclass_jump */,
18115 - XTENSA_OPCODE_IS_JUMP,
18116 - Opcode_j_encode_fns, 0, 0 },
18117 - { "jx", 50 /* xt_iclass_jumpx */,
18118 - XTENSA_OPCODE_IS_JUMP,
18119 - Opcode_jx_encode_fns, 0, 0 },
18120 - { "l16ui", 51 /* xt_iclass_l16ui */,
18122 - Opcode_l16ui_encode_fns, 0, 0 },
18123 - { "l16si", 52 /* xt_iclass_l16si */,
18125 - Opcode_l16si_encode_fns, 0, 0 },
18126 - { "l32i", 53 /* xt_iclass_l32i */,
18128 - Opcode_l32i_encode_fns, 0, 0 },
18129 - { "l32r", 54 /* xt_iclass_l32r */,
18131 - Opcode_l32r_encode_fns, 0, 0 },
18132 - { "l8ui", 55 /* xt_iclass_l8i */,
18134 - Opcode_l8ui_encode_fns, 0, 0 },
18135 - { "loop", 56 /* xt_iclass_loop */,
18136 - XTENSA_OPCODE_IS_LOOP,
18137 - Opcode_loop_encode_fns, 0, 0 },
18138 - { "loopnez", 57 /* xt_iclass_loopz */,
18139 - XTENSA_OPCODE_IS_LOOP,
18140 - Opcode_loopnez_encode_fns, 0, 0 },
18141 - { "loopgtz", 57 /* xt_iclass_loopz */,
18142 - XTENSA_OPCODE_IS_LOOP,
18143 - Opcode_loopgtz_encode_fns, 0, 0 },
18144 - { "movi", 58 /* xt_iclass_movi */,
18146 - Opcode_movi_encode_fns, 0, 0 },
18147 - { "moveqz", 59 /* xt_iclass_movz */,
18149 - Opcode_moveqz_encode_fns, 0, 0 },
18150 - { "movnez", 59 /* xt_iclass_movz */,
18152 - Opcode_movnez_encode_fns, 0, 0 },
18153 - { "movltz", 59 /* xt_iclass_movz */,
18155 - Opcode_movltz_encode_fns, 0, 0 },
18156 - { "movgez", 59 /* xt_iclass_movz */,
18158 - Opcode_movgez_encode_fns, 0, 0 },
18159 - { "neg", 60 /* xt_iclass_neg */,
18161 - Opcode_neg_encode_fns, 0, 0 },
18162 - { "abs", 60 /* xt_iclass_neg */,
18164 - Opcode_abs_encode_fns, 0, 0 },
18165 - { "nop", 61 /* xt_iclass_nop */,
18167 - Opcode_nop_encode_fns, 0, 0 },
18168 - { "ret", 62 /* xt_iclass_return */,
18169 - XTENSA_OPCODE_IS_JUMP,
18170 - Opcode_ret_encode_fns, 0, 0 },
18171 - { "s16i", 63 /* xt_iclass_s16i */,
18173 - Opcode_s16i_encode_fns, 0, 0 },
18174 - { "s32i", 64 /* xt_iclass_s32i */,
18176 - Opcode_s32i_encode_fns, 0, 0 },
18177 - { "s8i", 65 /* xt_iclass_s8i */,
18179 - Opcode_s8i_encode_fns, 0, 0 },
18180 - { "ssr", 66 /* xt_iclass_sar */,
18182 - Opcode_ssr_encode_fns, 0, 0 },
18183 - { "ssl", 66 /* xt_iclass_sar */,
18185 - Opcode_ssl_encode_fns, 0, 0 },
18186 - { "ssa8l", 66 /* xt_iclass_sar */,
18188 - Opcode_ssa8l_encode_fns, 0, 0 },
18189 - { "ssa8b", 66 /* xt_iclass_sar */,
18191 - Opcode_ssa8b_encode_fns, 0, 0 },
18192 - { "ssai", 67 /* xt_iclass_sari */,
18194 - Opcode_ssai_encode_fns, 0, 0 },
18195 - { "sll", 68 /* xt_iclass_shifts */,
18197 - Opcode_sll_encode_fns, 0, 0 },
18198 - { "src", 69 /* xt_iclass_shiftst */,
18200 - Opcode_src_encode_fns, 0, 0 },
18201 - { "srl", 70 /* xt_iclass_shiftt */,
18203 - Opcode_srl_encode_fns, 0, 0 },
18204 - { "sra", 70 /* xt_iclass_shiftt */,
18206 - Opcode_sra_encode_fns, 0, 0 },
18207 - { "slli", 71 /* xt_iclass_slli */,
18209 - Opcode_slli_encode_fns, 0, 0 },
18210 - { "srai", 72 /* xt_iclass_srai */,
18212 - Opcode_srai_encode_fns, 0, 0 },
18213 - { "srli", 73 /* xt_iclass_srli */,
18215 - Opcode_srli_encode_fns, 0, 0 },
18216 - { "memw", 74 /* xt_iclass_memw */,
18218 - Opcode_memw_encode_fns, 0, 0 },
18219 - { "extw", 75 /* xt_iclass_extw */,
18221 - Opcode_extw_encode_fns, 0, 0 },
18222 - { "isync", 76 /* xt_iclass_isync */,
18224 - Opcode_isync_encode_fns, 0, 0 },
18225 - { "rsync", 77 /* xt_iclass_sync */,
18227 - Opcode_rsync_encode_fns, 0, 0 },
18228 - { "esync", 77 /* xt_iclass_sync */,
18230 - Opcode_esync_encode_fns, 0, 0 },
18231 - { "dsync", 77 /* xt_iclass_sync */,
18233 - Opcode_dsync_encode_fns, 0, 0 },
18234 - { "rsil", 78 /* xt_iclass_rsil */,
18236 - Opcode_rsil_encode_fns, 0, 0 },
18237 - { "rsr.lend", 79 /* xt_iclass_rsr.lend */,
18239 - Opcode_rsr_lend_encode_fns, 0, 0 },
18240 - { "wsr.lend", 80 /* xt_iclass_wsr.lend */,
18242 - Opcode_wsr_lend_encode_fns, 0, 0 },
18243 - { "xsr.lend", 81 /* xt_iclass_xsr.lend */,
18245 - Opcode_xsr_lend_encode_fns, 0, 0 },
18246 - { "rsr.lcount", 82 /* xt_iclass_rsr.lcount */,
18248 - Opcode_rsr_lcount_encode_fns, 0, 0 },
18249 - { "wsr.lcount", 83 /* xt_iclass_wsr.lcount */,
18251 - Opcode_wsr_lcount_encode_fns, 0, 0 },
18252 - { "xsr.lcount", 84 /* xt_iclass_xsr.lcount */,
18254 - Opcode_xsr_lcount_encode_fns, 0, 0 },
18255 - { "rsr.lbeg", 85 /* xt_iclass_rsr.lbeg */,
18257 - Opcode_rsr_lbeg_encode_fns, 0, 0 },
18258 - { "wsr.lbeg", 86 /* xt_iclass_wsr.lbeg */,
18260 - Opcode_wsr_lbeg_encode_fns, 0, 0 },
18261 - { "xsr.lbeg", 87 /* xt_iclass_xsr.lbeg */,
18263 - Opcode_xsr_lbeg_encode_fns, 0, 0 },
18264 - { "rsr.sar", 88 /* xt_iclass_rsr.sar */,
18266 - Opcode_rsr_sar_encode_fns, 0, 0 },
18267 - { "wsr.sar", 89 /* xt_iclass_wsr.sar */,
18269 - Opcode_wsr_sar_encode_fns, 0, 0 },
18270 - { "xsr.sar", 90 /* xt_iclass_xsr.sar */,
18272 - Opcode_xsr_sar_encode_fns, 0, 0 },
18273 - { "rsr.litbase", 91 /* xt_iclass_rsr.litbase */,
18275 - Opcode_rsr_litbase_encode_fns, 0, 0 },
18276 - { "wsr.litbase", 92 /* xt_iclass_wsr.litbase */,
18278 - Opcode_wsr_litbase_encode_fns, 0, 0 },
18279 - { "xsr.litbase", 93 /* xt_iclass_xsr.litbase */,
18281 - Opcode_xsr_litbase_encode_fns, 0, 0 },
18282 - { "rsr.176", 94 /* xt_iclass_rsr.176 */,
18284 - Opcode_rsr_176_encode_fns, 0, 0 },
18285 - { "rsr.208", 95 /* xt_iclass_rsr.208 */,
18287 - Opcode_rsr_208_encode_fns, 0, 0 },
18288 - { "rsr.ps", 96 /* xt_iclass_rsr.ps */,
18290 - Opcode_rsr_ps_encode_fns, 0, 0 },
18291 - { "wsr.ps", 97 /* xt_iclass_wsr.ps */,
18293 - Opcode_wsr_ps_encode_fns, 0, 0 },
18294 - { "xsr.ps", 98 /* xt_iclass_xsr.ps */,
18296 - Opcode_xsr_ps_encode_fns, 0, 0 },
18297 - { "rsr.epc1", 99 /* xt_iclass_rsr.epc1 */,
18299 - Opcode_rsr_epc1_encode_fns, 0, 0 },
18300 - { "wsr.epc1", 100 /* xt_iclass_wsr.epc1 */,
18302 - Opcode_wsr_epc1_encode_fns, 0, 0 },
18303 - { "xsr.epc1", 101 /* xt_iclass_xsr.epc1 */,
18305 - Opcode_xsr_epc1_encode_fns, 0, 0 },
18306 - { "rsr.excsave1", 102 /* xt_iclass_rsr.excsave1 */,
18308 - Opcode_rsr_excsave1_encode_fns, 0, 0 },
18309 - { "wsr.excsave1", 103 /* xt_iclass_wsr.excsave1 */,
18311 - Opcode_wsr_excsave1_encode_fns, 0, 0 },
18312 - { "xsr.excsave1", 104 /* xt_iclass_xsr.excsave1 */,
18314 - Opcode_xsr_excsave1_encode_fns, 0, 0 },
18315 - { "rsr.epc2", 105 /* xt_iclass_rsr.epc2 */,
18317 - Opcode_rsr_epc2_encode_fns, 0, 0 },
18318 - { "wsr.epc2", 106 /* xt_iclass_wsr.epc2 */,
18320 - Opcode_wsr_epc2_encode_fns, 0, 0 },
18321 - { "xsr.epc2", 107 /* xt_iclass_xsr.epc2 */,
18323 - Opcode_xsr_epc2_encode_fns, 0, 0 },
18324 - { "rsr.excsave2", 108 /* xt_iclass_rsr.excsave2 */,
18326 - Opcode_rsr_excsave2_encode_fns, 0, 0 },
18327 - { "wsr.excsave2", 109 /* xt_iclass_wsr.excsave2 */,
18329 - Opcode_wsr_excsave2_encode_fns, 0, 0 },
18330 - { "xsr.excsave2", 110 /* xt_iclass_xsr.excsave2 */,
18332 - Opcode_xsr_excsave2_encode_fns, 0, 0 },
18333 - { "rsr.epc3", 111 /* xt_iclass_rsr.epc3 */,
18335 - Opcode_rsr_epc3_encode_fns, 0, 0 },
18336 - { "wsr.epc3", 112 /* xt_iclass_wsr.epc3 */,
18338 - Opcode_wsr_epc3_encode_fns, 0, 0 },
18339 - { "xsr.epc3", 113 /* xt_iclass_xsr.epc3 */,
18341 - Opcode_xsr_epc3_encode_fns, 0, 0 },
18342 - { "rsr.excsave3", 114 /* xt_iclass_rsr.excsave3 */,
18344 - Opcode_rsr_excsave3_encode_fns, 0, 0 },
18345 - { "wsr.excsave3", 115 /* xt_iclass_wsr.excsave3 */,
18347 - Opcode_wsr_excsave3_encode_fns, 0, 0 },
18348 - { "xsr.excsave3", 116 /* xt_iclass_xsr.excsave3 */,
18350 - Opcode_xsr_excsave3_encode_fns, 0, 0 },
18351 - { "rsr.epc4", 117 /* xt_iclass_rsr.epc4 */,
18353 - Opcode_rsr_epc4_encode_fns, 0, 0 },
18354 - { "wsr.epc4", 118 /* xt_iclass_wsr.epc4 */,
18356 - Opcode_wsr_epc4_encode_fns, 0, 0 },
18357 - { "xsr.epc4", 119 /* xt_iclass_xsr.epc4 */,
18359 - Opcode_xsr_epc4_encode_fns, 0, 0 },
18360 - { "rsr.excsave4", 120 /* xt_iclass_rsr.excsave4 */,
18362 - Opcode_rsr_excsave4_encode_fns, 0, 0 },
18363 - { "wsr.excsave4", 121 /* xt_iclass_wsr.excsave4 */,
18365 - Opcode_wsr_excsave4_encode_fns, 0, 0 },
18366 - { "xsr.excsave4", 122 /* xt_iclass_xsr.excsave4 */,
18368 - Opcode_xsr_excsave4_encode_fns, 0, 0 },
18369 - { "rsr.epc5", 123 /* xt_iclass_rsr.epc5 */,
18371 - Opcode_rsr_epc5_encode_fns, 0, 0 },
18372 - { "wsr.epc5", 124 /* xt_iclass_wsr.epc5 */,
18374 - Opcode_wsr_epc5_encode_fns, 0, 0 },
18375 - { "xsr.epc5", 125 /* xt_iclass_xsr.epc5 */,
18377 - Opcode_xsr_epc5_encode_fns, 0, 0 },
18378 - { "rsr.excsave5", 126 /* xt_iclass_rsr.excsave5 */,
18380 - Opcode_rsr_excsave5_encode_fns, 0, 0 },
18381 - { "wsr.excsave5", 127 /* xt_iclass_wsr.excsave5 */,
18383 - Opcode_wsr_excsave5_encode_fns, 0, 0 },
18384 - { "xsr.excsave5", 128 /* xt_iclass_xsr.excsave5 */,
18386 - Opcode_xsr_excsave5_encode_fns, 0, 0 },
18387 - { "rsr.epc6", 129 /* xt_iclass_rsr.epc6 */,
18389 - Opcode_rsr_epc6_encode_fns, 0, 0 },
18390 - { "wsr.epc6", 130 /* xt_iclass_wsr.epc6 */,
18392 - Opcode_wsr_epc6_encode_fns, 0, 0 },
18393 - { "xsr.epc6", 131 /* xt_iclass_xsr.epc6 */,
18395 - Opcode_xsr_epc6_encode_fns, 0, 0 },
18396 - { "rsr.excsave6", 132 /* xt_iclass_rsr.excsave6 */,
18398 - Opcode_rsr_excsave6_encode_fns, 0, 0 },
18399 - { "wsr.excsave6", 133 /* xt_iclass_wsr.excsave6 */,
18401 - Opcode_wsr_excsave6_encode_fns, 0, 0 },
18402 - { "xsr.excsave6", 134 /* xt_iclass_xsr.excsave6 */,
18404 - Opcode_xsr_excsave6_encode_fns, 0, 0 },
18405 - { "rsr.epc7", 135 /* xt_iclass_rsr.epc7 */,
18407 - Opcode_rsr_epc7_encode_fns, 0, 0 },
18408 - { "wsr.epc7", 136 /* xt_iclass_wsr.epc7 */,
18410 - Opcode_wsr_epc7_encode_fns, 0, 0 },
18411 - { "xsr.epc7", 137 /* xt_iclass_xsr.epc7 */,
18413 - Opcode_xsr_epc7_encode_fns, 0, 0 },
18414 - { "rsr.excsave7", 138 /* xt_iclass_rsr.excsave7 */,
18416 - Opcode_rsr_excsave7_encode_fns, 0, 0 },
18417 - { "wsr.excsave7", 139 /* xt_iclass_wsr.excsave7 */,
18419 - Opcode_wsr_excsave7_encode_fns, 0, 0 },
18420 - { "xsr.excsave7", 140 /* xt_iclass_xsr.excsave7 */,
18422 - Opcode_xsr_excsave7_encode_fns, 0, 0 },
18423 - { "rsr.eps2", 141 /* xt_iclass_rsr.eps2 */,
18425 - Opcode_rsr_eps2_encode_fns, 0, 0 },
18426 - { "wsr.eps2", 142 /* xt_iclass_wsr.eps2 */,
18428 - Opcode_wsr_eps2_encode_fns, 0, 0 },
18429 - { "xsr.eps2", 143 /* xt_iclass_xsr.eps2 */,
18431 - Opcode_xsr_eps2_encode_fns, 0, 0 },
18432 - { "rsr.eps3", 144 /* xt_iclass_rsr.eps3 */,
18434 - Opcode_rsr_eps3_encode_fns, 0, 0 },
18435 - { "wsr.eps3", 145 /* xt_iclass_wsr.eps3 */,
18437 - Opcode_wsr_eps3_encode_fns, 0, 0 },
18438 - { "xsr.eps3", 146 /* xt_iclass_xsr.eps3 */,
18440 - Opcode_xsr_eps3_encode_fns, 0, 0 },
18441 - { "rsr.eps4", 147 /* xt_iclass_rsr.eps4 */,
18443 - Opcode_rsr_eps4_encode_fns, 0, 0 },
18444 - { "wsr.eps4", 148 /* xt_iclass_wsr.eps4 */,
18446 - Opcode_wsr_eps4_encode_fns, 0, 0 },
18447 - { "xsr.eps4", 149 /* xt_iclass_xsr.eps4 */,
18449 - Opcode_xsr_eps4_encode_fns, 0, 0 },
18450 - { "rsr.eps5", 150 /* xt_iclass_rsr.eps5 */,
18452 - Opcode_rsr_eps5_encode_fns, 0, 0 },
18453 - { "wsr.eps5", 151 /* xt_iclass_wsr.eps5 */,
18455 - Opcode_wsr_eps5_encode_fns, 0, 0 },
18456 - { "xsr.eps5", 152 /* xt_iclass_xsr.eps5 */,
18458 - Opcode_xsr_eps5_encode_fns, 0, 0 },
18459 - { "rsr.eps6", 153 /* xt_iclass_rsr.eps6 */,
18461 - Opcode_rsr_eps6_encode_fns, 0, 0 },
18462 - { "wsr.eps6", 154 /* xt_iclass_wsr.eps6 */,
18464 - Opcode_wsr_eps6_encode_fns, 0, 0 },
18465 - { "xsr.eps6", 155 /* xt_iclass_xsr.eps6 */,
18467 - Opcode_xsr_eps6_encode_fns, 0, 0 },
18468 - { "rsr.eps7", 156 /* xt_iclass_rsr.eps7 */,
18470 - Opcode_rsr_eps7_encode_fns, 0, 0 },
18471 - { "wsr.eps7", 157 /* xt_iclass_wsr.eps7 */,
18473 - Opcode_wsr_eps7_encode_fns, 0, 0 },
18474 - { "xsr.eps7", 158 /* xt_iclass_xsr.eps7 */,
18476 - Opcode_xsr_eps7_encode_fns, 0, 0 },
18477 - { "rsr.excvaddr", 159 /* xt_iclass_rsr.excvaddr */,
18479 - Opcode_rsr_excvaddr_encode_fns, 0, 0 },
18480 - { "wsr.excvaddr", 160 /* xt_iclass_wsr.excvaddr */,
18482 - Opcode_wsr_excvaddr_encode_fns, 0, 0 },
18483 - { "xsr.excvaddr", 161 /* xt_iclass_xsr.excvaddr */,
18485 - Opcode_xsr_excvaddr_encode_fns, 0, 0 },
18486 - { "rsr.depc", 162 /* xt_iclass_rsr.depc */,
18488 - Opcode_rsr_depc_encode_fns, 0, 0 },
18489 - { "wsr.depc", 163 /* xt_iclass_wsr.depc */,
18491 - Opcode_wsr_depc_encode_fns, 0, 0 },
18492 - { "xsr.depc", 164 /* xt_iclass_xsr.depc */,
18494 - Opcode_xsr_depc_encode_fns, 0, 0 },
18495 - { "rsr.exccause", 165 /* xt_iclass_rsr.exccause */,
18497 - Opcode_rsr_exccause_encode_fns, 0, 0 },
18498 - { "wsr.exccause", 166 /* xt_iclass_wsr.exccause */,
18500 - Opcode_wsr_exccause_encode_fns, 0, 0 },
18501 - { "xsr.exccause", 167 /* xt_iclass_xsr.exccause */,
18503 - Opcode_xsr_exccause_encode_fns, 0, 0 },
18504 - { "rsr.misc0", 168 /* xt_iclass_rsr.misc0 */,
18506 - Opcode_rsr_misc0_encode_fns, 0, 0 },
18507 - { "wsr.misc0", 169 /* xt_iclass_wsr.misc0 */,
18509 - Opcode_wsr_misc0_encode_fns, 0, 0 },
18510 - { "xsr.misc0", 170 /* xt_iclass_xsr.misc0 */,
18512 - Opcode_xsr_misc0_encode_fns, 0, 0 },
18513 - { "rsr.misc1", 171 /* xt_iclass_rsr.misc1 */,
18515 - Opcode_rsr_misc1_encode_fns, 0, 0 },
18516 - { "wsr.misc1", 172 /* xt_iclass_wsr.misc1 */,
18518 - Opcode_wsr_misc1_encode_fns, 0, 0 },
18519 - { "xsr.misc1", 173 /* xt_iclass_xsr.misc1 */,
18521 - Opcode_xsr_misc1_encode_fns, 0, 0 },
18522 - { "rsr.misc2", 174 /* xt_iclass_rsr.misc2 */,
18524 - Opcode_rsr_misc2_encode_fns, 0, 0 },
18525 - { "wsr.misc2", 175 /* xt_iclass_wsr.misc2 */,
18527 - Opcode_wsr_misc2_encode_fns, 0, 0 },
18528 - { "xsr.misc2", 176 /* xt_iclass_xsr.misc2 */,
18530 - Opcode_xsr_misc2_encode_fns, 0, 0 },
18531 - { "rsr.misc3", 177 /* xt_iclass_rsr.misc3 */,
18533 - Opcode_rsr_misc3_encode_fns, 0, 0 },
18534 - { "wsr.misc3", 178 /* xt_iclass_wsr.misc3 */,
18536 - Opcode_wsr_misc3_encode_fns, 0, 0 },
18537 - { "xsr.misc3", 179 /* xt_iclass_xsr.misc3 */,
18539 - Opcode_xsr_misc3_encode_fns, 0, 0 },
18540 - { "rsr.prid", 180 /* xt_iclass_rsr.prid */,
18542 - Opcode_rsr_prid_encode_fns, 0, 0 },
18543 - { "rsr.vecbase", 181 /* xt_iclass_rsr.vecbase */,
18545 - Opcode_rsr_vecbase_encode_fns, 0, 0 },
18546 - { "wsr.vecbase", 182 /* xt_iclass_wsr.vecbase */,
18548 - Opcode_wsr_vecbase_encode_fns, 0, 0 },
18549 - { "xsr.vecbase", 183 /* xt_iclass_xsr.vecbase */,
18551 - Opcode_xsr_vecbase_encode_fns, 0, 0 },
18552 - { "mul.aa.ll", 184 /* xt_iclass_mac16_aa */,
18554 - Opcode_mul_aa_ll_encode_fns, 0, 0 },
18555 - { "mul.aa.hl", 184 /* xt_iclass_mac16_aa */,
18557 - Opcode_mul_aa_hl_encode_fns, 0, 0 },
18558 - { "mul.aa.lh", 184 /* xt_iclass_mac16_aa */,
18560 - Opcode_mul_aa_lh_encode_fns, 0, 0 },
18561 - { "mul.aa.hh", 184 /* xt_iclass_mac16_aa */,
18563 - Opcode_mul_aa_hh_encode_fns, 0, 0 },
18564 - { "umul.aa.ll", 184 /* xt_iclass_mac16_aa */,
18566 - Opcode_umul_aa_ll_encode_fns, 0, 0 },
18567 - { "umul.aa.hl", 184 /* xt_iclass_mac16_aa */,
18569 - Opcode_umul_aa_hl_encode_fns, 0, 0 },
18570 - { "umul.aa.lh", 184 /* xt_iclass_mac16_aa */,
18572 - Opcode_umul_aa_lh_encode_fns, 0, 0 },
18573 - { "umul.aa.hh", 184 /* xt_iclass_mac16_aa */,
18575 - Opcode_umul_aa_hh_encode_fns, 0, 0 },
18576 - { "mul.ad.ll", 185 /* xt_iclass_mac16_ad */,
18578 - Opcode_mul_ad_ll_encode_fns, 0, 0 },
18579 - { "mul.ad.hl", 185 /* xt_iclass_mac16_ad */,
18581 - Opcode_mul_ad_hl_encode_fns, 0, 0 },
18582 - { "mul.ad.lh", 185 /* xt_iclass_mac16_ad */,
18584 - Opcode_mul_ad_lh_encode_fns, 0, 0 },
18585 - { "mul.ad.hh", 185 /* xt_iclass_mac16_ad */,
18587 - Opcode_mul_ad_hh_encode_fns, 0, 0 },
18588 - { "mul.da.ll", 186 /* xt_iclass_mac16_da */,
18590 - Opcode_mul_da_ll_encode_fns, 0, 0 },
18591 - { "mul.da.hl", 186 /* xt_iclass_mac16_da */,
18593 - Opcode_mul_da_hl_encode_fns, 0, 0 },
18594 - { "mul.da.lh", 186 /* xt_iclass_mac16_da */,
18596 - Opcode_mul_da_lh_encode_fns, 0, 0 },
18597 - { "mul.da.hh", 186 /* xt_iclass_mac16_da */,
18599 - Opcode_mul_da_hh_encode_fns, 0, 0 },
18600 - { "mul.dd.ll", 187 /* xt_iclass_mac16_dd */,
18602 - Opcode_mul_dd_ll_encode_fns, 0, 0 },
18603 - { "mul.dd.hl", 187 /* xt_iclass_mac16_dd */,
18605 - Opcode_mul_dd_hl_encode_fns, 0, 0 },
18606 - { "mul.dd.lh", 187 /* xt_iclass_mac16_dd */,
18608 - Opcode_mul_dd_lh_encode_fns, 0, 0 },
18609 - { "mul.dd.hh", 187 /* xt_iclass_mac16_dd */,
18611 - Opcode_mul_dd_hh_encode_fns, 0, 0 },
18612 - { "mula.aa.ll", 188 /* xt_iclass_mac16a_aa */,
18614 - Opcode_mula_aa_ll_encode_fns, 0, 0 },
18615 - { "mula.aa.hl", 188 /* xt_iclass_mac16a_aa */,
18617 - Opcode_mula_aa_hl_encode_fns, 0, 0 },
18618 - { "mula.aa.lh", 188 /* xt_iclass_mac16a_aa */,
18620 - Opcode_mula_aa_lh_encode_fns, 0, 0 },
18621 - { "mula.aa.hh", 188 /* xt_iclass_mac16a_aa */,
18623 - Opcode_mula_aa_hh_encode_fns, 0, 0 },
18624 - { "muls.aa.ll", 188 /* xt_iclass_mac16a_aa */,
18626 - Opcode_muls_aa_ll_encode_fns, 0, 0 },
18627 - { "muls.aa.hl", 188 /* xt_iclass_mac16a_aa */,
18629 - Opcode_muls_aa_hl_encode_fns, 0, 0 },
18630 - { "muls.aa.lh", 188 /* xt_iclass_mac16a_aa */,
18632 - Opcode_muls_aa_lh_encode_fns, 0, 0 },
18633 - { "muls.aa.hh", 188 /* xt_iclass_mac16a_aa */,
18635 - Opcode_muls_aa_hh_encode_fns, 0, 0 },
18636 - { "mula.ad.ll", 189 /* xt_iclass_mac16a_ad */,
18638 - Opcode_mula_ad_ll_encode_fns, 0, 0 },
18639 - { "mula.ad.hl", 189 /* xt_iclass_mac16a_ad */,
18641 - Opcode_mula_ad_hl_encode_fns, 0, 0 },
18642 - { "mula.ad.lh", 189 /* xt_iclass_mac16a_ad */,
18644 - Opcode_mula_ad_lh_encode_fns, 0, 0 },
18645 - { "mula.ad.hh", 189 /* xt_iclass_mac16a_ad */,
18647 - Opcode_mula_ad_hh_encode_fns, 0, 0 },
18648 - { "muls.ad.ll", 189 /* xt_iclass_mac16a_ad */,
18650 - Opcode_muls_ad_ll_encode_fns, 0, 0 },
18651 - { "muls.ad.hl", 189 /* xt_iclass_mac16a_ad */,
18653 - Opcode_muls_ad_hl_encode_fns, 0, 0 },
18654 - { "muls.ad.lh", 189 /* xt_iclass_mac16a_ad */,
18656 - Opcode_muls_ad_lh_encode_fns, 0, 0 },
18657 - { "muls.ad.hh", 189 /* xt_iclass_mac16a_ad */,
18659 - Opcode_muls_ad_hh_encode_fns, 0, 0 },
18660 - { "mula.da.ll", 190 /* xt_iclass_mac16a_da */,
18662 - Opcode_mula_da_ll_encode_fns, 0, 0 },
18663 - { "mula.da.hl", 190 /* xt_iclass_mac16a_da */,
18665 - Opcode_mula_da_hl_encode_fns, 0, 0 },
18666 - { "mula.da.lh", 190 /* xt_iclass_mac16a_da */,
18668 - Opcode_mula_da_lh_encode_fns, 0, 0 },
18669 - { "mula.da.hh", 190 /* xt_iclass_mac16a_da */,
18671 - Opcode_mula_da_hh_encode_fns, 0, 0 },
18672 - { "muls.da.ll", 190 /* xt_iclass_mac16a_da */,
18674 - Opcode_muls_da_ll_encode_fns, 0, 0 },
18675 - { "muls.da.hl", 190 /* xt_iclass_mac16a_da */,
18677 - Opcode_muls_da_hl_encode_fns, 0, 0 },
18678 - { "muls.da.lh", 190 /* xt_iclass_mac16a_da */,
18680 - Opcode_muls_da_lh_encode_fns, 0, 0 },
18681 - { "muls.da.hh", 190 /* xt_iclass_mac16a_da */,
18683 - Opcode_muls_da_hh_encode_fns, 0, 0 },
18684 - { "mula.dd.ll", 191 /* xt_iclass_mac16a_dd */,
18686 - Opcode_mula_dd_ll_encode_fns, 0, 0 },
18687 - { "mula.dd.hl", 191 /* xt_iclass_mac16a_dd */,
18689 - Opcode_mula_dd_hl_encode_fns, 0, 0 },
18690 - { "mula.dd.lh", 191 /* xt_iclass_mac16a_dd */,
18692 - Opcode_mula_dd_lh_encode_fns, 0, 0 },
18693 - { "mula.dd.hh", 191 /* xt_iclass_mac16a_dd */,
18695 - Opcode_mula_dd_hh_encode_fns, 0, 0 },
18696 - { "muls.dd.ll", 191 /* xt_iclass_mac16a_dd */,
18698 - Opcode_muls_dd_ll_encode_fns, 0, 0 },
18699 - { "muls.dd.hl", 191 /* xt_iclass_mac16a_dd */,
18701 - Opcode_muls_dd_hl_encode_fns, 0, 0 },
18702 - { "muls.dd.lh", 191 /* xt_iclass_mac16a_dd */,
18704 - Opcode_muls_dd_lh_encode_fns, 0, 0 },
18705 - { "muls.dd.hh", 191 /* xt_iclass_mac16a_dd */,
18707 - Opcode_muls_dd_hh_encode_fns, 0, 0 },
18708 - { "mula.da.ll.lddec", 192 /* xt_iclass_mac16al_da */,
18710 - Opcode_mula_da_ll_lddec_encode_fns, 0, 0 },
18711 - { "mula.da.ll.ldinc", 192 /* xt_iclass_mac16al_da */,
18713 - Opcode_mula_da_ll_ldinc_encode_fns, 0, 0 },
18714 - { "mula.da.hl.lddec", 192 /* xt_iclass_mac16al_da */,
18716 - Opcode_mula_da_hl_lddec_encode_fns, 0, 0 },
18717 - { "mula.da.hl.ldinc", 192 /* xt_iclass_mac16al_da */,
18719 - Opcode_mula_da_hl_ldinc_encode_fns, 0, 0 },
18720 - { "mula.da.lh.lddec", 192 /* xt_iclass_mac16al_da */,
18722 - Opcode_mula_da_lh_lddec_encode_fns, 0, 0 },
18723 - { "mula.da.lh.ldinc", 192 /* xt_iclass_mac16al_da */,
18725 - Opcode_mula_da_lh_ldinc_encode_fns, 0, 0 },
18726 - { "mula.da.hh.lddec", 192 /* xt_iclass_mac16al_da */,
18728 - Opcode_mula_da_hh_lddec_encode_fns, 0, 0 },
18729 - { "mula.da.hh.ldinc", 192 /* xt_iclass_mac16al_da */,
18731 - Opcode_mula_da_hh_ldinc_encode_fns, 0, 0 },
18732 - { "mula.dd.ll.lddec", 193 /* xt_iclass_mac16al_dd */,
18734 - Opcode_mula_dd_ll_lddec_encode_fns, 0, 0 },
18735 - { "mula.dd.ll.ldinc", 193 /* xt_iclass_mac16al_dd */,
18737 - Opcode_mula_dd_ll_ldinc_encode_fns, 0, 0 },
18738 - { "mula.dd.hl.lddec", 193 /* xt_iclass_mac16al_dd */,
18740 - Opcode_mula_dd_hl_lddec_encode_fns, 0, 0 },
18741 - { "mula.dd.hl.ldinc", 193 /* xt_iclass_mac16al_dd */,
18743 - Opcode_mula_dd_hl_ldinc_encode_fns, 0, 0 },
18744 - { "mula.dd.lh.lddec", 193 /* xt_iclass_mac16al_dd */,
18746 - Opcode_mula_dd_lh_lddec_encode_fns, 0, 0 },
18747 - { "mula.dd.lh.ldinc", 193 /* xt_iclass_mac16al_dd */,
18749 - Opcode_mula_dd_lh_ldinc_encode_fns, 0, 0 },
18750 - { "mula.dd.hh.lddec", 193 /* xt_iclass_mac16al_dd */,
18752 - Opcode_mula_dd_hh_lddec_encode_fns, 0, 0 },
18753 - { "mula.dd.hh.ldinc", 193 /* xt_iclass_mac16al_dd */,
18755 - Opcode_mula_dd_hh_ldinc_encode_fns, 0, 0 },
18756 - { "lddec", 194 /* xt_iclass_mac16_l */,
18758 - Opcode_lddec_encode_fns, 0, 0 },
18759 - { "ldinc", 194 /* xt_iclass_mac16_l */,
18761 - Opcode_ldinc_encode_fns, 0, 0 },
18762 - { "mul16u", 195 /* xt_iclass_mul16 */,
18764 - Opcode_mul16u_encode_fns, 0, 0 },
18765 - { "mul16s", 195 /* xt_iclass_mul16 */,
18767 - Opcode_mul16s_encode_fns, 0, 0 },
18768 - { "rsr.m0", 196 /* xt_iclass_rsr.m0 */,
18770 - Opcode_rsr_m0_encode_fns, 0, 0 },
18771 - { "wsr.m0", 197 /* xt_iclass_wsr.m0 */,
18773 - Opcode_wsr_m0_encode_fns, 0, 0 },
18774 - { "xsr.m0", 198 /* xt_iclass_xsr.m0 */,
18776 - Opcode_xsr_m0_encode_fns, 0, 0 },
18777 - { "rsr.m1", 199 /* xt_iclass_rsr.m1 */,
18779 - Opcode_rsr_m1_encode_fns, 0, 0 },
18780 - { "wsr.m1", 200 /* xt_iclass_wsr.m1 */,
18782 - Opcode_wsr_m1_encode_fns, 0, 0 },
18783 - { "xsr.m1", 201 /* xt_iclass_xsr.m1 */,
18785 - Opcode_xsr_m1_encode_fns, 0, 0 },
18786 - { "rsr.m2", 202 /* xt_iclass_rsr.m2 */,
18788 - Opcode_rsr_m2_encode_fns, 0, 0 },
18789 - { "wsr.m2", 203 /* xt_iclass_wsr.m2 */,
18791 - Opcode_wsr_m2_encode_fns, 0, 0 },
18792 - { "xsr.m2", 204 /* xt_iclass_xsr.m2 */,
18794 - Opcode_xsr_m2_encode_fns, 0, 0 },
18795 - { "rsr.m3", 205 /* xt_iclass_rsr.m3 */,
18797 - Opcode_rsr_m3_encode_fns, 0, 0 },
18798 - { "wsr.m3", 206 /* xt_iclass_wsr.m3 */,
18800 - Opcode_wsr_m3_encode_fns, 0, 0 },
18801 - { "xsr.m3", 207 /* xt_iclass_xsr.m3 */,
18803 - Opcode_xsr_m3_encode_fns, 0, 0 },
18804 - { "rsr.acclo", 208 /* xt_iclass_rsr.acclo */,
18806 - Opcode_rsr_acclo_encode_fns, 0, 0 },
18807 - { "wsr.acclo", 209 /* xt_iclass_wsr.acclo */,
18809 - Opcode_wsr_acclo_encode_fns, 0, 0 },
18810 - { "xsr.acclo", 210 /* xt_iclass_xsr.acclo */,
18812 - Opcode_xsr_acclo_encode_fns, 0, 0 },
18813 - { "rsr.acchi", 211 /* xt_iclass_rsr.acchi */,
18815 - Opcode_rsr_acchi_encode_fns, 0, 0 },
18816 - { "wsr.acchi", 212 /* xt_iclass_wsr.acchi */,
18818 - Opcode_wsr_acchi_encode_fns, 0, 0 },
18819 - { "xsr.acchi", 213 /* xt_iclass_xsr.acchi */,
18821 - Opcode_xsr_acchi_encode_fns, 0, 0 },
18822 - { "rfi", 214 /* xt_iclass_rfi */,
18823 - XTENSA_OPCODE_IS_JUMP,
18824 - Opcode_rfi_encode_fns, 0, 0 },
18825 - { "waiti", 215 /* xt_iclass_wait */,
18827 - Opcode_waiti_encode_fns, 0, 0 },
18828 - { "rsr.interrupt", 216 /* xt_iclass_rsr.interrupt */,
18830 - Opcode_rsr_interrupt_encode_fns, 0, 0 },
18831 - { "wsr.intset", 217 /* xt_iclass_wsr.intset */,
18833 - Opcode_wsr_intset_encode_fns, 0, 0 },
18834 - { "wsr.intclear", 218 /* xt_iclass_wsr.intclear */,
18836 - Opcode_wsr_intclear_encode_fns, 0, 0 },
18837 - { "rsr.intenable", 219 /* xt_iclass_rsr.intenable */,
18839 - Opcode_rsr_intenable_encode_fns, 0, 0 },
18840 - { "wsr.intenable", 220 /* xt_iclass_wsr.intenable */,
18842 - Opcode_wsr_intenable_encode_fns, 0, 0 },
18843 - { "xsr.intenable", 221 /* xt_iclass_xsr.intenable */,
18845 - Opcode_xsr_intenable_encode_fns, 0, 0 },
18846 - { "break", 222 /* xt_iclass_break */,
18848 - Opcode_break_encode_fns, 0, 0 },
18849 - { "break.n", 223 /* xt_iclass_break.n */,
18851 - Opcode_break_n_encode_fns, 0, 0 },
18852 - { "rsr.dbreaka0", 224 /* xt_iclass_rsr.dbreaka0 */,
18854 - Opcode_rsr_dbreaka0_encode_fns, 0, 0 },
18855 - { "wsr.dbreaka0", 225 /* xt_iclass_wsr.dbreaka0 */,
18857 - Opcode_wsr_dbreaka0_encode_fns, 0, 0 },
18858 - { "xsr.dbreaka0", 226 /* xt_iclass_xsr.dbreaka0 */,
18860 - Opcode_xsr_dbreaka0_encode_fns, 0, 0 },
18861 - { "rsr.dbreakc0", 227 /* xt_iclass_rsr.dbreakc0 */,
18863 - Opcode_rsr_dbreakc0_encode_fns, 0, 0 },
18864 - { "wsr.dbreakc0", 228 /* xt_iclass_wsr.dbreakc0 */,
18866 - Opcode_wsr_dbreakc0_encode_fns, 0, 0 },
18867 - { "xsr.dbreakc0", 229 /* xt_iclass_xsr.dbreakc0 */,
18869 - Opcode_xsr_dbreakc0_encode_fns, 0, 0 },
18870 - { "rsr.dbreaka1", 230 /* xt_iclass_rsr.dbreaka1 */,
18872 - Opcode_rsr_dbreaka1_encode_fns, 0, 0 },
18873 - { "wsr.dbreaka1", 231 /* xt_iclass_wsr.dbreaka1 */,
18875 - Opcode_wsr_dbreaka1_encode_fns, 0, 0 },
18876 - { "xsr.dbreaka1", 232 /* xt_iclass_xsr.dbreaka1 */,
18878 - Opcode_xsr_dbreaka1_encode_fns, 0, 0 },
18879 - { "rsr.dbreakc1", 233 /* xt_iclass_rsr.dbreakc1 */,
18881 - Opcode_rsr_dbreakc1_encode_fns, 0, 0 },
18882 - { "wsr.dbreakc1", 234 /* xt_iclass_wsr.dbreakc1 */,
18884 - Opcode_wsr_dbreakc1_encode_fns, 0, 0 },
18885 - { "xsr.dbreakc1", 235 /* xt_iclass_xsr.dbreakc1 */,
18887 - Opcode_xsr_dbreakc1_encode_fns, 0, 0 },
18888 - { "rsr.ibreaka0", 236 /* xt_iclass_rsr.ibreaka0 */,
18890 - Opcode_rsr_ibreaka0_encode_fns, 0, 0 },
18891 - { "wsr.ibreaka0", 237 /* xt_iclass_wsr.ibreaka0 */,
18893 - Opcode_wsr_ibreaka0_encode_fns, 0, 0 },
18894 - { "xsr.ibreaka0", 238 /* xt_iclass_xsr.ibreaka0 */,
18896 - Opcode_xsr_ibreaka0_encode_fns, 0, 0 },
18897 - { "rsr.ibreaka1", 239 /* xt_iclass_rsr.ibreaka1 */,
18899 - Opcode_rsr_ibreaka1_encode_fns, 0, 0 },
18900 - { "wsr.ibreaka1", 240 /* xt_iclass_wsr.ibreaka1 */,
18902 - Opcode_wsr_ibreaka1_encode_fns, 0, 0 },
18903 - { "xsr.ibreaka1", 241 /* xt_iclass_xsr.ibreaka1 */,
18905 - Opcode_xsr_ibreaka1_encode_fns, 0, 0 },
18906 - { "rsr.ibreakenable", 242 /* xt_iclass_rsr.ibreakenable */,
18908 - Opcode_rsr_ibreakenable_encode_fns, 0, 0 },
18909 - { "wsr.ibreakenable", 243 /* xt_iclass_wsr.ibreakenable */,
18911 - Opcode_wsr_ibreakenable_encode_fns, 0, 0 },
18912 - { "xsr.ibreakenable", 244 /* xt_iclass_xsr.ibreakenable */,
18914 - Opcode_xsr_ibreakenable_encode_fns, 0, 0 },
18915 - { "rsr.debugcause", 245 /* xt_iclass_rsr.debugcause */,
18917 - Opcode_rsr_debugcause_encode_fns, 0, 0 },
18918 - { "wsr.debugcause", 246 /* xt_iclass_wsr.debugcause */,
18920 - Opcode_wsr_debugcause_encode_fns, 0, 0 },
18921 - { "xsr.debugcause", 247 /* xt_iclass_xsr.debugcause */,
18923 - Opcode_xsr_debugcause_encode_fns, 0, 0 },
18924 - { "rsr.icount", 248 /* xt_iclass_rsr.icount */,
18926 - Opcode_rsr_icount_encode_fns, 0, 0 },
18927 - { "wsr.icount", 249 /* xt_iclass_wsr.icount */,
18929 - Opcode_wsr_icount_encode_fns, 0, 0 },
18930 - { "xsr.icount", 250 /* xt_iclass_xsr.icount */,
18932 - Opcode_xsr_icount_encode_fns, 0, 0 },
18933 - { "rsr.icountlevel", 251 /* xt_iclass_rsr.icountlevel */,
18935 - Opcode_rsr_icountlevel_encode_fns, 0, 0 },
18936 - { "wsr.icountlevel", 252 /* xt_iclass_wsr.icountlevel */,
18938 - Opcode_wsr_icountlevel_encode_fns, 0, 0 },
18939 - { "xsr.icountlevel", 253 /* xt_iclass_xsr.icountlevel */,
18941 - Opcode_xsr_icountlevel_encode_fns, 0, 0 },
18942 - { "rsr.ddr", 254 /* xt_iclass_rsr.ddr */,
18944 - Opcode_rsr_ddr_encode_fns, 0, 0 },
18945 - { "wsr.ddr", 255 /* xt_iclass_wsr.ddr */,
18947 - Opcode_wsr_ddr_encode_fns, 0, 0 },
18948 - { "xsr.ddr", 256 /* xt_iclass_xsr.ddr */,
18950 - Opcode_xsr_ddr_encode_fns, 0, 0 },
18951 - { "rfdo", 257 /* xt_iclass_rfdo */,
18952 - XTENSA_OPCODE_IS_JUMP,
18953 - Opcode_rfdo_encode_fns, 0, 0 },
18954 - { "rfdd", 258 /* xt_iclass_rfdd */,
18955 - XTENSA_OPCODE_IS_JUMP,
18956 - Opcode_rfdd_encode_fns, 0, 0 },
18957 - { "wsr.mmid", 259 /* xt_iclass_wsr.mmid */,
18959 - Opcode_wsr_mmid_encode_fns, 0, 0 },
18960 - { "andb", 260 /* xt_iclass_bbool1 */,
18962 - Opcode_andb_encode_fns, 0, 0 },
18963 - { "andbc", 260 /* xt_iclass_bbool1 */,
18965 - Opcode_andbc_encode_fns, 0, 0 },
18966 - { "orb", 260 /* xt_iclass_bbool1 */,
18968 - Opcode_orb_encode_fns, 0, 0 },
18969 - { "orbc", 260 /* xt_iclass_bbool1 */,
18971 - Opcode_orbc_encode_fns, 0, 0 },
18972 - { "xorb", 260 /* xt_iclass_bbool1 */,
18974 - Opcode_xorb_encode_fns, 0, 0 },
18975 - { "any4", 261 /* xt_iclass_bbool4 */,
18977 - Opcode_any4_encode_fns, 0, 0 },
18978 - { "all4", 261 /* xt_iclass_bbool4 */,
18980 - Opcode_all4_encode_fns, 0, 0 },
18981 - { "any8", 262 /* xt_iclass_bbool8 */,
18983 - Opcode_any8_encode_fns, 0, 0 },
18984 - { "all8", 262 /* xt_iclass_bbool8 */,
18986 - Opcode_all8_encode_fns, 0, 0 },
18987 - { "bf", 263 /* xt_iclass_bbranch */,
18988 - XTENSA_OPCODE_IS_BRANCH,
18989 - Opcode_bf_encode_fns, 0, 0 },
18990 - { "bt", 263 /* xt_iclass_bbranch */,
18991 - XTENSA_OPCODE_IS_BRANCH,
18992 - Opcode_bt_encode_fns, 0, 0 },
18993 - { "movf", 264 /* xt_iclass_bmove */,
18995 - Opcode_movf_encode_fns, 0, 0 },
18996 - { "movt", 264 /* xt_iclass_bmove */,
18998 - Opcode_movt_encode_fns, 0, 0 },
18999 - { "rsr.br", 265 /* xt_iclass_RSR.BR */,
19001 - Opcode_rsr_br_encode_fns, 0, 0 },
19002 - { "wsr.br", 266 /* xt_iclass_WSR.BR */,
19004 - Opcode_wsr_br_encode_fns, 0, 0 },
19005 - { "xsr.br", 267 /* xt_iclass_XSR.BR */,
19007 - Opcode_xsr_br_encode_fns, 0, 0 },
19008 - { "rsr.ccount", 268 /* xt_iclass_rsr.ccount */,
19010 - Opcode_rsr_ccount_encode_fns, 0, 0 },
19011 - { "wsr.ccount", 269 /* xt_iclass_wsr.ccount */,
19013 - Opcode_wsr_ccount_encode_fns, 0, 0 },
19014 - { "xsr.ccount", 270 /* xt_iclass_xsr.ccount */,
19016 - Opcode_xsr_ccount_encode_fns, 0, 0 },
19017 - { "rsr.ccompare0", 271 /* xt_iclass_rsr.ccompare0 */,
19019 - Opcode_rsr_ccompare0_encode_fns, 0, 0 },
19020 - { "wsr.ccompare0", 272 /* xt_iclass_wsr.ccompare0 */,
19022 - Opcode_wsr_ccompare0_encode_fns, 0, 0 },
19023 - { "xsr.ccompare0", 273 /* xt_iclass_xsr.ccompare0 */,
19025 - Opcode_xsr_ccompare0_encode_fns, 0, 0 },
19026 - { "rsr.ccompare1", 274 /* xt_iclass_rsr.ccompare1 */,
19028 - Opcode_rsr_ccompare1_encode_fns, 0, 0 },
19029 - { "wsr.ccompare1", 275 /* xt_iclass_wsr.ccompare1 */,
19031 - Opcode_wsr_ccompare1_encode_fns, 0, 0 },
19032 - { "xsr.ccompare1", 276 /* xt_iclass_xsr.ccompare1 */,
19034 - Opcode_xsr_ccompare1_encode_fns, 0, 0 },
19035 - { "rsr.ccompare2", 277 /* xt_iclass_rsr.ccompare2 */,
19037 - Opcode_rsr_ccompare2_encode_fns, 0, 0 },
19038 - { "wsr.ccompare2", 278 /* xt_iclass_wsr.ccompare2 */,
19040 - Opcode_wsr_ccompare2_encode_fns, 0, 0 },
19041 - { "xsr.ccompare2", 279 /* xt_iclass_xsr.ccompare2 */,
19043 - Opcode_xsr_ccompare2_encode_fns, 0, 0 },
19044 - { "ipf", 280 /* xt_iclass_icache */,
19046 - Opcode_ipf_encode_fns, 0, 0 },
19047 - { "ihi", 280 /* xt_iclass_icache */,
19049 - Opcode_ihi_encode_fns, 0, 0 },
19050 - { "ipfl", 281 /* xt_iclass_icache_lock */,
19052 - Opcode_ipfl_encode_fns, 0, 0 },
19053 - { "ihu", 281 /* xt_iclass_icache_lock */,
19055 - Opcode_ihu_encode_fns, 0, 0 },
19056 - { "iiu", 281 /* xt_iclass_icache_lock */,
19058 - Opcode_iiu_encode_fns, 0, 0 },
19059 - { "iii", 282 /* xt_iclass_icache_inv */,
19061 - Opcode_iii_encode_fns, 0, 0 },
19062 - { "lict", 283 /* xt_iclass_licx */,
19064 - Opcode_lict_encode_fns, 0, 0 },
19065 - { "licw", 283 /* xt_iclass_licx */,
19067 - Opcode_licw_encode_fns, 0, 0 },
19068 - { "sict", 284 /* xt_iclass_sicx */,
19070 - Opcode_sict_encode_fns, 0, 0 },
19071 - { "sicw", 284 /* xt_iclass_sicx */,
19073 - Opcode_sicw_encode_fns, 0, 0 },
19074 - { "dhwb", 285 /* xt_iclass_dcache */,
19076 - Opcode_dhwb_encode_fns, 0, 0 },
19077 - { "dhwbi", 285 /* xt_iclass_dcache */,
19079 - Opcode_dhwbi_encode_fns, 0, 0 },
19080 - { "diwb", 286 /* xt_iclass_dcache_ind */,
19082 - Opcode_diwb_encode_fns, 0, 0 },
19083 - { "diwbi", 286 /* xt_iclass_dcache_ind */,
19085 - Opcode_diwbi_encode_fns, 0, 0 },
19086 - { "dhi", 287 /* xt_iclass_dcache_inv */,
19088 - Opcode_dhi_encode_fns, 0, 0 },
19089 - { "dii", 287 /* xt_iclass_dcache_inv */,
19091 - Opcode_dii_encode_fns, 0, 0 },
19092 - { "dpfr", 288 /* xt_iclass_dpf */,
19094 - Opcode_dpfr_encode_fns, 0, 0 },
19095 - { "dpfw", 288 /* xt_iclass_dpf */,
19097 - Opcode_dpfw_encode_fns, 0, 0 },
19098 - { "dpfro", 288 /* xt_iclass_dpf */,
19100 - Opcode_dpfro_encode_fns, 0, 0 },
19101 - { "dpfwo", 288 /* xt_iclass_dpf */,
19103 - Opcode_dpfwo_encode_fns, 0, 0 },
19104 - { "dpfl", 289 /* xt_iclass_dcache_lock */,
19106 - Opcode_dpfl_encode_fns, 0, 0 },
19107 - { "dhu", 289 /* xt_iclass_dcache_lock */,
19109 - Opcode_dhu_encode_fns, 0, 0 },
19110 - { "diu", 289 /* xt_iclass_dcache_lock */,
19112 - Opcode_diu_encode_fns, 0, 0 },
19113 - { "sdct", 290 /* xt_iclass_sdct */,
19115 - Opcode_sdct_encode_fns, 0, 0 },
19116 - { "ldct", 291 /* xt_iclass_ldct */,
19118 - Opcode_ldct_encode_fns, 0, 0 },
19119 - { "wsr.ptevaddr", 292 /* xt_iclass_wsr.ptevaddr */,
19121 - Opcode_wsr_ptevaddr_encode_fns, 0, 0 },
19122 - { "rsr.ptevaddr", 293 /* xt_iclass_rsr.ptevaddr */,
19124 - Opcode_rsr_ptevaddr_encode_fns, 0, 0 },
19125 - { "xsr.ptevaddr", 294 /* xt_iclass_xsr.ptevaddr */,
19127 - Opcode_xsr_ptevaddr_encode_fns, 0, 0 },
19128 - { "rsr.rasid", 295 /* xt_iclass_rsr.rasid */,
19130 - Opcode_rsr_rasid_encode_fns, 0, 0 },
19131 - { "wsr.rasid", 296 /* xt_iclass_wsr.rasid */,
19133 - Opcode_wsr_rasid_encode_fns, 0, 0 },
19134 - { "xsr.rasid", 297 /* xt_iclass_xsr.rasid */,
19136 - Opcode_xsr_rasid_encode_fns, 0, 0 },
19137 - { "rsr.itlbcfg", 298 /* xt_iclass_rsr.itlbcfg */,
19139 - Opcode_rsr_itlbcfg_encode_fns, 0, 0 },
19140 - { "wsr.itlbcfg", 299 /* xt_iclass_wsr.itlbcfg */,
19142 - Opcode_wsr_itlbcfg_encode_fns, 0, 0 },
19143 - { "xsr.itlbcfg", 300 /* xt_iclass_xsr.itlbcfg */,
19145 - Opcode_xsr_itlbcfg_encode_fns, 0, 0 },
19146 - { "rsr.dtlbcfg", 301 /* xt_iclass_rsr.dtlbcfg */,
19148 - Opcode_rsr_dtlbcfg_encode_fns, 0, 0 },
19149 - { "wsr.dtlbcfg", 302 /* xt_iclass_wsr.dtlbcfg */,
19151 - Opcode_wsr_dtlbcfg_encode_fns, 0, 0 },
19152 - { "xsr.dtlbcfg", 303 /* xt_iclass_xsr.dtlbcfg */,
19154 - Opcode_xsr_dtlbcfg_encode_fns, 0, 0 },
19155 - { "idtlb", 304 /* xt_iclass_idtlb */,
19157 - Opcode_idtlb_encode_fns, 0, 0 },
19158 - { "pdtlb", 305 /* xt_iclass_rdtlb */,
19160 - Opcode_pdtlb_encode_fns, 0, 0 },
19161 - { "rdtlb0", 305 /* xt_iclass_rdtlb */,
19163 - Opcode_rdtlb0_encode_fns, 0, 0 },
19164 - { "rdtlb1", 305 /* xt_iclass_rdtlb */,
19166 - Opcode_rdtlb1_encode_fns, 0, 0 },
19167 - { "wdtlb", 306 /* xt_iclass_wdtlb */,
19169 - Opcode_wdtlb_encode_fns, 0, 0 },
19170 - { "iitlb", 307 /* xt_iclass_iitlb */,
19172 - Opcode_iitlb_encode_fns, 0, 0 },
19173 - { "pitlb", 308 /* xt_iclass_ritlb */,
19175 - Opcode_pitlb_encode_fns, 0, 0 },
19176 - { "ritlb0", 308 /* xt_iclass_ritlb */,
19178 - Opcode_ritlb0_encode_fns, 0, 0 },
19179 - { "ritlb1", 308 /* xt_iclass_ritlb */,
19181 - Opcode_ritlb1_encode_fns, 0, 0 },
19182 - { "witlb", 309 /* xt_iclass_witlb */,
19184 - Opcode_witlb_encode_fns, 0, 0 },
19185 - { "ldpte", 310 /* xt_iclass_ldpte */,
19187 - Opcode_ldpte_encode_fns, 0, 0 },
19188 - { "hwwitlba", 311 /* xt_iclass_hwwitlba */,
19189 - XTENSA_OPCODE_IS_BRANCH,
19190 - Opcode_hwwitlba_encode_fns, 0, 0 },
19191 - { "hwwdtlba", 312 /* xt_iclass_hwwdtlba */,
19193 - Opcode_hwwdtlba_encode_fns, 0, 0 },
19194 - { "rsr.cpenable", 313 /* xt_iclass_rsr.cpenable */,
19196 - Opcode_rsr_cpenable_encode_fns, 0, 0 },
19197 - { "wsr.cpenable", 314 /* xt_iclass_wsr.cpenable */,
19199 - Opcode_wsr_cpenable_encode_fns, 0, 0 },
19200 - { "xsr.cpenable", 315 /* xt_iclass_xsr.cpenable */,
19202 - Opcode_xsr_cpenable_encode_fns, 0, 0 },
19203 - { "clamps", 316 /* xt_iclass_clamp */,
19205 - Opcode_clamps_encode_fns, 0, 0 },
19206 - { "min", 317 /* xt_iclass_minmax */,
19208 - Opcode_min_encode_fns, 0, 0 },
19209 - { "max", 317 /* xt_iclass_minmax */,
19211 - Opcode_max_encode_fns, 0, 0 },
19212 - { "minu", 317 /* xt_iclass_minmax */,
19214 - Opcode_minu_encode_fns, 0, 0 },
19215 - { "maxu", 317 /* xt_iclass_minmax */,
19217 - Opcode_maxu_encode_fns, 0, 0 },
19218 - { "nsa", 318 /* xt_iclass_nsa */,
19220 - Opcode_nsa_encode_fns, 0, 0 },
19221 - { "nsau", 318 /* xt_iclass_nsa */,
19223 - Opcode_nsau_encode_fns, 0, 0 },
19224 - { "sext", 319 /* xt_iclass_sx */,
19226 - Opcode_sext_encode_fns, 0, 0 },
19227 - { "l32ai", 320 /* xt_iclass_l32ai */,
19229 - Opcode_l32ai_encode_fns, 0, 0 },
19230 - { "s32ri", 321 /* xt_iclass_s32ri */,
19232 - Opcode_s32ri_encode_fns, 0, 0 },
19233 - { "s32c1i", 322 /* xt_iclass_s32c1i */,
19235 - Opcode_s32c1i_encode_fns, 0, 0 },
19236 - { "rsr.scompare1", 323 /* xt_iclass_rsr.scompare1 */,
19238 - Opcode_rsr_scompare1_encode_fns, 0, 0 },
19239 - { "wsr.scompare1", 324 /* xt_iclass_wsr.scompare1 */,
19241 - Opcode_wsr_scompare1_encode_fns, 0, 0 },
19242 - { "xsr.scompare1", 325 /* xt_iclass_xsr.scompare1 */,
19244 - Opcode_xsr_scompare1_encode_fns, 0, 0 },
19245 - { "quou", 326 /* xt_iclass_div */,
19247 - Opcode_quou_encode_fns, 0, 0 },
19248 - { "quos", 326 /* xt_iclass_div */,
19250 - Opcode_quos_encode_fns, 0, 0 },
19251 - { "remu", 326 /* xt_iclass_div */,
19253 - Opcode_remu_encode_fns, 0, 0 },
19254 - { "rems", 326 /* xt_iclass_div */,
19256 - Opcode_rems_encode_fns, 0, 0 },
19257 - { "mull", 327 /* xt_mul32 */,
19259 - Opcode_mull_encode_fns, 0, 0 },
19260 - { "muluh", 327 /* xt_mul32 */,
19262 - Opcode_muluh_encode_fns, 0, 0 },
19263 - { "mulsh", 327 /* xt_mul32 */,
19265 - Opcode_mulsh_encode_fns, 0, 0 },
19266 - { "rur.fcr", 328 /* rur_fcr */,
19268 - Opcode_rur_fcr_encode_fns, 0, 0 },
19269 - { "wur.fcr", 329 /* wur_fcr */,
19271 - Opcode_wur_fcr_encode_fns, 0, 0 },
19272 - { "rur.fsr", 330 /* rur_fsr */,
19274 - Opcode_rur_fsr_encode_fns, 0, 0 },
19275 - { "wur.fsr", 331 /* wur_fsr */,
19277 - Opcode_wur_fsr_encode_fns, 0, 0 },
19278 - { "add.s", 332 /* fp */,
19280 - Opcode_add_s_encode_fns, 0, 0 },
19281 - { "sub.s", 332 /* fp */,
19283 - Opcode_sub_s_encode_fns, 0, 0 },
19284 - { "mul.s", 332 /* fp */,
19286 - Opcode_mul_s_encode_fns, 0, 0 },
19287 - { "madd.s", 333 /* fp_mac */,
19289 - Opcode_madd_s_encode_fns, 0, 0 },
19290 - { "msub.s", 333 /* fp_mac */,
19292 - Opcode_msub_s_encode_fns, 0, 0 },
19293 - { "movf.s", 334 /* fp_cmov */,
19295 - Opcode_movf_s_encode_fns, 0, 0 },
19296 - { "movt.s", 334 /* fp_cmov */,
19298 - Opcode_movt_s_encode_fns, 0, 0 },
19299 - { "moveqz.s", 335 /* fp_mov */,
19301 - Opcode_moveqz_s_encode_fns, 0, 0 },
19302 - { "movnez.s", 335 /* fp_mov */,
19304 - Opcode_movnez_s_encode_fns, 0, 0 },
19305 - { "movltz.s", 335 /* fp_mov */,
19307 - Opcode_movltz_s_encode_fns, 0, 0 },
19308 - { "movgez.s", 335 /* fp_mov */,
19310 - Opcode_movgez_s_encode_fns, 0, 0 },
19311 - { "abs.s", 336 /* fp_mov2 */,
19313 - Opcode_abs_s_encode_fns, 0, 0 },
19314 - { "mov.s", 336 /* fp_mov2 */,
19316 - Opcode_mov_s_encode_fns, 0, 0 },
19317 - { "neg.s", 336 /* fp_mov2 */,
19319 - Opcode_neg_s_encode_fns, 0, 0 },
19320 - { "un.s", 337 /* fp_cmp */,
19322 - Opcode_un_s_encode_fns, 0, 0 },
19323 - { "oeq.s", 337 /* fp_cmp */,
19325 - Opcode_oeq_s_encode_fns, 0, 0 },
19326 - { "ueq.s", 337 /* fp_cmp */,
19328 - Opcode_ueq_s_encode_fns, 0, 0 },
19329 - { "olt.s", 337 /* fp_cmp */,
19331 - Opcode_olt_s_encode_fns, 0, 0 },
19332 - { "ult.s", 337 /* fp_cmp */,
19334 - Opcode_ult_s_encode_fns, 0, 0 },
19335 - { "ole.s", 337 /* fp_cmp */,
19337 - Opcode_ole_s_encode_fns, 0, 0 },
19338 - { "ule.s", 337 /* fp_cmp */,
19340 - Opcode_ule_s_encode_fns, 0, 0 },
19341 - { "float.s", 338 /* fp_float */,
19343 - Opcode_float_s_encode_fns, 0, 0 },
19344 - { "ufloat.s", 338 /* fp_float */,
19346 - Opcode_ufloat_s_encode_fns, 0, 0 },
19347 - { "round.s", 339 /* fp_int */,
19349 - Opcode_round_s_encode_fns, 0, 0 },
19350 - { "ceil.s", 339 /* fp_int */,
19352 - Opcode_ceil_s_encode_fns, 0, 0 },
19353 - { "floor.s", 339 /* fp_int */,
19355 - Opcode_floor_s_encode_fns, 0, 0 },
19356 - { "trunc.s", 339 /* fp_int */,
19358 - Opcode_trunc_s_encode_fns, 0, 0 },
19359 - { "utrunc.s", 339 /* fp_int */,
19361 - Opcode_utrunc_s_encode_fns, 0, 0 },
19362 - { "rfr", 340 /* fp_rfr */,
19364 - Opcode_rfr_encode_fns, 0, 0 },
19365 - { "wfr", 341 /* fp_wfr */,
19367 - Opcode_wfr_encode_fns, 0, 0 },
19368 - { "lsi", 342 /* fp_lsi */,
19370 - Opcode_lsi_encode_fns, 0, 0 },
19371 - { "lsiu", 343 /* fp_lsiu */,
19373 - Opcode_lsiu_encode_fns, 0, 0 },
19374 - { "lsx", 344 /* fp_lsx */,
19376 - Opcode_lsx_encode_fns, 0, 0 },
19377 - { "lsxu", 345 /* fp_lsxu */,
19379 - Opcode_lsxu_encode_fns, 0, 0 },
19380 - { "ssi", 346 /* fp_ssi */,
19382 - Opcode_ssi_encode_fns, 0, 0 },
19383 - { "ssiu", 347 /* fp_ssiu */,
19385 - Opcode_ssiu_encode_fns, 0, 0 },
19386 - { "ssx", 348 /* fp_ssx */,
19388 - Opcode_ssx_encode_fns, 0, 0 },
19389 - { "ssxu", 349 /* fp_ssxu */,
19391 - Opcode_ssxu_encode_fns, 0, 0 },
19392 - { "beqz.w18", 350 /* xt_iclass_wb18_0 */,
19393 - XTENSA_OPCODE_IS_BRANCH,
19394 - Opcode_beqz_w18_encode_fns, 0, 0 },
19395 - { "bnez.w18", 350 /* xt_iclass_wb18_0 */,
19396 - XTENSA_OPCODE_IS_BRANCH,
19397 - Opcode_bnez_w18_encode_fns, 0, 0 },
19398 - { "bgez.w18", 350 /* xt_iclass_wb18_0 */,
19399 - XTENSA_OPCODE_IS_BRANCH,
19400 - Opcode_bgez_w18_encode_fns, 0, 0 },
19401 - { "bltz.w18", 350 /* xt_iclass_wb18_0 */,
19402 - XTENSA_OPCODE_IS_BRANCH,
19403 - Opcode_bltz_w18_encode_fns, 0, 0 },
19404 - { "beqi.w18", 351 /* xt_iclass_wb18_1 */,
19405 - XTENSA_OPCODE_IS_BRANCH,
19406 - Opcode_beqi_w18_encode_fns, 0, 0 },
19407 - { "bnei.w18", 351 /* xt_iclass_wb18_1 */,
19408 - XTENSA_OPCODE_IS_BRANCH,
19409 - Opcode_bnei_w18_encode_fns, 0, 0 },
19410 - { "bgei.w18", 351 /* xt_iclass_wb18_1 */,
19411 - XTENSA_OPCODE_IS_BRANCH,
19412 - Opcode_bgei_w18_encode_fns, 0, 0 },
19413 - { "blti.w18", 351 /* xt_iclass_wb18_1 */,
19414 - XTENSA_OPCODE_IS_BRANCH,
19415 - Opcode_blti_w18_encode_fns, 0, 0 },
19416 - { "bgeui.w18", 352 /* xt_iclass_wb18_2 */,
19417 - XTENSA_OPCODE_IS_BRANCH,
19418 - Opcode_bgeui_w18_encode_fns, 0, 0 },
19419 - { "bltui.w18", 352 /* xt_iclass_wb18_2 */,
19420 - XTENSA_OPCODE_IS_BRANCH,
19421 - Opcode_bltui_w18_encode_fns, 0, 0 },
19422 - { "bbci.w18", 353 /* xt_iclass_wb18_3 */,
19423 - XTENSA_OPCODE_IS_BRANCH,
19424 - Opcode_bbci_w18_encode_fns, 0, 0 },
19425 - { "bbsi.w18", 353 /* xt_iclass_wb18_3 */,
19426 - XTENSA_OPCODE_IS_BRANCH,
19427 - Opcode_bbsi_w18_encode_fns, 0, 0 },
19428 - { "beq.w18", 354 /* xt_iclass_wb18_4 */,
19429 - XTENSA_OPCODE_IS_BRANCH,
19430 - Opcode_beq_w18_encode_fns, 0, 0 },
19431 - { "bne.w18", 354 /* xt_iclass_wb18_4 */,
19432 - XTENSA_OPCODE_IS_BRANCH,
19433 - Opcode_bne_w18_encode_fns, 0, 0 },
19434 - { "bge.w18", 354 /* xt_iclass_wb18_4 */,
19435 - XTENSA_OPCODE_IS_BRANCH,
19436 - Opcode_bge_w18_encode_fns, 0, 0 },
19437 - { "blt.w18", 354 /* xt_iclass_wb18_4 */,
19438 - XTENSA_OPCODE_IS_BRANCH,
19439 - Opcode_blt_w18_encode_fns, 0, 0 },
19440 - { "bgeu.w18", 354 /* xt_iclass_wb18_4 */,
19441 - XTENSA_OPCODE_IS_BRANCH,
19442 - Opcode_bgeu_w18_encode_fns, 0, 0 },
19443 - { "bltu.w18", 354 /* xt_iclass_wb18_4 */,
19444 - XTENSA_OPCODE_IS_BRANCH,
19445 - Opcode_bltu_w18_encode_fns, 0, 0 },
19446 - { "bany.w18", 354 /* xt_iclass_wb18_4 */,
19447 - XTENSA_OPCODE_IS_BRANCH,
19448 - Opcode_bany_w18_encode_fns, 0, 0 },
19449 - { "bnone.w18", 354 /* xt_iclass_wb18_4 */,
19450 - XTENSA_OPCODE_IS_BRANCH,
19451 - Opcode_bnone_w18_encode_fns, 0, 0 },
19452 - { "ball.w18", 354 /* xt_iclass_wb18_4 */,
19453 - XTENSA_OPCODE_IS_BRANCH,
19454 - Opcode_ball_w18_encode_fns, 0, 0 },
19455 - { "bnall.w18", 354 /* xt_iclass_wb18_4 */,
19456 - XTENSA_OPCODE_IS_BRANCH,
19457 - Opcode_bnall_w18_encode_fns, 0, 0 },
19458 - { "bbc.w18", 354 /* xt_iclass_wb18_4 */,
19459 - XTENSA_OPCODE_IS_BRANCH,
19460 - Opcode_bbc_w18_encode_fns, 0, 0 },
19461 - { "bbs.w18", 354 /* xt_iclass_wb18_4 */,
19462 - XTENSA_OPCODE_IS_BRANCH,
19463 - Opcode_bbs_w18_encode_fns, 0, 0 }
19467 -/* Slot-specific opcode decode functions. */
19470 -Slot_inst_decode (const xtensa_insnbuf insn)
19472 - switch (Field_op0_Slot_inst_get (insn))
19475 - switch (Field_op1_Slot_inst_get (insn))
19478 - switch (Field_op2_Slot_inst_get (insn))
19481 - switch (Field_r_Slot_inst_get (insn))
19484 - switch (Field_m_Slot_inst_get (insn))
19487 - if (Field_s_Slot_inst_get (insn) == 0 &&
19488 - Field_n_Slot_inst_get (insn) == 0)
19489 - return 79; /* ill */
19492 - switch (Field_n_Slot_inst_get (insn))
19495 - return 98; /* ret */
19497 - return 14; /* retw */
19499 - return 81; /* jx */
19503 - switch (Field_n_Slot_inst_get (insn))
19506 - return 77; /* callx0 */
19508 - return 10; /* callx4 */
19510 - return 9; /* callx8 */
19512 - return 8; /* callx12 */
19518 - return 12; /* movsp */
19520 - if (Field_s_Slot_inst_get (insn) == 0)
19522 - switch (Field_t_Slot_inst_get (insn))
19525 - return 116; /* isync */
19527 - return 117; /* rsync */
19529 - return 118; /* esync */
19531 - return 119; /* dsync */
19533 - return 0; /* excw */
19535 - return 114; /* memw */
19537 - return 115; /* extw */
19539 - return 97; /* nop */
19544 - switch (Field_t_Slot_inst_get (insn))
19547 - switch (Field_s_Slot_inst_get (insn))
19550 - return 1; /* rfe */
19552 - return 2; /* rfde */
19554 - return 16; /* rfwo */
19556 - return 17; /* rfwu */
19560 - return 316; /* rfi */
19564 - return 324; /* break */
19566 - switch (Field_s_Slot_inst_get (insn))
19569 - if (Field_t_Slot_inst_get (insn) == 0)
19570 - return 3; /* syscall */
19573 - if (Field_t_Slot_inst_get (insn) == 0)
19574 - return 4; /* simcall */
19579 - return 120; /* rsil */
19581 - if (Field_t_Slot_inst_get (insn) == 0)
19582 - return 317; /* waiti */
19585 - return 367; /* any4 */
19587 - return 368; /* all4 */
19589 - return 369; /* any8 */
19591 - return 370; /* all8 */
19595 - return 49; /* and */
19597 - return 50; /* or */
19599 - return 51; /* xor */
19601 - switch (Field_r_Slot_inst_get (insn))
19604 - if (Field_t_Slot_inst_get (insn) == 0)
19605 - return 102; /* ssr */
19608 - if (Field_t_Slot_inst_get (insn) == 0)
19609 - return 103; /* ssl */
19612 - if (Field_t_Slot_inst_get (insn) == 0)
19613 - return 104; /* ssa8l */
19616 - if (Field_t_Slot_inst_get (insn) == 0)
19617 - return 105; /* ssa8b */
19620 - if (Field_thi3_Slot_inst_get (insn) == 0)
19621 - return 106; /* ssai */
19624 - if (Field_s_Slot_inst_get (insn) == 0)
19625 - return 13; /* rotw */
19628 - return 448; /* nsa */
19630 - return 449; /* nsau */
19634 - switch (Field_r_Slot_inst_get (insn))
19637 - return 438; /* hwwitlba */
19639 - return 434; /* ritlb0 */
19641 - if (Field_t_Slot_inst_get (insn) == 0)
19642 - return 432; /* iitlb */
19645 - return 433; /* pitlb */
19647 - return 436; /* witlb */
19649 - return 435; /* ritlb1 */
19651 - return 439; /* hwwdtlba */
19653 - return 429; /* rdtlb0 */
19655 - if (Field_t_Slot_inst_get (insn) == 0)
19656 - return 427; /* idtlb */
19659 - return 428; /* pdtlb */
19661 - return 431; /* wdtlb */
19663 - return 430; /* rdtlb1 */
19667 - switch (Field_s_Slot_inst_get (insn))
19670 - return 95; /* neg */
19672 - return 96; /* abs */
19676 - return 41; /* add */
19678 - return 43; /* addx2 */
19680 - return 44; /* addx4 */
19682 - return 45; /* addx8 */
19684 - return 42; /* sub */
19686 - return 46; /* subx2 */
19688 - return 47; /* subx4 */
19690 - return 48; /* subx8 */
19694 - switch (Field_op2_Slot_inst_get (insn))
19698 - return 111; /* slli */
19701 - return 112; /* srai */
19703 - return 113; /* srli */
19705 - switch (Field_sr_Slot_inst_get (insn))
19708 - return 129; /* xsr.lbeg */
19710 - return 123; /* xsr.lend */
19712 - return 126; /* xsr.lcount */
19714 - return 132; /* xsr.sar */
19716 - return 377; /* xsr.br */
19718 - return 135; /* xsr.litbase */
19720 - return 456; /* xsr.scompare1 */
19722 - return 312; /* xsr.acclo */
19724 - return 315; /* xsr.acchi */
19726 - return 300; /* xsr.m0 */
19728 - return 303; /* xsr.m1 */
19730 - return 306; /* xsr.m2 */
19732 - return 309; /* xsr.m3 */
19734 - return 22; /* xsr.windowbase */
19736 - return 25; /* xsr.windowstart */
19738 - return 417; /* xsr.ptevaddr */
19740 - return 420; /* xsr.rasid */
19742 - return 423; /* xsr.itlbcfg */
19744 - return 426; /* xsr.dtlbcfg */
19746 - return 346; /* xsr.ibreakenable */
19748 - return 358; /* xsr.ddr */
19750 - return 340; /* xsr.ibreaka0 */
19752 - return 343; /* xsr.ibreaka1 */
19754 - return 328; /* xsr.dbreaka0 */
19756 - return 334; /* xsr.dbreaka1 */
19758 - return 331; /* xsr.dbreakc0 */
19760 - return 337; /* xsr.dbreakc1 */
19762 - return 143; /* xsr.epc1 */
19764 - return 149; /* xsr.epc2 */
19766 - return 155; /* xsr.epc3 */
19768 - return 161; /* xsr.epc4 */
19770 - return 167; /* xsr.epc5 */
19772 - return 173; /* xsr.epc6 */
19774 - return 179; /* xsr.epc7 */
19776 - return 206; /* xsr.depc */
19778 - return 185; /* xsr.eps2 */
19780 - return 188; /* xsr.eps3 */
19782 - return 191; /* xsr.eps4 */
19784 - return 194; /* xsr.eps5 */
19786 - return 197; /* xsr.eps6 */
19788 - return 200; /* xsr.eps7 */
19790 - return 146; /* xsr.excsave1 */
19792 - return 152; /* xsr.excsave2 */
19794 - return 158; /* xsr.excsave3 */
19796 - return 164; /* xsr.excsave4 */
19798 - return 170; /* xsr.excsave5 */
19800 - return 176; /* xsr.excsave6 */
19802 - return 182; /* xsr.excsave7 */
19804 - return 442; /* xsr.cpenable */
19806 - return 323; /* xsr.intenable */
19808 - return 140; /* xsr.ps */
19810 - return 225; /* xsr.vecbase */
19812 - return 209; /* xsr.exccause */
19814 - return 349; /* xsr.debugcause */
19816 - return 380; /* xsr.ccount */
19818 - return 352; /* xsr.icount */
19820 - return 355; /* xsr.icountlevel */
19822 - return 203; /* xsr.excvaddr */
19824 - return 383; /* xsr.ccompare0 */
19826 - return 386; /* xsr.ccompare1 */
19828 - return 389; /* xsr.ccompare2 */
19830 - return 212; /* xsr.misc0 */
19832 - return 215; /* xsr.misc1 */
19834 - return 218; /* xsr.misc2 */
19836 - return 221; /* xsr.misc3 */
19840 - return 108; /* src */
19842 - if (Field_s_Slot_inst_get (insn) == 0)
19843 - return 109; /* srl */
19846 - if (Field_t_Slot_inst_get (insn) == 0)
19847 - return 107; /* sll */
19850 - if (Field_s_Slot_inst_get (insn) == 0)
19851 - return 110; /* sra */
19854 - return 296; /* mul16u */
19856 - return 297; /* mul16s */
19858 - switch (Field_r_Slot_inst_get (insn))
19861 - return 396; /* lict */
19863 - return 398; /* sict */
19865 - return 397; /* licw */
19867 - return 399; /* sicw */
19869 - return 414; /* ldct */
19871 - return 413; /* sdct */
19873 - if (Field_t_Slot_inst_get (insn) == 0)
19874 - return 359; /* rfdo */
19875 - if (Field_t_Slot_inst_get (insn) == 1)
19876 - return 360; /* rfdd */
19879 - return 437; /* ldpte */
19885 - switch (Field_op2_Slot_inst_get (insn))
19888 - return 362; /* andb */
19890 - return 363; /* andbc */
19892 - return 364; /* orb */
19894 - return 365; /* orbc */
19896 - return 366; /* xorb */
19898 - return 461; /* mull */
19900 - return 462; /* muluh */
19902 - return 463; /* mulsh */
19904 - return 457; /* quou */
19906 - return 458; /* quos */
19908 - return 459; /* remu */
19910 - return 460; /* rems */
19914 - switch (Field_op2_Slot_inst_get (insn))
19917 - switch (Field_sr_Slot_inst_get (insn))
19920 - return 127; /* rsr.lbeg */
19922 - return 121; /* rsr.lend */
19924 - return 124; /* rsr.lcount */
19926 - return 130; /* rsr.sar */
19928 - return 375; /* rsr.br */
19930 - return 133; /* rsr.litbase */
19932 - return 454; /* rsr.scompare1 */
19934 - return 310; /* rsr.acclo */
19936 - return 313; /* rsr.acchi */
19938 - return 298; /* rsr.m0 */
19940 - return 301; /* rsr.m1 */
19942 - return 304; /* rsr.m2 */
19944 - return 307; /* rsr.m3 */
19946 - return 20; /* rsr.windowbase */
19948 - return 23; /* rsr.windowstart */
19950 - return 416; /* rsr.ptevaddr */
19952 - return 418; /* rsr.rasid */
19954 - return 421; /* rsr.itlbcfg */
19956 - return 424; /* rsr.dtlbcfg */
19958 - return 344; /* rsr.ibreakenable */
19960 - return 356; /* rsr.ddr */
19962 - return 338; /* rsr.ibreaka0 */
19964 - return 341; /* rsr.ibreaka1 */
19966 - return 326; /* rsr.dbreaka0 */
19968 - return 332; /* rsr.dbreaka1 */
19970 - return 329; /* rsr.dbreakc0 */
19972 - return 335; /* rsr.dbreakc1 */
19974 - return 136; /* rsr.176 */
19976 - return 141; /* rsr.epc1 */
19978 - return 147; /* rsr.epc2 */
19980 - return 153; /* rsr.epc3 */
19982 - return 159; /* rsr.epc4 */
19984 - return 165; /* rsr.epc5 */
19986 - return 171; /* rsr.epc6 */
19988 - return 177; /* rsr.epc7 */
19990 - return 204; /* rsr.depc */
19992 - return 183; /* rsr.eps2 */
19994 - return 186; /* rsr.eps3 */
19996 - return 189; /* rsr.eps4 */
19998 - return 192; /* rsr.eps5 */
20000 - return 195; /* rsr.eps6 */
20002 - return 198; /* rsr.eps7 */
20004 - return 137; /* rsr.208 */
20006 - return 144; /* rsr.excsave1 */
20008 - return 150; /* rsr.excsave2 */
20010 - return 156; /* rsr.excsave3 */
20012 - return 162; /* rsr.excsave4 */
20014 - return 168; /* rsr.excsave5 */
20016 - return 174; /* rsr.excsave6 */
20018 - return 180; /* rsr.excsave7 */
20020 - return 440; /* rsr.cpenable */
20022 - return 318; /* rsr.interrupt */
20024 - return 321; /* rsr.intenable */
20026 - return 138; /* rsr.ps */
20028 - return 223; /* rsr.vecbase */
20030 - return 207; /* rsr.exccause */
20032 - return 347; /* rsr.debugcause */
20034 - return 378; /* rsr.ccount */
20036 - return 222; /* rsr.prid */
20038 - return 350; /* rsr.icount */
20040 - return 353; /* rsr.icountlevel */
20042 - return 201; /* rsr.excvaddr */
20044 - return 381; /* rsr.ccompare0 */
20046 - return 384; /* rsr.ccompare1 */
20048 - return 387; /* rsr.ccompare2 */
20050 - return 210; /* rsr.misc0 */
20052 - return 213; /* rsr.misc1 */
20054 - return 216; /* rsr.misc2 */
20056 - return 219; /* rsr.misc3 */
20060 - switch (Field_sr_Slot_inst_get (insn))
20063 - return 128; /* wsr.lbeg */
20065 - return 122; /* wsr.lend */
20067 - return 125; /* wsr.lcount */
20069 - return 131; /* wsr.sar */
20071 - return 376; /* wsr.br */
20073 - return 134; /* wsr.litbase */
20075 - return 455; /* wsr.scompare1 */
20077 - return 311; /* wsr.acclo */
20079 - return 314; /* wsr.acchi */
20081 - return 299; /* wsr.m0 */
20083 - return 302; /* wsr.m1 */
20085 - return 305; /* wsr.m2 */
20087 - return 308; /* wsr.m3 */
20089 - return 21; /* wsr.windowbase */
20091 - return 24; /* wsr.windowstart */
20093 - return 415; /* wsr.ptevaddr */
20095 - return 361; /* wsr.mmid */
20097 - return 419; /* wsr.rasid */
20099 - return 422; /* wsr.itlbcfg */
20101 - return 425; /* wsr.dtlbcfg */
20103 - return 345; /* wsr.ibreakenable */
20105 - return 357; /* wsr.ddr */
20107 - return 339; /* wsr.ibreaka0 */
20109 - return 342; /* wsr.ibreaka1 */
20111 - return 327; /* wsr.dbreaka0 */
20113 - return 333; /* wsr.dbreaka1 */
20115 - return 330; /* wsr.dbreakc0 */
20117 - return 336; /* wsr.dbreakc1 */
20119 - return 142; /* wsr.epc1 */
20121 - return 148; /* wsr.epc2 */
20123 - return 154; /* wsr.epc3 */
20125 - return 160; /* wsr.epc4 */
20127 - return 166; /* wsr.epc5 */
20129 - return 172; /* wsr.epc6 */
20131 - return 178; /* wsr.epc7 */
20133 - return 205; /* wsr.depc */
20135 - return 184; /* wsr.eps2 */
20137 - return 187; /* wsr.eps3 */
20139 - return 190; /* wsr.eps4 */
20141 - return 193; /* wsr.eps5 */
20143 - return 196; /* wsr.eps6 */
20145 - return 199; /* wsr.eps7 */
20147 - return 145; /* wsr.excsave1 */
20149 - return 151; /* wsr.excsave2 */
20151 - return 157; /* wsr.excsave3 */
20153 - return 163; /* wsr.excsave4 */
20155 - return 169; /* wsr.excsave5 */
20157 - return 175; /* wsr.excsave6 */
20159 - return 181; /* wsr.excsave7 */
20161 - return 441; /* wsr.cpenable */
20163 - return 319; /* wsr.intset */
20165 - return 320; /* wsr.intclear */
20167 - return 322; /* wsr.intenable */
20169 - return 139; /* wsr.ps */
20171 - return 224; /* wsr.vecbase */
20173 - return 208; /* wsr.exccause */
20175 - return 348; /* wsr.debugcause */
20177 - return 379; /* wsr.ccount */
20179 - return 351; /* wsr.icount */
20181 - return 354; /* wsr.icountlevel */
20183 - return 202; /* wsr.excvaddr */
20185 - return 382; /* wsr.ccompare0 */
20187 - return 385; /* wsr.ccompare1 */
20189 - return 388; /* wsr.ccompare2 */
20191 - return 211; /* wsr.misc0 */
20193 - return 214; /* wsr.misc1 */
20195 - return 217; /* wsr.misc2 */
20197 - return 220; /* wsr.misc3 */
20201 - return 450; /* sext */
20203 - return 443; /* clamps */
20205 - return 444; /* min */
20207 - return 445; /* max */
20209 - return 446; /* minu */
20211 - return 447; /* maxu */
20213 - return 91; /* moveqz */
20215 - return 92; /* movnez */
20217 - return 93; /* movltz */
20219 - return 94; /* movgez */
20221 - return 373; /* movf */
20223 - return 374; /* movt */
20225 - switch (Field_st_Slot_inst_get (insn))
20228 - return 37; /* rur.threadptr */
20230 - return 464; /* rur.fcr */
20232 - return 466; /* rur.fsr */
20236 - switch (Field_sr_Slot_inst_get (insn))
20239 - return 38; /* wur.threadptr */
20241 - return 465; /* wur.fcr */
20243 - return 467; /* wur.fsr */
20250 - return 78; /* extui */
20252 - switch (Field_op2_Slot_inst_get (insn))
20255 - return 500; /* lsx */
20257 - return 501; /* lsxu */
20259 - return 504; /* ssx */
20261 - return 505; /* ssxu */
20265 - switch (Field_op2_Slot_inst_get (insn))
20268 - return 18; /* l32e */
20270 - return 19; /* s32e */
20274 - switch (Field_op2_Slot_inst_get (insn))
20277 - return 468; /* add.s */
20279 - return 469; /* sub.s */
20281 - return 470; /* mul.s */
20283 - return 471; /* madd.s */
20285 - return 472; /* msub.s */
20287 - return 491; /* round.s */
20289 - return 494; /* trunc.s */
20291 - return 493; /* floor.s */
20293 - return 492; /* ceil.s */
20295 - return 489; /* float.s */
20297 - return 490; /* ufloat.s */
20299 - return 495; /* utrunc.s */
20301 - switch (Field_t_Slot_inst_get (insn))
20304 - return 480; /* mov.s */
20306 - return 479; /* abs.s */
20308 - return 496; /* rfr */
20310 - return 497; /* wfr */
20312 - return 481; /* neg.s */
20318 - switch (Field_op2_Slot_inst_get (insn))
20321 - return 482; /* un.s */
20323 - return 483; /* oeq.s */
20325 - return 484; /* ueq.s */
20327 - return 485; /* olt.s */
20329 - return 486; /* ult.s */
20331 - return 487; /* ole.s */
20333 - return 488; /* ule.s */
20335 - return 475; /* moveqz.s */
20337 - return 476; /* movnez.s */
20339 - return 477; /* movltz.s */
20341 - return 478; /* movgez.s */
20343 - return 473; /* movf.s */
20345 - return 474; /* movt.s */
20351 - return 85; /* l32r */
20353 - switch (Field_r_Slot_inst_get (insn))
20356 - return 86; /* l8ui */
20358 - return 82; /* l16ui */
20360 - return 84; /* l32i */
20362 - return 101; /* s8i */
20364 - return 99; /* s16i */
20366 - return 100; /* s32i */
20368 - switch (Field_t_Slot_inst_get (insn))
20371 - return 406; /* dpfr */
20373 - return 407; /* dpfw */
20375 - return 408; /* dpfro */
20377 - return 409; /* dpfwo */
20379 - return 400; /* dhwb */
20381 - return 401; /* dhwbi */
20383 - return 404; /* dhi */
20385 - return 405; /* dii */
20387 - switch (Field_op1_Slot_inst_get (insn))
20390 - return 410; /* dpfl */
20392 - return 411; /* dhu */
20394 - return 412; /* diu */
20396 - return 402; /* diwb */
20398 - return 403; /* diwbi */
20402 - return 390; /* ipf */
20404 - switch (Field_op1_Slot_inst_get (insn))
20407 - return 392; /* ipfl */
20409 - return 393; /* ihu */
20411 - return 394; /* iiu */
20415 - return 391; /* ihi */
20417 - return 395; /* iii */
20421 - return 83; /* l16si */
20423 - return 90; /* movi */
20425 - return 451; /* l32ai */
20427 - return 39; /* addi */
20429 - return 40; /* addmi */
20431 - return 453; /* s32c1i */
20433 - return 452; /* s32ri */
20437 - switch (Field_r_Slot_inst_get (insn))
20440 - return 498; /* lsi */
20442 - return 502; /* ssi */
20444 - return 499; /* lsiu */
20446 - return 503; /* ssiu */
20450 - switch (Field_op2_Slot_inst_get (insn))
20453 - switch (Field_op1_Slot_inst_get (insn))
20456 - if (Field_t3_Slot_inst_get (insn) == 0 &&
20457 - Field_tlo_Slot_inst_get (insn) == 0 &&
20458 - Field_r3_Slot_inst_get (insn) == 0)
20459 - return 287; /* mula.dd.ll.ldinc */
20462 - if (Field_t3_Slot_inst_get (insn) == 0 &&
20463 - Field_tlo_Slot_inst_get (insn) == 0 &&
20464 - Field_r3_Slot_inst_get (insn) == 0)
20465 - return 289; /* mula.dd.hl.ldinc */
20468 - if (Field_t3_Slot_inst_get (insn) == 0 &&
20469 - Field_tlo_Slot_inst_get (insn) == 0 &&
20470 - Field_r3_Slot_inst_get (insn) == 0)
20471 - return 291; /* mula.dd.lh.ldinc */
20474 - if (Field_t3_Slot_inst_get (insn) == 0 &&
20475 - Field_tlo_Slot_inst_get (insn) == 0 &&
20476 - Field_r3_Slot_inst_get (insn) == 0)
20477 - return 293; /* mula.dd.hh.ldinc */
20482 - switch (Field_op1_Slot_inst_get (insn))
20485 - if (Field_t3_Slot_inst_get (insn) == 0 &&
20486 - Field_tlo_Slot_inst_get (insn) == 0 &&
20487 - Field_r3_Slot_inst_get (insn) == 0)
20488 - return 286; /* mula.dd.ll.lddec */
20491 - if (Field_t3_Slot_inst_get (insn) == 0 &&
20492 - Field_tlo_Slot_inst_get (insn) == 0 &&
20493 - Field_r3_Slot_inst_get (insn) == 0)
20494 - return 288; /* mula.dd.hl.lddec */
20497 - if (Field_t3_Slot_inst_get (insn) == 0 &&
20498 - Field_tlo_Slot_inst_get (insn) == 0 &&
20499 - Field_r3_Slot_inst_get (insn) == 0)
20500 - return 290; /* mula.dd.lh.lddec */
20503 - if (Field_t3_Slot_inst_get (insn) == 0 &&
20504 - Field_tlo_Slot_inst_get (insn) == 0 &&
20505 - Field_r3_Slot_inst_get (insn) == 0)
20506 - return 292; /* mula.dd.hh.lddec */
20511 - switch (Field_op1_Slot_inst_get (insn))
20514 - if (Field_s_Slot_inst_get (insn) == 0 &&
20515 - Field_w_Slot_inst_get (insn) == 0 &&
20516 - Field_r3_Slot_inst_get (insn) == 0 &&
20517 - Field_t3_Slot_inst_get (insn) == 0 &&
20518 - Field_tlo_Slot_inst_get (insn) == 0)
20519 - return 242; /* mul.dd.ll */
20522 - if (Field_s_Slot_inst_get (insn) == 0 &&
20523 - Field_w_Slot_inst_get (insn) == 0 &&
20524 - Field_r3_Slot_inst_get (insn) == 0 &&
20525 - Field_t3_Slot_inst_get (insn) == 0 &&
20526 - Field_tlo_Slot_inst_get (insn) == 0)
20527 - return 243; /* mul.dd.hl */
20530 - if (Field_s_Slot_inst_get (insn) == 0 &&
20531 - Field_w_Slot_inst_get (insn) == 0 &&
20532 - Field_r3_Slot_inst_get (insn) == 0 &&
20533 - Field_t3_Slot_inst_get (insn) == 0 &&
20534 - Field_tlo_Slot_inst_get (insn) == 0)
20535 - return 244; /* mul.dd.lh */
20538 - if (Field_s_Slot_inst_get (insn) == 0 &&
20539 - Field_w_Slot_inst_get (insn) == 0 &&
20540 - Field_r3_Slot_inst_get (insn) == 0 &&
20541 - Field_t3_Slot_inst_get (insn) == 0 &&
20542 - Field_tlo_Slot_inst_get (insn) == 0)
20543 - return 245; /* mul.dd.hh */
20546 - if (Field_s_Slot_inst_get (insn) == 0 &&
20547 - Field_w_Slot_inst_get (insn) == 0 &&
20548 - Field_r3_Slot_inst_get (insn) == 0 &&
20549 - Field_t3_Slot_inst_get (insn) == 0 &&
20550 - Field_tlo_Slot_inst_get (insn) == 0)
20551 - return 270; /* mula.dd.ll */
20554 - if (Field_s_Slot_inst_get (insn) == 0 &&
20555 - Field_w_Slot_inst_get (insn) == 0 &&
20556 - Field_r3_Slot_inst_get (insn) == 0 &&
20557 - Field_t3_Slot_inst_get (insn) == 0 &&
20558 - Field_tlo_Slot_inst_get (insn) == 0)
20559 - return 271; /* mula.dd.hl */
20562 - if (Field_s_Slot_inst_get (insn) == 0 &&
20563 - Field_w_Slot_inst_get (insn) == 0 &&
20564 - Field_r3_Slot_inst_get (insn) == 0 &&
20565 - Field_t3_Slot_inst_get (insn) == 0 &&
20566 - Field_tlo_Slot_inst_get (insn) == 0)
20567 - return 272; /* mula.dd.lh */
20570 - if (Field_s_Slot_inst_get (insn) == 0 &&
20571 - Field_w_Slot_inst_get (insn) == 0 &&
20572 - Field_r3_Slot_inst_get (insn) == 0 &&
20573 - Field_t3_Slot_inst_get (insn) == 0 &&
20574 - Field_tlo_Slot_inst_get (insn) == 0)
20575 - return 273; /* mula.dd.hh */
20578 - if (Field_s_Slot_inst_get (insn) == 0 &&
20579 - Field_w_Slot_inst_get (insn) == 0 &&
20580 - Field_r3_Slot_inst_get (insn) == 0 &&
20581 - Field_t3_Slot_inst_get (insn) == 0 &&
20582 - Field_tlo_Slot_inst_get (insn) == 0)
20583 - return 274; /* muls.dd.ll */
20586 - if (Field_s_Slot_inst_get (insn) == 0 &&
20587 - Field_w_Slot_inst_get (insn) == 0 &&
20588 - Field_r3_Slot_inst_get (insn) == 0 &&
20589 - Field_t3_Slot_inst_get (insn) == 0 &&
20590 - Field_tlo_Slot_inst_get (insn) == 0)
20591 - return 275; /* muls.dd.hl */
20594 - if (Field_s_Slot_inst_get (insn) == 0 &&
20595 - Field_w_Slot_inst_get (insn) == 0 &&
20596 - Field_r3_Slot_inst_get (insn) == 0 &&
20597 - Field_t3_Slot_inst_get (insn) == 0 &&
20598 - Field_tlo_Slot_inst_get (insn) == 0)
20599 - return 276; /* muls.dd.lh */
20602 - if (Field_s_Slot_inst_get (insn) == 0 &&
20603 - Field_w_Slot_inst_get (insn) == 0 &&
20604 - Field_r3_Slot_inst_get (insn) == 0 &&
20605 - Field_t3_Slot_inst_get (insn) == 0 &&
20606 - Field_tlo_Slot_inst_get (insn) == 0)
20607 - return 277; /* muls.dd.hh */
20612 - switch (Field_op1_Slot_inst_get (insn))
20615 - if (Field_r_Slot_inst_get (insn) == 0 &&
20616 - Field_t3_Slot_inst_get (insn) == 0 &&
20617 - Field_tlo_Slot_inst_get (insn) == 0)
20618 - return 234; /* mul.ad.ll */
20621 - if (Field_r_Slot_inst_get (insn) == 0 &&
20622 - Field_t3_Slot_inst_get (insn) == 0 &&
20623 - Field_tlo_Slot_inst_get (insn) == 0)
20624 - return 235; /* mul.ad.hl */
20627 - if (Field_r_Slot_inst_get (insn) == 0 &&
20628 - Field_t3_Slot_inst_get (insn) == 0 &&
20629 - Field_tlo_Slot_inst_get (insn) == 0)
20630 - return 236; /* mul.ad.lh */
20633 - if (Field_r_Slot_inst_get (insn) == 0 &&
20634 - Field_t3_Slot_inst_get (insn) == 0 &&
20635 - Field_tlo_Slot_inst_get (insn) == 0)
20636 - return 237; /* mul.ad.hh */
20639 - if (Field_r_Slot_inst_get (insn) == 0 &&
20640 - Field_t3_Slot_inst_get (insn) == 0 &&
20641 - Field_tlo_Slot_inst_get (insn) == 0)
20642 - return 254; /* mula.ad.ll */
20645 - if (Field_r_Slot_inst_get (insn) == 0 &&
20646 - Field_t3_Slot_inst_get (insn) == 0 &&
20647 - Field_tlo_Slot_inst_get (insn) == 0)
20648 - return 255; /* mula.ad.hl */
20651 - if (Field_r_Slot_inst_get (insn) == 0 &&
20652 - Field_t3_Slot_inst_get (insn) == 0 &&
20653 - Field_tlo_Slot_inst_get (insn) == 0)
20654 - return 256; /* mula.ad.lh */
20657 - if (Field_r_Slot_inst_get (insn) == 0 &&
20658 - Field_t3_Slot_inst_get (insn) == 0 &&
20659 - Field_tlo_Slot_inst_get (insn) == 0)
20660 - return 257; /* mula.ad.hh */
20663 - if (Field_r_Slot_inst_get (insn) == 0 &&
20664 - Field_t3_Slot_inst_get (insn) == 0 &&
20665 - Field_tlo_Slot_inst_get (insn) == 0)
20666 - return 258; /* muls.ad.ll */
20669 - if (Field_r_Slot_inst_get (insn) == 0 &&
20670 - Field_t3_Slot_inst_get (insn) == 0 &&
20671 - Field_tlo_Slot_inst_get (insn) == 0)
20672 - return 259; /* muls.ad.hl */
20675 - if (Field_r_Slot_inst_get (insn) == 0 &&
20676 - Field_t3_Slot_inst_get (insn) == 0 &&
20677 - Field_tlo_Slot_inst_get (insn) == 0)
20678 - return 260; /* muls.ad.lh */
20681 - if (Field_r_Slot_inst_get (insn) == 0 &&
20682 - Field_t3_Slot_inst_get (insn) == 0 &&
20683 - Field_tlo_Slot_inst_get (insn) == 0)
20684 - return 261; /* muls.ad.hh */
20689 - switch (Field_op1_Slot_inst_get (insn))
20692 - if (Field_r3_Slot_inst_get (insn) == 0)
20693 - return 279; /* mula.da.ll.ldinc */
20696 - if (Field_r3_Slot_inst_get (insn) == 0)
20697 - return 281; /* mula.da.hl.ldinc */
20700 - if (Field_r3_Slot_inst_get (insn) == 0)
20701 - return 283; /* mula.da.lh.ldinc */
20704 - if (Field_r3_Slot_inst_get (insn) == 0)
20705 - return 285; /* mula.da.hh.ldinc */
20710 - switch (Field_op1_Slot_inst_get (insn))
20713 - if (Field_r3_Slot_inst_get (insn) == 0)
20714 - return 278; /* mula.da.ll.lddec */
20717 - if (Field_r3_Slot_inst_get (insn) == 0)
20718 - return 280; /* mula.da.hl.lddec */
20721 - if (Field_r3_Slot_inst_get (insn) == 0)
20722 - return 282; /* mula.da.lh.lddec */
20725 - if (Field_r3_Slot_inst_get (insn) == 0)
20726 - return 284; /* mula.da.hh.lddec */
20731 - switch (Field_op1_Slot_inst_get (insn))
20734 - if (Field_s_Slot_inst_get (insn) == 0 &&
20735 - Field_w_Slot_inst_get (insn) == 0 &&
20736 - Field_r3_Slot_inst_get (insn) == 0)
20737 - return 238; /* mul.da.ll */
20740 - if (Field_s_Slot_inst_get (insn) == 0 &&
20741 - Field_w_Slot_inst_get (insn) == 0 &&
20742 - Field_r3_Slot_inst_get (insn) == 0)
20743 - return 239; /* mul.da.hl */
20746 - if (Field_s_Slot_inst_get (insn) == 0 &&
20747 - Field_w_Slot_inst_get (insn) == 0 &&
20748 - Field_r3_Slot_inst_get (insn) == 0)
20749 - return 240; /* mul.da.lh */
20752 - if (Field_s_Slot_inst_get (insn) == 0 &&
20753 - Field_w_Slot_inst_get (insn) == 0 &&
20754 - Field_r3_Slot_inst_get (insn) == 0)
20755 - return 241; /* mul.da.hh */
20758 - if (Field_s_Slot_inst_get (insn) == 0 &&
20759 - Field_w_Slot_inst_get (insn) == 0 &&
20760 - Field_r3_Slot_inst_get (insn) == 0)
20761 - return 262; /* mula.da.ll */
20764 - if (Field_s_Slot_inst_get (insn) == 0 &&
20765 - Field_w_Slot_inst_get (insn) == 0 &&
20766 - Field_r3_Slot_inst_get (insn) == 0)
20767 - return 263; /* mula.da.hl */
20770 - if (Field_s_Slot_inst_get (insn) == 0 &&
20771 - Field_w_Slot_inst_get (insn) == 0 &&
20772 - Field_r3_Slot_inst_get (insn) == 0)
20773 - return 264; /* mula.da.lh */
20776 - if (Field_s_Slot_inst_get (insn) == 0 &&
20777 - Field_w_Slot_inst_get (insn) == 0 &&
20778 - Field_r3_Slot_inst_get (insn) == 0)
20779 - return 265; /* mula.da.hh */
20782 - if (Field_s_Slot_inst_get (insn) == 0 &&
20783 - Field_w_Slot_inst_get (insn) == 0 &&
20784 - Field_r3_Slot_inst_get (insn) == 0)
20785 - return 266; /* muls.da.ll */
20788 - if (Field_s_Slot_inst_get (insn) == 0 &&
20789 - Field_w_Slot_inst_get (insn) == 0 &&
20790 - Field_r3_Slot_inst_get (insn) == 0)
20791 - return 267; /* muls.da.hl */
20794 - if (Field_s_Slot_inst_get (insn) == 0 &&
20795 - Field_w_Slot_inst_get (insn) == 0 &&
20796 - Field_r3_Slot_inst_get (insn) == 0)
20797 - return 268; /* muls.da.lh */
20800 - if (Field_s_Slot_inst_get (insn) == 0 &&
20801 - Field_w_Slot_inst_get (insn) == 0 &&
20802 - Field_r3_Slot_inst_get (insn) == 0)
20803 - return 269; /* muls.da.hh */
20808 - switch (Field_op1_Slot_inst_get (insn))
20811 - if (Field_r_Slot_inst_get (insn) == 0)
20812 - return 230; /* umul.aa.ll */
20815 - if (Field_r_Slot_inst_get (insn) == 0)
20816 - return 231; /* umul.aa.hl */
20819 - if (Field_r_Slot_inst_get (insn) == 0)
20820 - return 232; /* umul.aa.lh */
20823 - if (Field_r_Slot_inst_get (insn) == 0)
20824 - return 233; /* umul.aa.hh */
20827 - if (Field_r_Slot_inst_get (insn) == 0)
20828 - return 226; /* mul.aa.ll */
20831 - if (Field_r_Slot_inst_get (insn) == 0)
20832 - return 227; /* mul.aa.hl */
20835 - if (Field_r_Slot_inst_get (insn) == 0)
20836 - return 228; /* mul.aa.lh */
20839 - if (Field_r_Slot_inst_get (insn) == 0)
20840 - return 229; /* mul.aa.hh */
20843 - if (Field_r_Slot_inst_get (insn) == 0)
20844 - return 246; /* mula.aa.ll */
20847 - if (Field_r_Slot_inst_get (insn) == 0)
20848 - return 247; /* mula.aa.hl */
20851 - if (Field_r_Slot_inst_get (insn) == 0)
20852 - return 248; /* mula.aa.lh */
20855 - if (Field_r_Slot_inst_get (insn) == 0)
20856 - return 249; /* mula.aa.hh */
20859 - if (Field_r_Slot_inst_get (insn) == 0)
20860 - return 250; /* muls.aa.ll */
20863 - if (Field_r_Slot_inst_get (insn) == 0)
20864 - return 251; /* muls.aa.hl */
20867 - if (Field_r_Slot_inst_get (insn) == 0)
20868 - return 252; /* muls.aa.lh */
20871 - if (Field_r_Slot_inst_get (insn) == 0)
20872 - return 253; /* muls.aa.hh */
20877 - if (Field_op1_Slot_inst_get (insn) == 0 &&
20878 - Field_t_Slot_inst_get (insn) == 0 &&
20879 - Field_rhi_Slot_inst_get (insn) == 0)
20880 - return 295; /* ldinc */
20883 - if (Field_op1_Slot_inst_get (insn) == 0 &&
20884 - Field_t_Slot_inst_get (insn) == 0 &&
20885 - Field_rhi_Slot_inst_get (insn) == 0)
20886 - return 294; /* lddec */
20891 - switch (Field_n_Slot_inst_get (insn))
20894 - return 76; /* call0 */
20896 - return 7; /* call4 */
20898 - return 6; /* call8 */
20900 - return 5; /* call12 */
20904 - switch (Field_n_Slot_inst_get (insn))
20907 - return 80; /* j */
20909 - switch (Field_m_Slot_inst_get (insn))
20912 - return 72; /* beqz */
20914 - return 73; /* bnez */
20916 - return 75; /* bltz */
20918 - return 74; /* bgez */
20922 - switch (Field_m_Slot_inst_get (insn))
20925 - return 52; /* beqi */
20927 - return 53; /* bnei */
20929 - return 55; /* blti */
20931 - return 54; /* bgei */
20935 - switch (Field_m_Slot_inst_get (insn))
20938 - return 11; /* entry */
20940 - switch (Field_r_Slot_inst_get (insn))
20943 - return 371; /* bf */
20945 - return 372; /* bt */
20947 - return 87; /* loop */
20949 - return 88; /* loopnez */
20951 - return 89; /* loopgtz */
20955 - return 59; /* bltui */
20957 - return 58; /* bgeui */
20963 - switch (Field_r_Slot_inst_get (insn))
20966 - return 67; /* bnone */
20968 - return 60; /* beq */
20970 - return 63; /* blt */
20972 - return 65; /* bltu */
20974 - return 68; /* ball */
20976 - return 70; /* bbc */
20979 - return 56; /* bbci */
20981 - return 66; /* bany */
20983 - return 61; /* bne */
20985 - return 62; /* bge */
20987 - return 64; /* bgeu */
20989 - return 69; /* bnall */
20991 - return 71; /* bbs */
20994 - return 57; /* bbsi */
20999 +static xtensa_iclass_internal iclasses[] = {
21000 + { 0, 0 /* xt_iclass_excw */,
21002 + { 0, 0 /* xt_iclass_rfe */,
21003 + 2, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
21004 + { 0, 0 /* xt_iclass_rfde */,
21005 + 1, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
21006 + { 0, 0 /* xt_iclass_syscall */,
21008 + { 0, 0 /* xt_iclass_simcall */,
21010 + { 2, Iclass_xt_iclass_call12_args,
21011 + 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
21012 + { 2, Iclass_xt_iclass_call8_args,
21013 + 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 },
21014 + { 2, Iclass_xt_iclass_call4_args,
21015 + 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 },
21016 + { 2, Iclass_xt_iclass_callx12_args,
21017 + 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 },
21018 + { 2, Iclass_xt_iclass_callx8_args,
21019 + 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 },
21020 + { 2, Iclass_xt_iclass_callx4_args,
21021 + 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 },
21022 + { 3, Iclass_xt_iclass_entry_args,
21023 + 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 },
21024 + { 2, Iclass_xt_iclass_movsp_args,
21025 + 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 },
21026 + { 1, Iclass_xt_iclass_rotw_args,
21027 + 1, Iclass_xt_iclass_rotw_stateArgs, 0, 0 },
21028 + { 1, Iclass_xt_iclass_retw_args,
21029 + 4, Iclass_xt_iclass_retw_stateArgs, 0, 0 },
21030 + { 0, 0 /* xt_iclass_rfwou */,
21031 + 5, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 },
21032 + { 3, Iclass_xt_iclass_l32e_args,
21034 + { 3, Iclass_xt_iclass_s32e_args,
21036 + { 1, Iclass_xt_iclass_rsr_windowbase_args,
21037 + 1, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 },
21038 + { 1, Iclass_xt_iclass_wsr_windowbase_args,
21039 + 1, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 },
21040 + { 1, Iclass_xt_iclass_xsr_windowbase_args,
21041 + 1, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 },
21042 + { 1, Iclass_xt_iclass_rsr_windowstart_args,
21043 + 1, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 },
21044 + { 1, Iclass_xt_iclass_wsr_windowstart_args,
21045 + 1, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 },
21046 + { 1, Iclass_xt_iclass_xsr_windowstart_args,
21047 + 1, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 },
21048 + { 3, Iclass_xt_iclass_add_n_args,
21050 + { 3, Iclass_xt_iclass_addi_n_args,
21052 + { 2, Iclass_xt_iclass_bz6_args,
21054 + { 0, 0 /* xt_iclass_ill_n */,
21056 + { 3, Iclass_xt_iclass_loadi4_args,
21058 + { 2, Iclass_xt_iclass_mov_n_args,
21060 + { 2, Iclass_xt_iclass_movi_n_args,
21062 + { 0, 0 /* xt_iclass_nopn */,
21064 + { 1, Iclass_xt_iclass_retn_args,
21066 + { 3, Iclass_xt_iclass_storei4_args,
21068 + { 1, Iclass_rur_threadptr_args,
21069 + 1, Iclass_rur_threadptr_stateArgs, 0, 0 },
21070 + { 1, Iclass_wur_threadptr_args,
21071 + 1, Iclass_wur_threadptr_stateArgs, 0, 0 },
21072 + { 3, Iclass_xt_iclass_addi_args,
21074 + { 3, Iclass_xt_iclass_addmi_args,
21076 + { 3, Iclass_xt_iclass_addsub_args,
21078 + { 3, Iclass_xt_iclass_bit_args,
21080 + { 3, Iclass_xt_iclass_bsi8_args,
21082 + { 3, Iclass_xt_iclass_bsi8b_args,
21084 + { 3, Iclass_xt_iclass_bsi8u_args,
21086 + { 3, Iclass_xt_iclass_bst8_args,
21088 + { 2, Iclass_xt_iclass_bsz12_args,
21090 + { 2, Iclass_xt_iclass_call0_args,
21092 + { 2, Iclass_xt_iclass_callx0_args,
21094 + { 4, Iclass_xt_iclass_exti_args,
21096 + { 0, 0 /* xt_iclass_ill */,
21098 + { 1, Iclass_xt_iclass_jump_args,
21100 + { 1, Iclass_xt_iclass_jumpx_args,
21102 + { 3, Iclass_xt_iclass_l16ui_args,
21104 + { 3, Iclass_xt_iclass_l16si_args,
21106 + { 3, Iclass_xt_iclass_l32i_args,
21108 + { 2, Iclass_xt_iclass_l32r_args,
21109 + 2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 },
21110 + { 3, Iclass_xt_iclass_l8i_args,
21112 + { 2, Iclass_xt_iclass_loop_args,
21113 + 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 },
21114 + { 2, Iclass_xt_iclass_loopz_args,
21115 + 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 },
21116 + { 2, Iclass_xt_iclass_movi_args,
21118 + { 3, Iclass_xt_iclass_movz_args,
21120 + { 2, Iclass_xt_iclass_neg_args,
21122 + { 0, 0 /* xt_iclass_nop */,
21124 + { 1, Iclass_xt_iclass_return_args,
21126 + { 3, Iclass_xt_iclass_s16i_args,
21128 + { 3, Iclass_xt_iclass_s32i_args,
21130 + { 3, Iclass_xt_iclass_s8i_args,
21132 + { 1, Iclass_xt_iclass_sar_args,
21133 + 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
21134 + { 1, Iclass_xt_iclass_sari_args,
21135 + 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
21136 + { 2, Iclass_xt_iclass_shifts_args,
21137 + 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
21138 + { 3, Iclass_xt_iclass_shiftst_args,
21139 + 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
21140 + { 2, Iclass_xt_iclass_shiftt_args,
21141 + 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
21142 + { 3, Iclass_xt_iclass_slli_args,
21144 + { 3, Iclass_xt_iclass_srai_args,
21146 + { 3, Iclass_xt_iclass_srli_args,
21148 + { 0, 0 /* xt_iclass_memw */,
21150 + { 0, 0 /* xt_iclass_extw */,
21152 + { 0, 0 /* xt_iclass_isync */,
21154 + { 0, 0 /* xt_iclass_sync */,
21155 + 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
21156 + { 2, Iclass_xt_iclass_rsil_args,
21157 + 6, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
21158 + { 1, Iclass_xt_iclass_rsr_lend_args,
21159 + 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 },
21160 + { 1, Iclass_xt_iclass_wsr_lend_args,
21161 + 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 },
21162 + { 1, Iclass_xt_iclass_xsr_lend_args,
21163 + 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 },
21164 + { 1, Iclass_xt_iclass_rsr_lcount_args,
21165 + 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 },
21166 + { 1, Iclass_xt_iclass_wsr_lcount_args,
21167 + 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 },
21168 + { 1, Iclass_xt_iclass_xsr_lcount_args,
21169 + 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 },
21170 + { 1, Iclass_xt_iclass_rsr_lbeg_args,
21171 + 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 },
21172 + { 1, Iclass_xt_iclass_wsr_lbeg_args,
21173 + 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 },
21174 + { 1, Iclass_xt_iclass_xsr_lbeg_args,
21175 + 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 },
21176 + { 1, Iclass_xt_iclass_rsr_sar_args,
21177 + 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
21178 + { 1, Iclass_xt_iclass_wsr_sar_args,
21179 + 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
21180 + { 1, Iclass_xt_iclass_xsr_sar_args,
21181 + 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
21182 + { 1, Iclass_xt_iclass_rsr_litbase_args,
21183 + 2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 },
21184 + { 1, Iclass_xt_iclass_wsr_litbase_args,
21185 + 2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 },
21186 + { 1, Iclass_xt_iclass_xsr_litbase_args,
21187 + 2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 },
21188 + { 1, Iclass_xt_iclass_rsr_176_args,
21190 + { 1, Iclass_xt_iclass_rsr_208_args,
21192 + { 1, Iclass_xt_iclass_rsr_ps_args,
21193 + 6, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
21194 + { 1, Iclass_xt_iclass_wsr_ps_args,
21195 + 6, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
21196 + { 1, Iclass_xt_iclass_xsr_ps_args,
21197 + 6, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
21198 + { 1, Iclass_xt_iclass_rsr_epc1_args,
21199 + 1, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
21200 + { 1, Iclass_xt_iclass_wsr_epc1_args,
21201 + 1, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
21202 + { 1, Iclass_xt_iclass_xsr_epc1_args,
21203 + 1, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
21204 + { 1, Iclass_xt_iclass_rsr_excsave1_args,
21205 + 1, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
21206 + { 1, Iclass_xt_iclass_wsr_excsave1_args,
21207 + 1, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
21208 + { 1, Iclass_xt_iclass_xsr_excsave1_args,
21209 + 1, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
21210 + { 1, Iclass_xt_iclass_rsr_epc2_args,
21211 + 1, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
21212 + { 1, Iclass_xt_iclass_wsr_epc2_args,
21213 + 1, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
21214 + { 1, Iclass_xt_iclass_xsr_epc2_args,
21215 + 1, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
21216 + { 1, Iclass_xt_iclass_rsr_excsave2_args,
21217 + 1, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
21218 + { 1, Iclass_xt_iclass_wsr_excsave2_args,
21219 + 1, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
21220 + { 1, Iclass_xt_iclass_xsr_excsave2_args,
21221 + 1, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
21222 + { 1, Iclass_xt_iclass_rsr_epc3_args,
21223 + 1, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 },
21224 + { 1, Iclass_xt_iclass_wsr_epc3_args,
21225 + 1, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 },
21226 + { 1, Iclass_xt_iclass_xsr_epc3_args,
21227 + 1, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 },
21228 + { 1, Iclass_xt_iclass_rsr_excsave3_args,
21229 + 1, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 },
21230 + { 1, Iclass_xt_iclass_wsr_excsave3_args,
21231 + 1, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 },
21232 + { 1, Iclass_xt_iclass_xsr_excsave3_args,
21233 + 1, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 },
21234 + { 1, Iclass_xt_iclass_rsr_epc4_args,
21235 + 1, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 },
21236 + { 1, Iclass_xt_iclass_wsr_epc4_args,
21237 + 1, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 },
21238 + { 1, Iclass_xt_iclass_xsr_epc4_args,
21239 + 1, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 },
21240 + { 1, Iclass_xt_iclass_rsr_excsave4_args,
21241 + 1, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 },
21242 + { 1, Iclass_xt_iclass_wsr_excsave4_args,
21243 + 1, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 },
21244 + { 1, Iclass_xt_iclass_xsr_excsave4_args,
21245 + 1, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 },
21246 + { 1, Iclass_xt_iclass_rsr_epc5_args,
21247 + 1, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 },
21248 + { 1, Iclass_xt_iclass_wsr_epc5_args,
21249 + 1, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 },
21250 + { 1, Iclass_xt_iclass_xsr_epc5_args,
21251 + 1, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 },
21252 + { 1, Iclass_xt_iclass_rsr_excsave5_args,
21253 + 1, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 },
21254 + { 1, Iclass_xt_iclass_wsr_excsave5_args,
21255 + 1, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 },
21256 + { 1, Iclass_xt_iclass_xsr_excsave5_args,
21257 + 1, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 },
21258 + { 1, Iclass_xt_iclass_rsr_eps2_args,
21259 + 1, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
21260 + { 1, Iclass_xt_iclass_wsr_eps2_args,
21261 + 1, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
21262 + { 1, Iclass_xt_iclass_xsr_eps2_args,
21263 + 1, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
21264 + { 1, Iclass_xt_iclass_rsr_eps3_args,
21265 + 1, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 },
21266 + { 1, Iclass_xt_iclass_wsr_eps3_args,
21267 + 1, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 },
21268 + { 1, Iclass_xt_iclass_xsr_eps3_args,
21269 + 1, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 },
21270 + { 1, Iclass_xt_iclass_rsr_eps4_args,
21271 + 1, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 },
21272 + { 1, Iclass_xt_iclass_wsr_eps4_args,
21273 + 1, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 },
21274 + { 1, Iclass_xt_iclass_xsr_eps4_args,
21275 + 1, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 },
21276 + { 1, Iclass_xt_iclass_rsr_eps5_args,
21277 + 1, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 },
21278 + { 1, Iclass_xt_iclass_wsr_eps5_args,
21279 + 1, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 },
21280 + { 1, Iclass_xt_iclass_xsr_eps5_args,
21281 + 1, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 },
21282 + { 1, Iclass_xt_iclass_rsr_excvaddr_args,
21283 + 1, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
21284 + { 1, Iclass_xt_iclass_wsr_excvaddr_args,
21285 + 1, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
21286 + { 1, Iclass_xt_iclass_xsr_excvaddr_args,
21287 + 1, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
21288 + { 1, Iclass_xt_iclass_rsr_depc_args,
21289 + 1, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
21290 + { 1, Iclass_xt_iclass_wsr_depc_args,
21291 + 1, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
21292 + { 1, Iclass_xt_iclass_xsr_depc_args,
21293 + 1, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
21294 + { 1, Iclass_xt_iclass_rsr_exccause_args,
21295 + 2, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
21296 + { 1, Iclass_xt_iclass_wsr_exccause_args,
21297 + 1, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
21298 + { 1, Iclass_xt_iclass_xsr_exccause_args,
21299 + 1, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
21300 + { 1, Iclass_xt_iclass_rsr_misc0_args,
21301 + 1, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 },
21302 + { 1, Iclass_xt_iclass_wsr_misc0_args,
21303 + 1, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 },
21304 + { 1, Iclass_xt_iclass_xsr_misc0_args,
21305 + 1, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 },
21306 + { 1, Iclass_xt_iclass_rsr_misc1_args,
21307 + 1, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 },
21308 + { 1, Iclass_xt_iclass_wsr_misc1_args,
21309 + 1, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 },
21310 + { 1, Iclass_xt_iclass_xsr_misc1_args,
21311 + 1, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 },
21312 + { 1, Iclass_xt_iclass_rsr_prid_args,
21314 + { 1, Iclass_xt_iclass_rsr_vecbase_args,
21315 + 1, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 },
21316 + { 1, Iclass_xt_iclass_wsr_vecbase_args,
21317 + 1, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 },
21318 + { 1, Iclass_xt_iclass_xsr_vecbase_args,
21319 + 1, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 },
21320 + { 1, Iclass_xt_iclass_rfi_args,
21321 + 16, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
21322 + { 1, Iclass_xt_iclass_wait_args,
21323 + 1, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
21324 + { 1, Iclass_xt_iclass_rsr_interrupt_args,
21325 + 1, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
21326 + { 1, Iclass_xt_iclass_wsr_intset_args,
21327 + 2, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
21328 + { 1, Iclass_xt_iclass_wsr_intclear_args,
21329 + 2, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
21330 + { 1, Iclass_xt_iclass_rsr_intenable_args,
21331 + 1, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
21332 + { 1, Iclass_xt_iclass_wsr_intenable_args,
21333 + 1, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
21334 + { 1, Iclass_xt_iclass_xsr_intenable_args,
21335 + 1, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
21336 + { 2, Iclass_xt_iclass_break_args,
21337 + 2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
21338 + { 1, Iclass_xt_iclass_break_n_args,
21339 + 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
21340 + { 1, Iclass_xt_iclass_rsr_dbreaka0_args,
21341 + 1, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 },
21342 + { 1, Iclass_xt_iclass_wsr_dbreaka0_args,
21343 + 2, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 },
21344 + { 1, Iclass_xt_iclass_xsr_dbreaka0_args,
21345 + 2, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 },
21346 + { 1, Iclass_xt_iclass_rsr_dbreakc0_args,
21347 + 1, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 },
21348 + { 1, Iclass_xt_iclass_wsr_dbreakc0_args,
21349 + 2, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 },
21350 + { 1, Iclass_xt_iclass_xsr_dbreakc0_args,
21351 + 2, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 },
21352 + { 1, Iclass_xt_iclass_rsr_dbreaka1_args,
21353 + 1, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 },
21354 + { 1, Iclass_xt_iclass_wsr_dbreaka1_args,
21355 + 2, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 },
21356 + { 1, Iclass_xt_iclass_xsr_dbreaka1_args,
21357 + 2, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 },
21358 + { 1, Iclass_xt_iclass_rsr_dbreakc1_args,
21359 + 1, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 },
21360 + { 1, Iclass_xt_iclass_wsr_dbreakc1_args,
21361 + 2, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 },
21362 + { 1, Iclass_xt_iclass_xsr_dbreakc1_args,
21363 + 2, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 },
21364 + { 1, Iclass_xt_iclass_rsr_ibreaka0_args,
21365 + 1, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 },
21366 + { 1, Iclass_xt_iclass_wsr_ibreaka0_args,
21367 + 1, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 },
21368 + { 1, Iclass_xt_iclass_xsr_ibreaka0_args,
21369 + 1, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 },
21370 + { 1, Iclass_xt_iclass_rsr_ibreaka1_args,
21371 + 1, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 },
21372 + { 1, Iclass_xt_iclass_wsr_ibreaka1_args,
21373 + 1, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 },
21374 + { 1, Iclass_xt_iclass_xsr_ibreaka1_args,
21375 + 1, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 },
21376 + { 1, Iclass_xt_iclass_rsr_ibreakenable_args,
21377 + 1, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 },
21378 + { 1, Iclass_xt_iclass_wsr_ibreakenable_args,
21379 + 1, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 },
21380 + { 1, Iclass_xt_iclass_xsr_ibreakenable_args,
21381 + 1, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 },
21382 + { 1, Iclass_xt_iclass_rsr_debugcause_args,
21383 + 2, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
21384 + { 1, Iclass_xt_iclass_wsr_debugcause_args,
21385 + 2, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
21386 + { 1, Iclass_xt_iclass_xsr_debugcause_args,
21387 + 2, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
21388 + { 1, Iclass_xt_iclass_rsr_icount_args,
21389 + 1, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
21390 + { 1, Iclass_xt_iclass_wsr_icount_args,
21391 + 2, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
21392 + { 1, Iclass_xt_iclass_xsr_icount_args,
21393 + 2, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
21394 + { 1, Iclass_xt_iclass_rsr_icountlevel_args,
21395 + 1, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
21396 + { 1, Iclass_xt_iclass_wsr_icountlevel_args,
21397 + 1, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
21398 + { 1, Iclass_xt_iclass_xsr_icountlevel_args,
21399 + 1, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
21400 + { 1, Iclass_xt_iclass_rsr_ddr_args,
21401 + 1, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
21402 + { 1, Iclass_xt_iclass_wsr_ddr_args,
21403 + 2, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
21404 + { 1, Iclass_xt_iclass_xsr_ddr_args,
21405 + 2, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
21406 + { 1, Iclass_xt_iclass_rfdo_args,
21407 + 9, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
21408 + { 0, 0 /* xt_iclass_rfdd */,
21409 + 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
21410 + { 1, Iclass_xt_iclass_wsr_mmid_args,
21411 + 1, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 },
21412 + { 1, Iclass_xt_iclass_rsr_ccount_args,
21413 + 1, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
21414 + { 1, Iclass_xt_iclass_wsr_ccount_args,
21415 + 2, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
21416 + { 1, Iclass_xt_iclass_xsr_ccount_args,
21417 + 2, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
21418 + { 1, Iclass_xt_iclass_rsr_ccompare0_args,
21419 + 1, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
21420 + { 1, Iclass_xt_iclass_wsr_ccompare0_args,
21421 + 2, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
21422 + { 1, Iclass_xt_iclass_xsr_ccompare0_args,
21423 + 2, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
21424 + { 1, Iclass_xt_iclass_idtlb_args,
21425 + 1, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
21426 + { 2, Iclass_xt_iclass_rdtlb_args,
21428 + { 2, Iclass_xt_iclass_wdtlb_args,
21429 + 1, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
21430 + { 1, Iclass_xt_iclass_iitlb_args,
21432 + { 2, Iclass_xt_iclass_ritlb_args,
21434 + { 2, Iclass_xt_iclass_witlb_args,
21436 + { 3, Iclass_xt_iclass_minmax_args,
21438 + { 2, Iclass_xt_iclass_nsa_args,
21440 + { 3, Iclass_xt_iclass_sx_args,
21442 + { 3, Iclass_xt_iclass_l32ai_args,
21444 + { 3, Iclass_xt_iclass_s32ri_args,
21446 + { 3, Iclass_xt_iclass_s32c1i_args,
21447 + 2, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 },
21448 + { 1, Iclass_xt_iclass_rsr_scompare1_args,
21449 + 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 },
21450 + { 1, Iclass_xt_iclass_wsr_scompare1_args,
21451 + 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 },
21452 + { 1, Iclass_xt_iclass_xsr_scompare1_args,
21453 + 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 },
21454 + { 3, Iclass_xt_mul32_args,
21459 +/* Opcode encodings. */
21462 +Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf)
21464 + slotbuf[0] = 0x80200;
21468 +Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf)
21470 + slotbuf[0] = 0x300;
21474 +Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf)
21476 + slotbuf[0] = 0x2300;
21480 +Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf)
21482 + slotbuf[0] = 0x500;
21486 +Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf)
21488 + slotbuf[0] = 0x1500;
21492 +Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf)
21494 + slotbuf[0] = 0x5c0000;
21498 +Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf)
21500 + slotbuf[0] = 0x580000;
21504 +Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf)
21506 + slotbuf[0] = 0x540000;
21510 +Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf)
21512 + slotbuf[0] = 0xf0000;
21516 +Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
21518 + slotbuf[0] = 0xb0000;
21522 +Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
21524 + slotbuf[0] = 0x70000;
21528 +Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf)
21530 + slotbuf[0] = 0x6c0000;
21534 +Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf)
21536 + slotbuf[0] = 0x100;
21540 +Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf)
21542 + slotbuf[0] = 0x804;
21546 +Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf)
21548 + slotbuf[0] = 0x60000;
21552 +Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
21554 + slotbuf[0] = 0xd10f;
21558 +Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
21560 + slotbuf[0] = 0x4300;
21564 +Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21566 + slotbuf[0] = 0x5300;
21570 +Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
21572 + slotbuf[0] = 0x90;
21576 +Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
21578 + slotbuf[0] = 0x94;
21582 +Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
21584 + slotbuf[0] = 0x4830;
21588 +Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
21590 + slotbuf[0] = 0x4831;
21594 +Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
21596 + slotbuf[0] = 0x4816;
21600 +Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
21602 + slotbuf[0] = 0x4930;
21606 +Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
21608 + slotbuf[0] = 0x4931;
21612 +Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
21614 + slotbuf[0] = 0x4916;
21618 +Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
21620 + slotbuf[0] = 0xa000;
21624 +Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
21626 + slotbuf[0] = 0xb000;
21630 +Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
21632 + slotbuf[0] = 0xc800;
21636 +Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
21638 + slotbuf[0] = 0xcc00;
21642 +Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
21644 + slotbuf[0] = 0xd60f;
21648 +Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
21650 + slotbuf[0] = 0x8000;
21654 +Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
21656 + slotbuf[0] = 0xd000;
21660 +Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
21662 + slotbuf[0] = 0xc000;
21666 +Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
21668 + slotbuf[0] = 0xd30f;
21672 +Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
21674 + slotbuf[0] = 0xd00f;
21678 +Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
21680 + slotbuf[0] = 0x9000;
21684 +Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
21686 + slotbuf[0] = 0x7e03e;
21690 +Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
21692 + slotbuf[0] = 0xe73f;
21696 +Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf)
21698 + slotbuf[0] = 0x200c00;
21702 +Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf)
21704 + slotbuf[0] = 0x200d00;
21708 +Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf)
21710 + slotbuf[0] = 0x8;
21714 +Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf)
21716 + slotbuf[0] = 0xc;
21720 +Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
21722 + slotbuf[0] = 0x9;
21726 +Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
21728 + slotbuf[0] = 0xa;
21732 +Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
21734 + slotbuf[0] = 0xb;
21738 +Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
21740 + slotbuf[0] = 0xd;
21744 +Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
21746 + slotbuf[0] = 0xe;
21750 +Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
21752 + slotbuf[0] = 0xf;
21756 +Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf)
21758 + slotbuf[0] = 0x1;
21762 +Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf)
21764 + slotbuf[0] = 0x2;
21768 +Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf)
21770 + slotbuf[0] = 0x3;
21774 +Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf)
21776 + slotbuf[0] = 0x680000;
21780 +Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf)
21782 + slotbuf[0] = 0x690000;
21786 +Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf)
21788 + slotbuf[0] = 0x6b0000;
21792 +Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf)
21794 + slotbuf[0] = 0x6a0000;
21798 +Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf)
21800 + slotbuf[0] = 0x700600;
21804 +Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
21806 + slotbuf[0] = 0x700e00;
21810 +Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf)
21812 + slotbuf[0] = 0x6f0000;
21816 +Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf)
21818 + slotbuf[0] = 0x6e0000;
21822 +Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf)
21824 + slotbuf[0] = 0x700100;
21828 +Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf)
21830 + slotbuf[0] = 0x700900;
21834 +Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf)
21836 + slotbuf[0] = 0x700a00;
21840 +Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf)
21842 + slotbuf[0] = 0x700200;
21846 +Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21848 + slotbuf[0] = 0x700b00;
21852 +Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21854 + slotbuf[0] = 0x700300;
21858 +Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf)
21860 + slotbuf[0] = 0x700800;
21864 +Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf)
21866 + slotbuf[0] = 0x700000;
21870 +Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf)
21872 + slotbuf[0] = 0x700400;
21876 +Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf)
21878 + slotbuf[0] = 0x700c00;
21882 +Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
21884 + slotbuf[0] = 0x700500;
21888 +Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf)
21890 + slotbuf[0] = 0x700d00;
21894 +Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
21896 + slotbuf[0] = 0x640000;
21900 +Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
21902 + slotbuf[0] = 0x650000;
21906 +Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
21908 + slotbuf[0] = 0x670000;
21912 +Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
21914 + slotbuf[0] = 0x660000;
21918 +Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf)
21920 + slotbuf[0] = 0x500000;
21924 +Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf)
21926 + slotbuf[0] = 0x30000;
21930 +Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf)
21932 + slotbuf[0] = 0x40;
21936 +Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf)
21942 +Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf)
21944 + slotbuf[0] = 0x600000;
21948 +Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf)
21950 + slotbuf[0] = 0xa0000;
21954 +Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
21956 + slotbuf[0] = 0x200100;
21960 +Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf)
21962 + slotbuf[0] = 0x200900;
21966 +Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
21968 + slotbuf[0] = 0x200200;
21972 +Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf)
21974 + slotbuf[0] = 0x100000;
21978 +Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
21980 + slotbuf[0] = 0x200000;
21984 +Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf)
21986 + slotbuf[0] = 0x6d0800;
21990 +Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
21992 + slotbuf[0] = 0x6d0900;
21996 +Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf)
21998 + slotbuf[0] = 0x6d0a00;
22002 +Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf)
22004 + slotbuf[0] = 0x200a00;
22008 +Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
22010 + slotbuf[0] = 0x38;
22014 +Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
22016 + slotbuf[0] = 0x39;
22020 +Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
22022 + slotbuf[0] = 0x3a;
22026 +Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
22028 + slotbuf[0] = 0x3b;
22032 +Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf)
22034 + slotbuf[0] = 0x6;
22038 +Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf)
22040 + slotbuf[0] = 0x1006;
22044 +Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf)
22046 + slotbuf[0] = 0xf0200;
22050 +Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf)
22052 + slotbuf[0] = 0x20000;
22056 +Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf)
22058 + slotbuf[0] = 0x200500;
22062 +Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
22064 + slotbuf[0] = 0x200600;
22068 +Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf)
22070 + slotbuf[0] = 0x200400;
22074 +Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf)
22076 + slotbuf[0] = 0x4;
22080 +Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf)
22082 + slotbuf[0] = 0x104;
22086 +Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf)
22088 + slotbuf[0] = 0x204;
22092 +Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf)
22094 + slotbuf[0] = 0x304;
22098 +Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf)
22100 + slotbuf[0] = 0x404;
22104 +Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf)
22106 + slotbuf[0] = 0x1a;
22110 +Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf)
22112 + slotbuf[0] = 0x18;
22116 +Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf)
22118 + slotbuf[0] = 0x19;
22122 +Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf)
22124 + slotbuf[0] = 0x1b;
22128 +Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf)
22130 + slotbuf[0] = 0x10;
22134 +Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf)
22136 + slotbuf[0] = 0x12;
22140 +Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf)
22142 + slotbuf[0] = 0x14;
22146 +Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf)
22148 + slotbuf[0] = 0xc0200;
22152 +Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf)
22154 + slotbuf[0] = 0xd0200;
22158 +Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf)
22160 + slotbuf[0] = 0x200;
22164 +Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
22166 + slotbuf[0] = 0x10200;
22170 +Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf)
22172 + slotbuf[0] = 0x20200;
22176 +Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
22178 + slotbuf[0] = 0x30200;
22182 +Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf)
22184 + slotbuf[0] = 0x600;
22188 +Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
22190 + slotbuf[0] = 0x130;
22194 +Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
22196 + slotbuf[0] = 0x131;
22200 +Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
22202 + slotbuf[0] = 0x116;
22206 +Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
22208 + slotbuf[0] = 0x230;
22212 +Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
22214 + slotbuf[0] = 0x231;
22218 +Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
22220 + slotbuf[0] = 0x216;
22224 +Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
22226 + slotbuf[0] = 0x30;
22230 +Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
22232 + slotbuf[0] = 0x31;
22236 +Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
22238 + slotbuf[0] = 0x16;
22242 +Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
22244 + slotbuf[0] = 0x330;
22248 +Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
22250 + slotbuf[0] = 0x331;
22254 +Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
22256 + slotbuf[0] = 0x316;
22260 +Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
22262 + slotbuf[0] = 0x530;
22266 +Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
22268 + slotbuf[0] = 0x531;
22272 +Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
22274 + slotbuf[0] = 0x516;
22278 +Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf)
22280 + slotbuf[0] = 0xb030;
22284 +Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf)
22286 + slotbuf[0] = 0xd030;
22290 +Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
22292 + slotbuf[0] = 0xe630;
22296 +Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
22298 + slotbuf[0] = 0xe631;
22302 +Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
22304 + slotbuf[0] = 0xe616;
22308 +Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22310 + slotbuf[0] = 0xb130;
22314 +Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22316 + slotbuf[0] = 0xb131;
22320 +Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22322 + slotbuf[0] = 0xb116;
22326 +Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22328 + slotbuf[0] = 0xd130;
22332 +Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22334 + slotbuf[0] = 0xd131;
22338 +Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22340 + slotbuf[0] = 0xd116;
22344 +Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
22346 + slotbuf[0] = 0xb230;
22350 +Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
22352 + slotbuf[0] = 0xb231;
22356 +Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
22358 + slotbuf[0] = 0xb216;
22362 +Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
22364 + slotbuf[0] = 0xd230;
22368 +Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
22370 + slotbuf[0] = 0xd231;
22374 +Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
22376 + slotbuf[0] = 0xd216;
22380 +Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
22382 + slotbuf[0] = 0xb330;
22386 +Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
22388 + slotbuf[0] = 0xb331;
22392 +Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
22394 + slotbuf[0] = 0xb316;
22398 +Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
22400 + slotbuf[0] = 0xd330;
22404 +Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
22406 + slotbuf[0] = 0xd331;
22410 +Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
22412 + slotbuf[0] = 0xd316;
22416 +Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
22418 + slotbuf[0] = 0xb430;
22422 +Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
22424 + slotbuf[0] = 0xb431;
22428 +Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
22430 + slotbuf[0] = 0xb416;
22434 +Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
22436 + slotbuf[0] = 0xd430;
22440 +Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
22442 + slotbuf[0] = 0xd431;
22446 +Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
22448 + slotbuf[0] = 0xd416;
22452 +Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
22454 + slotbuf[0] = 0xb530;
22458 +Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
22460 + slotbuf[0] = 0xb531;
22464 +Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
22466 + slotbuf[0] = 0xb516;
22470 +Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
22472 + slotbuf[0] = 0xd530;
22476 +Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
22478 + slotbuf[0] = 0xd531;
22482 +Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
22484 + slotbuf[0] = 0xd516;
22488 +Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
22490 + slotbuf[0] = 0xc230;
22494 +Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
22496 + slotbuf[0] = 0xc231;
22500 +Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
22502 + slotbuf[0] = 0xc216;
22506 +Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
22508 + slotbuf[0] = 0xc330;
22512 +Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
22514 + slotbuf[0] = 0xc331;
22518 +Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
22520 + slotbuf[0] = 0xc316;
22524 +Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
22526 + slotbuf[0] = 0xc430;
22530 +Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
22532 + slotbuf[0] = 0xc431;
22536 +Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
22538 + slotbuf[0] = 0xc416;
22542 +Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
22544 + slotbuf[0] = 0xc530;
22548 +Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
22550 + slotbuf[0] = 0xc531;
22554 +Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
22556 + slotbuf[0] = 0xc516;
22560 +Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
22562 + slotbuf[0] = 0xee30;
22566 +Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
22568 + slotbuf[0] = 0xee31;
22572 +Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
22574 + slotbuf[0] = 0xee16;
22578 +Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
22580 + slotbuf[0] = 0xc030;
22584 +Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
22586 + slotbuf[0] = 0xc031;
22590 +Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
22592 + slotbuf[0] = 0xc016;
22596 +Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
22598 + slotbuf[0] = 0xe830;
22602 +Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
22604 + slotbuf[0] = 0xe831;
22608 +Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
22610 + slotbuf[0] = 0xe816;
22614 +Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
22616 + slotbuf[0] = 0xf430;
22620 +Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
22622 + slotbuf[0] = 0xf431;
22626 +Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
22628 + slotbuf[0] = 0xf416;
22632 +Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22634 + slotbuf[0] = 0xf530;
22638 +Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22640 + slotbuf[0] = 0xf531;
22644 +Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22646 + slotbuf[0] = 0xf516;
22650 +Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf)
22652 + slotbuf[0] = 0xeb30;
22656 +Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
22658 + slotbuf[0] = 0xe730;
22662 +Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
22664 + slotbuf[0] = 0xe731;
22668 +Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
22670 + slotbuf[0] = 0xe716;
22674 +Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf)
22676 + slotbuf[0] = 0x10300;
22680 +Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf)
22682 + slotbuf[0] = 0x700;
22686 +Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf)
22688 + slotbuf[0] = 0xe230;
22692 +Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf)
22694 + slotbuf[0] = 0xe231;
22698 +Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf)
22700 + slotbuf[0] = 0xe331;
22704 +Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
22706 + slotbuf[0] = 0xe430;
22710 +Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
22712 + slotbuf[0] = 0xe431;
22716 +Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
22718 + slotbuf[0] = 0xe416;
22722 +Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf)
22724 + slotbuf[0] = 0x400;
22728 +Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
22730 + slotbuf[0] = 0xd20f;
22734 +Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
22736 + slotbuf[0] = 0x9030;
22740 +Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
22742 + slotbuf[0] = 0x9031;
22746 +Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
22748 + slotbuf[0] = 0x9016;
22752 +Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
22754 + slotbuf[0] = 0xa030;
22758 +Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
22760 + slotbuf[0] = 0xa031;
22764 +Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
22766 + slotbuf[0] = 0xa016;
22770 +Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22772 + slotbuf[0] = 0x9130;
22776 +Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22778 + slotbuf[0] = 0x9131;
22782 +Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22784 + slotbuf[0] = 0x9116;
22788 +Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22790 + slotbuf[0] = 0xa130;
22794 +Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22796 + slotbuf[0] = 0xa131;
22800 +Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22802 + slotbuf[0] = 0xa116;
22806 +Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
22808 + slotbuf[0] = 0x8030;
22812 +Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
22814 + slotbuf[0] = 0x8031;
22818 +Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
22820 + slotbuf[0] = 0x8016;
22824 +Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22826 + slotbuf[0] = 0x8130;
22830 +Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22832 + slotbuf[0] = 0x8131;
22836 +Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22838 + slotbuf[0] = 0x8116;
22842 +Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
22844 + slotbuf[0] = 0x6030;
22848 +Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
22850 + slotbuf[0] = 0x6031;
22854 +Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
22856 + slotbuf[0] = 0x6016;
22860 +Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
22862 + slotbuf[0] = 0xe930;
22866 +Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
22868 + slotbuf[0] = 0xe931;
22872 +Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
22874 + slotbuf[0] = 0xe916;
22878 +Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
22880 + slotbuf[0] = 0xec30;
22884 +Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
22886 + slotbuf[0] = 0xec31;
22890 +Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
22892 + slotbuf[0] = 0xec16;
22896 +Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
22898 + slotbuf[0] = 0xed30;
22902 +Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
22904 + slotbuf[0] = 0xed31;
22908 +Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
22910 + slotbuf[0] = 0xed16;
22914 +Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
22916 + slotbuf[0] = 0x6830;
22920 +Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
22922 + slotbuf[0] = 0x6831;
22926 +Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
22928 + slotbuf[0] = 0x6816;
22932 +Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf)
22934 + slotbuf[0] = 0xe1f;
22938 +Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf)
22940 + slotbuf[0] = 0x10e1f;
22944 +Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf)
22946 + slotbuf[0] = 0x5931;
22950 +Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
22952 + slotbuf[0] = 0xea30;
22956 +Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
22958 + slotbuf[0] = 0xea31;
22962 +Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
22964 + slotbuf[0] = 0xea16;
22968 +Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
22970 + slotbuf[0] = 0xf030;
22974 +Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
22976 + slotbuf[0] = 0xf031;
22980 +Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
22982 + slotbuf[0] = 0xf016;
22986 +Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
22988 + slotbuf[0] = 0xc05;
22992 +Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
22994 + slotbuf[0] = 0xd05;
22998 +Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
23000 + slotbuf[0] = 0xb05;
23004 +Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
23006 + slotbuf[0] = 0xf05;
23010 +Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
23012 + slotbuf[0] = 0xe05;
23016 +Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
23018 + slotbuf[0] = 0x405;
23022 +Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
23024 + slotbuf[0] = 0x505;
23028 +Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
23030 + slotbuf[0] = 0x305;
23034 +Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
23036 + slotbuf[0] = 0x705;
23040 +Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
23042 + slotbuf[0] = 0x605;
23046 +Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf)
23048 + slotbuf[0] = 0x34;
23052 +Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf)
23054 + slotbuf[0] = 0x35;
23058 +Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf)
23060 + slotbuf[0] = 0x36;
23064 +Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
23066 + slotbuf[0] = 0x37;
23070 +Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf)
23072 + slotbuf[0] = 0xe04;
23076 +Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf)
23078 + slotbuf[0] = 0xf04;
23082 +Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf)
23084 + slotbuf[0] = 0x32;
23088 +Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf)
23090 + slotbuf[0] = 0x200b00;
23094 +Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf)
23096 + slotbuf[0] = 0x200f00;
23100 +Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf)
23102 + slotbuf[0] = 0x200e00;
23106 +Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
23108 + slotbuf[0] = 0xc30;
23112 +Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
23114 + slotbuf[0] = 0xc31;
23118 +Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
23120 + slotbuf[0] = 0xc16;
23124 +Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf)
23126 + slotbuf[0] = 0x28;
23130 +Opcode_muluh_Slot_inst_encode (xtensa_insnbuf slotbuf)
23132 + slotbuf[0] = 0x2a;
23136 +Opcode_mulsh_Slot_inst_encode (xtensa_insnbuf slotbuf)
23138 + slotbuf[0] = 0x2b;
23142 +Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf)
23144 + slotbuf[0] = 0x1c;
23148 +Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf)
23150 + slotbuf[0] = 0x1d;
23154 -Slot_inst16b_decode (const xtensa_insnbuf insn)
23156 - switch (Field_op0_Slot_inst16b_get (insn))
23159 - switch (Field_i_Slot_inst16b_get (insn))
23162 - return 33; /* movi.n */
23164 - switch (Field_z_Slot_inst16b_get (insn))
23167 - return 28; /* beqz.n */
23169 - return 29; /* bnez.n */
23175 - switch (Field_r_Slot_inst16b_get (insn))
23178 - return 32; /* mov.n */
23180 - switch (Field_t_Slot_inst16b_get (insn))
23183 - return 35; /* ret.n */
23185 - return 15; /* retw.n */
23187 - return 325; /* break.n */
23189 - if (Field_s_Slot_inst16b_get (insn) == 0)
23190 - return 34; /* nop.n */
23193 - if (Field_s_Slot_inst16b_get (insn) == 0)
23194 - return 30; /* ill.n */
23203 +xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = {
23204 + Opcode_excw_Slot_inst_encode, 0, 0
23207 +xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = {
23208 + Opcode_rfe_Slot_inst_encode, 0, 0
23211 +xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = {
23212 + Opcode_rfde_Slot_inst_encode, 0, 0
23215 +xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = {
23216 + Opcode_syscall_Slot_inst_encode, 0, 0
23219 +xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = {
23220 + Opcode_simcall_Slot_inst_encode, 0, 0
23223 +xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = {
23224 + Opcode_call12_Slot_inst_encode, 0, 0
23227 +xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = {
23228 + Opcode_call8_Slot_inst_encode, 0, 0
23231 +xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = {
23232 + Opcode_call4_Slot_inst_encode, 0, 0
23235 +xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = {
23236 + Opcode_callx12_Slot_inst_encode, 0, 0
23239 +xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = {
23240 + Opcode_callx8_Slot_inst_encode, 0, 0
23243 +xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = {
23244 + Opcode_callx4_Slot_inst_encode, 0, 0
23247 +xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = {
23248 + Opcode_entry_Slot_inst_encode, 0, 0
23251 +xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = {
23252 + Opcode_movsp_Slot_inst_encode, 0, 0
23255 +xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = {
23256 + Opcode_rotw_Slot_inst_encode, 0, 0
23259 +xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = {
23260 + Opcode_retw_Slot_inst_encode, 0, 0
23263 +xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = {
23264 + 0, 0, Opcode_retw_n_Slot_inst16b_encode
23267 +xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = {
23268 + Opcode_rfwo_Slot_inst_encode, 0, 0
23271 +xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = {
23272 + Opcode_rfwu_Slot_inst_encode, 0, 0
23275 +xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = {
23276 + Opcode_l32e_Slot_inst_encode, 0, 0
23279 +xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = {
23280 + Opcode_s32e_Slot_inst_encode, 0, 0
23283 +xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = {
23284 + Opcode_rsr_windowbase_Slot_inst_encode, 0, 0
23287 +xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = {
23288 + Opcode_wsr_windowbase_Slot_inst_encode, 0, 0
23291 +xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = {
23292 + Opcode_xsr_windowbase_Slot_inst_encode, 0, 0
23295 +xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = {
23296 + Opcode_rsr_windowstart_Slot_inst_encode, 0, 0
23299 +xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = {
23300 + Opcode_wsr_windowstart_Slot_inst_encode, 0, 0
23303 +xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = {
23304 + Opcode_xsr_windowstart_Slot_inst_encode, 0, 0
23307 +xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = {
23308 + 0, Opcode_add_n_Slot_inst16a_encode, 0
23311 +xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = {
23312 + 0, Opcode_addi_n_Slot_inst16a_encode, 0
23315 +xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = {
23316 + 0, 0, Opcode_beqz_n_Slot_inst16b_encode
23319 +xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = {
23320 + 0, 0, Opcode_bnez_n_Slot_inst16b_encode
23323 +xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = {
23324 + 0, 0, Opcode_ill_n_Slot_inst16b_encode
23327 +xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = {
23328 + 0, Opcode_l32i_n_Slot_inst16a_encode, 0
23331 +xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = {
23332 + 0, 0, Opcode_mov_n_Slot_inst16b_encode
23335 +xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = {
23336 + 0, 0, Opcode_movi_n_Slot_inst16b_encode
23339 +xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = {
23340 + 0, 0, Opcode_nop_n_Slot_inst16b_encode
23343 +xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = {
23344 + 0, 0, Opcode_ret_n_Slot_inst16b_encode
23347 +xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = {
23348 + 0, Opcode_s32i_n_Slot_inst16a_encode, 0
23351 +xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = {
23352 + Opcode_rur_threadptr_Slot_inst_encode, 0, 0
23355 +xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = {
23356 + Opcode_wur_threadptr_Slot_inst_encode, 0, 0
23359 +xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = {
23360 + Opcode_addi_Slot_inst_encode, 0, 0
23363 +xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = {
23364 + Opcode_addmi_Slot_inst_encode, 0, 0
23367 +xtensa_opcode_encode_fn Opcode_add_encode_fns[] = {
23368 + Opcode_add_Slot_inst_encode, 0, 0
23371 +xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = {
23372 + Opcode_sub_Slot_inst_encode, 0, 0
23375 +xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = {
23376 + Opcode_addx2_Slot_inst_encode, 0, 0
23379 +xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = {
23380 + Opcode_addx4_Slot_inst_encode, 0, 0
23383 +xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = {
23384 + Opcode_addx8_Slot_inst_encode, 0, 0
23387 +xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = {
23388 + Opcode_subx2_Slot_inst_encode, 0, 0
23391 +xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = {
23392 + Opcode_subx4_Slot_inst_encode, 0, 0
23395 +xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = {
23396 + Opcode_subx8_Slot_inst_encode, 0, 0
23399 +xtensa_opcode_encode_fn Opcode_and_encode_fns[] = {
23400 + Opcode_and_Slot_inst_encode, 0, 0
23403 +xtensa_opcode_encode_fn Opcode_or_encode_fns[] = {
23404 + Opcode_or_Slot_inst_encode, 0, 0
23407 +xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = {
23408 + Opcode_xor_Slot_inst_encode, 0, 0
23411 +xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = {
23412 + Opcode_beqi_Slot_inst_encode, 0, 0
23415 +xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = {
23416 + Opcode_bnei_Slot_inst_encode, 0, 0
23419 +xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = {
23420 + Opcode_bgei_Slot_inst_encode, 0, 0
23423 +xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = {
23424 + Opcode_blti_Slot_inst_encode, 0, 0
23427 +xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = {
23428 + Opcode_bbci_Slot_inst_encode, 0, 0
23431 +xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = {
23432 + Opcode_bbsi_Slot_inst_encode, 0, 0
23435 +xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = {
23436 + Opcode_bgeui_Slot_inst_encode, 0, 0
23439 +xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = {
23440 + Opcode_bltui_Slot_inst_encode, 0, 0
23443 +xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = {
23444 + Opcode_beq_Slot_inst_encode, 0, 0
23447 +xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = {
23448 + Opcode_bne_Slot_inst_encode, 0, 0
23451 +xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = {
23452 + Opcode_bge_Slot_inst_encode, 0, 0
23455 +xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = {
23456 + Opcode_blt_Slot_inst_encode, 0, 0
23459 +xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = {
23460 + Opcode_bgeu_Slot_inst_encode, 0, 0
23463 +xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = {
23464 + Opcode_bltu_Slot_inst_encode, 0, 0
23467 +xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = {
23468 + Opcode_bany_Slot_inst_encode, 0, 0
23471 +xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = {
23472 + Opcode_bnone_Slot_inst_encode, 0, 0
23475 +xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = {
23476 + Opcode_ball_Slot_inst_encode, 0, 0
23479 +xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = {
23480 + Opcode_bnall_Slot_inst_encode, 0, 0
23483 +xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = {
23484 + Opcode_bbc_Slot_inst_encode, 0, 0
23487 +xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = {
23488 + Opcode_bbs_Slot_inst_encode, 0, 0
23491 +xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = {
23492 + Opcode_beqz_Slot_inst_encode, 0, 0
23495 +xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = {
23496 + Opcode_bnez_Slot_inst_encode, 0, 0
23499 +xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = {
23500 + Opcode_bgez_Slot_inst_encode, 0, 0
23503 +xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = {
23504 + Opcode_bltz_Slot_inst_encode, 0, 0
23507 +xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = {
23508 + Opcode_call0_Slot_inst_encode, 0, 0
23511 +xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = {
23512 + Opcode_callx0_Slot_inst_encode, 0, 0
23515 +xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = {
23516 + Opcode_extui_Slot_inst_encode, 0, 0
23519 +xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = {
23520 + Opcode_ill_Slot_inst_encode, 0, 0
23523 +xtensa_opcode_encode_fn Opcode_j_encode_fns[] = {
23524 + Opcode_j_Slot_inst_encode, 0, 0
23527 +xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = {
23528 + Opcode_jx_Slot_inst_encode, 0, 0
23531 +xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = {
23532 + Opcode_l16ui_Slot_inst_encode, 0, 0
23535 +xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = {
23536 + Opcode_l16si_Slot_inst_encode, 0, 0
23539 +xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = {
23540 + Opcode_l32i_Slot_inst_encode, 0, 0
23543 +xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = {
23544 + Opcode_l32r_Slot_inst_encode, 0, 0
23547 +xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = {
23548 + Opcode_l8ui_Slot_inst_encode, 0, 0
23551 +xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = {
23552 + Opcode_loop_Slot_inst_encode, 0, 0
23555 +xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = {
23556 + Opcode_loopnez_Slot_inst_encode, 0, 0
23559 +xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = {
23560 + Opcode_loopgtz_Slot_inst_encode, 0, 0
23563 +xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = {
23564 + Opcode_movi_Slot_inst_encode, 0, 0
23567 +xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = {
23568 + Opcode_moveqz_Slot_inst_encode, 0, 0
23571 +xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = {
23572 + Opcode_movnez_Slot_inst_encode, 0, 0
23575 +xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = {
23576 + Opcode_movltz_Slot_inst_encode, 0, 0
23579 +xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = {
23580 + Opcode_movgez_Slot_inst_encode, 0, 0
23583 +xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = {
23584 + Opcode_neg_Slot_inst_encode, 0, 0
23587 +xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = {
23588 + Opcode_abs_Slot_inst_encode, 0, 0
23591 +xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = {
23592 + Opcode_nop_Slot_inst_encode, 0, 0
23595 +xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = {
23596 + Opcode_ret_Slot_inst_encode, 0, 0
23599 +xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = {
23600 + Opcode_s16i_Slot_inst_encode, 0, 0
23603 +xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = {
23604 + Opcode_s32i_Slot_inst_encode, 0, 0
23607 +xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = {
23608 + Opcode_s8i_Slot_inst_encode, 0, 0
23611 +xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = {
23612 + Opcode_ssr_Slot_inst_encode, 0, 0
23615 +xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = {
23616 + Opcode_ssl_Slot_inst_encode, 0, 0
23619 +xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = {
23620 + Opcode_ssa8l_Slot_inst_encode, 0, 0
23623 +xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = {
23624 + Opcode_ssa8b_Slot_inst_encode, 0, 0
23627 +xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = {
23628 + Opcode_ssai_Slot_inst_encode, 0, 0
23631 +xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = {
23632 + Opcode_sll_Slot_inst_encode, 0, 0
23635 +xtensa_opcode_encode_fn Opcode_src_encode_fns[] = {
23636 + Opcode_src_Slot_inst_encode, 0, 0
23639 +xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = {
23640 + Opcode_srl_Slot_inst_encode, 0, 0
23643 +xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = {
23644 + Opcode_sra_Slot_inst_encode, 0, 0
23647 +xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = {
23648 + Opcode_slli_Slot_inst_encode, 0, 0
23651 +xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = {
23652 + Opcode_srai_Slot_inst_encode, 0, 0
23655 +xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = {
23656 + Opcode_srli_Slot_inst_encode, 0, 0
23659 +xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = {
23660 + Opcode_memw_Slot_inst_encode, 0, 0
23663 +xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = {
23664 + Opcode_extw_Slot_inst_encode, 0, 0
23667 +xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = {
23668 + Opcode_isync_Slot_inst_encode, 0, 0
23671 +xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = {
23672 + Opcode_rsync_Slot_inst_encode, 0, 0
23675 +xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = {
23676 + Opcode_esync_Slot_inst_encode, 0, 0
23679 +xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = {
23680 + Opcode_dsync_Slot_inst_encode, 0, 0
23683 +xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = {
23684 + Opcode_rsil_Slot_inst_encode, 0, 0
23687 +xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = {
23688 + Opcode_rsr_lend_Slot_inst_encode, 0, 0
23691 +xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = {
23692 + Opcode_wsr_lend_Slot_inst_encode, 0, 0
23695 +xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = {
23696 + Opcode_xsr_lend_Slot_inst_encode, 0, 0
23699 +xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = {
23700 + Opcode_rsr_lcount_Slot_inst_encode, 0, 0
23703 +xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = {
23704 + Opcode_wsr_lcount_Slot_inst_encode, 0, 0
23707 +xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = {
23708 + Opcode_xsr_lcount_Slot_inst_encode, 0, 0
23711 +xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = {
23712 + Opcode_rsr_lbeg_Slot_inst_encode, 0, 0
23715 +xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = {
23716 + Opcode_wsr_lbeg_Slot_inst_encode, 0, 0
23719 +xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = {
23720 + Opcode_xsr_lbeg_Slot_inst_encode, 0, 0
23723 +xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = {
23724 + Opcode_rsr_sar_Slot_inst_encode, 0, 0
23727 +xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = {
23728 + Opcode_wsr_sar_Slot_inst_encode, 0, 0
23731 +xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = {
23732 + Opcode_xsr_sar_Slot_inst_encode, 0, 0
23735 +xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = {
23736 + Opcode_rsr_litbase_Slot_inst_encode, 0, 0
23739 +xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = {
23740 + Opcode_wsr_litbase_Slot_inst_encode, 0, 0
23743 +xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = {
23744 + Opcode_xsr_litbase_Slot_inst_encode, 0, 0
23747 +xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = {
23748 + Opcode_rsr_176_Slot_inst_encode, 0, 0
23751 +xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = {
23752 + Opcode_rsr_208_Slot_inst_encode, 0, 0
23755 +xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = {
23756 + Opcode_rsr_ps_Slot_inst_encode, 0, 0
23759 +xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = {
23760 + Opcode_wsr_ps_Slot_inst_encode, 0, 0
23763 +xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = {
23764 + Opcode_xsr_ps_Slot_inst_encode, 0, 0
23767 +xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = {
23768 + Opcode_rsr_epc1_Slot_inst_encode, 0, 0
23771 +xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = {
23772 + Opcode_wsr_epc1_Slot_inst_encode, 0, 0
23775 +xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = {
23776 + Opcode_xsr_epc1_Slot_inst_encode, 0, 0
23779 +xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = {
23780 + Opcode_rsr_excsave1_Slot_inst_encode, 0, 0
23783 +xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = {
23784 + Opcode_wsr_excsave1_Slot_inst_encode, 0, 0
23787 +xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = {
23788 + Opcode_xsr_excsave1_Slot_inst_encode, 0, 0
23791 +xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = {
23792 + Opcode_rsr_epc2_Slot_inst_encode, 0, 0
23795 +xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = {
23796 + Opcode_wsr_epc2_Slot_inst_encode, 0, 0
23799 +xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = {
23800 + Opcode_xsr_epc2_Slot_inst_encode, 0, 0
23803 +xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = {
23804 + Opcode_rsr_excsave2_Slot_inst_encode, 0, 0
23807 +xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = {
23808 + Opcode_wsr_excsave2_Slot_inst_encode, 0, 0
23811 +xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = {
23812 + Opcode_xsr_excsave2_Slot_inst_encode, 0, 0
23815 +xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = {
23816 + Opcode_rsr_epc3_Slot_inst_encode, 0, 0
23819 +xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = {
23820 + Opcode_wsr_epc3_Slot_inst_encode, 0, 0
23823 +xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = {
23824 + Opcode_xsr_epc3_Slot_inst_encode, 0, 0
23827 +xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = {
23828 + Opcode_rsr_excsave3_Slot_inst_encode, 0, 0
23831 +xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = {
23832 + Opcode_wsr_excsave3_Slot_inst_encode, 0, 0
23835 +xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = {
23836 + Opcode_xsr_excsave3_Slot_inst_encode, 0, 0
23839 +xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = {
23840 + Opcode_rsr_epc4_Slot_inst_encode, 0, 0
23843 +xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = {
23844 + Opcode_wsr_epc4_Slot_inst_encode, 0, 0
23847 +xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = {
23848 + Opcode_xsr_epc4_Slot_inst_encode, 0, 0
23851 +xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = {
23852 + Opcode_rsr_excsave4_Slot_inst_encode, 0, 0
23855 +xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = {
23856 + Opcode_wsr_excsave4_Slot_inst_encode, 0, 0
23859 +xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = {
23860 + Opcode_xsr_excsave4_Slot_inst_encode, 0, 0
23863 +xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = {
23864 + Opcode_rsr_epc5_Slot_inst_encode, 0, 0
23867 +xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = {
23868 + Opcode_wsr_epc5_Slot_inst_encode, 0, 0
23871 +xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = {
23872 + Opcode_xsr_epc5_Slot_inst_encode, 0, 0
23875 +xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = {
23876 + Opcode_rsr_excsave5_Slot_inst_encode, 0, 0
23879 +xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = {
23880 + Opcode_wsr_excsave5_Slot_inst_encode, 0, 0
23883 +xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = {
23884 + Opcode_xsr_excsave5_Slot_inst_encode, 0, 0
23887 +xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = {
23888 + Opcode_rsr_eps2_Slot_inst_encode, 0, 0
23891 +xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = {
23892 + Opcode_wsr_eps2_Slot_inst_encode, 0, 0
23895 +xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = {
23896 + Opcode_xsr_eps2_Slot_inst_encode, 0, 0
23899 +xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = {
23900 + Opcode_rsr_eps3_Slot_inst_encode, 0, 0
23903 +xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = {
23904 + Opcode_wsr_eps3_Slot_inst_encode, 0, 0
23907 +xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = {
23908 + Opcode_xsr_eps3_Slot_inst_encode, 0, 0
23911 +xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = {
23912 + Opcode_rsr_eps4_Slot_inst_encode, 0, 0
23915 +xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = {
23916 + Opcode_wsr_eps4_Slot_inst_encode, 0, 0
23919 +xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = {
23920 + Opcode_xsr_eps4_Slot_inst_encode, 0, 0
23923 +xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = {
23924 + Opcode_rsr_eps5_Slot_inst_encode, 0, 0
23927 +xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = {
23928 + Opcode_wsr_eps5_Slot_inst_encode, 0, 0
23931 +xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = {
23932 + Opcode_xsr_eps5_Slot_inst_encode, 0, 0
23935 +xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = {
23936 + Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0
23939 +xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = {
23940 + Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0
23943 +xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = {
23944 + Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0
23947 +xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = {
23948 + Opcode_rsr_depc_Slot_inst_encode, 0, 0
23951 +xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = {
23952 + Opcode_wsr_depc_Slot_inst_encode, 0, 0
23955 +xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = {
23956 + Opcode_xsr_depc_Slot_inst_encode, 0, 0
23959 +xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = {
23960 + Opcode_rsr_exccause_Slot_inst_encode, 0, 0
23963 +xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = {
23964 + Opcode_wsr_exccause_Slot_inst_encode, 0, 0
23967 +xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = {
23968 + Opcode_xsr_exccause_Slot_inst_encode, 0, 0
23971 +xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = {
23972 + Opcode_rsr_misc0_Slot_inst_encode, 0, 0
23975 +xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = {
23976 + Opcode_wsr_misc0_Slot_inst_encode, 0, 0
23979 +xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = {
23980 + Opcode_xsr_misc0_Slot_inst_encode, 0, 0
23983 +xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = {
23984 + Opcode_rsr_misc1_Slot_inst_encode, 0, 0
23987 +xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = {
23988 + Opcode_wsr_misc1_Slot_inst_encode, 0, 0
23991 +xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = {
23992 + Opcode_xsr_misc1_Slot_inst_encode, 0, 0
23995 +xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = {
23996 + Opcode_rsr_prid_Slot_inst_encode, 0, 0
23999 +xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = {
24000 + Opcode_rsr_vecbase_Slot_inst_encode, 0, 0
24003 +xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = {
24004 + Opcode_wsr_vecbase_Slot_inst_encode, 0, 0
24007 +xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = {
24008 + Opcode_xsr_vecbase_Slot_inst_encode, 0, 0
24011 +xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = {
24012 + Opcode_rfi_Slot_inst_encode, 0, 0
24015 +xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = {
24016 + Opcode_waiti_Slot_inst_encode, 0, 0
24019 +xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = {
24020 + Opcode_rsr_interrupt_Slot_inst_encode, 0, 0
24023 +xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = {
24024 + Opcode_wsr_intset_Slot_inst_encode, 0, 0
24027 +xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = {
24028 + Opcode_wsr_intclear_Slot_inst_encode, 0, 0
24031 +xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = {
24032 + Opcode_rsr_intenable_Slot_inst_encode, 0, 0
24035 +xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = {
24036 + Opcode_wsr_intenable_Slot_inst_encode, 0, 0
24039 +xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = {
24040 + Opcode_xsr_intenable_Slot_inst_encode, 0, 0
24043 +xtensa_opcode_encode_fn Opcode_break_encode_fns[] = {
24044 + Opcode_break_Slot_inst_encode, 0, 0
24047 +xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = {
24048 + 0, 0, Opcode_break_n_Slot_inst16b_encode
24051 +xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = {
24052 + Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0
24055 +xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = {
24056 + Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0
24059 +xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = {
24060 + Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0
24063 +xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = {
24064 + Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0
24067 +xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = {
24068 + Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0
24071 +xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = {
24072 + Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0
24075 +xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = {
24076 + Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0
24080 -Slot_inst16a_decode (const xtensa_insnbuf insn)
24082 - switch (Field_op0_Slot_inst16a_get (insn))
24085 - return 31; /* l32i.n */
24087 - return 36; /* s32i.n */
24089 - return 26; /* add.n */
24091 - return 27; /* addi.n */
24095 +xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = {
24096 + Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0
24100 -Slot_xt_flix64_slot2_decode (const xtensa_insnbuf insn)
24102 - switch (Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn))
24105 - if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 1)
24106 - return 41; /* add */
24107 - if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 5)
24108 - return 42; /* sub */
24109 - if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 2)
24110 - return 43; /* addx2 */
24111 - if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 3)
24112 - return 49; /* and */
24113 - if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 4)
24114 - return 450; /* sext */
24117 - if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 1)
24118 - return 27; /* addi.n */
24119 - if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 2)
24120 - return 44; /* addx4 */
24121 - if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 3)
24122 - return 50; /* or */
24123 - if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 5)
24124 - return 51; /* xor */
24125 - if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 4)
24126 - return 113; /* srli */
24129 - if (Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0 &&
24130 - Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6)
24131 - return 33; /* movi.n */
24132 - if (Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 2 &&
24133 - Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 &&
24134 - Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0)
24135 - return 32; /* mov.n */
24136 - if (Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 3 &&
24137 - Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 &&
24138 - Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0)
24139 - return 97; /* nop */
24140 - if (Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 8 &&
24141 - Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 &&
24142 - Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0)
24143 - return 96; /* abs */
24144 - if (Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 9 &&
24145 - Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 &&
24146 - Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0)
24147 - return 95; /* neg */
24148 - if (Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 5 &&
24149 - Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 &&
24150 - Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0)
24151 - return 110; /* sra */
24152 - if (Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 3 &&
24153 - Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 &&
24154 - Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0)
24155 - return 109; /* srl */
24156 - if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 7)
24157 - return 112; /* srai */
24160 +xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = {
24161 + Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0
24165 -Slot_xt_flix64_slot0_decode (const xtensa_insnbuf insn)
24167 - switch (Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_get (insn))
24170 - if (Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_get (insn) == 2)
24171 - return 78; /* extui */
24172 - switch (Field_op1_Slot_xt_flix64_slot0_get (insn))
24175 - switch (Field_op2_Slot_xt_flix64_slot0_get (insn))
24178 - if (Field_r_Slot_xt_flix64_slot0_get (insn) == 2)
24180 - if (Field_s_Slot_xt_flix64_slot0_get (insn) == 0)
24182 - if (Field_t_Slot_xt_flix64_slot0_get (insn) == 15)
24183 - return 97; /* nop */
24188 - return 49; /* and */
24190 - return 50; /* or */
24192 - return 51; /* xor */
24194 - switch (Field_r_Slot_xt_flix64_slot0_get (insn))
24197 - if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0)
24198 - return 102; /* ssr */
24201 - if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0)
24202 - return 103; /* ssl */
24205 - if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0)
24206 - return 104; /* ssa8l */
24209 - if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0)
24210 - return 105; /* ssa8b */
24213 - if (Field_thi3_Slot_xt_flix64_slot0_get (insn) == 0)
24214 - return 106; /* ssai */
24217 - return 448; /* nsa */
24219 - return 449; /* nsau */
24223 - switch (Field_s_Slot_xt_flix64_slot0_get (insn))
24226 - return 95; /* neg */
24228 - return 96; /* abs */
24232 - return 41; /* add */
24234 - return 43; /* addx2 */
24236 - return 44; /* addx4 */
24238 - return 45; /* addx8 */
24240 - return 42; /* sub */
24242 - return 46; /* subx2 */
24244 - return 47; /* subx4 */
24246 - return 48; /* subx8 */
24250 - if (Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_get (insn) == 1)
24251 - return 112; /* srai */
24252 - if (Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_get (insn) == 0)
24253 - return 111; /* slli */
24254 - switch (Field_op2_Slot_xt_flix64_slot0_get (insn))
24257 - return 113; /* srli */
24259 - return 108; /* src */
24261 - if (Field_s_Slot_xt_flix64_slot0_get (insn) == 0)
24262 - return 109; /* srl */
24265 - if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0)
24266 - return 107; /* sll */
24269 - if (Field_s_Slot_xt_flix64_slot0_get (insn) == 0)
24270 - return 110; /* sra */
24273 - return 296; /* mul16u */
24275 - return 297; /* mul16s */
24279 - if (Field_op2_Slot_xt_flix64_slot0_get (insn) == 8)
24280 - return 461; /* mull */
24283 - switch (Field_op2_Slot_xt_flix64_slot0_get (insn))
24286 - return 450; /* sext */
24288 - return 443; /* clamps */
24290 - return 444; /* min */
24292 - return 445; /* max */
24294 - return 446; /* minu */
24296 - return 447; /* maxu */
24298 - return 91; /* moveqz */
24300 - return 92; /* movnez */
24302 - return 93; /* movltz */
24304 - return 94; /* movgez */
24310 - switch (Field_r_Slot_xt_flix64_slot0_get (insn))
24313 - return 86; /* l8ui */
24315 - return 82; /* l16ui */
24317 - return 84; /* l32i */
24319 - return 101; /* s8i */
24321 - return 99; /* s16i */
24323 - return 100; /* s32i */
24325 - return 83; /* l16si */
24327 - return 90; /* movi */
24329 - return 39; /* addi */
24331 - return 40; /* addmi */
24335 - if (Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_get (insn) == 1)
24336 - return 85; /* l32r */
24337 - if (Field_sae4_Slot_xt_flix64_slot0_get (insn) == 0 &&
24338 - Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_get (insn) == 3 &&
24339 - Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_get (insn) == 0 &&
24340 - Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_get (insn) == 0)
24341 - return 32; /* mov.n */
24344 +xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = {
24345 + Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0
24349 -Slot_xt_flix64_slot1_decode (const xtensa_insnbuf insn)
24351 - if (Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0 &&
24352 - Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 1)
24353 - return 78; /* extui */
24354 - switch (Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn))
24357 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24358 - return 90; /* movi */
24361 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 1)
24362 - return 39; /* addi */
24365 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 1)
24366 - return 40; /* addmi */
24367 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
24368 - Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_get (insn) == 0)
24369 - return 51; /* xor */
24372 - switch (Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn))
24375 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24376 - return 111; /* slli */
24379 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24380 - return 112; /* srai */
24383 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
24384 - Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
24385 - return 107; /* sll */
24388 - switch (Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn))
24391 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24392 - return 41; /* add */
24395 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24396 - return 45; /* addx8 */
24399 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24400 - return 43; /* addx2 */
24403 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24404 - return 49; /* and */
24407 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24408 - return 91; /* moveqz */
24411 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24412 - return 94; /* movgez */
24415 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24416 - return 44; /* addx4 */
24419 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24420 - return 93; /* movltz */
24423 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24424 - return 92; /* movnez */
24427 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24428 - return 296; /* mul16u */
24431 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24432 - return 297; /* mul16s */
24435 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24436 - return 461; /* mull */
24439 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24440 - return 50; /* or */
24443 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24444 - return 450; /* sext */
24447 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24448 - return 108; /* src */
24451 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24452 - return 113; /* srli */
24455 - if (Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 280 &&
24456 - Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
24457 - Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
24458 - return 32; /* mov.n */
24459 - if (Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 281 &&
24460 - Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
24461 - Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
24462 - return 81; /* jx */
24463 - if (Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 141 &&
24464 - Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
24465 - Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
24466 - return 103; /* ssl */
24467 - if (Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 71 &&
24468 - Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
24469 - Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
24470 - return 97; /* nop */
24471 - if (Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 148 &&
24472 - Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
24473 - Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
24474 - return 95; /* neg */
24475 - if (Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 149 &&
24476 - Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
24477 - Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
24478 - return 110; /* sra */
24479 - if (Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 75 &&
24480 - Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
24481 - Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
24482 - return 109; /* srl */
24483 - if (Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 5 &&
24484 - Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
24485 - Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
24486 - return 42; /* sub */
24487 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 3)
24488 - return 80; /* j */
24491 +xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = {
24492 + Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0
24495 +xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = {
24496 + Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0
24500 -Slot_xt_flix64_slot3_decode (const xtensa_insnbuf insn)
24502 - switch (Field_op0_s6_Slot_xt_flix64_slot3_get (insn))
24505 - if (Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_get (insn) == 0)
24506 - return 516; /* bbci.w18 */
24509 - if (Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_get (insn) == 0)
24510 - return 517; /* bbsi.w18 */
24513 - if (Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24514 - return 526; /* ball.w18 */
24517 - if (Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24518 - return 524; /* bany.w18 */
24521 - if (Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24522 - return 528; /* bbc.w18 */
24525 - if (Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24526 - return 529; /* bbs.w18 */
24529 - if (Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24530 - return 518; /* beq.w18 */
24533 - if (Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24534 - return 510; /* beqi.w18 */
24537 - if (Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24538 - return 520; /* bge.w18 */
24541 - if (Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24542 - return 512; /* bgei.w18 */
24545 - if (Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24546 - return 522; /* bgeu.w18 */
24549 - if (Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24550 - return 514; /* bgeui.w18 */
24553 - if (Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24554 - return 521; /* blt.w18 */
24557 - if (Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24558 - return 513; /* blti.w18 */
24561 - if (Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24562 - return 523; /* bltu.w18 */
24565 - if (Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24566 - return 515; /* bltui.w18 */
24569 - if (Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24570 - return 527; /* bnall.w18 */
24573 - if (Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24574 - return 519; /* bne.w18 */
24577 - if (Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24578 - return 511; /* bnei.w18 */
24581 - if (Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24582 - return 525; /* bnone.w18 */
24585 - if (Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24586 - return 506; /* beqz.w18 */
24589 - if (Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24590 - return 508; /* bgez.w18 */
24593 - if (Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24594 - return 509; /* bltz.w18 */
24597 - if (Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24598 - return 507; /* bnez.w18 */
24601 - if (Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24602 - return 97; /* nop */
24607 +xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = {
24608 + Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0
24612 -/* Instruction slots. */
24613 +xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = {
24614 + Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0
24618 -Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn,
24619 - xtensa_insnbuf slotbuf)
24622 - slotbuf[0] = (insn[0] & 0xffffff);
24624 +xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = {
24625 + Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0
24629 -Slot_x24_Format_inst_0_set (xtensa_insnbuf insn,
24630 - const xtensa_insnbuf slotbuf)
24632 - insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff);
24634 +xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = {
24635 + Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0
24639 -Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn,
24640 - xtensa_insnbuf slotbuf)
24643 - slotbuf[0] = (insn[0] & 0xffff);
24645 +xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = {
24646 + Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0
24650 -Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn,
24651 - const xtensa_insnbuf slotbuf)
24653 - insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
24655 +xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = {
24656 + Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0
24660 -Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn,
24661 - xtensa_insnbuf slotbuf)
24664 - slotbuf[0] = (insn[0] & 0xffff);
24666 +xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = {
24667 + Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0
24671 -Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn,
24672 - const xtensa_insnbuf slotbuf)
24674 - insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
24676 +xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = {
24677 + Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0
24681 -Slot_xt_format1_Format_xt_flix64_slot0_4_get (const xtensa_insnbuf insn,
24682 - xtensa_insnbuf slotbuf)
24685 - slotbuf[0] = ((insn[0] & 0xffffff0) >> 4);
24687 +xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = {
24688 + Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0
24692 -Slot_xt_format1_Format_xt_flix64_slot0_4_set (xtensa_insnbuf insn,
24693 - const xtensa_insnbuf slotbuf)
24695 - insn[0] = (insn[0] & ~0xffffff0) | ((slotbuf[0] & 0xffffff) << 4);
24697 +xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = {
24698 + Opcode_rsr_debugcause_Slot_inst_encode, 0, 0
24702 -Slot_xt_format2_Format_xt_flix64_slot0_4_get (const xtensa_insnbuf insn,
24703 - xtensa_insnbuf slotbuf)
24706 - slotbuf[0] = ((insn[0] & 0xffffff0) >> 4);
24708 +xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = {
24709 + Opcode_wsr_debugcause_Slot_inst_encode, 0, 0
24713 -Slot_xt_format2_Format_xt_flix64_slot0_4_set (xtensa_insnbuf insn,
24714 - const xtensa_insnbuf slotbuf)
24716 - insn[0] = (insn[0] & ~0xffffff0) | ((slotbuf[0] & 0xffffff) << 4);
24718 +xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = {
24719 + Opcode_xsr_debugcause_Slot_inst_encode, 0, 0
24723 -Slot_xt_format1_Format_xt_flix64_slot1_28_get (const xtensa_insnbuf insn,
24724 - xtensa_insnbuf slotbuf)
24727 - slotbuf[0] = ((insn[0] & 0xf0000000) >> 28);
24728 - slotbuf[0] = (slotbuf[0] & ~0xffff0) | ((insn[1] & 0xffff) << 4);
24730 +xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = {
24731 + Opcode_rsr_icount_Slot_inst_encode, 0, 0
24735 -Slot_xt_format1_Format_xt_flix64_slot1_28_set (xtensa_insnbuf insn,
24736 - const xtensa_insnbuf slotbuf)
24738 - insn[0] = (insn[0] & ~0xf0000000) | ((slotbuf[0] & 0xf) << 28);
24739 - insn[1] = (insn[1] & ~0xffff) | ((slotbuf[0] & 0xffff0) >> 4);
24741 +xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = {
24742 + Opcode_wsr_icount_Slot_inst_encode, 0, 0
24746 -Slot_xt_format1_Format_xt_flix64_slot2_48_get (const xtensa_insnbuf insn,
24747 - xtensa_insnbuf slotbuf)
24750 - slotbuf[0] = ((insn[1] & 0xffff0000) >> 16);
24752 +xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = {
24753 + Opcode_xsr_icount_Slot_inst_encode, 0, 0
24757 -Slot_xt_format1_Format_xt_flix64_slot2_48_set (xtensa_insnbuf insn,
24758 - const xtensa_insnbuf slotbuf)
24760 - insn[1] = (insn[1] & ~0xffff0000) | ((slotbuf[0] & 0xffff) << 16);
24762 +xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = {
24763 + Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0
24767 -Slot_xt_format2_Format_xt_flix64_slot3_28_get (const xtensa_insnbuf insn,
24768 - xtensa_insnbuf slotbuf)
24770 - slotbuf[0] = ((insn[0] & 0xf0000000) >> 28);
24771 - slotbuf[0] = (slotbuf[0] & ~0xfffffff0) | ((insn[1] & 0xfffffff) << 4);
24772 - slotbuf[1] = ((insn[1] & 0x70000000) >> 28);
24774 +xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = {
24775 + Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0
24779 -Slot_xt_format2_Format_xt_flix64_slot3_28_set (xtensa_insnbuf insn,
24780 - const xtensa_insnbuf slotbuf)
24782 - insn[0] = (insn[0] & ~0xf0000000) | ((slotbuf[0] & 0xf) << 28);
24783 - insn[1] = (insn[1] & ~0xfffffff) | ((slotbuf[0] & 0xfffffff0) >> 4);
24784 - insn[1] = (insn[1] & ~0x70000000) | ((slotbuf[1] & 0x7) << 28);
24786 +xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = {
24787 + Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0
24790 -static xtensa_get_field_fn
24791 -Slot_inst_get_field_fns[] = {
24792 - Field_t_Slot_inst_get,
24793 - Field_bbi4_Slot_inst_get,
24794 - Field_bbi_Slot_inst_get,
24795 - Field_imm12_Slot_inst_get,
24796 - Field_imm8_Slot_inst_get,
24797 - Field_s_Slot_inst_get,
24798 - Field_imm12b_Slot_inst_get,
24799 - Field_imm16_Slot_inst_get,
24800 - Field_m_Slot_inst_get,
24801 - Field_n_Slot_inst_get,
24802 - Field_offset_Slot_inst_get,
24803 - Field_op0_Slot_inst_get,
24804 - Field_op1_Slot_inst_get,
24805 - Field_op2_Slot_inst_get,
24806 - Field_r_Slot_inst_get,
24807 - Field_sa4_Slot_inst_get,
24808 - Field_sae4_Slot_inst_get,
24809 - Field_sae_Slot_inst_get,
24810 - Field_sal_Slot_inst_get,
24811 - Field_sargt_Slot_inst_get,
24812 - Field_sas4_Slot_inst_get,
24813 - Field_sas_Slot_inst_get,
24814 - Field_sr_Slot_inst_get,
24815 - Field_st_Slot_inst_get,
24816 - Field_thi3_Slot_inst_get,
24817 - Field_imm4_Slot_inst_get,
24818 - Field_mn_Slot_inst_get,
24827 - Field_r3_Slot_inst_get,
24828 - Field_rbit2_Slot_inst_get,
24829 - Field_rhi_Slot_inst_get,
24830 - Field_t3_Slot_inst_get,
24831 - Field_tbit2_Slot_inst_get,
24832 - Field_tlo_Slot_inst_get,
24833 - Field_w_Slot_inst_get,
24834 - Field_y_Slot_inst_get,
24835 - Field_x_Slot_inst_get,
24836 - Field_t2_Slot_inst_get,
24837 - Field_s2_Slot_inst_get,
24838 - Field_r2_Slot_inst_get,
24839 - Field_t4_Slot_inst_get,
24840 - Field_s4_Slot_inst_get,
24841 - Field_r4_Slot_inst_get,
24842 - Field_t8_Slot_inst_get,
24843 - Field_s8_Slot_inst_get,
24844 - Field_r8_Slot_inst_get,
24845 - Field_xt_wbr15_imm_Slot_inst_get,
24846 - Field_xt_wbr18_imm_Slot_inst_get,
24915 - Implicit_Field_ar0_get,
24916 - Implicit_Field_ar4_get,
24917 - Implicit_Field_ar8_get,
24918 - Implicit_Field_ar12_get,
24919 - Implicit_Field_mr0_get,
24920 - Implicit_Field_mr1_get,
24921 - Implicit_Field_mr2_get,
24922 - Implicit_Field_mr3_get,
24923 - Implicit_Field_bt16_get,
24924 - Implicit_Field_bs16_get,
24925 - Implicit_Field_br16_get,
24926 - Implicit_Field_brall_get
24927 +xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = {
24928 + Opcode_rsr_ddr_Slot_inst_encode, 0, 0
24931 +xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = {
24932 + Opcode_wsr_ddr_Slot_inst_encode, 0, 0
24935 -static xtensa_set_field_fn
24936 -Slot_inst_set_field_fns[] = {
24937 - Field_t_Slot_inst_set,
24938 - Field_bbi4_Slot_inst_set,
24939 - Field_bbi_Slot_inst_set,
24940 - Field_imm12_Slot_inst_set,
24941 - Field_imm8_Slot_inst_set,
24942 - Field_s_Slot_inst_set,
24943 - Field_imm12b_Slot_inst_set,
24944 - Field_imm16_Slot_inst_set,
24945 - Field_m_Slot_inst_set,
24946 - Field_n_Slot_inst_set,
24947 - Field_offset_Slot_inst_set,
24948 - Field_op0_Slot_inst_set,
24949 - Field_op1_Slot_inst_set,
24950 - Field_op2_Slot_inst_set,
24951 - Field_r_Slot_inst_set,
24952 - Field_sa4_Slot_inst_set,
24953 - Field_sae4_Slot_inst_set,
24954 - Field_sae_Slot_inst_set,
24955 - Field_sal_Slot_inst_set,
24956 - Field_sargt_Slot_inst_set,
24957 - Field_sas4_Slot_inst_set,
24958 - Field_sas_Slot_inst_set,
24959 - Field_sr_Slot_inst_set,
24960 - Field_st_Slot_inst_set,
24961 - Field_thi3_Slot_inst_set,
24962 - Field_imm4_Slot_inst_set,
24963 - Field_mn_Slot_inst_set,
24972 - Field_r3_Slot_inst_set,
24973 - Field_rbit2_Slot_inst_set,
24974 - Field_rhi_Slot_inst_set,
24975 - Field_t3_Slot_inst_set,
24976 - Field_tbit2_Slot_inst_set,
24977 - Field_tlo_Slot_inst_set,
24978 - Field_w_Slot_inst_set,
24979 - Field_y_Slot_inst_set,
24980 - Field_x_Slot_inst_set,
24981 - Field_t2_Slot_inst_set,
24982 - Field_s2_Slot_inst_set,
24983 - Field_r2_Slot_inst_set,
24984 - Field_t4_Slot_inst_set,
24985 - Field_s4_Slot_inst_set,
24986 - Field_r4_Slot_inst_set,
24987 - Field_t8_Slot_inst_set,
24988 - Field_s8_Slot_inst_set,
24989 - Field_r8_Slot_inst_set,
24990 - Field_xt_wbr15_imm_Slot_inst_set,
24991 - Field_xt_wbr18_imm_Slot_inst_set,
25060 - Implicit_Field_set,
25061 - Implicit_Field_set,
25062 - Implicit_Field_set,
25063 - Implicit_Field_set,
25064 - Implicit_Field_set,
25065 - Implicit_Field_set,
25066 - Implicit_Field_set,
25067 - Implicit_Field_set,
25068 - Implicit_Field_set,
25069 - Implicit_Field_set,
25070 - Implicit_Field_set,
25071 - Implicit_Field_set
25072 +xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = {
25073 + Opcode_xsr_ddr_Slot_inst_encode, 0, 0
25076 -static xtensa_get_field_fn
25077 -Slot_inst16a_get_field_fns[] = {
25078 - Field_t_Slot_inst16a_get,
25083 - Field_s_Slot_inst16a_get,
25089 - Field_op0_Slot_inst16a_get,
25092 - Field_r_Slot_inst16a_get,
25100 - Field_sr_Slot_inst16a_get,
25101 - Field_st_Slot_inst16a_get,
25103 - Field_imm4_Slot_inst16a_get,
25105 - Field_i_Slot_inst16a_get,
25106 - Field_imm6lo_Slot_inst16a_get,
25107 - Field_imm6hi_Slot_inst16a_get,
25108 - Field_imm7lo_Slot_inst16a_get,
25109 - Field_imm7hi_Slot_inst16a_get,
25110 - Field_z_Slot_inst16a_get,
25111 - Field_imm6_Slot_inst16a_get,
25112 - Field_imm7_Slot_inst16a_get,
25122 - Field_t2_Slot_inst16a_get,
25123 - Field_s2_Slot_inst16a_get,
25124 - Field_r2_Slot_inst16a_get,
25125 - Field_t4_Slot_inst16a_get,
25126 - Field_s4_Slot_inst16a_get,
25127 - Field_r4_Slot_inst16a_get,
25128 - Field_t8_Slot_inst16a_get,
25129 - Field_s8_Slot_inst16a_get,
25130 - Field_r8_Slot_inst16a_get,
25201 - Implicit_Field_ar0_get,
25202 - Implicit_Field_ar4_get,
25203 - Implicit_Field_ar8_get,
25204 - Implicit_Field_ar12_get,
25205 - Implicit_Field_mr0_get,
25206 - Implicit_Field_mr1_get,
25207 - Implicit_Field_mr2_get,
25208 - Implicit_Field_mr3_get,
25209 - Implicit_Field_bt16_get,
25210 - Implicit_Field_bs16_get,
25211 - Implicit_Field_br16_get,
25212 - Implicit_Field_brall_get
25213 +xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = {
25214 + Opcode_rfdo_Slot_inst_encode, 0, 0
25217 +xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = {
25218 + Opcode_rfdd_Slot_inst_encode, 0, 0
25221 +xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = {
25222 + Opcode_wsr_mmid_Slot_inst_encode, 0, 0
25225 +xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = {
25226 + Opcode_rsr_ccount_Slot_inst_encode, 0, 0
25229 +xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = {
25230 + Opcode_wsr_ccount_Slot_inst_encode, 0, 0
25233 +xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = {
25234 + Opcode_xsr_ccount_Slot_inst_encode, 0, 0
25237 -static xtensa_set_field_fn
25238 -Slot_inst16a_set_field_fns[] = {
25239 - Field_t_Slot_inst16a_set,
25244 - Field_s_Slot_inst16a_set,
25250 - Field_op0_Slot_inst16a_set,
25253 - Field_r_Slot_inst16a_set,
25261 - Field_sr_Slot_inst16a_set,
25262 - Field_st_Slot_inst16a_set,
25264 - Field_imm4_Slot_inst16a_set,
25266 - Field_i_Slot_inst16a_set,
25267 - Field_imm6lo_Slot_inst16a_set,
25268 - Field_imm6hi_Slot_inst16a_set,
25269 - Field_imm7lo_Slot_inst16a_set,
25270 - Field_imm7hi_Slot_inst16a_set,
25271 - Field_z_Slot_inst16a_set,
25272 - Field_imm6_Slot_inst16a_set,
25273 - Field_imm7_Slot_inst16a_set,
25283 - Field_t2_Slot_inst16a_set,
25284 - Field_s2_Slot_inst16a_set,
25285 - Field_r2_Slot_inst16a_set,
25286 - Field_t4_Slot_inst16a_set,
25287 - Field_s4_Slot_inst16a_set,
25288 - Field_r4_Slot_inst16a_set,
25289 - Field_t8_Slot_inst16a_set,
25290 - Field_s8_Slot_inst16a_set,
25291 - Field_r8_Slot_inst16a_set,
25362 - Implicit_Field_set,
25363 - Implicit_Field_set,
25364 - Implicit_Field_set,
25365 - Implicit_Field_set,
25366 - Implicit_Field_set,
25367 - Implicit_Field_set,
25368 - Implicit_Field_set,
25369 - Implicit_Field_set,
25370 - Implicit_Field_set,
25371 - Implicit_Field_set,
25372 - Implicit_Field_set,
25373 - Implicit_Field_set
25374 +xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = {
25375 + Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0
25378 -static xtensa_get_field_fn
25379 -Slot_inst16b_get_field_fns[] = {
25380 - Field_t_Slot_inst16b_get,
25385 - Field_s_Slot_inst16b_get,
25391 - Field_op0_Slot_inst16b_get,
25394 - Field_r_Slot_inst16b_get,
25402 - Field_sr_Slot_inst16b_get,
25403 - Field_st_Slot_inst16b_get,
25405 - Field_imm4_Slot_inst16b_get,
25407 - Field_i_Slot_inst16b_get,
25408 - Field_imm6lo_Slot_inst16b_get,
25409 - Field_imm6hi_Slot_inst16b_get,
25410 - Field_imm7lo_Slot_inst16b_get,
25411 - Field_imm7hi_Slot_inst16b_get,
25412 - Field_z_Slot_inst16b_get,
25413 - Field_imm6_Slot_inst16b_get,
25414 - Field_imm7_Slot_inst16b_get,
25424 - Field_t2_Slot_inst16b_get,
25425 - Field_s2_Slot_inst16b_get,
25426 - Field_r2_Slot_inst16b_get,
25427 - Field_t4_Slot_inst16b_get,
25428 - Field_s4_Slot_inst16b_get,
25429 - Field_r4_Slot_inst16b_get,
25430 - Field_t8_Slot_inst16b_get,
25431 - Field_s8_Slot_inst16b_get,
25432 - Field_r8_Slot_inst16b_get,
25503 - Implicit_Field_ar0_get,
25504 - Implicit_Field_ar4_get,
25505 - Implicit_Field_ar8_get,
25506 - Implicit_Field_ar12_get,
25507 - Implicit_Field_mr0_get,
25508 - Implicit_Field_mr1_get,
25509 - Implicit_Field_mr2_get,
25510 - Implicit_Field_mr3_get,
25511 - Implicit_Field_bt16_get,
25512 - Implicit_Field_bs16_get,
25513 - Implicit_Field_br16_get,
25514 - Implicit_Field_brall_get
25515 +xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = {
25516 + Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0
25519 +xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = {
25520 + Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0
25523 +xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = {
25524 + Opcode_idtlb_Slot_inst_encode, 0, 0
25527 -static xtensa_set_field_fn
25528 -Slot_inst16b_set_field_fns[] = {
25529 - Field_t_Slot_inst16b_set,
25534 - Field_s_Slot_inst16b_set,
25540 - Field_op0_Slot_inst16b_set,
25543 - Field_r_Slot_inst16b_set,
25551 - Field_sr_Slot_inst16b_set,
25552 - Field_st_Slot_inst16b_set,
25554 - Field_imm4_Slot_inst16b_set,
25556 - Field_i_Slot_inst16b_set,
25557 - Field_imm6lo_Slot_inst16b_set,
25558 - Field_imm6hi_Slot_inst16b_set,
25559 - Field_imm7lo_Slot_inst16b_set,
25560 - Field_imm7hi_Slot_inst16b_set,
25561 - Field_z_Slot_inst16b_set,
25562 - Field_imm6_Slot_inst16b_set,
25563 - Field_imm7_Slot_inst16b_set,
25573 - Field_t2_Slot_inst16b_set,
25574 - Field_s2_Slot_inst16b_set,
25575 - Field_r2_Slot_inst16b_set,
25576 - Field_t4_Slot_inst16b_set,
25577 - Field_s4_Slot_inst16b_set,
25578 - Field_r4_Slot_inst16b_set,
25579 - Field_t8_Slot_inst16b_set,
25580 - Field_s8_Slot_inst16b_set,
25581 - Field_r8_Slot_inst16b_set,
25652 - Implicit_Field_set,
25653 - Implicit_Field_set,
25654 - Implicit_Field_set,
25655 - Implicit_Field_set,
25656 - Implicit_Field_set,
25657 - Implicit_Field_set,
25658 - Implicit_Field_set,
25659 - Implicit_Field_set,
25660 - Implicit_Field_set,
25661 - Implicit_Field_set,
25662 - Implicit_Field_set,
25663 - Implicit_Field_set
25664 +xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = {
25665 + Opcode_pdtlb_Slot_inst_encode, 0, 0
25668 -static xtensa_get_field_fn
25669 -Slot_xt_flix64_slot0_get_field_fns[] = {
25670 - Field_t_Slot_xt_flix64_slot0_get,
25674 - Field_imm8_Slot_xt_flix64_slot0_get,
25675 - Field_s_Slot_xt_flix64_slot0_get,
25676 - Field_imm12b_Slot_xt_flix64_slot0_get,
25677 - Field_imm16_Slot_xt_flix64_slot0_get,
25678 - Field_m_Slot_xt_flix64_slot0_get,
25679 - Field_n_Slot_xt_flix64_slot0_get,
25682 - Field_op1_Slot_xt_flix64_slot0_get,
25683 - Field_op2_Slot_xt_flix64_slot0_get,
25684 - Field_r_Slot_xt_flix64_slot0_get,
25686 - Field_sae4_Slot_xt_flix64_slot0_get,
25687 - Field_sae_Slot_xt_flix64_slot0_get,
25688 - Field_sal_Slot_xt_flix64_slot0_get,
25689 - Field_sargt_Slot_xt_flix64_slot0_get,
25691 - Field_sas_Slot_xt_flix64_slot0_get,
25694 - Field_thi3_Slot_xt_flix64_slot0_get,
25725 - Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_get,
25726 - Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_get,
25727 - Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_get,
25728 - Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_get,
25729 - Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_get,
25730 - Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_get,
25792 - Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_get,
25793 - Implicit_Field_ar0_get,
25794 - Implicit_Field_ar4_get,
25795 - Implicit_Field_ar8_get,
25796 - Implicit_Field_ar12_get,
25797 - Implicit_Field_mr0_get,
25798 - Implicit_Field_mr1_get,
25799 - Implicit_Field_mr2_get,
25800 - Implicit_Field_mr3_get,
25801 - Implicit_Field_bt16_get,
25802 - Implicit_Field_bs16_get,
25803 - Implicit_Field_br16_get,
25804 - Implicit_Field_brall_get
25805 +xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = {
25806 + Opcode_rdtlb0_Slot_inst_encode, 0, 0
25809 +xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = {
25810 + Opcode_rdtlb1_Slot_inst_encode, 0, 0
25813 +xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = {
25814 + Opcode_wdtlb_Slot_inst_encode, 0, 0
25817 +xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = {
25818 + Opcode_iitlb_Slot_inst_encode, 0, 0
25821 +xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = {
25822 + Opcode_pitlb_Slot_inst_encode, 0, 0
25825 +xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = {
25826 + Opcode_ritlb0_Slot_inst_encode, 0, 0
25829 +xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = {
25830 + Opcode_ritlb1_Slot_inst_encode, 0, 0
25833 +xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = {
25834 + Opcode_witlb_Slot_inst_encode, 0, 0
25837 +xtensa_opcode_encode_fn Opcode_min_encode_fns[] = {
25838 + Opcode_min_Slot_inst_encode, 0, 0
25841 +xtensa_opcode_encode_fn Opcode_max_encode_fns[] = {
25842 + Opcode_max_Slot_inst_encode, 0, 0
25845 +xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = {
25846 + Opcode_minu_Slot_inst_encode, 0, 0
25849 +xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = {
25850 + Opcode_maxu_Slot_inst_encode, 0, 0
25853 +xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = {
25854 + Opcode_nsa_Slot_inst_encode, 0, 0
25857 +xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = {
25858 + Opcode_nsau_Slot_inst_encode, 0, 0
25861 +xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = {
25862 + Opcode_sext_Slot_inst_encode, 0, 0
25865 +xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = {
25866 + Opcode_l32ai_Slot_inst_encode, 0, 0
25869 +xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = {
25870 + Opcode_s32ri_Slot_inst_encode, 0, 0
25873 +xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = {
25874 + Opcode_s32c1i_Slot_inst_encode, 0, 0
25877 +xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = {
25878 + Opcode_rsr_scompare1_Slot_inst_encode, 0, 0
25881 +xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = {
25882 + Opcode_wsr_scompare1_Slot_inst_encode, 0, 0
25885 +xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = {
25886 + Opcode_xsr_scompare1_Slot_inst_encode, 0, 0
25889 +xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = {
25890 + Opcode_mull_Slot_inst_encode, 0, 0
25893 +xtensa_opcode_encode_fn Opcode_muluh_encode_fns[] = {
25894 + Opcode_muluh_Slot_inst_encode, 0, 0
25897 +xtensa_opcode_encode_fn Opcode_mulsh_encode_fns[] = {
25898 + Opcode_mulsh_Slot_inst_encode, 0, 0
25901 +xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = {
25902 + Opcode_mul16u_Slot_inst_encode, 0, 0
25905 +xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = {
25906 + Opcode_mul16s_Slot_inst_encode, 0, 0
25910 +/* Opcode table. */
25912 +static xtensa_opcode_internal opcodes[] = {
25913 + { "excw", 0 /* xt_iclass_excw */,
25915 + Opcode_excw_encode_fns, 0, 0 },
25916 + { "rfe", 1 /* xt_iclass_rfe */,
25917 + XTENSA_OPCODE_IS_JUMP,
25918 + Opcode_rfe_encode_fns, 0, 0 },
25919 + { "rfde", 2 /* xt_iclass_rfde */,
25920 + XTENSA_OPCODE_IS_JUMP,
25921 + Opcode_rfde_encode_fns, 0, 0 },
25922 + { "syscall", 3 /* xt_iclass_syscall */,
25924 + Opcode_syscall_encode_fns, 0, 0 },
25925 + { "simcall", 4 /* xt_iclass_simcall */,
25927 + Opcode_simcall_encode_fns, 0, 0 },
25928 + { "call12", 5 /* xt_iclass_call12 */,
25929 + XTENSA_OPCODE_IS_CALL,
25930 + Opcode_call12_encode_fns, 0, 0 },
25931 + { "call8", 6 /* xt_iclass_call8 */,
25932 + XTENSA_OPCODE_IS_CALL,
25933 + Opcode_call8_encode_fns, 0, 0 },
25934 + { "call4", 7 /* xt_iclass_call4 */,
25935 + XTENSA_OPCODE_IS_CALL,
25936 + Opcode_call4_encode_fns, 0, 0 },
25937 + { "callx12", 8 /* xt_iclass_callx12 */,
25938 + XTENSA_OPCODE_IS_CALL,
25939 + Opcode_callx12_encode_fns, 0, 0 },
25940 + { "callx8", 9 /* xt_iclass_callx8 */,
25941 + XTENSA_OPCODE_IS_CALL,
25942 + Opcode_callx8_encode_fns, 0, 0 },
25943 + { "callx4", 10 /* xt_iclass_callx4 */,
25944 + XTENSA_OPCODE_IS_CALL,
25945 + Opcode_callx4_encode_fns, 0, 0 },
25946 + { "entry", 11 /* xt_iclass_entry */,
25948 + Opcode_entry_encode_fns, 0, 0 },
25949 + { "movsp", 12 /* xt_iclass_movsp */,
25951 + Opcode_movsp_encode_fns, 0, 0 },
25952 + { "rotw", 13 /* xt_iclass_rotw */,
25954 + Opcode_rotw_encode_fns, 0, 0 },
25955 + { "retw", 14 /* xt_iclass_retw */,
25956 + XTENSA_OPCODE_IS_JUMP,
25957 + Opcode_retw_encode_fns, 0, 0 },
25958 + { "retw.n", 14 /* xt_iclass_retw */,
25959 + XTENSA_OPCODE_IS_JUMP,
25960 + Opcode_retw_n_encode_fns, 0, 0 },
25961 + { "rfwo", 15 /* xt_iclass_rfwou */,
25962 + XTENSA_OPCODE_IS_JUMP,
25963 + Opcode_rfwo_encode_fns, 0, 0 },
25964 + { "rfwu", 15 /* xt_iclass_rfwou */,
25965 + XTENSA_OPCODE_IS_JUMP,
25966 + Opcode_rfwu_encode_fns, 0, 0 },
25967 + { "l32e", 16 /* xt_iclass_l32e */,
25969 + Opcode_l32e_encode_fns, 0, 0 },
25970 + { "s32e", 17 /* xt_iclass_s32e */,
25972 + Opcode_s32e_encode_fns, 0, 0 },
25973 + { "rsr.windowbase", 18 /* xt_iclass_rsr.windowbase */,
25975 + Opcode_rsr_windowbase_encode_fns, 0, 0 },
25976 + { "wsr.windowbase", 19 /* xt_iclass_wsr.windowbase */,
25978 + Opcode_wsr_windowbase_encode_fns, 0, 0 },
25979 + { "xsr.windowbase", 20 /* xt_iclass_xsr.windowbase */,
25981 + Opcode_xsr_windowbase_encode_fns, 0, 0 },
25982 + { "rsr.windowstart", 21 /* xt_iclass_rsr.windowstart */,
25984 + Opcode_rsr_windowstart_encode_fns, 0, 0 },
25985 + { "wsr.windowstart", 22 /* xt_iclass_wsr.windowstart */,
25987 + Opcode_wsr_windowstart_encode_fns, 0, 0 },
25988 + { "xsr.windowstart", 23 /* xt_iclass_xsr.windowstart */,
25990 + Opcode_xsr_windowstart_encode_fns, 0, 0 },
25991 + { "add.n", 24 /* xt_iclass_add.n */,
25993 + Opcode_add_n_encode_fns, 0, 0 },
25994 + { "addi.n", 25 /* xt_iclass_addi.n */,
25996 + Opcode_addi_n_encode_fns, 0, 0 },
25997 + { "beqz.n", 26 /* xt_iclass_bz6 */,
25998 + XTENSA_OPCODE_IS_BRANCH,
25999 + Opcode_beqz_n_encode_fns, 0, 0 },
26000 + { "bnez.n", 26 /* xt_iclass_bz6 */,
26001 + XTENSA_OPCODE_IS_BRANCH,
26002 + Opcode_bnez_n_encode_fns, 0, 0 },
26003 + { "ill.n", 27 /* xt_iclass_ill.n */,
26005 + Opcode_ill_n_encode_fns, 0, 0 },
26006 + { "l32i.n", 28 /* xt_iclass_loadi4 */,
26008 + Opcode_l32i_n_encode_fns, 0, 0 },
26009 + { "mov.n", 29 /* xt_iclass_mov.n */,
26011 + Opcode_mov_n_encode_fns, 0, 0 },
26012 + { "movi.n", 30 /* xt_iclass_movi.n */,
26014 + Opcode_movi_n_encode_fns, 0, 0 },
26015 + { "nop.n", 31 /* xt_iclass_nopn */,
26017 + Opcode_nop_n_encode_fns, 0, 0 },
26018 + { "ret.n", 32 /* xt_iclass_retn */,
26019 + XTENSA_OPCODE_IS_JUMP,
26020 + Opcode_ret_n_encode_fns, 0, 0 },
26021 + { "s32i.n", 33 /* xt_iclass_storei4 */,
26023 + Opcode_s32i_n_encode_fns, 0, 0 },
26024 + { "rur.threadptr", 34 /* rur_threadptr */,
26026 + Opcode_rur_threadptr_encode_fns, 0, 0 },
26027 + { "wur.threadptr", 35 /* wur_threadptr */,
26029 + Opcode_wur_threadptr_encode_fns, 0, 0 },
26030 + { "addi", 36 /* xt_iclass_addi */,
26032 + Opcode_addi_encode_fns, 0, 0 },
26033 + { "addmi", 37 /* xt_iclass_addmi */,
26035 + Opcode_addmi_encode_fns, 0, 0 },
26036 + { "add", 38 /* xt_iclass_addsub */,
26038 + Opcode_add_encode_fns, 0, 0 },
26039 + { "sub", 38 /* xt_iclass_addsub */,
26041 + Opcode_sub_encode_fns, 0, 0 },
26042 + { "addx2", 38 /* xt_iclass_addsub */,
26044 + Opcode_addx2_encode_fns, 0, 0 },
26045 + { "addx4", 38 /* xt_iclass_addsub */,
26047 + Opcode_addx4_encode_fns, 0, 0 },
26048 + { "addx8", 38 /* xt_iclass_addsub */,
26050 + Opcode_addx8_encode_fns, 0, 0 },
26051 + { "subx2", 38 /* xt_iclass_addsub */,
26053 + Opcode_subx2_encode_fns, 0, 0 },
26054 + { "subx4", 38 /* xt_iclass_addsub */,
26056 + Opcode_subx4_encode_fns, 0, 0 },
26057 + { "subx8", 38 /* xt_iclass_addsub */,
26059 + Opcode_subx8_encode_fns, 0, 0 },
26060 + { "and", 39 /* xt_iclass_bit */,
26062 + Opcode_and_encode_fns, 0, 0 },
26063 + { "or", 39 /* xt_iclass_bit */,
26065 + Opcode_or_encode_fns, 0, 0 },
26066 + { "xor", 39 /* xt_iclass_bit */,
26068 + Opcode_xor_encode_fns, 0, 0 },
26069 + { "beqi", 40 /* xt_iclass_bsi8 */,
26070 + XTENSA_OPCODE_IS_BRANCH,
26071 + Opcode_beqi_encode_fns, 0, 0 },
26072 + { "bnei", 40 /* xt_iclass_bsi8 */,
26073 + XTENSA_OPCODE_IS_BRANCH,
26074 + Opcode_bnei_encode_fns, 0, 0 },
26075 + { "bgei", 40 /* xt_iclass_bsi8 */,
26076 + XTENSA_OPCODE_IS_BRANCH,
26077 + Opcode_bgei_encode_fns, 0, 0 },
26078 + { "blti", 40 /* xt_iclass_bsi8 */,
26079 + XTENSA_OPCODE_IS_BRANCH,
26080 + Opcode_blti_encode_fns, 0, 0 },
26081 + { "bbci", 41 /* xt_iclass_bsi8b */,
26082 + XTENSA_OPCODE_IS_BRANCH,
26083 + Opcode_bbci_encode_fns, 0, 0 },
26084 + { "bbsi", 41 /* xt_iclass_bsi8b */,
26085 + XTENSA_OPCODE_IS_BRANCH,
26086 + Opcode_bbsi_encode_fns, 0, 0 },
26087 + { "bgeui", 42 /* xt_iclass_bsi8u */,
26088 + XTENSA_OPCODE_IS_BRANCH,
26089 + Opcode_bgeui_encode_fns, 0, 0 },
26090 + { "bltui", 42 /* xt_iclass_bsi8u */,
26091 + XTENSA_OPCODE_IS_BRANCH,
26092 + Opcode_bltui_encode_fns, 0, 0 },
26093 + { "beq", 43 /* xt_iclass_bst8 */,
26094 + XTENSA_OPCODE_IS_BRANCH,
26095 + Opcode_beq_encode_fns, 0, 0 },
26096 + { "bne", 43 /* xt_iclass_bst8 */,
26097 + XTENSA_OPCODE_IS_BRANCH,
26098 + Opcode_bne_encode_fns, 0, 0 },
26099 + { "bge", 43 /* xt_iclass_bst8 */,
26100 + XTENSA_OPCODE_IS_BRANCH,
26101 + Opcode_bge_encode_fns, 0, 0 },
26102 + { "blt", 43 /* xt_iclass_bst8 */,
26103 + XTENSA_OPCODE_IS_BRANCH,
26104 + Opcode_blt_encode_fns, 0, 0 },
26105 + { "bgeu", 43 /* xt_iclass_bst8 */,
26106 + XTENSA_OPCODE_IS_BRANCH,
26107 + Opcode_bgeu_encode_fns, 0, 0 },
26108 + { "bltu", 43 /* xt_iclass_bst8 */,
26109 + XTENSA_OPCODE_IS_BRANCH,
26110 + Opcode_bltu_encode_fns, 0, 0 },
26111 + { "bany", 43 /* xt_iclass_bst8 */,
26112 + XTENSA_OPCODE_IS_BRANCH,
26113 + Opcode_bany_encode_fns, 0, 0 },
26114 + { "bnone", 43 /* xt_iclass_bst8 */,
26115 + XTENSA_OPCODE_IS_BRANCH,
26116 + Opcode_bnone_encode_fns, 0, 0 },
26117 + { "ball", 43 /* xt_iclass_bst8 */,
26118 + XTENSA_OPCODE_IS_BRANCH,
26119 + Opcode_ball_encode_fns, 0, 0 },
26120 + { "bnall", 43 /* xt_iclass_bst8 */,
26121 + XTENSA_OPCODE_IS_BRANCH,
26122 + Opcode_bnall_encode_fns, 0, 0 },
26123 + { "bbc", 43 /* xt_iclass_bst8 */,
26124 + XTENSA_OPCODE_IS_BRANCH,
26125 + Opcode_bbc_encode_fns, 0, 0 },
26126 + { "bbs", 43 /* xt_iclass_bst8 */,
26127 + XTENSA_OPCODE_IS_BRANCH,
26128 + Opcode_bbs_encode_fns, 0, 0 },
26129 + { "beqz", 44 /* xt_iclass_bsz12 */,
26130 + XTENSA_OPCODE_IS_BRANCH,
26131 + Opcode_beqz_encode_fns, 0, 0 },
26132 + { "bnez", 44 /* xt_iclass_bsz12 */,
26133 + XTENSA_OPCODE_IS_BRANCH,
26134 + Opcode_bnez_encode_fns, 0, 0 },
26135 + { "bgez", 44 /* xt_iclass_bsz12 */,
26136 + XTENSA_OPCODE_IS_BRANCH,
26137 + Opcode_bgez_encode_fns, 0, 0 },
26138 + { "bltz", 44 /* xt_iclass_bsz12 */,
26139 + XTENSA_OPCODE_IS_BRANCH,
26140 + Opcode_bltz_encode_fns, 0, 0 },
26141 + { "call0", 45 /* xt_iclass_call0 */,
26142 + XTENSA_OPCODE_IS_CALL,
26143 + Opcode_call0_encode_fns, 0, 0 },
26144 + { "callx0", 46 /* xt_iclass_callx0 */,
26145 + XTENSA_OPCODE_IS_CALL,
26146 + Opcode_callx0_encode_fns, 0, 0 },
26147 + { "extui", 47 /* xt_iclass_exti */,
26149 + Opcode_extui_encode_fns, 0, 0 },
26150 + { "ill", 48 /* xt_iclass_ill */,
26152 + Opcode_ill_encode_fns, 0, 0 },
26153 + { "j", 49 /* xt_iclass_jump */,
26154 + XTENSA_OPCODE_IS_JUMP,
26155 + Opcode_j_encode_fns, 0, 0 },
26156 + { "jx", 50 /* xt_iclass_jumpx */,
26157 + XTENSA_OPCODE_IS_JUMP,
26158 + Opcode_jx_encode_fns, 0, 0 },
26159 + { "l16ui", 51 /* xt_iclass_l16ui */,
26161 + Opcode_l16ui_encode_fns, 0, 0 },
26162 + { "l16si", 52 /* xt_iclass_l16si */,
26164 + Opcode_l16si_encode_fns, 0, 0 },
26165 + { "l32i", 53 /* xt_iclass_l32i */,
26167 + Opcode_l32i_encode_fns, 0, 0 },
26168 + { "l32r", 54 /* xt_iclass_l32r */,
26170 + Opcode_l32r_encode_fns, 0, 0 },
26171 + { "l8ui", 55 /* xt_iclass_l8i */,
26173 + Opcode_l8ui_encode_fns, 0, 0 },
26174 + { "loop", 56 /* xt_iclass_loop */,
26175 + XTENSA_OPCODE_IS_LOOP,
26176 + Opcode_loop_encode_fns, 0, 0 },
26177 + { "loopnez", 57 /* xt_iclass_loopz */,
26178 + XTENSA_OPCODE_IS_LOOP,
26179 + Opcode_loopnez_encode_fns, 0, 0 },
26180 + { "loopgtz", 57 /* xt_iclass_loopz */,
26181 + XTENSA_OPCODE_IS_LOOP,
26182 + Opcode_loopgtz_encode_fns, 0, 0 },
26183 + { "movi", 58 /* xt_iclass_movi */,
26185 + Opcode_movi_encode_fns, 0, 0 },
26186 + { "moveqz", 59 /* xt_iclass_movz */,
26188 + Opcode_moveqz_encode_fns, 0, 0 },
26189 + { "movnez", 59 /* xt_iclass_movz */,
26191 + Opcode_movnez_encode_fns, 0, 0 },
26192 + { "movltz", 59 /* xt_iclass_movz */,
26194 + Opcode_movltz_encode_fns, 0, 0 },
26195 + { "movgez", 59 /* xt_iclass_movz */,
26197 + Opcode_movgez_encode_fns, 0, 0 },
26198 + { "neg", 60 /* xt_iclass_neg */,
26200 + Opcode_neg_encode_fns, 0, 0 },
26201 + { "abs", 60 /* xt_iclass_neg */,
26203 + Opcode_abs_encode_fns, 0, 0 },
26204 + { "nop", 61 /* xt_iclass_nop */,
26206 + Opcode_nop_encode_fns, 0, 0 },
26207 + { "ret", 62 /* xt_iclass_return */,
26208 + XTENSA_OPCODE_IS_JUMP,
26209 + Opcode_ret_encode_fns, 0, 0 },
26210 + { "s16i", 63 /* xt_iclass_s16i */,
26212 + Opcode_s16i_encode_fns, 0, 0 },
26213 + { "s32i", 64 /* xt_iclass_s32i */,
26215 + Opcode_s32i_encode_fns, 0, 0 },
26216 + { "s8i", 65 /* xt_iclass_s8i */,
26218 + Opcode_s8i_encode_fns, 0, 0 },
26219 + { "ssr", 66 /* xt_iclass_sar */,
26221 + Opcode_ssr_encode_fns, 0, 0 },
26222 + { "ssl", 66 /* xt_iclass_sar */,
26224 + Opcode_ssl_encode_fns, 0, 0 },
26225 + { "ssa8l", 66 /* xt_iclass_sar */,
26227 + Opcode_ssa8l_encode_fns, 0, 0 },
26228 + { "ssa8b", 66 /* xt_iclass_sar */,
26230 + Opcode_ssa8b_encode_fns, 0, 0 },
26231 + { "ssai", 67 /* xt_iclass_sari */,
26233 + Opcode_ssai_encode_fns, 0, 0 },
26234 + { "sll", 68 /* xt_iclass_shifts */,
26236 + Opcode_sll_encode_fns, 0, 0 },
26237 + { "src", 69 /* xt_iclass_shiftst */,
26239 + Opcode_src_encode_fns, 0, 0 },
26240 + { "srl", 70 /* xt_iclass_shiftt */,
26242 + Opcode_srl_encode_fns, 0, 0 },
26243 + { "sra", 70 /* xt_iclass_shiftt */,
26245 + Opcode_sra_encode_fns, 0, 0 },
26246 + { "slli", 71 /* xt_iclass_slli */,
26248 + Opcode_slli_encode_fns, 0, 0 },
26249 + { "srai", 72 /* xt_iclass_srai */,
26251 + Opcode_srai_encode_fns, 0, 0 },
26252 + { "srli", 73 /* xt_iclass_srli */,
26254 + Opcode_srli_encode_fns, 0, 0 },
26255 + { "memw", 74 /* xt_iclass_memw */,
26257 + Opcode_memw_encode_fns, 0, 0 },
26258 + { "extw", 75 /* xt_iclass_extw */,
26260 + Opcode_extw_encode_fns, 0, 0 },
26261 + { "isync", 76 /* xt_iclass_isync */,
26263 + Opcode_isync_encode_fns, 0, 0 },
26264 + { "rsync", 77 /* xt_iclass_sync */,
26266 + Opcode_rsync_encode_fns, 0, 0 },
26267 + { "esync", 77 /* xt_iclass_sync */,
26269 + Opcode_esync_encode_fns, 0, 0 },
26270 + { "dsync", 77 /* xt_iclass_sync */,
26272 + Opcode_dsync_encode_fns, 0, 0 },
26273 + { "rsil", 78 /* xt_iclass_rsil */,
26275 + Opcode_rsil_encode_fns, 0, 0 },
26276 + { "rsr.lend", 79 /* xt_iclass_rsr.lend */,
26278 + Opcode_rsr_lend_encode_fns, 0, 0 },
26279 + { "wsr.lend", 80 /* xt_iclass_wsr.lend */,
26281 + Opcode_wsr_lend_encode_fns, 0, 0 },
26282 + { "xsr.lend", 81 /* xt_iclass_xsr.lend */,
26284 + Opcode_xsr_lend_encode_fns, 0, 0 },
26285 + { "rsr.lcount", 82 /* xt_iclass_rsr.lcount */,
26287 + Opcode_rsr_lcount_encode_fns, 0, 0 },
26288 + { "wsr.lcount", 83 /* xt_iclass_wsr.lcount */,
26290 + Opcode_wsr_lcount_encode_fns, 0, 0 },
26291 + { "xsr.lcount", 84 /* xt_iclass_xsr.lcount */,
26293 + Opcode_xsr_lcount_encode_fns, 0, 0 },
26294 + { "rsr.lbeg", 85 /* xt_iclass_rsr.lbeg */,
26296 + Opcode_rsr_lbeg_encode_fns, 0, 0 },
26297 + { "wsr.lbeg", 86 /* xt_iclass_wsr.lbeg */,
26299 + Opcode_wsr_lbeg_encode_fns, 0, 0 },
26300 + { "xsr.lbeg", 87 /* xt_iclass_xsr.lbeg */,
26302 + Opcode_xsr_lbeg_encode_fns, 0, 0 },
26303 + { "rsr.sar", 88 /* xt_iclass_rsr.sar */,
26305 + Opcode_rsr_sar_encode_fns, 0, 0 },
26306 + { "wsr.sar", 89 /* xt_iclass_wsr.sar */,
26308 + Opcode_wsr_sar_encode_fns, 0, 0 },
26309 + { "xsr.sar", 90 /* xt_iclass_xsr.sar */,
26311 + Opcode_xsr_sar_encode_fns, 0, 0 },
26312 + { "rsr.litbase", 91 /* xt_iclass_rsr.litbase */,
26314 + Opcode_rsr_litbase_encode_fns, 0, 0 },
26315 + { "wsr.litbase", 92 /* xt_iclass_wsr.litbase */,
26317 + Opcode_wsr_litbase_encode_fns, 0, 0 },
26318 + { "xsr.litbase", 93 /* xt_iclass_xsr.litbase */,
26320 + Opcode_xsr_litbase_encode_fns, 0, 0 },
26321 + { "rsr.176", 94 /* xt_iclass_rsr.176 */,
26323 + Opcode_rsr_176_encode_fns, 0, 0 },
26324 + { "rsr.208", 95 /* xt_iclass_rsr.208 */,
26326 + Opcode_rsr_208_encode_fns, 0, 0 },
26327 + { "rsr.ps", 96 /* xt_iclass_rsr.ps */,
26329 + Opcode_rsr_ps_encode_fns, 0, 0 },
26330 + { "wsr.ps", 97 /* xt_iclass_wsr.ps */,
26332 + Opcode_wsr_ps_encode_fns, 0, 0 },
26333 + { "xsr.ps", 98 /* xt_iclass_xsr.ps */,
26335 + Opcode_xsr_ps_encode_fns, 0, 0 },
26336 + { "rsr.epc1", 99 /* xt_iclass_rsr.epc1 */,
26338 + Opcode_rsr_epc1_encode_fns, 0, 0 },
26339 + { "wsr.epc1", 100 /* xt_iclass_wsr.epc1 */,
26341 + Opcode_wsr_epc1_encode_fns, 0, 0 },
26342 + { "xsr.epc1", 101 /* xt_iclass_xsr.epc1 */,
26344 + Opcode_xsr_epc1_encode_fns, 0, 0 },
26345 + { "rsr.excsave1", 102 /* xt_iclass_rsr.excsave1 */,
26347 + Opcode_rsr_excsave1_encode_fns, 0, 0 },
26348 + { "wsr.excsave1", 103 /* xt_iclass_wsr.excsave1 */,
26350 + Opcode_wsr_excsave1_encode_fns, 0, 0 },
26351 + { "xsr.excsave1", 104 /* xt_iclass_xsr.excsave1 */,
26353 + Opcode_xsr_excsave1_encode_fns, 0, 0 },
26354 + { "rsr.epc2", 105 /* xt_iclass_rsr.epc2 */,
26356 + Opcode_rsr_epc2_encode_fns, 0, 0 },
26357 + { "wsr.epc2", 106 /* xt_iclass_wsr.epc2 */,
26359 + Opcode_wsr_epc2_encode_fns, 0, 0 },
26360 + { "xsr.epc2", 107 /* xt_iclass_xsr.epc2 */,
26362 + Opcode_xsr_epc2_encode_fns, 0, 0 },
26363 + { "rsr.excsave2", 108 /* xt_iclass_rsr.excsave2 */,
26365 + Opcode_rsr_excsave2_encode_fns, 0, 0 },
26366 + { "wsr.excsave2", 109 /* xt_iclass_wsr.excsave2 */,
26368 + Opcode_wsr_excsave2_encode_fns, 0, 0 },
26369 + { "xsr.excsave2", 110 /* xt_iclass_xsr.excsave2 */,
26371 + Opcode_xsr_excsave2_encode_fns, 0, 0 },
26372 + { "rsr.epc3", 111 /* xt_iclass_rsr.epc3 */,
26374 + Opcode_rsr_epc3_encode_fns, 0, 0 },
26375 + { "wsr.epc3", 112 /* xt_iclass_wsr.epc3 */,
26377 + Opcode_wsr_epc3_encode_fns, 0, 0 },
26378 + { "xsr.epc3", 113 /* xt_iclass_xsr.epc3 */,
26380 + Opcode_xsr_epc3_encode_fns, 0, 0 },
26381 + { "rsr.excsave3", 114 /* xt_iclass_rsr.excsave3 */,
26383 + Opcode_rsr_excsave3_encode_fns, 0, 0 },
26384 + { "wsr.excsave3", 115 /* xt_iclass_wsr.excsave3 */,
26386 + Opcode_wsr_excsave3_encode_fns, 0, 0 },
26387 + { "xsr.excsave3", 116 /* xt_iclass_xsr.excsave3 */,
26389 + Opcode_xsr_excsave3_encode_fns, 0, 0 },
26390 + { "rsr.epc4", 117 /* xt_iclass_rsr.epc4 */,
26392 + Opcode_rsr_epc4_encode_fns, 0, 0 },
26393 + { "wsr.epc4", 118 /* xt_iclass_wsr.epc4 */,
26395 + Opcode_wsr_epc4_encode_fns, 0, 0 },
26396 + { "xsr.epc4", 119 /* xt_iclass_xsr.epc4 */,
26398 + Opcode_xsr_epc4_encode_fns, 0, 0 },
26399 + { "rsr.excsave4", 120 /* xt_iclass_rsr.excsave4 */,
26401 + Opcode_rsr_excsave4_encode_fns, 0, 0 },
26402 + { "wsr.excsave4", 121 /* xt_iclass_wsr.excsave4 */,
26404 + Opcode_wsr_excsave4_encode_fns, 0, 0 },
26405 + { "xsr.excsave4", 122 /* xt_iclass_xsr.excsave4 */,
26407 + Opcode_xsr_excsave4_encode_fns, 0, 0 },
26408 + { "rsr.epc5", 123 /* xt_iclass_rsr.epc5 */,
26410 + Opcode_rsr_epc5_encode_fns, 0, 0 },
26411 + { "wsr.epc5", 124 /* xt_iclass_wsr.epc5 */,
26413 + Opcode_wsr_epc5_encode_fns, 0, 0 },
26414 + { "xsr.epc5", 125 /* xt_iclass_xsr.epc5 */,
26416 + Opcode_xsr_epc5_encode_fns, 0, 0 },
26417 + { "rsr.excsave5", 126 /* xt_iclass_rsr.excsave5 */,
26419 + Opcode_rsr_excsave5_encode_fns, 0, 0 },
26420 + { "wsr.excsave5", 127 /* xt_iclass_wsr.excsave5 */,
26422 + Opcode_wsr_excsave5_encode_fns, 0, 0 },
26423 + { "xsr.excsave5", 128 /* xt_iclass_xsr.excsave5 */,
26425 + Opcode_xsr_excsave5_encode_fns, 0, 0 },
26426 + { "rsr.eps2", 129 /* xt_iclass_rsr.eps2 */,
26428 + Opcode_rsr_eps2_encode_fns, 0, 0 },
26429 + { "wsr.eps2", 130 /* xt_iclass_wsr.eps2 */,
26431 + Opcode_wsr_eps2_encode_fns, 0, 0 },
26432 + { "xsr.eps2", 131 /* xt_iclass_xsr.eps2 */,
26434 + Opcode_xsr_eps2_encode_fns, 0, 0 },
26435 + { "rsr.eps3", 132 /* xt_iclass_rsr.eps3 */,
26437 + Opcode_rsr_eps3_encode_fns, 0, 0 },
26438 + { "wsr.eps3", 133 /* xt_iclass_wsr.eps3 */,
26440 + Opcode_wsr_eps3_encode_fns, 0, 0 },
26441 + { "xsr.eps3", 134 /* xt_iclass_xsr.eps3 */,
26443 + Opcode_xsr_eps3_encode_fns, 0, 0 },
26444 + { "rsr.eps4", 135 /* xt_iclass_rsr.eps4 */,
26446 + Opcode_rsr_eps4_encode_fns, 0, 0 },
26447 + { "wsr.eps4", 136 /* xt_iclass_wsr.eps4 */,
26449 + Opcode_wsr_eps4_encode_fns, 0, 0 },
26450 + { "xsr.eps4", 137 /* xt_iclass_xsr.eps4 */,
26452 + Opcode_xsr_eps4_encode_fns, 0, 0 },
26453 + { "rsr.eps5", 138 /* xt_iclass_rsr.eps5 */,
26455 + Opcode_rsr_eps5_encode_fns, 0, 0 },
26456 + { "wsr.eps5", 139 /* xt_iclass_wsr.eps5 */,
26458 + Opcode_wsr_eps5_encode_fns, 0, 0 },
26459 + { "xsr.eps5", 140 /* xt_iclass_xsr.eps5 */,
26461 + Opcode_xsr_eps5_encode_fns, 0, 0 },
26462 + { "rsr.excvaddr", 141 /* xt_iclass_rsr.excvaddr */,
26464 + Opcode_rsr_excvaddr_encode_fns, 0, 0 },
26465 + { "wsr.excvaddr", 142 /* xt_iclass_wsr.excvaddr */,
26467 + Opcode_wsr_excvaddr_encode_fns, 0, 0 },
26468 + { "xsr.excvaddr", 143 /* xt_iclass_xsr.excvaddr */,
26470 + Opcode_xsr_excvaddr_encode_fns, 0, 0 },
26471 + { "rsr.depc", 144 /* xt_iclass_rsr.depc */,
26473 + Opcode_rsr_depc_encode_fns, 0, 0 },
26474 + { "wsr.depc", 145 /* xt_iclass_wsr.depc */,
26476 + Opcode_wsr_depc_encode_fns, 0, 0 },
26477 + { "xsr.depc", 146 /* xt_iclass_xsr.depc */,
26479 + Opcode_xsr_depc_encode_fns, 0, 0 },
26480 + { "rsr.exccause", 147 /* xt_iclass_rsr.exccause */,
26482 + Opcode_rsr_exccause_encode_fns, 0, 0 },
26483 + { "wsr.exccause", 148 /* xt_iclass_wsr.exccause */,
26485 + Opcode_wsr_exccause_encode_fns, 0, 0 },
26486 + { "xsr.exccause", 149 /* xt_iclass_xsr.exccause */,
26488 + Opcode_xsr_exccause_encode_fns, 0, 0 },
26489 + { "rsr.misc0", 150 /* xt_iclass_rsr.misc0 */,
26491 + Opcode_rsr_misc0_encode_fns, 0, 0 },
26492 + { "wsr.misc0", 151 /* xt_iclass_wsr.misc0 */,
26494 + Opcode_wsr_misc0_encode_fns, 0, 0 },
26495 + { "xsr.misc0", 152 /* xt_iclass_xsr.misc0 */,
26497 + Opcode_xsr_misc0_encode_fns, 0, 0 },
26498 + { "rsr.misc1", 153 /* xt_iclass_rsr.misc1 */,
26500 + Opcode_rsr_misc1_encode_fns, 0, 0 },
26501 + { "wsr.misc1", 154 /* xt_iclass_wsr.misc1 */,
26503 + Opcode_wsr_misc1_encode_fns, 0, 0 },
26504 + { "xsr.misc1", 155 /* xt_iclass_xsr.misc1 */,
26506 + Opcode_xsr_misc1_encode_fns, 0, 0 },
26507 + { "rsr.prid", 156 /* xt_iclass_rsr.prid */,
26509 + Opcode_rsr_prid_encode_fns, 0, 0 },
26510 + { "rsr.vecbase", 157 /* xt_iclass_rsr.vecbase */,
26512 + Opcode_rsr_vecbase_encode_fns, 0, 0 },
26513 + { "wsr.vecbase", 158 /* xt_iclass_wsr.vecbase */,
26515 + Opcode_wsr_vecbase_encode_fns, 0, 0 },
26516 + { "xsr.vecbase", 159 /* xt_iclass_xsr.vecbase */,
26518 + Opcode_xsr_vecbase_encode_fns, 0, 0 },
26519 + { "rfi", 160 /* xt_iclass_rfi */,
26520 + XTENSA_OPCODE_IS_JUMP,
26521 + Opcode_rfi_encode_fns, 0, 0 },
26522 + { "waiti", 161 /* xt_iclass_wait */,
26524 + Opcode_waiti_encode_fns, 0, 0 },
26525 + { "rsr.interrupt", 162 /* xt_iclass_rsr.interrupt */,
26527 + Opcode_rsr_interrupt_encode_fns, 0, 0 },
26528 + { "wsr.intset", 163 /* xt_iclass_wsr.intset */,
26530 + Opcode_wsr_intset_encode_fns, 0, 0 },
26531 + { "wsr.intclear", 164 /* xt_iclass_wsr.intclear */,
26533 + Opcode_wsr_intclear_encode_fns, 0, 0 },
26534 + { "rsr.intenable", 165 /* xt_iclass_rsr.intenable */,
26536 + Opcode_rsr_intenable_encode_fns, 0, 0 },
26537 + { "wsr.intenable", 166 /* xt_iclass_wsr.intenable */,
26539 + Opcode_wsr_intenable_encode_fns, 0, 0 },
26540 + { "xsr.intenable", 167 /* xt_iclass_xsr.intenable */,
26542 + Opcode_xsr_intenable_encode_fns, 0, 0 },
26543 + { "break", 168 /* xt_iclass_break */,
26545 + Opcode_break_encode_fns, 0, 0 },
26546 + { "break.n", 169 /* xt_iclass_break.n */,
26548 + Opcode_break_n_encode_fns, 0, 0 },
26549 + { "rsr.dbreaka0", 170 /* xt_iclass_rsr.dbreaka0 */,
26551 + Opcode_rsr_dbreaka0_encode_fns, 0, 0 },
26552 + { "wsr.dbreaka0", 171 /* xt_iclass_wsr.dbreaka0 */,
26554 + Opcode_wsr_dbreaka0_encode_fns, 0, 0 },
26555 + { "xsr.dbreaka0", 172 /* xt_iclass_xsr.dbreaka0 */,
26557 + Opcode_xsr_dbreaka0_encode_fns, 0, 0 },
26558 + { "rsr.dbreakc0", 173 /* xt_iclass_rsr.dbreakc0 */,
26560 + Opcode_rsr_dbreakc0_encode_fns, 0, 0 },
26561 + { "wsr.dbreakc0", 174 /* xt_iclass_wsr.dbreakc0 */,
26563 + Opcode_wsr_dbreakc0_encode_fns, 0, 0 },
26564 + { "xsr.dbreakc0", 175 /* xt_iclass_xsr.dbreakc0 */,
26566 + Opcode_xsr_dbreakc0_encode_fns, 0, 0 },
26567 + { "rsr.dbreaka1", 176 /* xt_iclass_rsr.dbreaka1 */,
26569 + Opcode_rsr_dbreaka1_encode_fns, 0, 0 },
26570 + { "wsr.dbreaka1", 177 /* xt_iclass_wsr.dbreaka1 */,
26572 + Opcode_wsr_dbreaka1_encode_fns, 0, 0 },
26573 + { "xsr.dbreaka1", 178 /* xt_iclass_xsr.dbreaka1 */,
26575 + Opcode_xsr_dbreaka1_encode_fns, 0, 0 },
26576 + { "rsr.dbreakc1", 179 /* xt_iclass_rsr.dbreakc1 */,
26578 + Opcode_rsr_dbreakc1_encode_fns, 0, 0 },
26579 + { "wsr.dbreakc1", 180 /* xt_iclass_wsr.dbreakc1 */,
26581 + Opcode_wsr_dbreakc1_encode_fns, 0, 0 },
26582 + { "xsr.dbreakc1", 181 /* xt_iclass_xsr.dbreakc1 */,
26584 + Opcode_xsr_dbreakc1_encode_fns, 0, 0 },
26585 + { "rsr.ibreaka0", 182 /* xt_iclass_rsr.ibreaka0 */,
26587 + Opcode_rsr_ibreaka0_encode_fns, 0, 0 },
26588 + { "wsr.ibreaka0", 183 /* xt_iclass_wsr.ibreaka0 */,
26590 + Opcode_wsr_ibreaka0_encode_fns, 0, 0 },
26591 + { "xsr.ibreaka0", 184 /* xt_iclass_xsr.ibreaka0 */,
26593 + Opcode_xsr_ibreaka0_encode_fns, 0, 0 },
26594 + { "rsr.ibreaka1", 185 /* xt_iclass_rsr.ibreaka1 */,
26596 + Opcode_rsr_ibreaka1_encode_fns, 0, 0 },
26597 + { "wsr.ibreaka1", 186 /* xt_iclass_wsr.ibreaka1 */,
26599 + Opcode_wsr_ibreaka1_encode_fns, 0, 0 },
26600 + { "xsr.ibreaka1", 187 /* xt_iclass_xsr.ibreaka1 */,
26602 + Opcode_xsr_ibreaka1_encode_fns, 0, 0 },
26603 + { "rsr.ibreakenable", 188 /* xt_iclass_rsr.ibreakenable */,
26605 + Opcode_rsr_ibreakenable_encode_fns, 0, 0 },
26606 + { "wsr.ibreakenable", 189 /* xt_iclass_wsr.ibreakenable */,
26608 + Opcode_wsr_ibreakenable_encode_fns, 0, 0 },
26609 + { "xsr.ibreakenable", 190 /* xt_iclass_xsr.ibreakenable */,
26611 + Opcode_xsr_ibreakenable_encode_fns, 0, 0 },
26612 + { "rsr.debugcause", 191 /* xt_iclass_rsr.debugcause */,
26614 + Opcode_rsr_debugcause_encode_fns, 0, 0 },
26615 + { "wsr.debugcause", 192 /* xt_iclass_wsr.debugcause */,
26617 + Opcode_wsr_debugcause_encode_fns, 0, 0 },
26618 + { "xsr.debugcause", 193 /* xt_iclass_xsr.debugcause */,
26620 + Opcode_xsr_debugcause_encode_fns, 0, 0 },
26621 + { "rsr.icount", 194 /* xt_iclass_rsr.icount */,
26623 + Opcode_rsr_icount_encode_fns, 0, 0 },
26624 + { "wsr.icount", 195 /* xt_iclass_wsr.icount */,
26626 + Opcode_wsr_icount_encode_fns, 0, 0 },
26627 + { "xsr.icount", 196 /* xt_iclass_xsr.icount */,
26629 + Opcode_xsr_icount_encode_fns, 0, 0 },
26630 + { "rsr.icountlevel", 197 /* xt_iclass_rsr.icountlevel */,
26632 + Opcode_rsr_icountlevel_encode_fns, 0, 0 },
26633 + { "wsr.icountlevel", 198 /* xt_iclass_wsr.icountlevel */,
26635 + Opcode_wsr_icountlevel_encode_fns, 0, 0 },
26636 + { "xsr.icountlevel", 199 /* xt_iclass_xsr.icountlevel */,
26638 + Opcode_xsr_icountlevel_encode_fns, 0, 0 },
26639 + { "rsr.ddr", 200 /* xt_iclass_rsr.ddr */,
26641 + Opcode_rsr_ddr_encode_fns, 0, 0 },
26642 + { "wsr.ddr", 201 /* xt_iclass_wsr.ddr */,
26644 + Opcode_wsr_ddr_encode_fns, 0, 0 },
26645 + { "xsr.ddr", 202 /* xt_iclass_xsr.ddr */,
26647 + Opcode_xsr_ddr_encode_fns, 0, 0 },
26648 + { "rfdo", 203 /* xt_iclass_rfdo */,
26649 + XTENSA_OPCODE_IS_JUMP,
26650 + Opcode_rfdo_encode_fns, 0, 0 },
26651 + { "rfdd", 204 /* xt_iclass_rfdd */,
26652 + XTENSA_OPCODE_IS_JUMP,
26653 + Opcode_rfdd_encode_fns, 0, 0 },
26654 + { "wsr.mmid", 205 /* xt_iclass_wsr.mmid */,
26656 + Opcode_wsr_mmid_encode_fns, 0, 0 },
26657 + { "rsr.ccount", 206 /* xt_iclass_rsr.ccount */,
26659 + Opcode_rsr_ccount_encode_fns, 0, 0 },
26660 + { "wsr.ccount", 207 /* xt_iclass_wsr.ccount */,
26662 + Opcode_wsr_ccount_encode_fns, 0, 0 },
26663 + { "xsr.ccount", 208 /* xt_iclass_xsr.ccount */,
26665 + Opcode_xsr_ccount_encode_fns, 0, 0 },
26666 + { "rsr.ccompare0", 209 /* xt_iclass_rsr.ccompare0 */,
26668 + Opcode_rsr_ccompare0_encode_fns, 0, 0 },
26669 + { "wsr.ccompare0", 210 /* xt_iclass_wsr.ccompare0 */,
26671 + Opcode_wsr_ccompare0_encode_fns, 0, 0 },
26672 + { "xsr.ccompare0", 211 /* xt_iclass_xsr.ccompare0 */,
26674 + Opcode_xsr_ccompare0_encode_fns, 0, 0 },
26675 + { "idtlb", 212 /* xt_iclass_idtlb */,
26677 + Opcode_idtlb_encode_fns, 0, 0 },
26678 + { "pdtlb", 213 /* xt_iclass_rdtlb */,
26680 + Opcode_pdtlb_encode_fns, 0, 0 },
26681 + { "rdtlb0", 213 /* xt_iclass_rdtlb */,
26683 + Opcode_rdtlb0_encode_fns, 0, 0 },
26684 + { "rdtlb1", 213 /* xt_iclass_rdtlb */,
26686 + Opcode_rdtlb1_encode_fns, 0, 0 },
26687 + { "wdtlb", 214 /* xt_iclass_wdtlb */,
26689 + Opcode_wdtlb_encode_fns, 0, 0 },
26690 + { "iitlb", 215 /* xt_iclass_iitlb */,
26692 + Opcode_iitlb_encode_fns, 0, 0 },
26693 + { "pitlb", 216 /* xt_iclass_ritlb */,
26695 + Opcode_pitlb_encode_fns, 0, 0 },
26696 + { "ritlb0", 216 /* xt_iclass_ritlb */,
26698 + Opcode_ritlb0_encode_fns, 0, 0 },
26699 + { "ritlb1", 216 /* xt_iclass_ritlb */,
26701 + Opcode_ritlb1_encode_fns, 0, 0 },
26702 + { "witlb", 217 /* xt_iclass_witlb */,
26704 + Opcode_witlb_encode_fns, 0, 0 },
26705 + { "min", 218 /* xt_iclass_minmax */,
26707 + Opcode_min_encode_fns, 0, 0 },
26708 + { "max", 218 /* xt_iclass_minmax */,
26710 + Opcode_max_encode_fns, 0, 0 },
26711 + { "minu", 218 /* xt_iclass_minmax */,
26713 + Opcode_minu_encode_fns, 0, 0 },
26714 + { "maxu", 218 /* xt_iclass_minmax */,
26716 + Opcode_maxu_encode_fns, 0, 0 },
26717 + { "nsa", 219 /* xt_iclass_nsa */,
26719 + Opcode_nsa_encode_fns, 0, 0 },
26720 + { "nsau", 219 /* xt_iclass_nsa */,
26722 + Opcode_nsau_encode_fns, 0, 0 },
26723 + { "sext", 220 /* xt_iclass_sx */,
26725 + Opcode_sext_encode_fns, 0, 0 },
26726 + { "l32ai", 221 /* xt_iclass_l32ai */,
26728 + Opcode_l32ai_encode_fns, 0, 0 },
26729 + { "s32ri", 222 /* xt_iclass_s32ri */,
26731 + Opcode_s32ri_encode_fns, 0, 0 },
26732 + { "s32c1i", 223 /* xt_iclass_s32c1i */,
26734 + Opcode_s32c1i_encode_fns, 0, 0 },
26735 + { "rsr.scompare1", 224 /* xt_iclass_rsr.scompare1 */,
26737 + Opcode_rsr_scompare1_encode_fns, 0, 0 },
26738 + { "wsr.scompare1", 225 /* xt_iclass_wsr.scompare1 */,
26740 + Opcode_wsr_scompare1_encode_fns, 0, 0 },
26741 + { "xsr.scompare1", 226 /* xt_iclass_xsr.scompare1 */,
26743 + Opcode_xsr_scompare1_encode_fns, 0, 0 },
26744 + { "mull", 227 /* xt_mul32 */,
26746 + Opcode_mull_encode_fns, 0, 0 },
26747 + { "muluh", 227 /* xt_mul32 */,
26749 + Opcode_muluh_encode_fns, 0, 0 },
26750 + { "mulsh", 227 /* xt_mul32 */,
26752 + Opcode_mulsh_encode_fns, 0, 0 },
26753 + { "mul16u", 227 /* xt_mul32 */,
26755 + Opcode_mul16u_encode_fns, 0, 0 },
26756 + { "mul16s", 227 /* xt_mul32 */,
26758 + Opcode_mul16s_encode_fns, 0, 0 }
26761 -static xtensa_set_field_fn
26762 -Slot_xt_flix64_slot0_set_field_fns[] = {
26763 - Field_t_Slot_xt_flix64_slot0_set,
26767 - Field_imm8_Slot_xt_flix64_slot0_set,
26768 - Field_s_Slot_xt_flix64_slot0_set,
26769 - Field_imm12b_Slot_xt_flix64_slot0_set,
26770 - Field_imm16_Slot_xt_flix64_slot0_set,
26771 - Field_m_Slot_xt_flix64_slot0_set,
26772 - Field_n_Slot_xt_flix64_slot0_set,
26775 - Field_op1_Slot_xt_flix64_slot0_set,
26776 - Field_op2_Slot_xt_flix64_slot0_set,
26777 - Field_r_Slot_xt_flix64_slot0_set,
26779 - Field_sae4_Slot_xt_flix64_slot0_set,
26780 - Field_sae_Slot_xt_flix64_slot0_set,
26781 - Field_sal_Slot_xt_flix64_slot0_set,
26782 - Field_sargt_Slot_xt_flix64_slot0_set,
26784 - Field_sas_Slot_xt_flix64_slot0_set,
26787 - Field_thi3_Slot_xt_flix64_slot0_set,
26818 - Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_set,
26819 - Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_set,
26820 - Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_set,
26821 - Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_set,
26822 - Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_set,
26823 - Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_set,
26885 - Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_set,
26886 - Implicit_Field_set,
26887 - Implicit_Field_set,
26888 - Implicit_Field_set,
26889 - Implicit_Field_set,
26890 - Implicit_Field_set,
26891 - Implicit_Field_set,
26892 - Implicit_Field_set,
26893 - Implicit_Field_set,
26894 - Implicit_Field_set,
26895 - Implicit_Field_set,
26896 - Implicit_Field_set,
26897 - Implicit_Field_set
26900 +/* Slot-specific opcode decode functions. */
26902 -static xtensa_get_field_fn
26903 -Slot_xt_flix64_slot1_get_field_fns[] = {
26904 - Field_t_Slot_xt_flix64_slot1_get,
26908 - Field_imm8_Slot_xt_flix64_slot1_get,
26909 - Field_s_Slot_xt_flix64_slot1_get,
26910 - Field_imm12b_Slot_xt_flix64_slot1_get,
26914 - Field_offset_Slot_xt_flix64_slot1_get,
26917 - Field_op2_Slot_xt_flix64_slot1_get,
26918 - Field_r_Slot_xt_flix64_slot1_get,
26921 - Field_sae_Slot_xt_flix64_slot1_get,
26922 - Field_sal_Slot_xt_flix64_slot1_get,
26923 - Field_sargt_Slot_xt_flix64_slot1_get,
26965 - Field_op0_s4_Slot_xt_flix64_slot1_get,
26966 - Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_get,
26967 - Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26968 - Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26969 - Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26970 - Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26971 - Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26972 - Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26973 - Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26974 - Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26975 - Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26976 - Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26977 - Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26978 - Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26979 - Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26980 - Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26981 - Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26982 - Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26983 - Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26984 - Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26985 - Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26986 - Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_get,
27027 - Implicit_Field_ar0_get,
27028 - Implicit_Field_ar4_get,
27029 - Implicit_Field_ar8_get,
27030 - Implicit_Field_ar12_get,
27031 - Implicit_Field_mr0_get,
27032 - Implicit_Field_mr1_get,
27033 - Implicit_Field_mr2_get,
27034 - Implicit_Field_mr3_get,
27035 - Implicit_Field_bt16_get,
27036 - Implicit_Field_bs16_get,
27037 - Implicit_Field_br16_get,
27038 - Implicit_Field_brall_get
27041 +Slot_inst_decode (const xtensa_insnbuf insn)
27043 + switch (Field_op0_Slot_inst_get (insn))
27046 + switch (Field_op1_Slot_inst_get (insn))
27049 + switch (Field_op2_Slot_inst_get (insn))
27052 + switch (Field_r_Slot_inst_get (insn))
27055 + switch (Field_m_Slot_inst_get (insn))
27058 + if (Field_s_Slot_inst_get (insn) == 0 &&
27059 + Field_n_Slot_inst_get (insn) == 0)
27060 + return 79; /* ill */
27063 + switch (Field_n_Slot_inst_get (insn))
27066 + return 98; /* ret */
27068 + return 14; /* retw */
27070 + return 81; /* jx */
27074 + switch (Field_n_Slot_inst_get (insn))
27077 + return 77; /* callx0 */
27079 + return 10; /* callx4 */
27081 + return 9; /* callx8 */
27083 + return 8; /* callx12 */
27089 + return 12; /* movsp */
27091 + if (Field_s_Slot_inst_get (insn) == 0)
27093 + switch (Field_t_Slot_inst_get (insn))
27096 + return 116; /* isync */
27098 + return 117; /* rsync */
27100 + return 118; /* esync */
27102 + return 119; /* dsync */
27104 + return 0; /* excw */
27106 + return 114; /* memw */
27108 + return 115; /* extw */
27110 + return 97; /* nop */
27115 + switch (Field_t_Slot_inst_get (insn))
27118 + switch (Field_s_Slot_inst_get (insn))
27121 + return 1; /* rfe */
27123 + return 2; /* rfde */
27125 + return 16; /* rfwo */
27127 + return 17; /* rfwu */
27131 + return 202; /* rfi */
27135 + return 210; /* break */
27137 + switch (Field_s_Slot_inst_get (insn))
27140 + if (Field_t_Slot_inst_get (insn) == 0)
27141 + return 3; /* syscall */
27144 + if (Field_t_Slot_inst_get (insn) == 0)
27145 + return 4; /* simcall */
27150 + return 120; /* rsil */
27152 + if (Field_t_Slot_inst_get (insn) == 0)
27153 + return 203; /* waiti */
27158 + return 49; /* and */
27160 + return 50; /* or */
27162 + return 51; /* xor */
27164 + switch (Field_r_Slot_inst_get (insn))
27167 + if (Field_t_Slot_inst_get (insn) == 0)
27168 + return 102; /* ssr */
27171 + if (Field_t_Slot_inst_get (insn) == 0)
27172 + return 103; /* ssl */
27175 + if (Field_t_Slot_inst_get (insn) == 0)
27176 + return 104; /* ssa8l */
27179 + if (Field_t_Slot_inst_get (insn) == 0)
27180 + return 105; /* ssa8b */
27183 + if (Field_thi3_Slot_inst_get (insn) == 0)
27184 + return 106; /* ssai */
27187 + if (Field_s_Slot_inst_get (insn) == 0)
27188 + return 13; /* rotw */
27191 + return 268; /* nsa */
27193 + return 269; /* nsau */
27197 + switch (Field_r_Slot_inst_get (insn))
27200 + return 261; /* ritlb0 */
27202 + if (Field_t_Slot_inst_get (insn) == 0)
27203 + return 259; /* iitlb */
27206 + return 260; /* pitlb */
27208 + return 263; /* witlb */
27210 + return 262; /* ritlb1 */
27212 + return 256; /* rdtlb0 */
27214 + if (Field_t_Slot_inst_get (insn) == 0)
27215 + return 254; /* idtlb */
27218 + return 255; /* pdtlb */
27220 + return 258; /* wdtlb */
27222 + return 257; /* rdtlb1 */
27226 + switch (Field_s_Slot_inst_get (insn))
27229 + return 95; /* neg */
27231 + return 96; /* abs */
27235 + return 41; /* add */
27237 + return 43; /* addx2 */
27239 + return 44; /* addx4 */
27241 + return 45; /* addx8 */
27243 + return 42; /* sub */
27245 + return 46; /* subx2 */
27247 + return 47; /* subx4 */
27249 + return 48; /* subx8 */
27253 + switch (Field_op2_Slot_inst_get (insn))
27257 + return 111; /* slli */
27260 + return 112; /* srai */
27262 + return 113; /* srli */
27264 + switch (Field_sr_Slot_inst_get (insn))
27267 + return 129; /* xsr.lbeg */
27269 + return 123; /* xsr.lend */
27271 + return 126; /* xsr.lcount */
27273 + return 132; /* xsr.sar */
27275 + return 135; /* xsr.litbase */
27277 + return 276; /* xsr.scompare1 */
27279 + return 22; /* xsr.windowbase */
27281 + return 25; /* xsr.windowstart */
27283 + return 232; /* xsr.ibreakenable */
27285 + return 244; /* xsr.ddr */
27287 + return 226; /* xsr.ibreaka0 */
27289 + return 229; /* xsr.ibreaka1 */
27291 + return 214; /* xsr.dbreaka0 */
27293 + return 220; /* xsr.dbreaka1 */
27295 + return 217; /* xsr.dbreakc0 */
27297 + return 223; /* xsr.dbreakc1 */
27299 + return 143; /* xsr.epc1 */
27301 + return 149; /* xsr.epc2 */
27303 + return 155; /* xsr.epc3 */
27305 + return 161; /* xsr.epc4 */
27307 + return 167; /* xsr.epc5 */
27309 + return 188; /* xsr.depc */
27311 + return 173; /* xsr.eps2 */
27313 + return 176; /* xsr.eps3 */
27315 + return 179; /* xsr.eps4 */
27317 + return 182; /* xsr.eps5 */
27319 + return 146; /* xsr.excsave1 */
27321 + return 152; /* xsr.excsave2 */
27323 + return 158; /* xsr.excsave3 */
27325 + return 164; /* xsr.excsave4 */
27327 + return 170; /* xsr.excsave5 */
27329 + return 209; /* xsr.intenable */
27331 + return 140; /* xsr.ps */
27333 + return 201; /* xsr.vecbase */
27335 + return 191; /* xsr.exccause */
27337 + return 235; /* xsr.debugcause */
27339 + return 250; /* xsr.ccount */
27341 + return 238; /* xsr.icount */
27343 + return 241; /* xsr.icountlevel */
27345 + return 185; /* xsr.excvaddr */
27347 + return 253; /* xsr.ccompare0 */
27349 + return 194; /* xsr.misc0 */
27351 + return 197; /* xsr.misc1 */
27355 + return 108; /* src */
27357 + if (Field_s_Slot_inst_get (insn) == 0)
27358 + return 109; /* srl */
27361 + if (Field_t_Slot_inst_get (insn) == 0)
27362 + return 107; /* sll */
27365 + if (Field_s_Slot_inst_get (insn) == 0)
27366 + return 110; /* sra */
27369 + return 280; /* mul16u */
27371 + return 281; /* mul16s */
27373 + switch (Field_r_Slot_inst_get (insn))
27376 + if (Field_t_Slot_inst_get (insn) == 0)
27377 + return 245; /* rfdo */
27378 + if (Field_t_Slot_inst_get (insn) == 1)
27379 + return 246; /* rfdd */
27386 + switch (Field_op2_Slot_inst_get (insn))
27389 + return 277; /* mull */
27391 + return 278; /* muluh */
27393 + return 279; /* mulsh */
27397 + switch (Field_op2_Slot_inst_get (insn))
27400 + switch (Field_sr_Slot_inst_get (insn))
27403 + return 127; /* rsr.lbeg */
27405 + return 121; /* rsr.lend */
27407 + return 124; /* rsr.lcount */
27409 + return 130; /* rsr.sar */
27411 + return 133; /* rsr.litbase */
27413 + return 274; /* rsr.scompare1 */
27415 + return 20; /* rsr.windowbase */
27417 + return 23; /* rsr.windowstart */
27419 + return 230; /* rsr.ibreakenable */
27421 + return 242; /* rsr.ddr */
27423 + return 224; /* rsr.ibreaka0 */
27425 + return 227; /* rsr.ibreaka1 */
27427 + return 212; /* rsr.dbreaka0 */
27429 + return 218; /* rsr.dbreaka1 */
27431 + return 215; /* rsr.dbreakc0 */
27433 + return 221; /* rsr.dbreakc1 */
27435 + return 136; /* rsr.176 */
27437 + return 141; /* rsr.epc1 */
27439 + return 147; /* rsr.epc2 */
27441 + return 153; /* rsr.epc3 */
27443 + return 159; /* rsr.epc4 */
27445 + return 165; /* rsr.epc5 */
27447 + return 186; /* rsr.depc */
27449 + return 171; /* rsr.eps2 */
27451 + return 174; /* rsr.eps3 */
27453 + return 177; /* rsr.eps4 */
27455 + return 180; /* rsr.eps5 */
27457 + return 137; /* rsr.208 */
27459 + return 144; /* rsr.excsave1 */
27461 + return 150; /* rsr.excsave2 */
27463 + return 156; /* rsr.excsave3 */
27465 + return 162; /* rsr.excsave4 */
27467 + return 168; /* rsr.excsave5 */
27469 + return 204; /* rsr.interrupt */
27471 + return 207; /* rsr.intenable */
27473 + return 138; /* rsr.ps */
27475 + return 199; /* rsr.vecbase */
27477 + return 189; /* rsr.exccause */
27479 + return 233; /* rsr.debugcause */
27481 + return 248; /* rsr.ccount */
27483 + return 198; /* rsr.prid */
27485 + return 236; /* rsr.icount */
27487 + return 239; /* rsr.icountlevel */
27489 + return 183; /* rsr.excvaddr */
27491 + return 251; /* rsr.ccompare0 */
27493 + return 192; /* rsr.misc0 */
27495 + return 195; /* rsr.misc1 */
27499 + switch (Field_sr_Slot_inst_get (insn))
27502 + return 128; /* wsr.lbeg */
27504 + return 122; /* wsr.lend */
27506 + return 125; /* wsr.lcount */
27508 + return 131; /* wsr.sar */
27510 + return 134; /* wsr.litbase */
27512 + return 275; /* wsr.scompare1 */
27514 + return 21; /* wsr.windowbase */
27516 + return 24; /* wsr.windowstart */
27518 + return 247; /* wsr.mmid */
27520 + return 231; /* wsr.ibreakenable */
27522 + return 243; /* wsr.ddr */
27524 + return 225; /* wsr.ibreaka0 */
27526 + return 228; /* wsr.ibreaka1 */
27528 + return 213; /* wsr.dbreaka0 */
27530 + return 219; /* wsr.dbreaka1 */
27532 + return 216; /* wsr.dbreakc0 */
27534 + return 222; /* wsr.dbreakc1 */
27536 + return 142; /* wsr.epc1 */
27538 + return 148; /* wsr.epc2 */
27540 + return 154; /* wsr.epc3 */
27542 + return 160; /* wsr.epc4 */
27544 + return 166; /* wsr.epc5 */
27546 + return 187; /* wsr.depc */
27548 + return 172; /* wsr.eps2 */
27550 + return 175; /* wsr.eps3 */
27552 + return 178; /* wsr.eps4 */
27554 + return 181; /* wsr.eps5 */
27556 + return 145; /* wsr.excsave1 */
27558 + return 151; /* wsr.excsave2 */
27560 + return 157; /* wsr.excsave3 */
27562 + return 163; /* wsr.excsave4 */
27564 + return 169; /* wsr.excsave5 */
27566 + return 205; /* wsr.intset */
27568 + return 206; /* wsr.intclear */
27570 + return 208; /* wsr.intenable */
27572 + return 139; /* wsr.ps */
27574 + return 200; /* wsr.vecbase */
27576 + return 190; /* wsr.exccause */
27578 + return 234; /* wsr.debugcause */
27580 + return 249; /* wsr.ccount */
27582 + return 237; /* wsr.icount */
27584 + return 240; /* wsr.icountlevel */
27586 + return 184; /* wsr.excvaddr */
27588 + return 252; /* wsr.ccompare0 */
27590 + return 193; /* wsr.misc0 */
27592 + return 196; /* wsr.misc1 */
27596 + return 270; /* sext */
27598 + return 264; /* min */
27600 + return 265; /* max */
27602 + return 266; /* minu */
27604 + return 267; /* maxu */
27606 + return 91; /* moveqz */
27608 + return 92; /* movnez */
27610 + return 93; /* movltz */
27612 + return 94; /* movgez */
27614 + if (Field_st_Slot_inst_get (insn) == 231)
27615 + return 37; /* rur.threadptr */
27618 + if (Field_sr_Slot_inst_get (insn) == 231)
27619 + return 38; /* wur.threadptr */
27625 + return 78; /* extui */
27627 + switch (Field_op2_Slot_inst_get (insn))
27630 + return 18; /* l32e */
27632 + return 19; /* s32e */
27638 + return 85; /* l32r */
27640 + switch (Field_r_Slot_inst_get (insn))
27643 + return 86; /* l8ui */
27645 + return 82; /* l16ui */
27647 + return 84; /* l32i */
27649 + return 101; /* s8i */
27651 + return 99; /* s16i */
27653 + return 100; /* s32i */
27655 + return 83; /* l16si */
27657 + return 90; /* movi */
27659 + return 271; /* l32ai */
27661 + return 39; /* addi */
27663 + return 40; /* addmi */
27665 + return 273; /* s32c1i */
27667 + return 272; /* s32ri */
27671 + switch (Field_n_Slot_inst_get (insn))
27674 + return 76; /* call0 */
27676 + return 7; /* call4 */
27678 + return 6; /* call8 */
27680 + return 5; /* call12 */
27684 + switch (Field_n_Slot_inst_get (insn))
27687 + return 80; /* j */
27689 + switch (Field_m_Slot_inst_get (insn))
27692 + return 72; /* beqz */
27694 + return 73; /* bnez */
27696 + return 75; /* bltz */
27698 + return 74; /* bgez */
27702 + switch (Field_m_Slot_inst_get (insn))
27705 + return 52; /* beqi */
27707 + return 53; /* bnei */
27709 + return 55; /* blti */
27711 + return 54; /* bgei */
27715 + switch (Field_m_Slot_inst_get (insn))
27718 + return 11; /* entry */
27720 + switch (Field_r_Slot_inst_get (insn))
27723 + return 87; /* loop */
27725 + return 88; /* loopnez */
27727 + return 89; /* loopgtz */
27731 + return 59; /* bltui */
27733 + return 58; /* bgeui */
27739 + switch (Field_r_Slot_inst_get (insn))
27742 + return 67; /* bnone */
27744 + return 60; /* beq */
27746 + return 63; /* blt */
27748 + return 65; /* bltu */
27750 + return 68; /* ball */
27752 + return 70; /* bbc */
27755 + return 56; /* bbci */
27757 + return 66; /* bany */
27759 + return 61; /* bne */
27761 + return 62; /* bge */
27763 + return 64; /* bgeu */
27765 + return 69; /* bnall */
27767 + return 71; /* bbs */
27770 + return 57; /* bbsi */
27777 -static xtensa_set_field_fn
27778 -Slot_xt_flix64_slot1_set_field_fns[] = {
27779 - Field_t_Slot_xt_flix64_slot1_set,
27783 - Field_imm8_Slot_xt_flix64_slot1_set,
27784 - Field_s_Slot_xt_flix64_slot1_set,
27785 - Field_imm12b_Slot_xt_flix64_slot1_set,
27789 - Field_offset_Slot_xt_flix64_slot1_set,
27792 - Field_op2_Slot_xt_flix64_slot1_set,
27793 - Field_r_Slot_xt_flix64_slot1_set,
27796 - Field_sae_Slot_xt_flix64_slot1_set,
27797 - Field_sal_Slot_xt_flix64_slot1_set,
27798 - Field_sargt_Slot_xt_flix64_slot1_set,
27840 - Field_op0_s4_Slot_xt_flix64_slot1_set,
27841 - Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_set,
27842 - Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27843 - Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27844 - Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27845 - Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27846 - Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27847 - Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27848 - Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27849 - Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27850 - Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27851 - Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27852 - Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27853 - Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27854 - Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27855 - Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27856 - Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27857 - Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27858 - Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27859 - Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27860 - Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27861 - Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27902 - Implicit_Field_set,
27903 - Implicit_Field_set,
27904 - Implicit_Field_set,
27905 - Implicit_Field_set,
27906 - Implicit_Field_set,
27907 - Implicit_Field_set,
27908 - Implicit_Field_set,
27909 - Implicit_Field_set,
27910 - Implicit_Field_set,
27911 - Implicit_Field_set,
27912 - Implicit_Field_set,
27913 - Implicit_Field_set
27916 +Slot_inst16b_decode (const xtensa_insnbuf insn)
27918 + switch (Field_op0_Slot_inst16b_get (insn))
27921 + switch (Field_i_Slot_inst16b_get (insn))
27924 + return 33; /* movi.n */
27926 + switch (Field_z_Slot_inst16b_get (insn))
27929 + return 28; /* beqz.n */
27931 + return 29; /* bnez.n */
27937 + switch (Field_r_Slot_inst16b_get (insn))
27940 + return 32; /* mov.n */
27942 + switch (Field_t_Slot_inst16b_get (insn))
27945 + return 35; /* ret.n */
27947 + return 15; /* retw.n */
27949 + return 211; /* break.n */
27951 + if (Field_s_Slot_inst16b_get (insn) == 0)
27952 + return 34; /* nop.n */
27955 + if (Field_s_Slot_inst16b_get (insn) == 0)
27956 + return 30; /* ill.n */
27967 +Slot_inst16a_decode (const xtensa_insnbuf insn)
27969 + switch (Field_op0_Slot_inst16a_get (insn))
27972 + return 31; /* l32i.n */
27974 + return 36; /* s32i.n */
27976 + return 26; /* add.n */
27978 + return 27; /* addi.n */
27983 -static xtensa_get_field_fn
27984 -Slot_xt_flix64_slot2_get_field_fns[] = {
27985 - Field_t_Slot_xt_flix64_slot2_get,
27990 - Field_s_Slot_xt_flix64_slot2_get,
27999 - Field_r_Slot_xt_flix64_slot2_get,
28004 - Field_sargt_Slot_xt_flix64_slot2_get,
28019 - Field_imm7_Slot_xt_flix64_slot2_get,
28068 - Field_op0_s5_Slot_xt_flix64_slot2_get,
28069 - Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_get,
28070 - Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_get,
28071 - Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_get,
28072 - Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_get,
28073 - Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_get,
28074 - Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_get,
28075 - Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_get,
28076 - Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_get,
28077 - Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_get,
28078 - Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_get,
28079 - Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_get,
28080 - Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_get,
28081 - Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_get,
28108 - Implicit_Field_ar0_get,
28109 - Implicit_Field_ar4_get,
28110 - Implicit_Field_ar8_get,
28111 - Implicit_Field_ar12_get,
28112 - Implicit_Field_mr0_get,
28113 - Implicit_Field_mr1_get,
28114 - Implicit_Field_mr2_get,
28115 - Implicit_Field_mr3_get,
28116 - Implicit_Field_bt16_get,
28117 - Implicit_Field_bs16_get,
28118 - Implicit_Field_br16_get,
28119 - Implicit_Field_brall_get
28122 +/* Instruction slots. */
28124 -static xtensa_set_field_fn
28125 -Slot_xt_flix64_slot2_set_field_fns[] = {
28126 - Field_t_Slot_xt_flix64_slot2_set,
28131 - Field_s_Slot_xt_flix64_slot2_set,
28140 - Field_r_Slot_xt_flix64_slot2_set,
28145 - Field_sargt_Slot_xt_flix64_slot2_set,
28160 - Field_imm7_Slot_xt_flix64_slot2_set,
28209 - Field_op0_s5_Slot_xt_flix64_slot2_set,
28210 - Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_set,
28211 - Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_set,
28212 - Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_set,
28213 - Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_set,
28214 - Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_set,
28215 - Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_set,
28216 - Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_set,
28217 - Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_set,
28218 - Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_set,
28219 - Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_set,
28220 - Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_set,
28221 - Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_set,
28222 - Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_set,
28234 +Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn,
28235 + xtensa_insnbuf slotbuf)
28237 + slotbuf[0] = (insn[0] & 0xffffff);
28241 +Slot_x24_Format_inst_0_set (xtensa_insnbuf insn,
28242 + const xtensa_insnbuf slotbuf)
28244 + insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff);
28248 +Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn,
28249 + xtensa_insnbuf slotbuf)
28251 + slotbuf[0] = ((insn[0] & 0xffff00) >> 8);
28255 +Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn,
28256 + const xtensa_insnbuf slotbuf)
28258 + insn[0] = (insn[0] & ~0xffff00) | ((slotbuf[0] & 0xffff) << 8);
28262 +Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn,
28263 + xtensa_insnbuf slotbuf)
28265 + slotbuf[0] = ((insn[0] & 0xffff00) >> 8);
28269 +Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn,
28270 + const xtensa_insnbuf slotbuf)
28272 + insn[0] = (insn[0] & ~0xffff00) | ((slotbuf[0] & 0xffff) << 8);
28275 +static xtensa_get_field_fn
28276 +Slot_inst_get_field_fns[] = {
28277 + Field_t_Slot_inst_get,
28278 + Field_bbi4_Slot_inst_get,
28279 + Field_bbi_Slot_inst_get,
28280 + Field_imm12_Slot_inst_get,
28281 + Field_imm8_Slot_inst_get,
28282 + Field_s_Slot_inst_get,
28283 + Field_imm12b_Slot_inst_get,
28284 + Field_imm16_Slot_inst_get,
28285 + Field_m_Slot_inst_get,
28286 + Field_n_Slot_inst_get,
28287 + Field_offset_Slot_inst_get,
28288 + Field_op0_Slot_inst_get,
28289 + Field_op1_Slot_inst_get,
28290 + Field_op2_Slot_inst_get,
28291 + Field_r_Slot_inst_get,
28292 + Field_sa4_Slot_inst_get,
28293 + Field_sae4_Slot_inst_get,
28294 + Field_sae_Slot_inst_get,
28295 + Field_sal_Slot_inst_get,
28296 + Field_sargt_Slot_inst_get,
28297 + Field_sas4_Slot_inst_get,
28298 + Field_sas_Slot_inst_get,
28299 + Field_sr_Slot_inst_get,
28300 + Field_st_Slot_inst_get,
28301 + Field_thi3_Slot_inst_get,
28302 + Field_imm4_Slot_inst_get,
28303 + Field_mn_Slot_inst_get,
28307 @@ -20837,6 +9122,43 @@ Slot_xt_flix64_slot2_set_field_fns[] = {
28311 + Field_xt_wbr15_imm_Slot_inst_get,
28312 + Field_xt_wbr18_imm_Slot_inst_get,
28313 + Implicit_Field_ar0_get,
28314 + Implicit_Field_ar4_get,
28315 + Implicit_Field_ar8_get,
28316 + Implicit_Field_ar12_get
28319 +static xtensa_set_field_fn
28320 +Slot_inst_set_field_fns[] = {
28321 + Field_t_Slot_inst_set,
28322 + Field_bbi4_Slot_inst_set,
28323 + Field_bbi_Slot_inst_set,
28324 + Field_imm12_Slot_inst_set,
28325 + Field_imm8_Slot_inst_set,
28326 + Field_s_Slot_inst_set,
28327 + Field_imm12b_Slot_inst_set,
28328 + Field_imm16_Slot_inst_set,
28329 + Field_m_Slot_inst_set,
28330 + Field_n_Slot_inst_set,
28331 + Field_offset_Slot_inst_set,
28332 + Field_op0_Slot_inst_set,
28333 + Field_op1_Slot_inst_set,
28334 + Field_op2_Slot_inst_set,
28335 + Field_r_Slot_inst_set,
28336 + Field_sa4_Slot_inst_set,
28337 + Field_sae4_Slot_inst_set,
28338 + Field_sae_Slot_inst_set,
28339 + Field_sal_Slot_inst_set,
28340 + Field_sargt_Slot_inst_set,
28341 + Field_sas4_Slot_inst_set,
28342 + Field_sas_Slot_inst_set,
28343 + Field_sr_Slot_inst_set,
28344 + Field_st_Slot_inst_set,
28345 + Field_thi3_Slot_inst_set,
28346 + Field_imm4_Slot_inst_set,
28347 + Field_mn_Slot_inst_set,
28351 @@ -20845,14 +9167,8 @@ Slot_xt_flix64_slot2_set_field_fns[] = {
28355 - Implicit_Field_set,
28356 - Implicit_Field_set,
28357 - Implicit_Field_set,
28358 - Implicit_Field_set,
28359 - Implicit_Field_set,
28360 - Implicit_Field_set,
28361 - Implicit_Field_set,
28362 - Implicit_Field_set,
28363 + Field_xt_wbr15_imm_Slot_inst_set,
28364 + Field_xt_wbr18_imm_Slot_inst_set,
28365 Implicit_Field_set,
28366 Implicit_Field_set,
28367 Implicit_Field_set,
28368 @@ -20860,94 +9176,22 @@ Slot_xt_flix64_slot2_set_field_fns[] = {
28371 static xtensa_get_field_fn
28372 -Slot_xt_flix64_slot3_get_field_fns[] = {
28373 - Field_t_Slot_xt_flix64_slot3_get,
28375 - Field_bbi_Slot_xt_flix64_slot3_get,
28378 - Field_s_Slot_xt_flix64_slot3_get,
28387 - Field_r_Slot_xt_flix64_slot3_get,
28427 - Field_xt_wbr18_imm_Slot_xt_flix64_slot3_get,
28449 +Slot_inst16a_get_field_fns[] = {
28450 + Field_t_Slot_inst16a_get,
28455 + Field_s_Slot_inst16a_get,
28461 + Field_op0_Slot_inst16a_get,
28464 + Field_r_Slot_inst16a_get,
28468 @@ -20955,93 +9199,44 @@ Slot_xt_flix64_slot3_get_field_fns[] = {
28472 + Field_sr_Slot_inst16a_get,
28473 + Field_st_Slot_inst16a_get,
28475 + Field_imm4_Slot_inst16a_get,
28477 + Field_i_Slot_inst16a_get,
28478 + Field_imm6lo_Slot_inst16a_get,
28479 + Field_imm6hi_Slot_inst16a_get,
28480 + Field_imm7lo_Slot_inst16a_get,
28481 + Field_imm7hi_Slot_inst16a_get,
28482 + Field_z_Slot_inst16a_get,
28483 + Field_imm6_Slot_inst16a_get,
28484 + Field_imm7_Slot_inst16a_get,
28486 - Field_op0_s6_Slot_xt_flix64_slot3_get,
28487 - Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28488 - Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_get,
28489 - Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28490 - Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28491 - Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28492 - Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28493 - Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28494 - Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28495 - Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28496 - Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28497 - Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28498 - Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28499 - Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28500 - Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28501 - Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28502 - Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28503 - Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28504 - Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28505 - Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28506 - Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28507 - Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28508 - Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28509 - Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28510 - Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28512 Implicit_Field_ar0_get,
28513 Implicit_Field_ar4_get,
28514 Implicit_Field_ar8_get,
28515 - Implicit_Field_ar12_get,
28516 - Implicit_Field_mr0_get,
28517 - Implicit_Field_mr1_get,
28518 - Implicit_Field_mr2_get,
28519 - Implicit_Field_mr3_get,
28520 - Implicit_Field_bt16_get,
28521 - Implicit_Field_bs16_get,
28522 - Implicit_Field_br16_get,
28523 - Implicit_Field_brall_get
28524 + Implicit_Field_ar12_get
28527 static xtensa_set_field_fn
28528 -Slot_xt_flix64_slot3_set_field_fns[] = {
28529 - Field_t_Slot_xt_flix64_slot3_set,
28531 - Field_bbi_Slot_xt_flix64_slot3_set,
28534 - Field_s_Slot_xt_flix64_slot3_set,
28543 - Field_r_Slot_xt_flix64_slot3_set,
28560 +Slot_inst16a_set_field_fns[] = {
28561 + Field_t_Slot_inst16a_set,
28566 + Field_s_Slot_inst16a_set,
28572 + Field_op0_Slot_inst16a_set,
28575 + Field_r_Slot_inst16a_set,
28579 @@ -21049,22 +9244,44 @@ Slot_xt_flix64_slot3_set_field_fns[] = {
28583 + Field_sr_Slot_inst16a_set,
28584 + Field_st_Slot_inst16a_set,
28586 + Field_imm4_Slot_inst16a_set,
28588 + Field_i_Slot_inst16a_set,
28589 + Field_imm6lo_Slot_inst16a_set,
28590 + Field_imm6hi_Slot_inst16a_set,
28591 + Field_imm7lo_Slot_inst16a_set,
28592 + Field_imm7hi_Slot_inst16a_set,
28593 + Field_z_Slot_inst16a_set,
28594 + Field_imm6_Slot_inst16a_set,
28595 + Field_imm7_Slot_inst16a_set,
28598 + Implicit_Field_set,
28599 + Implicit_Field_set,
28600 + Implicit_Field_set,
28601 + Implicit_Field_set
28604 +static xtensa_get_field_fn
28605 +Slot_inst16b_get_field_fns[] = {
28606 + Field_t_Slot_inst16b_get,
28608 - Field_xt_wbr18_imm_Slot_xt_flix64_slot3_set,
28612 + Field_s_Slot_inst16b_get,
28618 + Field_op0_Slot_inst16b_get,
28621 + Field_r_Slot_inst16b_get,
28625 @@ -21072,21 +9289,44 @@ Slot_xt_flix64_slot3_set_field_fns[] = {
28629 + Field_sr_Slot_inst16b_get,
28630 + Field_st_Slot_inst16b_get,
28632 + Field_imm4_Slot_inst16b_get,
28634 + Field_i_Slot_inst16b_get,
28635 + Field_imm6lo_Slot_inst16b_get,
28636 + Field_imm6hi_Slot_inst16b_get,
28637 + Field_imm7lo_Slot_inst16b_get,
28638 + Field_imm7hi_Slot_inst16b_get,
28639 + Field_z_Slot_inst16b_get,
28640 + Field_imm6_Slot_inst16b_get,
28641 + Field_imm7_Slot_inst16b_get,
28644 + Implicit_Field_ar0_get,
28645 + Implicit_Field_ar4_get,
28646 + Implicit_Field_ar8_get,
28647 + Implicit_Field_ar12_get
28650 +static xtensa_set_field_fn
28651 +Slot_inst16b_set_field_fns[] = {
28652 + Field_t_Slot_inst16b_set,
28657 + Field_s_Slot_inst16b_set,
28663 + Field_op0_Slot_inst16b_set,
28666 + Field_r_Slot_inst16b_set,
28670 @@ -21094,46 +9334,24 @@ Slot_xt_flix64_slot3_set_field_fns[] = {
28674 + Field_sr_Slot_inst16b_set,
28675 + Field_st_Slot_inst16b_set,
28677 + Field_imm4_Slot_inst16b_set,
28679 + Field_i_Slot_inst16b_set,
28680 + Field_imm6lo_Slot_inst16b_set,
28681 + Field_imm6hi_Slot_inst16b_set,
28682 + Field_imm7lo_Slot_inst16b_set,
28683 + Field_imm7hi_Slot_inst16b_set,
28684 + Field_z_Slot_inst16b_set,
28685 + Field_imm6_Slot_inst16b_set,
28686 + Field_imm7_Slot_inst16b_set,
28688 - Field_op0_s6_Slot_xt_flix64_slot3_set,
28689 - Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28690 - Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_set,
28691 - Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28692 - Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28693 - Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28694 - Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28695 - Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28696 - Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28697 - Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28698 - Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28699 - Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28700 - Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28701 - Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28702 - Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28703 - Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28704 - Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28705 - Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28706 - Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28707 - Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28708 - Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28709 - Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28710 - Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28711 - Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28712 - Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28714 Implicit_Field_set,
28715 Implicit_Field_set,
28716 Implicit_Field_set,
28717 - Implicit_Field_set,
28718 - Implicit_Field_set,
28719 - Implicit_Field_set,
28720 - Implicit_Field_set,
28721 - Implicit_Field_set,
28722 - Implicit_Field_set,
28723 - Implicit_Field_set,
28724 - Implicit_Field_set,
28728 @@ -21149,27 +9367,7 @@ static xtensa_slot_internal slots[] = {
28729 { "Inst16b", "x16b", 0,
28730 Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set,
28731 Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns,
28732 - Slot_inst16b_decode, "nop.n" },
28733 - { "xt_flix64_slot0", "xt_format1", 0,
28734 - Slot_xt_format1_Format_xt_flix64_slot0_4_get, Slot_xt_format1_Format_xt_flix64_slot0_4_set,
28735 - Slot_xt_flix64_slot0_get_field_fns, Slot_xt_flix64_slot0_set_field_fns,
28736 - Slot_xt_flix64_slot0_decode, "nop" },
28737 - { "xt_flix64_slot0", "xt_format2", 0,
28738 - Slot_xt_format2_Format_xt_flix64_slot0_4_get, Slot_xt_format2_Format_xt_flix64_slot0_4_set,
28739 - Slot_xt_flix64_slot0_get_field_fns, Slot_xt_flix64_slot0_set_field_fns,
28740 - Slot_xt_flix64_slot0_decode, "nop" },
28741 - { "xt_flix64_slot1", "xt_format1", 1,
28742 - Slot_xt_format1_Format_xt_flix64_slot1_28_get, Slot_xt_format1_Format_xt_flix64_slot1_28_set,
28743 - Slot_xt_flix64_slot1_get_field_fns, Slot_xt_flix64_slot1_set_field_fns,
28744 - Slot_xt_flix64_slot1_decode, "nop" },
28745 - { "xt_flix64_slot2", "xt_format1", 2,
28746 - Slot_xt_format1_Format_xt_flix64_slot2_48_get, Slot_xt_format1_Format_xt_flix64_slot2_48_set,
28747 - Slot_xt_flix64_slot2_get_field_fns, Slot_xt_flix64_slot2_set_field_fns,
28748 - Slot_xt_flix64_slot2_decode, "nop" },
28749 - { "xt_flix64_slot3", "xt_format2", 1,
28750 - Slot_xt_format2_Format_xt_flix64_slot3_28_get, Slot_xt_format2_Format_xt_flix64_slot3_28_set,
28751 - Slot_xt_flix64_slot3_get_field_fns, Slot_xt_flix64_slot3_set_field_fns,
28752 - Slot_xt_flix64_slot3_decode, "nop" }
28753 + Slot_inst16b_decode, "nop.n" }
28757 @@ -21179,35 +9377,18 @@ static void
28758 Format_x24_encode (xtensa_insnbuf insn)
28765 Format_x16a_encode (xtensa_insnbuf insn)
28769 + insn[0] = 0x800000;
28773 Format_x16b_encode (xtensa_insnbuf insn)
28780 -Format_xt_format1_encode (xtensa_insnbuf insn)
28787 -Format_xt_format2_encode (xtensa_insnbuf insn)
28791 + insn[0] = 0xc00000;
28794 static int Format_x24_slots[] = { 0 };
28795 @@ -21216,32 +9397,22 @@ static int Format_x16a_slots[] = { 1 };
28797 static int Format_x16b_slots[] = { 2 };
28799 -static int Format_xt_format1_slots[] = { 3, 5, 6 };
28801 -static int Format_xt_format2_slots[] = { 4, 7 };
28803 static xtensa_format_internal formats[] = {
28804 { "x24", 3, Format_x24_encode, 1, Format_x24_slots },
28805 { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots },
28806 - { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots },
28807 - { "xt_format1", 8, Format_xt_format1_encode, 3, Format_xt_format1_slots },
28808 - { "xt_format2", 8, Format_xt_format2_encode, 2, Format_xt_format2_slots }
28809 + { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots }
28814 format_decoder (const xtensa_insnbuf insn)
28816 - if ((insn[0] & 0x8) == 0 && (insn[1] & 0) == 0)
28817 + if ((insn[0] & 0x800000) == 0)
28818 return 0; /* x24 */
28819 - if ((insn[0] & 0xc) == 0x8 && (insn[1] & 0) == 0)
28820 + if ((insn[0] & 0xc00000) == 0x800000)
28821 return 1; /* x16a */
28822 - if ((insn[0] & 0xe) == 0xc && (insn[1] & 0) == 0)
28823 + if ((insn[0] & 0xe00000) == 0xc00000)
28824 return 2; /* x16b */
28825 - if ((insn[0] & 0xf) == 0xe && (insn[1] & 0) == 0)
28826 - return 3; /* xt_format1 */
28827 - if ((insn[0] & 0xf) == 0xf && (insn[1] & 0x80000000) == 0)
28828 - return 4; /* xt_format2 */
28832 @@ -21260,14 +9431,14 @@ static int length_table[16] = {
28843 length_decoder (const unsigned char *insn)
28845 - int op0 = insn[0] & 0xf;
28846 + int op0 = (insn[0] >> 4) & 0xf;
28847 return length_table[op0];
28850 @@ -21275,15 +9446,15 @@ length_decoder (const unsigned char *insn)
28851 /* Top-level ISA structure. */
28853 xtensa_isa_internal xtensa_modules = {
28854 - 0 /* little-endian */,
28855 - 8 /* insn_size */, 0,
28856 - 5, formats, format_decoder, length_decoder,
28858 - 135 /* num_fields */,
28863 + 1 /* big-endian */,
28864 + 3 /* insn_size */, 0,
28865 + 3, formats, format_decoder, length_decoder,
28867 + 41 /* num_fields */,
28872 NUM_STATES, states, 0,
28873 NUM_SYSREGS, sysregs, 0,
28874 { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 },
28875 diff --git a/include/xtensa-config.h b/include/xtensa-config.h
28876 index 30f4f41..fe9b051 100644
28877 --- a/include/xtensa-config.h
28878 +++ b/include/xtensa-config.h
28880 #define XCHAL_HAVE_L32R 1
28882 #undef XSHAL_USE_ABSOLUTE_LITERALS
28883 -#define XSHAL_USE_ABSOLUTE_LITERALS 0
28885 -#undef XSHAL_HAVE_TEXT_SECTION_LITERALS
28886 -#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */
28887 +#define XSHAL_USE_ABSOLUTE_LITERALS 1
28889 #undef XCHAL_HAVE_MAC16
28890 #define XCHAL_HAVE_MAC16 0
28891 @@ -59,10 +56,10 @@
28892 #define XCHAL_HAVE_MUL32 1
28894 #undef XCHAL_HAVE_MUL32_HIGH
28895 -#define XCHAL_HAVE_MUL32_HIGH 0
28896 +#define XCHAL_HAVE_MUL32_HIGH 1
28898 #undef XCHAL_HAVE_DIV32
28899 -#define XCHAL_HAVE_DIV32 1
28900 +#define XCHAL_HAVE_DIV32 0
28902 #undef XCHAL_HAVE_NSA
28903 #define XCHAL_HAVE_NSA 1
28904 @@ -103,8 +100,6 @@
28905 #undef XCHAL_HAVE_FP_RSQRT
28906 #define XCHAL_HAVE_FP_RSQRT 0
28908 -#undef XCHAL_HAVE_DFP_accel
28909 -#define XCHAL_HAVE_DFP_accel 0
28910 #undef XCHAL_HAVE_WINDOWED
28911 #define XCHAL_HAVE_WINDOWED 1
28913 @@ -119,32 +114,32 @@
28916 #undef XCHAL_ICACHE_SIZE
28917 -#define XCHAL_ICACHE_SIZE 16384
28918 +#define XCHAL_ICACHE_SIZE 0
28920 #undef XCHAL_DCACHE_SIZE
28921 -#define XCHAL_DCACHE_SIZE 16384
28922 +#define XCHAL_DCACHE_SIZE 0
28924 #undef XCHAL_ICACHE_LINESIZE
28925 -#define XCHAL_ICACHE_LINESIZE 32
28926 +#define XCHAL_ICACHE_LINESIZE 16
28928 #undef XCHAL_DCACHE_LINESIZE
28929 -#define XCHAL_DCACHE_LINESIZE 32
28930 +#define XCHAL_DCACHE_LINESIZE 16
28932 #undef XCHAL_ICACHE_LINEWIDTH
28933 -#define XCHAL_ICACHE_LINEWIDTH 5
28934 +#define XCHAL_ICACHE_LINEWIDTH 4
28936 #undef XCHAL_DCACHE_LINEWIDTH
28937 -#define XCHAL_DCACHE_LINEWIDTH 5
28938 +#define XCHAL_DCACHE_LINEWIDTH 4
28940 #undef XCHAL_DCACHE_IS_WRITEBACK
28941 -#define XCHAL_DCACHE_IS_WRITEBACK 1
28942 +#define XCHAL_DCACHE_IS_WRITEBACK 0
28945 #undef XCHAL_HAVE_MMU
28946 #define XCHAL_HAVE_MMU 1
28948 #undef XCHAL_MMU_MIN_PTE_PAGE_SIZE
28949 -#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12
28950 +#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 29
28953 #undef XCHAL_HAVE_DEBUG
28954 @@ -157,8 +152,11 @@
28955 #define XCHAL_NUM_DBREAK 2
28957 #undef XCHAL_DEBUGLEVEL
28958 -#define XCHAL_DEBUGLEVEL 6
28959 +#define XCHAL_DEBUGLEVEL 4
28962 +#undef XCHAL_EXCM_LEVEL
28963 +#define XCHAL_EXCM_LEVEL 3
28965 #undef XCHAL_MAX_INSTRUCTION_SIZE
28966 #define XCHAL_MAX_INSTRUCTION_SIZE 3