1 These Binutils patches are from the ath9k-htc-firmware repository
2 (commit f6af791348b68ceadab375e4ed0f7bcda86cb3c0).
4 Not applying the first patch (apparently) leads to miscompiled firmware,
5 and loading it fails with a "Target is unresponsive" message from the
8 The final hunk, applied to 'gas/config/tc-xtensa.c', is copied from the
9 upstream file 'local/patches/binutils-2.27_fixup.patch'.
11 From dbca73446265ce01b8e11462c3346b25953e3399 Mon Sep 17 00:00:00 2001
12 From: Sujith Manoharan <c_manoha@qca.qualcomm.com>
13 Date: Mon, 7 Jan 2013 15:59:53 +0530
14 Subject: [PATCH] binutils: AR9271/AR7010 config
16 Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
18 bfd/xtensa-modules.c | 27121 +++++++++++++---------------------------------
19 include/xtensa-config.h | 36 +-
20 2 files changed, 7663 insertions(+), 19494 deletions(-)
22 diff --git a/bfd/xtensa-modules.c b/bfd/xtensa-modules.c
23 index 3a79fcd..4704645 100644
24 --- a/bfd/xtensa-modules.c
25 +++ b/bfd/xtensa-modules.c
26 @@ -29,14 +29,6 @@ static xtensa_sysreg_internal sysregs[] = {
37 - { "PTEVADDR", 83, 0 },
41 @@ -47,29 +39,21 @@ static xtensa_sysreg_internal sysregs[] = {
44 { "CCOMPARE0", 240, 0 },
45 - { "CCOMPARE1", 241, 0 },
46 - { "CCOMPARE2", 242, 0 },
47 { "VECBASE", 231, 0 },
55 { "EXCSAVE1", 209, 0 },
56 { "EXCSAVE2", 210, 0 },
57 { "EXCSAVE3", 211, 0 },
58 { "EXCSAVE4", 212, 0 },
59 { "EXCSAVE5", 213, 0 },
60 - { "EXCSAVE6", 214, 0 },
61 - { "EXCSAVE7", 215, 0 },
68 { "EXCCAUSE", 232, 0 },
70 { "EXCVADDR", 238, 0 },
71 @@ -80,8 +64,6 @@ static xtensa_sysreg_internal sysregs[] = {
75 - { "MISC2", 246, 0 },
76 - { "MISC3", 247, 0 },
77 { "INTENABLE", 228, 0 },
78 { "DBREAKA0", 144, 0 },
79 { "DBREAKC0", 160, 0 },
80 @@ -92,19 +74,13 @@ static xtensa_sysreg_internal sysregs[] = {
81 { "IBREAKENABLE", 96, 0 },
82 { "ICOUNTLEVEL", 237, 0 },
83 { "DEBUGCAUSE", 233, 0 },
85 - { "ITLBCFG", 91, 0 },
86 - { "DTLBCFG", 92, 0 },
87 - { "CPENABLE", 224, 0 },
88 { "SCOMPARE1", 12, 0 },
89 - { "THREADPTR", 231, 1 },
92 + { "THREADPTR", 231, 1 }
95 -#define NUM_SYSREGS 74
96 -#define MAX_SPECIAL_REG 247
97 -#define MAX_USER_REG 233
98 +#define NUM_SYSREGS 50
99 +#define MAX_SPECIAL_REG 245
100 +#define MAX_USER_REG 231
103 /* Processor states. */
104 @@ -114,40 +90,33 @@ static xtensa_state_internal states[] = {
108 - { "INTERRUPT", 32, 0 },
109 + { "INTERRUPT", 19, 0 },
112 - { "VECBASE", 22, 0 },
113 + { "VECBASE", 21, 0 },
121 { "EXCSAVE1", 32, 0 },
122 { "EXCSAVE2", 32, 0 },
123 { "EXCSAVE3", 32, 0 },
124 { "EXCSAVE4", 32, 0 },
125 { "EXCSAVE5", 32, 0 },
126 - { "EXCSAVE6", 32, 0 },
127 - { "EXCSAVE7", 32, 0 },
138 { "EXCCAUSE", 6, 0 },
139 { "PSINTLEVEL", 4, 0 },
142 - { "PSRING", 2, 0 },
145 { "EXCVADDR", 32, 0 },
146 - { "WindowBase", 4, 0 },
147 - { "WindowStart", 16, 0 },
148 + { "WindowBase", 3, 0 },
149 + { "WindowStart", 8, 0 },
150 { "PSCALLINC", 2, 0 },
153 @@ -158,11 +127,8 @@ static xtensa_state_internal states[] = {
157 - { "MISC2", 32, 0 },
158 - { "MISC3", 32, 0 },
160 { "InOCDMode", 1, 0 },
161 - { "INTENABLE", 32, 0 },
162 + { "INTENABLE", 19, 0 },
163 { "DBREAKA0", 32, 0 },
164 { "DBREAKC0", 8, 0 },
165 { "DBREAKA1", 32, 0 },
166 @@ -174,34 +140,10 @@ static xtensa_state_internal states[] = {
167 { "DEBUGCAUSE", 6, 0 },
169 { "CCOMPARE0", 32, 0 },
170 - { "CCOMPARE1", 32, 0 },
171 - { "CCOMPARE2", 32, 0 },
175 - { "INSTPGSZID4", 2, 0 },
176 - { "DATAPGSZID4", 2, 0 },
177 - { "PTBASE", 10, 0 },
178 - { "CPENABLE", 1, 0 },
179 - { "SCOMPARE1", 32, 0 },
180 - { "RoundMode", 2, 0 },
181 - { "InvalidEnable", 1, 0 },
182 - { "DivZeroEnable", 1, 0 },
183 - { "OverflowEnable", 1, 0 },
184 - { "UnderflowEnable", 1, 0 },
185 - { "InexactEnable", 1, 0 },
186 - { "InvalidFlag", 1, 0 },
187 - { "DivZeroFlag", 1, 0 },
188 - { "OverflowFlag", 1, 0 },
189 - { "UnderflowFlag", 1, 0 },
190 - { "InexactFlag", 1, 0 },
191 - { "FPreserved20", 20, 0 },
192 - { "FPreserved20a", 20, 0 },
193 - { "FPreserved5", 5, 0 },
194 - { "FPreserved7", 7, 0 }
197 -#define NUM_STATES 89
198 + { "SCOMPARE1", 32, 0 }
201 +#define NUM_STATES 55
203 /* Macros for xtensa_state numbers (for use in iclasses because the
204 state numbers are not available when the iclass table is generated). */
205 @@ -219,82 +161,48 @@ static xtensa_state_internal states[] = {
206 #define STATE_EPC3 10
207 #define STATE_EPC4 11
208 #define STATE_EPC5 12
209 -#define STATE_EPC6 13
210 -#define STATE_EPC7 14
211 -#define STATE_EXCSAVE1 15
212 -#define STATE_EXCSAVE2 16
213 -#define STATE_EXCSAVE3 17
214 -#define STATE_EXCSAVE4 18
215 -#define STATE_EXCSAVE5 19
216 -#define STATE_EXCSAVE6 20
217 -#define STATE_EXCSAVE7 21
218 -#define STATE_EPS2 22
219 -#define STATE_EPS3 23
220 -#define STATE_EPS4 24
221 -#define STATE_EPS5 25
222 -#define STATE_EPS6 26
223 -#define STATE_EPS7 27
224 -#define STATE_EXCCAUSE 28
225 -#define STATE_PSINTLEVEL 29
226 -#define STATE_PSUM 30
227 -#define STATE_PSWOE 31
228 -#define STATE_PSRING 32
229 -#define STATE_PSEXCM 33
230 -#define STATE_DEPC 34
231 -#define STATE_EXCVADDR 35
232 -#define STATE_WindowBase 36
233 -#define STATE_WindowStart 37
234 -#define STATE_PSCALLINC 38
235 -#define STATE_PSOWB 39
236 -#define STATE_LBEG 40
237 -#define STATE_LEND 41
238 -#define STATE_SAR 42
239 -#define STATE_THREADPTR 43
240 -#define STATE_LITBADDR 44
241 -#define STATE_LITBEN 45
242 -#define STATE_MISC0 46
243 -#define STATE_MISC1 47
244 -#define STATE_MISC2 48
245 -#define STATE_MISC3 49
246 -#define STATE_ACC 50
247 -#define STATE_InOCDMode 51
248 -#define STATE_INTENABLE 52
249 -#define STATE_DBREAKA0 53
250 -#define STATE_DBREAKC0 54
251 -#define STATE_DBREAKA1 55
252 -#define STATE_DBREAKC1 56
253 -#define STATE_IBREAKA0 57
254 -#define STATE_IBREAKA1 58
255 -#define STATE_IBREAKENABLE 59
256 -#define STATE_ICOUNTLEVEL 60
257 -#define STATE_DEBUGCAUSE 61
258 -#define STATE_DBNUM 62
259 -#define STATE_CCOMPARE0 63
260 -#define STATE_CCOMPARE1 64
261 -#define STATE_CCOMPARE2 65
262 -#define STATE_ASID3 66
263 -#define STATE_ASID2 67
264 -#define STATE_ASID1 68
265 -#define STATE_INSTPGSZID4 69
266 -#define STATE_DATAPGSZID4 70
267 -#define STATE_PTBASE 71
268 -#define STATE_CPENABLE 72
269 -#define STATE_SCOMPARE1 73
270 -#define STATE_RoundMode 74
271 -#define STATE_InvalidEnable 75
272 -#define STATE_DivZeroEnable 76
273 -#define STATE_OverflowEnable 77
274 -#define STATE_UnderflowEnable 78
275 -#define STATE_InexactEnable 79
276 -#define STATE_InvalidFlag 80
277 -#define STATE_DivZeroFlag 81
278 -#define STATE_OverflowFlag 82
279 -#define STATE_UnderflowFlag 83
280 -#define STATE_InexactFlag 84
281 -#define STATE_FPreserved20 85
282 -#define STATE_FPreserved20a 86
283 -#define STATE_FPreserved5 87
284 -#define STATE_FPreserved7 88
285 +#define STATE_EXCSAVE1 13
286 +#define STATE_EXCSAVE2 14
287 +#define STATE_EXCSAVE3 15
288 +#define STATE_EXCSAVE4 16
289 +#define STATE_EXCSAVE5 17
290 +#define STATE_EPS2 18
291 +#define STATE_EPS3 19
292 +#define STATE_EPS4 20
293 +#define STATE_EPS5 21
294 +#define STATE_EXCCAUSE 22
295 +#define STATE_PSINTLEVEL 23
296 +#define STATE_PSUM 24
297 +#define STATE_PSWOE 25
298 +#define STATE_PSEXCM 26
299 +#define STATE_DEPC 27
300 +#define STATE_EXCVADDR 28
301 +#define STATE_WindowBase 29
302 +#define STATE_WindowStart 30
303 +#define STATE_PSCALLINC 31
304 +#define STATE_PSOWB 32
305 +#define STATE_LBEG 33
306 +#define STATE_LEND 34
307 +#define STATE_SAR 35
308 +#define STATE_THREADPTR 36
309 +#define STATE_LITBADDR 37
310 +#define STATE_LITBEN 38
311 +#define STATE_MISC0 39
312 +#define STATE_MISC1 40
313 +#define STATE_InOCDMode 41
314 +#define STATE_INTENABLE 42
315 +#define STATE_DBREAKA0 43
316 +#define STATE_DBREAKC0 44
317 +#define STATE_DBREAKA1 45
318 +#define STATE_DBREAKC1 46
319 +#define STATE_IBREAKA0 47
320 +#define STATE_IBREAKA1 48
321 +#define STATE_IBREAKENABLE 49
322 +#define STATE_ICOUNTLEVEL 50
323 +#define STATE_DEBUGCAUSE 51
324 +#define STATE_DBNUM 52
325 +#define STATE_CCOMPARE0 53
326 +#define STATE_SCOMPARE1 54
329 /* Field definitions. */
330 @@ -303,7 +211,7 @@ static unsigned
331 Field_t_Slot_inst_get (const xtensa_insnbuf insn)
334 - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
335 + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
339 @@ -312,14 +220,14 @@ Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
342 tie_t = (val << 28) >> 28;
343 - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
344 + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
348 Field_t_Slot_inst16a_get (const xtensa_insnbuf insn)
351 - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
352 + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
356 @@ -328,14 +236,14 @@ Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
359 tie_t = (val << 28) >> 28;
360 - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
361 + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
365 Field_t_Slot_inst16b_get (const xtensa_insnbuf insn)
368 - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
369 + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
373 @@ -344,20491 +252,8868 @@ Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
376 tie_t = (val << 28) >> 28;
377 - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
378 + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
382 -Field_t_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
383 +Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn)
386 - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
387 + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
392 -Field_t_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
393 +Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
396 - tie_t = (val << 28) >> 28;
397 - insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
398 + tie_t = (val << 31) >> 31;
399 + insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
403 -Field_t_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
404 +Field_bbi_Slot_inst_get (const xtensa_insnbuf insn)
407 - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
408 + tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
409 + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
414 -Field_t_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
415 +Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
418 tie_t = (val << 28) >> 28;
419 - insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
420 + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
421 + tie_t = (val << 27) >> 31;
422 + insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
426 -Field_t_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
427 +Field_imm12_Slot_inst_get (const xtensa_insnbuf insn)
430 - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
431 + tie_t = (tie_t << 12) | ((insn[0] << 20) >> 20);
436 -Field_t_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
437 +Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
440 - tie_t = (val << 28) >> 28;
441 - insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
442 + tie_t = (val << 20) >> 20;
443 + insn[0] = (insn[0] & ~0xfff) | (tie_t << 0);
447 -Field_t_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
448 +Field_imm8_Slot_inst_get (const xtensa_insnbuf insn)
451 - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
452 + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24);
457 -Field_t_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
458 +Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
461 - tie_t = (val << 28) >> 28;
462 - insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
463 + tie_t = (val << 24) >> 24;
464 + insn[0] = (insn[0] & ~0xff) | (tie_t << 0);
468 -Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn)
469 +Field_s_Slot_inst_get (const xtensa_insnbuf insn)
472 - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
473 + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
478 -Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
479 +Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
482 - tie_t = (val << 31) >> 31;
483 - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
484 + tie_t = (val << 28) >> 28;
485 + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
489 -Field_bbi_Slot_inst_get (const xtensa_insnbuf insn)
490 +Field_s_Slot_inst16a_get (const xtensa_insnbuf insn)
493 - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
494 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
499 -Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
500 +Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
503 tie_t = (val << 28) >> 28;
504 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
505 - tie_t = (val << 27) >> 31;
506 - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
510 -Field_bbi_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
511 +Field_s_Slot_inst16b_get (const xtensa_insnbuf insn)
514 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
515 - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
516 + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
521 -Field_bbi_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
522 +Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
525 tie_t = (val << 28) >> 28;
526 - insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
527 - tie_t = (val << 27) >> 31;
528 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
529 + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
533 -Field_imm12_Slot_inst_get (const xtensa_insnbuf insn)
534 +Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn)
537 - tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20);
538 + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
539 + tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24);
544 -Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
545 +Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
548 - tie_t = (val << 20) >> 20;
549 - insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12);
550 + tie_t = (val << 24) >> 24;
551 + insn[0] = (insn[0] & ~0xff) | (tie_t << 0);
552 + tie_t = (val << 20) >> 28;
553 + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
557 -Field_imm8_Slot_inst_get (const xtensa_insnbuf insn)
558 +Field_imm16_Slot_inst_get (const xtensa_insnbuf insn)
561 - tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
562 + tie_t = (tie_t << 16) | ((insn[0] << 16) >> 16);
567 -Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
568 +Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
571 - tie_t = (val << 24) >> 24;
572 - insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
573 + tie_t = (val << 16) >> 16;
574 + insn[0] = (insn[0] & ~0xffff) | (tie_t << 0);
578 -Field_imm8_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
579 +Field_m_Slot_inst_get (const xtensa_insnbuf insn)
582 - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
583 + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30);
588 -Field_imm8_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
589 +Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
592 - tie_t = (val << 24) >> 24;
593 - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
594 + tie_t = (val << 30) >> 30;
595 + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16);
599 -Field_imm8_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
600 +Field_n_Slot_inst_get (const xtensa_insnbuf insn)
603 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
604 - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
605 + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30);
610 -Field_imm8_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
611 +Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
614 - tie_t = (val << 28) >> 28;
615 - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
616 - tie_t = (val << 24) >> 28;
617 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
618 + tie_t = (val << 30) >> 30;
619 + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18);
623 -Field_s_Slot_inst_get (const xtensa_insnbuf insn)
624 +Field_offset_Slot_inst_get (const xtensa_insnbuf insn)
627 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
628 + tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14);
633 -Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
634 +Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
637 - tie_t = (val << 28) >> 28;
638 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
639 + tie_t = (val << 14) >> 14;
640 + insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0);
644 -Field_s_Slot_inst16a_get (const xtensa_insnbuf insn)
645 +Field_op0_Slot_inst_get (const xtensa_insnbuf insn)
648 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
649 + tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
654 -Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
655 +Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
658 tie_t = (val << 28) >> 28;
659 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
660 + insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
664 -Field_s_Slot_inst16b_get (const xtensa_insnbuf insn)
665 +Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn)
668 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
669 + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
674 -Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
675 +Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
678 tie_t = (val << 28) >> 28;
679 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
680 + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
684 -Field_s_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
685 +Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn)
688 - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
689 + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
694 -Field_s_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
695 +Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
698 tie_t = (val << 28) >> 28;
699 - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
700 + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
704 -Field_s_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
705 +Field_op1_Slot_inst_get (const xtensa_insnbuf insn)
708 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
709 + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
714 -Field_s_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
715 +Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
718 tie_t = (val << 28) >> 28;
719 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
720 + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
724 -Field_s_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
725 +Field_op2_Slot_inst_get (const xtensa_insnbuf insn)
728 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
729 + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
734 -Field_s_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
735 +Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
738 tie_t = (val << 28) >> 28;
739 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
740 + insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
744 -Field_s_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
745 +Field_r_Slot_inst_get (const xtensa_insnbuf insn)
748 - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
749 + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
754 -Field_s_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
755 +Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
758 tie_t = (val << 28) >> 28;
759 - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
760 + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
764 -Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn)
765 +Field_r_Slot_inst16a_get (const xtensa_insnbuf insn)
768 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
769 - tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
770 + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
775 -Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
776 +Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
779 - tie_t = (val << 24) >> 24;
780 - insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
781 - tie_t = (val << 20) >> 28;
782 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
783 + tie_t = (val << 28) >> 28;
784 + insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
788 -Field_imm12b_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
789 +Field_r_Slot_inst16b_get (const xtensa_insnbuf insn)
792 - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
793 - tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
794 + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
799 -Field_imm12b_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
800 +Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
803 - tie_t = (val << 24) >> 24;
804 - insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
805 - tie_t = (val << 20) >> 28;
806 - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
807 + tie_t = (val << 28) >> 28;
808 + insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
812 -Field_imm12b_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
813 +Field_sa4_Slot_inst_get (const xtensa_insnbuf insn)
816 - tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20);
817 + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
822 -Field_imm12b_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
823 +Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
826 - tie_t = (val << 20) >> 20;
827 - insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4);
828 + tie_t = (val << 31) >> 31;
829 + insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
833 -Field_imm16_Slot_inst_get (const xtensa_insnbuf insn)
834 +Field_sae4_Slot_inst_get (const xtensa_insnbuf insn)
837 - tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16);
838 + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
843 -Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
844 +Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
847 - tie_t = (val << 16) >> 16;
848 - insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8);
849 + tie_t = (val << 31) >> 31;
850 + insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
854 -Field_imm16_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
855 +Field_sae_Slot_inst_get (const xtensa_insnbuf insn)
858 - tie_t = (tie_t << 16) | ((insn[0] << 12) >> 16);
859 + tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
860 + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
865 -Field_imm16_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
866 +Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
869 - tie_t = (val << 16) >> 16;
870 - insn[0] = (insn[0] & ~0xffff0) | (tie_t << 4);
871 + tie_t = (val << 28) >> 28;
872 + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
873 + tie_t = (val << 27) >> 31;
874 + insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
878 -Field_m_Slot_inst_get (const xtensa_insnbuf insn)
879 +Field_sal_Slot_inst_get (const xtensa_insnbuf insn)
882 - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
883 + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
884 + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
889 -Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
890 +Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
893 - tie_t = (val << 30) >> 30;
894 - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
895 + tie_t = (val << 28) >> 28;
896 + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
897 + tie_t = (val << 27) >> 31;
898 + insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
902 -Field_m_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
903 +Field_sargt_Slot_inst_get (const xtensa_insnbuf insn)
906 - tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30);
907 + tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
908 + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
913 -Field_m_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
914 +Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
917 - tie_t = (val << 30) >> 30;
918 - insn[0] = (insn[0] & ~0xc) | (tie_t << 2);
919 + tie_t = (val << 28) >> 28;
920 + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
921 + tie_t = (val << 27) >> 31;
922 + insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
926 -Field_n_Slot_inst_get (const xtensa_insnbuf insn)
927 +Field_sas4_Slot_inst_get (const xtensa_insnbuf insn)
930 - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
931 + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
936 -Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
937 +Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
940 - tie_t = (val << 30) >> 30;
941 - insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
942 + tie_t = (val << 31) >> 31;
943 + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
947 -Field_n_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
948 +Field_sas_Slot_inst_get (const xtensa_insnbuf insn)
951 - tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30);
952 + tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
953 + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
958 -Field_n_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
959 +Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
962 - tie_t = (val << 30) >> 30;
963 - insn[0] = (insn[0] & ~0x3) | (tie_t << 0);
964 + tie_t = (val << 28) >> 28;
965 + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
966 + tie_t = (val << 27) >> 31;
967 + insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
971 -Field_offset_Slot_inst_get (const xtensa_insnbuf insn)
972 +Field_sr_Slot_inst_get (const xtensa_insnbuf insn)
975 - tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
976 + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
977 + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
982 -Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
983 +Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
986 - tie_t = (val << 14) >> 14;
987 - insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
988 + tie_t = (val << 28) >> 28;
989 + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
990 + tie_t = (val << 24) >> 28;
991 + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
995 -Field_offset_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
996 +Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn)
999 - tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14);
1000 + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1001 + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1006 -Field_offset_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
1007 +Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1010 - tie_t = (val << 14) >> 14;
1011 - insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0);
1012 + tie_t = (val << 28) >> 28;
1013 + insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1014 + tie_t = (val << 24) >> 28;
1015 + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1019 -Field_op0_Slot_inst_get (const xtensa_insnbuf insn)
1020 +Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn)
1023 + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1024 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1029 -Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1030 +Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1033 tie_t = (val << 28) >> 28;
1034 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1035 + tie_t = (val << 24) >> 28;
1036 + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1040 -Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn)
1041 +Field_st_Slot_inst_get (const xtensa_insnbuf insn)
1044 - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1045 + tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1046 + tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
1051 -Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1052 +Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1055 tie_t = (val << 28) >> 28;
1056 - insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1057 + insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
1058 + tie_t = (val << 24) >> 28;
1059 + insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1063 -Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn)
1064 +Field_st_Slot_inst16a_get (const xtensa_insnbuf insn)
1067 - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1068 + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1069 + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1074 -Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1075 +Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1078 tie_t = (val << 28) >> 28;
1079 - insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1080 + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1081 + tie_t = (val << 24) >> 28;
1082 + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1086 -Field_op1_Slot_inst_get (const xtensa_insnbuf insn)
1087 +Field_st_Slot_inst16b_get (const xtensa_insnbuf insn)
1090 - tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
1091 + tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1092 + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1097 -Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1098 +Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1101 tie_t = (val << 28) >> 28;
1102 - insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
1103 + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1104 + tie_t = (val << 24) >> 28;
1105 + insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1109 -Field_op1_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
1110 +Field_thi3_Slot_inst_get (const xtensa_insnbuf insn)
1113 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1114 + tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29);
1119 -Field_op1_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
1120 +Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1123 - tie_t = (val << 28) >> 28;
1124 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1125 + tie_t = (val << 29) >> 29;
1126 + insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
1130 -Field_op2_Slot_inst_get (const xtensa_insnbuf insn)
1131 +Field_imm4_Slot_inst_get (const xtensa_insnbuf insn)
1134 - tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
1135 + tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1140 -Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1141 +Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1144 tie_t = (val << 28) >> 28;
1145 - insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
1146 + insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1150 -Field_op2_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
1151 +Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn)
1154 - tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
1155 + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1160 -Field_op2_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
1161 +Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1164 tie_t = (val << 28) >> 28;
1165 - insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
1166 + insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1170 -Field_op2_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
1171 +Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn)
1174 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1175 + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1180 -Field_op2_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
1181 +Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1184 tie_t = (val << 28) >> 28;
1185 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1186 + insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1190 -Field_r_Slot_inst_get (const xtensa_insnbuf insn)
1191 +Field_mn_Slot_inst_get (const xtensa_insnbuf insn)
1194 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1195 + tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30);
1196 + tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30);
1201 -Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1202 +Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1205 - tie_t = (val << 28) >> 28;
1206 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1207 + tie_t = (val << 30) >> 30;
1208 + insn[0] = (insn[0] & ~0x30000) | (tie_t << 16);
1209 + tie_t = (val << 28) >> 30;
1210 + insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18);
1214 -Field_r_Slot_inst16a_get (const xtensa_insnbuf insn)
1215 +Field_i_Slot_inst16a_get (const xtensa_insnbuf insn)
1218 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1219 + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
1224 -Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1225 +Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1228 - tie_t = (val << 28) >> 28;
1229 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1230 + tie_t = (val << 31) >> 31;
1231 + insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
1235 -Field_r_Slot_inst16b_get (const xtensa_insnbuf insn)
1236 +Field_i_Slot_inst16b_get (const xtensa_insnbuf insn)
1239 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1240 + tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
1245 -Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1246 +Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1249 - tie_t = (val << 28) >> 28;
1250 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1251 + tie_t = (val << 31) >> 31;
1252 + insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
1256 -Field_r_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
1257 +Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn)
1260 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1261 + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1266 -Field_r_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
1267 +Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1270 tie_t = (val << 28) >> 28;
1271 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1272 + insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1276 -Field_r_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
1277 +Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn)
1280 - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1281 + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1286 -Field_r_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
1287 +Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1290 tie_t = (val << 28) >> 28;
1291 - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1292 + insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1296 -Field_r_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
1297 +Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn)
1300 - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1301 + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
1306 -Field_r_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
1307 +Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1310 - tie_t = (val << 28) >> 28;
1311 - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1312 + tie_t = (val << 30) >> 30;
1313 + insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
1317 -Field_r_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
1318 +Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn)
1321 - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1322 + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
1327 -Field_r_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
1328 +Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1331 - tie_t = (val << 28) >> 28;
1332 - insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1333 + tie_t = (val << 30) >> 30;
1334 + insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
1338 -Field_sa4_Slot_inst_get (const xtensa_insnbuf insn)
1339 +Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn)
1342 - tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
1343 + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1348 -Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1349 +Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1352 - tie_t = (val << 31) >> 31;
1353 - insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
1354 + tie_t = (val << 28) >> 28;
1355 + insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1359 -Field_sae4_Slot_inst_get (const xtensa_insnbuf insn)
1360 +Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn)
1363 - tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
1364 + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1369 -Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1370 +Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1373 - tie_t = (val << 31) >> 31;
1374 - insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
1375 + tie_t = (val << 28) >> 28;
1376 + insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1380 -Field_sae4_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
1381 +Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn)
1384 - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
1385 + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
1390 -Field_sae4_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
1391 +Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1394 - tie_t = (val << 31) >> 31;
1395 - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
1396 + tie_t = (val << 29) >> 29;
1397 + insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
1401 -Field_sae_Slot_inst_get (const xtensa_insnbuf insn)
1402 +Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn)
1405 - tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
1406 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1407 + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
1412 -Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1413 +Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1416 - tie_t = (val << 28) >> 28;
1417 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1418 - tie_t = (val << 27) >> 31;
1419 - insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
1420 + tie_t = (val << 29) >> 29;
1421 + insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
1425 -Field_sae_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
1426 +Field_z_Slot_inst16a_get (const xtensa_insnbuf insn)
1429 - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
1430 - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1431 + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31);
1436 -Field_sae_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
1437 +Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1440 - tie_t = (val << 28) >> 28;
1441 - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1442 - tie_t = (val << 27) >> 31;
1443 - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
1444 + tie_t = (val << 31) >> 31;
1445 + insn[0] = (insn[0] & ~0x400) | (tie_t << 10);
1449 -Field_sae_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
1450 +Field_z_Slot_inst16b_get (const xtensa_insnbuf insn)
1453 - tie_t = (tie_t << 5) | ((insn[0] << 15) >> 27);
1454 + tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31);
1459 -Field_sae_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
1460 +Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1463 - tie_t = (val << 27) >> 27;
1464 - insn[0] = (insn[0] & ~0x1f000) | (tie_t << 12);
1465 + tie_t = (val << 31) >> 31;
1466 + insn[0] = (insn[0] & ~0x400) | (tie_t << 10);
1470 -Field_sal_Slot_inst_get (const xtensa_insnbuf insn)
1471 +Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn)
1474 - tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
1475 - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1476 + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
1477 + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1482 -Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1483 +Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1486 tie_t = (val << 28) >> 28;
1487 - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1488 - tie_t = (val << 27) >> 31;
1489 - insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
1490 + insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1491 + tie_t = (val << 26) >> 30;
1492 + insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
1496 -Field_sal_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
1497 +Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn)
1500 - tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
1501 + tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
1502 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1507 -Field_sal_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
1508 +Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1511 tie_t = (val << 28) >> 28;
1512 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1513 - tie_t = (val << 27) >> 31;
1514 - insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
1515 + tie_t = (val << 26) >> 30;
1516 + insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
1520 -Field_sal_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
1521 +Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn)
1524 - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
1525 + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
1526 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1531 -Field_sal_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
1532 +Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1535 tie_t = (val << 28) >> 28;
1536 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1537 - tie_t = (val << 27) >> 31;
1538 - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
1539 + tie_t = (val << 25) >> 29;
1540 + insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
1544 -Field_sargt_Slot_inst_get (const xtensa_insnbuf insn)
1545 +Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn)
1548 - tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
1549 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1550 + tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
1551 + tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1556 -Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1557 +Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1560 tie_t = (val << 28) >> 28;
1561 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1562 - tie_t = (val << 27) >> 31;
1563 - insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
1564 + insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
1565 + tie_t = (val << 25) >> 29;
1566 + insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
1570 -Field_sargt_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
1571 +Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn)
1574 - tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
1575 - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1576 + tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17);
1581 -Field_sargt_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
1582 +Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1585 - tie_t = (val << 28) >> 28;
1586 - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1587 - tie_t = (val << 27) >> 31;
1588 - insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
1589 + tie_t = (val << 17) >> 17;
1590 + insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9);
1594 -Field_sargt_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
1595 +Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn)
1598 - tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27);
1599 + tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
1604 -Field_sargt_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
1605 +Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1608 - tie_t = (val << 27) >> 27;
1609 - insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8);
1610 + tie_t = (val << 14) >> 14;
1611 + insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
1615 -Field_sargt_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
1617 +Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED,
1618 + uint32 val ATTRIBUTE_UNUSED)
1620 - unsigned tie_t = 0;
1621 - tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27);
1627 -Field_sargt_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
1629 +Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1632 - tie_t = (val << 27) >> 27;
1633 - insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8);
1638 -Field_sas4_Slot_inst_get (const xtensa_insnbuf insn)
1639 +Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1641 - unsigned tie_t = 0;
1642 - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
1648 -Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1650 +Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1653 - tie_t = (val << 31) >> 31;
1654 - insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
1659 -Field_sas_Slot_inst_get (const xtensa_insnbuf insn)
1660 +Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
1662 - unsigned tie_t = 0;
1663 - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
1664 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1670 -Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1672 +/* Functional units. */
1674 +static xtensa_funcUnit_internal funcUnits[] = {
1679 +/* Register files. */
1681 +static xtensa_regfile_internal regfiles[] = {
1682 + { "AR", "a", 0, 32, 32 }
1688 +static xtensa_interface_internal interfaces[] = {
1693 +/* Constant tables. */
1695 +/* constant table ai4c */
1696 +static const unsigned CONST_TBL_ai4c_0[] = {
1716 +/* constant table b4c */
1717 +static const unsigned CONST_TBL_b4c_0[] = {
1737 +/* constant table b4cu */
1738 +static const unsigned CONST_TBL_b4cu_0[] = {
1759 +/* Instruction operands. */
1762 +Operand_soffsetx4_decode (uint32 *valp)
1765 - tie_t = (val << 28) >> 28;
1766 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1767 - tie_t = (val << 27) >> 31;
1768 - insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
1769 + unsigned soffsetx4_0, offset_0;
1770 + offset_0 = *valp & 0x3ffff;
1771 + soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2);
1772 + *valp = soffsetx4_0;
1777 -Field_sas_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
1779 +Operand_soffsetx4_encode (uint32 *valp)
1781 - unsigned tie_t = 0;
1782 - tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
1783 - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1785 + unsigned offset_0, soffsetx4_0;
1786 + soffsetx4_0 = *valp;
1787 + offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff;
1793 -Field_sas_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
1795 +Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
1798 - tie_t = (val << 28) >> 28;
1799 - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1800 - tie_t = (val << 27) >> 31;
1801 - insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
1802 + *valp -= (pc & ~0x3);
1807 -Field_sr_Slot_inst_get (const xtensa_insnbuf insn)
1809 +Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
1811 - unsigned tie_t = 0;
1812 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1813 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1815 + *valp += (pc & ~0x3);
1820 -Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1822 +Operand_uimm12x8_decode (uint32 *valp)
1825 - tie_t = (val << 28) >> 28;
1826 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1827 - tie_t = (val << 24) >> 28;
1828 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1829 + unsigned uimm12x8_0, imm12_0;
1830 + imm12_0 = *valp & 0xfff;
1831 + uimm12x8_0 = imm12_0 << 3;
1832 + *valp = uimm12x8_0;
1837 -Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn)
1839 +Operand_uimm12x8_encode (uint32 *valp)
1841 - unsigned tie_t = 0;
1842 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1843 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1845 + unsigned imm12_0, uimm12x8_0;
1846 + uimm12x8_0 = *valp;
1847 + imm12_0 = ((uimm12x8_0 >> 3) & 0xfff);
1853 -Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1855 +Operand_simm4_decode (uint32 *valp)
1858 - tie_t = (val << 28) >> 28;
1859 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1860 - tie_t = (val << 24) >> 28;
1861 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1862 + unsigned simm4_0, mn_0;
1863 + mn_0 = *valp & 0xf;
1864 + simm4_0 = ((int) mn_0 << 28) >> 28;
1870 -Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn)
1872 +Operand_simm4_encode (uint32 *valp)
1874 - unsigned tie_t = 0;
1875 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1876 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1878 + unsigned mn_0, simm4_0;
1880 + mn_0 = (simm4_0 & 0xf);
1886 -Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1888 +Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED)
1891 - tie_t = (val << 28) >> 28;
1892 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1893 - tie_t = (val << 24) >> 28;
1894 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1899 -Field_st_Slot_inst_get (const xtensa_insnbuf insn)
1901 +Operand_arr_encode (uint32 *valp)
1903 - unsigned tie_t = 0;
1904 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1905 - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1908 + error = (*valp & ~0xf) != 0;
1913 -Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1915 +Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED)
1918 - tie_t = (val << 28) >> 28;
1919 - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1920 - tie_t = (val << 24) >> 28;
1921 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1926 -Field_st_Slot_inst16a_get (const xtensa_insnbuf insn)
1928 +Operand_ars_encode (uint32 *valp)
1930 - unsigned tie_t = 0;
1931 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1932 - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1935 + error = (*valp & ~0xf) != 0;
1940 -Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
1942 +Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED)
1945 - tie_t = (val << 28) >> 28;
1946 - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1947 - tie_t = (val << 24) >> 28;
1948 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1953 -Field_st_Slot_inst16b_get (const xtensa_insnbuf insn)
1955 +Operand_art_encode (uint32 *valp)
1957 - unsigned tie_t = 0;
1958 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1959 - tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1962 + error = (*valp & ~0xf) != 0;
1967 -Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
1970 - tie_t = (val << 28) >> 28;
1971 - insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1972 - tie_t = (val << 24) >> 28;
1973 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1977 -Field_thi3_Slot_inst_get (const xtensa_insnbuf insn)
1979 +Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED)
1981 - unsigned tie_t = 0;
1982 - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
1988 -Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
1990 +Operand_ar0_encode (uint32 *valp)
1993 - tie_t = (val << 29) >> 29;
1994 - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
1996 + error = (*valp & ~0x1f) != 0;
2001 -Field_thi3_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
2003 +Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED)
2005 - unsigned tie_t = 0;
2006 - tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29);
2012 -Field_thi3_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
2014 +Operand_ar4_encode (uint32 *valp)
2017 - tie_t = (val << 29) >> 29;
2018 - insn[0] = (insn[0] & ~0xe) | (tie_t << 1);
2020 + error = (*valp & ~0x1f) != 0;
2025 -Field_imm4_Slot_inst_get (const xtensa_insnbuf insn)
2027 +Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED)
2029 - unsigned tie_t = 0;
2030 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
2036 -Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2038 +Operand_ar8_encode (uint32 *valp)
2041 - tie_t = (val << 28) >> 28;
2042 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
2044 + error = (*valp & ~0x1f) != 0;
2049 -Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn)
2051 +Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED)
2053 - unsigned tie_t = 0;
2054 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
2060 -Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2062 +Operand_ar12_encode (uint32 *valp)
2065 - tie_t = (val << 28) >> 28;
2066 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
2068 + error = (*valp & ~0x1f) != 0;
2073 -Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn)
2075 +Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED)
2077 - unsigned tie_t = 0;
2078 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
2084 -Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2086 +Operand_ars_entry_encode (uint32 *valp)
2089 - tie_t = (val << 28) >> 28;
2090 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
2092 + error = (*valp & ~0x1f) != 0;
2097 -Field_mn_Slot_inst_get (const xtensa_insnbuf insn)
2099 +Operand_immrx4_decode (uint32 *valp)
2101 - unsigned tie_t = 0;
2102 - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
2103 - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
2105 + unsigned immrx4_0, r_0;
2106 + r_0 = *valp & 0xf;
2107 + immrx4_0 = (((0xfffffff) << 4) | r_0) << 2;
2113 -Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2115 +Operand_immrx4_encode (uint32 *valp)
2118 - tie_t = (val << 30) >> 30;
2119 - insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
2120 - tie_t = (val << 28) >> 30;
2121 - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
2122 + unsigned r_0, immrx4_0;
2124 + r_0 = ((immrx4_0 >> 2) & 0xf);
2130 -Field_i_Slot_inst16a_get (const xtensa_insnbuf insn)
2132 +Operand_lsi4x4_decode (uint32 *valp)
2134 - unsigned tie_t = 0;
2135 - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
2137 + unsigned lsi4x4_0, r_0;
2138 + r_0 = *valp & 0xf;
2139 + lsi4x4_0 = r_0 << 2;
2145 -Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2147 +Operand_lsi4x4_encode (uint32 *valp)
2150 - tie_t = (val << 31) >> 31;
2151 - insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
2152 + unsigned r_0, lsi4x4_0;
2154 + r_0 = ((lsi4x4_0 >> 2) & 0xf);
2160 -Field_i_Slot_inst16b_get (const xtensa_insnbuf insn)
2162 +Operand_simm7_decode (uint32 *valp)
2164 - unsigned tie_t = 0;
2165 - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
2167 + unsigned simm7_0, imm7_0;
2168 + imm7_0 = *valp & 0x7f;
2169 + simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0;
2175 -Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2177 +Operand_simm7_encode (uint32 *valp)
2180 - tie_t = (val << 31) >> 31;
2181 - insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
2182 + unsigned imm7_0, simm7_0;
2184 + imm7_0 = (simm7_0 & 0x7f);
2190 -Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn)
2192 +Operand_uimm6_decode (uint32 *valp)
2194 - unsigned tie_t = 0;
2195 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
2197 + unsigned uimm6_0, imm6_0;
2198 + imm6_0 = *valp & 0x3f;
2199 + uimm6_0 = 0x4 + (((0) << 6) | imm6_0);
2205 -Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2207 +Operand_uimm6_encode (uint32 *valp)
2210 - tie_t = (val << 28) >> 28;
2211 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
2212 + unsigned imm6_0, uimm6_0;
2214 + imm6_0 = (uimm6_0 - 0x4) & 0x3f;
2220 -Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn)
2222 +Operand_uimm6_ator (uint32 *valp, uint32 pc)
2224 - unsigned tie_t = 0;
2225 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
2232 -Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2234 +Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
2237 - tie_t = (val << 28) >> 28;
2238 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
2244 -Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn)
2246 +Operand_ai4const_decode (uint32 *valp)
2248 - unsigned tie_t = 0;
2249 - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
2251 + unsigned ai4const_0, t_0;
2252 + t_0 = *valp & 0xf;
2253 + ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf];
2254 + *valp = ai4const_0;
2259 -Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2261 +Operand_ai4const_encode (uint32 *valp)
2264 - tie_t = (val << 30) >> 30;
2265 - insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
2266 + unsigned t_0, ai4const_0;
2267 + ai4const_0 = *valp;
2268 + switch (ai4const_0)
2270 + case 0xffffffff: t_0 = 0; break;
2271 + case 0x1: t_0 = 0x1; break;
2272 + case 0x2: t_0 = 0x2; break;
2273 + case 0x3: t_0 = 0x3; break;
2274 + case 0x4: t_0 = 0x4; break;
2275 + case 0x5: t_0 = 0x5; break;
2276 + case 0x6: t_0 = 0x6; break;
2277 + case 0x7: t_0 = 0x7; break;
2278 + case 0x8: t_0 = 0x8; break;
2279 + case 0x9: t_0 = 0x9; break;
2280 + case 0xa: t_0 = 0xa; break;
2281 + case 0xb: t_0 = 0xb; break;
2282 + case 0xc: t_0 = 0xc; break;
2283 + case 0xd: t_0 = 0xd; break;
2284 + case 0xe: t_0 = 0xe; break;
2285 + default: t_0 = 0xf; break;
2292 -Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn)
2294 +Operand_b4const_decode (uint32 *valp)
2296 - unsigned tie_t = 0;
2297 - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
2299 + unsigned b4const_0, r_0;
2300 + r_0 = *valp & 0xf;
2301 + b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf];
2302 + *valp = b4const_0;
2307 -Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2309 +Operand_b4const_encode (uint32 *valp)
2312 - tie_t = (val << 30) >> 30;
2313 - insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
2315 + unsigned r_0, b4const_0;
2316 + b4const_0 = *valp;
2317 + switch (b4const_0)
2319 + case 0xffffffff: r_0 = 0; break;
2320 + case 0x1: r_0 = 0x1; break;
2321 + case 0x2: r_0 = 0x2; break;
2322 + case 0x3: r_0 = 0x3; break;
2323 + case 0x4: r_0 = 0x4; break;
2324 + case 0x5: r_0 = 0x5; break;
2325 + case 0x6: r_0 = 0x6; break;
2326 + case 0x7: r_0 = 0x7; break;
2327 + case 0x8: r_0 = 0x8; break;
2328 + case 0xa: r_0 = 0x9; break;
2329 + case 0xc: r_0 = 0xa; break;
2330 + case 0x10: r_0 = 0xb; break;
2331 + case 0x20: r_0 = 0xc; break;
2332 + case 0x40: r_0 = 0xd; break;
2333 + case 0x80: r_0 = 0xe; break;
2334 + default: r_0 = 0xf; break;
2341 -Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn)
2343 +Operand_b4constu_decode (uint32 *valp)
2345 - unsigned tie_t = 0;
2346 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
2348 + unsigned b4constu_0, r_0;
2349 + r_0 = *valp & 0xf;
2350 + b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf];
2351 + *valp = b4constu_0;
2356 -Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2358 +Operand_b4constu_encode (uint32 *valp)
2361 - tie_t = (val << 28) >> 28;
2362 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
2363 + unsigned r_0, b4constu_0;
2364 + b4constu_0 = *valp;
2365 + switch (b4constu_0)
2367 + case 0x8000: r_0 = 0; break;
2368 + case 0x10000: r_0 = 0x1; break;
2369 + case 0x2: r_0 = 0x2; break;
2370 + case 0x3: r_0 = 0x3; break;
2371 + case 0x4: r_0 = 0x4; break;
2372 + case 0x5: r_0 = 0x5; break;
2373 + case 0x6: r_0 = 0x6; break;
2374 + case 0x7: r_0 = 0x7; break;
2375 + case 0x8: r_0 = 0x8; break;
2376 + case 0xa: r_0 = 0x9; break;
2377 + case 0xc: r_0 = 0xa; break;
2378 + case 0x10: r_0 = 0xb; break;
2379 + case 0x20: r_0 = 0xc; break;
2380 + case 0x40: r_0 = 0xd; break;
2381 + case 0x80: r_0 = 0xe; break;
2382 + default: r_0 = 0xf; break;
2389 -Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn)
2391 +Operand_uimm8_decode (uint32 *valp)
2393 - unsigned tie_t = 0;
2394 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
2396 + unsigned uimm8_0, imm8_0;
2397 + imm8_0 = *valp & 0xff;
2404 -Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2406 +Operand_uimm8_encode (uint32 *valp)
2409 - tie_t = (val << 28) >> 28;
2410 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
2411 + unsigned imm8_0, uimm8_0;
2413 + imm8_0 = (uimm8_0 & 0xff);
2419 -Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn)
2421 +Operand_uimm8x2_decode (uint32 *valp)
2423 - unsigned tie_t = 0;
2424 - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
2426 + unsigned uimm8x2_0, imm8_0;
2427 + imm8_0 = *valp & 0xff;
2428 + uimm8x2_0 = imm8_0 << 1;
2429 + *valp = uimm8x2_0;
2434 -Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2436 +Operand_uimm8x2_encode (uint32 *valp)
2439 - tie_t = (val << 29) >> 29;
2440 - insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
2441 + unsigned imm8_0, uimm8x2_0;
2442 + uimm8x2_0 = *valp;
2443 + imm8_0 = ((uimm8x2_0 >> 1) & 0xff);
2449 -Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn)
2451 +Operand_uimm8x4_decode (uint32 *valp)
2453 - unsigned tie_t = 0;
2454 - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
2456 + unsigned uimm8x4_0, imm8_0;
2457 + imm8_0 = *valp & 0xff;
2458 + uimm8x4_0 = imm8_0 << 2;
2459 + *valp = uimm8x4_0;
2464 -Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2466 +Operand_uimm8x4_encode (uint32 *valp)
2469 - tie_t = (val << 29) >> 29;
2470 - insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
2471 + unsigned imm8_0, uimm8x4_0;
2472 + uimm8x4_0 = *valp;
2473 + imm8_0 = ((uimm8x4_0 >> 2) & 0xff);
2479 -Field_z_Slot_inst16a_get (const xtensa_insnbuf insn)
2481 +Operand_uimm4x16_decode (uint32 *valp)
2483 - unsigned tie_t = 0;
2484 - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
2486 + unsigned uimm4x16_0, op2_0;
2487 + op2_0 = *valp & 0xf;
2488 + uimm4x16_0 = op2_0 << 4;
2489 + *valp = uimm4x16_0;
2494 -Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2496 +Operand_uimm4x16_encode (uint32 *valp)
2499 - tie_t = (val << 31) >> 31;
2500 - insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
2501 + unsigned op2_0, uimm4x16_0;
2502 + uimm4x16_0 = *valp;
2503 + op2_0 = ((uimm4x16_0 >> 4) & 0xf);
2509 -Field_z_Slot_inst16b_get (const xtensa_insnbuf insn)
2511 +Operand_simm8_decode (uint32 *valp)
2513 - unsigned tie_t = 0;
2514 - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
2516 + unsigned simm8_0, imm8_0;
2517 + imm8_0 = *valp & 0xff;
2518 + simm8_0 = ((int) imm8_0 << 24) >> 24;
2524 -Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2526 +Operand_simm8_encode (uint32 *valp)
2529 - tie_t = (val << 31) >> 31;
2530 - insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
2531 + unsigned imm8_0, simm8_0;
2533 + imm8_0 = (simm8_0 & 0xff);
2539 -Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn)
2541 +Operand_simm8x256_decode (uint32 *valp)
2543 - unsigned tie_t = 0;
2544 - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
2545 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
2547 + unsigned simm8x256_0, imm8_0;
2548 + imm8_0 = *valp & 0xff;
2549 + simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8;
2550 + *valp = simm8x256_0;
2555 -Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2557 +Operand_simm8x256_encode (uint32 *valp)
2560 - tie_t = (val << 28) >> 28;
2561 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
2562 - tie_t = (val << 26) >> 30;
2563 - insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
2564 + unsigned imm8_0, simm8x256_0;
2565 + simm8x256_0 = *valp;
2566 + imm8_0 = ((simm8x256_0 >> 8) & 0xff);
2572 -Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn)
2574 +Operand_simm12b_decode (uint32 *valp)
2576 - unsigned tie_t = 0;
2577 - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
2578 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
2580 + unsigned simm12b_0, imm12b_0;
2581 + imm12b_0 = *valp & 0xfff;
2582 + simm12b_0 = ((int) imm12b_0 << 20) >> 20;
2583 + *valp = simm12b_0;
2588 -Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2590 +Operand_simm12b_encode (uint32 *valp)
2593 - tie_t = (val << 28) >> 28;
2594 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
2595 - tie_t = (val << 26) >> 30;
2596 - insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
2597 + unsigned imm12b_0, simm12b_0;
2598 + simm12b_0 = *valp;
2599 + imm12b_0 = (simm12b_0 & 0xfff);
2605 -Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn)
2607 +Operand_msalp32_decode (uint32 *valp)
2609 - unsigned tie_t = 0;
2610 - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
2611 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
2613 + unsigned msalp32_0, sal_0;
2614 + sal_0 = *valp & 0x1f;
2615 + msalp32_0 = 0x20 - sal_0;
2616 + *valp = msalp32_0;
2621 -Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2623 +Operand_msalp32_encode (uint32 *valp)
2626 - tie_t = (val << 28) >> 28;
2627 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
2628 - tie_t = (val << 25) >> 29;
2629 - insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
2630 + unsigned sal_0, msalp32_0;
2631 + msalp32_0 = *valp;
2632 + sal_0 = (0x20 - msalp32_0) & 0x1f;
2638 -Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn)
2640 - unsigned tie_t = 0;
2641 - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
2642 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
2645 +Operand_op2p1_decode (uint32 *valp)
2647 + unsigned op2p1_0, op2_0;
2648 + op2_0 = *valp & 0xf;
2649 + op2p1_0 = op2_0 + 0x1;
2655 -Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2657 +Operand_op2p1_encode (uint32 *valp)
2660 - tie_t = (val << 28) >> 28;
2661 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
2662 - tie_t = (val << 25) >> 29;
2663 - insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
2664 + unsigned op2_0, op2p1_0;
2666 + op2_0 = (op2p1_0 - 0x1) & 0xf;
2672 -Field_imm7_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
2674 +Operand_label8_decode (uint32 *valp)
2676 - unsigned tie_t = 0;
2677 - tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
2679 + unsigned label8_0, imm8_0;
2680 + imm8_0 = *valp & 0xff;
2681 + label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24);
2687 -Field_imm7_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
2689 +Operand_label8_encode (uint32 *valp)
2692 - tie_t = (val << 25) >> 25;
2693 - insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
2694 + unsigned imm8_0, label8_0;
2696 + imm8_0 = (label8_0 - 0x4) & 0xff;
2702 -Field_r3_Slot_inst_get (const xtensa_insnbuf insn)
2704 +Operand_label8_ator (uint32 *valp, uint32 pc)
2706 - unsigned tie_t = 0;
2707 - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
2714 -Field_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2716 +Operand_label8_rtoa (uint32 *valp, uint32 pc)
2719 - tie_t = (val << 31) >> 31;
2720 - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
2726 -Field_rbit2_Slot_inst_get (const xtensa_insnbuf insn)
2728 +Operand_ulabel8_decode (uint32 *valp)
2730 - unsigned tie_t = 0;
2731 - tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
2733 + unsigned ulabel8_0, imm8_0;
2734 + imm8_0 = *valp & 0xff;
2735 + ulabel8_0 = 0x4 + (((0) << 8) | imm8_0);
2736 + *valp = ulabel8_0;
2741 -Field_rbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2743 +Operand_ulabel8_encode (uint32 *valp)
2746 - tie_t = (val << 31) >> 31;
2747 - insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
2748 + unsigned imm8_0, ulabel8_0;
2749 + ulabel8_0 = *valp;
2750 + imm8_0 = (ulabel8_0 - 0x4) & 0xff;
2756 -Field_rhi_Slot_inst_get (const xtensa_insnbuf insn)
2758 +Operand_ulabel8_ator (uint32 *valp, uint32 pc)
2760 - unsigned tie_t = 0;
2761 - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2768 -Field_rhi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2770 +Operand_ulabel8_rtoa (uint32 *valp, uint32 pc)
2773 - tie_t = (val << 30) >> 30;
2774 - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2780 -Field_t3_Slot_inst_get (const xtensa_insnbuf insn)
2782 +Operand_label12_decode (uint32 *valp)
2784 - unsigned tie_t = 0;
2785 - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
2787 + unsigned label12_0, imm12_0;
2788 + imm12_0 = *valp & 0xfff;
2789 + label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20);
2790 + *valp = label12_0;
2795 -Field_t3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2797 +Operand_label12_encode (uint32 *valp)
2800 - tie_t = (val << 31) >> 31;
2801 - insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
2802 + unsigned imm12_0, label12_0;
2803 + label12_0 = *valp;
2804 + imm12_0 = (label12_0 - 0x4) & 0xfff;
2810 -Field_tbit2_Slot_inst_get (const xtensa_insnbuf insn)
2812 +Operand_label12_ator (uint32 *valp, uint32 pc)
2814 - unsigned tie_t = 0;
2815 - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
2822 -Field_tbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2824 +Operand_label12_rtoa (uint32 *valp, uint32 pc)
2827 - tie_t = (val << 31) >> 31;
2828 - insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
2834 -Field_tlo_Slot_inst_get (const xtensa_insnbuf insn)
2836 +Operand_soffset_decode (uint32 *valp)
2838 - unsigned tie_t = 0;
2839 - tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
2841 + unsigned soffset_0, offset_0;
2842 + offset_0 = *valp & 0x3ffff;
2843 + soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14);
2844 + *valp = soffset_0;
2849 -Field_tlo_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2851 +Operand_soffset_encode (uint32 *valp)
2854 - tie_t = (val << 30) >> 30;
2855 - insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
2856 + unsigned offset_0, soffset_0;
2857 + soffset_0 = *valp;
2858 + offset_0 = (soffset_0 - 0x4) & 0x3ffff;
2864 -Field_w_Slot_inst_get (const xtensa_insnbuf insn)
2866 +Operand_soffset_ator (uint32 *valp, uint32 pc)
2868 - unsigned tie_t = 0;
2869 - tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
2876 -Field_w_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2878 +Operand_soffset_rtoa (uint32 *valp, uint32 pc)
2881 - tie_t = (val << 30) >> 30;
2882 - insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
2888 -Field_y_Slot_inst_get (const xtensa_insnbuf insn)
2890 +Operand_uimm16x4_decode (uint32 *valp)
2892 - unsigned tie_t = 0;
2893 - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
2895 + unsigned uimm16x4_0, imm16_0;
2896 + imm16_0 = *valp & 0xffff;
2897 + uimm16x4_0 = (((0xffff) << 16) | imm16_0) << 2;
2898 + *valp = uimm16x4_0;
2903 -Field_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2905 +Operand_uimm16x4_encode (uint32 *valp)
2908 - tie_t = (val << 31) >> 31;
2909 - insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
2910 + unsigned imm16_0, uimm16x4_0;
2911 + uimm16x4_0 = *valp;
2912 + imm16_0 = (uimm16x4_0 >> 2) & 0xffff;
2918 -Field_x_Slot_inst_get (const xtensa_insnbuf insn)
2920 +Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
2922 - unsigned tie_t = 0;
2923 - tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
2925 + *valp -= ((pc + 3) & ~0x3);
2930 -Field_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2932 +Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
2935 - tie_t = (val << 31) >> 31;
2936 - insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
2937 + *valp += ((pc + 3) & ~0x3);
2942 -Field_t2_Slot_inst_get (const xtensa_insnbuf insn)
2944 +Operand_immt_decode (uint32 *valp)
2946 - unsigned tie_t = 0;
2947 - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
2949 + unsigned immt_0, t_0;
2950 + t_0 = *valp & 0xf;
2957 -Field_t2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2959 +Operand_immt_encode (uint32 *valp)
2962 - tie_t = (val << 29) >> 29;
2963 - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
2964 + unsigned t_0, immt_0;
2966 + t_0 = immt_0 & 0xf;
2972 -Field_t2_Slot_inst16a_get (const xtensa_insnbuf insn)
2974 +Operand_imms_decode (uint32 *valp)
2976 - unsigned tie_t = 0;
2977 - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
2979 + unsigned imms_0, s_0;
2980 + s_0 = *valp & 0xf;
2987 -Field_t2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2989 +Operand_imms_encode (uint32 *valp)
2992 - tie_t = (val << 29) >> 29;
2993 - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
2994 + unsigned s_0, imms_0;
2996 + s_0 = imms_0 & 0xf;
3002 -Field_t2_Slot_inst16b_get (const xtensa_insnbuf insn)
3004 +Operand_tp7_decode (uint32 *valp)
3006 - unsigned tie_t = 0;
3007 - tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
3009 + unsigned tp7_0, t_0;
3010 + t_0 = *valp & 0xf;
3011 + tp7_0 = t_0 + 0x7;
3017 -Field_t2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
3019 +Operand_tp7_encode (uint32 *valp)
3022 - tie_t = (val << 29) >> 29;
3023 - insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
3024 + unsigned t_0, tp7_0;
3026 + t_0 = (tp7_0 - 0x7) & 0xf;
3032 -Field_s2_Slot_inst_get (const xtensa_insnbuf insn)
3034 +Operand_xt_wbr15_label_decode (uint32 *valp)
3036 - unsigned tie_t = 0;
3037 - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
3039 + unsigned xt_wbr15_label_0, xt_wbr15_imm_0;
3040 + xt_wbr15_imm_0 = *valp & 0x7fff;
3041 + xt_wbr15_label_0 = 0x4 + (((int) xt_wbr15_imm_0 << 17) >> 17);
3042 + *valp = xt_wbr15_label_0;
3047 -Field_s2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
3049 +Operand_xt_wbr15_label_encode (uint32 *valp)
3052 - tie_t = (val << 29) >> 29;
3053 - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
3054 + unsigned xt_wbr15_imm_0, xt_wbr15_label_0;
3055 + xt_wbr15_label_0 = *valp;
3056 + xt_wbr15_imm_0 = (xt_wbr15_label_0 - 0x4) & 0x7fff;
3057 + *valp = xt_wbr15_imm_0;
3062 -Field_s2_Slot_inst16a_get (const xtensa_insnbuf insn)
3064 +Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc)
3066 - unsigned tie_t = 0;
3067 - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
3074 -Field_s2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
3076 +Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc)
3079 - tie_t = (val << 29) >> 29;
3080 - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
3086 -Field_s2_Slot_inst16b_get (const xtensa_insnbuf insn)
3088 +Operand_xt_wbr18_label_decode (uint32 *valp)
3090 - unsigned tie_t = 0;
3091 - tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
3093 + unsigned xt_wbr18_label_0, xt_wbr18_imm_0;
3094 + xt_wbr18_imm_0 = *valp & 0x3ffff;
3095 + xt_wbr18_label_0 = 0x4 + (((int) xt_wbr18_imm_0 << 14) >> 14);
3096 + *valp = xt_wbr18_label_0;
3101 -Field_s2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
3103 +Operand_xt_wbr18_label_encode (uint32 *valp)
3106 - tie_t = (val << 29) >> 29;
3107 - insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
3108 + unsigned xt_wbr18_imm_0, xt_wbr18_label_0;
3109 + xt_wbr18_label_0 = *valp;
3110 + xt_wbr18_imm_0 = (xt_wbr18_label_0 - 0x4) & 0x3ffff;
3111 + *valp = xt_wbr18_imm_0;
3116 -Field_r2_Slot_inst_get (const xtensa_insnbuf insn)
3118 +Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc)
3120 - unsigned tie_t = 0;
3121 - tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
3128 -Field_r2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
3130 +Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc)
3133 - tie_t = (val << 29) >> 29;
3134 - insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
3140 -Field_r2_Slot_inst16a_get (const xtensa_insnbuf insn)
3142 - unsigned tie_t = 0;
3143 - tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
3146 +static xtensa_operand_internal operands[] = {
3147 + { "soffsetx4", 10, -1, 0,
3148 + XTENSA_OPERAND_IS_PCRELATIVE,
3149 + Operand_soffsetx4_encode, Operand_soffsetx4_decode,
3150 + Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
3151 + { "uimm12x8", 3, -1, 0,
3153 + Operand_uimm12x8_encode, Operand_uimm12x8_decode,
3155 + { "simm4", 26, -1, 0,
3157 + Operand_simm4_encode, Operand_simm4_decode,
3159 + { "arr", 14, 0, 1,
3160 + XTENSA_OPERAND_IS_REGISTER,
3161 + Operand_arr_encode, Operand_arr_decode,
3164 + XTENSA_OPERAND_IS_REGISTER,
3165 + Operand_ars_encode, Operand_ars_decode,
3167 + { "*ars_invisible", 5, 0, 1,
3168 + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
3169 + Operand_ars_encode, Operand_ars_decode,
3172 + XTENSA_OPERAND_IS_REGISTER,
3173 + Operand_art_encode, Operand_art_decode,
3175 + { "ar0", 37, 0, 1,
3176 + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
3177 + Operand_ar0_encode, Operand_ar0_decode,
3179 + { "ar4", 38, 0, 1,
3180 + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
3181 + Operand_ar4_encode, Operand_ar4_decode,
3183 + { "ar8", 39, 0, 1,
3184 + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
3185 + Operand_ar8_encode, Operand_ar8_decode,
3187 + { "ar12", 40, 0, 1,
3188 + XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
3189 + Operand_ar12_encode, Operand_ar12_decode,
3191 + { "ars_entry", 5, 0, 1,
3192 + XTENSA_OPERAND_IS_REGISTER,
3193 + Operand_ars_entry_encode, Operand_ars_entry_decode,
3195 + { "immrx4", 14, -1, 0,
3197 + Operand_immrx4_encode, Operand_immrx4_decode,
3199 + { "lsi4x4", 14, -1, 0,
3201 + Operand_lsi4x4_encode, Operand_lsi4x4_decode,
3203 + { "simm7", 34, -1, 0,
3205 + Operand_simm7_encode, Operand_simm7_decode,
3207 + { "uimm6", 33, -1, 0,
3208 + XTENSA_OPERAND_IS_PCRELATIVE,
3209 + Operand_uimm6_encode, Operand_uimm6_decode,
3210 + Operand_uimm6_ator, Operand_uimm6_rtoa },
3211 + { "ai4const", 0, -1, 0,
3213 + Operand_ai4const_encode, Operand_ai4const_decode,
3215 + { "b4const", 14, -1, 0,
3217 + Operand_b4const_encode, Operand_b4const_decode,
3219 + { "b4constu", 14, -1, 0,
3221 + Operand_b4constu_encode, Operand_b4constu_decode,
3223 + { "uimm8", 4, -1, 0,
3225 + Operand_uimm8_encode, Operand_uimm8_decode,
3227 + { "uimm8x2", 4, -1, 0,
3229 + Operand_uimm8x2_encode, Operand_uimm8x2_decode,
3231 + { "uimm8x4", 4, -1, 0,
3233 + Operand_uimm8x4_encode, Operand_uimm8x4_decode,
3235 + { "uimm4x16", 13, -1, 0,
3237 + Operand_uimm4x16_encode, Operand_uimm4x16_decode,
3239 + { "simm8", 4, -1, 0,
3241 + Operand_simm8_encode, Operand_simm8_decode,
3243 + { "simm8x256", 4, -1, 0,
3245 + Operand_simm8x256_encode, Operand_simm8x256_decode,
3247 + { "simm12b", 6, -1, 0,
3249 + Operand_simm12b_encode, Operand_simm12b_decode,
3251 + { "msalp32", 18, -1, 0,
3253 + Operand_msalp32_encode, Operand_msalp32_decode,
3255 + { "op2p1", 13, -1, 0,
3257 + Operand_op2p1_encode, Operand_op2p1_decode,
3259 + { "label8", 4, -1, 0,
3260 + XTENSA_OPERAND_IS_PCRELATIVE,
3261 + Operand_label8_encode, Operand_label8_decode,
3262 + Operand_label8_ator, Operand_label8_rtoa },
3263 + { "ulabel8", 4, -1, 0,
3264 + XTENSA_OPERAND_IS_PCRELATIVE,
3265 + Operand_ulabel8_encode, Operand_ulabel8_decode,
3266 + Operand_ulabel8_ator, Operand_ulabel8_rtoa },
3267 + { "label12", 3, -1, 0,
3268 + XTENSA_OPERAND_IS_PCRELATIVE,
3269 + Operand_label12_encode, Operand_label12_decode,
3270 + Operand_label12_ator, Operand_label12_rtoa },
3271 + { "soffset", 10, -1, 0,
3272 + XTENSA_OPERAND_IS_PCRELATIVE,
3273 + Operand_soffset_encode, Operand_soffset_decode,
3274 + Operand_soffset_ator, Operand_soffset_rtoa },
3275 + { "uimm16x4", 7, -1, 0,
3276 + XTENSA_OPERAND_IS_PCRELATIVE,
3277 + Operand_uimm16x4_encode, Operand_uimm16x4_decode,
3278 + Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
3279 + { "immt", 0, -1, 0,
3281 + Operand_immt_encode, Operand_immt_decode,
3283 + { "imms", 5, -1, 0,
3285 + Operand_imms_encode, Operand_imms_decode,
3287 + { "tp7", 0, -1, 0,
3289 + Operand_tp7_encode, Operand_tp7_decode,
3291 + { "xt_wbr15_label", 35, -1, 0,
3292 + XTENSA_OPERAND_IS_PCRELATIVE,
3293 + Operand_xt_wbr15_label_encode, Operand_xt_wbr15_label_decode,
3294 + Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa },
3295 + { "xt_wbr18_label", 36, -1, 0,
3296 + XTENSA_OPERAND_IS_PCRELATIVE,
3297 + Operand_xt_wbr18_label_encode, Operand_xt_wbr18_label_decode,
3298 + Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa },
3299 + { "t", 0, -1, 0, 0, 0, 0, 0, 0 },
3300 + { "bbi4", 1, -1, 0, 0, 0, 0, 0, 0 },
3301 + { "bbi", 2, -1, 0, 0, 0, 0, 0, 0 },
3302 + { "imm12", 3, -1, 0, 0, 0, 0, 0, 0 },
3303 + { "imm8", 4, -1, 0, 0, 0, 0, 0, 0 },
3304 + { "s", 5, -1, 0, 0, 0, 0, 0, 0 },
3305 + { "imm12b", 6, -1, 0, 0, 0, 0, 0, 0 },
3306 + { "imm16", 7, -1, 0, 0, 0, 0, 0, 0 },
3307 + { "m", 8, -1, 0, 0, 0, 0, 0, 0 },
3308 + { "n", 9, -1, 0, 0, 0, 0, 0, 0 },
3309 + { "offset", 10, -1, 0, 0, 0, 0, 0, 0 },
3310 + { "op0", 11, -1, 0, 0, 0, 0, 0, 0 },
3311 + { "op1", 12, -1, 0, 0, 0, 0, 0, 0 },
3312 + { "op2", 13, -1, 0, 0, 0, 0, 0, 0 },
3313 + { "r", 14, -1, 0, 0, 0, 0, 0, 0 },
3314 + { "sa4", 15, -1, 0, 0, 0, 0, 0, 0 },
3315 + { "sae4", 16, -1, 0, 0, 0, 0, 0, 0 },
3316 + { "sae", 17, -1, 0, 0, 0, 0, 0, 0 },
3317 + { "sal", 18, -1, 0, 0, 0, 0, 0, 0 },
3318 + { "sargt", 19, -1, 0, 0, 0, 0, 0, 0 },
3319 + { "sas4", 20, -1, 0, 0, 0, 0, 0, 0 },
3320 + { "sas", 21, -1, 0, 0, 0, 0, 0, 0 },
3321 + { "sr", 22, -1, 0, 0, 0, 0, 0, 0 },
3322 + { "st", 23, -1, 0, 0, 0, 0, 0, 0 },
3323 + { "thi3", 24, -1, 0, 0, 0, 0, 0, 0 },
3324 + { "imm4", 25, -1, 0, 0, 0, 0, 0, 0 },
3325 + { "mn", 26, -1, 0, 0, 0, 0, 0, 0 },
3326 + { "i", 27, -1, 0, 0, 0, 0, 0, 0 },
3327 + { "imm6lo", 28, -1, 0, 0, 0, 0, 0, 0 },
3328 + { "imm6hi", 29, -1, 0, 0, 0, 0, 0, 0 },
3329 + { "imm7lo", 30, -1, 0, 0, 0, 0, 0, 0 },
3330 + { "imm7hi", 31, -1, 0, 0, 0, 0, 0, 0 },
3331 + { "z", 32, -1, 0, 0, 0, 0, 0, 0 },
3332 + { "imm6", 33, -1, 0, 0, 0, 0, 0, 0 },
3333 + { "imm7", 34, -1, 0, 0, 0, 0, 0, 0 },
3334 + { "xt_wbr15_imm", 35, -1, 0, 0, 0, 0, 0, 0 },
3335 + { "xt_wbr18_imm", 36, -1, 0, 0, 0, 0, 0, 0 }
3339 -Field_r2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
3342 - tie_t = (val << 29) >> 29;
3343 - insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
3346 +/* Iclass table. */
3349 -Field_r2_Slot_inst16b_get (const xtensa_insnbuf insn)
3351 - unsigned tie_t = 0;
3352 - tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
3355 +static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
3356 + { { STATE_PSEXCM }, 'o' },
3357 + { { STATE_EPC1 }, 'i' }
3361 -Field_r2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
3364 - tie_t = (val << 29) >> 29;
3365 - insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
3367 +static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
3368 + { { STATE_DEPC }, 'i' }
3372 -Field_t4_Slot_inst_get (const xtensa_insnbuf insn)
3374 - unsigned tie_t = 0;
3375 - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
3378 +static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
3379 + { { 0 /* soffsetx4 */ }, 'i' },
3380 + { { 10 /* ar12 */ }, 'o' }
3384 -Field_t4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
3387 - tie_t = (val << 30) >> 30;
3388 - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
3390 +static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
3391 + { { STATE_PSCALLINC }, 'o' }
3395 -Field_t4_Slot_inst16a_get (const xtensa_insnbuf insn)
3397 - unsigned tie_t = 0;
3398 - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
3401 +static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
3402 + { { 0 /* soffsetx4 */ }, 'i' },
3403 + { { 9 /* ar8 */ }, 'o' }
3407 -Field_t4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
3410 - tie_t = (val << 30) >> 30;
3411 - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
3413 +static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
3414 + { { STATE_PSCALLINC }, 'o' }
3418 -Field_t4_Slot_inst16b_get (const xtensa_insnbuf insn)
3420 - unsigned tie_t = 0;
3421 - tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
3424 +static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
3425 + { { 0 /* soffsetx4 */ }, 'i' },
3426 + { { 8 /* ar4 */ }, 'o' }
3430 -Field_t4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
3433 - tie_t = (val << 30) >> 30;
3434 - insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
3436 +static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
3437 + { { STATE_PSCALLINC }, 'o' }
3441 -Field_s4_Slot_inst_get (const xtensa_insnbuf insn)
3443 - unsigned tie_t = 0;
3444 - tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
3447 +static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
3448 + { { 4 /* ars */ }, 'i' },
3449 + { { 10 /* ar12 */ }, 'o' }
3453 -Field_s4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
3456 - tie_t = (val << 30) >> 30;
3457 - insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
3459 +static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
3460 + { { STATE_PSCALLINC }, 'o' }
3464 -Field_s4_Slot_inst16a_get (const xtensa_insnbuf insn)
3466 - unsigned tie_t = 0;
3467 - tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
3470 +static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
3471 + { { 4 /* ars */ }, 'i' },
3472 + { { 9 /* ar8 */ }, 'o' }
3476 -Field_s4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
3479 - tie_t = (val << 30) >> 30;
3480 - insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
3482 +static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
3483 + { { STATE_PSCALLINC }, 'o' }
3487 -Field_s4_Slot_inst16b_get (const xtensa_insnbuf insn)
3489 - unsigned tie_t = 0;
3490 - tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
3493 +static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
3494 + { { 4 /* ars */ }, 'i' },
3495 + { { 8 /* ar4 */ }, 'o' }
3499 -Field_s4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
3502 - tie_t = (val << 30) >> 30;
3503 - insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
3505 +static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
3506 + { { STATE_PSCALLINC }, 'o' }
3510 -Field_r4_Slot_inst_get (const xtensa_insnbuf insn)
3512 - unsigned tie_t = 0;
3513 - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3516 +static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
3517 + { { 11 /* ars_entry */ }, 's' },
3518 + { { 4 /* ars */ }, 'i' },
3519 + { { 1 /* uimm12x8 */ }, 'i' }
3523 -Field_r4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
3526 - tie_t = (val << 30) >> 30;
3527 - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3529 +static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
3530 + { { STATE_PSCALLINC }, 'i' },
3531 + { { STATE_PSEXCM }, 'i' },
3532 + { { STATE_PSWOE }, 'i' },
3533 + { { STATE_WindowBase }, 'm' },
3534 + { { STATE_WindowStart }, 'm' }
3538 -Field_r4_Slot_inst16a_get (const xtensa_insnbuf insn)
3540 - unsigned tie_t = 0;
3541 - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3544 +static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
3545 + { { 6 /* art */ }, 'o' },
3546 + { { 4 /* ars */ }, 'i' }
3550 -Field_r4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
3553 - tie_t = (val << 30) >> 30;
3554 - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3556 +static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
3557 + { { STATE_WindowBase }, 'i' },
3558 + { { STATE_WindowStart }, 'i' }
3562 -Field_r4_Slot_inst16b_get (const xtensa_insnbuf insn)
3564 - unsigned tie_t = 0;
3565 - tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
3568 +static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
3569 + { { 2 /* simm4 */ }, 'i' }
3573 -Field_r4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
3576 - tie_t = (val << 30) >> 30;
3577 - insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
3579 +static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
3580 + { { STATE_WindowBase }, 'm' }
3584 -Field_t8_Slot_inst_get (const xtensa_insnbuf insn)
3586 - unsigned tie_t = 0;
3587 - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
3590 +static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
3591 + { { 5 /* *ars_invisible */ }, 'i' }
3595 -Field_t8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
3598 - tie_t = (val << 31) >> 31;
3599 - insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
3601 +static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
3602 + { { STATE_WindowBase }, 'm' },
3603 + { { STATE_WindowStart }, 'm' },
3604 + { { STATE_PSEXCM }, 'i' },
3605 + { { STATE_PSWOE }, 'i' }
3609 -Field_t8_Slot_inst16a_get (const xtensa_insnbuf insn)
3611 - unsigned tie_t = 0;
3612 - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
3615 +static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
3616 + { { STATE_EPC1 }, 'i' },
3617 + { { STATE_PSEXCM }, 'o' },
3618 + { { STATE_WindowBase }, 'm' },
3619 + { { STATE_WindowStart }, 'm' },
3620 + { { STATE_PSOWB }, 'i' }
3624 -Field_t8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
3627 - tie_t = (val << 31) >> 31;
3628 - insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
3630 +static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
3631 + { { 6 /* art */ }, 'o' },
3632 + { { 4 /* ars */ }, 'i' },
3633 + { { 12 /* immrx4 */ }, 'i' }
3637 -Field_t8_Slot_inst16b_get (const xtensa_insnbuf insn)
3639 - unsigned tie_t = 0;
3640 - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
3643 +static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
3644 + { { 6 /* art */ }, 'i' },
3645 + { { 4 /* ars */ }, 'i' },
3646 + { { 12 /* immrx4 */ }, 'i' }
3650 -Field_t8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
3653 - tie_t = (val << 31) >> 31;
3654 - insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
3656 +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
3657 + { { 6 /* art */ }, 'o' }
3661 -Field_s8_Slot_inst_get (const xtensa_insnbuf insn)
3663 - unsigned tie_t = 0;
3664 - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
3667 +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
3668 + { { STATE_WindowBase }, 'i' }
3672 -Field_s8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
3675 - tie_t = (val << 31) >> 31;
3676 - insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
3678 +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
3679 + { { 6 /* art */ }, 'i' }
3683 -Field_s8_Slot_inst16a_get (const xtensa_insnbuf insn)
3685 - unsigned tie_t = 0;
3686 - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
3691 -Field_s8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
3694 - tie_t = (val << 31) >> 31;
3695 - insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
3697 +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
3698 + { { STATE_WindowBase }, 'o' }
3702 -Field_s8_Slot_inst16b_get (const xtensa_insnbuf insn)
3704 - unsigned tie_t = 0;
3705 - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
3708 +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
3709 + { { 6 /* art */ }, 'm' }
3713 -Field_s8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
3716 - tie_t = (val << 31) >> 31;
3717 - insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
3719 +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
3720 + { { STATE_WindowBase }, 'm' }
3724 -Field_r8_Slot_inst_get (const xtensa_insnbuf insn)
3726 - unsigned tie_t = 0;
3727 - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
3730 +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
3731 + { { 6 /* art */ }, 'o' }
3735 -Field_r8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
3738 - tie_t = (val << 31) >> 31;
3739 - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
3741 +static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
3742 + { { STATE_WindowStart }, 'i' }
3746 -Field_r8_Slot_inst16a_get (const xtensa_insnbuf insn)
3748 - unsigned tie_t = 0;
3749 - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
3752 +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
3753 + { { 6 /* art */ }, 'i' }
3757 -Field_r8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
3760 - tie_t = (val << 31) >> 31;
3761 - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
3763 +static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
3764 + { { STATE_WindowStart }, 'o' }
3768 -Field_r8_Slot_inst16b_get (const xtensa_insnbuf insn)
3770 - unsigned tie_t = 0;
3771 - tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
3774 +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
3775 + { { 6 /* art */ }, 'm' }
3779 -Field_r8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
3782 - tie_t = (val << 31) >> 31;
3783 - insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
3785 +static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
3786 + { { STATE_WindowStart }, 'm' }
3790 -Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn)
3792 - unsigned tie_t = 0;
3793 - tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17);
3796 +static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
3797 + { { 3 /* arr */ }, 'o' },
3798 + { { 4 /* ars */ }, 'i' },
3799 + { { 6 /* art */ }, 'i' }
3803 -Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
3806 - tie_t = (val << 17) >> 17;
3807 - insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9);
3809 +static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
3810 + { { 3 /* arr */ }, 'o' },
3811 + { { 4 /* ars */ }, 'i' },
3812 + { { 16 /* ai4const */ }, 'i' }
3816 -Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn)
3818 - unsigned tie_t = 0;
3819 - tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
3822 +static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
3823 + { { 4 /* ars */ }, 'i' },
3824 + { { 15 /* uimm6 */ }, 'i' }
3828 -Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
3831 - tie_t = (val << 14) >> 14;
3832 - insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
3834 +static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
3835 + { { 6 /* art */ }, 'o' },
3836 + { { 4 /* ars */ }, 'i' },
3837 + { { 13 /* lsi4x4 */ }, 'i' }
3841 -Field_xt_wbr18_imm_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3843 - unsigned tie_t = 0;
3844 - tie_t = (tie_t << 18) | ((insn[0] << 6) >> 14);
3847 +static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
3848 + { { 6 /* art */ }, 'o' },
3849 + { { 4 /* ars */ }, 'i' }
3853 -Field_xt_wbr18_imm_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3856 - tie_t = (val << 14) >> 14;
3857 - insn[0] = (insn[0] & ~0x3ffff00) | (tie_t << 8);
3859 +static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
3860 + { { 4 /* ars */ }, 'o' },
3861 + { { 14 /* simm7 */ }, 'i' }
3865 -Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
3867 - unsigned tie_t = 0;
3868 - tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
3871 +static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
3872 + { { 5 /* *ars_invisible */ }, 'i' }
3876 -Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
3879 - tie_t = (val << 28) >> 28;
3880 - insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
3882 +static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
3883 + { { 6 /* art */ }, 'i' },
3884 + { { 4 /* ars */ }, 'i' },
3885 + { { 13 /* lsi4x4 */ }, 'i' }
3889 -Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
3891 - unsigned tie_t = 0;
3892 - tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
3895 +static xtensa_arg_internal Iclass_rur_threadptr_args[] = {
3896 + { { 3 /* arr */ }, 'o' }
3900 -Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
3903 - tie_t = (val << 29) >> 29;
3904 - insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
3906 +static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = {
3907 + { { STATE_THREADPTR }, 'i' }
3911 -Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
3913 - unsigned tie_t = 0;
3914 - tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
3917 +static xtensa_arg_internal Iclass_wur_threadptr_args[] = {
3918 + { { 6 /* art */ }, 'i' }
3922 -Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
3925 - tie_t = (val << 29) >> 29;
3926 - insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
3928 +static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = {
3929 + { { STATE_THREADPTR }, 'o' }
3933 -Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
3935 - unsigned tie_t = 0;
3936 - tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29);
3939 +static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
3940 + { { 6 /* art */ }, 'o' },
3941 + { { 4 /* ars */ }, 'i' },
3942 + { { 23 /* simm8 */ }, 'i' }
3946 -Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
3949 - tie_t = (val << 29) >> 29;
3950 - insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
3952 +static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
3953 + { { 6 /* art */ }, 'o' },
3954 + { { 4 /* ars */ }, 'i' },
3955 + { { 24 /* simm8x256 */ }, 'i' }
3959 -Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
3961 - unsigned tie_t = 0;
3962 - tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29);
3965 +static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
3966 + { { 3 /* arr */ }, 'o' },
3967 + { { 4 /* ars */ }, 'i' },
3968 + { { 6 /* art */ }, 'i' }
3972 -Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
3975 - tie_t = (val << 29) >> 29;
3976 - insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
3978 +static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
3979 + { { 3 /* arr */ }, 'o' },
3980 + { { 4 /* ars */ }, 'i' },
3981 + { { 6 /* art */ }, 'i' }
3985 -Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
3987 - unsigned tie_t = 0;
3988 - tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
3989 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
3992 +static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
3993 + { { 4 /* ars */ }, 'i' },
3994 + { { 17 /* b4const */ }, 'i' },
3995 + { { 28 /* label8 */ }, 'i' }
3999 -Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
4002 - tie_t = (val << 28) >> 28;
4003 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
4004 - tie_t = (val << 24) >> 28;
4005 - insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
4007 +static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
4008 + { { 4 /* ars */ }, 'i' },
4009 + { { 40 /* bbi */ }, 'i' },
4010 + { { 28 /* label8 */ }, 'i' }
4014 -Field_op0_s4_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4016 - unsigned tie_t = 0;
4017 - tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30);
4020 +static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
4021 + { { 4 /* ars */ }, 'i' },
4022 + { { 18 /* b4constu */ }, 'i' },
4023 + { { 28 /* label8 */ }, 'i' }
4027 -Field_op0_s4_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4030 - tie_t = (val << 30) >> 30;
4031 - insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18);
4033 +static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
4034 + { { 4 /* ars */ }, 'i' },
4035 + { { 6 /* art */ }, 'i' },
4036 + { { 28 /* label8 */ }, 'i' }
4040 -Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4042 - unsigned tie_t = 0;
4043 - tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
4046 +static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
4047 + { { 4 /* ars */ }, 'i' },
4048 + { { 30 /* label12 */ }, 'i' }
4052 -Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4055 - tie_t = (val << 28) >> 28;
4056 - insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
4058 +static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
4059 + { { 0 /* soffsetx4 */ }, 'i' },
4060 + { { 7 /* ar0 */ }, 'o' }
4064 -Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4066 - unsigned tie_t = 0;
4067 - tie_t = (tie_t << 1) | ((insn[0] << 14) >> 31);
4070 +static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
4071 + { { 4 /* ars */ }, 'i' },
4072 + { { 7 /* ar0 */ }, 'o' }
4076 -Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4079 - tie_t = (val << 31) >> 31;
4080 - insn[0] = (insn[0] & ~0x20000) | (tie_t << 17);
4082 +static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
4083 + { { 3 /* arr */ }, 'o' },
4084 + { { 6 /* art */ }, 'i' },
4085 + { { 55 /* sae */ }, 'i' },
4086 + { { 27 /* op2p1 */ }, 'i' }
4090 -Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4092 - unsigned tie_t = 0;
4093 - tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30);
4096 +static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
4097 + { { 31 /* soffset */ }, 'i' }
4101 -Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4104 - tie_t = (val << 30) >> 30;
4105 - insn[0] = (insn[0] & ~0x30000) | (tie_t << 16);
4107 +static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
4108 + { { 4 /* ars */ }, 'i' }
4112 -Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4114 - unsigned tie_t = 0;
4115 - tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27);
4118 +static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
4119 + { { 6 /* art */ }, 'o' },
4120 + { { 4 /* ars */ }, 'i' },
4121 + { { 20 /* uimm8x2 */ }, 'i' }
4125 -Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4128 - tie_t = (val << 27) >> 27;
4129 - insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13);
4131 +static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
4132 + { { 6 /* art */ }, 'o' },
4133 + { { 4 /* ars */ }, 'i' },
4134 + { { 20 /* uimm8x2 */ }, 'i' }
4138 -Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4140 - unsigned tie_t = 0;
4141 - tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26);
4144 +static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
4145 + { { 6 /* art */ }, 'o' },
4146 + { { 4 /* ars */ }, 'i' },
4147 + { { 21 /* uimm8x4 */ }, 'i' }
4151 -Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4154 - tie_t = (val << 26) >> 26;
4155 - insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
4157 +static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
4158 + { { 6 /* art */ }, 'o' },
4159 + { { 32 /* uimm16x4 */ }, 'i' }
4163 -Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4165 - unsigned tie_t = 0;
4166 - tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26);
4167 - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
4170 +static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = {
4171 + { { STATE_LITBADDR }, 'i' },
4172 + { { STATE_LITBEN }, 'i' }
4176 -Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4179 - tie_t = (val << 29) >> 29;
4180 - insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
4181 - tie_t = (val << 23) >> 26;
4182 - insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
4184 +static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
4185 + { { 6 /* art */ }, 'o' },
4186 + { { 4 /* ars */ }, 'i' },
4187 + { { 19 /* uimm8 */ }, 'i' }
4191 -Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4193 - unsigned tie_t = 0;
4194 - tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26);
4195 - tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
4198 +static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = {
4199 + { { 4 /* ars */ }, 'i' },
4200 + { { 29 /* ulabel8 */ }, 'i' }
4204 -Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4207 - tie_t = (val << 29) >> 29;
4208 - insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
4209 - tie_t = (val << 23) >> 26;
4210 - insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
4212 +static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = {
4213 + { { STATE_LBEG }, 'o' },
4214 + { { STATE_LEND }, 'o' },
4215 + { { STATE_LCOUNT }, 'o' }
4219 -Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4221 - unsigned tie_t = 0;
4222 - tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26);
4223 - tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30);
4226 +static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = {
4227 + { { 4 /* ars */ }, 'i' },
4228 + { { 29 /* ulabel8 */ }, 'i' }
4232 -Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4235 - tie_t = (val << 30) >> 30;
4236 - insn[0] = (insn[0] & ~0x60) | (tie_t << 5);
4237 - tie_t = (val << 24) >> 26;
4238 - insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
4240 +static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = {
4241 + { { STATE_LBEG }, 'o' },
4242 + { { STATE_LEND }, 'o' },
4243 + { { STATE_LCOUNT }, 'o' }
4247 -Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4249 - unsigned tie_t = 0;
4250 - tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26);
4251 - tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
4254 +static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
4255 + { { 6 /* art */ }, 'o' },
4256 + { { 25 /* simm12b */ }, 'i' }
4260 -Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4263 - tie_t = (val << 31) >> 31;
4264 - insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
4265 - tie_t = (val << 25) >> 26;
4266 - insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
4268 +static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
4269 + { { 3 /* arr */ }, 'm' },
4270 + { { 4 /* ars */ }, 'i' },
4271 + { { 6 /* art */ }, 'i' }
4275 -Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4277 - unsigned tie_t = 0;
4278 - tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26);
4279 - tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
4282 +static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
4283 + { { 3 /* arr */ }, 'o' },
4284 + { { 6 /* art */ }, 'i' }
4288 -Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4291 - tie_t = (val << 30) >> 30;
4292 - insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
4293 - tie_t = (val << 24) >> 26;
4294 - insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
4296 +static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
4297 + { { 5 /* *ars_invisible */ }, 'i' }
4301 -Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4303 - unsigned tie_t = 0;
4304 - tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26);
4305 - tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
4308 +static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
4309 + { { 6 /* art */ }, 'i' },
4310 + { { 4 /* ars */ }, 'i' },
4311 + { { 20 /* uimm8x2 */ }, 'i' }
4315 -Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4318 - tie_t = (val << 30) >> 30;
4319 - insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
4320 - tie_t = (val << 24) >> 26;
4321 - insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
4323 +static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
4324 + { { 6 /* art */ }, 'i' },
4325 + { { 4 /* ars */ }, 'i' },
4326 + { { 21 /* uimm8x4 */ }, 'i' }
4330 -Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4332 - unsigned tie_t = 0;
4333 - tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26);
4334 - tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31);
4337 +static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
4338 + { { 6 /* art */ }, 'i' },
4339 + { { 4 /* ars */ }, 'i' },
4340 + { { 19 /* uimm8 */ }, 'i' }
4344 -Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4347 - tie_t = (val << 31) >> 31;
4348 - insn[0] = (insn[0] & ~0x200) | (tie_t << 9);
4349 - tie_t = (val << 25) >> 26;
4350 - insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
4352 +static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
4353 + { { 4 /* ars */ }, 'i' }
4357 -Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4359 - unsigned tie_t = 0;
4360 - tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29);
4363 +static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
4364 + { { STATE_SAR }, 'o' }
4368 -Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4371 - tie_t = (val << 29) >> 29;
4372 - insn[0] = (insn[0] & ~0x38000) | (tie_t << 15);
4374 +static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
4375 + { { 59 /* sas */ }, 'i' }
4379 -Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4381 - unsigned tie_t = 0;
4382 - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
4385 +static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
4386 + { { STATE_SAR }, 'o' }
4390 -Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4393 - tie_t = (val << 31) >> 31;
4394 - insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
4396 +static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
4397 + { { 3 /* arr */ }, 'o' },
4398 + { { 4 /* ars */ }, 'i' }
4402 -Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4404 - unsigned tie_t = 0;
4405 - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
4406 - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4409 +static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
4410 + { { STATE_SAR }, 'i' }
4414 -Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4417 - tie_t = (val << 28) >> 28;
4418 - insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4419 - tie_t = (val << 27) >> 31;
4420 - insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
4422 +static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
4423 + { { 3 /* arr */ }, 'o' },
4424 + { { 4 /* ars */ }, 'i' },
4425 + { { 6 /* art */ }, 'i' }
4429 -Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4431 - unsigned tie_t = 0;
4432 - tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
4435 +static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
4436 + { { STATE_SAR }, 'i' }
4440 -Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4443 - tie_t = (val << 30) >> 30;
4444 - insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
4446 +static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
4447 + { { 3 /* arr */ }, 'o' },
4448 + { { 6 /* art */ }, 'i' }
4452 -Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4454 - unsigned tie_t = 0;
4455 - tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
4456 - tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26);
4459 +static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
4460 + { { STATE_SAR }, 'i' }
4464 -Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4467 - tie_t = (val << 26) >> 26;
4468 - insn[0] = (insn[0] & ~0x3f) | (tie_t << 0);
4469 - tie_t = (val << 21) >> 27;
4470 - insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
4472 +static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
4473 + { { 3 /* arr */ }, 'o' },
4474 + { { 4 /* ars */ }, 'i' },
4475 + { { 26 /* msalp32 */ }, 'i' }
4479 -Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4481 - unsigned tie_t = 0;
4482 - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
4483 - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4486 +static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
4487 + { { 3 /* arr */ }, 'o' },
4488 + { { 6 /* art */ }, 'i' },
4489 + { { 57 /* sargt */ }, 'i' }
4493 -Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4496 - tie_t = (val << 28) >> 28;
4497 - insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4498 - tie_t = (val << 27) >> 31;
4499 - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
4501 +static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
4502 + { { 3 /* arr */ }, 'o' },
4503 + { { 6 /* art */ }, 'i' },
4504 + { { 43 /* s */ }, 'i' }
4508 -Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4510 - unsigned tie_t = 0;
4511 - tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
4512 - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
4515 +static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
4516 + { { STATE_XTSYNC }, 'i' }
4520 -Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4523 - tie_t = (val << 31) >> 31;
4524 - insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
4525 - tie_t = (val << 29) >> 30;
4526 - insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
4528 +static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
4529 + { { 6 /* art */ }, 'o' },
4530 + { { 43 /* s */ }, 'i' }
4534 -Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4536 - unsigned tie_t = 0;
4537 - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
4538 - tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27);
4541 +static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
4542 + { { STATE_PSWOE }, 'i' },
4543 + { { STATE_PSCALLINC }, 'i' },
4544 + { { STATE_PSOWB }, 'i' },
4545 + { { STATE_PSUM }, 'i' },
4546 + { { STATE_PSEXCM }, 'i' },
4547 + { { STATE_PSINTLEVEL }, 'm' }
4551 -Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4554 - tie_t = (val << 27) >> 27;
4555 - insn[0] = (insn[0] & ~0x1f) | (tie_t << 0);
4556 - tie_t = (val << 26) >> 31;
4557 - insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
4559 +static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = {
4560 + { { 6 /* art */ }, 'o' }
4564 -Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
4566 - unsigned tie_t = 0;
4567 - tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29);
4570 +static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = {
4571 + { { STATE_LEND }, 'i' }
4575 -Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
4578 - tie_t = (val << 29) >> 29;
4579 - insn[0] = (insn[0] & ~0x7000) | (tie_t << 12);
4581 +static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = {
4582 + { { 6 /* art */ }, 'i' }
4586 -Field_op0_s5_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
4588 - unsigned tie_t = 0;
4589 - tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
4592 +static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = {
4593 + { { STATE_LEND }, 'o' }
4597 -Field_op0_s5_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
4600 - tie_t = (val << 29) >> 29;
4601 - insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
4603 +static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = {
4604 + { { 6 /* art */ }, 'm' }
4608 -Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
4610 - unsigned tie_t = 0;
4611 - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
4614 +static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = {
4615 + { { STATE_LEND }, 'm' }
4619 -Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
4622 - tie_t = (val << 31) >> 31;
4623 - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
4625 +static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = {
4626 + { { 6 /* art */ }, 'o' }
4630 -Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
4632 - unsigned tie_t = 0;
4633 - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
4634 - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
4637 +static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = {
4638 + { { STATE_LCOUNT }, 'i' }
4642 -Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
4645 - tie_t = (val << 31) >> 31;
4646 - insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
4647 - tie_t = (val << 30) >> 31;
4648 - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
4650 +static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = {
4651 + { { 6 /* art */ }, 'i' }
4655 -Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
4657 - unsigned tie_t = 0;
4658 - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
4659 - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
4660 - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
4663 +static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = {
4664 + { { STATE_XTSYNC }, 'o' },
4665 + { { STATE_LCOUNT }, 'o' }
4669 -Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
4672 - tie_t = (val << 31) >> 31;
4673 - insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
4674 - tie_t = (val << 30) >> 31;
4675 - insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
4676 - tie_t = (val << 29) >> 31;
4677 - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
4679 +static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = {
4680 + { { 6 /* art */ }, 'm' }
4684 -Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
4686 - unsigned tie_t = 0;
4687 - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
4688 - tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
4689 - tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
4692 +static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = {
4693 + { { STATE_XTSYNC }, 'o' },
4694 + { { STATE_LCOUNT }, 'm' }
4698 -Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
4701 - tie_t = (val << 31) >> 31;
4702 - insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
4703 - tie_t = (val << 30) >> 31;
4704 - insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
4705 - tie_t = (val << 29) >> 31;
4706 - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
4708 +static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = {
4709 + { { 6 /* art */ }, 'o' }
4713 -Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
4715 - unsigned tie_t = 0;
4716 - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
4717 - tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
4720 +static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = {
4721 + { { STATE_LBEG }, 'i' }
4725 -Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
4728 - tie_t = (val << 29) >> 29;
4729 - insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
4730 - tie_t = (val << 28) >> 31;
4731 - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
4733 +static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = {
4734 + { { 6 /* art */ }, 'i' }
4738 -Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
4740 - unsigned tie_t = 0;
4741 - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
4742 - tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
4745 +static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = {
4746 + { { STATE_LBEG }, 'o' }
4750 -Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
4753 - tie_t = (val << 29) >> 29;
4754 - insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
4755 - tie_t = (val << 28) >> 31;
4756 - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
4758 +static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = {
4759 + { { 6 /* art */ }, 'm' }
4763 -Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
4765 - unsigned tie_t = 0;
4766 - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
4767 - tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
4770 +static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = {
4771 + { { STATE_LBEG }, 'm' }
4775 -Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
4778 - tie_t = (val << 30) >> 30;
4779 - insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
4780 - tie_t = (val << 29) >> 31;
4781 - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
4783 +static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
4784 + { { 6 /* art */ }, 'o' }
4788 -Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
4790 - unsigned tie_t = 0;
4791 - tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
4792 - tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31);
4795 +static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
4796 + { { STATE_SAR }, 'i' }
4800 -Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
4803 - tie_t = (val << 31) >> 31;
4804 - insn[0] = (insn[0] & ~0x400) | (tie_t << 10);
4805 - tie_t = (val << 30) >> 31;
4806 - insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
4808 +static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
4809 + { { 6 /* art */ }, 'i' }
4813 -Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
4815 - unsigned tie_t = 0;
4816 - tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30);
4819 +static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
4820 + { { STATE_SAR }, 'o' },
4821 + { { STATE_XTSYNC }, 'o' }
4825 -Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
4828 - tie_t = (val << 30) >> 30;
4829 - insn[0] = (insn[0] & ~0x60) | (tie_t << 5);
4831 +static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
4832 + { { 6 /* art */ }, 'm' }
4836 -Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
4838 - unsigned tie_t = 0;
4839 - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
4842 +static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
4843 + { { STATE_SAR }, 'm' }
4847 -Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
4850 - tie_t = (val << 31) >> 31;
4851 - insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
4853 +static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = {
4854 + { { 6 /* art */ }, 'o' }
4858 -Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
4860 - unsigned tie_t = 0;
4861 - tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
4862 - tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30);
4863 - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4866 +static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = {
4867 + { { STATE_LITBADDR }, 'i' },
4868 + { { STATE_LITBEN }, 'i' }
4872 -Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
4875 - tie_t = (val << 28) >> 28;
4876 - insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4877 - tie_t = (val << 26) >> 30;
4878 - insn[0] = (insn[0] & ~0x60) | (tie_t << 5);
4879 - tie_t = (val << 22) >> 28;
4880 - insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
4882 +static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = {
4883 + { { 6 /* art */ }, 'i' }
4887 -Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
4889 - unsigned tie_t = 0;
4890 - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
4891 - tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
4894 +static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = {
4895 + { { STATE_LITBADDR }, 'o' },
4896 + { { STATE_LITBEN }, 'o' }
4900 -Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
4903 - tie_t = (val << 31) >> 31;
4904 - insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
4905 - tie_t = (val << 30) >> 31;
4906 - insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
4908 +static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = {
4909 + { { 6 /* art */ }, 'm' }
4913 -Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
4915 - unsigned tie_t = 0;
4916 - tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
4917 - tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
4920 +static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = {
4921 + { { STATE_LITBADDR }, 'm' },
4922 + { { STATE_LITBEN }, 'm' }
4926 -Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
4929 - tie_t = (val << 30) >> 30;
4930 - insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
4931 - tie_t = (val << 29) >> 31;
4932 - insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
4934 +static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = {
4935 + { { 6 /* art */ }, 'o' }
4939 -Field_op0_s6_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
4941 - unsigned tie_t = 0;
4942 - tie_t = (tie_t << 5) | ((insn[0] << 0) >> 27);
4945 +static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = {
4946 + { { 6 /* art */ }, 'o' }
4950 -Field_op0_s6_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
4953 - tie_t = (val << 27) >> 27;
4954 - insn[0] = (insn[0] & ~0xf8000000) | (tie_t << 27);
4956 +static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
4957 + { { 6 /* art */ }, 'o' }
4961 -Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
4963 - unsigned tie_t = 0;
4964 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
4965 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
4966 - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
4969 +static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
4970 + { { STATE_PSWOE }, 'i' },
4971 + { { STATE_PSCALLINC }, 'i' },
4972 + { { STATE_PSOWB }, 'i' },
4973 + { { STATE_PSUM }, 'i' },
4974 + { { STATE_PSEXCM }, 'i' },
4975 + { { STATE_PSINTLEVEL }, 'i' }
4979 -Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
4982 - tie_t = (val << 28) >> 28;
4983 - insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
4984 - tie_t = (val << 27) >> 31;
4985 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
4986 - tie_t = (val << 24) >> 29;
4987 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
4989 +static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
4990 + { { 6 /* art */ }, 'i' }
4994 -Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
4996 - unsigned tie_t = 0;
4997 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5000 +static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
5001 + { { STATE_PSWOE }, 'o' },
5002 + { { STATE_PSCALLINC }, 'o' },
5003 + { { STATE_PSOWB }, 'o' },
5004 + { { STATE_PSUM }, 'o' },
5005 + { { STATE_PSEXCM }, 'o' },
5006 + { { STATE_PSINTLEVEL }, 'o' }
5010 -Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5013 - tie_t = (val << 29) >> 29;
5014 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5016 +static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
5017 + { { 6 /* art */ }, 'm' }
5021 -Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5023 - unsigned tie_t = 0;
5024 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5025 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5026 - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
5029 +static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
5030 + { { STATE_PSWOE }, 'm' },
5031 + { { STATE_PSCALLINC }, 'm' },
5032 + { { STATE_PSOWB }, 'm' },
5033 + { { STATE_PSUM }, 'm' },
5034 + { { STATE_PSEXCM }, 'm' },
5035 + { { STATE_PSINTLEVEL }, 'm' }
5039 -Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5042 - tie_t = (val << 28) >> 28;
5043 - insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
5044 - tie_t = (val << 27) >> 31;
5045 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5046 - tie_t = (val << 24) >> 29;
5047 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5049 +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
5050 + { { 6 /* art */ }, 'o' }
5054 -Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5056 - unsigned tie_t = 0;
5057 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5058 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5059 - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
5064 -Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5067 - tie_t = (val << 28) >> 28;
5068 - insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
5069 - tie_t = (val << 27) >> 31;
5070 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5071 - tie_t = (val << 24) >> 29;
5072 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5074 +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
5075 + { { STATE_EPC1 }, 'i' }
5079 -Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5081 - unsigned tie_t = 0;
5082 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5083 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5084 - tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
5087 +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
5088 + { { 6 /* art */ }, 'i' }
5092 -Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5095 - tie_t = (val << 28) >> 28;
5096 - insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
5097 - tie_t = (val << 27) >> 31;
5098 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5099 - tie_t = (val << 24) >> 29;
5100 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5102 +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
5103 + { { STATE_EPC1 }, 'o' }
5107 -Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5109 - unsigned tie_t = 0;
5110 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5111 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5114 +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
5115 + { { 6 /* art */ }, 'm' }
5119 -Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5122 - tie_t = (val << 31) >> 31;
5123 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5124 - tie_t = (val << 28) >> 29;
5125 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5127 +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
5128 + { { STATE_EPC1 }, 'm' }
5132 -Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5134 - unsigned tie_t = 0;
5135 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5136 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5139 +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
5140 + { { 6 /* art */ }, 'o' }
5144 -Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5147 - tie_t = (val << 31) >> 31;
5148 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5149 - tie_t = (val << 28) >> 29;
5150 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5152 +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
5153 + { { STATE_EXCSAVE1 }, 'i' }
5157 -Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5159 - unsigned tie_t = 0;
5160 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5161 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5164 +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
5165 + { { 6 /* art */ }, 'i' }
5169 -Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5172 - tie_t = (val << 31) >> 31;
5173 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5174 - tie_t = (val << 28) >> 29;
5175 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5177 +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
5178 + { { STATE_EXCSAVE1 }, 'o' }
5182 -Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5184 - unsigned tie_t = 0;
5185 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5186 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5189 +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
5190 + { { 6 /* art */ }, 'm' }
5194 -Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5197 - tie_t = (val << 31) >> 31;
5198 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5199 - tie_t = (val << 28) >> 29;
5200 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5202 +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
5203 + { { STATE_EXCSAVE1 }, 'm' }
5207 -Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5209 - unsigned tie_t = 0;
5210 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5211 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5214 +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
5215 + { { 6 /* art */ }, 'o' }
5219 -Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5222 - tie_t = (val << 31) >> 31;
5223 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5224 - tie_t = (val << 28) >> 29;
5225 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5227 +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
5228 + { { STATE_EPC2 }, 'i' }
5232 -Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5234 - unsigned tie_t = 0;
5235 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5236 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5239 +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
5240 + { { 6 /* art */ }, 'i' }
5244 -Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5247 - tie_t = (val << 31) >> 31;
5248 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5249 - tie_t = (val << 28) >> 29;
5250 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5252 +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
5253 + { { STATE_EPC2 }, 'o' }
5257 -Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5259 - unsigned tie_t = 0;
5260 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5261 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5264 +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
5265 + { { 6 /* art */ }, 'm' }
5269 -Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5272 - tie_t = (val << 31) >> 31;
5273 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5274 - tie_t = (val << 28) >> 29;
5275 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5277 +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
5278 + { { STATE_EPC2 }, 'm' }
5282 -Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5284 - unsigned tie_t = 0;
5285 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5286 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5289 +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
5290 + { { 6 /* art */ }, 'o' }
5294 -Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5297 - tie_t = (val << 31) >> 31;
5298 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5299 - tie_t = (val << 28) >> 29;
5300 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5302 +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
5303 + { { STATE_EXCSAVE2 }, 'i' }
5307 -Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5309 - unsigned tie_t = 0;
5310 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5311 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5314 +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
5315 + { { 6 /* art */ }, 'i' }
5319 -Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5322 - tie_t = (val << 31) >> 31;
5323 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5324 - tie_t = (val << 28) >> 29;
5325 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5327 +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
5328 + { { STATE_EXCSAVE2 }, 'o' }
5332 -Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5334 - unsigned tie_t = 0;
5335 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5336 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5339 +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
5340 + { { 6 /* art */ }, 'm' }
5344 -Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5347 - tie_t = (val << 31) >> 31;
5348 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5349 - tie_t = (val << 28) >> 29;
5350 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5352 +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
5353 + { { STATE_EXCSAVE2 }, 'm' }
5357 -Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5359 - unsigned tie_t = 0;
5360 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5361 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5364 +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = {
5365 + { { 6 /* art */ }, 'o' }
5369 -Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5372 - tie_t = (val << 31) >> 31;
5373 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5374 - tie_t = (val << 28) >> 29;
5375 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5377 +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = {
5378 + { { STATE_EPC3 }, 'i' }
5382 -Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5384 - unsigned tie_t = 0;
5385 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5386 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5389 +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = {
5390 + { { 6 /* art */ }, 'i' }
5394 -Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5397 - tie_t = (val << 31) >> 31;
5398 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5399 - tie_t = (val << 28) >> 29;
5400 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5402 +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = {
5403 + { { STATE_EPC3 }, 'o' }
5407 -Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5409 - unsigned tie_t = 0;
5410 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5411 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5414 +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = {
5415 + { { 6 /* art */ }, 'm' }
5419 -Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5422 - tie_t = (val << 31) >> 31;
5423 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5424 - tie_t = (val << 28) >> 29;
5425 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5427 +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = {
5428 + { { STATE_EPC3 }, 'm' }
5432 -Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5434 - unsigned tie_t = 0;
5435 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5436 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5439 +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = {
5440 + { { 6 /* art */ }, 'o' }
5444 -Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5447 - tie_t = (val << 31) >> 31;
5448 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5449 - tie_t = (val << 28) >> 29;
5450 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5452 +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = {
5453 + { { STATE_EXCSAVE3 }, 'i' }
5457 -Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5459 - unsigned tie_t = 0;
5460 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5461 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5464 +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = {
5465 + { { 6 /* art */ }, 'i' }
5469 -Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5472 - tie_t = (val << 31) >> 31;
5473 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5474 - tie_t = (val << 28) >> 29;
5475 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5477 +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = {
5478 + { { STATE_EXCSAVE3 }, 'o' }
5482 -Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5484 - unsigned tie_t = 0;
5485 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5486 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5489 +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = {
5490 + { { 6 /* art */ }, 'm' }
5494 -Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5497 - tie_t = (val << 31) >> 31;
5498 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5499 - tie_t = (val << 28) >> 29;
5500 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5502 +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = {
5503 + { { STATE_EXCSAVE3 }, 'm' }
5507 -Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5509 - unsigned tie_t = 0;
5510 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5511 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5514 +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = {
5515 + { { 6 /* art */ }, 'o' }
5519 -Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5522 - tie_t = (val << 31) >> 31;
5523 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5524 - tie_t = (val << 28) >> 29;
5525 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5527 +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = {
5528 + { { STATE_EPC4 }, 'i' }
5532 -Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5534 - unsigned tie_t = 0;
5535 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5536 - tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
5539 +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = {
5540 + { { 6 /* art */ }, 'i' }
5544 -Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5547 - tie_t = (val << 31) >> 31;
5548 - insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
5549 - tie_t = (val << 28) >> 29;
5550 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5552 +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = {
5553 + { { STATE_EPC4 }, 'o' }
5557 -Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
5559 - unsigned tie_t = 0;
5560 - tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
5561 - tie_t = (tie_t << 27) | ((insn[0] << 5) >> 5);
5564 +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = {
5565 + { { 6 /* art */ }, 'm' }
5569 -Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
5572 - tie_t = (val << 5) >> 5;
5573 - insn[0] = (insn[0] & ~0x7ffffff) | (tie_t << 0);
5574 - tie_t = (val << 2) >> 29;
5575 - insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
5577 +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = {
5578 + { { STATE_EPC4 }, 'm' }
5582 -Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
5584 - unsigned tie_t = 0;
5585 - tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
5588 +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = {
5589 + { { 6 /* art */ }, 'o' }
5593 -Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
5596 - tie_t = (val << 28) >> 28;
5597 - insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
5599 +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = {
5600 + { { STATE_EXCSAVE4 }, 'i' }
5604 -Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED,
5605 - uint32 val ATTRIBUTE_UNUSED)
5609 +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = {
5610 + { { 6 /* art */ }, 'i' }
5614 -Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
5618 +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = {
5619 + { { STATE_EXCSAVE4 }, 'o' }
5623 -Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
5627 +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = {
5628 + { { 6 /* art */ }, 'm' }
5632 -Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
5636 +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = {
5637 + { { STATE_EXCSAVE4 }, 'm' }
5641 -Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
5645 +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = {
5646 + { { 6 /* art */ }, 'o' }
5650 -Implicit_Field_mr0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
5654 +static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = {
5655 + { { STATE_EPC5 }, 'i' }
5659 -Implicit_Field_mr1_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
5663 +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = {
5664 + { { 6 /* art */ }, 'i' }
5668 -Implicit_Field_mr2_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
5672 +static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = {
5673 + { { STATE_EPC5 }, 'o' }
5677 -Implicit_Field_mr3_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
5681 +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = {
5682 + { { 6 /* art */ }, 'm' }
5686 -Implicit_Field_bt16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
5690 +static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = {
5691 + { { STATE_EPC5 }, 'm' }
5695 -Implicit_Field_bs16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
5699 +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = {
5700 + { { 6 /* art */ }, 'o' }
5704 -Implicit_Field_br16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
5708 +static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = {
5709 + { { STATE_EXCSAVE5 }, 'i' }
5713 -Implicit_Field_brall_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
5717 +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = {
5718 + { { 6 /* art */ }, 'i' }
5722 -/* Functional units. */
5723 +static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = {
5724 + { { STATE_EXCSAVE5 }, 'o' }
5727 -static xtensa_funcUnit_internal funcUnits[] = {
5728 +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = {
5729 + { { 6 /* art */ }, 'm' }
5732 +static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = {
5733 + { { STATE_EXCSAVE5 }, 'm' }
5737 -/* Register files. */
5738 +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
5739 + { { 6 /* art */ }, 'o' }
5742 -static xtensa_regfile_internal regfiles[] = {
5743 - { "AR", "a", 0, 32, 64 },
5744 - { "MR", "m", 1, 32, 4 },
5745 - { "BR", "b", 2, 1, 16 },
5746 - { "FR", "f", 3, 32, 16 },
5747 - { "BR2", "b", 2, 2, 8 },
5748 - { "BR4", "b", 2, 4, 4 },
5749 - { "BR8", "b", 2, 8, 2 },
5750 - { "BR16", "b", 2, 16, 1 }
5751 +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
5752 + { { STATE_EPS2 }, 'i' }
5757 +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
5758 + { { 6 /* art */ }, 'i' }
5761 -static xtensa_interface_internal interfaces[] = {
5762 +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
5763 + { { STATE_EPS2 }, 'o' }
5766 +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
5767 + { { 6 /* art */ }, 'm' }
5771 -/* Constant tables. */
5772 +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
5773 + { { STATE_EPS2 }, 'm' }
5776 -/* constant table ai4c */
5777 -static const unsigned CONST_TBL_ai4c_0[] = {
5795 +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = {
5796 + { { 6 /* art */ }, 'o' }
5799 -/* constant table b4c */
5800 -static const unsigned CONST_TBL_b4c_0[] = {
5818 +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = {
5819 + { { STATE_EPS3 }, 'i' }
5822 -/* constant table b4cu */
5823 -static const unsigned CONST_TBL_b4cu_0[] = {
5841 +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = {
5842 + { { 6 /* art */ }, 'i' }
5846 -/* Instruction operands. */
5849 -Operand_soffsetx4_decode (uint32 *valp)
5851 - unsigned soffsetx4_0, offset_0;
5852 - offset_0 = *valp & 0x3ffff;
5853 - soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2);
5854 - *valp = soffsetx4_0;
5857 +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = {
5858 + { { STATE_EPS3 }, 'o' }
5862 -Operand_soffsetx4_encode (uint32 *valp)
5864 - unsigned offset_0, soffsetx4_0;
5865 - soffsetx4_0 = *valp;
5866 - offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff;
5870 +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = {
5871 + { { 6 /* art */ }, 'm' }
5875 -Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
5877 - *valp -= (pc & ~0x3);
5880 +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = {
5881 + { { STATE_EPS3 }, 'm' }
5885 -Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
5887 - *valp += (pc & ~0x3);
5890 +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = {
5891 + { { 6 /* art */ }, 'o' }
5895 -Operand_uimm12x8_decode (uint32 *valp)
5897 - unsigned uimm12x8_0, imm12_0;
5898 - imm12_0 = *valp & 0xfff;
5899 - uimm12x8_0 = imm12_0 << 3;
5900 - *valp = uimm12x8_0;
5903 +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = {
5904 + { { STATE_EPS4 }, 'i' }
5908 -Operand_uimm12x8_encode (uint32 *valp)
5910 - unsigned imm12_0, uimm12x8_0;
5911 - uimm12x8_0 = *valp;
5912 - imm12_0 = ((uimm12x8_0 >> 3) & 0xfff);
5916 +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = {
5917 + { { 6 /* art */ }, 'i' }
5921 -Operand_simm4_decode (uint32 *valp)
5923 - unsigned simm4_0, mn_0;
5924 - mn_0 = *valp & 0xf;
5925 - simm4_0 = ((int) mn_0 << 28) >> 28;
5929 +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = {
5930 + { { STATE_EPS4 }, 'o' }
5934 -Operand_simm4_encode (uint32 *valp)
5936 - unsigned mn_0, simm4_0;
5938 - mn_0 = (simm4_0 & 0xf);
5942 +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = {
5943 + { { 6 /* art */ }, 'm' }
5947 -Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED)
5951 +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = {
5952 + { { STATE_EPS4 }, 'm' }
5956 -Operand_arr_encode (uint32 *valp)
5959 - error = (*valp & ~0xf) != 0;
5962 +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = {
5963 + { { 6 /* art */ }, 'o' }
5967 -Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED)
5971 +static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = {
5972 + { { STATE_EPS5 }, 'i' }
5976 -Operand_ars_encode (uint32 *valp)
5979 - error = (*valp & ~0xf) != 0;
5982 +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = {
5983 + { { 6 /* art */ }, 'i' }
5987 -Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED)
5991 +static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = {
5992 + { { STATE_EPS5 }, 'o' }
5996 -Operand_art_encode (uint32 *valp)
5999 - error = (*valp & ~0xf) != 0;
6002 +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = {
6003 + { { 6 /* art */ }, 'm' }
6007 -Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED)
6011 +static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = {
6012 + { { STATE_EPS5 }, 'm' }
6016 -Operand_ar0_encode (uint32 *valp)
6019 - error = (*valp & ~0x3f) != 0;
6022 +static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
6023 + { { 6 /* art */ }, 'o' }
6027 -Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED)
6031 +static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
6032 + { { STATE_EXCVADDR }, 'i' }
6036 -Operand_ar4_encode (uint32 *valp)
6039 - error = (*valp & ~0x3f) != 0;
6042 +static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
6043 + { { 6 /* art */ }, 'i' }
6047 -Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED)
6051 +static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
6052 + { { STATE_EXCVADDR }, 'o' }
6056 -Operand_ar8_encode (uint32 *valp)
6059 - error = (*valp & ~0x3f) != 0;
6062 +static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
6063 + { { 6 /* art */ }, 'm' }
6067 -Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED)
6071 +static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
6072 + { { STATE_EXCVADDR }, 'm' }
6076 -Operand_ar12_encode (uint32 *valp)
6079 - error = (*valp & ~0x3f) != 0;
6082 +static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
6083 + { { 6 /* art */ }, 'o' }
6087 -Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED)
6091 +static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
6092 + { { STATE_DEPC }, 'i' }
6096 -Operand_ars_entry_encode (uint32 *valp)
6099 - error = (*valp & ~0x3f) != 0;
6102 +static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
6103 + { { 6 /* art */ }, 'i' }
6107 -Operand_immrx4_decode (uint32 *valp)
6109 - unsigned immrx4_0, r_0;
6110 - r_0 = *valp & 0xf;
6111 - immrx4_0 = (((0xfffffff) << 4) | r_0) << 2;
6115 +static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
6116 + { { STATE_DEPC }, 'o' }
6120 -Operand_immrx4_encode (uint32 *valp)
6122 - unsigned r_0, immrx4_0;
6124 - r_0 = ((immrx4_0 >> 2) & 0xf);
6128 +static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
6129 + { { 6 /* art */ }, 'm' }
6133 -Operand_lsi4x4_decode (uint32 *valp)
6135 - unsigned lsi4x4_0, r_0;
6136 - r_0 = *valp & 0xf;
6137 - lsi4x4_0 = r_0 << 2;
6141 +static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
6142 + { { STATE_DEPC }, 'm' }
6146 -Operand_lsi4x4_encode (uint32 *valp)
6148 - unsigned r_0, lsi4x4_0;
6150 - r_0 = ((lsi4x4_0 >> 2) & 0xf);
6154 +static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
6155 + { { 6 /* art */ }, 'o' }
6159 -Operand_simm7_decode (uint32 *valp)
6161 - unsigned simm7_0, imm7_0;
6162 - imm7_0 = *valp & 0x7f;
6163 - simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0;
6167 +static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
6168 + { { STATE_EXCCAUSE }, 'i' },
6169 + { { STATE_XTSYNC }, 'i' }
6173 -Operand_simm7_encode (uint32 *valp)
6175 - unsigned imm7_0, simm7_0;
6177 - imm7_0 = (simm7_0 & 0x7f);
6181 +static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
6182 + { { 6 /* art */ }, 'i' }
6186 -Operand_uimm6_decode (uint32 *valp)
6188 - unsigned uimm6_0, imm6_0;
6189 - imm6_0 = *valp & 0x3f;
6190 - uimm6_0 = 0x4 + (((0) << 6) | imm6_0);
6194 +static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
6195 + { { STATE_EXCCAUSE }, 'o' }
6199 -Operand_uimm6_encode (uint32 *valp)
6201 - unsigned imm6_0, uimm6_0;
6203 - imm6_0 = (uimm6_0 - 0x4) & 0x3f;
6207 +static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
6208 + { { 6 /* art */ }, 'm' }
6212 -Operand_uimm6_ator (uint32 *valp, uint32 pc)
6217 +static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
6218 + { { STATE_EXCCAUSE }, 'm' }
6222 -Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
6227 +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = {
6228 + { { 6 /* art */ }, 'o' }
6232 -Operand_ai4const_decode (uint32 *valp)
6234 - unsigned ai4const_0, t_0;
6235 - t_0 = *valp & 0xf;
6236 - ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf];
6237 - *valp = ai4const_0;
6240 +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = {
6241 + { { STATE_MISC0 }, 'i' }
6245 -Operand_ai4const_encode (uint32 *valp)
6247 - unsigned t_0, ai4const_0;
6248 - ai4const_0 = *valp;
6249 - switch (ai4const_0)
6251 - case 0xffffffff: t_0 = 0; break;
6252 - case 0x1: t_0 = 0x1; break;
6253 - case 0x2: t_0 = 0x2; break;
6254 - case 0x3: t_0 = 0x3; break;
6255 - case 0x4: t_0 = 0x4; break;
6256 - case 0x5: t_0 = 0x5; break;
6257 - case 0x6: t_0 = 0x6; break;
6258 - case 0x7: t_0 = 0x7; break;
6259 - case 0x8: t_0 = 0x8; break;
6260 - case 0x9: t_0 = 0x9; break;
6261 - case 0xa: t_0 = 0xa; break;
6262 - case 0xb: t_0 = 0xb; break;
6263 - case 0xc: t_0 = 0xc; break;
6264 - case 0xd: t_0 = 0xd; break;
6265 - case 0xe: t_0 = 0xe; break;
6266 - default: t_0 = 0xf; break;
6271 +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = {
6272 + { { 6 /* art */ }, 'i' }
6276 -Operand_b4const_decode (uint32 *valp)
6278 - unsigned b4const_0, r_0;
6279 - r_0 = *valp & 0xf;
6280 - b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf];
6281 - *valp = b4const_0;
6284 +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = {
6285 + { { STATE_MISC0 }, 'o' }
6289 -Operand_b4const_encode (uint32 *valp)
6291 - unsigned r_0, b4const_0;
6292 - b4const_0 = *valp;
6293 - switch (b4const_0)
6295 - case 0xffffffff: r_0 = 0; break;
6296 - case 0x1: r_0 = 0x1; break;
6297 - case 0x2: r_0 = 0x2; break;
6298 - case 0x3: r_0 = 0x3; break;
6299 - case 0x4: r_0 = 0x4; break;
6300 - case 0x5: r_0 = 0x5; break;
6301 - case 0x6: r_0 = 0x6; break;
6302 - case 0x7: r_0 = 0x7; break;
6303 - case 0x8: r_0 = 0x8; break;
6304 - case 0xa: r_0 = 0x9; break;
6305 - case 0xc: r_0 = 0xa; break;
6306 - case 0x10: r_0 = 0xb; break;
6307 - case 0x20: r_0 = 0xc; break;
6308 - case 0x40: r_0 = 0xd; break;
6309 - case 0x80: r_0 = 0xe; break;
6310 - default: r_0 = 0xf; break;
6315 +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = {
6316 + { { 6 /* art */ }, 'm' }
6320 -Operand_b4constu_decode (uint32 *valp)
6322 - unsigned b4constu_0, r_0;
6323 - r_0 = *valp & 0xf;
6324 - b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf];
6325 - *valp = b4constu_0;
6328 +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = {
6329 + { { STATE_MISC0 }, 'm' }
6333 -Operand_b4constu_encode (uint32 *valp)
6335 - unsigned r_0, b4constu_0;
6336 - b4constu_0 = *valp;
6337 - switch (b4constu_0)
6339 - case 0x8000: r_0 = 0; break;
6340 - case 0x10000: r_0 = 0x1; break;
6341 - case 0x2: r_0 = 0x2; break;
6342 - case 0x3: r_0 = 0x3; break;
6343 - case 0x4: r_0 = 0x4; break;
6344 - case 0x5: r_0 = 0x5; break;
6345 - case 0x6: r_0 = 0x6; break;
6346 - case 0x7: r_0 = 0x7; break;
6347 - case 0x8: r_0 = 0x8; break;
6348 - case 0xa: r_0 = 0x9; break;
6349 - case 0xc: r_0 = 0xa; break;
6350 - case 0x10: r_0 = 0xb; break;
6351 - case 0x20: r_0 = 0xc; break;
6352 - case 0x40: r_0 = 0xd; break;
6353 - case 0x80: r_0 = 0xe; break;
6354 - default: r_0 = 0xf; break;
6359 +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = {
6360 + { { 6 /* art */ }, 'o' }
6364 -Operand_uimm8_decode (uint32 *valp)
6366 - unsigned uimm8_0, imm8_0;
6367 - imm8_0 = *valp & 0xff;
6372 +static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = {
6373 + { { STATE_MISC1 }, 'i' }
6377 -Operand_uimm8_encode (uint32 *valp)
6379 - unsigned imm8_0, uimm8_0;
6381 - imm8_0 = (uimm8_0 & 0xff);
6385 +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = {
6386 + { { 6 /* art */ }, 'i' }
6390 -Operand_uimm8x2_decode (uint32 *valp)
6392 - unsigned uimm8x2_0, imm8_0;
6393 - imm8_0 = *valp & 0xff;
6394 - uimm8x2_0 = imm8_0 << 1;
6395 - *valp = uimm8x2_0;
6398 +static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = {
6399 + { { STATE_MISC1 }, 'o' }
6403 -Operand_uimm8x2_encode (uint32 *valp)
6405 - unsigned imm8_0, uimm8x2_0;
6406 - uimm8x2_0 = *valp;
6407 - imm8_0 = ((uimm8x2_0 >> 1) & 0xff);
6411 +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = {
6412 + { { 6 /* art */ }, 'm' }
6416 -Operand_uimm8x4_decode (uint32 *valp)
6418 - unsigned uimm8x4_0, imm8_0;
6419 - imm8_0 = *valp & 0xff;
6420 - uimm8x4_0 = imm8_0 << 2;
6421 - *valp = uimm8x4_0;
6424 +static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = {
6425 + { { STATE_MISC1 }, 'm' }
6429 -Operand_uimm8x4_encode (uint32 *valp)
6431 - unsigned imm8_0, uimm8x4_0;
6432 - uimm8x4_0 = *valp;
6433 - imm8_0 = ((uimm8x4_0 >> 2) & 0xff);
6437 +static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
6438 + { { 6 /* art */ }, 'o' }
6442 -Operand_uimm4x16_decode (uint32 *valp)
6444 - unsigned uimm4x16_0, op2_0;
6445 - op2_0 = *valp & 0xf;
6446 - uimm4x16_0 = op2_0 << 4;
6447 - *valp = uimm4x16_0;
6450 +static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = {
6451 + { { 6 /* art */ }, 'o' }
6455 -Operand_uimm4x16_encode (uint32 *valp)
6457 - unsigned op2_0, uimm4x16_0;
6458 - uimm4x16_0 = *valp;
6459 - op2_0 = ((uimm4x16_0 >> 4) & 0xf);
6463 +static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = {
6464 + { { STATE_VECBASE }, 'i' }
6468 -Operand_simm8_decode (uint32 *valp)
6470 - unsigned simm8_0, imm8_0;
6471 - imm8_0 = *valp & 0xff;
6472 - simm8_0 = ((int) imm8_0 << 24) >> 24;
6476 +static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = {
6477 + { { 6 /* art */ }, 'i' }
6481 -Operand_simm8_encode (uint32 *valp)
6483 - unsigned imm8_0, simm8_0;
6485 - imm8_0 = (simm8_0 & 0xff);
6489 +static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = {
6490 + { { STATE_VECBASE }, 'o' }
6494 -Operand_simm8x256_decode (uint32 *valp)
6496 - unsigned simm8x256_0, imm8_0;
6497 - imm8_0 = *valp & 0xff;
6498 - simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8;
6499 - *valp = simm8x256_0;
6502 +static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = {
6503 + { { 6 /* art */ }, 'm' }
6507 -Operand_simm8x256_encode (uint32 *valp)
6509 - unsigned imm8_0, simm8x256_0;
6510 - simm8x256_0 = *valp;
6511 - imm8_0 = ((simm8x256_0 >> 8) & 0xff);
6515 +static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = {
6516 + { { STATE_VECBASE }, 'm' }
6520 -Operand_simm12b_decode (uint32 *valp)
6522 - unsigned simm12b_0, imm12b_0;
6523 - imm12b_0 = *valp & 0xfff;
6524 - simm12b_0 = ((int) imm12b_0 << 20) >> 20;
6525 - *valp = simm12b_0;
6528 +static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
6529 + { { 43 /* s */ }, 'i' }
6533 -Operand_simm12b_encode (uint32 *valp)
6535 - unsigned imm12b_0, simm12b_0;
6536 - simm12b_0 = *valp;
6537 - imm12b_0 = (simm12b_0 & 0xfff);
6541 +static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
6542 + { { STATE_PSWOE }, 'o' },
6543 + { { STATE_PSCALLINC }, 'o' },
6544 + { { STATE_PSOWB }, 'o' },
6545 + { { STATE_PSUM }, 'o' },
6546 + { { STATE_PSEXCM }, 'o' },
6547 + { { STATE_PSINTLEVEL }, 'o' },
6548 + { { STATE_EPC1 }, 'i' },
6549 + { { STATE_EPC2 }, 'i' },
6550 + { { STATE_EPC3 }, 'i' },
6551 + { { STATE_EPC4 }, 'i' },
6552 + { { STATE_EPC5 }, 'i' },
6553 + { { STATE_EPS2 }, 'i' },
6554 + { { STATE_EPS3 }, 'i' },
6555 + { { STATE_EPS4 }, 'i' },
6556 + { { STATE_EPS5 }, 'i' },
6557 + { { STATE_InOCDMode }, 'm' }
6561 -Operand_msalp32_decode (uint32 *valp)
6563 - unsigned msalp32_0, sal_0;
6564 - sal_0 = *valp & 0x1f;
6565 - msalp32_0 = 0x20 - sal_0;
6566 - *valp = msalp32_0;
6569 +static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
6570 + { { 43 /* s */ }, 'i' }
6574 -Operand_msalp32_encode (uint32 *valp)
6576 - unsigned sal_0, msalp32_0;
6577 - msalp32_0 = *valp;
6578 - sal_0 = (0x20 - msalp32_0) & 0x1f;
6582 +static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
6583 + { { STATE_PSINTLEVEL }, 'o' }
6587 -Operand_op2p1_decode (uint32 *valp)
6589 - unsigned op2p1_0, op2_0;
6590 - op2_0 = *valp & 0xf;
6591 - op2p1_0 = op2_0 + 0x1;
6595 +static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
6596 + { { 6 /* art */ }, 'o' }
6600 -Operand_op2p1_encode (uint32 *valp)
6602 - unsigned op2_0, op2p1_0;
6604 - op2_0 = (op2p1_0 - 0x1) & 0xf;
6608 +static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
6609 + { { STATE_INTERRUPT }, 'i' }
6613 -Operand_label8_decode (uint32 *valp)
6615 - unsigned label8_0, imm8_0;
6616 - imm8_0 = *valp & 0xff;
6617 - label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24);
6621 +static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
6622 + { { 6 /* art */ }, 'i' }
6626 -Operand_label8_encode (uint32 *valp)
6628 - unsigned imm8_0, label8_0;
6630 - imm8_0 = (label8_0 - 0x4) & 0xff;
6634 +static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
6635 + { { STATE_XTSYNC }, 'o' },
6636 + { { STATE_INTERRUPT }, 'm' }
6640 -Operand_label8_ator (uint32 *valp, uint32 pc)
6645 +static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
6646 + { { 6 /* art */ }, 'i' }
6650 -Operand_label8_rtoa (uint32 *valp, uint32 pc)
6657 -Operand_ulabel8_decode (uint32 *valp)
6659 - unsigned ulabel8_0, imm8_0;
6660 - imm8_0 = *valp & 0xff;
6661 - ulabel8_0 = 0x4 + (((0) << 8) | imm8_0);
6662 - *valp = ulabel8_0;
6665 +static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
6666 + { { STATE_XTSYNC }, 'o' },
6667 + { { STATE_INTERRUPT }, 'm' }
6671 -Operand_ulabel8_encode (uint32 *valp)
6673 - unsigned imm8_0, ulabel8_0;
6674 - ulabel8_0 = *valp;
6675 - imm8_0 = (ulabel8_0 - 0x4) & 0xff;
6679 +static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
6680 + { { 6 /* art */ }, 'o' }
6684 -Operand_ulabel8_ator (uint32 *valp, uint32 pc)
6689 +static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
6690 + { { STATE_INTENABLE }, 'i' }
6694 -Operand_ulabel8_rtoa (uint32 *valp, uint32 pc)
6699 +static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
6700 + { { 6 /* art */ }, 'i' }
6704 -Operand_label12_decode (uint32 *valp)
6706 - unsigned label12_0, imm12_0;
6707 - imm12_0 = *valp & 0xfff;
6708 - label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20);
6709 - *valp = label12_0;
6712 +static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
6713 + { { STATE_INTENABLE }, 'o' }
6717 -Operand_label12_encode (uint32 *valp)
6719 - unsigned imm12_0, label12_0;
6720 - label12_0 = *valp;
6721 - imm12_0 = (label12_0 - 0x4) & 0xfff;
6725 +static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
6726 + { { 6 /* art */ }, 'm' }
6730 -Operand_label12_ator (uint32 *valp, uint32 pc)
6735 +static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
6736 + { { STATE_INTENABLE }, 'm' }
6740 -Operand_label12_rtoa (uint32 *valp, uint32 pc)
6745 +static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
6746 + { { 34 /* imms */ }, 'i' },
6747 + { { 33 /* immt */ }, 'i' }
6751 -Operand_soffset_decode (uint32 *valp)
6753 - unsigned soffset_0, offset_0;
6754 - offset_0 = *valp & 0x3ffff;
6755 - soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14);
6756 - *valp = soffset_0;
6759 +static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
6760 + { { STATE_PSEXCM }, 'i' },
6761 + { { STATE_PSINTLEVEL }, 'i' }
6765 -Operand_soffset_encode (uint32 *valp)
6767 - unsigned offset_0, soffset_0;
6768 - soffset_0 = *valp;
6769 - offset_0 = (soffset_0 - 0x4) & 0x3ffff;
6773 +static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
6774 + { { 34 /* imms */ }, 'i' }
6778 -Operand_soffset_ator (uint32 *valp, uint32 pc)
6783 +static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
6784 + { { STATE_PSEXCM }, 'i' },
6785 + { { STATE_PSINTLEVEL }, 'i' }
6789 -Operand_soffset_rtoa (uint32 *valp, uint32 pc)
6794 +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = {
6795 + { { 6 /* art */ }, 'o' }
6799 -Operand_uimm16x4_decode (uint32 *valp)
6801 - unsigned uimm16x4_0, imm16_0;
6802 - imm16_0 = *valp & 0xffff;
6803 - uimm16x4_0 = (((0xffff) << 16) | imm16_0) << 2;
6804 - *valp = uimm16x4_0;
6807 +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = {
6808 + { { STATE_DBREAKA0 }, 'i' }
6812 -Operand_uimm16x4_encode (uint32 *valp)
6814 - unsigned imm16_0, uimm16x4_0;
6815 - uimm16x4_0 = *valp;
6816 - imm16_0 = (uimm16x4_0 >> 2) & 0xffff;
6820 +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = {
6821 + { { 6 /* art */ }, 'i' }
6825 -Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
6827 - *valp -= ((pc + 3) & ~0x3);
6830 +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = {
6831 + { { STATE_DBREAKA0 }, 'o' },
6832 + { { STATE_XTSYNC }, 'o' }
6836 -Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
6838 - *valp += ((pc + 3) & ~0x3);
6841 +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = {
6842 + { { 6 /* art */ }, 'm' }
6846 -Operand_mx_decode (uint32 *valp ATTRIBUTE_UNUSED)
6850 +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = {
6851 + { { STATE_DBREAKA0 }, 'm' },
6852 + { { STATE_XTSYNC }, 'o' }
6856 -Operand_mx_encode (uint32 *valp)
6859 - error = (*valp & ~0x3) != 0;
6862 +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = {
6863 + { { 6 /* art */ }, 'o' }
6867 -Operand_my_decode (uint32 *valp)
6872 +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = {
6873 + { { STATE_DBREAKC0 }, 'i' }
6877 -Operand_my_encode (uint32 *valp)
6880 - error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0);
6881 - *valp = *valp & 1;
6884 +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = {
6885 + { { 6 /* art */ }, 'i' }
6889 -Operand_mw_decode (uint32 *valp ATTRIBUTE_UNUSED)
6893 +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = {
6894 + { { STATE_DBREAKC0 }, 'o' },
6895 + { { STATE_XTSYNC }, 'o' }
6899 -Operand_mw_encode (uint32 *valp)
6902 - error = (*valp & ~0x3) != 0;
6905 +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = {
6906 + { { 6 /* art */ }, 'm' }
6910 -Operand_mr0_decode (uint32 *valp ATTRIBUTE_UNUSED)
6914 +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = {
6915 + { { STATE_DBREAKC0 }, 'm' },
6916 + { { STATE_XTSYNC }, 'o' }
6920 -Operand_mr0_encode (uint32 *valp)
6923 - error = (*valp & ~0x3) != 0;
6926 +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = {
6927 + { { 6 /* art */ }, 'o' }
6931 -Operand_mr1_decode (uint32 *valp ATTRIBUTE_UNUSED)
6935 +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = {
6936 + { { STATE_DBREAKA1 }, 'i' }
6940 -Operand_mr1_encode (uint32 *valp)
6943 - error = (*valp & ~0x3) != 0;
6946 +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = {
6947 + { { 6 /* art */ }, 'i' }
6951 -Operand_mr2_decode (uint32 *valp ATTRIBUTE_UNUSED)
6957 -Operand_mr2_encode (uint32 *valp)
6960 - error = (*valp & ~0x3) != 0;
6963 +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = {
6964 + { { STATE_DBREAKA1 }, 'o' },
6965 + { { STATE_XTSYNC }, 'o' }
6969 -Operand_mr3_decode (uint32 *valp ATTRIBUTE_UNUSED)
6973 +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = {
6974 + { { 6 /* art */ }, 'm' }
6978 -Operand_mr3_encode (uint32 *valp)
6981 - error = (*valp & ~0x3) != 0;
6984 +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = {
6985 + { { STATE_DBREAKA1 }, 'm' },
6986 + { { STATE_XTSYNC }, 'o' }
6990 -Operand_immt_decode (uint32 *valp)
6992 - unsigned immt_0, t_0;
6993 - t_0 = *valp & 0xf;
6998 +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = {
6999 + { { 6 /* art */ }, 'o' }
7003 -Operand_immt_encode (uint32 *valp)
7005 - unsigned t_0, immt_0;
7007 - t_0 = immt_0 & 0xf;
7011 +static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = {
7012 + { { STATE_DBREAKC1 }, 'i' }
7016 -Operand_imms_decode (uint32 *valp)
7018 - unsigned imms_0, s_0;
7019 - s_0 = *valp & 0xf;
7024 +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = {
7025 + { { 6 /* art */ }, 'i' }
7029 -Operand_imms_encode (uint32 *valp)
7031 - unsigned s_0, imms_0;
7033 - s_0 = imms_0 & 0xf;
7037 +static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = {
7038 + { { STATE_DBREAKC1 }, 'o' },
7039 + { { STATE_XTSYNC }, 'o' }
7043 -Operand_bt_decode (uint32 *valp ATTRIBUTE_UNUSED)
7047 +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = {
7048 + { { 6 /* art */ }, 'm' }
7052 -Operand_bt_encode (uint32 *valp)
7055 - error = (*valp & ~0xf) != 0;
7058 +static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = {
7059 + { { STATE_DBREAKC1 }, 'm' },
7060 + { { STATE_XTSYNC }, 'o' }
7064 -Operand_bs_decode (uint32 *valp ATTRIBUTE_UNUSED)
7068 +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = {
7069 + { { 6 /* art */ }, 'o' }
7073 -Operand_bs_encode (uint32 *valp)
7076 - error = (*valp & ~0xf) != 0;
7079 +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = {
7080 + { { STATE_IBREAKA0 }, 'i' }
7084 -Operand_br_decode (uint32 *valp ATTRIBUTE_UNUSED)
7088 +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = {
7089 + { { 6 /* art */ }, 'i' }
7093 -Operand_br_encode (uint32 *valp)
7096 - error = (*valp & ~0xf) != 0;
7099 +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = {
7100 + { { STATE_IBREAKA0 }, 'o' }
7104 -Operand_bt2_decode (uint32 *valp)
7106 - *valp = *valp << 1;
7109 +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = {
7110 + { { 6 /* art */ }, 'm' }
7114 -Operand_bt2_encode (uint32 *valp)
7117 - error = (*valp & ~(0x7 << 1)) != 0;
7118 - *valp = *valp >> 1;
7121 +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = {
7122 + { { STATE_IBREAKA0 }, 'm' }
7126 -Operand_bs2_decode (uint32 *valp)
7128 - *valp = *valp << 1;
7131 +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = {
7132 + { { 6 /* art */ }, 'o' }
7136 -Operand_bs2_encode (uint32 *valp)
7139 - error = (*valp & ~(0x7 << 1)) != 0;
7140 - *valp = *valp >> 1;
7143 +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = {
7144 + { { STATE_IBREAKA1 }, 'i' }
7148 -Operand_br2_decode (uint32 *valp)
7150 - *valp = *valp << 1;
7153 +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = {
7154 + { { 6 /* art */ }, 'i' }
7158 -Operand_br2_encode (uint32 *valp)
7161 - error = (*valp & ~(0x7 << 1)) != 0;
7162 - *valp = *valp >> 1;
7165 +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = {
7166 + { { STATE_IBREAKA1 }, 'o' }
7170 -Operand_bt4_decode (uint32 *valp)
7172 - *valp = *valp << 2;
7175 +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = {
7176 + { { 6 /* art */ }, 'm' }
7180 -Operand_bt4_encode (uint32 *valp)
7183 - error = (*valp & ~(0x3 << 2)) != 0;
7184 - *valp = *valp >> 2;
7187 +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = {
7188 + { { STATE_IBREAKA1 }, 'm' }
7192 -Operand_bs4_decode (uint32 *valp)
7194 - *valp = *valp << 2;
7197 +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = {
7198 + { { 6 /* art */ }, 'o' }
7202 -Operand_bs4_encode (uint32 *valp)
7205 - error = (*valp & ~(0x3 << 2)) != 0;
7206 - *valp = *valp >> 2;
7209 +static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = {
7210 + { { STATE_IBREAKENABLE }, 'i' }
7214 -Operand_br4_decode (uint32 *valp)
7216 - *valp = *valp << 2;
7219 +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = {
7220 + { { 6 /* art */ }, 'i' }
7224 -Operand_br4_encode (uint32 *valp)
7227 - error = (*valp & ~(0x3 << 2)) != 0;
7228 - *valp = *valp >> 2;
7231 +static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = {
7232 + { { STATE_IBREAKENABLE }, 'o' }
7236 -Operand_bt8_decode (uint32 *valp)
7238 - *valp = *valp << 3;
7241 +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = {
7242 + { { 6 /* art */ }, 'm' }
7246 -Operand_bt8_encode (uint32 *valp)
7249 - error = (*valp & ~(0x1 << 3)) != 0;
7250 - *valp = *valp >> 3;
7253 +static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = {
7254 + { { STATE_IBREAKENABLE }, 'm' }
7258 -Operand_bs8_decode (uint32 *valp)
7260 - *valp = *valp << 3;
7263 +static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = {
7264 + { { 6 /* art */ }, 'o' }
7268 -Operand_bs8_encode (uint32 *valp)
7271 - error = (*valp & ~(0x1 << 3)) != 0;
7272 - *valp = *valp >> 3;
7275 +static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = {
7276 + { { STATE_DEBUGCAUSE }, 'i' },
7277 + { { STATE_DBNUM }, 'i' }
7281 -Operand_br8_decode (uint32 *valp)
7283 - *valp = *valp << 3;
7286 +static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = {
7287 + { { 6 /* art */ }, 'i' }
7291 -Operand_br8_encode (uint32 *valp)
7294 - error = (*valp & ~(0x1 << 3)) != 0;
7295 - *valp = *valp >> 3;
7298 +static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = {
7299 + { { STATE_DEBUGCAUSE }, 'o' },
7300 + { { STATE_DBNUM }, 'o' }
7304 -Operand_bt16_decode (uint32 *valp)
7306 - *valp = *valp << 4;
7309 +static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = {
7310 + { { 6 /* art */ }, 'm' }
7314 -Operand_bt16_encode (uint32 *valp)
7317 - error = (*valp & ~(0 << 4)) != 0;
7318 - *valp = *valp >> 4;
7321 +static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = {
7322 + { { STATE_DEBUGCAUSE }, 'm' },
7323 + { { STATE_DBNUM }, 'm' }
7327 -Operand_bs16_decode (uint32 *valp)
7329 - *valp = *valp << 4;
7332 +static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = {
7333 + { { 6 /* art */ }, 'o' }
7337 -Operand_bs16_encode (uint32 *valp)
7340 - error = (*valp & ~(0 << 4)) != 0;
7341 - *valp = *valp >> 4;
7344 +static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = {
7345 + { { STATE_ICOUNT }, 'i' }
7349 -Operand_br16_decode (uint32 *valp)
7351 - *valp = *valp << 4;
7354 +static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = {
7355 + { { 6 /* art */ }, 'i' }
7359 -Operand_br16_encode (uint32 *valp)
7362 - error = (*valp & ~(0 << 4)) != 0;
7363 - *valp = *valp >> 4;
7366 +static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = {
7367 + { { STATE_XTSYNC }, 'o' },
7368 + { { STATE_ICOUNT }, 'o' }
7372 -Operand_brall_decode (uint32 *valp)
7374 - *valp = *valp << 4;
7377 +static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = {
7378 + { { 6 /* art */ }, 'm' }
7382 -Operand_brall_encode (uint32 *valp)
7385 - error = (*valp & ~(0 << 4)) != 0;
7386 - *valp = *valp >> 4;
7389 +static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = {
7390 + { { STATE_XTSYNC }, 'o' },
7391 + { { STATE_ICOUNT }, 'm' }
7395 -Operand_tp7_decode (uint32 *valp)
7397 - unsigned tp7_0, t_0;
7398 - t_0 = *valp & 0xf;
7399 - tp7_0 = t_0 + 0x7;
7403 +static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = {
7404 + { { 6 /* art */ }, 'o' }
7408 -Operand_tp7_encode (uint32 *valp)
7410 - unsigned t_0, tp7_0;
7412 - t_0 = (tp7_0 - 0x7) & 0xf;
7416 +static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = {
7417 + { { STATE_ICOUNTLEVEL }, 'i' }
7421 -Operand_xt_wbr15_label_decode (uint32 *valp)
7423 - unsigned xt_wbr15_label_0, xt_wbr15_imm_0;
7424 - xt_wbr15_imm_0 = *valp & 0x7fff;
7425 - xt_wbr15_label_0 = 0x4 + (((int) xt_wbr15_imm_0 << 17) >> 17);
7426 - *valp = xt_wbr15_label_0;
7429 +static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = {
7430 + { { 6 /* art */ }, 'i' }
7434 -Operand_xt_wbr15_label_encode (uint32 *valp)
7436 - unsigned xt_wbr15_imm_0, xt_wbr15_label_0;
7437 - xt_wbr15_label_0 = *valp;
7438 - xt_wbr15_imm_0 = (xt_wbr15_label_0 - 0x4) & 0x7fff;
7439 - *valp = xt_wbr15_imm_0;
7442 +static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = {
7443 + { { STATE_ICOUNTLEVEL }, 'o' }
7447 -Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc)
7452 +static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = {
7453 + { { 6 /* art */ }, 'm' }
7457 -Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc)
7462 +static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = {
7463 + { { STATE_ICOUNTLEVEL }, 'm' }
7467 -Operand_xt_wbr18_label_decode (uint32 *valp)
7469 - unsigned xt_wbr18_label_0, xt_wbr18_imm_0;
7470 - xt_wbr18_imm_0 = *valp & 0x3ffff;
7471 - xt_wbr18_label_0 = 0x4 + (((int) xt_wbr18_imm_0 << 14) >> 14);
7472 - *valp = xt_wbr18_label_0;
7475 +static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = {
7476 + { { 6 /* art */ }, 'o' }
7480 -Operand_xt_wbr18_label_encode (uint32 *valp)
7482 - unsigned xt_wbr18_imm_0, xt_wbr18_label_0;
7483 - xt_wbr18_label_0 = *valp;
7484 - xt_wbr18_imm_0 = (xt_wbr18_label_0 - 0x4) & 0x3ffff;
7485 - *valp = xt_wbr18_imm_0;
7488 +static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = {
7489 + { { STATE_DDR }, 'i' }
7493 -Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc)
7498 +static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = {
7499 + { { 6 /* art */ }, 'i' }
7503 -Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc)
7508 +static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = {
7509 + { { STATE_XTSYNC }, 'o' },
7510 + { { STATE_DDR }, 'o' }
7514 -Operand_cimm8x4_decode (uint32 *valp)
7516 - unsigned cimm8x4_0, imm8_0;
7517 - imm8_0 = *valp & 0xff;
7518 - cimm8x4_0 = (imm8_0 << 2) | 0;
7519 - *valp = cimm8x4_0;
7522 +static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = {
7523 + { { 6 /* art */ }, 'm' }
7527 -Operand_cimm8x4_encode (uint32 *valp)
7529 - unsigned imm8_0, cimm8x4_0;
7530 - cimm8x4_0 = *valp;
7531 - imm8_0 = (cimm8x4_0 >> 2) & 0xff;
7535 +static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = {
7536 + { { STATE_XTSYNC }, 'o' },
7537 + { { STATE_DDR }, 'm' }
7541 -Operand_frr_decode (uint32 *valp ATTRIBUTE_UNUSED)
7545 +static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = {
7546 + { { 34 /* imms */ }, 'i' }
7550 -Operand_frr_encode (uint32 *valp)
7553 - error = (*valp & ~0xf) != 0;
7556 +static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = {
7557 + { { STATE_InOCDMode }, 'm' },
7558 + { { STATE_EPC4 }, 'i' },
7559 + { { STATE_PSWOE }, 'o' },
7560 + { { STATE_PSCALLINC }, 'o' },
7561 + { { STATE_PSOWB }, 'o' },
7562 + { { STATE_PSUM }, 'o' },
7563 + { { STATE_PSEXCM }, 'o' },
7564 + { { STATE_PSINTLEVEL }, 'o' },
7565 + { { STATE_EPS4 }, 'i' }
7569 -Operand_frs_decode (uint32 *valp ATTRIBUTE_UNUSED)
7573 +static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = {
7574 + { { STATE_InOCDMode }, 'm' }
7578 -Operand_frs_encode (uint32 *valp)
7581 - error = (*valp & ~0xf) != 0;
7584 +static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = {
7585 + { { 6 /* art */ }, 'i' }
7589 -Operand_frt_decode (uint32 *valp ATTRIBUTE_UNUSED)
7593 +static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = {
7594 + { { STATE_XTSYNC }, 'o' }
7598 -Operand_frt_encode (uint32 *valp)
7601 - error = (*valp & ~0xf) != 0;
7604 +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = {
7605 + { { 6 /* art */ }, 'o' }
7608 -static xtensa_operand_internal operands[] = {
7609 - { "soffsetx4", 10, -1, 0,
7610 - XTENSA_OPERAND_IS_PCRELATIVE,
7611 - Operand_soffsetx4_encode, Operand_soffsetx4_decode,
7612 - Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
7613 - { "uimm12x8", 3, -1, 0,
7615 - Operand_uimm12x8_encode, Operand_uimm12x8_decode,
7617 - { "simm4", 26, -1, 0,
7619 - Operand_simm4_encode, Operand_simm4_decode,
7621 - { "arr", 14, 0, 1,
7622 - XTENSA_OPERAND_IS_REGISTER,
7623 - Operand_arr_encode, Operand_arr_decode,
7626 - XTENSA_OPERAND_IS_REGISTER,
7627 - Operand_ars_encode, Operand_ars_decode,
7629 - { "*ars_invisible", 5, 0, 1,
7630 - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
7631 - Operand_ars_encode, Operand_ars_decode,
7634 - XTENSA_OPERAND_IS_REGISTER,
7635 - Operand_art_encode, Operand_art_decode,
7637 - { "ar0", 123, 0, 1,
7638 - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
7639 - Operand_ar0_encode, Operand_ar0_decode,
7641 - { "ar4", 124, 0, 1,
7642 - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
7643 - Operand_ar4_encode, Operand_ar4_decode,
7645 - { "ar8", 125, 0, 1,
7646 - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
7647 - Operand_ar8_encode, Operand_ar8_decode,
7649 - { "ar12", 126, 0, 1,
7650 - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
7651 - Operand_ar12_encode, Operand_ar12_decode,
7653 - { "ars_entry", 5, 0, 1,
7654 - XTENSA_OPERAND_IS_REGISTER,
7655 - Operand_ars_entry_encode, Operand_ars_entry_decode,
7657 - { "immrx4", 14, -1, 0,
7659 - Operand_immrx4_encode, Operand_immrx4_decode,
7661 - { "lsi4x4", 14, -1, 0,
7663 - Operand_lsi4x4_encode, Operand_lsi4x4_decode,
7665 - { "simm7", 34, -1, 0,
7667 - Operand_simm7_encode, Operand_simm7_decode,
7669 - { "uimm6", 33, -1, 0,
7670 - XTENSA_OPERAND_IS_PCRELATIVE,
7671 - Operand_uimm6_encode, Operand_uimm6_decode,
7672 - Operand_uimm6_ator, Operand_uimm6_rtoa },
7673 - { "ai4const", 0, -1, 0,
7675 - Operand_ai4const_encode, Operand_ai4const_decode,
7677 - { "b4const", 14, -1, 0,
7679 - Operand_b4const_encode, Operand_b4const_decode,
7681 - { "b4constu", 14, -1, 0,
7683 - Operand_b4constu_encode, Operand_b4constu_decode,
7685 - { "uimm8", 4, -1, 0,
7687 - Operand_uimm8_encode, Operand_uimm8_decode,
7689 - { "uimm8x2", 4, -1, 0,
7691 - Operand_uimm8x2_encode, Operand_uimm8x2_decode,
7693 - { "uimm8x4", 4, -1, 0,
7695 - Operand_uimm8x4_encode, Operand_uimm8x4_decode,
7697 - { "uimm4x16", 13, -1, 0,
7699 - Operand_uimm4x16_encode, Operand_uimm4x16_decode,
7701 - { "simm8", 4, -1, 0,
7703 - Operand_simm8_encode, Operand_simm8_decode,
7705 - { "simm8x256", 4, -1, 0,
7707 - Operand_simm8x256_encode, Operand_simm8x256_decode,
7709 - { "simm12b", 6, -1, 0,
7711 - Operand_simm12b_encode, Operand_simm12b_decode,
7713 - { "msalp32", 18, -1, 0,
7715 - Operand_msalp32_encode, Operand_msalp32_decode,
7717 - { "op2p1", 13, -1, 0,
7719 - Operand_op2p1_encode, Operand_op2p1_decode,
7721 - { "label8", 4, -1, 0,
7722 - XTENSA_OPERAND_IS_PCRELATIVE,
7723 - Operand_label8_encode, Operand_label8_decode,
7724 - Operand_label8_ator, Operand_label8_rtoa },
7725 - { "ulabel8", 4, -1, 0,
7726 - XTENSA_OPERAND_IS_PCRELATIVE,
7727 - Operand_ulabel8_encode, Operand_ulabel8_decode,
7728 - Operand_ulabel8_ator, Operand_ulabel8_rtoa },
7729 - { "label12", 3, -1, 0,
7730 - XTENSA_OPERAND_IS_PCRELATIVE,
7731 - Operand_label12_encode, Operand_label12_decode,
7732 - Operand_label12_ator, Operand_label12_rtoa },
7733 - { "soffset", 10, -1, 0,
7734 - XTENSA_OPERAND_IS_PCRELATIVE,
7735 - Operand_soffset_encode, Operand_soffset_decode,
7736 - Operand_soffset_ator, Operand_soffset_rtoa },
7737 - { "uimm16x4", 7, -1, 0,
7738 - XTENSA_OPERAND_IS_PCRELATIVE,
7739 - Operand_uimm16x4_encode, Operand_uimm16x4_decode,
7740 - Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
7742 - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
7743 - Operand_mx_encode, Operand_mx_decode,
7746 - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
7747 - Operand_my_encode, Operand_my_decode,
7750 - XTENSA_OPERAND_IS_REGISTER,
7751 - Operand_mw_encode, Operand_mw_decode,
7753 - { "mr0", 127, 1, 1,
7754 - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
7755 - Operand_mr0_encode, Operand_mr0_decode,
7757 - { "mr1", 128, 1, 1,
7758 - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
7759 - Operand_mr1_encode, Operand_mr1_decode,
7761 - { "mr2", 129, 1, 1,
7762 - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
7763 - Operand_mr2_encode, Operand_mr2_decode,
7765 - { "mr3", 130, 1, 1,
7766 - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
7767 - Operand_mr3_encode, Operand_mr3_decode,
7769 - { "immt", 0, -1, 0,
7771 - Operand_immt_encode, Operand_immt_decode,
7773 - { "imms", 5, -1, 0,
7775 - Operand_imms_encode, Operand_imms_decode,
7778 - XTENSA_OPERAND_IS_REGISTER,
7779 - Operand_bt_encode, Operand_bt_decode,
7782 - XTENSA_OPERAND_IS_REGISTER,
7783 - Operand_bs_encode, Operand_bs_decode,
7786 - XTENSA_OPERAND_IS_REGISTER,
7787 - Operand_br_encode, Operand_br_decode,
7789 - { "bt2", 44, 2, 2,
7790 - XTENSA_OPERAND_IS_REGISTER,
7791 - Operand_bt2_encode, Operand_bt2_decode,
7793 - { "bs2", 45, 2, 2,
7794 - XTENSA_OPERAND_IS_REGISTER,
7795 - Operand_bs2_encode, Operand_bs2_decode,
7797 - { "br2", 46, 2, 2,
7798 - XTENSA_OPERAND_IS_REGISTER,
7799 - Operand_br2_encode, Operand_br2_decode,
7801 - { "bt4", 47, 2, 4,
7802 - XTENSA_OPERAND_IS_REGISTER,
7803 - Operand_bt4_encode, Operand_bt4_decode,
7805 - { "bs4", 48, 2, 4,
7806 - XTENSA_OPERAND_IS_REGISTER,
7807 - Operand_bs4_encode, Operand_bs4_decode,
7809 - { "br4", 49, 2, 4,
7810 - XTENSA_OPERAND_IS_REGISTER,
7811 - Operand_br4_encode, Operand_br4_decode,
7813 - { "bt8", 50, 2, 8,
7814 - XTENSA_OPERAND_IS_REGISTER,
7815 - Operand_bt8_encode, Operand_bt8_decode,
7817 - { "bs8", 51, 2, 8,
7818 - XTENSA_OPERAND_IS_REGISTER,
7819 - Operand_bs8_encode, Operand_bs8_decode,
7821 - { "br8", 52, 2, 8,
7822 - XTENSA_OPERAND_IS_REGISTER,
7823 - Operand_br8_encode, Operand_br8_decode,
7825 - { "bt16", 131, 2, 16,
7826 - XTENSA_OPERAND_IS_REGISTER,
7827 - Operand_bt16_encode, Operand_bt16_decode,
7829 - { "bs16", 132, 2, 16,
7830 - XTENSA_OPERAND_IS_REGISTER,
7831 - Operand_bs16_encode, Operand_bs16_decode,
7833 - { "br16", 133, 2, 16,
7834 - XTENSA_OPERAND_IS_REGISTER,
7835 - Operand_br16_encode, Operand_br16_decode,
7837 - { "brall", 134, 2, 16,
7838 - XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
7839 - Operand_brall_encode, Operand_brall_decode,
7841 - { "tp7", 0, -1, 0,
7843 - Operand_tp7_encode, Operand_tp7_decode,
7845 - { "xt_wbr15_label", 53, -1, 0,
7846 - XTENSA_OPERAND_IS_PCRELATIVE,
7847 - Operand_xt_wbr15_label_encode, Operand_xt_wbr15_label_decode,
7848 - Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa },
7849 - { "xt_wbr18_label", 54, -1, 0,
7850 - XTENSA_OPERAND_IS_PCRELATIVE,
7851 - Operand_xt_wbr18_label_encode, Operand_xt_wbr18_label_decode,
7852 - Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa },
7853 - { "cimm8x4", 4, -1, 0,
7855 - Operand_cimm8x4_encode, Operand_cimm8x4_decode,
7857 - { "frr", 14, 3, 1,
7858 - XTENSA_OPERAND_IS_REGISTER,
7859 - Operand_frr_encode, Operand_frr_decode,
7862 - XTENSA_OPERAND_IS_REGISTER,
7863 - Operand_frs_encode, Operand_frs_decode,
7866 - XTENSA_OPERAND_IS_REGISTER,
7867 - Operand_frt_encode, Operand_frt_decode,
7869 - { "t", 0, -1, 0, 0, 0, 0, 0, 0 },
7870 - { "bbi4", 1, -1, 0, 0, 0, 0, 0, 0 },
7871 - { "bbi", 2, -1, 0, 0, 0, 0, 0, 0 },
7872 - { "imm12", 3, -1, 0, 0, 0, 0, 0, 0 },
7873 - { "imm8", 4, -1, 0, 0, 0, 0, 0, 0 },
7874 - { "s", 5, -1, 0, 0, 0, 0, 0, 0 },
7875 - { "imm12b", 6, -1, 0, 0, 0, 0, 0, 0 },
7876 - { "imm16", 7, -1, 0, 0, 0, 0, 0, 0 },
7877 - { "m", 8, -1, 0, 0, 0, 0, 0, 0 },
7878 - { "n", 9, -1, 0, 0, 0, 0, 0, 0 },
7879 - { "offset", 10, -1, 0, 0, 0, 0, 0, 0 },
7880 - { "op0", 11, -1, 0, 0, 0, 0, 0, 0 },
7881 - { "op1", 12, -1, 0, 0, 0, 0, 0, 0 },
7882 - { "op2", 13, -1, 0, 0, 0, 0, 0, 0 },
7883 - { "r", 14, -1, 0, 0, 0, 0, 0, 0 },
7884 - { "sa4", 15, -1, 0, 0, 0, 0, 0, 0 },
7885 - { "sae4", 16, -1, 0, 0, 0, 0, 0, 0 },
7886 - { "sae", 17, -1, 0, 0, 0, 0, 0, 0 },
7887 - { "sal", 18, -1, 0, 0, 0, 0, 0, 0 },
7888 - { "sargt", 19, -1, 0, 0, 0, 0, 0, 0 },
7889 - { "sas4", 20, -1, 0, 0, 0, 0, 0, 0 },
7890 - { "sas", 21, -1, 0, 0, 0, 0, 0, 0 },
7891 - { "sr", 22, -1, 0, 0, 0, 0, 0, 0 },
7892 - { "st", 23, -1, 0, 0, 0, 0, 0, 0 },
7893 - { "thi3", 24, -1, 0, 0, 0, 0, 0, 0 },
7894 - { "imm4", 25, -1, 0, 0, 0, 0, 0, 0 },
7895 - { "mn", 26, -1, 0, 0, 0, 0, 0, 0 },
7896 - { "i", 27, -1, 0, 0, 0, 0, 0, 0 },
7897 - { "imm6lo", 28, -1, 0, 0, 0, 0, 0, 0 },
7898 - { "imm6hi", 29, -1, 0, 0, 0, 0, 0, 0 },
7899 - { "imm7lo", 30, -1, 0, 0, 0, 0, 0, 0 },
7900 - { "imm7hi", 31, -1, 0, 0, 0, 0, 0, 0 },
7901 - { "z", 32, -1, 0, 0, 0, 0, 0, 0 },
7902 - { "imm6", 33, -1, 0, 0, 0, 0, 0, 0 },
7903 - { "imm7", 34, -1, 0, 0, 0, 0, 0, 0 },
7904 - { "r3", 35, -1, 0, 0, 0, 0, 0, 0 },
7905 - { "rbit2", 36, -1, 0, 0, 0, 0, 0, 0 },
7906 - { "rhi", 37, -1, 0, 0, 0, 0, 0, 0 },
7907 - { "t3", 38, -1, 0, 0, 0, 0, 0, 0 },
7908 - { "tbit2", 39, -1, 0, 0, 0, 0, 0, 0 },
7909 - { "tlo", 40, -1, 0, 0, 0, 0, 0, 0 },
7910 - { "w", 41, -1, 0, 0, 0, 0, 0, 0 },
7911 - { "y", 42, -1, 0, 0, 0, 0, 0, 0 },
7912 - { "x", 43, -1, 0, 0, 0, 0, 0, 0 },
7913 - { "t2", 44, -1, 0, 0, 0, 0, 0, 0 },
7914 - { "s2", 45, -1, 0, 0, 0, 0, 0, 0 },
7915 - { "r2", 46, -1, 0, 0, 0, 0, 0, 0 },
7916 - { "t4", 47, -1, 0, 0, 0, 0, 0, 0 },
7917 - { "s4", 48, -1, 0, 0, 0, 0, 0, 0 },
7918 - { "r4", 49, -1, 0, 0, 0, 0, 0, 0 },
7919 - { "t8", 50, -1, 0, 0, 0, 0, 0, 0 },
7920 - { "s8", 51, -1, 0, 0, 0, 0, 0, 0 },
7921 - { "r8", 52, -1, 0, 0, 0, 0, 0, 0 },
7922 - { "xt_wbr15_imm", 53, -1, 0, 0, 0, 0, 0, 0 },
7923 - { "xt_wbr18_imm", 54, -1, 0, 0, 0, 0, 0, 0 },
7924 - { "op0_xt_flix64_slot0_s3", 55, -1, 0, 0, 0, 0, 0, 0 },
7925 - { "combined3e2c5767_fld7", 56, -1, 0, 0, 0, 0, 0, 0 },
7926 - { "combined3e2c5767_fld8", 57, -1, 0, 0, 0, 0, 0, 0 },
7927 - { "combined3e2c5767_fld9", 58, -1, 0, 0, 0, 0, 0, 0 },
7928 - { "combined3e2c5767_fld11", 59, -1, 0, 0, 0, 0, 0, 0 },
7929 - { "combined3e2c5767_fld49xt_flix64_slot0", 60, -1, 0, 0, 0, 0, 0, 0 },
7930 - { "op0_s4", 61, -1, 0, 0, 0, 0, 0, 0 },
7931 - { "combined3e2c5767_fld16", 62, -1, 0, 0, 0, 0, 0, 0 },
7932 - { "combined3e2c5767_fld19xt_flix64_slot1", 63, -1, 0, 0, 0, 0, 0, 0 },
7933 - { "combined3e2c5767_fld20xt_flix64_slot1", 64, -1, 0, 0, 0, 0, 0, 0 },
7934 - { "combined3e2c5767_fld21xt_flix64_slot1", 65, -1, 0, 0, 0, 0, 0, 0 },
7935 - { "combined3e2c5767_fld22xt_flix64_slot1", 66, -1, 0, 0, 0, 0, 0, 0 },
7936 - { "combined3e2c5767_fld23xt_flix64_slot1", 67, -1, 0, 0, 0, 0, 0, 0 },
7937 - { "combined3e2c5767_fld25xt_flix64_slot1", 68, -1, 0, 0, 0, 0, 0, 0 },
7938 - { "combined3e2c5767_fld26xt_flix64_slot1", 69, -1, 0, 0, 0, 0, 0, 0 },
7939 - { "combined3e2c5767_fld28xt_flix64_slot1", 70, -1, 0, 0, 0, 0, 0, 0 },
7940 - { "combined3e2c5767_fld30xt_flix64_slot1", 71, -1, 0, 0, 0, 0, 0, 0 },
7941 - { "combined3e2c5767_fld32xt_flix64_slot1", 72, -1, 0, 0, 0, 0, 0, 0 },
7942 - { "combined3e2c5767_fld33xt_flix64_slot1", 73, -1, 0, 0, 0, 0, 0, 0 },
7943 - { "combined3e2c5767_fld35xt_flix64_slot1", 74, -1, 0, 0, 0, 0, 0, 0 },
7944 - { "combined3e2c5767_fld51xt_flix64_slot1", 75, -1, 0, 0, 0, 0, 0, 0 },
7945 - { "combined3e2c5767_fld52xt_flix64_slot1", 76, -1, 0, 0, 0, 0, 0, 0 },
7946 - { "combined3e2c5767_fld53xt_flix64_slot1", 77, -1, 0, 0, 0, 0, 0, 0 },
7947 - { "combined3e2c5767_fld54xt_flix64_slot1", 78, -1, 0, 0, 0, 0, 0, 0 },
7948 - { "combined3e2c5767_fld57xt_flix64_slot1", 79, -1, 0, 0, 0, 0, 0, 0 },
7949 - { "combined3e2c5767_fld58xt_flix64_slot1", 80, -1, 0, 0, 0, 0, 0, 0 },
7950 - { "combined3e2c5767_fld60xt_flix64_slot1", 81, -1, 0, 0, 0, 0, 0, 0 },
7951 - { "combined3e2c5767_fld62xt_flix64_slot1", 82, -1, 0, 0, 0, 0, 0, 0 },
7952 - { "op0_s5", 83, -1, 0, 0, 0, 0, 0, 0 },
7953 - { "combined3e2c5767_fld36xt_flix64_slot2", 84, -1, 0, 0, 0, 0, 0, 0 },
7954 - { "combined3e2c5767_fld37xt_flix64_slot2", 85, -1, 0, 0, 0, 0, 0, 0 },
7955 - { "combined3e2c5767_fld39xt_flix64_slot2", 86, -1, 0, 0, 0, 0, 0, 0 },
7956 - { "combined3e2c5767_fld41xt_flix64_slot2", 87, -1, 0, 0, 0, 0, 0, 0 },
7957 - { "combined3e2c5767_fld42xt_flix64_slot2", 88, -1, 0, 0, 0, 0, 0, 0 },
7958 - { "combined3e2c5767_fld44xt_flix64_slot2", 89, -1, 0, 0, 0, 0, 0, 0 },
7959 - { "combined3e2c5767_fld45xt_flix64_slot2", 90, -1, 0, 0, 0, 0, 0, 0 },
7960 - { "combined3e2c5767_fld47xt_flix64_slot2", 91, -1, 0, 0, 0, 0, 0, 0 },
7961 - { "combined3e2c5767_fld63xt_flix64_slot2", 92, -1, 0, 0, 0, 0, 0, 0 },
7962 - { "combined3e2c5767_fld64xt_flix64_slot2", 93, -1, 0, 0, 0, 0, 0, 0 },
7963 - { "combined3e2c5767_fld65xt_flix64_slot2", 94, -1, 0, 0, 0, 0, 0, 0 },
7964 - { "combined3e2c5767_fld66xt_flix64_slot2", 95, -1, 0, 0, 0, 0, 0, 0 },
7965 - { "combined3e2c5767_fld68xt_flix64_slot2", 96, -1, 0, 0, 0, 0, 0, 0 },
7966 - { "op0_s6", 97, -1, 0, 0, 0, 0, 0, 0 },
7967 - { "combined3e2c5767_fld70xt_flix64_slot3", 98, -1, 0, 0, 0, 0, 0, 0 },
7968 - { "combined3e2c5767_fld71", 99, -1, 0, 0, 0, 0, 0, 0 },
7969 - { "combined3e2c5767_fld72xt_flix64_slot3", 100, -1, 0, 0, 0, 0, 0, 0 },
7970 - { "combined3e2c5767_fld73xt_flix64_slot3", 101, -1, 0, 0, 0, 0, 0, 0 },
7971 - { "combined3e2c5767_fld74xt_flix64_slot3", 102, -1, 0, 0, 0, 0, 0, 0 },
7972 - { "combined3e2c5767_fld75xt_flix64_slot3", 103, -1, 0, 0, 0, 0, 0, 0 },
7973 - { "combined3e2c5767_fld76xt_flix64_slot3", 104, -1, 0, 0, 0, 0, 0, 0 },
7974 - { "combined3e2c5767_fld77xt_flix64_slot3", 105, -1, 0, 0, 0, 0, 0, 0 },
7975 - { "combined3e2c5767_fld78xt_flix64_slot3", 106, -1, 0, 0, 0, 0, 0, 0 },
7976 - { "combined3e2c5767_fld79xt_flix64_slot3", 107, -1, 0, 0, 0, 0, 0, 0 },
7977 - { "combined3e2c5767_fld80xt_flix64_slot3", 108, -1, 0, 0, 0, 0, 0, 0 },
7978 - { "combined3e2c5767_fld81xt_flix64_slot3", 109, -1, 0, 0, 0, 0, 0, 0 },
7979 - { "combined3e2c5767_fld82xt_flix64_slot3", 110, -1, 0, 0, 0, 0, 0, 0 },
7980 - { "combined3e2c5767_fld83xt_flix64_slot3", 111, -1, 0, 0, 0, 0, 0, 0 },
7981 - { "combined3e2c5767_fld84xt_flix64_slot3", 112, -1, 0, 0, 0, 0, 0, 0 },
7982 - { "combined3e2c5767_fld85xt_flix64_slot3", 113, -1, 0, 0, 0, 0, 0, 0 },
7983 - { "combined3e2c5767_fld86xt_flix64_slot3", 114, -1, 0, 0, 0, 0, 0, 0 },
7984 - { "combined3e2c5767_fld87xt_flix64_slot3", 115, -1, 0, 0, 0, 0, 0, 0 },
7985 - { "combined3e2c5767_fld88xt_flix64_slot3", 116, -1, 0, 0, 0, 0, 0, 0 },
7986 - { "combined3e2c5767_fld89xt_flix64_slot3", 117, -1, 0, 0, 0, 0, 0, 0 },
7987 - { "combined3e2c5767_fld90xt_flix64_slot3", 118, -1, 0, 0, 0, 0, 0, 0 },
7988 - { "combined3e2c5767_fld91xt_flix64_slot3", 119, -1, 0, 0, 0, 0, 0, 0 },
7989 - { "combined3e2c5767_fld92xt_flix64_slot3", 120, -1, 0, 0, 0, 0, 0, 0 },
7990 - { "combined3e2c5767_fld93xt_flix64_slot3", 121, -1, 0, 0, 0, 0, 0, 0 },
7991 - { "op0_xt_flix64_slot0", 122, -1, 0, 0, 0, 0, 0, 0 }
7992 +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = {
7993 + { { STATE_CCOUNT }, 'i' }
7997 -/* Iclass table. */
7999 -static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
8000 - { { STATE_PSRING }, 'i' },
8001 - { { STATE_PSEXCM }, 'm' },
8002 - { { STATE_EPC1 }, 'i' }
8003 +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = {
8004 + { { 6 /* art */ }, 'i' }
8007 -static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
8008 - { { STATE_PSEXCM }, 'i' },
8009 - { { STATE_PSRING }, 'i' },
8010 - { { STATE_DEPC }, 'i' }
8011 +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = {
8012 + { { STATE_XTSYNC }, 'o' },
8013 + { { STATE_CCOUNT }, 'o' }
8016 -static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
8017 - { { 0 /* soffsetx4 */ }, 'i' },
8018 - { { 10 /* ar12 */ }, 'o' }
8019 +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = {
8020 + { { 6 /* art */ }, 'm' }
8023 -static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
8024 - { { STATE_PSCALLINC }, 'o' }
8025 +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = {
8026 + { { STATE_XTSYNC }, 'o' },
8027 + { { STATE_CCOUNT }, 'm' }
8030 -static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
8031 - { { 0 /* soffsetx4 */ }, 'i' },
8032 - { { 9 /* ar8 */ }, 'o' }
8035 -static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
8036 - { { STATE_PSCALLINC }, 'o' }
8039 -static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
8040 - { { 0 /* soffsetx4 */ }, 'i' },
8041 - { { 8 /* ar4 */ }, 'o' }
8044 -static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
8045 - { { STATE_PSCALLINC }, 'o' }
8048 -static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
8049 - { { 4 /* ars */ }, 'i' },
8050 - { { 10 /* ar12 */ }, 'o' }
8051 +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = {
8052 + { { 6 /* art */ }, 'o' }
8055 -static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
8056 - { { STATE_PSCALLINC }, 'o' }
8057 +static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = {
8058 + { { STATE_CCOMPARE0 }, 'i' }
8061 -static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
8062 - { { 4 /* ars */ }, 'i' },
8063 - { { 9 /* ar8 */ }, 'o' }
8064 +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = {
8065 + { { 6 /* art */ }, 'i' }
8068 -static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
8069 - { { STATE_PSCALLINC }, 'o' }
8070 +static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = {
8071 + { { STATE_CCOMPARE0 }, 'o' },
8072 + { { STATE_INTERRUPT }, 'm' }
8075 -static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
8076 - { { 4 /* ars */ }, 'i' },
8077 - { { 8 /* ar4 */ }, 'o' }
8078 +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = {
8079 + { { 6 /* art */ }, 'm' }
8082 -static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
8083 - { { STATE_PSCALLINC }, 'o' }
8084 +static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = {
8085 + { { STATE_CCOMPARE0 }, 'm' },
8086 + { { STATE_INTERRUPT }, 'm' }
8089 -static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
8090 - { { 11 /* ars_entry */ }, 's' },
8091 - { { 4 /* ars */ }, 'i' },
8092 - { { 1 /* uimm12x8 */ }, 'i' }
8093 +static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = {
8094 + { { 4 /* ars */ }, 'i' }
8097 -static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
8098 - { { STATE_PSCALLINC }, 'i' },
8099 - { { STATE_PSEXCM }, 'i' },
8100 - { { STATE_PSWOE }, 'i' },
8101 - { { STATE_WindowBase }, 'm' },
8102 - { { STATE_WindowStart }, 'm' }
8103 +static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = {
8104 + { { STATE_XTSYNC }, 'o' }
8107 -static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
8108 +static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = {
8109 { { 6 /* art */ }, 'o' },
8110 { { 4 /* ars */ }, 'i' }
8113 -static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
8114 - { { STATE_WindowBase }, 'i' },
8115 - { { STATE_WindowStart }, 'i' }
8118 -static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
8119 - { { 2 /* simm4 */ }, 'i' }
8122 -static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
8123 - { { STATE_PSEXCM }, 'i' },
8124 - { { STATE_PSRING }, 'i' },
8125 - { { STATE_WindowBase }, 'm' }
8128 -static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
8129 - { { 5 /* *ars_invisible */ }, 'i' }
8130 +static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = {
8131 + { { 6 /* art */ }, 'i' },
8132 + { { 4 /* ars */ }, 'i' }
8135 -static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
8136 - { { STATE_WindowBase }, 'm' },
8137 - { { STATE_WindowStart }, 'm' },
8138 - { { STATE_PSEXCM }, 'i' },
8139 - { { STATE_PSWOE }, 'i' }
8140 +static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = {
8141 + { { STATE_XTSYNC }, 'o' }
8144 -static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
8145 - { { STATE_EPC1 }, 'i' },
8146 - { { STATE_PSEXCM }, 'm' },
8147 - { { STATE_PSRING }, 'i' },
8148 - { { STATE_WindowBase }, 'm' },
8149 - { { STATE_WindowStart }, 'm' },
8150 - { { STATE_PSOWB }, 'i' }
8151 +static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = {
8152 + { { 4 /* ars */ }, 'i' }
8155 -static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
8156 +static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = {
8157 { { 6 /* art */ }, 'o' },
8158 - { { 4 /* ars */ }, 'i' },
8159 - { { 12 /* immrx4 */ }, 'i' }
8162 -static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = {
8163 - { { STATE_PSEXCM }, 'i' },
8164 - { { STATE_PSRING }, 'i' }
8165 + { { 4 /* ars */ }, 'i' }
8168 -static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
8169 +static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = {
8170 { { 6 /* art */ }, 'i' },
8171 - { { 4 /* ars */ }, 'i' },
8172 - { { 12 /* immrx4 */ }, 'i' }
8175 -static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = {
8176 - { { STATE_PSEXCM }, 'i' },
8177 - { { STATE_PSRING }, 'i' }
8180 -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
8181 - { { 6 /* art */ }, 'o' }
8184 -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
8185 - { { STATE_PSEXCM }, 'i' },
8186 - { { STATE_PSRING }, 'i' },
8187 - { { STATE_WindowBase }, 'i' }
8190 -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
8191 - { { 6 /* art */ }, 'i' }
8194 -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
8195 - { { STATE_PSEXCM }, 'i' },
8196 - { { STATE_PSRING }, 'i' },
8197 - { { STATE_WindowBase }, 'o' }
8200 -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
8201 - { { 6 /* art */ }, 'm' }
8204 -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
8205 - { { STATE_PSEXCM }, 'i' },
8206 - { { STATE_PSRING }, 'i' },
8207 - { { STATE_WindowBase }, 'm' }
8210 -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
8211 - { { 6 /* art */ }, 'o' }
8214 -static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
8215 - { { STATE_PSEXCM }, 'i' },
8216 - { { STATE_PSRING }, 'i' },
8217 - { { STATE_WindowStart }, 'i' }
8220 -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
8221 - { { 6 /* art */ }, 'i' }
8224 -static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
8225 - { { STATE_PSEXCM }, 'i' },
8226 - { { STATE_PSRING }, 'i' },
8227 - { { STATE_WindowStart }, 'o' }
8230 -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
8231 - { { 6 /* art */ }, 'm' }
8234 -static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
8235 - { { STATE_PSEXCM }, 'i' },
8236 - { { STATE_PSRING }, 'i' },
8237 - { { STATE_WindowStart }, 'm' }
8238 + { { 4 /* ars */ }, 'i' }
8241 -static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
8242 +static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = {
8243 { { 3 /* arr */ }, 'o' },
8244 { { 4 /* ars */ }, 'i' },
8245 { { 6 /* art */ }, 'i' }
8248 -static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
8249 - { { 3 /* arr */ }, 'o' },
8250 - { { 4 /* ars */ }, 'i' },
8251 - { { 16 /* ai4const */ }, 'i' }
8252 +static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = {
8253 + { { 6 /* art */ }, 'o' },
8254 + { { 4 /* ars */ }, 'i' }
8257 -static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
8258 +static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = {
8259 + { { 3 /* arr */ }, 'o' },
8260 { { 4 /* ars */ }, 'i' },
8261 - { { 15 /* uimm6 */ }, 'i' }
8262 + { { 35 /* tp7 */ }, 'i' }
8265 -static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
8266 +static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = {
8267 { { 6 /* art */ }, 'o' },
8268 { { 4 /* ars */ }, 'i' },
8269 - { { 13 /* lsi4x4 */ }, 'i' }
8272 -static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
8273 - { { 6 /* art */ }, 'o' },
8274 - { { 4 /* ars */ }, 'i' }
8277 -static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
8278 - { { 4 /* ars */ }, 'o' },
8279 - { { 14 /* simm7 */ }, 'i' }
8280 + { { 21 /* uimm8x4 */ }, 'i' }
8283 -static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
8284 - { { 5 /* *ars_invisible */ }, 'i' }
8285 +static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = {
8286 + { { 6 /* art */ }, 'i' },
8287 + { { 4 /* ars */ }, 'i' },
8288 + { { 21 /* uimm8x4 */ }, 'i' }
8291 -static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
8292 - { { 6 /* art */ }, 'i' },
8293 +static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = {
8294 + { { 6 /* art */ }, 'm' },
8295 { { 4 /* ars */ }, 'i' },
8296 - { { 13 /* lsi4x4 */ }, 'i' }
8297 + { { 21 /* uimm8x4 */ }, 'i' }
8300 -static xtensa_arg_internal Iclass_rur_threadptr_args[] = {
8301 - { { 3 /* arr */ }, 'o' }
8302 +static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = {
8303 + { { STATE_SCOMPARE1 }, 'i' },
8304 + { { STATE_SCOMPARE1 }, 'i' }
8307 -static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = {
8308 - { { STATE_THREADPTR }, 'i' }
8309 +static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = {
8310 + { { 6 /* art */ }, 'o' }
8313 -static xtensa_arg_internal Iclass_wur_threadptr_args[] = {
8314 - { { 6 /* art */ }, 'i' }
8315 +static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = {
8316 + { { STATE_SCOMPARE1 }, 'i' }
8319 -static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = {
8320 - { { STATE_THREADPTR }, 'o' }
8321 +static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = {
8322 + { { 6 /* art */ }, 'i' }
8325 -static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
8326 - { { 6 /* art */ }, 'o' },
8327 - { { 4 /* ars */ }, 'i' },
8328 - { { 23 /* simm8 */ }, 'i' }
8329 +static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = {
8330 + { { STATE_SCOMPARE1 }, 'o' }
8333 -static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
8334 - { { 6 /* art */ }, 'o' },
8335 - { { 4 /* ars */ }, 'i' },
8336 - { { 24 /* simm8x256 */ }, 'i' }
8337 +static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = {
8338 + { { 6 /* art */ }, 'm' }
8341 -static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
8342 - { { 3 /* arr */ }, 'o' },
8343 - { { 4 /* ars */ }, 'i' },
8344 - { { 6 /* art */ }, 'i' }
8345 +static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = {
8346 + { { STATE_SCOMPARE1 }, 'm' }
8349 -static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
8350 +static xtensa_arg_internal Iclass_xt_mul32_args[] = {
8351 { { 3 /* arr */ }, 'o' },
8352 { { 4 /* ars */ }, 'i' },
8353 { { 6 /* art */ }, 'i' }
8356 -static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
8357 - { { 4 /* ars */ }, 'i' },
8358 - { { 17 /* b4const */ }, 'i' },
8359 - { { 28 /* label8 */ }, 'i' }
8362 -static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
8363 - { { 4 /* ars */ }, 'i' },
8364 - { { 67 /* bbi */ }, 'i' },
8365 - { { 28 /* label8 */ }, 'i' }
8368 -static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
8369 - { { 4 /* ars */ }, 'i' },
8370 - { { 18 /* b4constu */ }, 'i' },
8371 - { { 28 /* label8 */ }, 'i' }
8374 -static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
8375 - { { 4 /* ars */ }, 'i' },
8376 - { { 6 /* art */ }, 'i' },
8377 - { { 28 /* label8 */ }, 'i' }
8380 -static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
8381 - { { 4 /* ars */ }, 'i' },
8382 - { { 30 /* label12 */ }, 'i' }
8385 -static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
8386 - { { 0 /* soffsetx4 */ }, 'i' },
8387 - { { 7 /* ar0 */ }, 'o' }
8390 -static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
8391 - { { 4 /* ars */ }, 'i' },
8392 - { { 7 /* ar0 */ }, 'o' }
8395 -static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
8396 - { { 3 /* arr */ }, 'o' },
8397 - { { 6 /* art */ }, 'i' },
8398 - { { 82 /* sae */ }, 'i' },
8399 - { { 27 /* op2p1 */ }, 'i' }
8402 -static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
8403 - { { 31 /* soffset */ }, 'i' }
8406 -static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
8407 - { { 4 /* ars */ }, 'i' }
8410 -static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
8411 - { { 6 /* art */ }, 'o' },
8412 - { { 4 /* ars */ }, 'i' },
8413 - { { 20 /* uimm8x2 */ }, 'i' }
8416 -static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
8417 - { { 6 /* art */ }, 'o' },
8418 - { { 4 /* ars */ }, 'i' },
8419 - { { 20 /* uimm8x2 */ }, 'i' }
8422 -static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
8423 - { { 6 /* art */ }, 'o' },
8424 - { { 4 /* ars */ }, 'i' },
8425 - { { 21 /* uimm8x4 */ }, 'i' }
8428 -static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
8429 - { { 6 /* art */ }, 'o' },
8430 - { { 32 /* uimm16x4 */ }, 'i' }
8433 -static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = {
8434 - { { STATE_LITBADDR }, 'i' },
8435 - { { STATE_LITBEN }, 'i' }
8438 -static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
8439 - { { 6 /* art */ }, 'o' },
8440 - { { 4 /* ars */ }, 'i' },
8441 - { { 19 /* uimm8 */ }, 'i' }
8444 -static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = {
8445 - { { 4 /* ars */ }, 'i' },
8446 - { { 29 /* ulabel8 */ }, 'i' }
8449 -static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = {
8450 - { { STATE_LBEG }, 'o' },
8451 - { { STATE_LEND }, 'o' },
8452 - { { STATE_LCOUNT }, 'o' }
8455 -static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = {
8456 - { { 4 /* ars */ }, 'i' },
8457 - { { 29 /* ulabel8 */ }, 'i' }
8460 -static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = {
8461 - { { STATE_LBEG }, 'o' },
8462 - { { STATE_LEND }, 'o' },
8463 - { { STATE_LCOUNT }, 'o' }
8466 -static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
8467 - { { 6 /* art */ }, 'o' },
8468 - { { 25 /* simm12b */ }, 'i' }
8471 -static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
8472 - { { 3 /* arr */ }, 'm' },
8473 - { { 4 /* ars */ }, 'i' },
8474 - { { 6 /* art */ }, 'i' }
8477 -static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
8478 - { { 3 /* arr */ }, 'o' },
8479 - { { 6 /* art */ }, 'i' }
8482 -static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
8483 - { { 5 /* *ars_invisible */ }, 'i' }
8486 -static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
8487 - { { 6 /* art */ }, 'i' },
8488 - { { 4 /* ars */ }, 'i' },
8489 - { { 20 /* uimm8x2 */ }, 'i' }
8492 -static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
8493 - { { 6 /* art */ }, 'i' },
8494 - { { 4 /* ars */ }, 'i' },
8495 - { { 21 /* uimm8x4 */ }, 'i' }
8498 -static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
8499 - { { 6 /* art */ }, 'i' },
8500 - { { 4 /* ars */ }, 'i' },
8501 - { { 19 /* uimm8 */ }, 'i' }
8504 -static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
8505 - { { 4 /* ars */ }, 'i' }
8508 -static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
8509 - { { STATE_SAR }, 'o' }
8512 -static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
8513 - { { 86 /* sas */ }, 'i' }
8516 -static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
8517 - { { STATE_SAR }, 'o' }
8520 -static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
8521 - { { 3 /* arr */ }, 'o' },
8522 - { { 4 /* ars */ }, 'i' }
8525 -static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
8526 - { { STATE_SAR }, 'i' }
8529 -static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
8530 - { { 3 /* arr */ }, 'o' },
8531 - { { 4 /* ars */ }, 'i' },
8532 - { { 6 /* art */ }, 'i' }
8535 -static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
8536 - { { STATE_SAR }, 'i' }
8539 -static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
8540 - { { 3 /* arr */ }, 'o' },
8541 - { { 6 /* art */ }, 'i' }
8544 -static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
8545 - { { STATE_SAR }, 'i' }
8548 -static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
8549 - { { 3 /* arr */ }, 'o' },
8550 - { { 4 /* ars */ }, 'i' },
8551 - { { 26 /* msalp32 */ }, 'i' }
8554 -static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
8555 - { { 3 /* arr */ }, 'o' },
8556 - { { 6 /* art */ }, 'i' },
8557 - { { 84 /* sargt */ }, 'i' }
8560 -static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
8561 - { { 3 /* arr */ }, 'o' },
8562 - { { 6 /* art */ }, 'i' },
8563 - { { 70 /* s */ }, 'i' }
8566 -static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
8567 - { { STATE_XTSYNC }, 'i' }
8570 -static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
8571 - { { 6 /* art */ }, 'o' },
8572 - { { 70 /* s */ }, 'i' }
8575 -static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
8576 - { { STATE_PSWOE }, 'i' },
8577 - { { STATE_PSCALLINC }, 'i' },
8578 - { { STATE_PSOWB }, 'i' },
8579 - { { STATE_PSRING }, 'i' },
8580 - { { STATE_PSUM }, 'i' },
8581 - { { STATE_PSEXCM }, 'i' },
8582 - { { STATE_PSINTLEVEL }, 'm' }
8585 -static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = {
8586 - { { 6 /* art */ }, 'o' }
8589 -static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = {
8590 - { { STATE_LEND }, 'i' }
8593 -static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = {
8594 - { { 6 /* art */ }, 'i' }
8597 -static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = {
8598 - { { STATE_LEND }, 'o' }
8601 -static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = {
8602 - { { 6 /* art */ }, 'm' }
8605 -static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = {
8606 - { { STATE_LEND }, 'm' }
8609 -static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = {
8610 - { { 6 /* art */ }, 'o' }
8613 -static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = {
8614 - { { STATE_LCOUNT }, 'i' }
8617 -static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = {
8618 - { { 6 /* art */ }, 'i' }
8621 -static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = {
8622 - { { STATE_XTSYNC }, 'o' },
8623 - { { STATE_LCOUNT }, 'o' }
8626 -static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = {
8627 - { { 6 /* art */ }, 'm' }
8630 -static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = {
8631 - { { STATE_XTSYNC }, 'o' },
8632 - { { STATE_LCOUNT }, 'm' }
8635 -static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = {
8636 - { { 6 /* art */ }, 'o' }
8639 -static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = {
8640 - { { STATE_LBEG }, 'i' }
8643 -static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = {
8644 - { { 6 /* art */ }, 'i' }
8647 -static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = {
8648 - { { STATE_LBEG }, 'o' }
8651 -static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = {
8652 - { { 6 /* art */ }, 'm' }
8655 -static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = {
8656 - { { STATE_LBEG }, 'm' }
8659 -static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
8660 - { { 6 /* art */ }, 'o' }
8663 -static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
8664 - { { STATE_SAR }, 'i' }
8667 -static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
8668 - { { 6 /* art */ }, 'i' }
8671 -static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
8672 - { { STATE_SAR }, 'o' },
8673 - { { STATE_XTSYNC }, 'o' }
8676 -static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
8677 - { { 6 /* art */ }, 'm' }
8680 -static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
8681 - { { STATE_SAR }, 'm' }
8684 -static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = {
8685 - { { 6 /* art */ }, 'o' }
8688 -static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = {
8689 - { { STATE_LITBADDR }, 'i' },
8690 - { { STATE_LITBEN }, 'i' }
8693 -static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = {
8694 - { { 6 /* art */ }, 'i' }
8697 -static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = {
8698 - { { STATE_LITBADDR }, 'o' },
8699 - { { STATE_LITBEN }, 'o' }
8702 -static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = {
8703 - { { 6 /* art */ }, 'm' }
8706 -static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = {
8707 - { { STATE_LITBADDR }, 'm' },
8708 - { { STATE_LITBEN }, 'm' }
8711 -static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = {
8712 - { { 6 /* art */ }, 'o' }
8715 -static xtensa_arg_internal Iclass_xt_iclass_rsr_176_stateArgs[] = {
8716 - { { STATE_PSEXCM }, 'i' },
8717 - { { STATE_PSRING }, 'i' }
8720 -static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = {
8721 - { { 6 /* art */ }, 'o' }
8724 -static xtensa_arg_internal Iclass_xt_iclass_rsr_208_stateArgs[] = {
8725 - { { STATE_PSEXCM }, 'i' },
8726 - { { STATE_PSRING }, 'i' }
8729 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
8730 - { { 6 /* art */ }, 'o' }
8733 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
8734 - { { STATE_PSWOE }, 'i' },
8735 - { { STATE_PSCALLINC }, 'i' },
8736 - { { STATE_PSOWB }, 'i' },
8737 - { { STATE_PSRING }, 'i' },
8738 - { { STATE_PSUM }, 'i' },
8739 - { { STATE_PSEXCM }, 'i' },
8740 - { { STATE_PSINTLEVEL }, 'i' }
8743 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
8744 - { { 6 /* art */ }, 'i' }
8747 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
8748 - { { STATE_PSWOE }, 'o' },
8749 - { { STATE_PSCALLINC }, 'o' },
8750 - { { STATE_PSOWB }, 'o' },
8751 - { { STATE_PSRING }, 'm' },
8752 - { { STATE_PSUM }, 'o' },
8753 - { { STATE_PSEXCM }, 'm' },
8754 - { { STATE_PSINTLEVEL }, 'o' }
8757 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
8758 - { { 6 /* art */ }, 'm' }
8761 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
8762 - { { STATE_PSWOE }, 'm' },
8763 - { { STATE_PSCALLINC }, 'm' },
8764 - { { STATE_PSOWB }, 'm' },
8765 - { { STATE_PSRING }, 'm' },
8766 - { { STATE_PSUM }, 'm' },
8767 - { { STATE_PSEXCM }, 'm' },
8768 - { { STATE_PSINTLEVEL }, 'm' }
8771 -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
8772 - { { 6 /* art */ }, 'o' }
8775 -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
8776 - { { STATE_PSEXCM }, 'i' },
8777 - { { STATE_PSRING }, 'i' },
8778 - { { STATE_EPC1 }, 'i' }
8781 -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
8782 - { { 6 /* art */ }, 'i' }
8785 -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
8786 - { { STATE_PSEXCM }, 'i' },
8787 - { { STATE_PSRING }, 'i' },
8788 - { { STATE_EPC1 }, 'o' }
8791 -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
8792 - { { 6 /* art */ }, 'm' }
8795 -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
8796 - { { STATE_PSEXCM }, 'i' },
8797 - { { STATE_PSRING }, 'i' },
8798 - { { STATE_EPC1 }, 'm' }
8801 -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
8802 - { { 6 /* art */ }, 'o' }
8805 -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
8806 - { { STATE_PSEXCM }, 'i' },
8807 - { { STATE_PSRING }, 'i' },
8808 - { { STATE_EXCSAVE1 }, 'i' }
8811 -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
8812 - { { 6 /* art */ }, 'i' }
8815 -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
8816 - { { STATE_PSEXCM }, 'i' },
8817 - { { STATE_PSRING }, 'i' },
8818 - { { STATE_EXCSAVE1 }, 'o' }
8821 -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
8822 - { { 6 /* art */ }, 'm' }
8825 -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
8826 - { { STATE_PSEXCM }, 'i' },
8827 - { { STATE_PSRING }, 'i' },
8828 - { { STATE_EXCSAVE1 }, 'm' }
8831 -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
8832 - { { 6 /* art */ }, 'o' }
8835 -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
8836 - { { STATE_PSEXCM }, 'i' },
8837 - { { STATE_PSRING }, 'i' },
8838 - { { STATE_EPC2 }, 'i' }
8841 -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
8842 - { { 6 /* art */ }, 'i' }
8845 -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
8846 - { { STATE_PSEXCM }, 'i' },
8847 - { { STATE_PSRING }, 'i' },
8848 - { { STATE_EPC2 }, 'o' }
8851 -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
8852 - { { 6 /* art */ }, 'm' }
8855 -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
8856 - { { STATE_PSEXCM }, 'i' },
8857 - { { STATE_PSRING }, 'i' },
8858 - { { STATE_EPC2 }, 'm' }
8861 -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
8862 - { { 6 /* art */ }, 'o' }
8865 -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
8866 - { { STATE_PSEXCM }, 'i' },
8867 - { { STATE_PSRING }, 'i' },
8868 - { { STATE_EXCSAVE2 }, 'i' }
8871 -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
8872 - { { 6 /* art */ }, 'i' }
8875 -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
8876 - { { STATE_PSEXCM }, 'i' },
8877 - { { STATE_PSRING }, 'i' },
8878 - { { STATE_EXCSAVE2 }, 'o' }
8881 -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
8882 - { { 6 /* art */ }, 'm' }
8885 -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
8886 - { { STATE_PSEXCM }, 'i' },
8887 - { { STATE_PSRING }, 'i' },
8888 - { { STATE_EXCSAVE2 }, 'm' }
8891 -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = {
8892 - { { 6 /* art */ }, 'o' }
8895 -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = {
8896 - { { STATE_PSEXCM }, 'i' },
8897 - { { STATE_PSRING }, 'i' },
8898 - { { STATE_EPC3 }, 'i' }
8901 -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = {
8902 - { { 6 /* art */ }, 'i' }
8905 -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = {
8906 - { { STATE_PSEXCM }, 'i' },
8907 - { { STATE_PSRING }, 'i' },
8908 - { { STATE_EPC3 }, 'o' }
8911 -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = {
8912 - { { 6 /* art */ }, 'm' }
8915 -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = {
8916 - { { STATE_PSEXCM }, 'i' },
8917 - { { STATE_PSRING }, 'i' },
8918 - { { STATE_EPC3 }, 'm' }
8921 -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = {
8922 - { { 6 /* art */ }, 'o' }
8925 -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = {
8926 - { { STATE_PSEXCM }, 'i' },
8927 - { { STATE_PSRING }, 'i' },
8928 - { { STATE_EXCSAVE3 }, 'i' }
8931 -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = {
8932 - { { 6 /* art */ }, 'i' }
8935 -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = {
8936 - { { STATE_PSEXCM }, 'i' },
8937 - { { STATE_PSRING }, 'i' },
8938 - { { STATE_EXCSAVE3 }, 'o' }
8941 -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = {
8942 - { { 6 /* art */ }, 'm' }
8945 -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = {
8946 - { { STATE_PSEXCM }, 'i' },
8947 - { { STATE_PSRING }, 'i' },
8948 - { { STATE_EXCSAVE3 }, 'm' }
8951 -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = {
8952 - { { 6 /* art */ }, 'o' }
8955 -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = {
8956 - { { STATE_PSEXCM }, 'i' },
8957 - { { STATE_PSRING }, 'i' },
8958 - { { STATE_EPC4 }, 'i' }
8961 -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = {
8962 - { { 6 /* art */ }, 'i' }
8965 -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = {
8966 - { { STATE_PSEXCM }, 'i' },
8967 - { { STATE_PSRING }, 'i' },
8968 - { { STATE_EPC4 }, 'o' }
8971 -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = {
8972 - { { 6 /* art */ }, 'm' }
8975 -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = {
8976 - { { STATE_PSEXCM }, 'i' },
8977 - { { STATE_PSRING }, 'i' },
8978 - { { STATE_EPC4 }, 'm' }
8981 -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = {
8982 - { { 6 /* art */ }, 'o' }
8985 -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = {
8986 - { { STATE_PSEXCM }, 'i' },
8987 - { { STATE_PSRING }, 'i' },
8988 - { { STATE_EXCSAVE4 }, 'i' }
8991 -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = {
8992 - { { 6 /* art */ }, 'i' }
8995 -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = {
8996 - { { STATE_PSEXCM }, 'i' },
8997 - { { STATE_PSRING }, 'i' },
8998 - { { STATE_EXCSAVE4 }, 'o' }
9001 -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = {
9002 - { { 6 /* art */ }, 'm' }
9005 -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = {
9006 - { { STATE_PSEXCM }, 'i' },
9007 - { { STATE_PSRING }, 'i' },
9008 - { { STATE_EXCSAVE4 }, 'm' }
9011 -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = {
9012 - { { 6 /* art */ }, 'o' }
9015 -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = {
9016 - { { STATE_PSEXCM }, 'i' },
9017 - { { STATE_PSRING }, 'i' },
9018 - { { STATE_EPC5 }, 'i' }
9021 -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = {
9022 - { { 6 /* art */ }, 'i' }
9025 -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = {
9026 - { { STATE_PSEXCM }, 'i' },
9027 - { { STATE_PSRING }, 'i' },
9028 - { { STATE_EPC5 }, 'o' }
9031 -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = {
9032 - { { 6 /* art */ }, 'm' }
9035 -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = {
9036 - { { STATE_PSEXCM }, 'i' },
9037 - { { STATE_PSRING }, 'i' },
9038 - { { STATE_EPC5 }, 'm' }
9041 -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = {
9042 - { { 6 /* art */ }, 'o' }
9045 -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = {
9046 - { { STATE_PSEXCM }, 'i' },
9047 - { { STATE_PSRING }, 'i' },
9048 - { { STATE_EXCSAVE5 }, 'i' }
9051 -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = {
9052 - { { 6 /* art */ }, 'i' }
9055 -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = {
9056 - { { STATE_PSEXCM }, 'i' },
9057 - { { STATE_PSRING }, 'i' },
9058 - { { STATE_EXCSAVE5 }, 'o' }
9061 -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = {
9062 - { { 6 /* art */ }, 'm' }
9065 -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = {
9066 - { { STATE_PSEXCM }, 'i' },
9067 - { { STATE_PSRING }, 'i' },
9068 - { { STATE_EXCSAVE5 }, 'm' }
9071 -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = {
9072 - { { 6 /* art */ }, 'o' }
9075 -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = {
9076 - { { STATE_PSEXCM }, 'i' },
9077 - { { STATE_PSRING }, 'i' },
9078 - { { STATE_EPC6 }, 'i' }
9081 -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = {
9082 - { { 6 /* art */ }, 'i' }
9085 -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = {
9086 - { { STATE_PSEXCM }, 'i' },
9087 - { { STATE_PSRING }, 'i' },
9088 - { { STATE_EPC6 }, 'o' }
9091 -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = {
9092 - { { 6 /* art */ }, 'm' }
9095 -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = {
9096 - { { STATE_PSEXCM }, 'i' },
9097 - { { STATE_PSRING }, 'i' },
9098 - { { STATE_EPC6 }, 'm' }
9101 -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = {
9102 - { { 6 /* art */ }, 'o' }
9105 -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = {
9106 - { { STATE_PSEXCM }, 'i' },
9107 - { { STATE_PSRING }, 'i' },
9108 - { { STATE_EXCSAVE6 }, 'i' }
9111 -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = {
9112 - { { 6 /* art */ }, 'i' }
9115 -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = {
9116 - { { STATE_PSEXCM }, 'i' },
9117 - { { STATE_PSRING }, 'i' },
9118 - { { STATE_EXCSAVE6 }, 'o' }
9121 -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = {
9122 - { { 6 /* art */ }, 'm' }
9125 -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = {
9126 - { { STATE_PSEXCM }, 'i' },
9127 - { { STATE_PSRING }, 'i' },
9128 - { { STATE_EXCSAVE6 }, 'm' }
9131 -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = {
9132 - { { 6 /* art */ }, 'o' }
9135 -static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = {
9136 - { { STATE_PSEXCM }, 'i' },
9137 - { { STATE_PSRING }, 'i' },
9138 - { { STATE_EPC7 }, 'i' }
9141 -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = {
9142 - { { 6 /* art */ }, 'i' }
9145 -static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = {
9146 - { { STATE_PSEXCM }, 'i' },
9147 - { { STATE_PSRING }, 'i' },
9148 - { { STATE_EPC7 }, 'o' }
9151 -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = {
9152 - { { 6 /* art */ }, 'm' }
9155 -static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = {
9156 - { { STATE_PSEXCM }, 'i' },
9157 - { { STATE_PSRING }, 'i' },
9158 - { { STATE_EPC7 }, 'm' }
9161 -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = {
9162 - { { 6 /* art */ }, 'o' }
9165 -static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = {
9166 - { { STATE_PSEXCM }, 'i' },
9167 - { { STATE_PSRING }, 'i' },
9168 - { { STATE_EXCSAVE7 }, 'i' }
9171 -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = {
9172 - { { 6 /* art */ }, 'i' }
9175 -static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = {
9176 - { { STATE_PSEXCM }, 'i' },
9177 - { { STATE_PSRING }, 'i' },
9178 - { { STATE_EXCSAVE7 }, 'o' }
9181 -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = {
9182 - { { 6 /* art */ }, 'm' }
9185 -static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = {
9186 - { { STATE_PSEXCM }, 'i' },
9187 - { { STATE_PSRING }, 'i' },
9188 - { { STATE_EXCSAVE7 }, 'm' }
9191 -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
9192 - { { 6 /* art */ }, 'o' }
9195 -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
9196 - { { STATE_PSEXCM }, 'i' },
9197 - { { STATE_PSRING }, 'i' },
9198 - { { STATE_EPS2 }, 'i' }
9201 -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
9202 - { { 6 /* art */ }, 'i' }
9205 -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
9206 - { { STATE_PSEXCM }, 'i' },
9207 - { { STATE_PSRING }, 'i' },
9208 - { { STATE_EPS2 }, 'o' }
9211 -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
9212 - { { 6 /* art */ }, 'm' }
9215 -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
9216 - { { STATE_PSEXCM }, 'i' },
9217 - { { STATE_PSRING }, 'i' },
9218 - { { STATE_EPS2 }, 'm' }
9221 -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = {
9222 - { { 6 /* art */ }, 'o' }
9225 -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = {
9226 - { { STATE_PSEXCM }, 'i' },
9227 - { { STATE_PSRING }, 'i' },
9228 - { { STATE_EPS3 }, 'i' }
9231 -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = {
9232 - { { 6 /* art */ }, 'i' }
9235 -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = {
9236 - { { STATE_PSEXCM }, 'i' },
9237 - { { STATE_PSRING }, 'i' },
9238 - { { STATE_EPS3 }, 'o' }
9241 -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = {
9242 - { { 6 /* art */ }, 'm' }
9245 -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = {
9246 - { { STATE_PSEXCM }, 'i' },
9247 - { { STATE_PSRING }, 'i' },
9248 - { { STATE_EPS3 }, 'm' }
9251 -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = {
9252 - { { 6 /* art */ }, 'o' }
9255 -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = {
9256 - { { STATE_PSEXCM }, 'i' },
9257 - { { STATE_PSRING }, 'i' },
9258 - { { STATE_EPS4 }, 'i' }
9261 -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = {
9262 - { { 6 /* art */ }, 'i' }
9265 -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = {
9266 - { { STATE_PSEXCM }, 'i' },
9267 - { { STATE_PSRING }, 'i' },
9268 - { { STATE_EPS4 }, 'o' }
9271 -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = {
9272 - { { 6 /* art */ }, 'm' }
9275 -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = {
9276 - { { STATE_PSEXCM }, 'i' },
9277 - { { STATE_PSRING }, 'i' },
9278 - { { STATE_EPS4 }, 'm' }
9281 -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = {
9282 - { { 6 /* art */ }, 'o' }
9285 -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = {
9286 - { { STATE_PSEXCM }, 'i' },
9287 - { { STATE_PSRING }, 'i' },
9288 - { { STATE_EPS5 }, 'i' }
9291 -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = {
9292 - { { 6 /* art */ }, 'i' }
9295 -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = {
9296 - { { STATE_PSEXCM }, 'i' },
9297 - { { STATE_PSRING }, 'i' },
9298 - { { STATE_EPS5 }, 'o' }
9301 -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = {
9302 - { { 6 /* art */ }, 'm' }
9305 -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = {
9306 - { { STATE_PSEXCM }, 'i' },
9307 - { { STATE_PSRING }, 'i' },
9308 - { { STATE_EPS5 }, 'm' }
9311 -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = {
9312 - { { 6 /* art */ }, 'o' }
9315 -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = {
9316 - { { STATE_PSEXCM }, 'i' },
9317 - { { STATE_PSRING }, 'i' },
9318 - { { STATE_EPS6 }, 'i' }
9321 -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = {
9322 - { { 6 /* art */ }, 'i' }
9325 -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = {
9326 - { { STATE_PSEXCM }, 'i' },
9327 - { { STATE_PSRING }, 'i' },
9328 - { { STATE_EPS6 }, 'o' }
9331 -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = {
9332 - { { 6 /* art */ }, 'm' }
9335 -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = {
9336 - { { STATE_PSEXCM }, 'i' },
9337 - { { STATE_PSRING }, 'i' },
9338 - { { STATE_EPS6 }, 'm' }
9341 -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = {
9342 - { { 6 /* art */ }, 'o' }
9345 -static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = {
9346 - { { STATE_PSEXCM }, 'i' },
9347 - { { STATE_PSRING }, 'i' },
9348 - { { STATE_EPS7 }, 'i' }
9351 -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = {
9352 - { { 6 /* art */ }, 'i' }
9355 -static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = {
9356 - { { STATE_PSEXCM }, 'i' },
9357 - { { STATE_PSRING }, 'i' },
9358 - { { STATE_EPS7 }, 'o' }
9361 -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = {
9362 - { { 6 /* art */ }, 'm' }
9365 -static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = {
9366 - { { STATE_PSEXCM }, 'i' },
9367 - { { STATE_PSRING }, 'i' },
9368 - { { STATE_EPS7 }, 'm' }
9371 -static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
9372 - { { 6 /* art */ }, 'o' }
9375 -static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
9376 - { { STATE_PSEXCM }, 'i' },
9377 - { { STATE_PSRING }, 'i' },
9378 - { { STATE_EXCVADDR }, 'i' }
9381 -static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
9382 - { { 6 /* art */ }, 'i' }
9385 -static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
9386 - { { STATE_PSEXCM }, 'i' },
9387 - { { STATE_PSRING }, 'i' },
9388 - { { STATE_EXCVADDR }, 'o' }
9391 -static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
9392 - { { 6 /* art */ }, 'm' }
9395 -static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
9396 - { { STATE_PSEXCM }, 'i' },
9397 - { { STATE_PSRING }, 'i' },
9398 - { { STATE_EXCVADDR }, 'm' }
9401 -static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
9402 - { { 6 /* art */ }, 'o' }
9405 -static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
9406 - { { STATE_PSEXCM }, 'i' },
9407 - { { STATE_PSRING }, 'i' },
9408 - { { STATE_DEPC }, 'i' }
9411 -static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
9412 - { { 6 /* art */ }, 'i' }
9415 -static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
9416 - { { STATE_PSEXCM }, 'i' },
9417 - { { STATE_PSRING }, 'i' },
9418 - { { STATE_DEPC }, 'o' }
9421 -static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
9422 - { { 6 /* art */ }, 'm' }
9425 -static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
9426 - { { STATE_PSEXCM }, 'i' },
9427 - { { STATE_PSRING }, 'i' },
9428 - { { STATE_DEPC }, 'm' }
9431 -static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
9432 - { { 6 /* art */ }, 'o' }
9435 -static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
9436 - { { STATE_PSEXCM }, 'i' },
9437 - { { STATE_PSRING }, 'i' },
9438 - { { STATE_EXCCAUSE }, 'i' },
9439 - { { STATE_XTSYNC }, 'i' }
9442 -static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
9443 - { { 6 /* art */ }, 'i' }
9446 -static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
9447 - { { STATE_PSEXCM }, 'i' },
9448 - { { STATE_PSRING }, 'i' },
9449 - { { STATE_EXCCAUSE }, 'o' }
9452 -static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
9453 - { { 6 /* art */ }, 'm' }
9456 -static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
9457 - { { STATE_PSEXCM }, 'i' },
9458 - { { STATE_PSRING }, 'i' },
9459 - { { STATE_EXCCAUSE }, 'm' }
9462 -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = {
9463 - { { 6 /* art */ }, 'o' }
9466 -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = {
9467 - { { STATE_PSEXCM }, 'i' },
9468 - { { STATE_PSRING }, 'i' },
9469 - { { STATE_MISC0 }, 'i' }
9472 -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = {
9473 - { { 6 /* art */ }, 'i' }
9476 -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = {
9477 - { { STATE_PSEXCM }, 'i' },
9478 - { { STATE_PSRING }, 'i' },
9479 - { { STATE_MISC0 }, 'o' }
9482 -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = {
9483 - { { 6 /* art */ }, 'm' }
9486 -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = {
9487 - { { STATE_PSEXCM }, 'i' },
9488 - { { STATE_PSRING }, 'i' },
9489 - { { STATE_MISC0 }, 'm' }
9492 -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = {
9493 - { { 6 /* art */ }, 'o' }
9496 -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = {
9497 - { { STATE_PSEXCM }, 'i' },
9498 - { { STATE_PSRING }, 'i' },
9499 - { { STATE_MISC1 }, 'i' }
9502 -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = {
9503 - { { 6 /* art */ }, 'i' }
9506 -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = {
9507 - { { STATE_PSEXCM }, 'i' },
9508 - { { STATE_PSRING }, 'i' },
9509 - { { STATE_MISC1 }, 'o' }
9512 -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = {
9513 - { { 6 /* art */ }, 'm' }
9516 -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = {
9517 - { { STATE_PSEXCM }, 'i' },
9518 - { { STATE_PSRING }, 'i' },
9519 - { { STATE_MISC1 }, 'm' }
9522 -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc2_args[] = {
9523 - { { 6 /* art */ }, 'o' }
9526 -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc2_stateArgs[] = {
9527 - { { STATE_PSEXCM }, 'i' },
9528 - { { STATE_PSRING }, 'i' },
9529 - { { STATE_MISC2 }, 'i' }
9532 -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc2_args[] = {
9533 - { { 6 /* art */ }, 'i' }
9536 -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc2_stateArgs[] = {
9537 - { { STATE_PSEXCM }, 'i' },
9538 - { { STATE_PSRING }, 'i' },
9539 - { { STATE_MISC2 }, 'o' }
9542 -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc2_args[] = {
9543 - { { 6 /* art */ }, 'm' }
9546 -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc2_stateArgs[] = {
9547 - { { STATE_PSEXCM }, 'i' },
9548 - { { STATE_PSRING }, 'i' },
9549 - { { STATE_MISC2 }, 'm' }
9552 -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc3_args[] = {
9553 - { { 6 /* art */ }, 'o' }
9556 -static xtensa_arg_internal Iclass_xt_iclass_rsr_misc3_stateArgs[] = {
9557 - { { STATE_PSEXCM }, 'i' },
9558 - { { STATE_PSRING }, 'i' },
9559 - { { STATE_MISC3 }, 'i' }
9562 -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc3_args[] = {
9563 - { { 6 /* art */ }, 'i' }
9566 -static xtensa_arg_internal Iclass_xt_iclass_wsr_misc3_stateArgs[] = {
9567 - { { STATE_PSEXCM }, 'i' },
9568 - { { STATE_PSRING }, 'i' },
9569 - { { STATE_MISC3 }, 'o' }
9572 -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc3_args[] = {
9573 - { { 6 /* art */ }, 'm' }
9576 -static xtensa_arg_internal Iclass_xt_iclass_xsr_misc3_stateArgs[] = {
9577 - { { STATE_PSEXCM }, 'i' },
9578 - { { STATE_PSRING }, 'i' },
9579 - { { STATE_MISC3 }, 'm' }
9582 -static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
9583 - { { 6 /* art */ }, 'o' }
9586 -static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = {
9587 - { { STATE_PSEXCM }, 'i' },
9588 - { { STATE_PSRING }, 'i' }
9591 -static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = {
9592 - { { 6 /* art */ }, 'o' }
9595 -static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = {
9596 - { { STATE_PSEXCM }, 'i' },
9597 - { { STATE_PSRING }, 'i' },
9598 - { { STATE_VECBASE }, 'i' }
9601 -static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = {
9602 - { { 6 /* art */ }, 'i' }
9605 -static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = {
9606 - { { STATE_PSEXCM }, 'i' },
9607 - { { STATE_PSRING }, 'i' },
9608 - { { STATE_VECBASE }, 'o' }
9611 -static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = {
9612 - { { 6 /* art */ }, 'm' }
9615 -static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = {
9616 - { { STATE_PSEXCM }, 'i' },
9617 - { { STATE_PSRING }, 'i' },
9618 - { { STATE_VECBASE }, 'm' }
9621 -static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_args[] = {
9622 - { { 4 /* ars */ }, 'i' },
9623 - { { 6 /* art */ }, 'i' }
9626 -static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_stateArgs[] = {
9627 - { { STATE_ACC }, 'o' }
9630 -static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_args[] = {
9631 - { { 4 /* ars */ }, 'i' },
9632 - { { 34 /* my */ }, 'i' }
9635 -static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_stateArgs[] = {
9636 - { { STATE_ACC }, 'o' }
9639 -static xtensa_arg_internal Iclass_xt_iclass_mac16_da_args[] = {
9640 - { { 33 /* mx */ }, 'i' },
9641 - { { 6 /* art */ }, 'i' }
9644 -static xtensa_arg_internal Iclass_xt_iclass_mac16_da_stateArgs[] = {
9645 - { { STATE_ACC }, 'o' }
9648 -static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_args[] = {
9649 - { { 33 /* mx */ }, 'i' },
9650 - { { 34 /* my */ }, 'i' }
9653 -static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_stateArgs[] = {
9654 - { { STATE_ACC }, 'o' }
9657 -static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_args[] = {
9658 - { { 4 /* ars */ }, 'i' },
9659 - { { 6 /* art */ }, 'i' }
9662 -static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_stateArgs[] = {
9663 - { { STATE_ACC }, 'm' }
9666 -static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_args[] = {
9667 - { { 4 /* ars */ }, 'i' },
9668 - { { 34 /* my */ }, 'i' }
9671 -static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_stateArgs[] = {
9672 - { { STATE_ACC }, 'm' }
9675 -static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_args[] = {
9676 - { { 33 /* mx */ }, 'i' },
9677 - { { 6 /* art */ }, 'i' }
9680 -static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_stateArgs[] = {
9681 - { { STATE_ACC }, 'm' }
9684 -static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_args[] = {
9685 - { { 33 /* mx */ }, 'i' },
9686 - { { 34 /* my */ }, 'i' }
9689 -static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_stateArgs[] = {
9690 - { { STATE_ACC }, 'm' }
9693 -static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_args[] = {
9694 - { { 35 /* mw */ }, 'o' },
9695 - { { 4 /* ars */ }, 'm' },
9696 - { { 33 /* mx */ }, 'i' },
9697 - { { 6 /* art */ }, 'i' }
9700 -static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_stateArgs[] = {
9701 - { { STATE_ACC }, 'm' }
9704 -static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_args[] = {
9705 - { { 35 /* mw */ }, 'o' },
9706 - { { 4 /* ars */ }, 'm' },
9707 - { { 33 /* mx */ }, 'i' },
9708 - { { 34 /* my */ }, 'i' }
9711 -static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_stateArgs[] = {
9712 - { { STATE_ACC }, 'm' }
9715 -static xtensa_arg_internal Iclass_xt_iclass_mac16_l_args[] = {
9716 - { { 35 /* mw */ }, 'o' },
9717 - { { 4 /* ars */ }, 'm' }
9720 -static xtensa_arg_internal Iclass_xt_iclass_mul16_args[] = {
9721 - { { 3 /* arr */ }, 'o' },
9722 - { { 4 /* ars */ }, 'i' },
9723 - { { 6 /* art */ }, 'i' }
9726 -static xtensa_arg_internal Iclass_xt_iclass_rsr_m0_args[] = {
9727 - { { 6 /* art */ }, 'o' },
9728 - { { 36 /* mr0 */ }, 'i' }
9731 -static xtensa_arg_internal Iclass_xt_iclass_wsr_m0_args[] = {
9732 - { { 6 /* art */ }, 'i' },
9733 - { { 36 /* mr0 */ }, 'o' }
9736 -static xtensa_arg_internal Iclass_xt_iclass_xsr_m0_args[] = {
9737 - { { 6 /* art */ }, 'm' },
9738 - { { 36 /* mr0 */ }, 'm' }
9741 -static xtensa_arg_internal Iclass_xt_iclass_rsr_m1_args[] = {
9742 - { { 6 /* art */ }, 'o' },
9743 - { { 37 /* mr1 */ }, 'i' }
9746 -static xtensa_arg_internal Iclass_xt_iclass_wsr_m1_args[] = {
9747 - { { 6 /* art */ }, 'i' },
9748 - { { 37 /* mr1 */ }, 'o' }
9751 -static xtensa_arg_internal Iclass_xt_iclass_xsr_m1_args[] = {
9752 - { { 6 /* art */ }, 'm' },
9753 - { { 37 /* mr1 */ }, 'm' }
9756 -static xtensa_arg_internal Iclass_xt_iclass_rsr_m2_args[] = {
9757 - { { 6 /* art */ }, 'o' },
9758 - { { 38 /* mr2 */ }, 'i' }
9761 -static xtensa_arg_internal Iclass_xt_iclass_wsr_m2_args[] = {
9762 - { { 6 /* art */ }, 'i' },
9763 - { { 38 /* mr2 */ }, 'o' }
9766 -static xtensa_arg_internal Iclass_xt_iclass_xsr_m2_args[] = {
9767 - { { 6 /* art */ }, 'm' },
9768 - { { 38 /* mr2 */ }, 'm' }
9771 -static xtensa_arg_internal Iclass_xt_iclass_rsr_m3_args[] = {
9772 - { { 6 /* art */ }, 'o' },
9773 - { { 39 /* mr3 */ }, 'i' }
9776 -static xtensa_arg_internal Iclass_xt_iclass_wsr_m3_args[] = {
9777 - { { 6 /* art */ }, 'i' },
9778 - { { 39 /* mr3 */ }, 'o' }
9781 -static xtensa_arg_internal Iclass_xt_iclass_xsr_m3_args[] = {
9782 - { { 6 /* art */ }, 'm' },
9783 - { { 39 /* mr3 */ }, 'm' }
9786 -static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = {
9787 - { { 6 /* art */ }, 'o' }
9790 -static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_stateArgs[] = {
9791 - { { STATE_ACC }, 'i' }
9794 -static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = {
9795 - { { 6 /* art */ }, 'i' }
9798 -static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_stateArgs[] = {
9799 - { { STATE_ACC }, 'm' }
9802 -static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = {
9803 - { { 6 /* art */ }, 'm' }
9806 -static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_stateArgs[] = {
9807 - { { STATE_ACC }, 'm' }
9810 -static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = {
9811 - { { 6 /* art */ }, 'o' }
9814 -static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_stateArgs[] = {
9815 - { { STATE_ACC }, 'i' }
9818 -static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = {
9819 - { { 6 /* art */ }, 'i' }
9822 -static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_stateArgs[] = {
9823 - { { STATE_ACC }, 'm' }
9826 -static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = {
9827 - { { 6 /* art */ }, 'm' }
9830 -static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_stateArgs[] = {
9831 - { { STATE_ACC }, 'm' }
9834 -static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
9835 - { { 70 /* s */ }, 'i' }
9838 -static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
9839 - { { STATE_PSWOE }, 'o' },
9840 - { { STATE_PSCALLINC }, 'o' },
9841 - { { STATE_PSOWB }, 'o' },
9842 - { { STATE_PSRING }, 'm' },
9843 - { { STATE_PSUM }, 'o' },
9844 - { { STATE_PSEXCM }, 'm' },
9845 - { { STATE_PSINTLEVEL }, 'o' },
9846 - { { STATE_EPC1 }, 'i' },
9847 - { { STATE_EPC2 }, 'i' },
9848 - { { STATE_EPC3 }, 'i' },
9849 - { { STATE_EPC4 }, 'i' },
9850 - { { STATE_EPC5 }, 'i' },
9851 - { { STATE_EPC6 }, 'i' },
9852 - { { STATE_EPC7 }, 'i' },
9853 - { { STATE_EPS2 }, 'i' },
9854 - { { STATE_EPS3 }, 'i' },
9855 - { { STATE_EPS4 }, 'i' },
9856 - { { STATE_EPS5 }, 'i' },
9857 - { { STATE_EPS6 }, 'i' },
9858 - { { STATE_EPS7 }, 'i' },
9859 - { { STATE_InOCDMode }, 'm' }
9862 -static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
9863 - { { 70 /* s */ }, 'i' }
9866 -static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
9867 - { { STATE_PSEXCM }, 'i' },
9868 - { { STATE_PSRING }, 'i' },
9869 - { { STATE_PSINTLEVEL }, 'o' }
9872 -static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
9873 - { { 6 /* art */ }, 'o' }
9876 -static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
9877 - { { STATE_PSEXCM }, 'i' },
9878 - { { STATE_PSRING }, 'i' },
9879 - { { STATE_INTERRUPT }, 'i' }
9882 -static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
9883 - { { 6 /* art */ }, 'i' }
9886 -static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
9887 - { { STATE_PSEXCM }, 'i' },
9888 - { { STATE_PSRING }, 'i' },
9889 - { { STATE_XTSYNC }, 'o' },
9890 - { { STATE_INTERRUPT }, 'm' }
9893 -static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
9894 - { { 6 /* art */ }, 'i' }
9897 -static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
9898 - { { STATE_PSEXCM }, 'i' },
9899 - { { STATE_PSRING }, 'i' },
9900 - { { STATE_XTSYNC }, 'o' },
9901 - { { STATE_INTERRUPT }, 'm' }
9904 -static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
9905 - { { 6 /* art */ }, 'o' }
9908 -static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
9909 - { { STATE_PSEXCM }, 'i' },
9910 - { { STATE_PSRING }, 'i' },
9911 - { { STATE_INTENABLE }, 'i' }
9914 -static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
9915 - { { 6 /* art */ }, 'i' }
9918 -static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
9919 - { { STATE_PSEXCM }, 'i' },
9920 - { { STATE_PSRING }, 'i' },
9921 - { { STATE_INTENABLE }, 'o' }
9924 -static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
9925 - { { 6 /* art */ }, 'm' }
9928 -static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
9929 - { { STATE_PSEXCM }, 'i' },
9930 - { { STATE_PSRING }, 'i' },
9931 - { { STATE_INTENABLE }, 'm' }
9934 -static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
9935 - { { 41 /* imms */ }, 'i' },
9936 - { { 40 /* immt */ }, 'i' }
9939 -static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
9940 - { { STATE_PSEXCM }, 'i' },
9941 - { { STATE_PSINTLEVEL }, 'i' }
9944 -static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
9945 - { { 41 /* imms */ }, 'i' }
9948 -static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
9949 - { { STATE_PSEXCM }, 'i' },
9950 - { { STATE_PSINTLEVEL }, 'i' }
9953 -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = {
9954 - { { 6 /* art */ }, 'o' }
9957 -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = {
9958 - { { STATE_PSEXCM }, 'i' },
9959 - { { STATE_PSRING }, 'i' },
9960 - { { STATE_DBREAKA0 }, 'i' }
9963 -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = {
9964 - { { 6 /* art */ }, 'i' }
9967 -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = {
9968 - { { STATE_PSEXCM }, 'i' },
9969 - { { STATE_PSRING }, 'i' },
9970 - { { STATE_DBREAKA0 }, 'o' },
9971 - { { STATE_XTSYNC }, 'o' }
9974 -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = {
9975 - { { 6 /* art */ }, 'm' }
9978 -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = {
9979 - { { STATE_PSEXCM }, 'i' },
9980 - { { STATE_PSRING }, 'i' },
9981 - { { STATE_DBREAKA0 }, 'm' },
9982 - { { STATE_XTSYNC }, 'o' }
9985 -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = {
9986 - { { 6 /* art */ }, 'o' }
9989 -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = {
9990 - { { STATE_PSEXCM }, 'i' },
9991 - { { STATE_PSRING }, 'i' },
9992 - { { STATE_DBREAKC0 }, 'i' }
9995 -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = {
9996 - { { 6 /* art */ }, 'i' }
9999 -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = {
10000 - { { STATE_PSEXCM }, 'i' },
10001 - { { STATE_PSRING }, 'i' },
10002 - { { STATE_DBREAKC0 }, 'o' },
10003 - { { STATE_XTSYNC }, 'o' }
10006 -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = {
10007 - { { 6 /* art */ }, 'm' }
10010 -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = {
10011 - { { STATE_PSEXCM }, 'i' },
10012 - { { STATE_PSRING }, 'i' },
10013 - { { STATE_DBREAKC0 }, 'm' },
10014 - { { STATE_XTSYNC }, 'o' }
10017 -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = {
10018 - { { 6 /* art */ }, 'o' }
10021 -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = {
10022 - { { STATE_PSEXCM }, 'i' },
10023 - { { STATE_PSRING }, 'i' },
10024 - { { STATE_DBREAKA1 }, 'i' }
10027 -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = {
10028 - { { 6 /* art */ }, 'i' }
10031 -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = {
10032 - { { STATE_PSEXCM }, 'i' },
10033 - { { STATE_PSRING }, 'i' },
10034 - { { STATE_DBREAKA1 }, 'o' },
10035 - { { STATE_XTSYNC }, 'o' }
10038 -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = {
10039 - { { 6 /* art */ }, 'm' }
10042 -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = {
10043 - { { STATE_PSEXCM }, 'i' },
10044 - { { STATE_PSRING }, 'i' },
10045 - { { STATE_DBREAKA1 }, 'm' },
10046 - { { STATE_XTSYNC }, 'o' }
10049 -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = {
10050 - { { 6 /* art */ }, 'o' }
10053 -static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = {
10054 - { { STATE_PSEXCM }, 'i' },
10055 - { { STATE_PSRING }, 'i' },
10056 - { { STATE_DBREAKC1 }, 'i' }
10059 -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = {
10060 - { { 6 /* art */ }, 'i' }
10063 -static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = {
10064 - { { STATE_PSEXCM }, 'i' },
10065 - { { STATE_PSRING }, 'i' },
10066 - { { STATE_DBREAKC1 }, 'o' },
10067 - { { STATE_XTSYNC }, 'o' }
10070 -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = {
10071 - { { 6 /* art */ }, 'm' }
10074 -static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = {
10075 - { { STATE_PSEXCM }, 'i' },
10076 - { { STATE_PSRING }, 'i' },
10077 - { { STATE_DBREAKC1 }, 'm' },
10078 - { { STATE_XTSYNC }, 'o' }
10081 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = {
10082 - { { 6 /* art */ }, 'o' }
10085 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = {
10086 - { { STATE_PSEXCM }, 'i' },
10087 - { { STATE_PSRING }, 'i' },
10088 - { { STATE_IBREAKA0 }, 'i' }
10091 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = {
10092 - { { 6 /* art */ }, 'i' }
10095 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = {
10096 - { { STATE_PSEXCM }, 'i' },
10097 - { { STATE_PSRING }, 'i' },
10098 - { { STATE_IBREAKA0 }, 'o' }
10101 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = {
10102 - { { 6 /* art */ }, 'm' }
10105 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = {
10106 - { { STATE_PSEXCM }, 'i' },
10107 - { { STATE_PSRING }, 'i' },
10108 - { { STATE_IBREAKA0 }, 'm' }
10111 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = {
10112 - { { 6 /* art */ }, 'o' }
10115 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = {
10116 - { { STATE_PSEXCM }, 'i' },
10117 - { { STATE_PSRING }, 'i' },
10118 - { { STATE_IBREAKA1 }, 'i' }
10121 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = {
10122 - { { 6 /* art */ }, 'i' }
10125 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = {
10126 - { { STATE_PSEXCM }, 'i' },
10127 - { { STATE_PSRING }, 'i' },
10128 - { { STATE_IBREAKA1 }, 'o' }
10131 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = {
10132 - { { 6 /* art */ }, 'm' }
10135 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = {
10136 - { { STATE_PSEXCM }, 'i' },
10137 - { { STATE_PSRING }, 'i' },
10138 - { { STATE_IBREAKA1 }, 'm' }
10141 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = {
10142 - { { 6 /* art */ }, 'o' }
10145 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = {
10146 - { { STATE_PSEXCM }, 'i' },
10147 - { { STATE_PSRING }, 'i' },
10148 - { { STATE_IBREAKENABLE }, 'i' }
10151 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = {
10152 - { { 6 /* art */ }, 'i' }
10155 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = {
10156 - { { STATE_PSEXCM }, 'i' },
10157 - { { STATE_PSRING }, 'i' },
10158 - { { STATE_IBREAKENABLE }, 'o' }
10161 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = {
10162 - { { 6 /* art */ }, 'm' }
10165 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = {
10166 - { { STATE_PSEXCM }, 'i' },
10167 - { { STATE_PSRING }, 'i' },
10168 - { { STATE_IBREAKENABLE }, 'm' }
10171 -static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = {
10172 - { { 6 /* art */ }, 'o' }
10175 -static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = {
10176 - { { STATE_PSEXCM }, 'i' },
10177 - { { STATE_PSRING }, 'i' },
10178 - { { STATE_DEBUGCAUSE }, 'i' },
10179 - { { STATE_DBNUM }, 'i' }
10182 -static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = {
10183 - { { 6 /* art */ }, 'i' }
10186 -static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = {
10187 - { { STATE_PSEXCM }, 'i' },
10188 - { { STATE_PSRING }, 'i' },
10189 - { { STATE_DEBUGCAUSE }, 'o' },
10190 - { { STATE_DBNUM }, 'o' }
10193 -static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = {
10194 - { { 6 /* art */ }, 'm' }
10197 -static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = {
10198 - { { STATE_PSEXCM }, 'i' },
10199 - { { STATE_PSRING }, 'i' },
10200 - { { STATE_DEBUGCAUSE }, 'm' },
10201 - { { STATE_DBNUM }, 'm' }
10204 -static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = {
10205 - { { 6 /* art */ }, 'o' }
10208 -static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = {
10209 - { { STATE_PSEXCM }, 'i' },
10210 - { { STATE_PSRING }, 'i' },
10211 - { { STATE_ICOUNT }, 'i' }
10214 -static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = {
10215 - { { 6 /* art */ }, 'i' }
10218 -static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = {
10219 - { { STATE_PSEXCM }, 'i' },
10220 - { { STATE_PSRING }, 'i' },
10221 - { { STATE_XTSYNC }, 'o' },
10222 - { { STATE_ICOUNT }, 'o' }
10225 -static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = {
10226 - { { 6 /* art */ }, 'm' }
10229 -static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = {
10230 - { { STATE_PSEXCM }, 'i' },
10231 - { { STATE_PSRING }, 'i' },
10232 - { { STATE_XTSYNC }, 'o' },
10233 - { { STATE_ICOUNT }, 'm' }
10236 -static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = {
10237 - { { 6 /* art */ }, 'o' }
10240 -static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = {
10241 - { { STATE_PSEXCM }, 'i' },
10242 - { { STATE_PSRING }, 'i' },
10243 - { { STATE_ICOUNTLEVEL }, 'i' }
10246 -static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = {
10247 - { { 6 /* art */ }, 'i' }
10250 -static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = {
10251 - { { STATE_PSEXCM }, 'i' },
10252 - { { STATE_PSRING }, 'i' },
10253 - { { STATE_ICOUNTLEVEL }, 'o' }
10256 -static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = {
10257 - { { 6 /* art */ }, 'm' }
10260 -static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = {
10261 - { { STATE_PSEXCM }, 'i' },
10262 - { { STATE_PSRING }, 'i' },
10263 - { { STATE_ICOUNTLEVEL }, 'm' }
10266 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = {
10267 - { { 6 /* art */ }, 'o' }
10270 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = {
10271 - { { STATE_PSEXCM }, 'i' },
10272 - { { STATE_PSRING }, 'i' },
10273 - { { STATE_DDR }, 'i' }
10276 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = {
10277 - { { 6 /* art */ }, 'i' }
10280 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = {
10281 - { { STATE_PSEXCM }, 'i' },
10282 - { { STATE_PSRING }, 'i' },
10283 - { { STATE_XTSYNC }, 'o' },
10284 - { { STATE_DDR }, 'o' }
10287 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = {
10288 - { { 6 /* art */ }, 'm' }
10291 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = {
10292 - { { STATE_PSEXCM }, 'i' },
10293 - { { STATE_PSRING }, 'i' },
10294 - { { STATE_XTSYNC }, 'o' },
10295 - { { STATE_DDR }, 'm' }
10298 -static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = {
10299 - { { 41 /* imms */ }, 'i' }
10302 -static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = {
10303 - { { STATE_InOCDMode }, 'm' },
10304 - { { STATE_EPC6 }, 'i' },
10305 - { { STATE_PSWOE }, 'o' },
10306 - { { STATE_PSCALLINC }, 'o' },
10307 - { { STATE_PSOWB }, 'o' },
10308 - { { STATE_PSRING }, 'o' },
10309 - { { STATE_PSUM }, 'o' },
10310 - { { STATE_PSEXCM }, 'o' },
10311 - { { STATE_PSINTLEVEL }, 'o' },
10312 - { { STATE_EPS6 }, 'i' }
10315 -static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = {
10316 - { { STATE_InOCDMode }, 'm' }
10319 -static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = {
10320 - { { 6 /* art */ }, 'i' }
10323 -static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = {
10324 - { { STATE_PSEXCM }, 'i' },
10325 - { { STATE_PSRING }, 'i' },
10326 - { { STATE_XTSYNC }, 'o' }
10329 -static xtensa_arg_internal Iclass_xt_iclass_bbool1_args[] = {
10330 - { { 44 /* br */ }, 'o' },
10331 - { { 43 /* bs */ }, 'i' },
10332 - { { 42 /* bt */ }, 'i' }
10335 -static xtensa_arg_internal Iclass_xt_iclass_bbool4_args[] = {
10336 - { { 42 /* bt */ }, 'o' },
10337 - { { 49 /* bs4 */ }, 'i' }
10340 -static xtensa_arg_internal Iclass_xt_iclass_bbool8_args[] = {
10341 - { { 42 /* bt */ }, 'o' },
10342 - { { 52 /* bs8 */ }, 'i' }
10345 -static xtensa_arg_internal Iclass_xt_iclass_bbranch_args[] = {
10346 - { { 43 /* bs */ }, 'i' },
10347 - { { 28 /* label8 */ }, 'i' }
10350 -static xtensa_arg_internal Iclass_xt_iclass_bmove_args[] = {
10351 - { { 3 /* arr */ }, 'm' },
10352 - { { 4 /* ars */ }, 'i' },
10353 - { { 42 /* bt */ }, 'i' }
10356 -static xtensa_arg_internal Iclass_xt_iclass_RSR_BR_args[] = {
10357 - { { 6 /* art */ }, 'o' },
10358 - { { 57 /* brall */ }, 'i' }
10361 -static xtensa_arg_internal Iclass_xt_iclass_WSR_BR_args[] = {
10362 - { { 6 /* art */ }, 'i' },
10363 - { { 57 /* brall */ }, 'o' }
10366 -static xtensa_arg_internal Iclass_xt_iclass_XSR_BR_args[] = {
10367 - { { 6 /* art */ }, 'm' },
10368 - { { 57 /* brall */ }, 'm' }
10371 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = {
10372 - { { 6 /* art */ }, 'o' }
10375 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = {
10376 - { { STATE_PSEXCM }, 'i' },
10377 - { { STATE_PSRING }, 'i' },
10378 - { { STATE_CCOUNT }, 'i' }
10381 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = {
10382 - { { 6 /* art */ }, 'i' }
10385 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = {
10386 - { { STATE_PSEXCM }, 'i' },
10387 - { { STATE_PSRING }, 'i' },
10388 - { { STATE_XTSYNC }, 'o' },
10389 - { { STATE_CCOUNT }, 'o' }
10392 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = {
10393 - { { 6 /* art */ }, 'm' }
10396 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = {
10397 - { { STATE_PSEXCM }, 'i' },
10398 - { { STATE_PSRING }, 'i' },
10399 - { { STATE_XTSYNC }, 'o' },
10400 - { { STATE_CCOUNT }, 'm' }
10403 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = {
10404 - { { 6 /* art */ }, 'o' }
10407 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = {
10408 - { { STATE_PSEXCM }, 'i' },
10409 - { { STATE_PSRING }, 'i' },
10410 - { { STATE_CCOMPARE0 }, 'i' }
10413 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = {
10414 - { { 6 /* art */ }, 'i' }
10417 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = {
10418 - { { STATE_PSEXCM }, 'i' },
10419 - { { STATE_PSRING }, 'i' },
10420 - { { STATE_CCOMPARE0 }, 'o' },
10421 - { { STATE_INTERRUPT }, 'm' }
10424 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = {
10425 - { { 6 /* art */ }, 'm' }
10428 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = {
10429 - { { STATE_PSEXCM }, 'i' },
10430 - { { STATE_PSRING }, 'i' },
10431 - { { STATE_CCOMPARE0 }, 'm' },
10432 - { { STATE_INTERRUPT }, 'm' }
10435 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = {
10436 - { { 6 /* art */ }, 'o' }
10439 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = {
10440 - { { STATE_PSEXCM }, 'i' },
10441 - { { STATE_PSRING }, 'i' },
10442 - { { STATE_CCOMPARE1 }, 'i' }
10445 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = {
10446 - { { 6 /* art */ }, 'i' }
10449 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = {
10450 - { { STATE_PSEXCM }, 'i' },
10451 - { { STATE_PSRING }, 'i' },
10452 - { { STATE_CCOMPARE1 }, 'o' },
10453 - { { STATE_INTERRUPT }, 'm' }
10456 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = {
10457 - { { 6 /* art */ }, 'm' }
10460 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = {
10461 - { { STATE_PSEXCM }, 'i' },
10462 - { { STATE_PSRING }, 'i' },
10463 - { { STATE_CCOMPARE1 }, 'm' },
10464 - { { STATE_INTERRUPT }, 'm' }
10467 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = {
10468 - { { 6 /* art */ }, 'o' }
10471 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = {
10472 - { { STATE_PSEXCM }, 'i' },
10473 - { { STATE_PSRING }, 'i' },
10474 - { { STATE_CCOMPARE2 }, 'i' }
10477 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = {
10478 - { { 6 /* art */ }, 'i' }
10481 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = {
10482 - { { STATE_PSEXCM }, 'i' },
10483 - { { STATE_PSRING }, 'i' },
10484 - { { STATE_CCOMPARE2 }, 'o' },
10485 - { { STATE_INTERRUPT }, 'm' }
10488 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = {
10489 - { { 6 /* art */ }, 'm' }
10492 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = {
10493 - { { STATE_PSEXCM }, 'i' },
10494 - { { STATE_PSRING }, 'i' },
10495 - { { STATE_CCOMPARE2 }, 'm' },
10496 - { { STATE_INTERRUPT }, 'm' }
10499 -static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = {
10500 - { { 4 /* ars */ }, 'i' },
10501 - { { 21 /* uimm8x4 */ }, 'i' }
10504 -static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = {
10505 - { { 4 /* ars */ }, 'i' },
10506 - { { 22 /* uimm4x16 */ }, 'i' }
10509 -static xtensa_arg_internal Iclass_xt_iclass_icache_lock_stateArgs[] = {
10510 - { { STATE_PSEXCM }, 'i' },
10511 - { { STATE_PSRING }, 'i' }
10514 -static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = {
10515 - { { 4 /* ars */ }, 'i' },
10516 - { { 21 /* uimm8x4 */ }, 'i' }
10519 -static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = {
10520 - { { STATE_PSEXCM }, 'i' },
10521 - { { STATE_PSRING }, 'i' }
10524 -static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = {
10525 - { { 6 /* art */ }, 'o' },
10526 - { { 4 /* ars */ }, 'i' }
10529 -static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = {
10530 - { { STATE_PSEXCM }, 'i' },
10531 - { { STATE_PSRING }, 'i' }
10534 -static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = {
10535 - { { 6 /* art */ }, 'i' },
10536 - { { 4 /* ars */ }, 'i' }
10539 -static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = {
10540 - { { STATE_PSEXCM }, 'i' },
10541 - { { STATE_PSRING }, 'i' }
10544 -static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = {
10545 - { { 4 /* ars */ }, 'i' },
10546 - { { 21 /* uimm8x4 */ }, 'i' }
10549 -static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = {
10550 - { { 4 /* ars */ }, 'i' },
10551 - { { 22 /* uimm4x16 */ }, 'i' }
10554 -static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = {
10555 - { { STATE_PSEXCM }, 'i' },
10556 - { { STATE_PSRING }, 'i' }
10559 -static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = {
10560 - { { 4 /* ars */ }, 'i' },
10561 - { { 21 /* uimm8x4 */ }, 'i' }
10564 -static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = {
10565 - { { STATE_PSEXCM }, 'i' },
10566 - { { STATE_PSRING }, 'i' }
10569 -static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = {
10570 - { { 4 /* ars */ }, 'i' },
10571 - { { 21 /* uimm8x4 */ }, 'i' }
10574 -static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = {
10575 - { { 4 /* ars */ }, 'i' },
10576 - { { 22 /* uimm4x16 */ }, 'i' }
10579 -static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_stateArgs[] = {
10580 - { { STATE_PSEXCM }, 'i' },
10581 - { { STATE_PSRING }, 'i' }
10584 -static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = {
10585 - { { 6 /* art */ }, 'i' },
10586 - { { 4 /* ars */ }, 'i' }
10589 -static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = {
10590 - { { STATE_PSEXCM }, 'i' },
10591 - { { STATE_PSRING }, 'i' }
10594 -static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = {
10595 - { { 6 /* art */ }, 'o' },
10596 - { { 4 /* ars */ }, 'i' }
10599 -static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = {
10600 - { { STATE_PSEXCM }, 'i' },
10601 - { { STATE_PSRING }, 'i' }
10604 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = {
10605 - { { 6 /* art */ }, 'i' }
10608 -static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = {
10609 - { { STATE_PSEXCM }, 'i' },
10610 - { { STATE_PSRING }, 'i' },
10611 - { { STATE_PTBASE }, 'o' },
10612 - { { STATE_XTSYNC }, 'o' }
10615 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = {
10616 - { { 6 /* art */ }, 'o' }
10619 -static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = {
10620 - { { STATE_PSEXCM }, 'i' },
10621 - { { STATE_PSRING }, 'i' },
10622 - { { STATE_PTBASE }, 'i' },
10623 - { { STATE_EXCVADDR }, 'i' }
10626 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = {
10627 - { { 6 /* art */ }, 'm' }
10630 -static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = {
10631 - { { STATE_PSEXCM }, 'i' },
10632 - { { STATE_PSRING }, 'i' },
10633 - { { STATE_PTBASE }, 'm' },
10634 - { { STATE_EXCVADDR }, 'i' },
10635 - { { STATE_XTSYNC }, 'o' }
10638 -static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = {
10639 - { { 6 /* art */ }, 'o' }
10642 -static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = {
10643 - { { STATE_PSEXCM }, 'i' },
10644 - { { STATE_PSRING }, 'i' },
10645 - { { STATE_ASID3 }, 'i' },
10646 - { { STATE_ASID2 }, 'i' },
10647 - { { STATE_ASID1 }, 'i' }
10650 -static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = {
10651 - { { 6 /* art */ }, 'i' }
10654 -static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = {
10655 - { { STATE_XTSYNC }, 'o' },
10656 - { { STATE_PSEXCM }, 'i' },
10657 - { { STATE_PSRING }, 'i' },
10658 - { { STATE_ASID3 }, 'o' },
10659 - { { STATE_ASID2 }, 'o' },
10660 - { { STATE_ASID1 }, 'o' }
10663 -static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = {
10664 - { { 6 /* art */ }, 'm' }
10667 -static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = {
10668 - { { STATE_XTSYNC }, 'o' },
10669 - { { STATE_PSEXCM }, 'i' },
10670 - { { STATE_PSRING }, 'i' },
10671 - { { STATE_ASID3 }, 'm' },
10672 - { { STATE_ASID2 }, 'm' },
10673 - { { STATE_ASID1 }, 'm' }
10676 -static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = {
10677 - { { 6 /* art */ }, 'o' }
10680 -static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = {
10681 - { { STATE_PSEXCM }, 'i' },
10682 - { { STATE_PSRING }, 'i' },
10683 - { { STATE_INSTPGSZID4 }, 'i' }
10686 -static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = {
10687 - { { 6 /* art */ }, 'i' }
10690 -static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = {
10691 - { { STATE_XTSYNC }, 'o' },
10692 - { { STATE_PSEXCM }, 'i' },
10693 - { { STATE_PSRING }, 'i' },
10694 - { { STATE_INSTPGSZID4 }, 'o' }
10697 -static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = {
10698 - { { 6 /* art */ }, 'm' }
10701 -static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = {
10702 - { { STATE_XTSYNC }, 'o' },
10703 - { { STATE_PSEXCM }, 'i' },
10704 - { { STATE_PSRING }, 'i' },
10705 - { { STATE_INSTPGSZID4 }, 'm' }
10708 -static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = {
10709 - { { 6 /* art */ }, 'o' }
10712 -static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = {
10713 - { { STATE_PSEXCM }, 'i' },
10714 - { { STATE_PSRING }, 'i' },
10715 - { { STATE_DATAPGSZID4 }, 'i' }
10718 -static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = {
10719 - { { 6 /* art */ }, 'i' }
10722 -static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = {
10723 - { { STATE_XTSYNC }, 'o' },
10724 - { { STATE_PSEXCM }, 'i' },
10725 - { { STATE_PSRING }, 'i' },
10726 - { { STATE_DATAPGSZID4 }, 'o' }
10729 -static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = {
10730 - { { 6 /* art */ }, 'm' }
10733 -static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = {
10734 - { { STATE_XTSYNC }, 'o' },
10735 - { { STATE_PSEXCM }, 'i' },
10736 - { { STATE_PSRING }, 'i' },
10737 - { { STATE_DATAPGSZID4 }, 'm' }
10740 -static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = {
10741 - { { 4 /* ars */ }, 'i' }
10744 -static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = {
10745 - { { STATE_PSEXCM }, 'i' },
10746 - { { STATE_PSRING }, 'i' },
10747 - { { STATE_XTSYNC }, 'o' }
10750 -static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = {
10751 - { { 6 /* art */ }, 'o' },
10752 - { { 4 /* ars */ }, 'i' }
10755 -static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = {
10756 - { { STATE_PSEXCM }, 'i' },
10757 - { { STATE_PSRING }, 'i' }
10760 -static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = {
10761 - { { 6 /* art */ }, 'i' },
10762 - { { 4 /* ars */ }, 'i' }
10765 -static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = {
10766 - { { STATE_PSEXCM }, 'i' },
10767 - { { STATE_PSRING }, 'i' },
10768 - { { STATE_XTSYNC }, 'o' }
10771 -static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = {
10772 - { { 4 /* ars */ }, 'i' }
10775 -static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = {
10776 - { { STATE_PSEXCM }, 'i' },
10777 - { { STATE_PSRING }, 'i' }
10780 -static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = {
10781 - { { 6 /* art */ }, 'o' },
10782 - { { 4 /* ars */ }, 'i' }
10785 -static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = {
10786 - { { STATE_PSEXCM }, 'i' },
10787 - { { STATE_PSRING }, 'i' }
10790 -static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = {
10791 - { { 6 /* art */ }, 'i' },
10792 - { { 4 /* ars */ }, 'i' }
10795 -static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = {
10796 - { { STATE_PSEXCM }, 'i' },
10797 - { { STATE_PSRING }, 'i' }
10800 -static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = {
10801 - { { STATE_PTBASE }, 'i' },
10802 - { { STATE_EXCVADDR }, 'i' }
10805 -static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = {
10806 - { { STATE_EXCVADDR }, 'i' }
10809 -static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = {
10810 - { { STATE_EXCVADDR }, 'i' }
10813 -static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = {
10814 - { { 6 /* art */ }, 'o' }
10817 -static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = {
10818 - { { STATE_PSEXCM }, 'i' },
10819 - { { STATE_PSRING }, 'i' },
10820 - { { STATE_CPENABLE }, 'i' }
10823 -static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = {
10824 - { { 6 /* art */ }, 'i' }
10827 -static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = {
10828 - { { STATE_PSEXCM }, 'i' },
10829 - { { STATE_PSRING }, 'i' },
10830 - { { STATE_CPENABLE }, 'o' }
10833 -static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = {
10834 - { { 6 /* art */ }, 'm' }
10837 -static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = {
10838 - { { STATE_PSEXCM }, 'i' },
10839 - { { STATE_PSRING }, 'i' },
10840 - { { STATE_CPENABLE }, 'm' }
10843 -static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = {
10844 - { { 3 /* arr */ }, 'o' },
10845 - { { 4 /* ars */ }, 'i' },
10846 - { { 58 /* tp7 */ }, 'i' }
10849 -static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = {
10850 - { { 3 /* arr */ }, 'o' },
10851 - { { 4 /* ars */ }, 'i' },
10852 - { { 6 /* art */ }, 'i' }
10855 -static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = {
10856 - { { 6 /* art */ }, 'o' },
10857 - { { 4 /* ars */ }, 'i' }
10860 -static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = {
10861 - { { 3 /* arr */ }, 'o' },
10862 - { { 4 /* ars */ }, 'i' },
10863 - { { 58 /* tp7 */ }, 'i' }
10866 -static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = {
10867 - { { 6 /* art */ }, 'o' },
10868 - { { 4 /* ars */ }, 'i' },
10869 - { { 21 /* uimm8x4 */ }, 'i' }
10872 -static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = {
10873 - { { 6 /* art */ }, 'i' },
10874 - { { 4 /* ars */ }, 'i' },
10875 - { { 21 /* uimm8x4 */ }, 'i' }
10878 -static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = {
10879 - { { 6 /* art */ }, 'm' },
10880 - { { 4 /* ars */ }, 'i' },
10881 - { { 21 /* uimm8x4 */ }, 'i' }
10884 -static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = {
10885 - { { STATE_SCOMPARE1 }, 'i' },
10886 - { { STATE_SCOMPARE1 }, 'i' }
10889 -static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = {
10890 - { { 6 /* art */ }, 'o' }
10893 -static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = {
10894 - { { STATE_SCOMPARE1 }, 'i' }
10897 -static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = {
10898 - { { 6 /* art */ }, 'i' }
10901 -static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = {
10902 - { { STATE_SCOMPARE1 }, 'o' }
10905 -static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = {
10906 - { { 6 /* art */ }, 'm' }
10909 -static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = {
10910 - { { STATE_SCOMPARE1 }, 'm' }
10913 -static xtensa_arg_internal Iclass_xt_iclass_div_args[] = {
10914 - { { 3 /* arr */ }, 'o' },
10915 - { { 4 /* ars */ }, 'i' },
10916 - { { 6 /* art */ }, 'i' }
10919 -static xtensa_arg_internal Iclass_xt_mul32_args[] = {
10920 - { { 3 /* arr */ }, 'o' },
10921 - { { 4 /* ars */ }, 'i' },
10922 - { { 6 /* art */ }, 'i' }
10925 -static xtensa_arg_internal Iclass_rur_fcr_args[] = {
10926 - { { 3 /* arr */ }, 'o' }
10929 -static xtensa_arg_internal Iclass_rur_fcr_stateArgs[] = {
10930 - { { STATE_RoundMode }, 'i' },
10931 - { { STATE_InvalidEnable }, 'i' },
10932 - { { STATE_DivZeroEnable }, 'i' },
10933 - { { STATE_OverflowEnable }, 'i' },
10934 - { { STATE_UnderflowEnable }, 'i' },
10935 - { { STATE_InexactEnable }, 'i' },
10936 - { { STATE_FPreserved20 }, 'i' },
10937 - { { STATE_FPreserved5 }, 'i' },
10938 - { { STATE_CPENABLE }, 'i' }
10941 -static xtensa_arg_internal Iclass_wur_fcr_args[] = {
10942 - { { 6 /* art */ }, 'i' }
10945 -static xtensa_arg_internal Iclass_wur_fcr_stateArgs[] = {
10946 - { { STATE_RoundMode }, 'o' },
10947 - { { STATE_InvalidEnable }, 'o' },
10948 - { { STATE_DivZeroEnable }, 'o' },
10949 - { { STATE_OverflowEnable }, 'o' },
10950 - { { STATE_UnderflowEnable }, 'o' },
10951 - { { STATE_InexactEnable }, 'o' },
10952 - { { STATE_FPreserved20 }, 'o' },
10953 - { { STATE_FPreserved5 }, 'o' },
10954 - { { STATE_CPENABLE }, 'i' }
10957 -static xtensa_arg_internal Iclass_rur_fsr_args[] = {
10958 - { { 3 /* arr */ }, 'o' }
10961 -static xtensa_arg_internal Iclass_rur_fsr_stateArgs[] = {
10962 - { { STATE_InvalidFlag }, 'i' },
10963 - { { STATE_DivZeroFlag }, 'i' },
10964 - { { STATE_OverflowFlag }, 'i' },
10965 - { { STATE_UnderflowFlag }, 'i' },
10966 - { { STATE_InexactFlag }, 'i' },
10967 - { { STATE_FPreserved20a }, 'i' },
10968 - { { STATE_FPreserved7 }, 'i' },
10969 - { { STATE_CPENABLE }, 'i' }
10972 -static xtensa_arg_internal Iclass_wur_fsr_args[] = {
10973 - { { 6 /* art */ }, 'i' }
10976 -static xtensa_arg_internal Iclass_wur_fsr_stateArgs[] = {
10977 - { { STATE_InvalidFlag }, 'o' },
10978 - { { STATE_DivZeroFlag }, 'o' },
10979 - { { STATE_OverflowFlag }, 'o' },
10980 - { { STATE_UnderflowFlag }, 'o' },
10981 - { { STATE_InexactFlag }, 'o' },
10982 - { { STATE_FPreserved20a }, 'o' },
10983 - { { STATE_FPreserved7 }, 'o' },
10984 - { { STATE_CPENABLE }, 'i' }
10987 -static xtensa_arg_internal Iclass_fp_args[] = {
10988 - { { 62 /* frr */ }, 'o' },
10989 - { { 63 /* frs */ }, 'i' },
10990 - { { 64 /* frt */ }, 'i' }
10993 -static xtensa_arg_internal Iclass_fp_stateArgs[] = {
10994 - { { STATE_RoundMode }, 'i' },
10995 - { { STATE_CPENABLE }, 'i' }
10998 -static xtensa_arg_internal Iclass_fp_mac_args[] = {
10999 - { { 62 /* frr */ }, 'm' },
11000 - { { 63 /* frs */ }, 'i' },
11001 - { { 64 /* frt */ }, 'i' }
11004 -static xtensa_arg_internal Iclass_fp_mac_stateArgs[] = {
11005 - { { STATE_RoundMode }, 'i' },
11006 - { { STATE_CPENABLE }, 'i' }
11009 -static xtensa_arg_internal Iclass_fp_cmov_args[] = {
11010 - { { 62 /* frr */ }, 'm' },
11011 - { { 63 /* frs */ }, 'i' },
11012 - { { 42 /* bt */ }, 'i' }
11015 -static xtensa_arg_internal Iclass_fp_cmov_stateArgs[] = {
11016 - { { STATE_CPENABLE }, 'i' }
11019 -static xtensa_arg_internal Iclass_fp_mov_args[] = {
11020 - { { 62 /* frr */ }, 'm' },
11021 - { { 63 /* frs */ }, 'i' },
11022 - { { 6 /* art */ }, 'i' }
11025 -static xtensa_arg_internal Iclass_fp_mov_stateArgs[] = {
11026 - { { STATE_CPENABLE }, 'i' }
11029 -static xtensa_arg_internal Iclass_fp_mov2_args[] = {
11030 - { { 62 /* frr */ }, 'o' },
11031 - { { 63 /* frs */ }, 'i' }
11034 -static xtensa_arg_internal Iclass_fp_mov2_stateArgs[] = {
11035 - { { STATE_CPENABLE }, 'i' }
11038 -static xtensa_arg_internal Iclass_fp_cmp_args[] = {
11039 - { { 44 /* br */ }, 'o' },
11040 - { { 63 /* frs */ }, 'i' },
11041 - { { 64 /* frt */ }, 'i' }
11044 -static xtensa_arg_internal Iclass_fp_cmp_stateArgs[] = {
11045 - { { STATE_CPENABLE }, 'i' }
11048 -static xtensa_arg_internal Iclass_fp_float_args[] = {
11049 - { { 62 /* frr */ }, 'o' },
11050 - { { 4 /* ars */ }, 'i' },
11051 - { { 65 /* t */ }, 'i' }
11054 -static xtensa_arg_internal Iclass_fp_float_stateArgs[] = {
11055 - { { STATE_RoundMode }, 'i' },
11056 - { { STATE_CPENABLE }, 'i' }
11059 -static xtensa_arg_internal Iclass_fp_int_args[] = {
11060 - { { 3 /* arr */ }, 'o' },
11061 - { { 63 /* frs */ }, 'i' },
11062 - { { 65 /* t */ }, 'i' }
11065 -static xtensa_arg_internal Iclass_fp_int_stateArgs[] = {
11066 - { { STATE_CPENABLE }, 'i' }
11069 -static xtensa_arg_internal Iclass_fp_rfr_args[] = {
11070 - { { 3 /* arr */ }, 'o' },
11071 - { { 63 /* frs */ }, 'i' }
11074 -static xtensa_arg_internal Iclass_fp_rfr_stateArgs[] = {
11075 - { { STATE_CPENABLE }, 'i' }
11078 -static xtensa_arg_internal Iclass_fp_wfr_args[] = {
11079 - { { 62 /* frr */ }, 'o' },
11080 - { { 4 /* ars */ }, 'i' }
11083 -static xtensa_arg_internal Iclass_fp_wfr_stateArgs[] = {
11084 - { { STATE_CPENABLE }, 'i' }
11087 -static xtensa_arg_internal Iclass_fp_lsi_args[] = {
11088 - { { 64 /* frt */ }, 'o' },
11089 - { { 4 /* ars */ }, 'i' },
11090 - { { 61 /* cimm8x4 */ }, 'i' }
11093 -static xtensa_arg_internal Iclass_fp_lsi_stateArgs[] = {
11094 - { { STATE_CPENABLE }, 'i' }
11097 -static xtensa_arg_internal Iclass_fp_lsiu_args[] = {
11098 - { { 64 /* frt */ }, 'o' },
11099 - { { 4 /* ars */ }, 'm' },
11100 - { { 61 /* cimm8x4 */ }, 'i' }
11103 -static xtensa_arg_internal Iclass_fp_lsiu_stateArgs[] = {
11104 - { { STATE_CPENABLE }, 'i' }
11107 -static xtensa_arg_internal Iclass_fp_lsx_args[] = {
11108 - { { 62 /* frr */ }, 'o' },
11109 - { { 4 /* ars */ }, 'i' },
11110 - { { 6 /* art */ }, 'i' }
11113 -static xtensa_arg_internal Iclass_fp_lsx_stateArgs[] = {
11114 - { { STATE_CPENABLE }, 'i' }
11117 -static xtensa_arg_internal Iclass_fp_lsxu_args[] = {
11118 - { { 62 /* frr */ }, 'o' },
11119 - { { 4 /* ars */ }, 'm' },
11120 - { { 6 /* art */ }, 'i' }
11123 -static xtensa_arg_internal Iclass_fp_lsxu_stateArgs[] = {
11124 - { { STATE_CPENABLE }, 'i' }
11127 -static xtensa_arg_internal Iclass_fp_ssi_args[] = {
11128 - { { 64 /* frt */ }, 'i' },
11129 - { { 4 /* ars */ }, 'i' },
11130 - { { 61 /* cimm8x4 */ }, 'i' }
11133 -static xtensa_arg_internal Iclass_fp_ssi_stateArgs[] = {
11134 - { { STATE_CPENABLE }, 'i' }
11137 -static xtensa_arg_internal Iclass_fp_ssiu_args[] = {
11138 - { { 64 /* frt */ }, 'i' },
11139 - { { 4 /* ars */ }, 'm' },
11140 - { { 61 /* cimm8x4 */ }, 'i' }
11143 -static xtensa_arg_internal Iclass_fp_ssiu_stateArgs[] = {
11144 - { { STATE_CPENABLE }, 'i' }
11147 -static xtensa_arg_internal Iclass_fp_ssx_args[] = {
11148 - { { 62 /* frr */ }, 'i' },
11149 - { { 4 /* ars */ }, 'i' },
11150 - { { 6 /* art */ }, 'i' }
11153 -static xtensa_arg_internal Iclass_fp_ssx_stateArgs[] = {
11154 - { { STATE_CPENABLE }, 'i' }
11157 -static xtensa_arg_internal Iclass_fp_ssxu_args[] = {
11158 - { { 62 /* frr */ }, 'i' },
11159 - { { 4 /* ars */ }, 'm' },
11160 - { { 6 /* art */ }, 'i' }
11163 -static xtensa_arg_internal Iclass_fp_ssxu_stateArgs[] = {
11164 - { { STATE_CPENABLE }, 'i' }
11167 -static xtensa_arg_internal Iclass_xt_iclass_wb18_0_args[] = {
11168 - { { 4 /* ars */ }, 'i' },
11169 - { { 60 /* xt_wbr18_label */ }, 'i' }
11172 -static xtensa_arg_internal Iclass_xt_iclass_wb18_1_args[] = {
11173 - { { 4 /* ars */ }, 'i' },
11174 - { { 17 /* b4const */ }, 'i' },
11175 - { { 60 /* xt_wbr18_label */ }, 'i' }
11178 -static xtensa_arg_internal Iclass_xt_iclass_wb18_2_args[] = {
11179 - { { 4 /* ars */ }, 'i' },
11180 - { { 18 /* b4constu */ }, 'i' },
11181 - { { 60 /* xt_wbr18_label */ }, 'i' }
11184 -static xtensa_arg_internal Iclass_xt_iclass_wb18_3_args[] = {
11185 - { { 4 /* ars */ }, 'i' },
11186 - { { 67 /* bbi */ }, 'i' },
11187 - { { 60 /* xt_wbr18_label */ }, 'i' }
11190 -static xtensa_arg_internal Iclass_xt_iclass_wb18_4_args[] = {
11191 - { { 4 /* ars */ }, 'i' },
11192 - { { 6 /* art */ }, 'i' },
11193 - { { 60 /* xt_wbr18_label */ }, 'i' }
11196 -static xtensa_iclass_internal iclasses[] = {
11197 - { 0, 0 /* xt_iclass_excw */,
11199 - { 0, 0 /* xt_iclass_rfe */,
11200 - 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
11201 - { 0, 0 /* xt_iclass_rfde */,
11202 - 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
11203 - { 0, 0 /* xt_iclass_syscall */,
11205 - { 0, 0 /* xt_iclass_simcall */,
11207 - { 2, Iclass_xt_iclass_call12_args,
11208 - 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
11209 - { 2, Iclass_xt_iclass_call8_args,
11210 - 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 },
11211 - { 2, Iclass_xt_iclass_call4_args,
11212 - 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 },
11213 - { 2, Iclass_xt_iclass_callx12_args,
11214 - 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 },
11215 - { 2, Iclass_xt_iclass_callx8_args,
11216 - 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 },
11217 - { 2, Iclass_xt_iclass_callx4_args,
11218 - 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 },
11219 - { 3, Iclass_xt_iclass_entry_args,
11220 - 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 },
11221 - { 2, Iclass_xt_iclass_movsp_args,
11222 - 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 },
11223 - { 1, Iclass_xt_iclass_rotw_args,
11224 - 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 },
11225 - { 1, Iclass_xt_iclass_retw_args,
11226 - 4, Iclass_xt_iclass_retw_stateArgs, 0, 0 },
11227 - { 0, 0 /* xt_iclass_rfwou */,
11228 - 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 },
11229 - { 3, Iclass_xt_iclass_l32e_args,
11230 - 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 },
11231 - { 3, Iclass_xt_iclass_s32e_args,
11232 - 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 },
11233 - { 1, Iclass_xt_iclass_rsr_windowbase_args,
11234 - 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 },
11235 - { 1, Iclass_xt_iclass_wsr_windowbase_args,
11236 - 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 },
11237 - { 1, Iclass_xt_iclass_xsr_windowbase_args,
11238 - 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 },
11239 - { 1, Iclass_xt_iclass_rsr_windowstart_args,
11240 - 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 },
11241 - { 1, Iclass_xt_iclass_wsr_windowstart_args,
11242 - 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 },
11243 - { 1, Iclass_xt_iclass_xsr_windowstart_args,
11244 - 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 },
11245 - { 3, Iclass_xt_iclass_add_n_args,
11247 - { 3, Iclass_xt_iclass_addi_n_args,
11249 - { 2, Iclass_xt_iclass_bz6_args,
11251 - { 0, 0 /* xt_iclass_ill_n */,
11253 - { 3, Iclass_xt_iclass_loadi4_args,
11255 - { 2, Iclass_xt_iclass_mov_n_args,
11257 - { 2, Iclass_xt_iclass_movi_n_args,
11259 - { 0, 0 /* xt_iclass_nopn */,
11261 - { 1, Iclass_xt_iclass_retn_args,
11263 - { 3, Iclass_xt_iclass_storei4_args,
11265 - { 1, Iclass_rur_threadptr_args,
11266 - 1, Iclass_rur_threadptr_stateArgs, 0, 0 },
11267 - { 1, Iclass_wur_threadptr_args,
11268 - 1, Iclass_wur_threadptr_stateArgs, 0, 0 },
11269 - { 3, Iclass_xt_iclass_addi_args,
11271 - { 3, Iclass_xt_iclass_addmi_args,
11273 - { 3, Iclass_xt_iclass_addsub_args,
11275 - { 3, Iclass_xt_iclass_bit_args,
11277 - { 3, Iclass_xt_iclass_bsi8_args,
11279 - { 3, Iclass_xt_iclass_bsi8b_args,
11281 - { 3, Iclass_xt_iclass_bsi8u_args,
11283 - { 3, Iclass_xt_iclass_bst8_args,
11285 - { 2, Iclass_xt_iclass_bsz12_args,
11287 - { 2, Iclass_xt_iclass_call0_args,
11289 - { 2, Iclass_xt_iclass_callx0_args,
11291 - { 4, Iclass_xt_iclass_exti_args,
11293 - { 0, 0 /* xt_iclass_ill */,
11295 - { 1, Iclass_xt_iclass_jump_args,
11297 - { 1, Iclass_xt_iclass_jumpx_args,
11299 - { 3, Iclass_xt_iclass_l16ui_args,
11301 - { 3, Iclass_xt_iclass_l16si_args,
11303 - { 3, Iclass_xt_iclass_l32i_args,
11305 - { 2, Iclass_xt_iclass_l32r_args,
11306 - 2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 },
11307 - { 3, Iclass_xt_iclass_l8i_args,
11309 - { 2, Iclass_xt_iclass_loop_args,
11310 - 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 },
11311 - { 2, Iclass_xt_iclass_loopz_args,
11312 - 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 },
11313 - { 2, Iclass_xt_iclass_movi_args,
11315 - { 3, Iclass_xt_iclass_movz_args,
11317 - { 2, Iclass_xt_iclass_neg_args,
11319 - { 0, 0 /* xt_iclass_nop */,
11321 - { 1, Iclass_xt_iclass_return_args,
11323 - { 3, Iclass_xt_iclass_s16i_args,
11325 - { 3, Iclass_xt_iclass_s32i_args,
11327 - { 3, Iclass_xt_iclass_s8i_args,
11329 - { 1, Iclass_xt_iclass_sar_args,
11330 - 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
11331 - { 1, Iclass_xt_iclass_sari_args,
11332 - 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
11333 - { 2, Iclass_xt_iclass_shifts_args,
11334 - 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
11335 - { 3, Iclass_xt_iclass_shiftst_args,
11336 - 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
11337 - { 2, Iclass_xt_iclass_shiftt_args,
11338 - 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
11339 - { 3, Iclass_xt_iclass_slli_args,
11341 - { 3, Iclass_xt_iclass_srai_args,
11343 - { 3, Iclass_xt_iclass_srli_args,
11345 - { 0, 0 /* xt_iclass_memw */,
11347 - { 0, 0 /* xt_iclass_extw */,
11349 - { 0, 0 /* xt_iclass_isync */,
11351 - { 0, 0 /* xt_iclass_sync */,
11352 - 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
11353 - { 2, Iclass_xt_iclass_rsil_args,
11354 - 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
11355 - { 1, Iclass_xt_iclass_rsr_lend_args,
11356 - 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 },
11357 - { 1, Iclass_xt_iclass_wsr_lend_args,
11358 - 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 },
11359 - { 1, Iclass_xt_iclass_xsr_lend_args,
11360 - 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 },
11361 - { 1, Iclass_xt_iclass_rsr_lcount_args,
11362 - 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 },
11363 - { 1, Iclass_xt_iclass_wsr_lcount_args,
11364 - 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 },
11365 - { 1, Iclass_xt_iclass_xsr_lcount_args,
11366 - 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 },
11367 - { 1, Iclass_xt_iclass_rsr_lbeg_args,
11368 - 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 },
11369 - { 1, Iclass_xt_iclass_wsr_lbeg_args,
11370 - 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 },
11371 - { 1, Iclass_xt_iclass_xsr_lbeg_args,
11372 - 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 },
11373 - { 1, Iclass_xt_iclass_rsr_sar_args,
11374 - 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
11375 - { 1, Iclass_xt_iclass_wsr_sar_args,
11376 - 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
11377 - { 1, Iclass_xt_iclass_xsr_sar_args,
11378 - 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
11379 - { 1, Iclass_xt_iclass_rsr_litbase_args,
11380 - 2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 },
11381 - { 1, Iclass_xt_iclass_wsr_litbase_args,
11382 - 2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 },
11383 - { 1, Iclass_xt_iclass_xsr_litbase_args,
11384 - 2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 },
11385 - { 1, Iclass_xt_iclass_rsr_176_args,
11386 - 2, Iclass_xt_iclass_rsr_176_stateArgs, 0, 0 },
11387 - { 1, Iclass_xt_iclass_rsr_208_args,
11388 - 2, Iclass_xt_iclass_rsr_208_stateArgs, 0, 0 },
11389 - { 1, Iclass_xt_iclass_rsr_ps_args,
11390 - 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
11391 - { 1, Iclass_xt_iclass_wsr_ps_args,
11392 - 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
11393 - { 1, Iclass_xt_iclass_xsr_ps_args,
11394 - 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
11395 - { 1, Iclass_xt_iclass_rsr_epc1_args,
11396 - 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
11397 - { 1, Iclass_xt_iclass_wsr_epc1_args,
11398 - 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
11399 - { 1, Iclass_xt_iclass_xsr_epc1_args,
11400 - 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
11401 - { 1, Iclass_xt_iclass_rsr_excsave1_args,
11402 - 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
11403 - { 1, Iclass_xt_iclass_wsr_excsave1_args,
11404 - 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
11405 - { 1, Iclass_xt_iclass_xsr_excsave1_args,
11406 - 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
11407 - { 1, Iclass_xt_iclass_rsr_epc2_args,
11408 - 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
11409 - { 1, Iclass_xt_iclass_wsr_epc2_args,
11410 - 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
11411 - { 1, Iclass_xt_iclass_xsr_epc2_args,
11412 - 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
11413 - { 1, Iclass_xt_iclass_rsr_excsave2_args,
11414 - 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
11415 - { 1, Iclass_xt_iclass_wsr_excsave2_args,
11416 - 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
11417 - { 1, Iclass_xt_iclass_xsr_excsave2_args,
11418 - 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
11419 - { 1, Iclass_xt_iclass_rsr_epc3_args,
11420 - 3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 },
11421 - { 1, Iclass_xt_iclass_wsr_epc3_args,
11422 - 3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 },
11423 - { 1, Iclass_xt_iclass_xsr_epc3_args,
11424 - 3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 },
11425 - { 1, Iclass_xt_iclass_rsr_excsave3_args,
11426 - 3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 },
11427 - { 1, Iclass_xt_iclass_wsr_excsave3_args,
11428 - 3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 },
11429 - { 1, Iclass_xt_iclass_xsr_excsave3_args,
11430 - 3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 },
11431 - { 1, Iclass_xt_iclass_rsr_epc4_args,
11432 - 3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 },
11433 - { 1, Iclass_xt_iclass_wsr_epc4_args,
11434 - 3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 },
11435 - { 1, Iclass_xt_iclass_xsr_epc4_args,
11436 - 3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 },
11437 - { 1, Iclass_xt_iclass_rsr_excsave4_args,
11438 - 3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 },
11439 - { 1, Iclass_xt_iclass_wsr_excsave4_args,
11440 - 3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 },
11441 - { 1, Iclass_xt_iclass_xsr_excsave4_args,
11442 - 3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 },
11443 - { 1, Iclass_xt_iclass_rsr_epc5_args,
11444 - 3, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 },
11445 - { 1, Iclass_xt_iclass_wsr_epc5_args,
11446 - 3, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 },
11447 - { 1, Iclass_xt_iclass_xsr_epc5_args,
11448 - 3, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 },
11449 - { 1, Iclass_xt_iclass_rsr_excsave5_args,
11450 - 3, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 },
11451 - { 1, Iclass_xt_iclass_wsr_excsave5_args,
11452 - 3, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 },
11453 - { 1, Iclass_xt_iclass_xsr_excsave5_args,
11454 - 3, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 },
11455 - { 1, Iclass_xt_iclass_rsr_epc6_args,
11456 - 3, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 },
11457 - { 1, Iclass_xt_iclass_wsr_epc6_args,
11458 - 3, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 },
11459 - { 1, Iclass_xt_iclass_xsr_epc6_args,
11460 - 3, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 },
11461 - { 1, Iclass_xt_iclass_rsr_excsave6_args,
11462 - 3, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 },
11463 - { 1, Iclass_xt_iclass_wsr_excsave6_args,
11464 - 3, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 },
11465 - { 1, Iclass_xt_iclass_xsr_excsave6_args,
11466 - 3, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 },
11467 - { 1, Iclass_xt_iclass_rsr_epc7_args,
11468 - 3, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 },
11469 - { 1, Iclass_xt_iclass_wsr_epc7_args,
11470 - 3, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 },
11471 - { 1, Iclass_xt_iclass_xsr_epc7_args,
11472 - 3, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 },
11473 - { 1, Iclass_xt_iclass_rsr_excsave7_args,
11474 - 3, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 },
11475 - { 1, Iclass_xt_iclass_wsr_excsave7_args,
11476 - 3, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 },
11477 - { 1, Iclass_xt_iclass_xsr_excsave7_args,
11478 - 3, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 },
11479 - { 1, Iclass_xt_iclass_rsr_eps2_args,
11480 - 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
11481 - { 1, Iclass_xt_iclass_wsr_eps2_args,
11482 - 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
11483 - { 1, Iclass_xt_iclass_xsr_eps2_args,
11484 - 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
11485 - { 1, Iclass_xt_iclass_rsr_eps3_args,
11486 - 3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 },
11487 - { 1, Iclass_xt_iclass_wsr_eps3_args,
11488 - 3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 },
11489 - { 1, Iclass_xt_iclass_xsr_eps3_args,
11490 - 3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 },
11491 - { 1, Iclass_xt_iclass_rsr_eps4_args,
11492 - 3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 },
11493 - { 1, Iclass_xt_iclass_wsr_eps4_args,
11494 - 3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 },
11495 - { 1, Iclass_xt_iclass_xsr_eps4_args,
11496 - 3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 },
11497 - { 1, Iclass_xt_iclass_rsr_eps5_args,
11498 - 3, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 },
11499 - { 1, Iclass_xt_iclass_wsr_eps5_args,
11500 - 3, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 },
11501 - { 1, Iclass_xt_iclass_xsr_eps5_args,
11502 - 3, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 },
11503 - { 1, Iclass_xt_iclass_rsr_eps6_args,
11504 - 3, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 },
11505 - { 1, Iclass_xt_iclass_wsr_eps6_args,
11506 - 3, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 },
11507 - { 1, Iclass_xt_iclass_xsr_eps6_args,
11508 - 3, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 },
11509 - { 1, Iclass_xt_iclass_rsr_eps7_args,
11510 - 3, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 },
11511 - { 1, Iclass_xt_iclass_wsr_eps7_args,
11512 - 3, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 },
11513 - { 1, Iclass_xt_iclass_xsr_eps7_args,
11514 - 3, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 },
11515 - { 1, Iclass_xt_iclass_rsr_excvaddr_args,
11516 - 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
11517 - { 1, Iclass_xt_iclass_wsr_excvaddr_args,
11518 - 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
11519 - { 1, Iclass_xt_iclass_xsr_excvaddr_args,
11520 - 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
11521 - { 1, Iclass_xt_iclass_rsr_depc_args,
11522 - 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
11523 - { 1, Iclass_xt_iclass_wsr_depc_args,
11524 - 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
11525 - { 1, Iclass_xt_iclass_xsr_depc_args,
11526 - 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
11527 - { 1, Iclass_xt_iclass_rsr_exccause_args,
11528 - 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
11529 - { 1, Iclass_xt_iclass_wsr_exccause_args,
11530 - 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
11531 - { 1, Iclass_xt_iclass_xsr_exccause_args,
11532 - 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
11533 - { 1, Iclass_xt_iclass_rsr_misc0_args,
11534 - 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 },
11535 - { 1, Iclass_xt_iclass_wsr_misc0_args,
11536 - 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 },
11537 - { 1, Iclass_xt_iclass_xsr_misc0_args,
11538 - 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 },
11539 - { 1, Iclass_xt_iclass_rsr_misc1_args,
11540 - 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 },
11541 - { 1, Iclass_xt_iclass_wsr_misc1_args,
11542 - 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 },
11543 - { 1, Iclass_xt_iclass_xsr_misc1_args,
11544 - 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 },
11545 - { 1, Iclass_xt_iclass_rsr_misc2_args,
11546 - 3, Iclass_xt_iclass_rsr_misc2_stateArgs, 0, 0 },
11547 - { 1, Iclass_xt_iclass_wsr_misc2_args,
11548 - 3, Iclass_xt_iclass_wsr_misc2_stateArgs, 0, 0 },
11549 - { 1, Iclass_xt_iclass_xsr_misc2_args,
11550 - 3, Iclass_xt_iclass_xsr_misc2_stateArgs, 0, 0 },
11551 - { 1, Iclass_xt_iclass_rsr_misc3_args,
11552 - 3, Iclass_xt_iclass_rsr_misc3_stateArgs, 0, 0 },
11553 - { 1, Iclass_xt_iclass_wsr_misc3_args,
11554 - 3, Iclass_xt_iclass_wsr_misc3_stateArgs, 0, 0 },
11555 - { 1, Iclass_xt_iclass_xsr_misc3_args,
11556 - 3, Iclass_xt_iclass_xsr_misc3_stateArgs, 0, 0 },
11557 - { 1, Iclass_xt_iclass_rsr_prid_args,
11558 - 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 },
11559 - { 1, Iclass_xt_iclass_rsr_vecbase_args,
11560 - 3, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 },
11561 - { 1, Iclass_xt_iclass_wsr_vecbase_args,
11562 - 3, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 },
11563 - { 1, Iclass_xt_iclass_xsr_vecbase_args,
11564 - 3, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 },
11565 - { 2, Iclass_xt_iclass_mac16_aa_args,
11566 - 1, Iclass_xt_iclass_mac16_aa_stateArgs, 0, 0 },
11567 - { 2, Iclass_xt_iclass_mac16_ad_args,
11568 - 1, Iclass_xt_iclass_mac16_ad_stateArgs, 0, 0 },
11569 - { 2, Iclass_xt_iclass_mac16_da_args,
11570 - 1, Iclass_xt_iclass_mac16_da_stateArgs, 0, 0 },
11571 - { 2, Iclass_xt_iclass_mac16_dd_args,
11572 - 1, Iclass_xt_iclass_mac16_dd_stateArgs, 0, 0 },
11573 - { 2, Iclass_xt_iclass_mac16a_aa_args,
11574 - 1, Iclass_xt_iclass_mac16a_aa_stateArgs, 0, 0 },
11575 - { 2, Iclass_xt_iclass_mac16a_ad_args,
11576 - 1, Iclass_xt_iclass_mac16a_ad_stateArgs, 0, 0 },
11577 - { 2, Iclass_xt_iclass_mac16a_da_args,
11578 - 1, Iclass_xt_iclass_mac16a_da_stateArgs, 0, 0 },
11579 - { 2, Iclass_xt_iclass_mac16a_dd_args,
11580 - 1, Iclass_xt_iclass_mac16a_dd_stateArgs, 0, 0 },
11581 - { 4, Iclass_xt_iclass_mac16al_da_args,
11582 - 1, Iclass_xt_iclass_mac16al_da_stateArgs, 0, 0 },
11583 - { 4, Iclass_xt_iclass_mac16al_dd_args,
11584 - 1, Iclass_xt_iclass_mac16al_dd_stateArgs, 0, 0 },
11585 - { 2, Iclass_xt_iclass_mac16_l_args,
11587 - { 3, Iclass_xt_iclass_mul16_args,
11589 - { 2, Iclass_xt_iclass_rsr_m0_args,
11591 - { 2, Iclass_xt_iclass_wsr_m0_args,
11593 - { 2, Iclass_xt_iclass_xsr_m0_args,
11595 - { 2, Iclass_xt_iclass_rsr_m1_args,
11597 - { 2, Iclass_xt_iclass_wsr_m1_args,
11599 - { 2, Iclass_xt_iclass_xsr_m1_args,
11601 - { 2, Iclass_xt_iclass_rsr_m2_args,
11603 - { 2, Iclass_xt_iclass_wsr_m2_args,
11605 - { 2, Iclass_xt_iclass_xsr_m2_args,
11607 - { 2, Iclass_xt_iclass_rsr_m3_args,
11609 - { 2, Iclass_xt_iclass_wsr_m3_args,
11611 - { 2, Iclass_xt_iclass_xsr_m3_args,
11613 - { 1, Iclass_xt_iclass_rsr_acclo_args,
11614 - 1, Iclass_xt_iclass_rsr_acclo_stateArgs, 0, 0 },
11615 - { 1, Iclass_xt_iclass_wsr_acclo_args,
11616 - 1, Iclass_xt_iclass_wsr_acclo_stateArgs, 0, 0 },
11617 - { 1, Iclass_xt_iclass_xsr_acclo_args,
11618 - 1, Iclass_xt_iclass_xsr_acclo_stateArgs, 0, 0 },
11619 - { 1, Iclass_xt_iclass_rsr_acchi_args,
11620 - 1, Iclass_xt_iclass_rsr_acchi_stateArgs, 0, 0 },
11621 - { 1, Iclass_xt_iclass_wsr_acchi_args,
11622 - 1, Iclass_xt_iclass_wsr_acchi_stateArgs, 0, 0 },
11623 - { 1, Iclass_xt_iclass_xsr_acchi_args,
11624 - 1, Iclass_xt_iclass_xsr_acchi_stateArgs, 0, 0 },
11625 - { 1, Iclass_xt_iclass_rfi_args,
11626 - 21, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
11627 - { 1, Iclass_xt_iclass_wait_args,
11628 - 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
11629 - { 1, Iclass_xt_iclass_rsr_interrupt_args,
11630 - 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
11631 - { 1, Iclass_xt_iclass_wsr_intset_args,
11632 - 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
11633 - { 1, Iclass_xt_iclass_wsr_intclear_args,
11634 - 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
11635 - { 1, Iclass_xt_iclass_rsr_intenable_args,
11636 - 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
11637 - { 1, Iclass_xt_iclass_wsr_intenable_args,
11638 - 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
11639 - { 1, Iclass_xt_iclass_xsr_intenable_args,
11640 - 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
11641 - { 2, Iclass_xt_iclass_break_args,
11642 - 2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
11643 - { 1, Iclass_xt_iclass_break_n_args,
11644 - 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
11645 - { 1, Iclass_xt_iclass_rsr_dbreaka0_args,
11646 - 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 },
11647 - { 1, Iclass_xt_iclass_wsr_dbreaka0_args,
11648 - 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 },
11649 - { 1, Iclass_xt_iclass_xsr_dbreaka0_args,
11650 - 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 },
11651 - { 1, Iclass_xt_iclass_rsr_dbreakc0_args,
11652 - 3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 },
11653 - { 1, Iclass_xt_iclass_wsr_dbreakc0_args,
11654 - 4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 },
11655 - { 1, Iclass_xt_iclass_xsr_dbreakc0_args,
11656 - 4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 },
11657 - { 1, Iclass_xt_iclass_rsr_dbreaka1_args,
11658 - 3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 },
11659 - { 1, Iclass_xt_iclass_wsr_dbreaka1_args,
11660 - 4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 },
11661 - { 1, Iclass_xt_iclass_xsr_dbreaka1_args,
11662 - 4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 },
11663 - { 1, Iclass_xt_iclass_rsr_dbreakc1_args,
11664 - 3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 },
11665 - { 1, Iclass_xt_iclass_wsr_dbreakc1_args,
11666 - 4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 },
11667 - { 1, Iclass_xt_iclass_xsr_dbreakc1_args,
11668 - 4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 },
11669 - { 1, Iclass_xt_iclass_rsr_ibreaka0_args,
11670 - 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 },
11671 - { 1, Iclass_xt_iclass_wsr_ibreaka0_args,
11672 - 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 },
11673 - { 1, Iclass_xt_iclass_xsr_ibreaka0_args,
11674 - 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 },
11675 - { 1, Iclass_xt_iclass_rsr_ibreaka1_args,
11676 - 3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 },
11677 - { 1, Iclass_xt_iclass_wsr_ibreaka1_args,
11678 - 3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 },
11679 - { 1, Iclass_xt_iclass_xsr_ibreaka1_args,
11680 - 3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 },
11681 - { 1, Iclass_xt_iclass_rsr_ibreakenable_args,
11682 - 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 },
11683 - { 1, Iclass_xt_iclass_wsr_ibreakenable_args,
11684 - 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 },
11685 - { 1, Iclass_xt_iclass_xsr_ibreakenable_args,
11686 - 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 },
11687 - { 1, Iclass_xt_iclass_rsr_debugcause_args,
11688 - 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
11689 - { 1, Iclass_xt_iclass_wsr_debugcause_args,
11690 - 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
11691 - { 1, Iclass_xt_iclass_xsr_debugcause_args,
11692 - 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
11693 - { 1, Iclass_xt_iclass_rsr_icount_args,
11694 - 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
11695 - { 1, Iclass_xt_iclass_wsr_icount_args,
11696 - 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
11697 - { 1, Iclass_xt_iclass_xsr_icount_args,
11698 - 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
11699 - { 1, Iclass_xt_iclass_rsr_icountlevel_args,
11700 - 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
11701 - { 1, Iclass_xt_iclass_wsr_icountlevel_args,
11702 - 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
11703 - { 1, Iclass_xt_iclass_xsr_icountlevel_args,
11704 - 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
11705 - { 1, Iclass_xt_iclass_rsr_ddr_args,
11706 - 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
11707 - { 1, Iclass_xt_iclass_wsr_ddr_args,
11708 - 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
11709 - { 1, Iclass_xt_iclass_xsr_ddr_args,
11710 - 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
11711 - { 1, Iclass_xt_iclass_rfdo_args,
11712 - 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
11713 - { 0, 0 /* xt_iclass_rfdd */,
11714 - 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
11715 - { 1, Iclass_xt_iclass_wsr_mmid_args,
11716 - 3, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 },
11717 - { 3, Iclass_xt_iclass_bbool1_args,
11719 - { 2, Iclass_xt_iclass_bbool4_args,
11721 - { 2, Iclass_xt_iclass_bbool8_args,
11723 - { 2, Iclass_xt_iclass_bbranch_args,
11725 - { 3, Iclass_xt_iclass_bmove_args,
11727 - { 2, Iclass_xt_iclass_RSR_BR_args,
11729 - { 2, Iclass_xt_iclass_WSR_BR_args,
11731 - { 2, Iclass_xt_iclass_XSR_BR_args,
11733 - { 1, Iclass_xt_iclass_rsr_ccount_args,
11734 - 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
11735 - { 1, Iclass_xt_iclass_wsr_ccount_args,
11736 - 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
11737 - { 1, Iclass_xt_iclass_xsr_ccount_args,
11738 - 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
11739 - { 1, Iclass_xt_iclass_rsr_ccompare0_args,
11740 - 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
11741 - { 1, Iclass_xt_iclass_wsr_ccompare0_args,
11742 - 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
11743 - { 1, Iclass_xt_iclass_xsr_ccompare0_args,
11744 - 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
11745 - { 1, Iclass_xt_iclass_rsr_ccompare1_args,
11746 - 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 },
11747 - { 1, Iclass_xt_iclass_wsr_ccompare1_args,
11748 - 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 },
11749 - { 1, Iclass_xt_iclass_xsr_ccompare1_args,
11750 - 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 },
11751 - { 1, Iclass_xt_iclass_rsr_ccompare2_args,
11752 - 3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 },
11753 - { 1, Iclass_xt_iclass_wsr_ccompare2_args,
11754 - 4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 },
11755 - { 1, Iclass_xt_iclass_xsr_ccompare2_args,
11756 - 4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 },
11757 - { 2, Iclass_xt_iclass_icache_args,
11759 - { 2, Iclass_xt_iclass_icache_lock_args,
11760 - 2, Iclass_xt_iclass_icache_lock_stateArgs, 0, 0 },
11761 - { 2, Iclass_xt_iclass_icache_inv_args,
11762 - 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 },
11763 - { 2, Iclass_xt_iclass_licx_args,
11764 - 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 },
11765 - { 2, Iclass_xt_iclass_sicx_args,
11766 - 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 },
11767 - { 2, Iclass_xt_iclass_dcache_args,
11769 - { 2, Iclass_xt_iclass_dcache_ind_args,
11770 - 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 },
11771 - { 2, Iclass_xt_iclass_dcache_inv_args,
11772 - 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 },
11773 - { 2, Iclass_xt_iclass_dpf_args,
11775 - { 2, Iclass_xt_iclass_dcache_lock_args,
11776 - 2, Iclass_xt_iclass_dcache_lock_stateArgs, 0, 0 },
11777 - { 2, Iclass_xt_iclass_sdct_args,
11778 - 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 },
11779 - { 2, Iclass_xt_iclass_ldct_args,
11780 - 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 },
11781 - { 1, Iclass_xt_iclass_wsr_ptevaddr_args,
11782 - 4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 },
11783 - { 1, Iclass_xt_iclass_rsr_ptevaddr_args,
11784 - 4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 },
11785 - { 1, Iclass_xt_iclass_xsr_ptevaddr_args,
11786 - 5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 },
11787 - { 1, Iclass_xt_iclass_rsr_rasid_args,
11788 - 5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 },
11789 - { 1, Iclass_xt_iclass_wsr_rasid_args,
11790 - 6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 },
11791 - { 1, Iclass_xt_iclass_xsr_rasid_args,
11792 - 6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 },
11793 - { 1, Iclass_xt_iclass_rsr_itlbcfg_args,
11794 - 3, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 },
11795 - { 1, Iclass_xt_iclass_wsr_itlbcfg_args,
11796 - 4, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 },
11797 - { 1, Iclass_xt_iclass_xsr_itlbcfg_args,
11798 - 4, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 },
11799 - { 1, Iclass_xt_iclass_rsr_dtlbcfg_args,
11800 - 3, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 },
11801 - { 1, Iclass_xt_iclass_wsr_dtlbcfg_args,
11802 - 4, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 },
11803 - { 1, Iclass_xt_iclass_xsr_dtlbcfg_args,
11804 - 4, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 },
11805 - { 1, Iclass_xt_iclass_idtlb_args,
11806 - 3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
11807 - { 2, Iclass_xt_iclass_rdtlb_args,
11808 - 2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 },
11809 - { 2, Iclass_xt_iclass_wdtlb_args,
11810 - 3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
11811 - { 1, Iclass_xt_iclass_iitlb_args,
11812 - 2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 },
11813 - { 2, Iclass_xt_iclass_ritlb_args,
11814 - 2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 },
11815 - { 2, Iclass_xt_iclass_witlb_args,
11816 - 2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 },
11817 - { 0, 0 /* xt_iclass_ldpte */,
11818 - 2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 },
11819 - { 0, 0 /* xt_iclass_hwwitlba */,
11820 - 1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 },
11821 - { 0, 0 /* xt_iclass_hwwdtlba */,
11822 - 1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 },
11823 - { 1, Iclass_xt_iclass_rsr_cpenable_args,
11824 - 3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 },
11825 - { 1, Iclass_xt_iclass_wsr_cpenable_args,
11826 - 3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 },
11827 - { 1, Iclass_xt_iclass_xsr_cpenable_args,
11828 - 3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 },
11829 - { 3, Iclass_xt_iclass_clamp_args,
11831 - { 3, Iclass_xt_iclass_minmax_args,
11833 - { 2, Iclass_xt_iclass_nsa_args,
11835 - { 3, Iclass_xt_iclass_sx_args,
11837 - { 3, Iclass_xt_iclass_l32ai_args,
11839 - { 3, Iclass_xt_iclass_s32ri_args,
11841 - { 3, Iclass_xt_iclass_s32c1i_args,
11842 - 2, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 },
11843 - { 1, Iclass_xt_iclass_rsr_scompare1_args,
11844 - 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 },
11845 - { 1, Iclass_xt_iclass_wsr_scompare1_args,
11846 - 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 },
11847 - { 1, Iclass_xt_iclass_xsr_scompare1_args,
11848 - 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 },
11849 - { 3, Iclass_xt_iclass_div_args,
11851 - { 3, Iclass_xt_mul32_args,
11853 - { 1, Iclass_rur_fcr_args,
11854 - 9, Iclass_rur_fcr_stateArgs, 0, 0 },
11855 - { 1, Iclass_wur_fcr_args,
11856 - 9, Iclass_wur_fcr_stateArgs, 0, 0 },
11857 - { 1, Iclass_rur_fsr_args,
11858 - 8, Iclass_rur_fsr_stateArgs, 0, 0 },
11859 - { 1, Iclass_wur_fsr_args,
11860 - 8, Iclass_wur_fsr_stateArgs, 0, 0 },
11861 - { 3, Iclass_fp_args,
11862 - 2, Iclass_fp_stateArgs, 0, 0 },
11863 - { 3, Iclass_fp_mac_args,
11864 - 2, Iclass_fp_mac_stateArgs, 0, 0 },
11865 - { 3, Iclass_fp_cmov_args,
11866 - 1, Iclass_fp_cmov_stateArgs, 0, 0 },
11867 - { 3, Iclass_fp_mov_args,
11868 - 1, Iclass_fp_mov_stateArgs, 0, 0 },
11869 - { 2, Iclass_fp_mov2_args,
11870 - 1, Iclass_fp_mov2_stateArgs, 0, 0 },
11871 - { 3, Iclass_fp_cmp_args,
11872 - 1, Iclass_fp_cmp_stateArgs, 0, 0 },
11873 - { 3, Iclass_fp_float_args,
11874 - 2, Iclass_fp_float_stateArgs, 0, 0 },
11875 - { 3, Iclass_fp_int_args,
11876 - 1, Iclass_fp_int_stateArgs, 0, 0 },
11877 - { 2, Iclass_fp_rfr_args,
11878 - 1, Iclass_fp_rfr_stateArgs, 0, 0 },
11879 - { 2, Iclass_fp_wfr_args,
11880 - 1, Iclass_fp_wfr_stateArgs, 0, 0 },
11881 - { 3, Iclass_fp_lsi_args,
11882 - 1, Iclass_fp_lsi_stateArgs, 0, 0 },
11883 - { 3, Iclass_fp_lsiu_args,
11884 - 1, Iclass_fp_lsiu_stateArgs, 0, 0 },
11885 - { 3, Iclass_fp_lsx_args,
11886 - 1, Iclass_fp_lsx_stateArgs, 0, 0 },
11887 - { 3, Iclass_fp_lsxu_args,
11888 - 1, Iclass_fp_lsxu_stateArgs, 0, 0 },
11889 - { 3, Iclass_fp_ssi_args,
11890 - 1, Iclass_fp_ssi_stateArgs, 0, 0 },
11891 - { 3, Iclass_fp_ssiu_args,
11892 - 1, Iclass_fp_ssiu_stateArgs, 0, 0 },
11893 - { 3, Iclass_fp_ssx_args,
11894 - 1, Iclass_fp_ssx_stateArgs, 0, 0 },
11895 - { 3, Iclass_fp_ssxu_args,
11896 - 1, Iclass_fp_ssxu_stateArgs, 0, 0 },
11897 - { 2, Iclass_xt_iclass_wb18_0_args,
11899 - { 3, Iclass_xt_iclass_wb18_1_args,
11901 - { 3, Iclass_xt_iclass_wb18_2_args,
11903 - { 3, Iclass_xt_iclass_wb18_3_args,
11905 - { 3, Iclass_xt_iclass_wb18_4_args,
11910 -/* Opcode encodings. */
11913 -Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf)
11915 - slotbuf[0] = 0x2080;
11919 -Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf)
11921 - slotbuf[0] = 0x3000;
11925 -Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf)
11927 - slotbuf[0] = 0x3200;
11931 -Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf)
11933 - slotbuf[0] = 0x5000;
11937 -Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf)
11939 - slotbuf[0] = 0x5100;
11943 -Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf)
11945 - slotbuf[0] = 0x35;
11949 -Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf)
11951 - slotbuf[0] = 0x25;
11955 -Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf)
11957 - slotbuf[0] = 0x15;
11961 -Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf)
11963 - slotbuf[0] = 0xf0;
11967 -Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
11969 - slotbuf[0] = 0xe0;
11973 -Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
11975 - slotbuf[0] = 0xd0;
11979 -Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf)
11981 - slotbuf[0] = 0x36;
11985 -Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf)
11987 - slotbuf[0] = 0x1000;
11991 -Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf)
11993 - slotbuf[0] = 0x408000;
11997 -Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf)
11999 - slotbuf[0] = 0x90;
12003 -Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
12005 - slotbuf[0] = 0xf01d;
12009 -Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
12011 - slotbuf[0] = 0x3400;
12015 -Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf)
12017 - slotbuf[0] = 0x3500;
12021 -Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
12023 - slotbuf[0] = 0x90000;
12027 -Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
12029 - slotbuf[0] = 0x490000;
12033 -Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
12035 - slotbuf[0] = 0x34800;
12039 -Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
12041 - slotbuf[0] = 0x134800;
12045 -Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
12047 - slotbuf[0] = 0x614800;
12051 -Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
12053 - slotbuf[0] = 0x34900;
12057 -Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
12059 - slotbuf[0] = 0x134900;
12063 -Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
12065 - slotbuf[0] = 0x614900;
12069 -Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
12071 - slotbuf[0] = 0xa;
12075 -Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
12077 - slotbuf[0] = 0xb;
12081 -Opcode_addi_n_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
12083 - slotbuf[0] = 0x3000;
12087 -Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
12089 - slotbuf[0] = 0x8c;
12093 -Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
12095 - slotbuf[0] = 0xcc;
12099 -Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
12101 - slotbuf[0] = 0xf06d;
12105 -Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
12107 - slotbuf[0] = 0x8;
12111 -Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
12113 - slotbuf[0] = 0xd;
12117 -Opcode_mov_n_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12119 - slotbuf[0] = 0x6000;
12123 -Opcode_mov_n_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12125 - slotbuf[0] = 0xa3000;
12129 -Opcode_mov_n_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
12131 - slotbuf[0] = 0xc080;
12135 -Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
12137 - slotbuf[0] = 0xc;
12141 -Opcode_movi_n_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
12143 - slotbuf[0] = 0xc000;
12147 -Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
12149 - slotbuf[0] = 0xf03d;
12153 -Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
12155 - slotbuf[0] = 0xf00d;
12159 -Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
12161 - slotbuf[0] = 0x9;
12165 -Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
12167 - slotbuf[0] = 0xe30e70;
12171 -Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
12173 - slotbuf[0] = 0xf3e700;
12177 -Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf)
12179 - slotbuf[0] = 0xc002;
12183 -Opcode_addi_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12185 - slotbuf[0] = 0x60000;
12189 -Opcode_addi_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12191 - slotbuf[0] = 0x200c00;
12195 -Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf)
12197 - slotbuf[0] = 0xd002;
12201 -Opcode_addmi_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12203 - slotbuf[0] = 0x70000;
12207 -Opcode_addmi_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12209 - slotbuf[0] = 0x200d00;
12213 -Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf)
12215 - slotbuf[0] = 0x800000;
12219 -Opcode_add_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12221 - slotbuf[0] = 0x92000;
12225 -Opcode_add_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
12227 - slotbuf[0] = 0x2000;
12231 -Opcode_add_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12233 - slotbuf[0] = 0x80000;
12237 -Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf)
12239 - slotbuf[0] = 0xc00000;
12243 -Opcode_sub_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12245 - slotbuf[0] = 0xa8000;
12249 -Opcode_sub_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
12251 - slotbuf[0] = 0xa000;
12255 -Opcode_sub_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12257 - slotbuf[0] = 0xc0000;
12261 -Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
12263 - slotbuf[0] = 0x900000;
12267 -Opcode_addx2_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12269 - slotbuf[0] = 0x94000;
12273 -Opcode_addx2_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
12275 - slotbuf[0] = 0x4000;
12279 -Opcode_addx2_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12281 - slotbuf[0] = 0x90000;
12285 -Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
12287 - slotbuf[0] = 0xa00000;
12291 -Opcode_addx4_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12293 - slotbuf[0] = 0x98000;
12297 -Opcode_addx4_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
12299 - slotbuf[0] = 0x5000;
12303 -Opcode_addx4_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12305 - slotbuf[0] = 0xa0000;
12309 -Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
12311 - slotbuf[0] = 0xb00000;
12315 -Opcode_addx8_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12317 - slotbuf[0] = 0x93000;
12321 -Opcode_addx8_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12323 - slotbuf[0] = 0xb0000;
12327 -Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
12329 - slotbuf[0] = 0xd00000;
12333 -Opcode_subx2_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12335 - slotbuf[0] = 0xd0000;
12339 -Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
12341 - slotbuf[0] = 0xe00000;
12345 -Opcode_subx4_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12347 - slotbuf[0] = 0xe0000;
12351 -Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
12353 - slotbuf[0] = 0xf00000;
12357 -Opcode_subx8_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12359 - slotbuf[0] = 0xf0000;
12363 -Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf)
12365 - slotbuf[0] = 0x100000;
12369 -Opcode_and_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12371 - slotbuf[0] = 0x95000;
12375 -Opcode_and_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
12377 - slotbuf[0] = 0x6000;
12381 -Opcode_and_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12383 - slotbuf[0] = 0x10000;
12387 -Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf)
12389 - slotbuf[0] = 0x200000;
12393 -Opcode_or_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12395 - slotbuf[0] = 0x9e000;
12399 -Opcode_or_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
12401 - slotbuf[0] = 0x7000;
12405 -Opcode_or_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12407 - slotbuf[0] = 0x20000;
12411 -Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf)
12413 - slotbuf[0] = 0x300000;
12417 -Opcode_xor_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12419 - slotbuf[0] = 0xb0000;
12423 -Opcode_xor_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
12425 - slotbuf[0] = 0xb000;
12429 -Opcode_xor_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12431 - slotbuf[0] = 0x30000;
12435 -Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf)
12437 - slotbuf[0] = 0x26;
12441 -Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf)
12443 - slotbuf[0] = 0x66;
12447 -Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf)
12449 - slotbuf[0] = 0xe6;
12453 -Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf)
12455 - slotbuf[0] = 0xa6;
12459 -Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf)
12461 - slotbuf[0] = 0x6007;
12465 -Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
12467 - slotbuf[0] = 0xe007;
12471 -Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf)
12473 - slotbuf[0] = 0xf6;
12477 -Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf)
12479 - slotbuf[0] = 0xb6;
12483 -Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf)
12485 - slotbuf[0] = 0x1007;
12489 -Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf)
12491 - slotbuf[0] = 0x9007;
12495 -Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf)
12497 - slotbuf[0] = 0xa007;
12501 -Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf)
12503 - slotbuf[0] = 0x2007;
12507 -Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf)
12509 - slotbuf[0] = 0xb007;
12513 -Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
12515 - slotbuf[0] = 0x3007;
12519 -Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf)
12521 - slotbuf[0] = 0x8007;
12525 -Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf)
12527 - slotbuf[0] = 0x7;
12531 -Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf)
12533 - slotbuf[0] = 0x4007;
12537 -Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf)
12539 - slotbuf[0] = 0xc007;
12543 -Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
12545 - slotbuf[0] = 0x5007;
12549 -Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf)
12551 - slotbuf[0] = 0xd007;
12555 -Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
12557 - slotbuf[0] = 0x16;
12561 -Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
12563 - slotbuf[0] = 0x56;
12567 -Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
12569 - slotbuf[0] = 0xd6;
12573 -Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
12575 - slotbuf[0] = 0x96;
12579 -Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf)
12581 - slotbuf[0] = 0x5;
12585 -Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf)
12587 - slotbuf[0] = 0xc0;
12591 -Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf)
12593 - slotbuf[0] = 0x40000;
12597 -Opcode_extui_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12599 - slotbuf[0] = 0x40000;
12603 -Opcode_extui_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12605 - slotbuf[0] = 0x4000;
12609 -Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf)
12615 -Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf)
12617 - slotbuf[0] = 0x6;
12621 -Opcode_j_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12623 - slotbuf[0] = 0xc0000;
12627 -Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf)
12629 - slotbuf[0] = 0xa0;
12633 -Opcode_jx_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12635 - slotbuf[0] = 0xa3010;
12639 -Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
12641 - slotbuf[0] = 0x1002;
12645 -Opcode_l16ui_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12647 - slotbuf[0] = 0x200100;
12651 -Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf)
12653 - slotbuf[0] = 0x9002;
12657 -Opcode_l16si_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12659 - slotbuf[0] = 0x200900;
12663 -Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
12665 - slotbuf[0] = 0x2002;
12669 -Opcode_l32i_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12671 - slotbuf[0] = 0x200200;
12675 -Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf)
12677 - slotbuf[0] = 0x1;
12681 -Opcode_l32r_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12683 - slotbuf[0] = 0x100000;
12687 -Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
12689 - slotbuf[0] = 0x2;
12693 -Opcode_l8ui_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12695 - slotbuf[0] = 0x200000;
12699 -Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf)
12701 - slotbuf[0] = 0x8076;
12705 -Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
12707 - slotbuf[0] = 0x9076;
12711 -Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf)
12713 - slotbuf[0] = 0xa076;
12717 -Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf)
12719 - slotbuf[0] = 0xa002;
12723 -Opcode_movi_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12725 - slotbuf[0] = 0x80000;
12729 -Opcode_movi_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12731 - slotbuf[0] = 0x200a00;
12735 -Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
12737 - slotbuf[0] = 0x830000;
12741 -Opcode_moveqz_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12743 - slotbuf[0] = 0x96000;
12747 -Opcode_moveqz_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12749 - slotbuf[0] = 0x83000;
12753 -Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
12755 - slotbuf[0] = 0x930000;
12759 -Opcode_movnez_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12761 - slotbuf[0] = 0x9a000;
12765 -Opcode_movnez_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12767 - slotbuf[0] = 0x93000;
12771 -Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
12773 - slotbuf[0] = 0xa30000;
12777 -Opcode_movltz_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12779 - slotbuf[0] = 0x99000;
12783 -Opcode_movltz_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12785 - slotbuf[0] = 0xa3000;
12789 -Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
12791 - slotbuf[0] = 0xb30000;
12795 -Opcode_movgez_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12797 - slotbuf[0] = 0x97000;
12801 -Opcode_movgez_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12803 - slotbuf[0] = 0xb3000;
12807 -Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf)
12809 - slotbuf[0] = 0x600000;
12813 -Opcode_neg_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12815 - slotbuf[0] = 0xa5000;
12819 -Opcode_neg_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
12821 - slotbuf[0] = 0xd100;
12825 -Opcode_neg_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12827 - slotbuf[0] = 0x60000;
12831 -Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf)
12833 - slotbuf[0] = 0x600100;
12837 -Opcode_abs_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
12839 - slotbuf[0] = 0xd000;
12843 -Opcode_abs_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12845 - slotbuf[0] = 0x60010;
12849 -Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf)
12851 - slotbuf[0] = 0x20f0;
12855 -Opcode_nop_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12857 - slotbuf[0] = 0xa3040;
12861 -Opcode_nop_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
12863 - slotbuf[0] = 0xc090;
12867 -Opcode_nop_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
12869 - slotbuf[0] = 0xc8000000;
12874 -Opcode_nop_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12876 - slotbuf[0] = 0x20f;
12880 -Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf)
12882 - slotbuf[0] = 0x80;
12886 -Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf)
12888 - slotbuf[0] = 0x5002;
12892 -Opcode_s16i_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12894 - slotbuf[0] = 0x200500;
12898 -Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
12900 - slotbuf[0] = 0x6002;
12904 -Opcode_s32i_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12906 - slotbuf[0] = 0x200600;
12910 -Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf)
12912 - slotbuf[0] = 0x4002;
12916 -Opcode_s8i_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12918 - slotbuf[0] = 0x200400;
12922 -Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf)
12924 - slotbuf[0] = 0x400000;
12928 -Opcode_ssr_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12930 - slotbuf[0] = 0x40000;
12934 -Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf)
12936 - slotbuf[0] = 0x401000;
12940 -Opcode_ssl_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12942 - slotbuf[0] = 0xa3020;
12946 -Opcode_ssl_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12948 - slotbuf[0] = 0x40100;
12952 -Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf)
12954 - slotbuf[0] = 0x402000;
12958 -Opcode_ssa8l_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12960 - slotbuf[0] = 0x40200;
12964 -Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf)
12966 - slotbuf[0] = 0x403000;
12970 -Opcode_ssa8b_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12972 - slotbuf[0] = 0x40300;
12976 -Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf)
12978 - slotbuf[0] = 0x404000;
12982 -Opcode_ssai_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
12984 - slotbuf[0] = 0x40400;
12988 -Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf)
12990 - slotbuf[0] = 0xa10000;
12994 -Opcode_sll_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
12996 - slotbuf[0] = 0xa6000;
13000 -Opcode_sll_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
13002 - slotbuf[0] = 0xa1000;
13006 -Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf)
13008 - slotbuf[0] = 0x810000;
13012 -Opcode_src_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
13014 - slotbuf[0] = 0xa2000;
13018 -Opcode_src_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
13020 - slotbuf[0] = 0x81000;
13024 -Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf)
13026 - slotbuf[0] = 0x910000;
13030 -Opcode_srl_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
13032 - slotbuf[0] = 0xa5200;
13036 -Opcode_srl_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
13038 - slotbuf[0] = 0xd400;
13042 -Opcode_srl_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
13044 - slotbuf[0] = 0x91000;
13048 -Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf)
13050 - slotbuf[0] = 0xb10000;
13054 -Opcode_sra_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
13056 - slotbuf[0] = 0xa5100;
13060 -Opcode_sra_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
13062 - slotbuf[0] = 0xd200;
13066 -Opcode_sra_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
13068 - slotbuf[0] = 0xb1000;
13072 -Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf)
13074 - slotbuf[0] = 0x10000;
13078 -Opcode_slli_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
13080 - slotbuf[0] = 0x90000;
13084 -Opcode_slli_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
13086 - slotbuf[0] = 0x1000;
13090 -Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf)
13092 - slotbuf[0] = 0x210000;
13096 -Opcode_srai_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
13098 - slotbuf[0] = 0xa0000;
13102 -Opcode_srai_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
13104 - slotbuf[0] = 0xe000;
13108 -Opcode_srai_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
13110 - slotbuf[0] = 0x21000;
13114 -Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf)
13116 - slotbuf[0] = 0x410000;
13120 -Opcode_srli_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
13122 - slotbuf[0] = 0xa4000;
13126 -Opcode_srli_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
13128 - slotbuf[0] = 0x9000;
13132 -Opcode_srli_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
13134 - slotbuf[0] = 0x41000;
13138 -Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf)
13140 - slotbuf[0] = 0x20c0;
13144 -Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf)
13146 - slotbuf[0] = 0x20d0;
13150 -Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf)
13152 - slotbuf[0] = 0x2000;
13156 -Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
13158 - slotbuf[0] = 0x2010;
13162 -Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf)
13164 - slotbuf[0] = 0x2020;
13168 -Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
13170 - slotbuf[0] = 0x2030;
13174 -Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf)
13176 - slotbuf[0] = 0x6000;
13180 -Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
13182 - slotbuf[0] = 0x30100;
13186 -Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
13188 - slotbuf[0] = 0x130100;
13192 -Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
13194 - slotbuf[0] = 0x610100;
13198 -Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
13200 - slotbuf[0] = 0x30200;
13204 -Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
13206 - slotbuf[0] = 0x130200;
13210 -Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
13212 - slotbuf[0] = 0x610200;
13216 -Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
13218 - slotbuf[0] = 0x30000;
13222 -Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
13224 - slotbuf[0] = 0x130000;
13228 -Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
13230 - slotbuf[0] = 0x610000;
13234 -Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
13236 - slotbuf[0] = 0x30300;
13240 -Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
13242 - slotbuf[0] = 0x130300;
13246 -Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
13248 - slotbuf[0] = 0x610300;
13252 -Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
13254 - slotbuf[0] = 0x30500;
13258 -Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
13260 - slotbuf[0] = 0x130500;
13264 -Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
13266 - slotbuf[0] = 0x610500;
13270 -Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf)
13272 - slotbuf[0] = 0x3b000;
13276 -Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf)
13278 - slotbuf[0] = 0x3d000;
13282 -Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
13284 - slotbuf[0] = 0x3e600;
13288 -Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
13290 - slotbuf[0] = 0x13e600;
13294 -Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
13296 - slotbuf[0] = 0x61e600;
13300 -Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
13302 - slotbuf[0] = 0x3b100;
13306 -Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
13308 - slotbuf[0] = 0x13b100;
13312 -Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
13314 - slotbuf[0] = 0x61b100;
13318 -Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
13320 - slotbuf[0] = 0x3d100;
13324 -Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
13326 - slotbuf[0] = 0x13d100;
13330 -Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
13332 - slotbuf[0] = 0x61d100;
13336 -Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
13338 - slotbuf[0] = 0x3b200;
13342 -Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
13344 - slotbuf[0] = 0x13b200;
13348 -Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
13350 - slotbuf[0] = 0x61b200;
13354 -Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
13356 - slotbuf[0] = 0x3d200;
13360 -Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
13362 - slotbuf[0] = 0x13d200;
13366 -Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
13368 - slotbuf[0] = 0x61d200;
13372 -Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
13374 - slotbuf[0] = 0x3b300;
13378 -Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
13380 - slotbuf[0] = 0x13b300;
13384 -Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
13386 - slotbuf[0] = 0x61b300;
13390 -Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
13392 - slotbuf[0] = 0x3d300;
13396 -Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
13398 - slotbuf[0] = 0x13d300;
13402 -Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
13404 - slotbuf[0] = 0x61d300;
13408 -Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
13410 - slotbuf[0] = 0x3b400;
13414 -Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
13416 - slotbuf[0] = 0x13b400;
13420 -Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
13422 - slotbuf[0] = 0x61b400;
13426 -Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
13428 - slotbuf[0] = 0x3d400;
13432 -Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
13434 - slotbuf[0] = 0x13d400;
13438 -Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
13440 - slotbuf[0] = 0x61d400;
13444 -Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
13446 - slotbuf[0] = 0x3b500;
13450 -Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
13452 - slotbuf[0] = 0x13b500;
13456 -Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
13458 - slotbuf[0] = 0x61b500;
13462 -Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
13464 - slotbuf[0] = 0x3d500;
13468 -Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
13470 - slotbuf[0] = 0x13d500;
13474 -Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
13476 - slotbuf[0] = 0x61d500;
13480 -Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
13482 - slotbuf[0] = 0x3b600;
13486 -Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
13488 - slotbuf[0] = 0x13b600;
13492 -Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
13494 - slotbuf[0] = 0x61b600;
13498 -Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
13500 - slotbuf[0] = 0x3d600;
13504 -Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
13506 - slotbuf[0] = 0x13d600;
13510 -Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
13512 - slotbuf[0] = 0x61d600;
13516 -Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
13518 - slotbuf[0] = 0x3b700;
13522 -Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
13524 - slotbuf[0] = 0x13b700;
13528 -Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
13530 - slotbuf[0] = 0x61b700;
13534 -Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
13536 - slotbuf[0] = 0x3d700;
13540 -Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
13542 - slotbuf[0] = 0x13d700;
13546 -Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
13548 - slotbuf[0] = 0x61d700;
13552 -Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
13554 - slotbuf[0] = 0x3c200;
13558 -Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
13560 - slotbuf[0] = 0x13c200;
13564 -Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
13566 - slotbuf[0] = 0x61c200;
13570 -Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
13572 - slotbuf[0] = 0x3c300;
13576 -Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
13578 - slotbuf[0] = 0x13c300;
13582 -Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
13584 - slotbuf[0] = 0x61c300;
13588 -Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
13590 - slotbuf[0] = 0x3c400;
13594 -Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
13596 - slotbuf[0] = 0x13c400;
13600 -Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
13602 - slotbuf[0] = 0x61c400;
13606 -Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
13608 - slotbuf[0] = 0x3c500;
13612 -Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
13614 - slotbuf[0] = 0x13c500;
13618 -Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
13620 - slotbuf[0] = 0x61c500;
13624 -Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
13626 - slotbuf[0] = 0x3c600;
13630 -Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
13632 - slotbuf[0] = 0x13c600;
13636 -Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
13638 - slotbuf[0] = 0x61c600;
13642 -Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
13644 - slotbuf[0] = 0x3c700;
13648 -Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
13650 - slotbuf[0] = 0x13c700;
13654 -Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
13656 - slotbuf[0] = 0x61c700;
13660 -Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
13662 - slotbuf[0] = 0x3ee00;
13666 -Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
13668 - slotbuf[0] = 0x13ee00;
13672 -Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
13674 - slotbuf[0] = 0x61ee00;
13678 -Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
13680 - slotbuf[0] = 0x3c000;
13684 -Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
13686 - slotbuf[0] = 0x13c000;
13690 -Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
13692 - slotbuf[0] = 0x61c000;
13696 -Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
13698 - slotbuf[0] = 0x3e800;
13702 -Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
13704 - slotbuf[0] = 0x13e800;
13708 -Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
13710 - slotbuf[0] = 0x61e800;
13714 -Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
13716 - slotbuf[0] = 0x3f400;
13720 -Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
13722 - slotbuf[0] = 0x13f400;
13726 -Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
13728 - slotbuf[0] = 0x61f400;
13732 -Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
13734 - slotbuf[0] = 0x3f500;
13738 -Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
13740 - slotbuf[0] = 0x13f500;
13744 -Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
13746 - slotbuf[0] = 0x61f500;
13750 -Opcode_rsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
13752 - slotbuf[0] = 0x3f600;
13756 -Opcode_wsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
13758 - slotbuf[0] = 0x13f600;
13762 -Opcode_xsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
13764 - slotbuf[0] = 0x61f600;
13768 -Opcode_rsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
13770 - slotbuf[0] = 0x3f700;
13774 -Opcode_wsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
13776 - slotbuf[0] = 0x13f700;
13780 -Opcode_xsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
13782 - slotbuf[0] = 0x61f700;
13786 -Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf)
13788 - slotbuf[0] = 0x3eb00;
13792 -Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
13794 - slotbuf[0] = 0x3e700;
13798 -Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
13800 - slotbuf[0] = 0x13e700;
13804 -Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
13806 - slotbuf[0] = 0x61e700;
13810 -Opcode_mul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
13812 - slotbuf[0] = 0x740004;
13816 -Opcode_mul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
13818 - slotbuf[0] = 0x750004;
13822 -Opcode_mul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
13824 - slotbuf[0] = 0x760004;
13828 -Opcode_mul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
13830 - slotbuf[0] = 0x770004;
13834 -Opcode_umul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
13836 - slotbuf[0] = 0x700004;
13840 -Opcode_umul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
13842 - slotbuf[0] = 0x710004;
13846 -Opcode_umul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
13848 - slotbuf[0] = 0x720004;
13852 -Opcode_umul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
13854 - slotbuf[0] = 0x730004;
13858 -Opcode_mul_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
13860 - slotbuf[0] = 0x340004;
13864 -Opcode_mul_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
13866 - slotbuf[0] = 0x350004;
13870 -Opcode_mul_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
13872 - slotbuf[0] = 0x360004;
13876 -Opcode_mul_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
13878 - slotbuf[0] = 0x370004;
13882 -Opcode_mul_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
13884 - slotbuf[0] = 0x640004;
13888 -Opcode_mul_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
13890 - slotbuf[0] = 0x650004;
13894 -Opcode_mul_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
13896 - slotbuf[0] = 0x660004;
13900 -Opcode_mul_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
13902 - slotbuf[0] = 0x670004;
13906 -Opcode_mul_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
13908 - slotbuf[0] = 0x240004;
13912 -Opcode_mul_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
13914 - slotbuf[0] = 0x250004;
13918 -Opcode_mul_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
13920 - slotbuf[0] = 0x260004;
13924 -Opcode_mul_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
13926 - slotbuf[0] = 0x270004;
13930 -Opcode_mula_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
13932 - slotbuf[0] = 0x780004;
13936 -Opcode_mula_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
13938 - slotbuf[0] = 0x790004;
13942 -Opcode_mula_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
13944 - slotbuf[0] = 0x7a0004;
13948 -Opcode_mula_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
13950 - slotbuf[0] = 0x7b0004;
13954 -Opcode_muls_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
13956 - slotbuf[0] = 0x7c0004;
13960 -Opcode_muls_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
13962 - slotbuf[0] = 0x7d0004;
13966 -Opcode_muls_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
13968 - slotbuf[0] = 0x7e0004;
13972 -Opcode_muls_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
13974 - slotbuf[0] = 0x7f0004;
13978 -Opcode_mula_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
13980 - slotbuf[0] = 0x380004;
13984 -Opcode_mula_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
13986 - slotbuf[0] = 0x390004;
13990 -Opcode_mula_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
13992 - slotbuf[0] = 0x3a0004;
13996 -Opcode_mula_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
13998 - slotbuf[0] = 0x3b0004;
14002 -Opcode_muls_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
14004 - slotbuf[0] = 0x3c0004;
14008 -Opcode_muls_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
14010 - slotbuf[0] = 0x3d0004;
14014 -Opcode_muls_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
14016 - slotbuf[0] = 0x3e0004;
14020 -Opcode_muls_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
14022 - slotbuf[0] = 0x3f0004;
14026 -Opcode_mula_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
14028 - slotbuf[0] = 0x680004;
14032 -Opcode_mula_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
14034 - slotbuf[0] = 0x690004;
14038 -Opcode_mula_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
14040 - slotbuf[0] = 0x6a0004;
14044 -Opcode_mula_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
14046 - slotbuf[0] = 0x6b0004;
14050 -Opcode_muls_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
14052 - slotbuf[0] = 0x6c0004;
14056 -Opcode_muls_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
14058 - slotbuf[0] = 0x6d0004;
14062 -Opcode_muls_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
14064 - slotbuf[0] = 0x6e0004;
14068 -Opcode_muls_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
14070 - slotbuf[0] = 0x6f0004;
14074 -Opcode_mula_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
14076 - slotbuf[0] = 0x280004;
14080 -Opcode_mula_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
14082 - slotbuf[0] = 0x290004;
14086 -Opcode_mula_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
14088 - slotbuf[0] = 0x2a0004;
14092 -Opcode_mula_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
14094 - slotbuf[0] = 0x2b0004;
14098 -Opcode_muls_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
14100 - slotbuf[0] = 0x2c0004;
14104 -Opcode_muls_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
14106 - slotbuf[0] = 0x2d0004;
14110 -Opcode_muls_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
14112 - slotbuf[0] = 0x2e0004;
14116 -Opcode_muls_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
14118 - slotbuf[0] = 0x2f0004;
14122 -Opcode_mula_da_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
14124 - slotbuf[0] = 0x580004;
14128 -Opcode_mula_da_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
14130 - slotbuf[0] = 0x480004;
14134 -Opcode_mula_da_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
14136 - slotbuf[0] = 0x590004;
14140 -Opcode_mula_da_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
14142 - slotbuf[0] = 0x490004;
14146 -Opcode_mula_da_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
14148 - slotbuf[0] = 0x5a0004;
14152 -Opcode_mula_da_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
14154 - slotbuf[0] = 0x4a0004;
14158 -Opcode_mula_da_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
14160 - slotbuf[0] = 0x5b0004;
14164 -Opcode_mula_da_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
14166 - slotbuf[0] = 0x4b0004;
14170 -Opcode_mula_dd_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
14172 - slotbuf[0] = 0x180004;
14176 -Opcode_mula_dd_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
14178 - slotbuf[0] = 0x80004;
14182 -Opcode_mula_dd_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
14184 - slotbuf[0] = 0x190004;
14188 -Opcode_mula_dd_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
14190 - slotbuf[0] = 0x90004;
14194 -Opcode_mula_dd_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
14196 - slotbuf[0] = 0x1a0004;
14200 -Opcode_mula_dd_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
14202 - slotbuf[0] = 0xa0004;
14206 -Opcode_mula_dd_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
14208 - slotbuf[0] = 0x1b0004;
14212 -Opcode_mula_dd_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
14214 - slotbuf[0] = 0xb0004;
14218 -Opcode_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
14220 - slotbuf[0] = 0x900004;
14224 -Opcode_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
14226 - slotbuf[0] = 0x800004;
14230 -Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf)
14232 - slotbuf[0] = 0xc10000;
14236 -Opcode_mul16u_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
14238 - slotbuf[0] = 0x9b000;
14242 -Opcode_mul16u_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
14244 - slotbuf[0] = 0xc1000;
14248 -Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf)
14250 - slotbuf[0] = 0xd10000;
14254 -Opcode_mul16s_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
14256 - slotbuf[0] = 0x9c000;
14260 -Opcode_mul16s_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
14262 - slotbuf[0] = 0xd1000;
14266 -Opcode_rsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
14268 - slotbuf[0] = 0x32000;
14272 -Opcode_wsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
14274 - slotbuf[0] = 0x132000;
14278 -Opcode_xsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
14280 - slotbuf[0] = 0x612000;
14284 -Opcode_rsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
14286 - slotbuf[0] = 0x32100;
14290 -Opcode_wsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
14292 - slotbuf[0] = 0x132100;
14296 -Opcode_xsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
14298 - slotbuf[0] = 0x612100;
14302 -Opcode_rsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
14304 - slotbuf[0] = 0x32200;
14308 -Opcode_wsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
14310 - slotbuf[0] = 0x132200;
14314 -Opcode_xsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
14316 - slotbuf[0] = 0x612200;
14320 -Opcode_rsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
14322 - slotbuf[0] = 0x32300;
14326 -Opcode_wsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
14328 - slotbuf[0] = 0x132300;
14332 -Opcode_xsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
14334 - slotbuf[0] = 0x612300;
14338 -Opcode_rsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
14340 - slotbuf[0] = 0x31000;
14344 -Opcode_wsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
14346 - slotbuf[0] = 0x131000;
14350 -Opcode_xsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
14352 - slotbuf[0] = 0x611000;
14356 -Opcode_rsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
14358 - slotbuf[0] = 0x31100;
14362 -Opcode_wsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
14364 - slotbuf[0] = 0x131100;
14368 -Opcode_xsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
14370 - slotbuf[0] = 0x611100;
14374 -Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf)
14376 - slotbuf[0] = 0x3010;
14380 -Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf)
14382 - slotbuf[0] = 0x7000;
14386 -Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf)
14388 - slotbuf[0] = 0x3e200;
14392 -Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf)
14394 - slotbuf[0] = 0x13e200;
14398 -Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf)
14400 - slotbuf[0] = 0x13e300;
14404 -Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
14406 - slotbuf[0] = 0x3e400;
14410 -Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
14412 - slotbuf[0] = 0x13e400;
14416 -Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
14418 - slotbuf[0] = 0x61e400;
14422 -Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf)
14424 - slotbuf[0] = 0x4000;
14428 -Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
14430 - slotbuf[0] = 0xf02d;
14434 -Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
14436 - slotbuf[0] = 0x39000;
14440 -Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
14442 - slotbuf[0] = 0x139000;
14446 -Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
14448 - slotbuf[0] = 0x619000;
14452 -Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
14454 - slotbuf[0] = 0x3a000;
14458 -Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
14460 - slotbuf[0] = 0x13a000;
14464 -Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
14466 - slotbuf[0] = 0x61a000;
14470 -Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
14472 - slotbuf[0] = 0x39100;
14476 -Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
14478 - slotbuf[0] = 0x139100;
14482 -Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
14484 - slotbuf[0] = 0x619100;
14488 -Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
14490 - slotbuf[0] = 0x3a100;
14494 -Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
14496 - slotbuf[0] = 0x13a100;
14500 -Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
14502 - slotbuf[0] = 0x61a100;
14506 -Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
14508 - slotbuf[0] = 0x38000;
14512 -Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
14514 - slotbuf[0] = 0x138000;
14518 -Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
14520 - slotbuf[0] = 0x618000;
14524 -Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
14526 - slotbuf[0] = 0x38100;
14530 -Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
14532 - slotbuf[0] = 0x138100;
14536 -Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
14538 - slotbuf[0] = 0x618100;
14542 -Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
14544 - slotbuf[0] = 0x36000;
14548 -Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
14550 - slotbuf[0] = 0x136000;
14554 -Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
14556 - slotbuf[0] = 0x616000;
14560 -Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
14562 - slotbuf[0] = 0x3e900;
14566 -Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
14568 - slotbuf[0] = 0x13e900;
14572 -Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
14574 - slotbuf[0] = 0x61e900;
14578 -Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
14580 - slotbuf[0] = 0x3ec00;
14584 -Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
14586 - slotbuf[0] = 0x13ec00;
14590 -Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
14592 - slotbuf[0] = 0x61ec00;
14596 -Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
14598 - slotbuf[0] = 0x3ed00;
14602 -Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
14604 - slotbuf[0] = 0x13ed00;
14608 -Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
14610 - slotbuf[0] = 0x61ed00;
14614 -Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
14616 - slotbuf[0] = 0x36800;
14620 -Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
14622 - slotbuf[0] = 0x136800;
14626 -Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
14628 - slotbuf[0] = 0x616800;
14632 -Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf)
14634 - slotbuf[0] = 0xf1e000;
14638 -Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf)
14640 - slotbuf[0] = 0xf1e010;
14644 -Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf)
14646 - slotbuf[0] = 0x135900;
14650 -Opcode_andb_Slot_inst_encode (xtensa_insnbuf slotbuf)
14652 - slotbuf[0] = 0x20000;
14656 -Opcode_andbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
14658 - slotbuf[0] = 0x120000;
14662 -Opcode_orb_Slot_inst_encode (xtensa_insnbuf slotbuf)
14664 - slotbuf[0] = 0x220000;
14668 -Opcode_orbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
14670 - slotbuf[0] = 0x320000;
14674 -Opcode_xorb_Slot_inst_encode (xtensa_insnbuf slotbuf)
14676 - slotbuf[0] = 0x420000;
14680 -Opcode_any4_Slot_inst_encode (xtensa_insnbuf slotbuf)
14682 - slotbuf[0] = 0x8000;
14686 -Opcode_all4_Slot_inst_encode (xtensa_insnbuf slotbuf)
14688 - slotbuf[0] = 0x9000;
14692 -Opcode_any8_Slot_inst_encode (xtensa_insnbuf slotbuf)
14694 - slotbuf[0] = 0xa000;
14698 -Opcode_all8_Slot_inst_encode (xtensa_insnbuf slotbuf)
14700 - slotbuf[0] = 0xb000;
14704 -Opcode_bf_Slot_inst_encode (xtensa_insnbuf slotbuf)
14706 - slotbuf[0] = 0x76;
14710 -Opcode_bt_Slot_inst_encode (xtensa_insnbuf slotbuf)
14712 - slotbuf[0] = 0x1076;
14716 -Opcode_movf_Slot_inst_encode (xtensa_insnbuf slotbuf)
14718 - slotbuf[0] = 0xc30000;
14722 -Opcode_movt_Slot_inst_encode (xtensa_insnbuf slotbuf)
14724 - slotbuf[0] = 0xd30000;
14728 -Opcode_rsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
14730 - slotbuf[0] = 0x30400;
14734 -Opcode_wsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
14736 - slotbuf[0] = 0x130400;
14740 -Opcode_xsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
14742 - slotbuf[0] = 0x610400;
14746 -Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
14748 - slotbuf[0] = 0x3ea00;
14752 -Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
14754 - slotbuf[0] = 0x13ea00;
14758 -Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
14760 - slotbuf[0] = 0x61ea00;
14764 -Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
14766 - slotbuf[0] = 0x3f000;
14770 -Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
14772 - slotbuf[0] = 0x13f000;
14776 -Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
14778 - slotbuf[0] = 0x61f000;
14782 -Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
14784 - slotbuf[0] = 0x3f100;
14788 -Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
14790 - slotbuf[0] = 0x13f100;
14794 -Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
14796 - slotbuf[0] = 0x61f100;
14800 -Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
14802 - slotbuf[0] = 0x3f200;
14806 -Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
14808 - slotbuf[0] = 0x13f200;
14812 -Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
14814 - slotbuf[0] = 0x61f200;
14818 -Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf)
14820 - slotbuf[0] = 0x70c2;
14824 -Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf)
14826 - slotbuf[0] = 0x70e2;
14830 -Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf)
14832 - slotbuf[0] = 0x70d2;
14836 -Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf)
14838 - slotbuf[0] = 0x270d2;
14842 -Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf)
14844 - slotbuf[0] = 0x370d2;
14848 -Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf)
14850 - slotbuf[0] = 0x70f2;
14854 -Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf)
14856 - slotbuf[0] = 0xf10000;
14860 -Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf)
14862 - slotbuf[0] = 0xf12000;
14866 -Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf)
14868 - slotbuf[0] = 0xf11000;
14872 -Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf)
14874 - slotbuf[0] = 0xf13000;
14878 -Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
14880 - slotbuf[0] = 0x7042;
14884 -Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
14886 - slotbuf[0] = 0x7052;
14890 -Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
14892 - slotbuf[0] = 0x47082;
14896 -Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
14898 - slotbuf[0] = 0x57082;
14902 -Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf)
14904 - slotbuf[0] = 0x7062;
14908 -Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf)
14910 - slotbuf[0] = 0x7072;
14914 -Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
14916 - slotbuf[0] = 0x7002;
14920 -Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf)
14922 - slotbuf[0] = 0x7012;
14926 -Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf)
14928 - slotbuf[0] = 0x7022;
14932 -Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
14934 - slotbuf[0] = 0x7032;
14938 -Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf)
14940 - slotbuf[0] = 0x7082;
14944 -Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf)
14946 - slotbuf[0] = 0x27082;
14950 -Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf)
14952 - slotbuf[0] = 0x37082;
14956 -Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf)
14958 - slotbuf[0] = 0xf19000;
14962 -Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf)
14964 - slotbuf[0] = 0xf18000;
14968 -Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
14970 - slotbuf[0] = 0x135300;
14974 -Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
14976 - slotbuf[0] = 0x35300;
14980 -Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
14982 - slotbuf[0] = 0x615300;
14986 -Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
14988 - slotbuf[0] = 0x35a00;
14992 -Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
14994 - slotbuf[0] = 0x135a00;
14998 -Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
15000 - slotbuf[0] = 0x615a00;
15004 -Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
15006 - slotbuf[0] = 0x35b00;
15010 -Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
15012 - slotbuf[0] = 0x135b00;
15016 -Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
15018 - slotbuf[0] = 0x615b00;
15022 -Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
15024 - slotbuf[0] = 0x35c00;
15028 -Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
15030 - slotbuf[0] = 0x135c00;
15034 -Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
15036 - slotbuf[0] = 0x615c00;
15040 -Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
15042 - slotbuf[0] = 0x50c000;
15046 -Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
15048 - slotbuf[0] = 0x50d000;
15052 -Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
15054 - slotbuf[0] = 0x50b000;
15058 -Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
15060 - slotbuf[0] = 0x50f000;
15064 -Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
15066 - slotbuf[0] = 0x50e000;
15070 -Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
15072 - slotbuf[0] = 0x504000;
15076 -Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
15078 - slotbuf[0] = 0x505000;
15082 -Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
15084 - slotbuf[0] = 0x503000;
15088 -Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
15090 - slotbuf[0] = 0x507000;
15094 -Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
15096 - slotbuf[0] = 0x506000;
15100 -Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf)
15102 - slotbuf[0] = 0xf1f000;
15106 -Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
15108 - slotbuf[0] = 0x501000;
15112 -Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
15114 - slotbuf[0] = 0x509000;
15118 -Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
15120 - slotbuf[0] = 0x3e000;
15124 -Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
15126 - slotbuf[0] = 0x13e000;
15130 -Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
15132 - slotbuf[0] = 0x61e000;
15136 -Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf)
15138 - slotbuf[0] = 0x330000;
15142 -Opcode_clamps_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
15144 - slotbuf[0] = 0x33000;
15148 -Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf)
15150 - slotbuf[0] = 0x430000;
15154 -Opcode_min_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
15156 - slotbuf[0] = 0x43000;
15160 -Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf)
15162 - slotbuf[0] = 0x530000;
15166 -Opcode_max_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
15168 - slotbuf[0] = 0x53000;
15172 -Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf)
15174 - slotbuf[0] = 0x630000;
15178 -Opcode_minu_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
15180 - slotbuf[0] = 0x63000;
15184 -Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
15186 - slotbuf[0] = 0x730000;
15190 -Opcode_maxu_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
15192 - slotbuf[0] = 0x73000;
15196 -Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf)
15198 - slotbuf[0] = 0x40e000;
15202 -Opcode_nsa_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
15204 - slotbuf[0] = 0x40e00;
15208 -Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf)
15210 - slotbuf[0] = 0x40f000;
15214 -Opcode_nsau_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
15216 - slotbuf[0] = 0x40f00;
15220 -Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf)
15222 - slotbuf[0] = 0x230000;
15226 -Opcode_sext_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
15228 - slotbuf[0] = 0x9f000;
15232 -Opcode_sext_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
15234 - slotbuf[0] = 0x8000;
15238 -Opcode_sext_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
15240 - slotbuf[0] = 0x23000;
15244 -Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf)
15246 - slotbuf[0] = 0xb002;
15250 -Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf)
15252 - slotbuf[0] = 0xf002;
15256 -Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf)
15258 - slotbuf[0] = 0xe002;
15262 -Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
15264 - slotbuf[0] = 0x30c00;
15268 -Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
15270 - slotbuf[0] = 0x130c00;
15274 -Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
15276 - slotbuf[0] = 0x610c00;
15280 -Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf)
15282 - slotbuf[0] = 0xc20000;
15286 -Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf)
15288 - slotbuf[0] = 0xd20000;
15292 -Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf)
15294 - slotbuf[0] = 0xe20000;
15298 -Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf)
15300 - slotbuf[0] = 0xf20000;
15304 -Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf)
15306 - slotbuf[0] = 0x820000;
15310 -Opcode_mull_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
15312 - slotbuf[0] = 0x9d000;
15316 -Opcode_mull_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
15318 - slotbuf[0] = 0x82000;
15322 -Opcode_muluh_Slot_inst_encode (xtensa_insnbuf slotbuf)
15324 - slotbuf[0] = 0xa20000;
15328 -Opcode_mulsh_Slot_inst_encode (xtensa_insnbuf slotbuf)
15330 - slotbuf[0] = 0xb20000;
15334 -Opcode_rur_fcr_Slot_inst_encode (xtensa_insnbuf slotbuf)
15336 - slotbuf[0] = 0xe30e80;
15340 -Opcode_wur_fcr_Slot_inst_encode (xtensa_insnbuf slotbuf)
15342 - slotbuf[0] = 0xf3e800;
15346 -Opcode_rur_fsr_Slot_inst_encode (xtensa_insnbuf slotbuf)
15348 - slotbuf[0] = 0xe30e90;
15352 -Opcode_wur_fsr_Slot_inst_encode (xtensa_insnbuf slotbuf)
15354 - slotbuf[0] = 0xf3e900;
15358 -Opcode_add_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15360 - slotbuf[0] = 0xa0000;
15364 -Opcode_sub_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15366 - slotbuf[0] = 0x1a0000;
15370 -Opcode_mul_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15372 - slotbuf[0] = 0x2a0000;
15376 -Opcode_madd_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15378 - slotbuf[0] = 0x4a0000;
15382 -Opcode_msub_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15384 - slotbuf[0] = 0x5a0000;
15388 -Opcode_movf_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15390 - slotbuf[0] = 0xcb0000;
15394 -Opcode_movt_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15396 - slotbuf[0] = 0xdb0000;
15400 -Opcode_moveqz_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15402 - slotbuf[0] = 0x8b0000;
15406 -Opcode_movnez_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15408 - slotbuf[0] = 0x9b0000;
15412 -Opcode_movltz_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15414 - slotbuf[0] = 0xab0000;
15418 -Opcode_movgez_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15420 - slotbuf[0] = 0xbb0000;
15424 -Opcode_abs_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15426 - slotbuf[0] = 0xfa0010;
15430 -Opcode_mov_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15432 - slotbuf[0] = 0xfa0000;
15436 -Opcode_neg_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15438 - slotbuf[0] = 0xfa0060;
15442 -Opcode_un_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15444 - slotbuf[0] = 0x1b0000;
15448 -Opcode_oeq_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15450 - slotbuf[0] = 0x2b0000;
15454 -Opcode_ueq_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15456 - slotbuf[0] = 0x3b0000;
15460 -Opcode_olt_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15462 - slotbuf[0] = 0x4b0000;
15466 -Opcode_ult_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15468 - slotbuf[0] = 0x5b0000;
15472 -Opcode_ole_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15474 - slotbuf[0] = 0x6b0000;
15478 -Opcode_ule_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15480 - slotbuf[0] = 0x7b0000;
15484 -Opcode_float_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15486 - slotbuf[0] = 0xca0000;
15490 -Opcode_ufloat_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15492 - slotbuf[0] = 0xda0000;
15496 -Opcode_round_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15498 - slotbuf[0] = 0x8a0000;
15502 -Opcode_ceil_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15504 - slotbuf[0] = 0xba0000;
15508 -Opcode_floor_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15510 - slotbuf[0] = 0xaa0000;
15514 -Opcode_trunc_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15516 - slotbuf[0] = 0x9a0000;
15520 -Opcode_utrunc_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
15522 - slotbuf[0] = 0xea0000;
15526 -Opcode_rfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
15528 - slotbuf[0] = 0xfa0040;
15532 -Opcode_wfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
15534 - slotbuf[0] = 0xfa0050;
15538 -Opcode_lsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
15540 - slotbuf[0] = 0x3;
15544 -Opcode_lsiu_Slot_inst_encode (xtensa_insnbuf slotbuf)
15546 - slotbuf[0] = 0x8003;
15550 -Opcode_lsx_Slot_inst_encode (xtensa_insnbuf slotbuf)
15552 - slotbuf[0] = 0x80000;
15556 -Opcode_lsxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
15558 - slotbuf[0] = 0x180000;
15562 -Opcode_ssi_Slot_inst_encode (xtensa_insnbuf slotbuf)
15564 - slotbuf[0] = 0x4003;
15568 -Opcode_ssiu_Slot_inst_encode (xtensa_insnbuf slotbuf)
15570 - slotbuf[0] = 0xc003;
15574 -Opcode_ssx_Slot_inst_encode (xtensa_insnbuf slotbuf)
15576 - slotbuf[0] = 0x480000;
15580 -Opcode_ssxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
15582 - slotbuf[0] = 0x580000;
15586 -Opcode_beqz_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15588 - slotbuf[0] = 0xa8000000;
15593 -Opcode_bnez_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15595 - slotbuf[0] = 0xc0000000;
15600 -Opcode_bgez_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15602 - slotbuf[0] = 0xb0000000;
15607 -Opcode_bltz_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15609 - slotbuf[0] = 0xb8000000;
15614 -Opcode_beqi_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15616 - slotbuf[0] = 0x40000000;
15621 -Opcode_bnei_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15623 - slotbuf[0] = 0x98000000;
15628 -Opcode_bgei_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15630 - slotbuf[0] = 0x50000000;
15635 -Opcode_blti_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15637 - slotbuf[0] = 0x70000000;
15642 -Opcode_bgeui_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15644 - slotbuf[0] = 0x60000000;
15649 -Opcode_bltui_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15651 - slotbuf[0] = 0x80000000;
15656 -Opcode_bbci_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15658 - slotbuf[0] = 0x8000000;
15663 -Opcode_bbsi_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15665 - slotbuf[0] = 0x10000000;
15670 -Opcode_beq_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15672 - slotbuf[0] = 0x38000000;
15677 -Opcode_bne_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15679 - slotbuf[0] = 0x90000000;
15684 -Opcode_bge_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15686 - slotbuf[0] = 0x48000000;
15691 -Opcode_blt_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15693 - slotbuf[0] = 0x68000000;
15698 -Opcode_bgeu_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15700 - slotbuf[0] = 0x58000000;
15705 -Opcode_bltu_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15707 - slotbuf[0] = 0x78000000;
15712 -Opcode_bany_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15714 - slotbuf[0] = 0x20000000;
15719 -Opcode_bnone_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15721 - slotbuf[0] = 0xa0000000;
15726 -Opcode_ball_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15728 - slotbuf[0] = 0x18000000;
15733 -Opcode_bnall_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15735 - slotbuf[0] = 0x88000000;
15740 -Opcode_bbc_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15742 - slotbuf[0] = 0x28000000;
15747 -Opcode_bbs_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
15749 - slotbuf[0] = 0x30000000;
15753 -xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = {
15754 - Opcode_excw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15757 -xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = {
15758 - Opcode_rfe_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15761 -xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = {
15762 - Opcode_rfde_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15765 -xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = {
15766 - Opcode_syscall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15769 -xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = {
15770 - Opcode_simcall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15773 -xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = {
15774 - Opcode_call12_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15777 -xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = {
15778 - Opcode_call8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15781 -xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = {
15782 - Opcode_call4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15785 -xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = {
15786 - Opcode_callx12_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15789 -xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = {
15790 - Opcode_callx8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15793 -xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = {
15794 - Opcode_callx4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15797 -xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = {
15798 - Opcode_entry_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15801 -xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = {
15802 - Opcode_movsp_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15805 -xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = {
15806 - Opcode_rotw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15809 -xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = {
15810 - Opcode_retw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15813 -xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = {
15814 - 0, 0, Opcode_retw_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
15817 -xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = {
15818 - Opcode_rfwo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15821 -xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = {
15822 - Opcode_rfwu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15825 -xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = {
15826 - Opcode_l32e_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15829 -xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = {
15830 - Opcode_s32e_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15833 -xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = {
15834 - Opcode_rsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15837 -xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = {
15838 - Opcode_wsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15841 -xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = {
15842 - Opcode_xsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15845 -xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = {
15846 - Opcode_rsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15849 -xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = {
15850 - Opcode_wsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15853 -xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = {
15854 - Opcode_xsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15857 -xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = {
15858 - 0, Opcode_add_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0
15861 -xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = {
15862 - 0, Opcode_addi_n_Slot_inst16a_encode, 0, 0, 0, 0, Opcode_addi_n_Slot_xt_flix64_slot2_encode, 0
15865 -xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = {
15866 - 0, 0, Opcode_beqz_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
15869 -xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = {
15870 - 0, 0, Opcode_bnez_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
15873 -xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = {
15874 - 0, 0, Opcode_ill_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
15877 -xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = {
15878 - 0, Opcode_l32i_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0
15881 -xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = {
15882 - 0, 0, Opcode_mov_n_Slot_inst16b_encode, Opcode_mov_n_Slot_xt_flix64_slot0_encode, Opcode_mov_n_Slot_xt_flix64_slot0_encode, Opcode_mov_n_Slot_xt_flix64_slot1_encode, Opcode_mov_n_Slot_xt_flix64_slot2_encode, 0
15885 -xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = {
15886 - 0, 0, Opcode_movi_n_Slot_inst16b_encode, 0, 0, 0, Opcode_movi_n_Slot_xt_flix64_slot2_encode, 0
15889 -xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = {
15890 - 0, 0, Opcode_nop_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
15893 -xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = {
15894 - 0, 0, Opcode_ret_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
15897 -xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = {
15898 - 0, Opcode_s32i_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0
15901 -xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = {
15902 - Opcode_rur_threadptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15905 -xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = {
15906 - Opcode_wur_threadptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15909 -xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = {
15910 - Opcode_addi_Slot_inst_encode, 0, 0, Opcode_addi_Slot_xt_flix64_slot0_encode, Opcode_addi_Slot_xt_flix64_slot0_encode, Opcode_addi_Slot_xt_flix64_slot1_encode, 0, 0
15913 -xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = {
15914 - Opcode_addmi_Slot_inst_encode, 0, 0, Opcode_addmi_Slot_xt_flix64_slot0_encode, Opcode_addmi_Slot_xt_flix64_slot0_encode, Opcode_addmi_Slot_xt_flix64_slot1_encode, 0, 0
15917 -xtensa_opcode_encode_fn Opcode_add_encode_fns[] = {
15918 - Opcode_add_Slot_inst_encode, 0, 0, Opcode_add_Slot_xt_flix64_slot0_encode, Opcode_add_Slot_xt_flix64_slot0_encode, Opcode_add_Slot_xt_flix64_slot1_encode, Opcode_add_Slot_xt_flix64_slot2_encode, 0
15921 -xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = {
15922 - Opcode_sub_Slot_inst_encode, 0, 0, Opcode_sub_Slot_xt_flix64_slot0_encode, Opcode_sub_Slot_xt_flix64_slot0_encode, Opcode_sub_Slot_xt_flix64_slot1_encode, Opcode_sub_Slot_xt_flix64_slot2_encode, 0
15925 -xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = {
15926 - Opcode_addx2_Slot_inst_encode, 0, 0, Opcode_addx2_Slot_xt_flix64_slot0_encode, Opcode_addx2_Slot_xt_flix64_slot0_encode, Opcode_addx2_Slot_xt_flix64_slot1_encode, Opcode_addx2_Slot_xt_flix64_slot2_encode, 0
15929 -xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = {
15930 - Opcode_addx4_Slot_inst_encode, 0, 0, Opcode_addx4_Slot_xt_flix64_slot0_encode, Opcode_addx4_Slot_xt_flix64_slot0_encode, Opcode_addx4_Slot_xt_flix64_slot1_encode, Opcode_addx4_Slot_xt_flix64_slot2_encode, 0
15933 -xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = {
15934 - Opcode_addx8_Slot_inst_encode, 0, 0, Opcode_addx8_Slot_xt_flix64_slot0_encode, Opcode_addx8_Slot_xt_flix64_slot0_encode, Opcode_addx8_Slot_xt_flix64_slot1_encode, 0, 0
15937 -xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = {
15938 - Opcode_subx2_Slot_inst_encode, 0, 0, Opcode_subx2_Slot_xt_flix64_slot0_encode, Opcode_subx2_Slot_xt_flix64_slot0_encode, 0, 0, 0
15941 -xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = {
15942 - Opcode_subx4_Slot_inst_encode, 0, 0, Opcode_subx4_Slot_xt_flix64_slot0_encode, Opcode_subx4_Slot_xt_flix64_slot0_encode, 0, 0, 0
15945 -xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = {
15946 - Opcode_subx8_Slot_inst_encode, 0, 0, Opcode_subx8_Slot_xt_flix64_slot0_encode, Opcode_subx8_Slot_xt_flix64_slot0_encode, 0, 0, 0
15949 -xtensa_opcode_encode_fn Opcode_and_encode_fns[] = {
15950 - Opcode_and_Slot_inst_encode, 0, 0, Opcode_and_Slot_xt_flix64_slot0_encode, Opcode_and_Slot_xt_flix64_slot0_encode, Opcode_and_Slot_xt_flix64_slot1_encode, Opcode_and_Slot_xt_flix64_slot2_encode, 0
15953 -xtensa_opcode_encode_fn Opcode_or_encode_fns[] = {
15954 - Opcode_or_Slot_inst_encode, 0, 0, Opcode_or_Slot_xt_flix64_slot0_encode, Opcode_or_Slot_xt_flix64_slot0_encode, Opcode_or_Slot_xt_flix64_slot1_encode, Opcode_or_Slot_xt_flix64_slot2_encode, 0
15957 -xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = {
15958 - Opcode_xor_Slot_inst_encode, 0, 0, Opcode_xor_Slot_xt_flix64_slot0_encode, Opcode_xor_Slot_xt_flix64_slot0_encode, Opcode_xor_Slot_xt_flix64_slot1_encode, Opcode_xor_Slot_xt_flix64_slot2_encode, 0
15961 -xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = {
15962 - Opcode_beqi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15965 -xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = {
15966 - Opcode_bnei_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15969 -xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = {
15970 - Opcode_bgei_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15973 -xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = {
15974 - Opcode_blti_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15977 -xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = {
15978 - Opcode_bbci_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15981 -xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = {
15982 - Opcode_bbsi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15985 -xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = {
15986 - Opcode_bgeui_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15989 -xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = {
15990 - Opcode_bltui_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15993 -xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = {
15994 - Opcode_beq_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
15997 -xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = {
15998 - Opcode_bne_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16001 -xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = {
16002 - Opcode_bge_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16005 -xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = {
16006 - Opcode_blt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16009 -xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = {
16010 - Opcode_bgeu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16013 -xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = {
16014 - Opcode_bltu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16017 -xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = {
16018 - Opcode_bany_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16021 -xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = {
16022 - Opcode_bnone_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16025 -xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = {
16026 - Opcode_ball_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16029 -xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = {
16030 - Opcode_bnall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16033 -xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = {
16034 - Opcode_bbc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16037 -xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = {
16038 - Opcode_bbs_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16041 -xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = {
16042 - Opcode_beqz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16045 -xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = {
16046 - Opcode_bnez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16049 -xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = {
16050 - Opcode_bgez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16053 -xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = {
16054 - Opcode_bltz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16057 -xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = {
16058 - Opcode_call0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16061 -xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = {
16062 - Opcode_callx0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16065 -xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = {
16066 - Opcode_extui_Slot_inst_encode, 0, 0, Opcode_extui_Slot_xt_flix64_slot0_encode, Opcode_extui_Slot_xt_flix64_slot0_encode, Opcode_extui_Slot_xt_flix64_slot1_encode, 0, 0
16069 -xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = {
16070 - Opcode_ill_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16073 -xtensa_opcode_encode_fn Opcode_j_encode_fns[] = {
16074 - Opcode_j_Slot_inst_encode, 0, 0, 0, 0, Opcode_j_Slot_xt_flix64_slot1_encode, 0, 0
16077 -xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = {
16078 - Opcode_jx_Slot_inst_encode, 0, 0, 0, 0, Opcode_jx_Slot_xt_flix64_slot1_encode, 0, 0
16081 -xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = {
16082 - Opcode_l16ui_Slot_inst_encode, 0, 0, Opcode_l16ui_Slot_xt_flix64_slot0_encode, Opcode_l16ui_Slot_xt_flix64_slot0_encode, 0, 0, 0
16085 -xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = {
16086 - Opcode_l16si_Slot_inst_encode, 0, 0, Opcode_l16si_Slot_xt_flix64_slot0_encode, Opcode_l16si_Slot_xt_flix64_slot0_encode, 0, 0, 0
16089 -xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = {
16090 - Opcode_l32i_Slot_inst_encode, 0, 0, Opcode_l32i_Slot_xt_flix64_slot0_encode, Opcode_l32i_Slot_xt_flix64_slot0_encode, 0, 0, 0
16093 -xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = {
16094 - Opcode_l32r_Slot_inst_encode, 0, 0, Opcode_l32r_Slot_xt_flix64_slot0_encode, Opcode_l32r_Slot_xt_flix64_slot0_encode, 0, 0, 0
16097 -xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = {
16098 - Opcode_l8ui_Slot_inst_encode, 0, 0, Opcode_l8ui_Slot_xt_flix64_slot0_encode, Opcode_l8ui_Slot_xt_flix64_slot0_encode, 0, 0, 0
16101 -xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = {
16102 - Opcode_loop_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16105 -xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = {
16106 - Opcode_loopnez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16109 -xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = {
16110 - Opcode_loopgtz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16113 -xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = {
16114 - Opcode_movi_Slot_inst_encode, 0, 0, Opcode_movi_Slot_xt_flix64_slot0_encode, Opcode_movi_Slot_xt_flix64_slot0_encode, Opcode_movi_Slot_xt_flix64_slot1_encode, 0, 0
16117 -xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = {
16118 - Opcode_moveqz_Slot_inst_encode, 0, 0, Opcode_moveqz_Slot_xt_flix64_slot0_encode, Opcode_moveqz_Slot_xt_flix64_slot0_encode, Opcode_moveqz_Slot_xt_flix64_slot1_encode, 0, 0
16121 -xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = {
16122 - Opcode_movnez_Slot_inst_encode, 0, 0, Opcode_movnez_Slot_xt_flix64_slot0_encode, Opcode_movnez_Slot_xt_flix64_slot0_encode, Opcode_movnez_Slot_xt_flix64_slot1_encode, 0, 0
16125 -xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = {
16126 - Opcode_movltz_Slot_inst_encode, 0, 0, Opcode_movltz_Slot_xt_flix64_slot0_encode, Opcode_movltz_Slot_xt_flix64_slot0_encode, Opcode_movltz_Slot_xt_flix64_slot1_encode, 0, 0
16129 -xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = {
16130 - Opcode_movgez_Slot_inst_encode, 0, 0, Opcode_movgez_Slot_xt_flix64_slot0_encode, Opcode_movgez_Slot_xt_flix64_slot0_encode, Opcode_movgez_Slot_xt_flix64_slot1_encode, 0, 0
16133 -xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = {
16134 - Opcode_neg_Slot_inst_encode, 0, 0, Opcode_neg_Slot_xt_flix64_slot0_encode, Opcode_neg_Slot_xt_flix64_slot0_encode, Opcode_neg_Slot_xt_flix64_slot1_encode, Opcode_neg_Slot_xt_flix64_slot2_encode, 0
16137 -xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = {
16138 - Opcode_abs_Slot_inst_encode, 0, 0, Opcode_abs_Slot_xt_flix64_slot0_encode, Opcode_abs_Slot_xt_flix64_slot0_encode, 0, Opcode_abs_Slot_xt_flix64_slot2_encode, 0
16141 -xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = {
16142 - Opcode_nop_Slot_inst_encode, 0, 0, Opcode_nop_Slot_xt_flix64_slot0_encode, Opcode_nop_Slot_xt_flix64_slot0_encode, Opcode_nop_Slot_xt_flix64_slot1_encode, Opcode_nop_Slot_xt_flix64_slot2_encode, Opcode_nop_Slot_xt_flix64_slot3_encode
16145 -xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = {
16146 - Opcode_ret_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16149 -xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = {
16150 - Opcode_s16i_Slot_inst_encode, 0, 0, Opcode_s16i_Slot_xt_flix64_slot0_encode, Opcode_s16i_Slot_xt_flix64_slot0_encode, 0, 0, 0
16153 -xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = {
16154 - Opcode_s32i_Slot_inst_encode, 0, 0, Opcode_s32i_Slot_xt_flix64_slot0_encode, Opcode_s32i_Slot_xt_flix64_slot0_encode, 0, 0, 0
16157 -xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = {
16158 - Opcode_s8i_Slot_inst_encode, 0, 0, Opcode_s8i_Slot_xt_flix64_slot0_encode, Opcode_s8i_Slot_xt_flix64_slot0_encode, 0, 0, 0
16161 -xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = {
16162 - Opcode_ssr_Slot_inst_encode, 0, 0, Opcode_ssr_Slot_xt_flix64_slot0_encode, Opcode_ssr_Slot_xt_flix64_slot0_encode, 0, 0, 0
16165 -xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = {
16166 - Opcode_ssl_Slot_inst_encode, 0, 0, Opcode_ssl_Slot_xt_flix64_slot0_encode, Opcode_ssl_Slot_xt_flix64_slot0_encode, Opcode_ssl_Slot_xt_flix64_slot1_encode, 0, 0
16169 -xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = {
16170 - Opcode_ssa8l_Slot_inst_encode, 0, 0, Opcode_ssa8l_Slot_xt_flix64_slot0_encode, Opcode_ssa8l_Slot_xt_flix64_slot0_encode, 0, 0, 0
16173 -xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = {
16174 - Opcode_ssa8b_Slot_inst_encode, 0, 0, Opcode_ssa8b_Slot_xt_flix64_slot0_encode, Opcode_ssa8b_Slot_xt_flix64_slot0_encode, 0, 0, 0
16177 -xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = {
16178 - Opcode_ssai_Slot_inst_encode, 0, 0, Opcode_ssai_Slot_xt_flix64_slot0_encode, Opcode_ssai_Slot_xt_flix64_slot0_encode, 0, 0, 0
16181 -xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = {
16182 - Opcode_sll_Slot_inst_encode, 0, 0, Opcode_sll_Slot_xt_flix64_slot0_encode, Opcode_sll_Slot_xt_flix64_slot0_encode, Opcode_sll_Slot_xt_flix64_slot1_encode, 0, 0
16185 -xtensa_opcode_encode_fn Opcode_src_encode_fns[] = {
16186 - Opcode_src_Slot_inst_encode, 0, 0, Opcode_src_Slot_xt_flix64_slot0_encode, Opcode_src_Slot_xt_flix64_slot0_encode, Opcode_src_Slot_xt_flix64_slot1_encode, 0, 0
16189 -xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = {
16190 - Opcode_srl_Slot_inst_encode, 0, 0, Opcode_srl_Slot_xt_flix64_slot0_encode, Opcode_srl_Slot_xt_flix64_slot0_encode, Opcode_srl_Slot_xt_flix64_slot1_encode, Opcode_srl_Slot_xt_flix64_slot2_encode, 0
16193 -xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = {
16194 - Opcode_sra_Slot_inst_encode, 0, 0, Opcode_sra_Slot_xt_flix64_slot0_encode, Opcode_sra_Slot_xt_flix64_slot0_encode, Opcode_sra_Slot_xt_flix64_slot1_encode, Opcode_sra_Slot_xt_flix64_slot2_encode, 0
16197 -xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = {
16198 - Opcode_slli_Slot_inst_encode, 0, 0, Opcode_slli_Slot_xt_flix64_slot0_encode, Opcode_slli_Slot_xt_flix64_slot0_encode, Opcode_slli_Slot_xt_flix64_slot1_encode, 0, 0
16201 -xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = {
16202 - Opcode_srai_Slot_inst_encode, 0, 0, Opcode_srai_Slot_xt_flix64_slot0_encode, Opcode_srai_Slot_xt_flix64_slot0_encode, Opcode_srai_Slot_xt_flix64_slot1_encode, Opcode_srai_Slot_xt_flix64_slot2_encode, 0
16205 -xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = {
16206 - Opcode_srli_Slot_inst_encode, 0, 0, Opcode_srli_Slot_xt_flix64_slot0_encode, Opcode_srli_Slot_xt_flix64_slot0_encode, Opcode_srli_Slot_xt_flix64_slot1_encode, Opcode_srli_Slot_xt_flix64_slot2_encode, 0
16209 -xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = {
16210 - Opcode_memw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16213 -xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = {
16214 - Opcode_extw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16217 -xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = {
16218 - Opcode_isync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16221 -xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = {
16222 - Opcode_rsync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16225 -xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = {
16226 - Opcode_esync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16229 -xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = {
16230 - Opcode_dsync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16233 -xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = {
16234 - Opcode_rsil_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16237 -xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = {
16238 - Opcode_rsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16241 -xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = {
16242 - Opcode_wsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16245 -xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = {
16246 - Opcode_xsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16249 -xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = {
16250 - Opcode_rsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16253 -xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = {
16254 - Opcode_wsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16257 -xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = {
16258 - Opcode_xsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16261 -xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = {
16262 - Opcode_rsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16265 -xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = {
16266 - Opcode_wsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16269 -xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = {
16270 - Opcode_xsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16273 -xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = {
16274 - Opcode_rsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16277 -xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = {
16278 - Opcode_wsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16281 -xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = {
16282 - Opcode_xsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16285 -xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = {
16286 - Opcode_rsr_litbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16289 -xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = {
16290 - Opcode_wsr_litbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16293 -xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = {
16294 - Opcode_xsr_litbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16297 -xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = {
16298 - Opcode_rsr_176_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16301 -xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = {
16302 - Opcode_rsr_208_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16305 -xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = {
16306 - Opcode_rsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16309 -xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = {
16310 - Opcode_wsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16313 -xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = {
16314 - Opcode_xsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16317 -xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = {
16318 - Opcode_rsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16321 -xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = {
16322 - Opcode_wsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16325 -xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = {
16326 - Opcode_xsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16329 -xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = {
16330 - Opcode_rsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16333 -xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = {
16334 - Opcode_wsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16337 -xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = {
16338 - Opcode_xsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16341 -xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = {
16342 - Opcode_rsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16345 -xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = {
16346 - Opcode_wsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16349 -xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = {
16350 - Opcode_xsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16353 -xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = {
16354 - Opcode_rsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16357 -xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = {
16358 - Opcode_wsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16361 -xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = {
16362 - Opcode_xsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16365 -xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = {
16366 - Opcode_rsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16369 -xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = {
16370 - Opcode_wsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16373 -xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = {
16374 - Opcode_xsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16377 -xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = {
16378 - Opcode_rsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16381 -xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = {
16382 - Opcode_wsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16385 -xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = {
16386 - Opcode_xsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16389 -xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = {
16390 - Opcode_rsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16393 -xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = {
16394 - Opcode_wsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16397 -xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = {
16398 - Opcode_xsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16401 -xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = {
16402 - Opcode_rsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16405 -xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = {
16406 - Opcode_wsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16409 -xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = {
16410 - Opcode_xsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16413 -xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = {
16414 - Opcode_rsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16417 -xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = {
16418 - Opcode_wsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16421 -xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = {
16422 - Opcode_xsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16425 -xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = {
16426 - Opcode_rsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16429 -xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = {
16430 - Opcode_wsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16433 -xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = {
16434 - Opcode_xsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16437 -xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = {
16438 - Opcode_rsr_epc6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16441 -xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = {
16442 - Opcode_wsr_epc6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16445 -xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = {
16446 - Opcode_xsr_epc6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16449 -xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = {
16450 - Opcode_rsr_excsave6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16453 -xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = {
16454 - Opcode_wsr_excsave6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16457 -xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = {
16458 - Opcode_xsr_excsave6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16461 -xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = {
16462 - Opcode_rsr_epc7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16465 -xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = {
16466 - Opcode_wsr_epc7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16469 -xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = {
16470 - Opcode_xsr_epc7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16473 -xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = {
16474 - Opcode_rsr_excsave7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16477 -xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = {
16478 - Opcode_wsr_excsave7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16481 -xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = {
16482 - Opcode_xsr_excsave7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16485 -xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = {
16486 - Opcode_rsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16489 -xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = {
16490 - Opcode_wsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16493 -xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = {
16494 - Opcode_xsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16497 -xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = {
16498 - Opcode_rsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16501 -xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = {
16502 - Opcode_wsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16505 -xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = {
16506 - Opcode_xsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16509 -xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = {
16510 - Opcode_rsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16513 -xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = {
16514 - Opcode_wsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16517 -xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = {
16518 - Opcode_xsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16521 -xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = {
16522 - Opcode_rsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16525 -xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = {
16526 - Opcode_wsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16529 -xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = {
16530 - Opcode_xsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16533 -xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = {
16534 - Opcode_rsr_eps6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16537 -xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = {
16538 - Opcode_wsr_eps6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16541 -xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = {
16542 - Opcode_xsr_eps6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16545 -xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = {
16546 - Opcode_rsr_eps7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16549 -xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = {
16550 - Opcode_wsr_eps7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16553 -xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = {
16554 - Opcode_xsr_eps7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16557 -xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = {
16558 - Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16561 -xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = {
16562 - Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16565 -xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = {
16566 - Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16569 -xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = {
16570 - Opcode_rsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16573 -xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = {
16574 - Opcode_wsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16577 -xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = {
16578 - Opcode_xsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16581 -xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = {
16582 - Opcode_rsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16585 -xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = {
16586 - Opcode_wsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16589 -xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = {
16590 - Opcode_xsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16593 -xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = {
16594 - Opcode_rsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16597 -xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = {
16598 - Opcode_wsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16601 -xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = {
16602 - Opcode_xsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16605 -xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = {
16606 - Opcode_rsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16609 -xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = {
16610 - Opcode_wsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16613 -xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = {
16614 - Opcode_xsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16617 -xtensa_opcode_encode_fn Opcode_rsr_misc2_encode_fns[] = {
16618 - Opcode_rsr_misc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16621 -xtensa_opcode_encode_fn Opcode_wsr_misc2_encode_fns[] = {
16622 - Opcode_wsr_misc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16625 -xtensa_opcode_encode_fn Opcode_xsr_misc2_encode_fns[] = {
16626 - Opcode_xsr_misc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16629 -xtensa_opcode_encode_fn Opcode_rsr_misc3_encode_fns[] = {
16630 - Opcode_rsr_misc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16633 -xtensa_opcode_encode_fn Opcode_wsr_misc3_encode_fns[] = {
16634 - Opcode_wsr_misc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16637 -xtensa_opcode_encode_fn Opcode_xsr_misc3_encode_fns[] = {
16638 - Opcode_xsr_misc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16641 -xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = {
16642 - Opcode_rsr_prid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16645 -xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = {
16646 - Opcode_rsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16649 -xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = {
16650 - Opcode_wsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16653 -xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = {
16654 - Opcode_xsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16657 -xtensa_opcode_encode_fn Opcode_mul_aa_ll_encode_fns[] = {
16658 - Opcode_mul_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16661 -xtensa_opcode_encode_fn Opcode_mul_aa_hl_encode_fns[] = {
16662 - Opcode_mul_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16665 -xtensa_opcode_encode_fn Opcode_mul_aa_lh_encode_fns[] = {
16666 - Opcode_mul_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16669 -xtensa_opcode_encode_fn Opcode_mul_aa_hh_encode_fns[] = {
16670 - Opcode_mul_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16673 -xtensa_opcode_encode_fn Opcode_umul_aa_ll_encode_fns[] = {
16674 - Opcode_umul_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16677 -xtensa_opcode_encode_fn Opcode_umul_aa_hl_encode_fns[] = {
16678 - Opcode_umul_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16681 -xtensa_opcode_encode_fn Opcode_umul_aa_lh_encode_fns[] = {
16682 - Opcode_umul_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16685 -xtensa_opcode_encode_fn Opcode_umul_aa_hh_encode_fns[] = {
16686 - Opcode_umul_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16689 -xtensa_opcode_encode_fn Opcode_mul_ad_ll_encode_fns[] = {
16690 - Opcode_mul_ad_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16693 -xtensa_opcode_encode_fn Opcode_mul_ad_hl_encode_fns[] = {
16694 - Opcode_mul_ad_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16697 -xtensa_opcode_encode_fn Opcode_mul_ad_lh_encode_fns[] = {
16698 - Opcode_mul_ad_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16701 -xtensa_opcode_encode_fn Opcode_mul_ad_hh_encode_fns[] = {
16702 - Opcode_mul_ad_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16705 -xtensa_opcode_encode_fn Opcode_mul_da_ll_encode_fns[] = {
16706 - Opcode_mul_da_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16709 -xtensa_opcode_encode_fn Opcode_mul_da_hl_encode_fns[] = {
16710 - Opcode_mul_da_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16713 -xtensa_opcode_encode_fn Opcode_mul_da_lh_encode_fns[] = {
16714 - Opcode_mul_da_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16717 -xtensa_opcode_encode_fn Opcode_mul_da_hh_encode_fns[] = {
16718 - Opcode_mul_da_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16721 -xtensa_opcode_encode_fn Opcode_mul_dd_ll_encode_fns[] = {
16722 - Opcode_mul_dd_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16725 -xtensa_opcode_encode_fn Opcode_mul_dd_hl_encode_fns[] = {
16726 - Opcode_mul_dd_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16729 -xtensa_opcode_encode_fn Opcode_mul_dd_lh_encode_fns[] = {
16730 - Opcode_mul_dd_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16733 -xtensa_opcode_encode_fn Opcode_mul_dd_hh_encode_fns[] = {
16734 - Opcode_mul_dd_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16737 -xtensa_opcode_encode_fn Opcode_mula_aa_ll_encode_fns[] = {
16738 - Opcode_mula_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16741 -xtensa_opcode_encode_fn Opcode_mula_aa_hl_encode_fns[] = {
16742 - Opcode_mula_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16745 -xtensa_opcode_encode_fn Opcode_mula_aa_lh_encode_fns[] = {
16746 - Opcode_mula_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16749 -xtensa_opcode_encode_fn Opcode_mula_aa_hh_encode_fns[] = {
16750 - Opcode_mula_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16753 -xtensa_opcode_encode_fn Opcode_muls_aa_ll_encode_fns[] = {
16754 - Opcode_muls_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16757 -xtensa_opcode_encode_fn Opcode_muls_aa_hl_encode_fns[] = {
16758 - Opcode_muls_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16761 -xtensa_opcode_encode_fn Opcode_muls_aa_lh_encode_fns[] = {
16762 - Opcode_muls_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16765 -xtensa_opcode_encode_fn Opcode_muls_aa_hh_encode_fns[] = {
16766 - Opcode_muls_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16769 -xtensa_opcode_encode_fn Opcode_mula_ad_ll_encode_fns[] = {
16770 - Opcode_mula_ad_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16773 -xtensa_opcode_encode_fn Opcode_mula_ad_hl_encode_fns[] = {
16774 - Opcode_mula_ad_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16777 -xtensa_opcode_encode_fn Opcode_mula_ad_lh_encode_fns[] = {
16778 - Opcode_mula_ad_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16781 -xtensa_opcode_encode_fn Opcode_mula_ad_hh_encode_fns[] = {
16782 - Opcode_mula_ad_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16785 -xtensa_opcode_encode_fn Opcode_muls_ad_ll_encode_fns[] = {
16786 - Opcode_muls_ad_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16789 -xtensa_opcode_encode_fn Opcode_muls_ad_hl_encode_fns[] = {
16790 - Opcode_muls_ad_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16793 -xtensa_opcode_encode_fn Opcode_muls_ad_lh_encode_fns[] = {
16794 - Opcode_muls_ad_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16797 -xtensa_opcode_encode_fn Opcode_muls_ad_hh_encode_fns[] = {
16798 - Opcode_muls_ad_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16801 -xtensa_opcode_encode_fn Opcode_mula_da_ll_encode_fns[] = {
16802 - Opcode_mula_da_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16805 -xtensa_opcode_encode_fn Opcode_mula_da_hl_encode_fns[] = {
16806 - Opcode_mula_da_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16809 -xtensa_opcode_encode_fn Opcode_mula_da_lh_encode_fns[] = {
16810 - Opcode_mula_da_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16813 -xtensa_opcode_encode_fn Opcode_mula_da_hh_encode_fns[] = {
16814 - Opcode_mula_da_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16817 -xtensa_opcode_encode_fn Opcode_muls_da_ll_encode_fns[] = {
16818 - Opcode_muls_da_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16821 -xtensa_opcode_encode_fn Opcode_muls_da_hl_encode_fns[] = {
16822 - Opcode_muls_da_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16825 -xtensa_opcode_encode_fn Opcode_muls_da_lh_encode_fns[] = {
16826 - Opcode_muls_da_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16829 -xtensa_opcode_encode_fn Opcode_muls_da_hh_encode_fns[] = {
16830 - Opcode_muls_da_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16833 -xtensa_opcode_encode_fn Opcode_mula_dd_ll_encode_fns[] = {
16834 - Opcode_mula_dd_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16837 -xtensa_opcode_encode_fn Opcode_mula_dd_hl_encode_fns[] = {
16838 - Opcode_mula_dd_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16841 -xtensa_opcode_encode_fn Opcode_mula_dd_lh_encode_fns[] = {
16842 - Opcode_mula_dd_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16845 -xtensa_opcode_encode_fn Opcode_mula_dd_hh_encode_fns[] = {
16846 - Opcode_mula_dd_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16849 -xtensa_opcode_encode_fn Opcode_muls_dd_ll_encode_fns[] = {
16850 - Opcode_muls_dd_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16853 -xtensa_opcode_encode_fn Opcode_muls_dd_hl_encode_fns[] = {
16854 - Opcode_muls_dd_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16857 -xtensa_opcode_encode_fn Opcode_muls_dd_lh_encode_fns[] = {
16858 - Opcode_muls_dd_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16861 -xtensa_opcode_encode_fn Opcode_muls_dd_hh_encode_fns[] = {
16862 - Opcode_muls_dd_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16865 -xtensa_opcode_encode_fn Opcode_mula_da_ll_lddec_encode_fns[] = {
16866 - Opcode_mula_da_ll_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16869 -xtensa_opcode_encode_fn Opcode_mula_da_ll_ldinc_encode_fns[] = {
16870 - Opcode_mula_da_ll_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16873 -xtensa_opcode_encode_fn Opcode_mula_da_hl_lddec_encode_fns[] = {
16874 - Opcode_mula_da_hl_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16877 -xtensa_opcode_encode_fn Opcode_mula_da_hl_ldinc_encode_fns[] = {
16878 - Opcode_mula_da_hl_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16881 -xtensa_opcode_encode_fn Opcode_mula_da_lh_lddec_encode_fns[] = {
16882 - Opcode_mula_da_lh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16885 -xtensa_opcode_encode_fn Opcode_mula_da_lh_ldinc_encode_fns[] = {
16886 - Opcode_mula_da_lh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16889 -xtensa_opcode_encode_fn Opcode_mula_da_hh_lddec_encode_fns[] = {
16890 - Opcode_mula_da_hh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16893 -xtensa_opcode_encode_fn Opcode_mula_da_hh_ldinc_encode_fns[] = {
16894 - Opcode_mula_da_hh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16897 -xtensa_opcode_encode_fn Opcode_mula_dd_ll_lddec_encode_fns[] = {
16898 - Opcode_mula_dd_ll_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16901 -xtensa_opcode_encode_fn Opcode_mula_dd_ll_ldinc_encode_fns[] = {
16902 - Opcode_mula_dd_ll_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16905 -xtensa_opcode_encode_fn Opcode_mula_dd_hl_lddec_encode_fns[] = {
16906 - Opcode_mula_dd_hl_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16909 -xtensa_opcode_encode_fn Opcode_mula_dd_hl_ldinc_encode_fns[] = {
16910 - Opcode_mula_dd_hl_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16913 -xtensa_opcode_encode_fn Opcode_mula_dd_lh_lddec_encode_fns[] = {
16914 - Opcode_mula_dd_lh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16917 -xtensa_opcode_encode_fn Opcode_mula_dd_lh_ldinc_encode_fns[] = {
16918 - Opcode_mula_dd_lh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16921 -xtensa_opcode_encode_fn Opcode_mula_dd_hh_lddec_encode_fns[] = {
16922 - Opcode_mula_dd_hh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16925 -xtensa_opcode_encode_fn Opcode_mula_dd_hh_ldinc_encode_fns[] = {
16926 - Opcode_mula_dd_hh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16929 -xtensa_opcode_encode_fn Opcode_lddec_encode_fns[] = {
16930 - Opcode_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16933 -xtensa_opcode_encode_fn Opcode_ldinc_encode_fns[] = {
16934 - Opcode_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16937 -xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = {
16938 - Opcode_mul16u_Slot_inst_encode, 0, 0, Opcode_mul16u_Slot_xt_flix64_slot0_encode, Opcode_mul16u_Slot_xt_flix64_slot0_encode, Opcode_mul16u_Slot_xt_flix64_slot1_encode, 0, 0
16941 -xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = {
16942 - Opcode_mul16s_Slot_inst_encode, 0, 0, Opcode_mul16s_Slot_xt_flix64_slot0_encode, Opcode_mul16s_Slot_xt_flix64_slot0_encode, Opcode_mul16s_Slot_xt_flix64_slot1_encode, 0, 0
16945 -xtensa_opcode_encode_fn Opcode_rsr_m0_encode_fns[] = {
16946 - Opcode_rsr_m0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16949 -xtensa_opcode_encode_fn Opcode_wsr_m0_encode_fns[] = {
16950 - Opcode_wsr_m0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16953 -xtensa_opcode_encode_fn Opcode_xsr_m0_encode_fns[] = {
16954 - Opcode_xsr_m0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16957 -xtensa_opcode_encode_fn Opcode_rsr_m1_encode_fns[] = {
16958 - Opcode_rsr_m1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16961 -xtensa_opcode_encode_fn Opcode_wsr_m1_encode_fns[] = {
16962 - Opcode_wsr_m1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16965 -xtensa_opcode_encode_fn Opcode_xsr_m1_encode_fns[] = {
16966 - Opcode_xsr_m1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16969 -xtensa_opcode_encode_fn Opcode_rsr_m2_encode_fns[] = {
16970 - Opcode_rsr_m2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16973 -xtensa_opcode_encode_fn Opcode_wsr_m2_encode_fns[] = {
16974 - Opcode_wsr_m2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16977 -xtensa_opcode_encode_fn Opcode_xsr_m2_encode_fns[] = {
16978 - Opcode_xsr_m2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16981 -xtensa_opcode_encode_fn Opcode_rsr_m3_encode_fns[] = {
16982 - Opcode_rsr_m3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16985 -xtensa_opcode_encode_fn Opcode_wsr_m3_encode_fns[] = {
16986 - Opcode_wsr_m3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16989 -xtensa_opcode_encode_fn Opcode_xsr_m3_encode_fns[] = {
16990 - Opcode_xsr_m3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16993 -xtensa_opcode_encode_fn Opcode_rsr_acclo_encode_fns[] = {
16994 - Opcode_rsr_acclo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
16997 -xtensa_opcode_encode_fn Opcode_wsr_acclo_encode_fns[] = {
16998 - Opcode_wsr_acclo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17001 -xtensa_opcode_encode_fn Opcode_xsr_acclo_encode_fns[] = {
17002 - Opcode_xsr_acclo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17005 -xtensa_opcode_encode_fn Opcode_rsr_acchi_encode_fns[] = {
17006 - Opcode_rsr_acchi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17009 -xtensa_opcode_encode_fn Opcode_wsr_acchi_encode_fns[] = {
17010 - Opcode_wsr_acchi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17013 -xtensa_opcode_encode_fn Opcode_xsr_acchi_encode_fns[] = {
17014 - Opcode_xsr_acchi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17017 -xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = {
17018 - Opcode_rfi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17021 -xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = {
17022 - Opcode_waiti_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17025 -xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = {
17026 - Opcode_rsr_interrupt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17029 -xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = {
17030 - Opcode_wsr_intset_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17033 -xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = {
17034 - Opcode_wsr_intclear_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17037 -xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = {
17038 - Opcode_rsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17041 -xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = {
17042 - Opcode_wsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17045 -xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = {
17046 - Opcode_xsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17049 -xtensa_opcode_encode_fn Opcode_break_encode_fns[] = {
17050 - Opcode_break_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17053 -xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = {
17054 - 0, 0, Opcode_break_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
17057 -xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = {
17058 - Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17061 -xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = {
17062 - Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17065 -xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = {
17066 - Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17069 -xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = {
17070 - Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17073 -xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = {
17074 - Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17077 -xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = {
17078 - Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17081 -xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = {
17082 - Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17085 -xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = {
17086 - Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17089 -xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = {
17090 - Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17093 -xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = {
17094 - Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17097 -xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = {
17098 - Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17101 -xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = {
17102 - Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17105 -xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = {
17106 - Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17109 -xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = {
17110 - Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17113 -xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = {
17114 - Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17117 -xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = {
17118 - Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17121 -xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = {
17122 - Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17125 -xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = {
17126 - Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17129 -xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = {
17130 - Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17133 -xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = {
17134 - Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17137 -xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = {
17138 - Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17141 -xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = {
17142 - Opcode_rsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17145 -xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = {
17146 - Opcode_wsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17149 -xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = {
17150 - Opcode_xsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17153 -xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = {
17154 - Opcode_rsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17157 -xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = {
17158 - Opcode_wsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17161 -xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = {
17162 - Opcode_xsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17165 -xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = {
17166 - Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17169 -xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = {
17170 - Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17173 -xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = {
17174 - Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17177 -xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = {
17178 - Opcode_rsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17181 -xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = {
17182 - Opcode_wsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17185 -xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = {
17186 - Opcode_xsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17189 -xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = {
17190 - Opcode_rfdo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17193 -xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = {
17194 - Opcode_rfdd_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17197 -xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = {
17198 - Opcode_wsr_mmid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17201 -xtensa_opcode_encode_fn Opcode_andb_encode_fns[] = {
17202 - Opcode_andb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17205 -xtensa_opcode_encode_fn Opcode_andbc_encode_fns[] = {
17206 - Opcode_andbc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17209 -xtensa_opcode_encode_fn Opcode_orb_encode_fns[] = {
17210 - Opcode_orb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17213 -xtensa_opcode_encode_fn Opcode_orbc_encode_fns[] = {
17214 - Opcode_orbc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17217 -xtensa_opcode_encode_fn Opcode_xorb_encode_fns[] = {
17218 - Opcode_xorb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17221 -xtensa_opcode_encode_fn Opcode_any4_encode_fns[] = {
17222 - Opcode_any4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17225 -xtensa_opcode_encode_fn Opcode_all4_encode_fns[] = {
17226 - Opcode_all4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17229 -xtensa_opcode_encode_fn Opcode_any8_encode_fns[] = {
17230 - Opcode_any8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17233 -xtensa_opcode_encode_fn Opcode_all8_encode_fns[] = {
17234 - Opcode_all8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17237 -xtensa_opcode_encode_fn Opcode_bf_encode_fns[] = {
17238 - Opcode_bf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17241 -xtensa_opcode_encode_fn Opcode_bt_encode_fns[] = {
17242 - Opcode_bt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17245 -xtensa_opcode_encode_fn Opcode_movf_encode_fns[] = {
17246 - Opcode_movf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17249 -xtensa_opcode_encode_fn Opcode_movt_encode_fns[] = {
17250 - Opcode_movt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17253 -xtensa_opcode_encode_fn Opcode_rsr_br_encode_fns[] = {
17254 - Opcode_rsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17257 -xtensa_opcode_encode_fn Opcode_wsr_br_encode_fns[] = {
17258 - Opcode_wsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17261 -xtensa_opcode_encode_fn Opcode_xsr_br_encode_fns[] = {
17262 - Opcode_xsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17265 -xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = {
17266 - Opcode_rsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17269 -xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = {
17270 - Opcode_wsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17273 -xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = {
17274 - Opcode_xsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17277 -xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = {
17278 - Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17281 -xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = {
17282 - Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17285 -xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = {
17286 - Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17289 -xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = {
17290 - Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17293 -xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = {
17294 - Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17297 -xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = {
17298 - Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17301 -xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = {
17302 - Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17305 -xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = {
17306 - Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17309 -xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = {
17310 - Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17313 -xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = {
17314 - Opcode_ipf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17317 -xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = {
17318 - Opcode_ihi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17321 -xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = {
17322 - Opcode_ipfl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17325 -xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = {
17326 - Opcode_ihu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17329 -xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = {
17330 - Opcode_iiu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17333 -xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = {
17334 - Opcode_iii_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17337 -xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = {
17338 - Opcode_lict_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17341 -xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = {
17342 - Opcode_licw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17345 -xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = {
17346 - Opcode_sict_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17349 -xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = {
17350 - Opcode_sicw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17353 -xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = {
17354 - Opcode_dhwb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17357 -xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = {
17358 - Opcode_dhwbi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17361 -xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = {
17362 - Opcode_diwb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17365 -xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = {
17366 - Opcode_diwbi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17369 -xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = {
17370 - Opcode_dhi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17373 -xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = {
17374 - Opcode_dii_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17377 -xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = {
17378 - Opcode_dpfr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17381 -xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = {
17382 - Opcode_dpfw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17385 -xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = {
17386 - Opcode_dpfro_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17389 -xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = {
17390 - Opcode_dpfwo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17393 -xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = {
17394 - Opcode_dpfl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17397 -xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = {
17398 - Opcode_dhu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17401 -xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = {
17402 - Opcode_diu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17405 -xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = {
17406 - Opcode_sdct_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17409 -xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = {
17410 - Opcode_ldct_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17413 -xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = {
17414 - Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17417 -xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = {
17418 - Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17421 -xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = {
17422 - Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17425 -xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = {
17426 - Opcode_rsr_rasid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17429 -xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = {
17430 - Opcode_wsr_rasid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17433 -xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = {
17434 - Opcode_xsr_rasid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17437 -xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = {
17438 - Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17441 -xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = {
17442 - Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17445 -xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = {
17446 - Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17449 -xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = {
17450 - Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17453 -xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = {
17454 - Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17457 -xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = {
17458 - Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17461 -xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = {
17462 - Opcode_idtlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17465 -xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = {
17466 - Opcode_pdtlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17469 -xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = {
17470 - Opcode_rdtlb0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17473 -xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = {
17474 - Opcode_rdtlb1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17477 -xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = {
17478 - Opcode_wdtlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17481 -xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = {
17482 - Opcode_iitlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17485 -xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = {
17486 - Opcode_pitlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17489 -xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = {
17490 - Opcode_ritlb0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17493 -xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = {
17494 - Opcode_ritlb1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17497 -xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = {
17498 - Opcode_witlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17501 -xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = {
17502 - Opcode_ldpte_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17505 -xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = {
17506 - Opcode_hwwitlba_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17509 -xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = {
17510 - Opcode_hwwdtlba_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17513 -xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = {
17514 - Opcode_rsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17517 -xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = {
17518 - Opcode_wsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17521 -xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = {
17522 - Opcode_xsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17525 -xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = {
17526 - Opcode_clamps_Slot_inst_encode, 0, 0, Opcode_clamps_Slot_xt_flix64_slot0_encode, Opcode_clamps_Slot_xt_flix64_slot0_encode, 0, 0, 0
17529 -xtensa_opcode_encode_fn Opcode_min_encode_fns[] = {
17530 - Opcode_min_Slot_inst_encode, 0, 0, Opcode_min_Slot_xt_flix64_slot0_encode, Opcode_min_Slot_xt_flix64_slot0_encode, 0, 0, 0
17533 -xtensa_opcode_encode_fn Opcode_max_encode_fns[] = {
17534 - Opcode_max_Slot_inst_encode, 0, 0, Opcode_max_Slot_xt_flix64_slot0_encode, Opcode_max_Slot_xt_flix64_slot0_encode, 0, 0, 0
17537 -xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = {
17538 - Opcode_minu_Slot_inst_encode, 0, 0, Opcode_minu_Slot_xt_flix64_slot0_encode, Opcode_minu_Slot_xt_flix64_slot0_encode, 0, 0, 0
17541 -xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = {
17542 - Opcode_maxu_Slot_inst_encode, 0, 0, Opcode_maxu_Slot_xt_flix64_slot0_encode, Opcode_maxu_Slot_xt_flix64_slot0_encode, 0, 0, 0
17545 -xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = {
17546 - Opcode_nsa_Slot_inst_encode, 0, 0, Opcode_nsa_Slot_xt_flix64_slot0_encode, Opcode_nsa_Slot_xt_flix64_slot0_encode, 0, 0, 0
17549 -xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = {
17550 - Opcode_nsau_Slot_inst_encode, 0, 0, Opcode_nsau_Slot_xt_flix64_slot0_encode, Opcode_nsau_Slot_xt_flix64_slot0_encode, 0, 0, 0
17553 -xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = {
17554 - Opcode_sext_Slot_inst_encode, 0, 0, Opcode_sext_Slot_xt_flix64_slot0_encode, Opcode_sext_Slot_xt_flix64_slot0_encode, Opcode_sext_Slot_xt_flix64_slot1_encode, Opcode_sext_Slot_xt_flix64_slot2_encode, 0
17557 -xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = {
17558 - Opcode_l32ai_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17561 -xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = {
17562 - Opcode_s32ri_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17565 -xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = {
17566 - Opcode_s32c1i_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17569 -xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = {
17570 - Opcode_rsr_scompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17573 -xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = {
17574 - Opcode_wsr_scompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17577 -xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = {
17578 - Opcode_xsr_scompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17581 -xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = {
17582 - Opcode_quou_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17585 -xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = {
17586 - Opcode_quos_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17589 -xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = {
17590 - Opcode_remu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17593 -xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = {
17594 - Opcode_rems_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17597 -xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = {
17598 - Opcode_mull_Slot_inst_encode, 0, 0, Opcode_mull_Slot_xt_flix64_slot0_encode, Opcode_mull_Slot_xt_flix64_slot0_encode, Opcode_mull_Slot_xt_flix64_slot1_encode, 0, 0
17601 -xtensa_opcode_encode_fn Opcode_muluh_encode_fns[] = {
17602 - Opcode_muluh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17605 -xtensa_opcode_encode_fn Opcode_mulsh_encode_fns[] = {
17606 - Opcode_mulsh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17609 -xtensa_opcode_encode_fn Opcode_rur_fcr_encode_fns[] = {
17610 - Opcode_rur_fcr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17613 -xtensa_opcode_encode_fn Opcode_wur_fcr_encode_fns[] = {
17614 - Opcode_wur_fcr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17617 -xtensa_opcode_encode_fn Opcode_rur_fsr_encode_fns[] = {
17618 - Opcode_rur_fsr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17621 -xtensa_opcode_encode_fn Opcode_wur_fsr_encode_fns[] = {
17622 - Opcode_wur_fsr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17625 -xtensa_opcode_encode_fn Opcode_add_s_encode_fns[] = {
17626 - Opcode_add_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17629 -xtensa_opcode_encode_fn Opcode_sub_s_encode_fns[] = {
17630 - Opcode_sub_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17633 -xtensa_opcode_encode_fn Opcode_mul_s_encode_fns[] = {
17634 - Opcode_mul_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17637 -xtensa_opcode_encode_fn Opcode_madd_s_encode_fns[] = {
17638 - Opcode_madd_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17641 -xtensa_opcode_encode_fn Opcode_msub_s_encode_fns[] = {
17642 - Opcode_msub_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17645 -xtensa_opcode_encode_fn Opcode_movf_s_encode_fns[] = {
17646 - Opcode_movf_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17649 -xtensa_opcode_encode_fn Opcode_movt_s_encode_fns[] = {
17650 - Opcode_movt_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17653 -xtensa_opcode_encode_fn Opcode_moveqz_s_encode_fns[] = {
17654 - Opcode_moveqz_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17657 -xtensa_opcode_encode_fn Opcode_movnez_s_encode_fns[] = {
17658 - Opcode_movnez_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17661 -xtensa_opcode_encode_fn Opcode_movltz_s_encode_fns[] = {
17662 - Opcode_movltz_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17665 -xtensa_opcode_encode_fn Opcode_movgez_s_encode_fns[] = {
17666 - Opcode_movgez_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17669 -xtensa_opcode_encode_fn Opcode_abs_s_encode_fns[] = {
17670 - Opcode_abs_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17673 -xtensa_opcode_encode_fn Opcode_mov_s_encode_fns[] = {
17674 - Opcode_mov_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17677 -xtensa_opcode_encode_fn Opcode_neg_s_encode_fns[] = {
17678 - Opcode_neg_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17681 -xtensa_opcode_encode_fn Opcode_un_s_encode_fns[] = {
17682 - Opcode_un_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17685 -xtensa_opcode_encode_fn Opcode_oeq_s_encode_fns[] = {
17686 - Opcode_oeq_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17689 -xtensa_opcode_encode_fn Opcode_ueq_s_encode_fns[] = {
17690 - Opcode_ueq_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17693 -xtensa_opcode_encode_fn Opcode_olt_s_encode_fns[] = {
17694 - Opcode_olt_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17697 -xtensa_opcode_encode_fn Opcode_ult_s_encode_fns[] = {
17698 - Opcode_ult_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17701 -xtensa_opcode_encode_fn Opcode_ole_s_encode_fns[] = {
17702 - Opcode_ole_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17705 -xtensa_opcode_encode_fn Opcode_ule_s_encode_fns[] = {
17706 - Opcode_ule_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17709 -xtensa_opcode_encode_fn Opcode_float_s_encode_fns[] = {
17710 - Opcode_float_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17713 -xtensa_opcode_encode_fn Opcode_ufloat_s_encode_fns[] = {
17714 - Opcode_ufloat_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17717 -xtensa_opcode_encode_fn Opcode_round_s_encode_fns[] = {
17718 - Opcode_round_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17721 -xtensa_opcode_encode_fn Opcode_ceil_s_encode_fns[] = {
17722 - Opcode_ceil_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17725 -xtensa_opcode_encode_fn Opcode_floor_s_encode_fns[] = {
17726 - Opcode_floor_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17729 -xtensa_opcode_encode_fn Opcode_trunc_s_encode_fns[] = {
17730 - Opcode_trunc_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17733 -xtensa_opcode_encode_fn Opcode_utrunc_s_encode_fns[] = {
17734 - Opcode_utrunc_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17737 -xtensa_opcode_encode_fn Opcode_rfr_encode_fns[] = {
17738 - Opcode_rfr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17741 -xtensa_opcode_encode_fn Opcode_wfr_encode_fns[] = {
17742 - Opcode_wfr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17745 -xtensa_opcode_encode_fn Opcode_lsi_encode_fns[] = {
17746 - Opcode_lsi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17749 -xtensa_opcode_encode_fn Opcode_lsiu_encode_fns[] = {
17750 - Opcode_lsiu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17753 -xtensa_opcode_encode_fn Opcode_lsx_encode_fns[] = {
17754 - Opcode_lsx_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17757 -xtensa_opcode_encode_fn Opcode_lsxu_encode_fns[] = {
17758 - Opcode_lsxu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17761 -xtensa_opcode_encode_fn Opcode_ssi_encode_fns[] = {
17762 - Opcode_ssi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17765 -xtensa_opcode_encode_fn Opcode_ssiu_encode_fns[] = {
17766 - Opcode_ssiu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17769 -xtensa_opcode_encode_fn Opcode_ssx_encode_fns[] = {
17770 - Opcode_ssx_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17773 -xtensa_opcode_encode_fn Opcode_ssxu_encode_fns[] = {
17774 - Opcode_ssxu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
17777 -xtensa_opcode_encode_fn Opcode_beqz_w18_encode_fns[] = {
17778 - 0, 0, 0, 0, 0, 0, 0, Opcode_beqz_w18_Slot_xt_flix64_slot3_encode
17781 -xtensa_opcode_encode_fn Opcode_bnez_w18_encode_fns[] = {
17782 - 0, 0, 0, 0, 0, 0, 0, Opcode_bnez_w18_Slot_xt_flix64_slot3_encode
17785 -xtensa_opcode_encode_fn Opcode_bgez_w18_encode_fns[] = {
17786 - 0, 0, 0, 0, 0, 0, 0, Opcode_bgez_w18_Slot_xt_flix64_slot3_encode
17789 -xtensa_opcode_encode_fn Opcode_bltz_w18_encode_fns[] = {
17790 - 0, 0, 0, 0, 0, 0, 0, Opcode_bltz_w18_Slot_xt_flix64_slot3_encode
17793 -xtensa_opcode_encode_fn Opcode_beqi_w18_encode_fns[] = {
17794 - 0, 0, 0, 0, 0, 0, 0, Opcode_beqi_w18_Slot_xt_flix64_slot3_encode
17797 -xtensa_opcode_encode_fn Opcode_bnei_w18_encode_fns[] = {
17798 - 0, 0, 0, 0, 0, 0, 0, Opcode_bnei_w18_Slot_xt_flix64_slot3_encode
17801 -xtensa_opcode_encode_fn Opcode_bgei_w18_encode_fns[] = {
17802 - 0, 0, 0, 0, 0, 0, 0, Opcode_bgei_w18_Slot_xt_flix64_slot3_encode
17805 -xtensa_opcode_encode_fn Opcode_blti_w18_encode_fns[] = {
17806 - 0, 0, 0, 0, 0, 0, 0, Opcode_blti_w18_Slot_xt_flix64_slot3_encode
17809 -xtensa_opcode_encode_fn Opcode_bgeui_w18_encode_fns[] = {
17810 - 0, 0, 0, 0, 0, 0, 0, Opcode_bgeui_w18_Slot_xt_flix64_slot3_encode
17813 -xtensa_opcode_encode_fn Opcode_bltui_w18_encode_fns[] = {
17814 - 0, 0, 0, 0, 0, 0, 0, Opcode_bltui_w18_Slot_xt_flix64_slot3_encode
17817 -xtensa_opcode_encode_fn Opcode_bbci_w18_encode_fns[] = {
17818 - 0, 0, 0, 0, 0, 0, 0, Opcode_bbci_w18_Slot_xt_flix64_slot3_encode
17821 -xtensa_opcode_encode_fn Opcode_bbsi_w18_encode_fns[] = {
17822 - 0, 0, 0, 0, 0, 0, 0, Opcode_bbsi_w18_Slot_xt_flix64_slot3_encode
17825 -xtensa_opcode_encode_fn Opcode_beq_w18_encode_fns[] = {
17826 - 0, 0, 0, 0, 0, 0, 0, Opcode_beq_w18_Slot_xt_flix64_slot3_encode
17829 -xtensa_opcode_encode_fn Opcode_bne_w18_encode_fns[] = {
17830 - 0, 0, 0, 0, 0, 0, 0, Opcode_bne_w18_Slot_xt_flix64_slot3_encode
17833 -xtensa_opcode_encode_fn Opcode_bge_w18_encode_fns[] = {
17834 - 0, 0, 0, 0, 0, 0, 0, Opcode_bge_w18_Slot_xt_flix64_slot3_encode
17837 -xtensa_opcode_encode_fn Opcode_blt_w18_encode_fns[] = {
17838 - 0, 0, 0, 0, 0, 0, 0, Opcode_blt_w18_Slot_xt_flix64_slot3_encode
17841 -xtensa_opcode_encode_fn Opcode_bgeu_w18_encode_fns[] = {
17842 - 0, 0, 0, 0, 0, 0, 0, Opcode_bgeu_w18_Slot_xt_flix64_slot3_encode
17845 -xtensa_opcode_encode_fn Opcode_bltu_w18_encode_fns[] = {
17846 - 0, 0, 0, 0, 0, 0, 0, Opcode_bltu_w18_Slot_xt_flix64_slot3_encode
17849 -xtensa_opcode_encode_fn Opcode_bany_w18_encode_fns[] = {
17850 - 0, 0, 0, 0, 0, 0, 0, Opcode_bany_w18_Slot_xt_flix64_slot3_encode
17853 -xtensa_opcode_encode_fn Opcode_bnone_w18_encode_fns[] = {
17854 - 0, 0, 0, 0, 0, 0, 0, Opcode_bnone_w18_Slot_xt_flix64_slot3_encode
17857 -xtensa_opcode_encode_fn Opcode_ball_w18_encode_fns[] = {
17858 - 0, 0, 0, 0, 0, 0, 0, Opcode_ball_w18_Slot_xt_flix64_slot3_encode
17861 -xtensa_opcode_encode_fn Opcode_bnall_w18_encode_fns[] = {
17862 - 0, 0, 0, 0, 0, 0, 0, Opcode_bnall_w18_Slot_xt_flix64_slot3_encode
17865 -xtensa_opcode_encode_fn Opcode_bbc_w18_encode_fns[] = {
17866 - 0, 0, 0, 0, 0, 0, 0, Opcode_bbc_w18_Slot_xt_flix64_slot3_encode
17869 -xtensa_opcode_encode_fn Opcode_bbs_w18_encode_fns[] = {
17870 - 0, 0, 0, 0, 0, 0, 0, Opcode_bbs_w18_Slot_xt_flix64_slot3_encode
17874 -/* Opcode table. */
17876 -static xtensa_opcode_internal opcodes[] = {
17877 - { "excw", 0 /* xt_iclass_excw */,
17879 - Opcode_excw_encode_fns, 0, 0 },
17880 - { "rfe", 1 /* xt_iclass_rfe */,
17881 - XTENSA_OPCODE_IS_JUMP,
17882 - Opcode_rfe_encode_fns, 0, 0 },
17883 - { "rfde", 2 /* xt_iclass_rfde */,
17884 - XTENSA_OPCODE_IS_JUMP,
17885 - Opcode_rfde_encode_fns, 0, 0 },
17886 - { "syscall", 3 /* xt_iclass_syscall */,
17888 - Opcode_syscall_encode_fns, 0, 0 },
17889 - { "simcall", 4 /* xt_iclass_simcall */,
17891 - Opcode_simcall_encode_fns, 0, 0 },
17892 - { "call12", 5 /* xt_iclass_call12 */,
17893 - XTENSA_OPCODE_IS_CALL,
17894 - Opcode_call12_encode_fns, 0, 0 },
17895 - { "call8", 6 /* xt_iclass_call8 */,
17896 - XTENSA_OPCODE_IS_CALL,
17897 - Opcode_call8_encode_fns, 0, 0 },
17898 - { "call4", 7 /* xt_iclass_call4 */,
17899 - XTENSA_OPCODE_IS_CALL,
17900 - Opcode_call4_encode_fns, 0, 0 },
17901 - { "callx12", 8 /* xt_iclass_callx12 */,
17902 - XTENSA_OPCODE_IS_CALL,
17903 - Opcode_callx12_encode_fns, 0, 0 },
17904 - { "callx8", 9 /* xt_iclass_callx8 */,
17905 - XTENSA_OPCODE_IS_CALL,
17906 - Opcode_callx8_encode_fns, 0, 0 },
17907 - { "callx4", 10 /* xt_iclass_callx4 */,
17908 - XTENSA_OPCODE_IS_CALL,
17909 - Opcode_callx4_encode_fns, 0, 0 },
17910 - { "entry", 11 /* xt_iclass_entry */,
17912 - Opcode_entry_encode_fns, 0, 0 },
17913 - { "movsp", 12 /* xt_iclass_movsp */,
17915 - Opcode_movsp_encode_fns, 0, 0 },
17916 - { "rotw", 13 /* xt_iclass_rotw */,
17918 - Opcode_rotw_encode_fns, 0, 0 },
17919 - { "retw", 14 /* xt_iclass_retw */,
17920 - XTENSA_OPCODE_IS_JUMP,
17921 - Opcode_retw_encode_fns, 0, 0 },
17922 - { "retw.n", 14 /* xt_iclass_retw */,
17923 - XTENSA_OPCODE_IS_JUMP,
17924 - Opcode_retw_n_encode_fns, 0, 0 },
17925 - { "rfwo", 15 /* xt_iclass_rfwou */,
17926 - XTENSA_OPCODE_IS_JUMP,
17927 - Opcode_rfwo_encode_fns, 0, 0 },
17928 - { "rfwu", 15 /* xt_iclass_rfwou */,
17929 - XTENSA_OPCODE_IS_JUMP,
17930 - Opcode_rfwu_encode_fns, 0, 0 },
17931 - { "l32e", 16 /* xt_iclass_l32e */,
17933 - Opcode_l32e_encode_fns, 0, 0 },
17934 - { "s32e", 17 /* xt_iclass_s32e */,
17936 - Opcode_s32e_encode_fns, 0, 0 },
17937 - { "rsr.windowbase", 18 /* xt_iclass_rsr.windowbase */,
17939 - Opcode_rsr_windowbase_encode_fns, 0, 0 },
17940 - { "wsr.windowbase", 19 /* xt_iclass_wsr.windowbase */,
17942 - Opcode_wsr_windowbase_encode_fns, 0, 0 },
17943 - { "xsr.windowbase", 20 /* xt_iclass_xsr.windowbase */,
17945 - Opcode_xsr_windowbase_encode_fns, 0, 0 },
17946 - { "rsr.windowstart", 21 /* xt_iclass_rsr.windowstart */,
17948 - Opcode_rsr_windowstart_encode_fns, 0, 0 },
17949 - { "wsr.windowstart", 22 /* xt_iclass_wsr.windowstart */,
17951 - Opcode_wsr_windowstart_encode_fns, 0, 0 },
17952 - { "xsr.windowstart", 23 /* xt_iclass_xsr.windowstart */,
17954 - Opcode_xsr_windowstart_encode_fns, 0, 0 },
17955 - { "add.n", 24 /* xt_iclass_add.n */,
17957 - Opcode_add_n_encode_fns, 0, 0 },
17958 - { "addi.n", 25 /* xt_iclass_addi.n */,
17960 - Opcode_addi_n_encode_fns, 0, 0 },
17961 - { "beqz.n", 26 /* xt_iclass_bz6 */,
17962 - XTENSA_OPCODE_IS_BRANCH,
17963 - Opcode_beqz_n_encode_fns, 0, 0 },
17964 - { "bnez.n", 26 /* xt_iclass_bz6 */,
17965 - XTENSA_OPCODE_IS_BRANCH,
17966 - Opcode_bnez_n_encode_fns, 0, 0 },
17967 - { "ill.n", 27 /* xt_iclass_ill.n */,
17969 - Opcode_ill_n_encode_fns, 0, 0 },
17970 - { "l32i.n", 28 /* xt_iclass_loadi4 */,
17972 - Opcode_l32i_n_encode_fns, 0, 0 },
17973 - { "mov.n", 29 /* xt_iclass_mov.n */,
17975 - Opcode_mov_n_encode_fns, 0, 0 },
17976 - { "movi.n", 30 /* xt_iclass_movi.n */,
17978 - Opcode_movi_n_encode_fns, 0, 0 },
17979 - { "nop.n", 31 /* xt_iclass_nopn */,
17981 - Opcode_nop_n_encode_fns, 0, 0 },
17982 - { "ret.n", 32 /* xt_iclass_retn */,
17983 - XTENSA_OPCODE_IS_JUMP,
17984 - Opcode_ret_n_encode_fns, 0, 0 },
17985 - { "s32i.n", 33 /* xt_iclass_storei4 */,
17987 - Opcode_s32i_n_encode_fns, 0, 0 },
17988 - { "rur.threadptr", 34 /* rur_threadptr */,
17990 - Opcode_rur_threadptr_encode_fns, 0, 0 },
17991 - { "wur.threadptr", 35 /* wur_threadptr */,
17993 - Opcode_wur_threadptr_encode_fns, 0, 0 },
17994 - { "addi", 36 /* xt_iclass_addi */,
17996 - Opcode_addi_encode_fns, 0, 0 },
17997 - { "addmi", 37 /* xt_iclass_addmi */,
17999 - Opcode_addmi_encode_fns, 0, 0 },
18000 - { "add", 38 /* xt_iclass_addsub */,
18002 - Opcode_add_encode_fns, 0, 0 },
18003 - { "sub", 38 /* xt_iclass_addsub */,
18005 - Opcode_sub_encode_fns, 0, 0 },
18006 - { "addx2", 38 /* xt_iclass_addsub */,
18008 - Opcode_addx2_encode_fns, 0, 0 },
18009 - { "addx4", 38 /* xt_iclass_addsub */,
18011 - Opcode_addx4_encode_fns, 0, 0 },
18012 - { "addx8", 38 /* xt_iclass_addsub */,
18014 - Opcode_addx8_encode_fns, 0, 0 },
18015 - { "subx2", 38 /* xt_iclass_addsub */,
18017 - Opcode_subx2_encode_fns, 0, 0 },
18018 - { "subx4", 38 /* xt_iclass_addsub */,
18020 - Opcode_subx4_encode_fns, 0, 0 },
18021 - { "subx8", 38 /* xt_iclass_addsub */,
18023 - Opcode_subx8_encode_fns, 0, 0 },
18024 - { "and", 39 /* xt_iclass_bit */,
18026 - Opcode_and_encode_fns, 0, 0 },
18027 - { "or", 39 /* xt_iclass_bit */,
18029 - Opcode_or_encode_fns, 0, 0 },
18030 - { "xor", 39 /* xt_iclass_bit */,
18032 - Opcode_xor_encode_fns, 0, 0 },
18033 - { "beqi", 40 /* xt_iclass_bsi8 */,
18034 - XTENSA_OPCODE_IS_BRANCH,
18035 - Opcode_beqi_encode_fns, 0, 0 },
18036 - { "bnei", 40 /* xt_iclass_bsi8 */,
18037 - XTENSA_OPCODE_IS_BRANCH,
18038 - Opcode_bnei_encode_fns, 0, 0 },
18039 - { "bgei", 40 /* xt_iclass_bsi8 */,
18040 - XTENSA_OPCODE_IS_BRANCH,
18041 - Opcode_bgei_encode_fns, 0, 0 },
18042 - { "blti", 40 /* xt_iclass_bsi8 */,
18043 - XTENSA_OPCODE_IS_BRANCH,
18044 - Opcode_blti_encode_fns, 0, 0 },
18045 - { "bbci", 41 /* xt_iclass_bsi8b */,
18046 - XTENSA_OPCODE_IS_BRANCH,
18047 - Opcode_bbci_encode_fns, 0, 0 },
18048 - { "bbsi", 41 /* xt_iclass_bsi8b */,
18049 - XTENSA_OPCODE_IS_BRANCH,
18050 - Opcode_bbsi_encode_fns, 0, 0 },
18051 - { "bgeui", 42 /* xt_iclass_bsi8u */,
18052 - XTENSA_OPCODE_IS_BRANCH,
18053 - Opcode_bgeui_encode_fns, 0, 0 },
18054 - { "bltui", 42 /* xt_iclass_bsi8u */,
18055 - XTENSA_OPCODE_IS_BRANCH,
18056 - Opcode_bltui_encode_fns, 0, 0 },
18057 - { "beq", 43 /* xt_iclass_bst8 */,
18058 - XTENSA_OPCODE_IS_BRANCH,
18059 - Opcode_beq_encode_fns, 0, 0 },
18060 - { "bne", 43 /* xt_iclass_bst8 */,
18061 - XTENSA_OPCODE_IS_BRANCH,
18062 - Opcode_bne_encode_fns, 0, 0 },
18063 - { "bge", 43 /* xt_iclass_bst8 */,
18064 - XTENSA_OPCODE_IS_BRANCH,
18065 - Opcode_bge_encode_fns, 0, 0 },
18066 - { "blt", 43 /* xt_iclass_bst8 */,
18067 - XTENSA_OPCODE_IS_BRANCH,
18068 - Opcode_blt_encode_fns, 0, 0 },
18069 - { "bgeu", 43 /* xt_iclass_bst8 */,
18070 - XTENSA_OPCODE_IS_BRANCH,
18071 - Opcode_bgeu_encode_fns, 0, 0 },
18072 - { "bltu", 43 /* xt_iclass_bst8 */,
18073 - XTENSA_OPCODE_IS_BRANCH,
18074 - Opcode_bltu_encode_fns, 0, 0 },
18075 - { "bany", 43 /* xt_iclass_bst8 */,
18076 - XTENSA_OPCODE_IS_BRANCH,
18077 - Opcode_bany_encode_fns, 0, 0 },
18078 - { "bnone", 43 /* xt_iclass_bst8 */,
18079 - XTENSA_OPCODE_IS_BRANCH,
18080 - Opcode_bnone_encode_fns, 0, 0 },
18081 - { "ball", 43 /* xt_iclass_bst8 */,
18082 - XTENSA_OPCODE_IS_BRANCH,
18083 - Opcode_ball_encode_fns, 0, 0 },
18084 - { "bnall", 43 /* xt_iclass_bst8 */,
18085 - XTENSA_OPCODE_IS_BRANCH,
18086 - Opcode_bnall_encode_fns, 0, 0 },
18087 - { "bbc", 43 /* xt_iclass_bst8 */,
18088 - XTENSA_OPCODE_IS_BRANCH,
18089 - Opcode_bbc_encode_fns, 0, 0 },
18090 - { "bbs", 43 /* xt_iclass_bst8 */,
18091 - XTENSA_OPCODE_IS_BRANCH,
18092 - Opcode_bbs_encode_fns, 0, 0 },
18093 - { "beqz", 44 /* xt_iclass_bsz12 */,
18094 - XTENSA_OPCODE_IS_BRANCH,
18095 - Opcode_beqz_encode_fns, 0, 0 },
18096 - { "bnez", 44 /* xt_iclass_bsz12 */,
18097 - XTENSA_OPCODE_IS_BRANCH,
18098 - Opcode_bnez_encode_fns, 0, 0 },
18099 - { "bgez", 44 /* xt_iclass_bsz12 */,
18100 - XTENSA_OPCODE_IS_BRANCH,
18101 - Opcode_bgez_encode_fns, 0, 0 },
18102 - { "bltz", 44 /* xt_iclass_bsz12 */,
18103 - XTENSA_OPCODE_IS_BRANCH,
18104 - Opcode_bltz_encode_fns, 0, 0 },
18105 - { "call0", 45 /* xt_iclass_call0 */,
18106 - XTENSA_OPCODE_IS_CALL,
18107 - Opcode_call0_encode_fns, 0, 0 },
18108 - { "callx0", 46 /* xt_iclass_callx0 */,
18109 - XTENSA_OPCODE_IS_CALL,
18110 - Opcode_callx0_encode_fns, 0, 0 },
18111 - { "extui", 47 /* xt_iclass_exti */,
18113 - Opcode_extui_encode_fns, 0, 0 },
18114 - { "ill", 48 /* xt_iclass_ill */,
18116 - Opcode_ill_encode_fns, 0, 0 },
18117 - { "j", 49 /* xt_iclass_jump */,
18118 - XTENSA_OPCODE_IS_JUMP,
18119 - Opcode_j_encode_fns, 0, 0 },
18120 - { "jx", 50 /* xt_iclass_jumpx */,
18121 - XTENSA_OPCODE_IS_JUMP,
18122 - Opcode_jx_encode_fns, 0, 0 },
18123 - { "l16ui", 51 /* xt_iclass_l16ui */,
18125 - Opcode_l16ui_encode_fns, 0, 0 },
18126 - { "l16si", 52 /* xt_iclass_l16si */,
18128 - Opcode_l16si_encode_fns, 0, 0 },
18129 - { "l32i", 53 /* xt_iclass_l32i */,
18131 - Opcode_l32i_encode_fns, 0, 0 },
18132 - { "l32r", 54 /* xt_iclass_l32r */,
18134 - Opcode_l32r_encode_fns, 0, 0 },
18135 - { "l8ui", 55 /* xt_iclass_l8i */,
18137 - Opcode_l8ui_encode_fns, 0, 0 },
18138 - { "loop", 56 /* xt_iclass_loop */,
18139 - XTENSA_OPCODE_IS_LOOP,
18140 - Opcode_loop_encode_fns, 0, 0 },
18141 - { "loopnez", 57 /* xt_iclass_loopz */,
18142 - XTENSA_OPCODE_IS_LOOP,
18143 - Opcode_loopnez_encode_fns, 0, 0 },
18144 - { "loopgtz", 57 /* xt_iclass_loopz */,
18145 - XTENSA_OPCODE_IS_LOOP,
18146 - Opcode_loopgtz_encode_fns, 0, 0 },
18147 - { "movi", 58 /* xt_iclass_movi */,
18149 - Opcode_movi_encode_fns, 0, 0 },
18150 - { "moveqz", 59 /* xt_iclass_movz */,
18152 - Opcode_moveqz_encode_fns, 0, 0 },
18153 - { "movnez", 59 /* xt_iclass_movz */,
18155 - Opcode_movnez_encode_fns, 0, 0 },
18156 - { "movltz", 59 /* xt_iclass_movz */,
18158 - Opcode_movltz_encode_fns, 0, 0 },
18159 - { "movgez", 59 /* xt_iclass_movz */,
18161 - Opcode_movgez_encode_fns, 0, 0 },
18162 - { "neg", 60 /* xt_iclass_neg */,
18164 - Opcode_neg_encode_fns, 0, 0 },
18165 - { "abs", 60 /* xt_iclass_neg */,
18167 - Opcode_abs_encode_fns, 0, 0 },
18168 - { "nop", 61 /* xt_iclass_nop */,
18170 - Opcode_nop_encode_fns, 0, 0 },
18171 - { "ret", 62 /* xt_iclass_return */,
18172 - XTENSA_OPCODE_IS_JUMP,
18173 - Opcode_ret_encode_fns, 0, 0 },
18174 - { "s16i", 63 /* xt_iclass_s16i */,
18176 - Opcode_s16i_encode_fns, 0, 0 },
18177 - { "s32i", 64 /* xt_iclass_s32i */,
18179 - Opcode_s32i_encode_fns, 0, 0 },
18180 - { "s8i", 65 /* xt_iclass_s8i */,
18182 - Opcode_s8i_encode_fns, 0, 0 },
18183 - { "ssr", 66 /* xt_iclass_sar */,
18185 - Opcode_ssr_encode_fns, 0, 0 },
18186 - { "ssl", 66 /* xt_iclass_sar */,
18188 - Opcode_ssl_encode_fns, 0, 0 },
18189 - { "ssa8l", 66 /* xt_iclass_sar */,
18191 - Opcode_ssa8l_encode_fns, 0, 0 },
18192 - { "ssa8b", 66 /* xt_iclass_sar */,
18194 - Opcode_ssa8b_encode_fns, 0, 0 },
18195 - { "ssai", 67 /* xt_iclass_sari */,
18197 - Opcode_ssai_encode_fns, 0, 0 },
18198 - { "sll", 68 /* xt_iclass_shifts */,
18200 - Opcode_sll_encode_fns, 0, 0 },
18201 - { "src", 69 /* xt_iclass_shiftst */,
18203 - Opcode_src_encode_fns, 0, 0 },
18204 - { "srl", 70 /* xt_iclass_shiftt */,
18206 - Opcode_srl_encode_fns, 0, 0 },
18207 - { "sra", 70 /* xt_iclass_shiftt */,
18209 - Opcode_sra_encode_fns, 0, 0 },
18210 - { "slli", 71 /* xt_iclass_slli */,
18212 - Opcode_slli_encode_fns, 0, 0 },
18213 - { "srai", 72 /* xt_iclass_srai */,
18215 - Opcode_srai_encode_fns, 0, 0 },
18216 - { "srli", 73 /* xt_iclass_srli */,
18218 - Opcode_srli_encode_fns, 0, 0 },
18219 - { "memw", 74 /* xt_iclass_memw */,
18221 - Opcode_memw_encode_fns, 0, 0 },
18222 - { "extw", 75 /* xt_iclass_extw */,
18224 - Opcode_extw_encode_fns, 0, 0 },
18225 - { "isync", 76 /* xt_iclass_isync */,
18227 - Opcode_isync_encode_fns, 0, 0 },
18228 - { "rsync", 77 /* xt_iclass_sync */,
18230 - Opcode_rsync_encode_fns, 0, 0 },
18231 - { "esync", 77 /* xt_iclass_sync */,
18233 - Opcode_esync_encode_fns, 0, 0 },
18234 - { "dsync", 77 /* xt_iclass_sync */,
18236 - Opcode_dsync_encode_fns, 0, 0 },
18237 - { "rsil", 78 /* xt_iclass_rsil */,
18239 - Opcode_rsil_encode_fns, 0, 0 },
18240 - { "rsr.lend", 79 /* xt_iclass_rsr.lend */,
18242 - Opcode_rsr_lend_encode_fns, 0, 0 },
18243 - { "wsr.lend", 80 /* xt_iclass_wsr.lend */,
18245 - Opcode_wsr_lend_encode_fns, 0, 0 },
18246 - { "xsr.lend", 81 /* xt_iclass_xsr.lend */,
18248 - Opcode_xsr_lend_encode_fns, 0, 0 },
18249 - { "rsr.lcount", 82 /* xt_iclass_rsr.lcount */,
18251 - Opcode_rsr_lcount_encode_fns, 0, 0 },
18252 - { "wsr.lcount", 83 /* xt_iclass_wsr.lcount */,
18254 - Opcode_wsr_lcount_encode_fns, 0, 0 },
18255 - { "xsr.lcount", 84 /* xt_iclass_xsr.lcount */,
18257 - Opcode_xsr_lcount_encode_fns, 0, 0 },
18258 - { "rsr.lbeg", 85 /* xt_iclass_rsr.lbeg */,
18260 - Opcode_rsr_lbeg_encode_fns, 0, 0 },
18261 - { "wsr.lbeg", 86 /* xt_iclass_wsr.lbeg */,
18263 - Opcode_wsr_lbeg_encode_fns, 0, 0 },
18264 - { "xsr.lbeg", 87 /* xt_iclass_xsr.lbeg */,
18266 - Opcode_xsr_lbeg_encode_fns, 0, 0 },
18267 - { "rsr.sar", 88 /* xt_iclass_rsr.sar */,
18269 - Opcode_rsr_sar_encode_fns, 0, 0 },
18270 - { "wsr.sar", 89 /* xt_iclass_wsr.sar */,
18272 - Opcode_wsr_sar_encode_fns, 0, 0 },
18273 - { "xsr.sar", 90 /* xt_iclass_xsr.sar */,
18275 - Opcode_xsr_sar_encode_fns, 0, 0 },
18276 - { "rsr.litbase", 91 /* xt_iclass_rsr.litbase */,
18278 - Opcode_rsr_litbase_encode_fns, 0, 0 },
18279 - { "wsr.litbase", 92 /* xt_iclass_wsr.litbase */,
18281 - Opcode_wsr_litbase_encode_fns, 0, 0 },
18282 - { "xsr.litbase", 93 /* xt_iclass_xsr.litbase */,
18284 - Opcode_xsr_litbase_encode_fns, 0, 0 },
18285 - { "rsr.176", 94 /* xt_iclass_rsr.176 */,
18287 - Opcode_rsr_176_encode_fns, 0, 0 },
18288 - { "rsr.208", 95 /* xt_iclass_rsr.208 */,
18290 - Opcode_rsr_208_encode_fns, 0, 0 },
18291 - { "rsr.ps", 96 /* xt_iclass_rsr.ps */,
18293 - Opcode_rsr_ps_encode_fns, 0, 0 },
18294 - { "wsr.ps", 97 /* xt_iclass_wsr.ps */,
18296 - Opcode_wsr_ps_encode_fns, 0, 0 },
18297 - { "xsr.ps", 98 /* xt_iclass_xsr.ps */,
18299 - Opcode_xsr_ps_encode_fns, 0, 0 },
18300 - { "rsr.epc1", 99 /* xt_iclass_rsr.epc1 */,
18302 - Opcode_rsr_epc1_encode_fns, 0, 0 },
18303 - { "wsr.epc1", 100 /* xt_iclass_wsr.epc1 */,
18305 - Opcode_wsr_epc1_encode_fns, 0, 0 },
18306 - { "xsr.epc1", 101 /* xt_iclass_xsr.epc1 */,
18308 - Opcode_xsr_epc1_encode_fns, 0, 0 },
18309 - { "rsr.excsave1", 102 /* xt_iclass_rsr.excsave1 */,
18311 - Opcode_rsr_excsave1_encode_fns, 0, 0 },
18312 - { "wsr.excsave1", 103 /* xt_iclass_wsr.excsave1 */,
18314 - Opcode_wsr_excsave1_encode_fns, 0, 0 },
18315 - { "xsr.excsave1", 104 /* xt_iclass_xsr.excsave1 */,
18317 - Opcode_xsr_excsave1_encode_fns, 0, 0 },
18318 - { "rsr.epc2", 105 /* xt_iclass_rsr.epc2 */,
18320 - Opcode_rsr_epc2_encode_fns, 0, 0 },
18321 - { "wsr.epc2", 106 /* xt_iclass_wsr.epc2 */,
18323 - Opcode_wsr_epc2_encode_fns, 0, 0 },
18324 - { "xsr.epc2", 107 /* xt_iclass_xsr.epc2 */,
18326 - Opcode_xsr_epc2_encode_fns, 0, 0 },
18327 - { "rsr.excsave2", 108 /* xt_iclass_rsr.excsave2 */,
18329 - Opcode_rsr_excsave2_encode_fns, 0, 0 },
18330 - { "wsr.excsave2", 109 /* xt_iclass_wsr.excsave2 */,
18332 - Opcode_wsr_excsave2_encode_fns, 0, 0 },
18333 - { "xsr.excsave2", 110 /* xt_iclass_xsr.excsave2 */,
18335 - Opcode_xsr_excsave2_encode_fns, 0, 0 },
18336 - { "rsr.epc3", 111 /* xt_iclass_rsr.epc3 */,
18338 - Opcode_rsr_epc3_encode_fns, 0, 0 },
18339 - { "wsr.epc3", 112 /* xt_iclass_wsr.epc3 */,
18341 - Opcode_wsr_epc3_encode_fns, 0, 0 },
18342 - { "xsr.epc3", 113 /* xt_iclass_xsr.epc3 */,
18344 - Opcode_xsr_epc3_encode_fns, 0, 0 },
18345 - { "rsr.excsave3", 114 /* xt_iclass_rsr.excsave3 */,
18347 - Opcode_rsr_excsave3_encode_fns, 0, 0 },
18348 - { "wsr.excsave3", 115 /* xt_iclass_wsr.excsave3 */,
18350 - Opcode_wsr_excsave3_encode_fns, 0, 0 },
18351 - { "xsr.excsave3", 116 /* xt_iclass_xsr.excsave3 */,
18353 - Opcode_xsr_excsave3_encode_fns, 0, 0 },
18354 - { "rsr.epc4", 117 /* xt_iclass_rsr.epc4 */,
18356 - Opcode_rsr_epc4_encode_fns, 0, 0 },
18357 - { "wsr.epc4", 118 /* xt_iclass_wsr.epc4 */,
18359 - Opcode_wsr_epc4_encode_fns, 0, 0 },
18360 - { "xsr.epc4", 119 /* xt_iclass_xsr.epc4 */,
18362 - Opcode_xsr_epc4_encode_fns, 0, 0 },
18363 - { "rsr.excsave4", 120 /* xt_iclass_rsr.excsave4 */,
18365 - Opcode_rsr_excsave4_encode_fns, 0, 0 },
18366 - { "wsr.excsave4", 121 /* xt_iclass_wsr.excsave4 */,
18368 - Opcode_wsr_excsave4_encode_fns, 0, 0 },
18369 - { "xsr.excsave4", 122 /* xt_iclass_xsr.excsave4 */,
18371 - Opcode_xsr_excsave4_encode_fns, 0, 0 },
18372 - { "rsr.epc5", 123 /* xt_iclass_rsr.epc5 */,
18374 - Opcode_rsr_epc5_encode_fns, 0, 0 },
18375 - { "wsr.epc5", 124 /* xt_iclass_wsr.epc5 */,
18377 - Opcode_wsr_epc5_encode_fns, 0, 0 },
18378 - { "xsr.epc5", 125 /* xt_iclass_xsr.epc5 */,
18380 - Opcode_xsr_epc5_encode_fns, 0, 0 },
18381 - { "rsr.excsave5", 126 /* xt_iclass_rsr.excsave5 */,
18383 - Opcode_rsr_excsave5_encode_fns, 0, 0 },
18384 - { "wsr.excsave5", 127 /* xt_iclass_wsr.excsave5 */,
18386 - Opcode_wsr_excsave5_encode_fns, 0, 0 },
18387 - { "xsr.excsave5", 128 /* xt_iclass_xsr.excsave5 */,
18389 - Opcode_xsr_excsave5_encode_fns, 0, 0 },
18390 - { "rsr.epc6", 129 /* xt_iclass_rsr.epc6 */,
18392 - Opcode_rsr_epc6_encode_fns, 0, 0 },
18393 - { "wsr.epc6", 130 /* xt_iclass_wsr.epc6 */,
18395 - Opcode_wsr_epc6_encode_fns, 0, 0 },
18396 - { "xsr.epc6", 131 /* xt_iclass_xsr.epc6 */,
18398 - Opcode_xsr_epc6_encode_fns, 0, 0 },
18399 - { "rsr.excsave6", 132 /* xt_iclass_rsr.excsave6 */,
18401 - Opcode_rsr_excsave6_encode_fns, 0, 0 },
18402 - { "wsr.excsave6", 133 /* xt_iclass_wsr.excsave6 */,
18404 - Opcode_wsr_excsave6_encode_fns, 0, 0 },
18405 - { "xsr.excsave6", 134 /* xt_iclass_xsr.excsave6 */,
18407 - Opcode_xsr_excsave6_encode_fns, 0, 0 },
18408 - { "rsr.epc7", 135 /* xt_iclass_rsr.epc7 */,
18410 - Opcode_rsr_epc7_encode_fns, 0, 0 },
18411 - { "wsr.epc7", 136 /* xt_iclass_wsr.epc7 */,
18413 - Opcode_wsr_epc7_encode_fns, 0, 0 },
18414 - { "xsr.epc7", 137 /* xt_iclass_xsr.epc7 */,
18416 - Opcode_xsr_epc7_encode_fns, 0, 0 },
18417 - { "rsr.excsave7", 138 /* xt_iclass_rsr.excsave7 */,
18419 - Opcode_rsr_excsave7_encode_fns, 0, 0 },
18420 - { "wsr.excsave7", 139 /* xt_iclass_wsr.excsave7 */,
18422 - Opcode_wsr_excsave7_encode_fns, 0, 0 },
18423 - { "xsr.excsave7", 140 /* xt_iclass_xsr.excsave7 */,
18425 - Opcode_xsr_excsave7_encode_fns, 0, 0 },
18426 - { "rsr.eps2", 141 /* xt_iclass_rsr.eps2 */,
18428 - Opcode_rsr_eps2_encode_fns, 0, 0 },
18429 - { "wsr.eps2", 142 /* xt_iclass_wsr.eps2 */,
18431 - Opcode_wsr_eps2_encode_fns, 0, 0 },
18432 - { "xsr.eps2", 143 /* xt_iclass_xsr.eps2 */,
18434 - Opcode_xsr_eps2_encode_fns, 0, 0 },
18435 - { "rsr.eps3", 144 /* xt_iclass_rsr.eps3 */,
18437 - Opcode_rsr_eps3_encode_fns, 0, 0 },
18438 - { "wsr.eps3", 145 /* xt_iclass_wsr.eps3 */,
18440 - Opcode_wsr_eps3_encode_fns, 0, 0 },
18441 - { "xsr.eps3", 146 /* xt_iclass_xsr.eps3 */,
18443 - Opcode_xsr_eps3_encode_fns, 0, 0 },
18444 - { "rsr.eps4", 147 /* xt_iclass_rsr.eps4 */,
18446 - Opcode_rsr_eps4_encode_fns, 0, 0 },
18447 - { "wsr.eps4", 148 /* xt_iclass_wsr.eps4 */,
18449 - Opcode_wsr_eps4_encode_fns, 0, 0 },
18450 - { "xsr.eps4", 149 /* xt_iclass_xsr.eps4 */,
18452 - Opcode_xsr_eps4_encode_fns, 0, 0 },
18453 - { "rsr.eps5", 150 /* xt_iclass_rsr.eps5 */,
18455 - Opcode_rsr_eps5_encode_fns, 0, 0 },
18456 - { "wsr.eps5", 151 /* xt_iclass_wsr.eps5 */,
18458 - Opcode_wsr_eps5_encode_fns, 0, 0 },
18459 - { "xsr.eps5", 152 /* xt_iclass_xsr.eps5 */,
18461 - Opcode_xsr_eps5_encode_fns, 0, 0 },
18462 - { "rsr.eps6", 153 /* xt_iclass_rsr.eps6 */,
18464 - Opcode_rsr_eps6_encode_fns, 0, 0 },
18465 - { "wsr.eps6", 154 /* xt_iclass_wsr.eps6 */,
18467 - Opcode_wsr_eps6_encode_fns, 0, 0 },
18468 - { "xsr.eps6", 155 /* xt_iclass_xsr.eps6 */,
18470 - Opcode_xsr_eps6_encode_fns, 0, 0 },
18471 - { "rsr.eps7", 156 /* xt_iclass_rsr.eps7 */,
18473 - Opcode_rsr_eps7_encode_fns, 0, 0 },
18474 - { "wsr.eps7", 157 /* xt_iclass_wsr.eps7 */,
18476 - Opcode_wsr_eps7_encode_fns, 0, 0 },
18477 - { "xsr.eps7", 158 /* xt_iclass_xsr.eps7 */,
18479 - Opcode_xsr_eps7_encode_fns, 0, 0 },
18480 - { "rsr.excvaddr", 159 /* xt_iclass_rsr.excvaddr */,
18482 - Opcode_rsr_excvaddr_encode_fns, 0, 0 },
18483 - { "wsr.excvaddr", 160 /* xt_iclass_wsr.excvaddr */,
18485 - Opcode_wsr_excvaddr_encode_fns, 0, 0 },
18486 - { "xsr.excvaddr", 161 /* xt_iclass_xsr.excvaddr */,
18488 - Opcode_xsr_excvaddr_encode_fns, 0, 0 },
18489 - { "rsr.depc", 162 /* xt_iclass_rsr.depc */,
18491 - Opcode_rsr_depc_encode_fns, 0, 0 },
18492 - { "wsr.depc", 163 /* xt_iclass_wsr.depc */,
18494 - Opcode_wsr_depc_encode_fns, 0, 0 },
18495 - { "xsr.depc", 164 /* xt_iclass_xsr.depc */,
18497 - Opcode_xsr_depc_encode_fns, 0, 0 },
18498 - { "rsr.exccause", 165 /* xt_iclass_rsr.exccause */,
18500 - Opcode_rsr_exccause_encode_fns, 0, 0 },
18501 - { "wsr.exccause", 166 /* xt_iclass_wsr.exccause */,
18503 - Opcode_wsr_exccause_encode_fns, 0, 0 },
18504 - { "xsr.exccause", 167 /* xt_iclass_xsr.exccause */,
18506 - Opcode_xsr_exccause_encode_fns, 0, 0 },
18507 - { "rsr.misc0", 168 /* xt_iclass_rsr.misc0 */,
18509 - Opcode_rsr_misc0_encode_fns, 0, 0 },
18510 - { "wsr.misc0", 169 /* xt_iclass_wsr.misc0 */,
18512 - Opcode_wsr_misc0_encode_fns, 0, 0 },
18513 - { "xsr.misc0", 170 /* xt_iclass_xsr.misc0 */,
18515 - Opcode_xsr_misc0_encode_fns, 0, 0 },
18516 - { "rsr.misc1", 171 /* xt_iclass_rsr.misc1 */,
18518 - Opcode_rsr_misc1_encode_fns, 0, 0 },
18519 - { "wsr.misc1", 172 /* xt_iclass_wsr.misc1 */,
18521 - Opcode_wsr_misc1_encode_fns, 0, 0 },
18522 - { "xsr.misc1", 173 /* xt_iclass_xsr.misc1 */,
18524 - Opcode_xsr_misc1_encode_fns, 0, 0 },
18525 - { "rsr.misc2", 174 /* xt_iclass_rsr.misc2 */,
18527 - Opcode_rsr_misc2_encode_fns, 0, 0 },
18528 - { "wsr.misc2", 175 /* xt_iclass_wsr.misc2 */,
18530 - Opcode_wsr_misc2_encode_fns, 0, 0 },
18531 - { "xsr.misc2", 176 /* xt_iclass_xsr.misc2 */,
18533 - Opcode_xsr_misc2_encode_fns, 0, 0 },
18534 - { "rsr.misc3", 177 /* xt_iclass_rsr.misc3 */,
18536 - Opcode_rsr_misc3_encode_fns, 0, 0 },
18537 - { "wsr.misc3", 178 /* xt_iclass_wsr.misc3 */,
18539 - Opcode_wsr_misc3_encode_fns, 0, 0 },
18540 - { "xsr.misc3", 179 /* xt_iclass_xsr.misc3 */,
18542 - Opcode_xsr_misc3_encode_fns, 0, 0 },
18543 - { "rsr.prid", 180 /* xt_iclass_rsr.prid */,
18545 - Opcode_rsr_prid_encode_fns, 0, 0 },
18546 - { "rsr.vecbase", 181 /* xt_iclass_rsr.vecbase */,
18548 - Opcode_rsr_vecbase_encode_fns, 0, 0 },
18549 - { "wsr.vecbase", 182 /* xt_iclass_wsr.vecbase */,
18551 - Opcode_wsr_vecbase_encode_fns, 0, 0 },
18552 - { "xsr.vecbase", 183 /* xt_iclass_xsr.vecbase */,
18554 - Opcode_xsr_vecbase_encode_fns, 0, 0 },
18555 - { "mul.aa.ll", 184 /* xt_iclass_mac16_aa */,
18557 - Opcode_mul_aa_ll_encode_fns, 0, 0 },
18558 - { "mul.aa.hl", 184 /* xt_iclass_mac16_aa */,
18560 - Opcode_mul_aa_hl_encode_fns, 0, 0 },
18561 - { "mul.aa.lh", 184 /* xt_iclass_mac16_aa */,
18563 - Opcode_mul_aa_lh_encode_fns, 0, 0 },
18564 - { "mul.aa.hh", 184 /* xt_iclass_mac16_aa */,
18566 - Opcode_mul_aa_hh_encode_fns, 0, 0 },
18567 - { "umul.aa.ll", 184 /* xt_iclass_mac16_aa */,
18569 - Opcode_umul_aa_ll_encode_fns, 0, 0 },
18570 - { "umul.aa.hl", 184 /* xt_iclass_mac16_aa */,
18572 - Opcode_umul_aa_hl_encode_fns, 0, 0 },
18573 - { "umul.aa.lh", 184 /* xt_iclass_mac16_aa */,
18575 - Opcode_umul_aa_lh_encode_fns, 0, 0 },
18576 - { "umul.aa.hh", 184 /* xt_iclass_mac16_aa */,
18578 - Opcode_umul_aa_hh_encode_fns, 0, 0 },
18579 - { "mul.ad.ll", 185 /* xt_iclass_mac16_ad */,
18581 - Opcode_mul_ad_ll_encode_fns, 0, 0 },
18582 - { "mul.ad.hl", 185 /* xt_iclass_mac16_ad */,
18584 - Opcode_mul_ad_hl_encode_fns, 0, 0 },
18585 - { "mul.ad.lh", 185 /* xt_iclass_mac16_ad */,
18587 - Opcode_mul_ad_lh_encode_fns, 0, 0 },
18588 - { "mul.ad.hh", 185 /* xt_iclass_mac16_ad */,
18590 - Opcode_mul_ad_hh_encode_fns, 0, 0 },
18591 - { "mul.da.ll", 186 /* xt_iclass_mac16_da */,
18593 - Opcode_mul_da_ll_encode_fns, 0, 0 },
18594 - { "mul.da.hl", 186 /* xt_iclass_mac16_da */,
18596 - Opcode_mul_da_hl_encode_fns, 0, 0 },
18597 - { "mul.da.lh", 186 /* xt_iclass_mac16_da */,
18599 - Opcode_mul_da_lh_encode_fns, 0, 0 },
18600 - { "mul.da.hh", 186 /* xt_iclass_mac16_da */,
18602 - Opcode_mul_da_hh_encode_fns, 0, 0 },
18603 - { "mul.dd.ll", 187 /* xt_iclass_mac16_dd */,
18605 - Opcode_mul_dd_ll_encode_fns, 0, 0 },
18606 - { "mul.dd.hl", 187 /* xt_iclass_mac16_dd */,
18608 - Opcode_mul_dd_hl_encode_fns, 0, 0 },
18609 - { "mul.dd.lh", 187 /* xt_iclass_mac16_dd */,
18611 - Opcode_mul_dd_lh_encode_fns, 0, 0 },
18612 - { "mul.dd.hh", 187 /* xt_iclass_mac16_dd */,
18614 - Opcode_mul_dd_hh_encode_fns, 0, 0 },
18615 - { "mula.aa.ll", 188 /* xt_iclass_mac16a_aa */,
18617 - Opcode_mula_aa_ll_encode_fns, 0, 0 },
18618 - { "mula.aa.hl", 188 /* xt_iclass_mac16a_aa */,
18620 - Opcode_mula_aa_hl_encode_fns, 0, 0 },
18621 - { "mula.aa.lh", 188 /* xt_iclass_mac16a_aa */,
18623 - Opcode_mula_aa_lh_encode_fns, 0, 0 },
18624 - { "mula.aa.hh", 188 /* xt_iclass_mac16a_aa */,
18626 - Opcode_mula_aa_hh_encode_fns, 0, 0 },
18627 - { "muls.aa.ll", 188 /* xt_iclass_mac16a_aa */,
18629 - Opcode_muls_aa_ll_encode_fns, 0, 0 },
18630 - { "muls.aa.hl", 188 /* xt_iclass_mac16a_aa */,
18632 - Opcode_muls_aa_hl_encode_fns, 0, 0 },
18633 - { "muls.aa.lh", 188 /* xt_iclass_mac16a_aa */,
18635 - Opcode_muls_aa_lh_encode_fns, 0, 0 },
18636 - { "muls.aa.hh", 188 /* xt_iclass_mac16a_aa */,
18638 - Opcode_muls_aa_hh_encode_fns, 0, 0 },
18639 - { "mula.ad.ll", 189 /* xt_iclass_mac16a_ad */,
18641 - Opcode_mula_ad_ll_encode_fns, 0, 0 },
18642 - { "mula.ad.hl", 189 /* xt_iclass_mac16a_ad */,
18644 - Opcode_mula_ad_hl_encode_fns, 0, 0 },
18645 - { "mula.ad.lh", 189 /* xt_iclass_mac16a_ad */,
18647 - Opcode_mula_ad_lh_encode_fns, 0, 0 },
18648 - { "mula.ad.hh", 189 /* xt_iclass_mac16a_ad */,
18650 - Opcode_mula_ad_hh_encode_fns, 0, 0 },
18651 - { "muls.ad.ll", 189 /* xt_iclass_mac16a_ad */,
18653 - Opcode_muls_ad_ll_encode_fns, 0, 0 },
18654 - { "muls.ad.hl", 189 /* xt_iclass_mac16a_ad */,
18656 - Opcode_muls_ad_hl_encode_fns, 0, 0 },
18657 - { "muls.ad.lh", 189 /* xt_iclass_mac16a_ad */,
18659 - Opcode_muls_ad_lh_encode_fns, 0, 0 },
18660 - { "muls.ad.hh", 189 /* xt_iclass_mac16a_ad */,
18662 - Opcode_muls_ad_hh_encode_fns, 0, 0 },
18663 - { "mula.da.ll", 190 /* xt_iclass_mac16a_da */,
18665 - Opcode_mula_da_ll_encode_fns, 0, 0 },
18666 - { "mula.da.hl", 190 /* xt_iclass_mac16a_da */,
18668 - Opcode_mula_da_hl_encode_fns, 0, 0 },
18669 - { "mula.da.lh", 190 /* xt_iclass_mac16a_da */,
18671 - Opcode_mula_da_lh_encode_fns, 0, 0 },
18672 - { "mula.da.hh", 190 /* xt_iclass_mac16a_da */,
18674 - Opcode_mula_da_hh_encode_fns, 0, 0 },
18675 - { "muls.da.ll", 190 /* xt_iclass_mac16a_da */,
18677 - Opcode_muls_da_ll_encode_fns, 0, 0 },
18678 - { "muls.da.hl", 190 /* xt_iclass_mac16a_da */,
18680 - Opcode_muls_da_hl_encode_fns, 0, 0 },
18681 - { "muls.da.lh", 190 /* xt_iclass_mac16a_da */,
18683 - Opcode_muls_da_lh_encode_fns, 0, 0 },
18684 - { "muls.da.hh", 190 /* xt_iclass_mac16a_da */,
18686 - Opcode_muls_da_hh_encode_fns, 0, 0 },
18687 - { "mula.dd.ll", 191 /* xt_iclass_mac16a_dd */,
18689 - Opcode_mula_dd_ll_encode_fns, 0, 0 },
18690 - { "mula.dd.hl", 191 /* xt_iclass_mac16a_dd */,
18692 - Opcode_mula_dd_hl_encode_fns, 0, 0 },
18693 - { "mula.dd.lh", 191 /* xt_iclass_mac16a_dd */,
18695 - Opcode_mula_dd_lh_encode_fns, 0, 0 },
18696 - { "mula.dd.hh", 191 /* xt_iclass_mac16a_dd */,
18698 - Opcode_mula_dd_hh_encode_fns, 0, 0 },
18699 - { "muls.dd.ll", 191 /* xt_iclass_mac16a_dd */,
18701 - Opcode_muls_dd_ll_encode_fns, 0, 0 },
18702 - { "muls.dd.hl", 191 /* xt_iclass_mac16a_dd */,
18704 - Opcode_muls_dd_hl_encode_fns, 0, 0 },
18705 - { "muls.dd.lh", 191 /* xt_iclass_mac16a_dd */,
18707 - Opcode_muls_dd_lh_encode_fns, 0, 0 },
18708 - { "muls.dd.hh", 191 /* xt_iclass_mac16a_dd */,
18710 - Opcode_muls_dd_hh_encode_fns, 0, 0 },
18711 - { "mula.da.ll.lddec", 192 /* xt_iclass_mac16al_da */,
18713 - Opcode_mula_da_ll_lddec_encode_fns, 0, 0 },
18714 - { "mula.da.ll.ldinc", 192 /* xt_iclass_mac16al_da */,
18716 - Opcode_mula_da_ll_ldinc_encode_fns, 0, 0 },
18717 - { "mula.da.hl.lddec", 192 /* xt_iclass_mac16al_da */,
18719 - Opcode_mula_da_hl_lddec_encode_fns, 0, 0 },
18720 - { "mula.da.hl.ldinc", 192 /* xt_iclass_mac16al_da */,
18722 - Opcode_mula_da_hl_ldinc_encode_fns, 0, 0 },
18723 - { "mula.da.lh.lddec", 192 /* xt_iclass_mac16al_da */,
18725 - Opcode_mula_da_lh_lddec_encode_fns, 0, 0 },
18726 - { "mula.da.lh.ldinc", 192 /* xt_iclass_mac16al_da */,
18728 - Opcode_mula_da_lh_ldinc_encode_fns, 0, 0 },
18729 - { "mula.da.hh.lddec", 192 /* xt_iclass_mac16al_da */,
18731 - Opcode_mula_da_hh_lddec_encode_fns, 0, 0 },
18732 - { "mula.da.hh.ldinc", 192 /* xt_iclass_mac16al_da */,
18734 - Opcode_mula_da_hh_ldinc_encode_fns, 0, 0 },
18735 - { "mula.dd.ll.lddec", 193 /* xt_iclass_mac16al_dd */,
18737 - Opcode_mula_dd_ll_lddec_encode_fns, 0, 0 },
18738 - { "mula.dd.ll.ldinc", 193 /* xt_iclass_mac16al_dd */,
18740 - Opcode_mula_dd_ll_ldinc_encode_fns, 0, 0 },
18741 - { "mula.dd.hl.lddec", 193 /* xt_iclass_mac16al_dd */,
18743 - Opcode_mula_dd_hl_lddec_encode_fns, 0, 0 },
18744 - { "mula.dd.hl.ldinc", 193 /* xt_iclass_mac16al_dd */,
18746 - Opcode_mula_dd_hl_ldinc_encode_fns, 0, 0 },
18747 - { "mula.dd.lh.lddec", 193 /* xt_iclass_mac16al_dd */,
18749 - Opcode_mula_dd_lh_lddec_encode_fns, 0, 0 },
18750 - { "mula.dd.lh.ldinc", 193 /* xt_iclass_mac16al_dd */,
18752 - Opcode_mula_dd_lh_ldinc_encode_fns, 0, 0 },
18753 - { "mula.dd.hh.lddec", 193 /* xt_iclass_mac16al_dd */,
18755 - Opcode_mula_dd_hh_lddec_encode_fns, 0, 0 },
18756 - { "mula.dd.hh.ldinc", 193 /* xt_iclass_mac16al_dd */,
18758 - Opcode_mula_dd_hh_ldinc_encode_fns, 0, 0 },
18759 - { "lddec", 194 /* xt_iclass_mac16_l */,
18761 - Opcode_lddec_encode_fns, 0, 0 },
18762 - { "ldinc", 194 /* xt_iclass_mac16_l */,
18764 - Opcode_ldinc_encode_fns, 0, 0 },
18765 - { "mul16u", 195 /* xt_iclass_mul16 */,
18767 - Opcode_mul16u_encode_fns, 0, 0 },
18768 - { "mul16s", 195 /* xt_iclass_mul16 */,
18770 - Opcode_mul16s_encode_fns, 0, 0 },
18771 - { "rsr.m0", 196 /* xt_iclass_rsr.m0 */,
18773 - Opcode_rsr_m0_encode_fns, 0, 0 },
18774 - { "wsr.m0", 197 /* xt_iclass_wsr.m0 */,
18776 - Opcode_wsr_m0_encode_fns, 0, 0 },
18777 - { "xsr.m0", 198 /* xt_iclass_xsr.m0 */,
18779 - Opcode_xsr_m0_encode_fns, 0, 0 },
18780 - { "rsr.m1", 199 /* xt_iclass_rsr.m1 */,
18782 - Opcode_rsr_m1_encode_fns, 0, 0 },
18783 - { "wsr.m1", 200 /* xt_iclass_wsr.m1 */,
18785 - Opcode_wsr_m1_encode_fns, 0, 0 },
18786 - { "xsr.m1", 201 /* xt_iclass_xsr.m1 */,
18788 - Opcode_xsr_m1_encode_fns, 0, 0 },
18789 - { "rsr.m2", 202 /* xt_iclass_rsr.m2 */,
18791 - Opcode_rsr_m2_encode_fns, 0, 0 },
18792 - { "wsr.m2", 203 /* xt_iclass_wsr.m2 */,
18794 - Opcode_wsr_m2_encode_fns, 0, 0 },
18795 - { "xsr.m2", 204 /* xt_iclass_xsr.m2 */,
18797 - Opcode_xsr_m2_encode_fns, 0, 0 },
18798 - { "rsr.m3", 205 /* xt_iclass_rsr.m3 */,
18800 - Opcode_rsr_m3_encode_fns, 0, 0 },
18801 - { "wsr.m3", 206 /* xt_iclass_wsr.m3 */,
18803 - Opcode_wsr_m3_encode_fns, 0, 0 },
18804 - { "xsr.m3", 207 /* xt_iclass_xsr.m3 */,
18806 - Opcode_xsr_m3_encode_fns, 0, 0 },
18807 - { "rsr.acclo", 208 /* xt_iclass_rsr.acclo */,
18809 - Opcode_rsr_acclo_encode_fns, 0, 0 },
18810 - { "wsr.acclo", 209 /* xt_iclass_wsr.acclo */,
18812 - Opcode_wsr_acclo_encode_fns, 0, 0 },
18813 - { "xsr.acclo", 210 /* xt_iclass_xsr.acclo */,
18815 - Opcode_xsr_acclo_encode_fns, 0, 0 },
18816 - { "rsr.acchi", 211 /* xt_iclass_rsr.acchi */,
18818 - Opcode_rsr_acchi_encode_fns, 0, 0 },
18819 - { "wsr.acchi", 212 /* xt_iclass_wsr.acchi */,
18821 - Opcode_wsr_acchi_encode_fns, 0, 0 },
18822 - { "xsr.acchi", 213 /* xt_iclass_xsr.acchi */,
18824 - Opcode_xsr_acchi_encode_fns, 0, 0 },
18825 - { "rfi", 214 /* xt_iclass_rfi */,
18826 - XTENSA_OPCODE_IS_JUMP,
18827 - Opcode_rfi_encode_fns, 0, 0 },
18828 - { "waiti", 215 /* xt_iclass_wait */,
18830 - Opcode_waiti_encode_fns, 0, 0 },
18831 - { "rsr.interrupt", 216 /* xt_iclass_rsr.interrupt */,
18833 - Opcode_rsr_interrupt_encode_fns, 0, 0 },
18834 - { "wsr.intset", 217 /* xt_iclass_wsr.intset */,
18836 - Opcode_wsr_intset_encode_fns, 0, 0 },
18837 - { "wsr.intclear", 218 /* xt_iclass_wsr.intclear */,
18839 - Opcode_wsr_intclear_encode_fns, 0, 0 },
18840 - { "rsr.intenable", 219 /* xt_iclass_rsr.intenable */,
18842 - Opcode_rsr_intenable_encode_fns, 0, 0 },
18843 - { "wsr.intenable", 220 /* xt_iclass_wsr.intenable */,
18845 - Opcode_wsr_intenable_encode_fns, 0, 0 },
18846 - { "xsr.intenable", 221 /* xt_iclass_xsr.intenable */,
18848 - Opcode_xsr_intenable_encode_fns, 0, 0 },
18849 - { "break", 222 /* xt_iclass_break */,
18851 - Opcode_break_encode_fns, 0, 0 },
18852 - { "break.n", 223 /* xt_iclass_break.n */,
18854 - Opcode_break_n_encode_fns, 0, 0 },
18855 - { "rsr.dbreaka0", 224 /* xt_iclass_rsr.dbreaka0 */,
18857 - Opcode_rsr_dbreaka0_encode_fns, 0, 0 },
18858 - { "wsr.dbreaka0", 225 /* xt_iclass_wsr.dbreaka0 */,
18860 - Opcode_wsr_dbreaka0_encode_fns, 0, 0 },
18861 - { "xsr.dbreaka0", 226 /* xt_iclass_xsr.dbreaka0 */,
18863 - Opcode_xsr_dbreaka0_encode_fns, 0, 0 },
18864 - { "rsr.dbreakc0", 227 /* xt_iclass_rsr.dbreakc0 */,
18866 - Opcode_rsr_dbreakc0_encode_fns, 0, 0 },
18867 - { "wsr.dbreakc0", 228 /* xt_iclass_wsr.dbreakc0 */,
18869 - Opcode_wsr_dbreakc0_encode_fns, 0, 0 },
18870 - { "xsr.dbreakc0", 229 /* xt_iclass_xsr.dbreakc0 */,
18872 - Opcode_xsr_dbreakc0_encode_fns, 0, 0 },
18873 - { "rsr.dbreaka1", 230 /* xt_iclass_rsr.dbreaka1 */,
18875 - Opcode_rsr_dbreaka1_encode_fns, 0, 0 },
18876 - { "wsr.dbreaka1", 231 /* xt_iclass_wsr.dbreaka1 */,
18878 - Opcode_wsr_dbreaka1_encode_fns, 0, 0 },
18879 - { "xsr.dbreaka1", 232 /* xt_iclass_xsr.dbreaka1 */,
18881 - Opcode_xsr_dbreaka1_encode_fns, 0, 0 },
18882 - { "rsr.dbreakc1", 233 /* xt_iclass_rsr.dbreakc1 */,
18884 - Opcode_rsr_dbreakc1_encode_fns, 0, 0 },
18885 - { "wsr.dbreakc1", 234 /* xt_iclass_wsr.dbreakc1 */,
18887 - Opcode_wsr_dbreakc1_encode_fns, 0, 0 },
18888 - { "xsr.dbreakc1", 235 /* xt_iclass_xsr.dbreakc1 */,
18890 - Opcode_xsr_dbreakc1_encode_fns, 0, 0 },
18891 - { "rsr.ibreaka0", 236 /* xt_iclass_rsr.ibreaka0 */,
18893 - Opcode_rsr_ibreaka0_encode_fns, 0, 0 },
18894 - { "wsr.ibreaka0", 237 /* xt_iclass_wsr.ibreaka0 */,
18896 - Opcode_wsr_ibreaka0_encode_fns, 0, 0 },
18897 - { "xsr.ibreaka0", 238 /* xt_iclass_xsr.ibreaka0 */,
18899 - Opcode_xsr_ibreaka0_encode_fns, 0, 0 },
18900 - { "rsr.ibreaka1", 239 /* xt_iclass_rsr.ibreaka1 */,
18902 - Opcode_rsr_ibreaka1_encode_fns, 0, 0 },
18903 - { "wsr.ibreaka1", 240 /* xt_iclass_wsr.ibreaka1 */,
18905 - Opcode_wsr_ibreaka1_encode_fns, 0, 0 },
18906 - { "xsr.ibreaka1", 241 /* xt_iclass_xsr.ibreaka1 */,
18908 - Opcode_xsr_ibreaka1_encode_fns, 0, 0 },
18909 - { "rsr.ibreakenable", 242 /* xt_iclass_rsr.ibreakenable */,
18911 - Opcode_rsr_ibreakenable_encode_fns, 0, 0 },
18912 - { "wsr.ibreakenable", 243 /* xt_iclass_wsr.ibreakenable */,
18914 - Opcode_wsr_ibreakenable_encode_fns, 0, 0 },
18915 - { "xsr.ibreakenable", 244 /* xt_iclass_xsr.ibreakenable */,
18917 - Opcode_xsr_ibreakenable_encode_fns, 0, 0 },
18918 - { "rsr.debugcause", 245 /* xt_iclass_rsr.debugcause */,
18920 - Opcode_rsr_debugcause_encode_fns, 0, 0 },
18921 - { "wsr.debugcause", 246 /* xt_iclass_wsr.debugcause */,
18923 - Opcode_wsr_debugcause_encode_fns, 0, 0 },
18924 - { "xsr.debugcause", 247 /* xt_iclass_xsr.debugcause */,
18926 - Opcode_xsr_debugcause_encode_fns, 0, 0 },
18927 - { "rsr.icount", 248 /* xt_iclass_rsr.icount */,
18929 - Opcode_rsr_icount_encode_fns, 0, 0 },
18930 - { "wsr.icount", 249 /* xt_iclass_wsr.icount */,
18932 - Opcode_wsr_icount_encode_fns, 0, 0 },
18933 - { "xsr.icount", 250 /* xt_iclass_xsr.icount */,
18935 - Opcode_xsr_icount_encode_fns, 0, 0 },
18936 - { "rsr.icountlevel", 251 /* xt_iclass_rsr.icountlevel */,
18938 - Opcode_rsr_icountlevel_encode_fns, 0, 0 },
18939 - { "wsr.icountlevel", 252 /* xt_iclass_wsr.icountlevel */,
18941 - Opcode_wsr_icountlevel_encode_fns, 0, 0 },
18942 - { "xsr.icountlevel", 253 /* xt_iclass_xsr.icountlevel */,
18944 - Opcode_xsr_icountlevel_encode_fns, 0, 0 },
18945 - { "rsr.ddr", 254 /* xt_iclass_rsr.ddr */,
18947 - Opcode_rsr_ddr_encode_fns, 0, 0 },
18948 - { "wsr.ddr", 255 /* xt_iclass_wsr.ddr */,
18950 - Opcode_wsr_ddr_encode_fns, 0, 0 },
18951 - { "xsr.ddr", 256 /* xt_iclass_xsr.ddr */,
18953 - Opcode_xsr_ddr_encode_fns, 0, 0 },
18954 - { "rfdo", 257 /* xt_iclass_rfdo */,
18955 - XTENSA_OPCODE_IS_JUMP,
18956 - Opcode_rfdo_encode_fns, 0, 0 },
18957 - { "rfdd", 258 /* xt_iclass_rfdd */,
18958 - XTENSA_OPCODE_IS_JUMP,
18959 - Opcode_rfdd_encode_fns, 0, 0 },
18960 - { "wsr.mmid", 259 /* xt_iclass_wsr.mmid */,
18962 - Opcode_wsr_mmid_encode_fns, 0, 0 },
18963 - { "andb", 260 /* xt_iclass_bbool1 */,
18965 - Opcode_andb_encode_fns, 0, 0 },
18966 - { "andbc", 260 /* xt_iclass_bbool1 */,
18968 - Opcode_andbc_encode_fns, 0, 0 },
18969 - { "orb", 260 /* xt_iclass_bbool1 */,
18971 - Opcode_orb_encode_fns, 0, 0 },
18972 - { "orbc", 260 /* xt_iclass_bbool1 */,
18974 - Opcode_orbc_encode_fns, 0, 0 },
18975 - { "xorb", 260 /* xt_iclass_bbool1 */,
18977 - Opcode_xorb_encode_fns, 0, 0 },
18978 - { "any4", 261 /* xt_iclass_bbool4 */,
18980 - Opcode_any4_encode_fns, 0, 0 },
18981 - { "all4", 261 /* xt_iclass_bbool4 */,
18983 - Opcode_all4_encode_fns, 0, 0 },
18984 - { "any8", 262 /* xt_iclass_bbool8 */,
18986 - Opcode_any8_encode_fns, 0, 0 },
18987 - { "all8", 262 /* xt_iclass_bbool8 */,
18989 - Opcode_all8_encode_fns, 0, 0 },
18990 - { "bf", 263 /* xt_iclass_bbranch */,
18991 - XTENSA_OPCODE_IS_BRANCH,
18992 - Opcode_bf_encode_fns, 0, 0 },
18993 - { "bt", 263 /* xt_iclass_bbranch */,
18994 - XTENSA_OPCODE_IS_BRANCH,
18995 - Opcode_bt_encode_fns, 0, 0 },
18996 - { "movf", 264 /* xt_iclass_bmove */,
18998 - Opcode_movf_encode_fns, 0, 0 },
18999 - { "movt", 264 /* xt_iclass_bmove */,
19001 - Opcode_movt_encode_fns, 0, 0 },
19002 - { "rsr.br", 265 /* xt_iclass_RSR.BR */,
19004 - Opcode_rsr_br_encode_fns, 0, 0 },
19005 - { "wsr.br", 266 /* xt_iclass_WSR.BR */,
19007 - Opcode_wsr_br_encode_fns, 0, 0 },
19008 - { "xsr.br", 267 /* xt_iclass_XSR.BR */,
19010 - Opcode_xsr_br_encode_fns, 0, 0 },
19011 - { "rsr.ccount", 268 /* xt_iclass_rsr.ccount */,
19013 - Opcode_rsr_ccount_encode_fns, 0, 0 },
19014 - { "wsr.ccount", 269 /* xt_iclass_wsr.ccount */,
19016 - Opcode_wsr_ccount_encode_fns, 0, 0 },
19017 - { "xsr.ccount", 270 /* xt_iclass_xsr.ccount */,
19019 - Opcode_xsr_ccount_encode_fns, 0, 0 },
19020 - { "rsr.ccompare0", 271 /* xt_iclass_rsr.ccompare0 */,
19022 - Opcode_rsr_ccompare0_encode_fns, 0, 0 },
19023 - { "wsr.ccompare0", 272 /* xt_iclass_wsr.ccompare0 */,
19025 - Opcode_wsr_ccompare0_encode_fns, 0, 0 },
19026 - { "xsr.ccompare0", 273 /* xt_iclass_xsr.ccompare0 */,
19028 - Opcode_xsr_ccompare0_encode_fns, 0, 0 },
19029 - { "rsr.ccompare1", 274 /* xt_iclass_rsr.ccompare1 */,
19031 - Opcode_rsr_ccompare1_encode_fns, 0, 0 },
19032 - { "wsr.ccompare1", 275 /* xt_iclass_wsr.ccompare1 */,
19034 - Opcode_wsr_ccompare1_encode_fns, 0, 0 },
19035 - { "xsr.ccompare1", 276 /* xt_iclass_xsr.ccompare1 */,
19037 - Opcode_xsr_ccompare1_encode_fns, 0, 0 },
19038 - { "rsr.ccompare2", 277 /* xt_iclass_rsr.ccompare2 */,
19040 - Opcode_rsr_ccompare2_encode_fns, 0, 0 },
19041 - { "wsr.ccompare2", 278 /* xt_iclass_wsr.ccompare2 */,
19043 - Opcode_wsr_ccompare2_encode_fns, 0, 0 },
19044 - { "xsr.ccompare2", 279 /* xt_iclass_xsr.ccompare2 */,
19046 - Opcode_xsr_ccompare2_encode_fns, 0, 0 },
19047 - { "ipf", 280 /* xt_iclass_icache */,
19049 - Opcode_ipf_encode_fns, 0, 0 },
19050 - { "ihi", 280 /* xt_iclass_icache */,
19052 - Opcode_ihi_encode_fns, 0, 0 },
19053 - { "ipfl", 281 /* xt_iclass_icache_lock */,
19055 - Opcode_ipfl_encode_fns, 0, 0 },
19056 - { "ihu", 281 /* xt_iclass_icache_lock */,
19058 - Opcode_ihu_encode_fns, 0, 0 },
19059 - { "iiu", 281 /* xt_iclass_icache_lock */,
19061 - Opcode_iiu_encode_fns, 0, 0 },
19062 - { "iii", 282 /* xt_iclass_icache_inv */,
19064 - Opcode_iii_encode_fns, 0, 0 },
19065 - { "lict", 283 /* xt_iclass_licx */,
19067 - Opcode_lict_encode_fns, 0, 0 },
19068 - { "licw", 283 /* xt_iclass_licx */,
19070 - Opcode_licw_encode_fns, 0, 0 },
19071 - { "sict", 284 /* xt_iclass_sicx */,
19073 - Opcode_sict_encode_fns, 0, 0 },
19074 - { "sicw", 284 /* xt_iclass_sicx */,
19076 - Opcode_sicw_encode_fns, 0, 0 },
19077 - { "dhwb", 285 /* xt_iclass_dcache */,
19079 - Opcode_dhwb_encode_fns, 0, 0 },
19080 - { "dhwbi", 285 /* xt_iclass_dcache */,
19082 - Opcode_dhwbi_encode_fns, 0, 0 },
19083 - { "diwb", 286 /* xt_iclass_dcache_ind */,
19085 - Opcode_diwb_encode_fns, 0, 0 },
19086 - { "diwbi", 286 /* xt_iclass_dcache_ind */,
19088 - Opcode_diwbi_encode_fns, 0, 0 },
19089 - { "dhi", 287 /* xt_iclass_dcache_inv */,
19091 - Opcode_dhi_encode_fns, 0, 0 },
19092 - { "dii", 287 /* xt_iclass_dcache_inv */,
19094 - Opcode_dii_encode_fns, 0, 0 },
19095 - { "dpfr", 288 /* xt_iclass_dpf */,
19097 - Opcode_dpfr_encode_fns, 0, 0 },
19098 - { "dpfw", 288 /* xt_iclass_dpf */,
19100 - Opcode_dpfw_encode_fns, 0, 0 },
19101 - { "dpfro", 288 /* xt_iclass_dpf */,
19103 - Opcode_dpfro_encode_fns, 0, 0 },
19104 - { "dpfwo", 288 /* xt_iclass_dpf */,
19106 - Opcode_dpfwo_encode_fns, 0, 0 },
19107 - { "dpfl", 289 /* xt_iclass_dcache_lock */,
19109 - Opcode_dpfl_encode_fns, 0, 0 },
19110 - { "dhu", 289 /* xt_iclass_dcache_lock */,
19112 - Opcode_dhu_encode_fns, 0, 0 },
19113 - { "diu", 289 /* xt_iclass_dcache_lock */,
19115 - Opcode_diu_encode_fns, 0, 0 },
19116 - { "sdct", 290 /* xt_iclass_sdct */,
19118 - Opcode_sdct_encode_fns, 0, 0 },
19119 - { "ldct", 291 /* xt_iclass_ldct */,
19121 - Opcode_ldct_encode_fns, 0, 0 },
19122 - { "wsr.ptevaddr", 292 /* xt_iclass_wsr.ptevaddr */,
19124 - Opcode_wsr_ptevaddr_encode_fns, 0, 0 },
19125 - { "rsr.ptevaddr", 293 /* xt_iclass_rsr.ptevaddr */,
19127 - Opcode_rsr_ptevaddr_encode_fns, 0, 0 },
19128 - { "xsr.ptevaddr", 294 /* xt_iclass_xsr.ptevaddr */,
19130 - Opcode_xsr_ptevaddr_encode_fns, 0, 0 },
19131 - { "rsr.rasid", 295 /* xt_iclass_rsr.rasid */,
19133 - Opcode_rsr_rasid_encode_fns, 0, 0 },
19134 - { "wsr.rasid", 296 /* xt_iclass_wsr.rasid */,
19136 - Opcode_wsr_rasid_encode_fns, 0, 0 },
19137 - { "xsr.rasid", 297 /* xt_iclass_xsr.rasid */,
19139 - Opcode_xsr_rasid_encode_fns, 0, 0 },
19140 - { "rsr.itlbcfg", 298 /* xt_iclass_rsr.itlbcfg */,
19142 - Opcode_rsr_itlbcfg_encode_fns, 0, 0 },
19143 - { "wsr.itlbcfg", 299 /* xt_iclass_wsr.itlbcfg */,
19145 - Opcode_wsr_itlbcfg_encode_fns, 0, 0 },
19146 - { "xsr.itlbcfg", 300 /* xt_iclass_xsr.itlbcfg */,
19148 - Opcode_xsr_itlbcfg_encode_fns, 0, 0 },
19149 - { "rsr.dtlbcfg", 301 /* xt_iclass_rsr.dtlbcfg */,
19151 - Opcode_rsr_dtlbcfg_encode_fns, 0, 0 },
19152 - { "wsr.dtlbcfg", 302 /* xt_iclass_wsr.dtlbcfg */,
19154 - Opcode_wsr_dtlbcfg_encode_fns, 0, 0 },
19155 - { "xsr.dtlbcfg", 303 /* xt_iclass_xsr.dtlbcfg */,
19157 - Opcode_xsr_dtlbcfg_encode_fns, 0, 0 },
19158 - { "idtlb", 304 /* xt_iclass_idtlb */,
19160 - Opcode_idtlb_encode_fns, 0, 0 },
19161 - { "pdtlb", 305 /* xt_iclass_rdtlb */,
19163 - Opcode_pdtlb_encode_fns, 0, 0 },
19164 - { "rdtlb0", 305 /* xt_iclass_rdtlb */,
19166 - Opcode_rdtlb0_encode_fns, 0, 0 },
19167 - { "rdtlb1", 305 /* xt_iclass_rdtlb */,
19169 - Opcode_rdtlb1_encode_fns, 0, 0 },
19170 - { "wdtlb", 306 /* xt_iclass_wdtlb */,
19172 - Opcode_wdtlb_encode_fns, 0, 0 },
19173 - { "iitlb", 307 /* xt_iclass_iitlb */,
19175 - Opcode_iitlb_encode_fns, 0, 0 },
19176 - { "pitlb", 308 /* xt_iclass_ritlb */,
19178 - Opcode_pitlb_encode_fns, 0, 0 },
19179 - { "ritlb0", 308 /* xt_iclass_ritlb */,
19181 - Opcode_ritlb0_encode_fns, 0, 0 },
19182 - { "ritlb1", 308 /* xt_iclass_ritlb */,
19184 - Opcode_ritlb1_encode_fns, 0, 0 },
19185 - { "witlb", 309 /* xt_iclass_witlb */,
19187 - Opcode_witlb_encode_fns, 0, 0 },
19188 - { "ldpte", 310 /* xt_iclass_ldpte */,
19190 - Opcode_ldpte_encode_fns, 0, 0 },
19191 - { "hwwitlba", 311 /* xt_iclass_hwwitlba */,
19192 - XTENSA_OPCODE_IS_BRANCH,
19193 - Opcode_hwwitlba_encode_fns, 0, 0 },
19194 - { "hwwdtlba", 312 /* xt_iclass_hwwdtlba */,
19196 - Opcode_hwwdtlba_encode_fns, 0, 0 },
19197 - { "rsr.cpenable", 313 /* xt_iclass_rsr.cpenable */,
19199 - Opcode_rsr_cpenable_encode_fns, 0, 0 },
19200 - { "wsr.cpenable", 314 /* xt_iclass_wsr.cpenable */,
19202 - Opcode_wsr_cpenable_encode_fns, 0, 0 },
19203 - { "xsr.cpenable", 315 /* xt_iclass_xsr.cpenable */,
19205 - Opcode_xsr_cpenable_encode_fns, 0, 0 },
19206 - { "clamps", 316 /* xt_iclass_clamp */,
19208 - Opcode_clamps_encode_fns, 0, 0 },
19209 - { "min", 317 /* xt_iclass_minmax */,
19211 - Opcode_min_encode_fns, 0, 0 },
19212 - { "max", 317 /* xt_iclass_minmax */,
19214 - Opcode_max_encode_fns, 0, 0 },
19215 - { "minu", 317 /* xt_iclass_minmax */,
19217 - Opcode_minu_encode_fns, 0, 0 },
19218 - { "maxu", 317 /* xt_iclass_minmax */,
19220 - Opcode_maxu_encode_fns, 0, 0 },
19221 - { "nsa", 318 /* xt_iclass_nsa */,
19223 - Opcode_nsa_encode_fns, 0, 0 },
19224 - { "nsau", 318 /* xt_iclass_nsa */,
19226 - Opcode_nsau_encode_fns, 0, 0 },
19227 - { "sext", 319 /* xt_iclass_sx */,
19229 - Opcode_sext_encode_fns, 0, 0 },
19230 - { "l32ai", 320 /* xt_iclass_l32ai */,
19232 - Opcode_l32ai_encode_fns, 0, 0 },
19233 - { "s32ri", 321 /* xt_iclass_s32ri */,
19235 - Opcode_s32ri_encode_fns, 0, 0 },
19236 - { "s32c1i", 322 /* xt_iclass_s32c1i */,
19238 - Opcode_s32c1i_encode_fns, 0, 0 },
19239 - { "rsr.scompare1", 323 /* xt_iclass_rsr.scompare1 */,
19241 - Opcode_rsr_scompare1_encode_fns, 0, 0 },
19242 - { "wsr.scompare1", 324 /* xt_iclass_wsr.scompare1 */,
19244 - Opcode_wsr_scompare1_encode_fns, 0, 0 },
19245 - { "xsr.scompare1", 325 /* xt_iclass_xsr.scompare1 */,
19247 - Opcode_xsr_scompare1_encode_fns, 0, 0 },
19248 - { "quou", 326 /* xt_iclass_div */,
19250 - Opcode_quou_encode_fns, 0, 0 },
19251 - { "quos", 326 /* xt_iclass_div */,
19253 - Opcode_quos_encode_fns, 0, 0 },
19254 - { "remu", 326 /* xt_iclass_div */,
19256 - Opcode_remu_encode_fns, 0, 0 },
19257 - { "rems", 326 /* xt_iclass_div */,
19259 - Opcode_rems_encode_fns, 0, 0 },
19260 - { "mull", 327 /* xt_mul32 */,
19262 - Opcode_mull_encode_fns, 0, 0 },
19263 - { "muluh", 327 /* xt_mul32 */,
19265 - Opcode_muluh_encode_fns, 0, 0 },
19266 - { "mulsh", 327 /* xt_mul32 */,
19268 - Opcode_mulsh_encode_fns, 0, 0 },
19269 - { "rur.fcr", 328 /* rur_fcr */,
19271 - Opcode_rur_fcr_encode_fns, 0, 0 },
19272 - { "wur.fcr", 329 /* wur_fcr */,
19274 - Opcode_wur_fcr_encode_fns, 0, 0 },
19275 - { "rur.fsr", 330 /* rur_fsr */,
19277 - Opcode_rur_fsr_encode_fns, 0, 0 },
19278 - { "wur.fsr", 331 /* wur_fsr */,
19280 - Opcode_wur_fsr_encode_fns, 0, 0 },
19281 - { "add.s", 332 /* fp */,
19283 - Opcode_add_s_encode_fns, 0, 0 },
19284 - { "sub.s", 332 /* fp */,
19286 - Opcode_sub_s_encode_fns, 0, 0 },
19287 - { "mul.s", 332 /* fp */,
19289 - Opcode_mul_s_encode_fns, 0, 0 },
19290 - { "madd.s", 333 /* fp_mac */,
19292 - Opcode_madd_s_encode_fns, 0, 0 },
19293 - { "msub.s", 333 /* fp_mac */,
19295 - Opcode_msub_s_encode_fns, 0, 0 },
19296 - { "movf.s", 334 /* fp_cmov */,
19298 - Opcode_movf_s_encode_fns, 0, 0 },
19299 - { "movt.s", 334 /* fp_cmov */,
19301 - Opcode_movt_s_encode_fns, 0, 0 },
19302 - { "moveqz.s", 335 /* fp_mov */,
19304 - Opcode_moveqz_s_encode_fns, 0, 0 },
19305 - { "movnez.s", 335 /* fp_mov */,
19307 - Opcode_movnez_s_encode_fns, 0, 0 },
19308 - { "movltz.s", 335 /* fp_mov */,
19310 - Opcode_movltz_s_encode_fns, 0, 0 },
19311 - { "movgez.s", 335 /* fp_mov */,
19313 - Opcode_movgez_s_encode_fns, 0, 0 },
19314 - { "abs.s", 336 /* fp_mov2 */,
19316 - Opcode_abs_s_encode_fns, 0, 0 },
19317 - { "mov.s", 336 /* fp_mov2 */,
19319 - Opcode_mov_s_encode_fns, 0, 0 },
19320 - { "neg.s", 336 /* fp_mov2 */,
19322 - Opcode_neg_s_encode_fns, 0, 0 },
19323 - { "un.s", 337 /* fp_cmp */,
19325 - Opcode_un_s_encode_fns, 0, 0 },
19326 - { "oeq.s", 337 /* fp_cmp */,
19328 - Opcode_oeq_s_encode_fns, 0, 0 },
19329 - { "ueq.s", 337 /* fp_cmp */,
19331 - Opcode_ueq_s_encode_fns, 0, 0 },
19332 - { "olt.s", 337 /* fp_cmp */,
19334 - Opcode_olt_s_encode_fns, 0, 0 },
19335 - { "ult.s", 337 /* fp_cmp */,
19337 - Opcode_ult_s_encode_fns, 0, 0 },
19338 - { "ole.s", 337 /* fp_cmp */,
19340 - Opcode_ole_s_encode_fns, 0, 0 },
19341 - { "ule.s", 337 /* fp_cmp */,
19343 - Opcode_ule_s_encode_fns, 0, 0 },
19344 - { "float.s", 338 /* fp_float */,
19346 - Opcode_float_s_encode_fns, 0, 0 },
19347 - { "ufloat.s", 338 /* fp_float */,
19349 - Opcode_ufloat_s_encode_fns, 0, 0 },
19350 - { "round.s", 339 /* fp_int */,
19352 - Opcode_round_s_encode_fns, 0, 0 },
19353 - { "ceil.s", 339 /* fp_int */,
19355 - Opcode_ceil_s_encode_fns, 0, 0 },
19356 - { "floor.s", 339 /* fp_int */,
19358 - Opcode_floor_s_encode_fns, 0, 0 },
19359 - { "trunc.s", 339 /* fp_int */,
19361 - Opcode_trunc_s_encode_fns, 0, 0 },
19362 - { "utrunc.s", 339 /* fp_int */,
19364 - Opcode_utrunc_s_encode_fns, 0, 0 },
19365 - { "rfr", 340 /* fp_rfr */,
19367 - Opcode_rfr_encode_fns, 0, 0 },
19368 - { "wfr", 341 /* fp_wfr */,
19370 - Opcode_wfr_encode_fns, 0, 0 },
19371 - { "lsi", 342 /* fp_lsi */,
19373 - Opcode_lsi_encode_fns, 0, 0 },
19374 - { "lsiu", 343 /* fp_lsiu */,
19376 - Opcode_lsiu_encode_fns, 0, 0 },
19377 - { "lsx", 344 /* fp_lsx */,
19379 - Opcode_lsx_encode_fns, 0, 0 },
19380 - { "lsxu", 345 /* fp_lsxu */,
19382 - Opcode_lsxu_encode_fns, 0, 0 },
19383 - { "ssi", 346 /* fp_ssi */,
19385 - Opcode_ssi_encode_fns, 0, 0 },
19386 - { "ssiu", 347 /* fp_ssiu */,
19388 - Opcode_ssiu_encode_fns, 0, 0 },
19389 - { "ssx", 348 /* fp_ssx */,
19391 - Opcode_ssx_encode_fns, 0, 0 },
19392 - { "ssxu", 349 /* fp_ssxu */,
19394 - Opcode_ssxu_encode_fns, 0, 0 },
19395 - { "beqz.w18", 350 /* xt_iclass_wb18_0 */,
19396 - XTENSA_OPCODE_IS_BRANCH,
19397 - Opcode_beqz_w18_encode_fns, 0, 0 },
19398 - { "bnez.w18", 350 /* xt_iclass_wb18_0 */,
19399 - XTENSA_OPCODE_IS_BRANCH,
19400 - Opcode_bnez_w18_encode_fns, 0, 0 },
19401 - { "bgez.w18", 350 /* xt_iclass_wb18_0 */,
19402 - XTENSA_OPCODE_IS_BRANCH,
19403 - Opcode_bgez_w18_encode_fns, 0, 0 },
19404 - { "bltz.w18", 350 /* xt_iclass_wb18_0 */,
19405 - XTENSA_OPCODE_IS_BRANCH,
19406 - Opcode_bltz_w18_encode_fns, 0, 0 },
19407 - { "beqi.w18", 351 /* xt_iclass_wb18_1 */,
19408 - XTENSA_OPCODE_IS_BRANCH,
19409 - Opcode_beqi_w18_encode_fns, 0, 0 },
19410 - { "bnei.w18", 351 /* xt_iclass_wb18_1 */,
19411 - XTENSA_OPCODE_IS_BRANCH,
19412 - Opcode_bnei_w18_encode_fns, 0, 0 },
19413 - { "bgei.w18", 351 /* xt_iclass_wb18_1 */,
19414 - XTENSA_OPCODE_IS_BRANCH,
19415 - Opcode_bgei_w18_encode_fns, 0, 0 },
19416 - { "blti.w18", 351 /* xt_iclass_wb18_1 */,
19417 - XTENSA_OPCODE_IS_BRANCH,
19418 - Opcode_blti_w18_encode_fns, 0, 0 },
19419 - { "bgeui.w18", 352 /* xt_iclass_wb18_2 */,
19420 - XTENSA_OPCODE_IS_BRANCH,
19421 - Opcode_bgeui_w18_encode_fns, 0, 0 },
19422 - { "bltui.w18", 352 /* xt_iclass_wb18_2 */,
19423 - XTENSA_OPCODE_IS_BRANCH,
19424 - Opcode_bltui_w18_encode_fns, 0, 0 },
19425 - { "bbci.w18", 353 /* xt_iclass_wb18_3 */,
19426 - XTENSA_OPCODE_IS_BRANCH,
19427 - Opcode_bbci_w18_encode_fns, 0, 0 },
19428 - { "bbsi.w18", 353 /* xt_iclass_wb18_3 */,
19429 - XTENSA_OPCODE_IS_BRANCH,
19430 - Opcode_bbsi_w18_encode_fns, 0, 0 },
19431 - { "beq.w18", 354 /* xt_iclass_wb18_4 */,
19432 - XTENSA_OPCODE_IS_BRANCH,
19433 - Opcode_beq_w18_encode_fns, 0, 0 },
19434 - { "bne.w18", 354 /* xt_iclass_wb18_4 */,
19435 - XTENSA_OPCODE_IS_BRANCH,
19436 - Opcode_bne_w18_encode_fns, 0, 0 },
19437 - { "bge.w18", 354 /* xt_iclass_wb18_4 */,
19438 - XTENSA_OPCODE_IS_BRANCH,
19439 - Opcode_bge_w18_encode_fns, 0, 0 },
19440 - { "blt.w18", 354 /* xt_iclass_wb18_4 */,
19441 - XTENSA_OPCODE_IS_BRANCH,
19442 - Opcode_blt_w18_encode_fns, 0, 0 },
19443 - { "bgeu.w18", 354 /* xt_iclass_wb18_4 */,
19444 - XTENSA_OPCODE_IS_BRANCH,
19445 - Opcode_bgeu_w18_encode_fns, 0, 0 },
19446 - { "bltu.w18", 354 /* xt_iclass_wb18_4 */,
19447 - XTENSA_OPCODE_IS_BRANCH,
19448 - Opcode_bltu_w18_encode_fns, 0, 0 },
19449 - { "bany.w18", 354 /* xt_iclass_wb18_4 */,
19450 - XTENSA_OPCODE_IS_BRANCH,
19451 - Opcode_bany_w18_encode_fns, 0, 0 },
19452 - { "bnone.w18", 354 /* xt_iclass_wb18_4 */,
19453 - XTENSA_OPCODE_IS_BRANCH,
19454 - Opcode_bnone_w18_encode_fns, 0, 0 },
19455 - { "ball.w18", 354 /* xt_iclass_wb18_4 */,
19456 - XTENSA_OPCODE_IS_BRANCH,
19457 - Opcode_ball_w18_encode_fns, 0, 0 },
19458 - { "bnall.w18", 354 /* xt_iclass_wb18_4 */,
19459 - XTENSA_OPCODE_IS_BRANCH,
19460 - Opcode_bnall_w18_encode_fns, 0, 0 },
19461 - { "bbc.w18", 354 /* xt_iclass_wb18_4 */,
19462 - XTENSA_OPCODE_IS_BRANCH,
19463 - Opcode_bbc_w18_encode_fns, 0, 0 },
19464 - { "bbs.w18", 354 /* xt_iclass_wb18_4 */,
19465 - XTENSA_OPCODE_IS_BRANCH,
19466 - Opcode_bbs_w18_encode_fns, 0, 0 }
19470 -/* Slot-specific opcode decode functions. */
19473 -Slot_inst_decode (const xtensa_insnbuf insn)
19475 - switch (Field_op0_Slot_inst_get (insn))
19478 - switch (Field_op1_Slot_inst_get (insn))
19481 - switch (Field_op2_Slot_inst_get (insn))
19484 - switch (Field_r_Slot_inst_get (insn))
19487 - switch (Field_m_Slot_inst_get (insn))
19490 - if (Field_s_Slot_inst_get (insn) == 0 &&
19491 - Field_n_Slot_inst_get (insn) == 0)
19492 - return 79; /* ill */
19495 - switch (Field_n_Slot_inst_get (insn))
19498 - return 98; /* ret */
19500 - return 14; /* retw */
19502 - return 81; /* jx */
19506 - switch (Field_n_Slot_inst_get (insn))
19509 - return 77; /* callx0 */
19511 - return 10; /* callx4 */
19513 - return 9; /* callx8 */
19515 - return 8; /* callx12 */
19521 - return 12; /* movsp */
19523 - if (Field_s_Slot_inst_get (insn) == 0)
19525 - switch (Field_t_Slot_inst_get (insn))
19528 - return 116; /* isync */
19530 - return 117; /* rsync */
19532 - return 118; /* esync */
19534 - return 119; /* dsync */
19536 - return 0; /* excw */
19538 - return 114; /* memw */
19540 - return 115; /* extw */
19542 - return 97; /* nop */
19547 - switch (Field_t_Slot_inst_get (insn))
19550 - switch (Field_s_Slot_inst_get (insn))
19553 - return 1; /* rfe */
19555 - return 2; /* rfde */
19557 - return 16; /* rfwo */
19559 - return 17; /* rfwu */
19563 - return 316; /* rfi */
19567 - return 324; /* break */
19569 - switch (Field_s_Slot_inst_get (insn))
19572 - if (Field_t_Slot_inst_get (insn) == 0)
19573 - return 3; /* syscall */
19576 - if (Field_t_Slot_inst_get (insn) == 0)
19577 - return 4; /* simcall */
19582 - return 120; /* rsil */
19584 - if (Field_t_Slot_inst_get (insn) == 0)
19585 - return 317; /* waiti */
19588 - return 367; /* any4 */
19590 - return 368; /* all4 */
19592 - return 369; /* any8 */
19594 - return 370; /* all8 */
19598 - return 49; /* and */
19600 - return 50; /* or */
19602 - return 51; /* xor */
19604 - switch (Field_r_Slot_inst_get (insn))
19607 - if (Field_t_Slot_inst_get (insn) == 0)
19608 - return 102; /* ssr */
19611 - if (Field_t_Slot_inst_get (insn) == 0)
19612 - return 103; /* ssl */
19615 - if (Field_t_Slot_inst_get (insn) == 0)
19616 - return 104; /* ssa8l */
19619 - if (Field_t_Slot_inst_get (insn) == 0)
19620 - return 105; /* ssa8b */
19623 - if (Field_thi3_Slot_inst_get (insn) == 0)
19624 - return 106; /* ssai */
19627 - if (Field_s_Slot_inst_get (insn) == 0)
19628 - return 13; /* rotw */
19631 - return 448; /* nsa */
19633 - return 449; /* nsau */
19637 - switch (Field_r_Slot_inst_get (insn))
19640 - return 438; /* hwwitlba */
19642 - return 434; /* ritlb0 */
19644 - if (Field_t_Slot_inst_get (insn) == 0)
19645 - return 432; /* iitlb */
19648 - return 433; /* pitlb */
19650 - return 436; /* witlb */
19652 - return 435; /* ritlb1 */
19654 - return 439; /* hwwdtlba */
19656 - return 429; /* rdtlb0 */
19658 - if (Field_t_Slot_inst_get (insn) == 0)
19659 - return 427; /* idtlb */
19662 - return 428; /* pdtlb */
19664 - return 431; /* wdtlb */
19666 - return 430; /* rdtlb1 */
19670 - switch (Field_s_Slot_inst_get (insn))
19673 - return 95; /* neg */
19675 - return 96; /* abs */
19679 - return 41; /* add */
19681 - return 43; /* addx2 */
19683 - return 44; /* addx4 */
19685 - return 45; /* addx8 */
19687 - return 42; /* sub */
19689 - return 46; /* subx2 */
19691 - return 47; /* subx4 */
19693 - return 48; /* subx8 */
19697 - switch (Field_op2_Slot_inst_get (insn))
19701 - return 111; /* slli */
19704 - return 112; /* srai */
19706 - return 113; /* srli */
19708 - switch (Field_sr_Slot_inst_get (insn))
19711 - return 129; /* xsr.lbeg */
19713 - return 123; /* xsr.lend */
19715 - return 126; /* xsr.lcount */
19717 - return 132; /* xsr.sar */
19719 - return 377; /* xsr.br */
19721 - return 135; /* xsr.litbase */
19723 - return 456; /* xsr.scompare1 */
19725 - return 312; /* xsr.acclo */
19727 - return 315; /* xsr.acchi */
19729 - return 300; /* xsr.m0 */
19731 - return 303; /* xsr.m1 */
19733 - return 306; /* xsr.m2 */
19735 - return 309; /* xsr.m3 */
19737 - return 22; /* xsr.windowbase */
19739 - return 25; /* xsr.windowstart */
19741 - return 417; /* xsr.ptevaddr */
19743 - return 420; /* xsr.rasid */
19745 - return 423; /* xsr.itlbcfg */
19747 - return 426; /* xsr.dtlbcfg */
19749 - return 346; /* xsr.ibreakenable */
19751 - return 358; /* xsr.ddr */
19753 - return 340; /* xsr.ibreaka0 */
19755 - return 343; /* xsr.ibreaka1 */
19757 - return 328; /* xsr.dbreaka0 */
19759 - return 334; /* xsr.dbreaka1 */
19761 - return 331; /* xsr.dbreakc0 */
19763 - return 337; /* xsr.dbreakc1 */
19765 - return 143; /* xsr.epc1 */
19767 - return 149; /* xsr.epc2 */
19769 - return 155; /* xsr.epc3 */
19771 - return 161; /* xsr.epc4 */
19773 - return 167; /* xsr.epc5 */
19775 - return 173; /* xsr.epc6 */
19777 - return 179; /* xsr.epc7 */
19779 - return 206; /* xsr.depc */
19781 - return 185; /* xsr.eps2 */
19783 - return 188; /* xsr.eps3 */
19785 - return 191; /* xsr.eps4 */
19787 - return 194; /* xsr.eps5 */
19789 - return 197; /* xsr.eps6 */
19791 - return 200; /* xsr.eps7 */
19793 - return 146; /* xsr.excsave1 */
19795 - return 152; /* xsr.excsave2 */
19797 - return 158; /* xsr.excsave3 */
19799 - return 164; /* xsr.excsave4 */
19801 - return 170; /* xsr.excsave5 */
19803 - return 176; /* xsr.excsave6 */
19805 - return 182; /* xsr.excsave7 */
19807 - return 442; /* xsr.cpenable */
19809 - return 323; /* xsr.intenable */
19811 - return 140; /* xsr.ps */
19813 - return 225; /* xsr.vecbase */
19815 - return 209; /* xsr.exccause */
19817 - return 349; /* xsr.debugcause */
19819 - return 380; /* xsr.ccount */
19821 - return 352; /* xsr.icount */
19823 - return 355; /* xsr.icountlevel */
19825 - return 203; /* xsr.excvaddr */
19827 - return 383; /* xsr.ccompare0 */
19829 - return 386; /* xsr.ccompare1 */
19831 - return 389; /* xsr.ccompare2 */
19833 - return 212; /* xsr.misc0 */
19835 - return 215; /* xsr.misc1 */
19837 - return 218; /* xsr.misc2 */
19839 - return 221; /* xsr.misc3 */
19843 - return 108; /* src */
19845 - if (Field_s_Slot_inst_get (insn) == 0)
19846 - return 109; /* srl */
19849 - if (Field_t_Slot_inst_get (insn) == 0)
19850 - return 107; /* sll */
19853 - if (Field_s_Slot_inst_get (insn) == 0)
19854 - return 110; /* sra */
19857 - return 296; /* mul16u */
19859 - return 297; /* mul16s */
19861 - switch (Field_r_Slot_inst_get (insn))
19864 - return 396; /* lict */
19866 - return 398; /* sict */
19868 - return 397; /* licw */
19870 - return 399; /* sicw */
19872 - return 414; /* ldct */
19874 - return 413; /* sdct */
19876 - if (Field_t_Slot_inst_get (insn) == 0)
19877 - return 359; /* rfdo */
19878 - if (Field_t_Slot_inst_get (insn) == 1)
19879 - return 360; /* rfdd */
19882 - return 437; /* ldpte */
19888 - switch (Field_op2_Slot_inst_get (insn))
19891 - return 362; /* andb */
19893 - return 363; /* andbc */
19895 - return 364; /* orb */
19897 - return 365; /* orbc */
19899 - return 366; /* xorb */
19901 - return 461; /* mull */
19903 - return 462; /* muluh */
19905 - return 463; /* mulsh */
19907 - return 457; /* quou */
19909 - return 458; /* quos */
19911 - return 459; /* remu */
19913 - return 460; /* rems */
19917 - switch (Field_op2_Slot_inst_get (insn))
19920 - switch (Field_sr_Slot_inst_get (insn))
19923 - return 127; /* rsr.lbeg */
19925 - return 121; /* rsr.lend */
19927 - return 124; /* rsr.lcount */
19929 - return 130; /* rsr.sar */
19931 - return 375; /* rsr.br */
19933 - return 133; /* rsr.litbase */
19935 - return 454; /* rsr.scompare1 */
19937 - return 310; /* rsr.acclo */
19939 - return 313; /* rsr.acchi */
19941 - return 298; /* rsr.m0 */
19943 - return 301; /* rsr.m1 */
19945 - return 304; /* rsr.m2 */
19947 - return 307; /* rsr.m3 */
19949 - return 20; /* rsr.windowbase */
19951 - return 23; /* rsr.windowstart */
19953 - return 416; /* rsr.ptevaddr */
19955 - return 418; /* rsr.rasid */
19957 - return 421; /* rsr.itlbcfg */
19959 - return 424; /* rsr.dtlbcfg */
19961 - return 344; /* rsr.ibreakenable */
19963 - return 356; /* rsr.ddr */
19965 - return 338; /* rsr.ibreaka0 */
19967 - return 341; /* rsr.ibreaka1 */
19969 - return 326; /* rsr.dbreaka0 */
19971 - return 332; /* rsr.dbreaka1 */
19973 - return 329; /* rsr.dbreakc0 */
19975 - return 335; /* rsr.dbreakc1 */
19977 - return 136; /* rsr.176 */
19979 - return 141; /* rsr.epc1 */
19981 - return 147; /* rsr.epc2 */
19983 - return 153; /* rsr.epc3 */
19985 - return 159; /* rsr.epc4 */
19987 - return 165; /* rsr.epc5 */
19989 - return 171; /* rsr.epc6 */
19991 - return 177; /* rsr.epc7 */
19993 - return 204; /* rsr.depc */
19995 - return 183; /* rsr.eps2 */
19997 - return 186; /* rsr.eps3 */
19999 - return 189; /* rsr.eps4 */
20001 - return 192; /* rsr.eps5 */
20003 - return 195; /* rsr.eps6 */
20005 - return 198; /* rsr.eps7 */
20007 - return 137; /* rsr.208 */
20009 - return 144; /* rsr.excsave1 */
20011 - return 150; /* rsr.excsave2 */
20013 - return 156; /* rsr.excsave3 */
20015 - return 162; /* rsr.excsave4 */
20017 - return 168; /* rsr.excsave5 */
20019 - return 174; /* rsr.excsave6 */
20021 - return 180; /* rsr.excsave7 */
20023 - return 440; /* rsr.cpenable */
20025 - return 318; /* rsr.interrupt */
20027 - return 321; /* rsr.intenable */
20029 - return 138; /* rsr.ps */
20031 - return 223; /* rsr.vecbase */
20033 - return 207; /* rsr.exccause */
20035 - return 347; /* rsr.debugcause */
20037 - return 378; /* rsr.ccount */
20039 - return 222; /* rsr.prid */
20041 - return 350; /* rsr.icount */
20043 - return 353; /* rsr.icountlevel */
20045 - return 201; /* rsr.excvaddr */
20047 - return 381; /* rsr.ccompare0 */
20049 - return 384; /* rsr.ccompare1 */
20051 - return 387; /* rsr.ccompare2 */
20053 - return 210; /* rsr.misc0 */
20055 - return 213; /* rsr.misc1 */
20057 - return 216; /* rsr.misc2 */
20059 - return 219; /* rsr.misc3 */
20063 - switch (Field_sr_Slot_inst_get (insn))
20066 - return 128; /* wsr.lbeg */
20068 - return 122; /* wsr.lend */
20070 - return 125; /* wsr.lcount */
20072 - return 131; /* wsr.sar */
20074 - return 376; /* wsr.br */
20076 - return 134; /* wsr.litbase */
20078 - return 455; /* wsr.scompare1 */
20080 - return 311; /* wsr.acclo */
20082 - return 314; /* wsr.acchi */
20084 - return 299; /* wsr.m0 */
20086 - return 302; /* wsr.m1 */
20088 - return 305; /* wsr.m2 */
20090 - return 308; /* wsr.m3 */
20092 - return 21; /* wsr.windowbase */
20094 - return 24; /* wsr.windowstart */
20096 - return 415; /* wsr.ptevaddr */
20098 - return 361; /* wsr.mmid */
20100 - return 419; /* wsr.rasid */
20102 - return 422; /* wsr.itlbcfg */
20104 - return 425; /* wsr.dtlbcfg */
20106 - return 345; /* wsr.ibreakenable */
20108 - return 357; /* wsr.ddr */
20110 - return 339; /* wsr.ibreaka0 */
20112 - return 342; /* wsr.ibreaka1 */
20114 - return 327; /* wsr.dbreaka0 */
20116 - return 333; /* wsr.dbreaka1 */
20118 - return 330; /* wsr.dbreakc0 */
20120 - return 336; /* wsr.dbreakc1 */
20122 - return 142; /* wsr.epc1 */
20124 - return 148; /* wsr.epc2 */
20126 - return 154; /* wsr.epc3 */
20128 - return 160; /* wsr.epc4 */
20130 - return 166; /* wsr.epc5 */
20132 - return 172; /* wsr.epc6 */
20134 - return 178; /* wsr.epc7 */
20136 - return 205; /* wsr.depc */
20138 - return 184; /* wsr.eps2 */
20140 - return 187; /* wsr.eps3 */
20142 - return 190; /* wsr.eps4 */
20144 - return 193; /* wsr.eps5 */
20146 - return 196; /* wsr.eps6 */
20148 - return 199; /* wsr.eps7 */
20150 - return 145; /* wsr.excsave1 */
20152 - return 151; /* wsr.excsave2 */
20154 - return 157; /* wsr.excsave3 */
20156 - return 163; /* wsr.excsave4 */
20158 - return 169; /* wsr.excsave5 */
20160 - return 175; /* wsr.excsave6 */
20162 - return 181; /* wsr.excsave7 */
20164 - return 441; /* wsr.cpenable */
20166 - return 319; /* wsr.intset */
20168 - return 320; /* wsr.intclear */
20170 - return 322; /* wsr.intenable */
20172 - return 139; /* wsr.ps */
20174 - return 224; /* wsr.vecbase */
20176 - return 208; /* wsr.exccause */
20178 - return 348; /* wsr.debugcause */
20180 - return 379; /* wsr.ccount */
20182 - return 351; /* wsr.icount */
20184 - return 354; /* wsr.icountlevel */
20186 - return 202; /* wsr.excvaddr */
20188 - return 382; /* wsr.ccompare0 */
20190 - return 385; /* wsr.ccompare1 */
20192 - return 388; /* wsr.ccompare2 */
20194 - return 211; /* wsr.misc0 */
20196 - return 214; /* wsr.misc1 */
20198 - return 217; /* wsr.misc2 */
20200 - return 220; /* wsr.misc3 */
20204 - return 450; /* sext */
20206 - return 443; /* clamps */
20208 - return 444; /* min */
20210 - return 445; /* max */
20212 - return 446; /* minu */
20214 - return 447; /* maxu */
20216 - return 91; /* moveqz */
20218 - return 92; /* movnez */
20220 - return 93; /* movltz */
20222 - return 94; /* movgez */
20224 - return 373; /* movf */
20226 - return 374; /* movt */
20228 - switch (Field_st_Slot_inst_get (insn))
20231 - return 37; /* rur.threadptr */
20233 - return 464; /* rur.fcr */
20235 - return 466; /* rur.fsr */
20239 - switch (Field_sr_Slot_inst_get (insn))
20242 - return 38; /* wur.threadptr */
20244 - return 465; /* wur.fcr */
20246 - return 467; /* wur.fsr */
20253 - return 78; /* extui */
20255 - switch (Field_op2_Slot_inst_get (insn))
20258 - return 500; /* lsx */
20260 - return 501; /* lsxu */
20262 - return 504; /* ssx */
20264 - return 505; /* ssxu */
20268 - switch (Field_op2_Slot_inst_get (insn))
20271 - return 18; /* l32e */
20273 - return 19; /* s32e */
20277 - switch (Field_op2_Slot_inst_get (insn))
20280 - return 468; /* add.s */
20282 - return 469; /* sub.s */
20284 - return 470; /* mul.s */
20286 - return 471; /* madd.s */
20288 - return 472; /* msub.s */
20290 - return 491; /* round.s */
20292 - return 494; /* trunc.s */
20294 - return 493; /* floor.s */
20296 - return 492; /* ceil.s */
20298 - return 489; /* float.s */
20300 - return 490; /* ufloat.s */
20302 - return 495; /* utrunc.s */
20304 - switch (Field_t_Slot_inst_get (insn))
20307 - return 480; /* mov.s */
20309 - return 479; /* abs.s */
20311 - return 496; /* rfr */
20313 - return 497; /* wfr */
20315 - return 481; /* neg.s */
20321 - switch (Field_op2_Slot_inst_get (insn))
20324 - return 482; /* un.s */
20326 - return 483; /* oeq.s */
20328 - return 484; /* ueq.s */
20330 - return 485; /* olt.s */
20332 - return 486; /* ult.s */
20334 - return 487; /* ole.s */
20336 - return 488; /* ule.s */
20338 - return 475; /* moveqz.s */
20340 - return 476; /* movnez.s */
20342 - return 477; /* movltz.s */
20344 - return 478; /* movgez.s */
20346 - return 473; /* movf.s */
20348 - return 474; /* movt.s */
20354 - return 85; /* l32r */
20356 - switch (Field_r_Slot_inst_get (insn))
20359 - return 86; /* l8ui */
20361 - return 82; /* l16ui */
20363 - return 84; /* l32i */
20365 - return 101; /* s8i */
20367 - return 99; /* s16i */
20369 - return 100; /* s32i */
20371 - switch (Field_t_Slot_inst_get (insn))
20374 - return 406; /* dpfr */
20376 - return 407; /* dpfw */
20378 - return 408; /* dpfro */
20380 - return 409; /* dpfwo */
20382 - return 400; /* dhwb */
20384 - return 401; /* dhwbi */
20386 - return 404; /* dhi */
20388 - return 405; /* dii */
20390 - switch (Field_op1_Slot_inst_get (insn))
20393 - return 410; /* dpfl */
20395 - return 411; /* dhu */
20397 - return 412; /* diu */
20399 - return 402; /* diwb */
20401 - return 403; /* diwbi */
20405 - return 390; /* ipf */
20407 - switch (Field_op1_Slot_inst_get (insn))
20410 - return 392; /* ipfl */
20412 - return 393; /* ihu */
20414 - return 394; /* iiu */
20418 - return 391; /* ihi */
20420 - return 395; /* iii */
20424 - return 83; /* l16si */
20426 - return 90; /* movi */
20428 - return 451; /* l32ai */
20430 - return 39; /* addi */
20432 - return 40; /* addmi */
20434 - return 453; /* s32c1i */
20436 - return 452; /* s32ri */
20440 - switch (Field_r_Slot_inst_get (insn))
20443 - return 498; /* lsi */
20445 - return 502; /* ssi */
20447 - return 499; /* lsiu */
20449 - return 503; /* ssiu */
20453 - switch (Field_op2_Slot_inst_get (insn))
20456 - switch (Field_op1_Slot_inst_get (insn))
20459 - if (Field_t3_Slot_inst_get (insn) == 0 &&
20460 - Field_tlo_Slot_inst_get (insn) == 0 &&
20461 - Field_r3_Slot_inst_get (insn) == 0)
20462 - return 287; /* mula.dd.ll.ldinc */
20465 - if (Field_t3_Slot_inst_get (insn) == 0 &&
20466 - Field_tlo_Slot_inst_get (insn) == 0 &&
20467 - Field_r3_Slot_inst_get (insn) == 0)
20468 - return 289; /* mula.dd.hl.ldinc */
20471 - if (Field_t3_Slot_inst_get (insn) == 0 &&
20472 - Field_tlo_Slot_inst_get (insn) == 0 &&
20473 - Field_r3_Slot_inst_get (insn) == 0)
20474 - return 291; /* mula.dd.lh.ldinc */
20477 - if (Field_t3_Slot_inst_get (insn) == 0 &&
20478 - Field_tlo_Slot_inst_get (insn) == 0 &&
20479 - Field_r3_Slot_inst_get (insn) == 0)
20480 - return 293; /* mula.dd.hh.ldinc */
20485 - switch (Field_op1_Slot_inst_get (insn))
20488 - if (Field_t3_Slot_inst_get (insn) == 0 &&
20489 - Field_tlo_Slot_inst_get (insn) == 0 &&
20490 - Field_r3_Slot_inst_get (insn) == 0)
20491 - return 286; /* mula.dd.ll.lddec */
20494 - if (Field_t3_Slot_inst_get (insn) == 0 &&
20495 - Field_tlo_Slot_inst_get (insn) == 0 &&
20496 - Field_r3_Slot_inst_get (insn) == 0)
20497 - return 288; /* mula.dd.hl.lddec */
20500 - if (Field_t3_Slot_inst_get (insn) == 0 &&
20501 - Field_tlo_Slot_inst_get (insn) == 0 &&
20502 - Field_r3_Slot_inst_get (insn) == 0)
20503 - return 290; /* mula.dd.lh.lddec */
20506 - if (Field_t3_Slot_inst_get (insn) == 0 &&
20507 - Field_tlo_Slot_inst_get (insn) == 0 &&
20508 - Field_r3_Slot_inst_get (insn) == 0)
20509 - return 292; /* mula.dd.hh.lddec */
20514 - switch (Field_op1_Slot_inst_get (insn))
20517 - if (Field_s_Slot_inst_get (insn) == 0 &&
20518 - Field_w_Slot_inst_get (insn) == 0 &&
20519 - Field_r3_Slot_inst_get (insn) == 0 &&
20520 - Field_t3_Slot_inst_get (insn) == 0 &&
20521 - Field_tlo_Slot_inst_get (insn) == 0)
20522 - return 242; /* mul.dd.ll */
20525 - if (Field_s_Slot_inst_get (insn) == 0 &&
20526 - Field_w_Slot_inst_get (insn) == 0 &&
20527 - Field_r3_Slot_inst_get (insn) == 0 &&
20528 - Field_t3_Slot_inst_get (insn) == 0 &&
20529 - Field_tlo_Slot_inst_get (insn) == 0)
20530 - return 243; /* mul.dd.hl */
20533 - if (Field_s_Slot_inst_get (insn) == 0 &&
20534 - Field_w_Slot_inst_get (insn) == 0 &&
20535 - Field_r3_Slot_inst_get (insn) == 0 &&
20536 - Field_t3_Slot_inst_get (insn) == 0 &&
20537 - Field_tlo_Slot_inst_get (insn) == 0)
20538 - return 244; /* mul.dd.lh */
20541 - if (Field_s_Slot_inst_get (insn) == 0 &&
20542 - Field_w_Slot_inst_get (insn) == 0 &&
20543 - Field_r3_Slot_inst_get (insn) == 0 &&
20544 - Field_t3_Slot_inst_get (insn) == 0 &&
20545 - Field_tlo_Slot_inst_get (insn) == 0)
20546 - return 245; /* mul.dd.hh */
20549 - if (Field_s_Slot_inst_get (insn) == 0 &&
20550 - Field_w_Slot_inst_get (insn) == 0 &&
20551 - Field_r3_Slot_inst_get (insn) == 0 &&
20552 - Field_t3_Slot_inst_get (insn) == 0 &&
20553 - Field_tlo_Slot_inst_get (insn) == 0)
20554 - return 270; /* mula.dd.ll */
20557 - if (Field_s_Slot_inst_get (insn) == 0 &&
20558 - Field_w_Slot_inst_get (insn) == 0 &&
20559 - Field_r3_Slot_inst_get (insn) == 0 &&
20560 - Field_t3_Slot_inst_get (insn) == 0 &&
20561 - Field_tlo_Slot_inst_get (insn) == 0)
20562 - return 271; /* mula.dd.hl */
20565 - if (Field_s_Slot_inst_get (insn) == 0 &&
20566 - Field_w_Slot_inst_get (insn) == 0 &&
20567 - Field_r3_Slot_inst_get (insn) == 0 &&
20568 - Field_t3_Slot_inst_get (insn) == 0 &&
20569 - Field_tlo_Slot_inst_get (insn) == 0)
20570 - return 272; /* mula.dd.lh */
20573 - if (Field_s_Slot_inst_get (insn) == 0 &&
20574 - Field_w_Slot_inst_get (insn) == 0 &&
20575 - Field_r3_Slot_inst_get (insn) == 0 &&
20576 - Field_t3_Slot_inst_get (insn) == 0 &&
20577 - Field_tlo_Slot_inst_get (insn) == 0)
20578 - return 273; /* mula.dd.hh */
20581 - if (Field_s_Slot_inst_get (insn) == 0 &&
20582 - Field_w_Slot_inst_get (insn) == 0 &&
20583 - Field_r3_Slot_inst_get (insn) == 0 &&
20584 - Field_t3_Slot_inst_get (insn) == 0 &&
20585 - Field_tlo_Slot_inst_get (insn) == 0)
20586 - return 274; /* muls.dd.ll */
20589 - if (Field_s_Slot_inst_get (insn) == 0 &&
20590 - Field_w_Slot_inst_get (insn) == 0 &&
20591 - Field_r3_Slot_inst_get (insn) == 0 &&
20592 - Field_t3_Slot_inst_get (insn) == 0 &&
20593 - Field_tlo_Slot_inst_get (insn) == 0)
20594 - return 275; /* muls.dd.hl */
20597 - if (Field_s_Slot_inst_get (insn) == 0 &&
20598 - Field_w_Slot_inst_get (insn) == 0 &&
20599 - Field_r3_Slot_inst_get (insn) == 0 &&
20600 - Field_t3_Slot_inst_get (insn) == 0 &&
20601 - Field_tlo_Slot_inst_get (insn) == 0)
20602 - return 276; /* muls.dd.lh */
20605 - if (Field_s_Slot_inst_get (insn) == 0 &&
20606 - Field_w_Slot_inst_get (insn) == 0 &&
20607 - Field_r3_Slot_inst_get (insn) == 0 &&
20608 - Field_t3_Slot_inst_get (insn) == 0 &&
20609 - Field_tlo_Slot_inst_get (insn) == 0)
20610 - return 277; /* muls.dd.hh */
20615 - switch (Field_op1_Slot_inst_get (insn))
20618 - if (Field_r_Slot_inst_get (insn) == 0 &&
20619 - Field_t3_Slot_inst_get (insn) == 0 &&
20620 - Field_tlo_Slot_inst_get (insn) == 0)
20621 - return 234; /* mul.ad.ll */
20624 - if (Field_r_Slot_inst_get (insn) == 0 &&
20625 - Field_t3_Slot_inst_get (insn) == 0 &&
20626 - Field_tlo_Slot_inst_get (insn) == 0)
20627 - return 235; /* mul.ad.hl */
20630 - if (Field_r_Slot_inst_get (insn) == 0 &&
20631 - Field_t3_Slot_inst_get (insn) == 0 &&
20632 - Field_tlo_Slot_inst_get (insn) == 0)
20633 - return 236; /* mul.ad.lh */
20636 - if (Field_r_Slot_inst_get (insn) == 0 &&
20637 - Field_t3_Slot_inst_get (insn) == 0 &&
20638 - Field_tlo_Slot_inst_get (insn) == 0)
20639 - return 237; /* mul.ad.hh */
20642 - if (Field_r_Slot_inst_get (insn) == 0 &&
20643 - Field_t3_Slot_inst_get (insn) == 0 &&
20644 - Field_tlo_Slot_inst_get (insn) == 0)
20645 - return 254; /* mula.ad.ll */
20648 - if (Field_r_Slot_inst_get (insn) == 0 &&
20649 - Field_t3_Slot_inst_get (insn) == 0 &&
20650 - Field_tlo_Slot_inst_get (insn) == 0)
20651 - return 255; /* mula.ad.hl */
20654 - if (Field_r_Slot_inst_get (insn) == 0 &&
20655 - Field_t3_Slot_inst_get (insn) == 0 &&
20656 - Field_tlo_Slot_inst_get (insn) == 0)
20657 - return 256; /* mula.ad.lh */
20660 - if (Field_r_Slot_inst_get (insn) == 0 &&
20661 - Field_t3_Slot_inst_get (insn) == 0 &&
20662 - Field_tlo_Slot_inst_get (insn) == 0)
20663 - return 257; /* mula.ad.hh */
20666 - if (Field_r_Slot_inst_get (insn) == 0 &&
20667 - Field_t3_Slot_inst_get (insn) == 0 &&
20668 - Field_tlo_Slot_inst_get (insn) == 0)
20669 - return 258; /* muls.ad.ll */
20672 - if (Field_r_Slot_inst_get (insn) == 0 &&
20673 - Field_t3_Slot_inst_get (insn) == 0 &&
20674 - Field_tlo_Slot_inst_get (insn) == 0)
20675 - return 259; /* muls.ad.hl */
20678 - if (Field_r_Slot_inst_get (insn) == 0 &&
20679 - Field_t3_Slot_inst_get (insn) == 0 &&
20680 - Field_tlo_Slot_inst_get (insn) == 0)
20681 - return 260; /* muls.ad.lh */
20684 - if (Field_r_Slot_inst_get (insn) == 0 &&
20685 - Field_t3_Slot_inst_get (insn) == 0 &&
20686 - Field_tlo_Slot_inst_get (insn) == 0)
20687 - return 261; /* muls.ad.hh */
20692 - switch (Field_op1_Slot_inst_get (insn))
20695 - if (Field_r3_Slot_inst_get (insn) == 0)
20696 - return 279; /* mula.da.ll.ldinc */
20699 - if (Field_r3_Slot_inst_get (insn) == 0)
20700 - return 281; /* mula.da.hl.ldinc */
20703 - if (Field_r3_Slot_inst_get (insn) == 0)
20704 - return 283; /* mula.da.lh.ldinc */
20707 - if (Field_r3_Slot_inst_get (insn) == 0)
20708 - return 285; /* mula.da.hh.ldinc */
20713 - switch (Field_op1_Slot_inst_get (insn))
20716 - if (Field_r3_Slot_inst_get (insn) == 0)
20717 - return 278; /* mula.da.ll.lddec */
20720 - if (Field_r3_Slot_inst_get (insn) == 0)
20721 - return 280; /* mula.da.hl.lddec */
20724 - if (Field_r3_Slot_inst_get (insn) == 0)
20725 - return 282; /* mula.da.lh.lddec */
20728 - if (Field_r3_Slot_inst_get (insn) == 0)
20729 - return 284; /* mula.da.hh.lddec */
20734 - switch (Field_op1_Slot_inst_get (insn))
20737 - if (Field_s_Slot_inst_get (insn) == 0 &&
20738 - Field_w_Slot_inst_get (insn) == 0 &&
20739 - Field_r3_Slot_inst_get (insn) == 0)
20740 - return 238; /* mul.da.ll */
20743 - if (Field_s_Slot_inst_get (insn) == 0 &&
20744 - Field_w_Slot_inst_get (insn) == 0 &&
20745 - Field_r3_Slot_inst_get (insn) == 0)
20746 - return 239; /* mul.da.hl */
20749 - if (Field_s_Slot_inst_get (insn) == 0 &&
20750 - Field_w_Slot_inst_get (insn) == 0 &&
20751 - Field_r3_Slot_inst_get (insn) == 0)
20752 - return 240; /* mul.da.lh */
20755 - if (Field_s_Slot_inst_get (insn) == 0 &&
20756 - Field_w_Slot_inst_get (insn) == 0 &&
20757 - Field_r3_Slot_inst_get (insn) == 0)
20758 - return 241; /* mul.da.hh */
20761 - if (Field_s_Slot_inst_get (insn) == 0 &&
20762 - Field_w_Slot_inst_get (insn) == 0 &&
20763 - Field_r3_Slot_inst_get (insn) == 0)
20764 - return 262; /* mula.da.ll */
20767 - if (Field_s_Slot_inst_get (insn) == 0 &&
20768 - Field_w_Slot_inst_get (insn) == 0 &&
20769 - Field_r3_Slot_inst_get (insn) == 0)
20770 - return 263; /* mula.da.hl */
20773 - if (Field_s_Slot_inst_get (insn) == 0 &&
20774 - Field_w_Slot_inst_get (insn) == 0 &&
20775 - Field_r3_Slot_inst_get (insn) == 0)
20776 - return 264; /* mula.da.lh */
20779 - if (Field_s_Slot_inst_get (insn) == 0 &&
20780 - Field_w_Slot_inst_get (insn) == 0 &&
20781 - Field_r3_Slot_inst_get (insn) == 0)
20782 - return 265; /* mula.da.hh */
20785 - if (Field_s_Slot_inst_get (insn) == 0 &&
20786 - Field_w_Slot_inst_get (insn) == 0 &&
20787 - Field_r3_Slot_inst_get (insn) == 0)
20788 - return 266; /* muls.da.ll */
20791 - if (Field_s_Slot_inst_get (insn) == 0 &&
20792 - Field_w_Slot_inst_get (insn) == 0 &&
20793 - Field_r3_Slot_inst_get (insn) == 0)
20794 - return 267; /* muls.da.hl */
20797 - if (Field_s_Slot_inst_get (insn) == 0 &&
20798 - Field_w_Slot_inst_get (insn) == 0 &&
20799 - Field_r3_Slot_inst_get (insn) == 0)
20800 - return 268; /* muls.da.lh */
20803 - if (Field_s_Slot_inst_get (insn) == 0 &&
20804 - Field_w_Slot_inst_get (insn) == 0 &&
20805 - Field_r3_Slot_inst_get (insn) == 0)
20806 - return 269; /* muls.da.hh */
20811 - switch (Field_op1_Slot_inst_get (insn))
20814 - if (Field_r_Slot_inst_get (insn) == 0)
20815 - return 230; /* umul.aa.ll */
20818 - if (Field_r_Slot_inst_get (insn) == 0)
20819 - return 231; /* umul.aa.hl */
20822 - if (Field_r_Slot_inst_get (insn) == 0)
20823 - return 232; /* umul.aa.lh */
20826 - if (Field_r_Slot_inst_get (insn) == 0)
20827 - return 233; /* umul.aa.hh */
20830 - if (Field_r_Slot_inst_get (insn) == 0)
20831 - return 226; /* mul.aa.ll */
20834 - if (Field_r_Slot_inst_get (insn) == 0)
20835 - return 227; /* mul.aa.hl */
20838 - if (Field_r_Slot_inst_get (insn) == 0)
20839 - return 228; /* mul.aa.lh */
20842 - if (Field_r_Slot_inst_get (insn) == 0)
20843 - return 229; /* mul.aa.hh */
20846 - if (Field_r_Slot_inst_get (insn) == 0)
20847 - return 246; /* mula.aa.ll */
20850 - if (Field_r_Slot_inst_get (insn) == 0)
20851 - return 247; /* mula.aa.hl */
20854 - if (Field_r_Slot_inst_get (insn) == 0)
20855 - return 248; /* mula.aa.lh */
20858 - if (Field_r_Slot_inst_get (insn) == 0)
20859 - return 249; /* mula.aa.hh */
20862 - if (Field_r_Slot_inst_get (insn) == 0)
20863 - return 250; /* muls.aa.ll */
20866 - if (Field_r_Slot_inst_get (insn) == 0)
20867 - return 251; /* muls.aa.hl */
20870 - if (Field_r_Slot_inst_get (insn) == 0)
20871 - return 252; /* muls.aa.lh */
20874 - if (Field_r_Slot_inst_get (insn) == 0)
20875 - return 253; /* muls.aa.hh */
20880 - if (Field_op1_Slot_inst_get (insn) == 0 &&
20881 - Field_t_Slot_inst_get (insn) == 0 &&
20882 - Field_rhi_Slot_inst_get (insn) == 0)
20883 - return 295; /* ldinc */
20886 - if (Field_op1_Slot_inst_get (insn) == 0 &&
20887 - Field_t_Slot_inst_get (insn) == 0 &&
20888 - Field_rhi_Slot_inst_get (insn) == 0)
20889 - return 294; /* lddec */
20894 - switch (Field_n_Slot_inst_get (insn))
20897 - return 76; /* call0 */
20899 - return 7; /* call4 */
20901 - return 6; /* call8 */
20903 - return 5; /* call12 */
20907 - switch (Field_n_Slot_inst_get (insn))
20910 - return 80; /* j */
20912 - switch (Field_m_Slot_inst_get (insn))
20915 - return 72; /* beqz */
20917 - return 73; /* bnez */
20919 - return 75; /* bltz */
20921 - return 74; /* bgez */
20925 - switch (Field_m_Slot_inst_get (insn))
20928 - return 52; /* beqi */
20930 - return 53; /* bnei */
20932 - return 55; /* blti */
20934 - return 54; /* bgei */
20938 - switch (Field_m_Slot_inst_get (insn))
20941 - return 11; /* entry */
20943 - switch (Field_r_Slot_inst_get (insn))
20946 - return 371; /* bf */
20948 - return 372; /* bt */
20950 - return 87; /* loop */
20952 - return 88; /* loopnez */
20954 - return 89; /* loopgtz */
20958 - return 59; /* bltui */
20960 - return 58; /* bgeui */
20966 - switch (Field_r_Slot_inst_get (insn))
20969 - return 67; /* bnone */
20971 - return 60; /* beq */
20973 - return 63; /* blt */
20975 - return 65; /* bltu */
20977 - return 68; /* ball */
20979 - return 70; /* bbc */
20982 - return 56; /* bbci */
20984 - return 66; /* bany */
20986 - return 61; /* bne */
20988 - return 62; /* bge */
20990 - return 64; /* bgeu */
20992 - return 69; /* bnall */
20994 - return 71; /* bbs */
20997 - return 57; /* bbsi */
21002 +static xtensa_iclass_internal iclasses[] = {
21003 + { 0, 0 /* xt_iclass_excw */,
21005 + { 0, 0 /* xt_iclass_rfe */,
21006 + 2, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
21007 + { 0, 0 /* xt_iclass_rfde */,
21008 + 1, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
21009 + { 0, 0 /* xt_iclass_syscall */,
21011 + { 0, 0 /* xt_iclass_simcall */,
21013 + { 2, Iclass_xt_iclass_call12_args,
21014 + 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
21015 + { 2, Iclass_xt_iclass_call8_args,
21016 + 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 },
21017 + { 2, Iclass_xt_iclass_call4_args,
21018 + 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 },
21019 + { 2, Iclass_xt_iclass_callx12_args,
21020 + 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 },
21021 + { 2, Iclass_xt_iclass_callx8_args,
21022 + 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 },
21023 + { 2, Iclass_xt_iclass_callx4_args,
21024 + 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 },
21025 + { 3, Iclass_xt_iclass_entry_args,
21026 + 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 },
21027 + { 2, Iclass_xt_iclass_movsp_args,
21028 + 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 },
21029 + { 1, Iclass_xt_iclass_rotw_args,
21030 + 1, Iclass_xt_iclass_rotw_stateArgs, 0, 0 },
21031 + { 1, Iclass_xt_iclass_retw_args,
21032 + 4, Iclass_xt_iclass_retw_stateArgs, 0, 0 },
21033 + { 0, 0 /* xt_iclass_rfwou */,
21034 + 5, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 },
21035 + { 3, Iclass_xt_iclass_l32e_args,
21037 + { 3, Iclass_xt_iclass_s32e_args,
21039 + { 1, Iclass_xt_iclass_rsr_windowbase_args,
21040 + 1, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 },
21041 + { 1, Iclass_xt_iclass_wsr_windowbase_args,
21042 + 1, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 },
21043 + { 1, Iclass_xt_iclass_xsr_windowbase_args,
21044 + 1, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 },
21045 + { 1, Iclass_xt_iclass_rsr_windowstart_args,
21046 + 1, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 },
21047 + { 1, Iclass_xt_iclass_wsr_windowstart_args,
21048 + 1, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 },
21049 + { 1, Iclass_xt_iclass_xsr_windowstart_args,
21050 + 1, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 },
21051 + { 3, Iclass_xt_iclass_add_n_args,
21053 + { 3, Iclass_xt_iclass_addi_n_args,
21055 + { 2, Iclass_xt_iclass_bz6_args,
21057 + { 0, 0 /* xt_iclass_ill_n */,
21059 + { 3, Iclass_xt_iclass_loadi4_args,
21061 + { 2, Iclass_xt_iclass_mov_n_args,
21063 + { 2, Iclass_xt_iclass_movi_n_args,
21065 + { 0, 0 /* xt_iclass_nopn */,
21067 + { 1, Iclass_xt_iclass_retn_args,
21069 + { 3, Iclass_xt_iclass_storei4_args,
21071 + { 1, Iclass_rur_threadptr_args,
21072 + 1, Iclass_rur_threadptr_stateArgs, 0, 0 },
21073 + { 1, Iclass_wur_threadptr_args,
21074 + 1, Iclass_wur_threadptr_stateArgs, 0, 0 },
21075 + { 3, Iclass_xt_iclass_addi_args,
21077 + { 3, Iclass_xt_iclass_addmi_args,
21079 + { 3, Iclass_xt_iclass_addsub_args,
21081 + { 3, Iclass_xt_iclass_bit_args,
21083 + { 3, Iclass_xt_iclass_bsi8_args,
21085 + { 3, Iclass_xt_iclass_bsi8b_args,
21087 + { 3, Iclass_xt_iclass_bsi8u_args,
21089 + { 3, Iclass_xt_iclass_bst8_args,
21091 + { 2, Iclass_xt_iclass_bsz12_args,
21093 + { 2, Iclass_xt_iclass_call0_args,
21095 + { 2, Iclass_xt_iclass_callx0_args,
21097 + { 4, Iclass_xt_iclass_exti_args,
21099 + { 0, 0 /* xt_iclass_ill */,
21101 + { 1, Iclass_xt_iclass_jump_args,
21103 + { 1, Iclass_xt_iclass_jumpx_args,
21105 + { 3, Iclass_xt_iclass_l16ui_args,
21107 + { 3, Iclass_xt_iclass_l16si_args,
21109 + { 3, Iclass_xt_iclass_l32i_args,
21111 + { 2, Iclass_xt_iclass_l32r_args,
21112 + 2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 },
21113 + { 3, Iclass_xt_iclass_l8i_args,
21115 + { 2, Iclass_xt_iclass_loop_args,
21116 + 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 },
21117 + { 2, Iclass_xt_iclass_loopz_args,
21118 + 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 },
21119 + { 2, Iclass_xt_iclass_movi_args,
21121 + { 3, Iclass_xt_iclass_movz_args,
21123 + { 2, Iclass_xt_iclass_neg_args,
21125 + { 0, 0 /* xt_iclass_nop */,
21127 + { 1, Iclass_xt_iclass_return_args,
21129 + { 3, Iclass_xt_iclass_s16i_args,
21131 + { 3, Iclass_xt_iclass_s32i_args,
21133 + { 3, Iclass_xt_iclass_s8i_args,
21135 + { 1, Iclass_xt_iclass_sar_args,
21136 + 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
21137 + { 1, Iclass_xt_iclass_sari_args,
21138 + 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
21139 + { 2, Iclass_xt_iclass_shifts_args,
21140 + 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
21141 + { 3, Iclass_xt_iclass_shiftst_args,
21142 + 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
21143 + { 2, Iclass_xt_iclass_shiftt_args,
21144 + 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
21145 + { 3, Iclass_xt_iclass_slli_args,
21147 + { 3, Iclass_xt_iclass_srai_args,
21149 + { 3, Iclass_xt_iclass_srli_args,
21151 + { 0, 0 /* xt_iclass_memw */,
21153 + { 0, 0 /* xt_iclass_extw */,
21155 + { 0, 0 /* xt_iclass_isync */,
21157 + { 0, 0 /* xt_iclass_sync */,
21158 + 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
21159 + { 2, Iclass_xt_iclass_rsil_args,
21160 + 6, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
21161 + { 1, Iclass_xt_iclass_rsr_lend_args,
21162 + 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 },
21163 + { 1, Iclass_xt_iclass_wsr_lend_args,
21164 + 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 },
21165 + { 1, Iclass_xt_iclass_xsr_lend_args,
21166 + 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 },
21167 + { 1, Iclass_xt_iclass_rsr_lcount_args,
21168 + 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 },
21169 + { 1, Iclass_xt_iclass_wsr_lcount_args,
21170 + 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 },
21171 + { 1, Iclass_xt_iclass_xsr_lcount_args,
21172 + 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 },
21173 + { 1, Iclass_xt_iclass_rsr_lbeg_args,
21174 + 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 },
21175 + { 1, Iclass_xt_iclass_wsr_lbeg_args,
21176 + 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 },
21177 + { 1, Iclass_xt_iclass_xsr_lbeg_args,
21178 + 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 },
21179 + { 1, Iclass_xt_iclass_rsr_sar_args,
21180 + 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
21181 + { 1, Iclass_xt_iclass_wsr_sar_args,
21182 + 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
21183 + { 1, Iclass_xt_iclass_xsr_sar_args,
21184 + 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
21185 + { 1, Iclass_xt_iclass_rsr_litbase_args,
21186 + 2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 },
21187 + { 1, Iclass_xt_iclass_wsr_litbase_args,
21188 + 2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 },
21189 + { 1, Iclass_xt_iclass_xsr_litbase_args,
21190 + 2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 },
21191 + { 1, Iclass_xt_iclass_rsr_176_args,
21193 + { 1, Iclass_xt_iclass_rsr_208_args,
21195 + { 1, Iclass_xt_iclass_rsr_ps_args,
21196 + 6, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
21197 + { 1, Iclass_xt_iclass_wsr_ps_args,
21198 + 6, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
21199 + { 1, Iclass_xt_iclass_xsr_ps_args,
21200 + 6, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
21201 + { 1, Iclass_xt_iclass_rsr_epc1_args,
21202 + 1, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
21203 + { 1, Iclass_xt_iclass_wsr_epc1_args,
21204 + 1, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
21205 + { 1, Iclass_xt_iclass_xsr_epc1_args,
21206 + 1, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
21207 + { 1, Iclass_xt_iclass_rsr_excsave1_args,
21208 + 1, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
21209 + { 1, Iclass_xt_iclass_wsr_excsave1_args,
21210 + 1, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
21211 + { 1, Iclass_xt_iclass_xsr_excsave1_args,
21212 + 1, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
21213 + { 1, Iclass_xt_iclass_rsr_epc2_args,
21214 + 1, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
21215 + { 1, Iclass_xt_iclass_wsr_epc2_args,
21216 + 1, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
21217 + { 1, Iclass_xt_iclass_xsr_epc2_args,
21218 + 1, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
21219 + { 1, Iclass_xt_iclass_rsr_excsave2_args,
21220 + 1, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
21221 + { 1, Iclass_xt_iclass_wsr_excsave2_args,
21222 + 1, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
21223 + { 1, Iclass_xt_iclass_xsr_excsave2_args,
21224 + 1, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
21225 + { 1, Iclass_xt_iclass_rsr_epc3_args,
21226 + 1, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 },
21227 + { 1, Iclass_xt_iclass_wsr_epc3_args,
21228 + 1, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 },
21229 + { 1, Iclass_xt_iclass_xsr_epc3_args,
21230 + 1, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 },
21231 + { 1, Iclass_xt_iclass_rsr_excsave3_args,
21232 + 1, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 },
21233 + { 1, Iclass_xt_iclass_wsr_excsave3_args,
21234 + 1, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 },
21235 + { 1, Iclass_xt_iclass_xsr_excsave3_args,
21236 + 1, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 },
21237 + { 1, Iclass_xt_iclass_rsr_epc4_args,
21238 + 1, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 },
21239 + { 1, Iclass_xt_iclass_wsr_epc4_args,
21240 + 1, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 },
21241 + { 1, Iclass_xt_iclass_xsr_epc4_args,
21242 + 1, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 },
21243 + { 1, Iclass_xt_iclass_rsr_excsave4_args,
21244 + 1, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 },
21245 + { 1, Iclass_xt_iclass_wsr_excsave4_args,
21246 + 1, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 },
21247 + { 1, Iclass_xt_iclass_xsr_excsave4_args,
21248 + 1, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 },
21249 + { 1, Iclass_xt_iclass_rsr_epc5_args,
21250 + 1, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 },
21251 + { 1, Iclass_xt_iclass_wsr_epc5_args,
21252 + 1, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 },
21253 + { 1, Iclass_xt_iclass_xsr_epc5_args,
21254 + 1, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 },
21255 + { 1, Iclass_xt_iclass_rsr_excsave5_args,
21256 + 1, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 },
21257 + { 1, Iclass_xt_iclass_wsr_excsave5_args,
21258 + 1, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 },
21259 + { 1, Iclass_xt_iclass_xsr_excsave5_args,
21260 + 1, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 },
21261 + { 1, Iclass_xt_iclass_rsr_eps2_args,
21262 + 1, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
21263 + { 1, Iclass_xt_iclass_wsr_eps2_args,
21264 + 1, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
21265 + { 1, Iclass_xt_iclass_xsr_eps2_args,
21266 + 1, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
21267 + { 1, Iclass_xt_iclass_rsr_eps3_args,
21268 + 1, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 },
21269 + { 1, Iclass_xt_iclass_wsr_eps3_args,
21270 + 1, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 },
21271 + { 1, Iclass_xt_iclass_xsr_eps3_args,
21272 + 1, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 },
21273 + { 1, Iclass_xt_iclass_rsr_eps4_args,
21274 + 1, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 },
21275 + { 1, Iclass_xt_iclass_wsr_eps4_args,
21276 + 1, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 },
21277 + { 1, Iclass_xt_iclass_xsr_eps4_args,
21278 + 1, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 },
21279 + { 1, Iclass_xt_iclass_rsr_eps5_args,
21280 + 1, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 },
21281 + { 1, Iclass_xt_iclass_wsr_eps5_args,
21282 + 1, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 },
21283 + { 1, Iclass_xt_iclass_xsr_eps5_args,
21284 + 1, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 },
21285 + { 1, Iclass_xt_iclass_rsr_excvaddr_args,
21286 + 1, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
21287 + { 1, Iclass_xt_iclass_wsr_excvaddr_args,
21288 + 1, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
21289 + { 1, Iclass_xt_iclass_xsr_excvaddr_args,
21290 + 1, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
21291 + { 1, Iclass_xt_iclass_rsr_depc_args,
21292 + 1, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
21293 + { 1, Iclass_xt_iclass_wsr_depc_args,
21294 + 1, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
21295 + { 1, Iclass_xt_iclass_xsr_depc_args,
21296 + 1, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
21297 + { 1, Iclass_xt_iclass_rsr_exccause_args,
21298 + 2, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
21299 + { 1, Iclass_xt_iclass_wsr_exccause_args,
21300 + 1, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
21301 + { 1, Iclass_xt_iclass_xsr_exccause_args,
21302 + 1, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
21303 + { 1, Iclass_xt_iclass_rsr_misc0_args,
21304 + 1, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 },
21305 + { 1, Iclass_xt_iclass_wsr_misc0_args,
21306 + 1, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 },
21307 + { 1, Iclass_xt_iclass_xsr_misc0_args,
21308 + 1, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 },
21309 + { 1, Iclass_xt_iclass_rsr_misc1_args,
21310 + 1, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 },
21311 + { 1, Iclass_xt_iclass_wsr_misc1_args,
21312 + 1, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 },
21313 + { 1, Iclass_xt_iclass_xsr_misc1_args,
21314 + 1, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 },
21315 + { 1, Iclass_xt_iclass_rsr_prid_args,
21317 + { 1, Iclass_xt_iclass_rsr_vecbase_args,
21318 + 1, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 },
21319 + { 1, Iclass_xt_iclass_wsr_vecbase_args,
21320 + 1, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 },
21321 + { 1, Iclass_xt_iclass_xsr_vecbase_args,
21322 + 1, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 },
21323 + { 1, Iclass_xt_iclass_rfi_args,
21324 + 16, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
21325 + { 1, Iclass_xt_iclass_wait_args,
21326 + 1, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
21327 + { 1, Iclass_xt_iclass_rsr_interrupt_args,
21328 + 1, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
21329 + { 1, Iclass_xt_iclass_wsr_intset_args,
21330 + 2, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
21331 + { 1, Iclass_xt_iclass_wsr_intclear_args,
21332 + 2, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
21333 + { 1, Iclass_xt_iclass_rsr_intenable_args,
21334 + 1, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
21335 + { 1, Iclass_xt_iclass_wsr_intenable_args,
21336 + 1, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
21337 + { 1, Iclass_xt_iclass_xsr_intenable_args,
21338 + 1, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
21339 + { 2, Iclass_xt_iclass_break_args,
21340 + 2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
21341 + { 1, Iclass_xt_iclass_break_n_args,
21342 + 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
21343 + { 1, Iclass_xt_iclass_rsr_dbreaka0_args,
21344 + 1, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 },
21345 + { 1, Iclass_xt_iclass_wsr_dbreaka0_args,
21346 + 2, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 },
21347 + { 1, Iclass_xt_iclass_xsr_dbreaka0_args,
21348 + 2, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 },
21349 + { 1, Iclass_xt_iclass_rsr_dbreakc0_args,
21350 + 1, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 },
21351 + { 1, Iclass_xt_iclass_wsr_dbreakc0_args,
21352 + 2, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 },
21353 + { 1, Iclass_xt_iclass_xsr_dbreakc0_args,
21354 + 2, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 },
21355 + { 1, Iclass_xt_iclass_rsr_dbreaka1_args,
21356 + 1, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 },
21357 + { 1, Iclass_xt_iclass_wsr_dbreaka1_args,
21358 + 2, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 },
21359 + { 1, Iclass_xt_iclass_xsr_dbreaka1_args,
21360 + 2, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 },
21361 + { 1, Iclass_xt_iclass_rsr_dbreakc1_args,
21362 + 1, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 },
21363 + { 1, Iclass_xt_iclass_wsr_dbreakc1_args,
21364 + 2, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 },
21365 + { 1, Iclass_xt_iclass_xsr_dbreakc1_args,
21366 + 2, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 },
21367 + { 1, Iclass_xt_iclass_rsr_ibreaka0_args,
21368 + 1, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 },
21369 + { 1, Iclass_xt_iclass_wsr_ibreaka0_args,
21370 + 1, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 },
21371 + { 1, Iclass_xt_iclass_xsr_ibreaka0_args,
21372 + 1, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 },
21373 + { 1, Iclass_xt_iclass_rsr_ibreaka1_args,
21374 + 1, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 },
21375 + { 1, Iclass_xt_iclass_wsr_ibreaka1_args,
21376 + 1, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 },
21377 + { 1, Iclass_xt_iclass_xsr_ibreaka1_args,
21378 + 1, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 },
21379 + { 1, Iclass_xt_iclass_rsr_ibreakenable_args,
21380 + 1, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 },
21381 + { 1, Iclass_xt_iclass_wsr_ibreakenable_args,
21382 + 1, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 },
21383 + { 1, Iclass_xt_iclass_xsr_ibreakenable_args,
21384 + 1, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 },
21385 + { 1, Iclass_xt_iclass_rsr_debugcause_args,
21386 + 2, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
21387 + { 1, Iclass_xt_iclass_wsr_debugcause_args,
21388 + 2, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
21389 + { 1, Iclass_xt_iclass_xsr_debugcause_args,
21390 + 2, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
21391 + { 1, Iclass_xt_iclass_rsr_icount_args,
21392 + 1, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
21393 + { 1, Iclass_xt_iclass_wsr_icount_args,
21394 + 2, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
21395 + { 1, Iclass_xt_iclass_xsr_icount_args,
21396 + 2, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
21397 + { 1, Iclass_xt_iclass_rsr_icountlevel_args,
21398 + 1, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
21399 + { 1, Iclass_xt_iclass_wsr_icountlevel_args,
21400 + 1, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
21401 + { 1, Iclass_xt_iclass_xsr_icountlevel_args,
21402 + 1, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
21403 + { 1, Iclass_xt_iclass_rsr_ddr_args,
21404 + 1, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
21405 + { 1, Iclass_xt_iclass_wsr_ddr_args,
21406 + 2, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
21407 + { 1, Iclass_xt_iclass_xsr_ddr_args,
21408 + 2, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
21409 + { 1, Iclass_xt_iclass_rfdo_args,
21410 + 9, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
21411 + { 0, 0 /* xt_iclass_rfdd */,
21412 + 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
21413 + { 1, Iclass_xt_iclass_wsr_mmid_args,
21414 + 1, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 },
21415 + { 1, Iclass_xt_iclass_rsr_ccount_args,
21416 + 1, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
21417 + { 1, Iclass_xt_iclass_wsr_ccount_args,
21418 + 2, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
21419 + { 1, Iclass_xt_iclass_xsr_ccount_args,
21420 + 2, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
21421 + { 1, Iclass_xt_iclass_rsr_ccompare0_args,
21422 + 1, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
21423 + { 1, Iclass_xt_iclass_wsr_ccompare0_args,
21424 + 2, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
21425 + { 1, Iclass_xt_iclass_xsr_ccompare0_args,
21426 + 2, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
21427 + { 1, Iclass_xt_iclass_idtlb_args,
21428 + 1, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
21429 + { 2, Iclass_xt_iclass_rdtlb_args,
21431 + { 2, Iclass_xt_iclass_wdtlb_args,
21432 + 1, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
21433 + { 1, Iclass_xt_iclass_iitlb_args,
21435 + { 2, Iclass_xt_iclass_ritlb_args,
21437 + { 2, Iclass_xt_iclass_witlb_args,
21439 + { 3, Iclass_xt_iclass_minmax_args,
21441 + { 2, Iclass_xt_iclass_nsa_args,
21443 + { 3, Iclass_xt_iclass_sx_args,
21445 + { 3, Iclass_xt_iclass_l32ai_args,
21447 + { 3, Iclass_xt_iclass_s32ri_args,
21449 + { 3, Iclass_xt_iclass_s32c1i_args,
21450 + 2, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 },
21451 + { 1, Iclass_xt_iclass_rsr_scompare1_args,
21452 + 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 },
21453 + { 1, Iclass_xt_iclass_wsr_scompare1_args,
21454 + 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 },
21455 + { 1, Iclass_xt_iclass_xsr_scompare1_args,
21456 + 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 },
21457 + { 3, Iclass_xt_mul32_args,
21462 +/* Opcode encodings. */
21465 +Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf)
21467 + slotbuf[0] = 0x80200;
21471 +Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf)
21473 + slotbuf[0] = 0x300;
21477 +Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf)
21479 + slotbuf[0] = 0x2300;
21483 +Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf)
21485 + slotbuf[0] = 0x500;
21489 +Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf)
21491 + slotbuf[0] = 0x1500;
21495 +Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf)
21497 + slotbuf[0] = 0x5c0000;
21501 +Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf)
21503 + slotbuf[0] = 0x580000;
21507 +Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf)
21509 + slotbuf[0] = 0x540000;
21513 +Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf)
21515 + slotbuf[0] = 0xf0000;
21519 +Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
21521 + slotbuf[0] = 0xb0000;
21525 +Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
21527 + slotbuf[0] = 0x70000;
21531 +Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf)
21533 + slotbuf[0] = 0x6c0000;
21537 +Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf)
21539 + slotbuf[0] = 0x100;
21543 +Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf)
21545 + slotbuf[0] = 0x804;
21549 +Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf)
21551 + slotbuf[0] = 0x60000;
21555 +Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
21557 + slotbuf[0] = 0xd10f;
21561 +Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
21563 + slotbuf[0] = 0x4300;
21567 +Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21569 + slotbuf[0] = 0x5300;
21573 +Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
21575 + slotbuf[0] = 0x90;
21579 +Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
21581 + slotbuf[0] = 0x94;
21585 +Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
21587 + slotbuf[0] = 0x4830;
21591 +Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
21593 + slotbuf[0] = 0x4831;
21597 +Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
21599 + slotbuf[0] = 0x4816;
21603 +Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
21605 + slotbuf[0] = 0x4930;
21609 +Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
21611 + slotbuf[0] = 0x4931;
21615 +Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
21617 + slotbuf[0] = 0x4916;
21621 +Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
21623 + slotbuf[0] = 0xa000;
21627 +Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
21629 + slotbuf[0] = 0xb000;
21633 +Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
21635 + slotbuf[0] = 0xc800;
21639 +Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
21641 + slotbuf[0] = 0xcc00;
21645 +Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
21647 + slotbuf[0] = 0xd60f;
21651 +Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
21653 + slotbuf[0] = 0x8000;
21657 +Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
21659 + slotbuf[0] = 0xd000;
21663 +Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
21665 + slotbuf[0] = 0xc000;
21669 +Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
21671 + slotbuf[0] = 0xd30f;
21675 +Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
21677 + slotbuf[0] = 0xd00f;
21681 +Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
21683 + slotbuf[0] = 0x9000;
21687 +Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
21689 + slotbuf[0] = 0x7e03e;
21693 +Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
21695 + slotbuf[0] = 0xe73f;
21699 +Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf)
21701 + slotbuf[0] = 0x200c00;
21705 +Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf)
21707 + slotbuf[0] = 0x200d00;
21711 +Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf)
21713 + slotbuf[0] = 0x8;
21717 +Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf)
21719 + slotbuf[0] = 0xc;
21723 +Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
21725 + slotbuf[0] = 0x9;
21729 +Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
21731 + slotbuf[0] = 0xa;
21735 +Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
21737 + slotbuf[0] = 0xb;
21741 +Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
21743 + slotbuf[0] = 0xd;
21747 +Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
21749 + slotbuf[0] = 0xe;
21753 +Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
21755 + slotbuf[0] = 0xf;
21759 +Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf)
21761 + slotbuf[0] = 0x1;
21765 +Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf)
21767 + slotbuf[0] = 0x2;
21771 +Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf)
21773 + slotbuf[0] = 0x3;
21777 +Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf)
21779 + slotbuf[0] = 0x680000;
21783 +Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf)
21785 + slotbuf[0] = 0x690000;
21789 +Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf)
21791 + slotbuf[0] = 0x6b0000;
21795 +Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf)
21797 + slotbuf[0] = 0x6a0000;
21801 +Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf)
21803 + slotbuf[0] = 0x700600;
21807 +Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
21809 + slotbuf[0] = 0x700e00;
21813 +Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf)
21815 + slotbuf[0] = 0x6f0000;
21819 +Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf)
21821 + slotbuf[0] = 0x6e0000;
21825 +Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf)
21827 + slotbuf[0] = 0x700100;
21831 +Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf)
21833 + slotbuf[0] = 0x700900;
21837 +Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf)
21839 + slotbuf[0] = 0x700a00;
21843 +Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf)
21845 + slotbuf[0] = 0x700200;
21849 +Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21851 + slotbuf[0] = 0x700b00;
21855 +Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
21857 + slotbuf[0] = 0x700300;
21861 +Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf)
21863 + slotbuf[0] = 0x700800;
21867 +Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf)
21869 + slotbuf[0] = 0x700000;
21873 +Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf)
21875 + slotbuf[0] = 0x700400;
21879 +Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf)
21881 + slotbuf[0] = 0x700c00;
21885 +Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
21887 + slotbuf[0] = 0x700500;
21891 +Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf)
21893 + slotbuf[0] = 0x700d00;
21897 +Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
21899 + slotbuf[0] = 0x640000;
21903 +Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
21905 + slotbuf[0] = 0x650000;
21909 +Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
21911 + slotbuf[0] = 0x670000;
21915 +Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
21917 + slotbuf[0] = 0x660000;
21921 +Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf)
21923 + slotbuf[0] = 0x500000;
21927 +Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf)
21929 + slotbuf[0] = 0x30000;
21933 +Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf)
21935 + slotbuf[0] = 0x40;
21939 +Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf)
21945 +Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf)
21947 + slotbuf[0] = 0x600000;
21951 +Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf)
21953 + slotbuf[0] = 0xa0000;
21957 +Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
21959 + slotbuf[0] = 0x200100;
21963 +Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf)
21965 + slotbuf[0] = 0x200900;
21969 +Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
21971 + slotbuf[0] = 0x200200;
21975 +Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf)
21977 + slotbuf[0] = 0x100000;
21981 +Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
21983 + slotbuf[0] = 0x200000;
21987 +Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf)
21989 + slotbuf[0] = 0x6d0800;
21993 +Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
21995 + slotbuf[0] = 0x6d0900;
21999 +Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf)
22001 + slotbuf[0] = 0x6d0a00;
22005 +Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf)
22007 + slotbuf[0] = 0x200a00;
22011 +Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
22013 + slotbuf[0] = 0x38;
22017 +Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
22019 + slotbuf[0] = 0x39;
22023 +Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
22025 + slotbuf[0] = 0x3a;
22029 +Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
22031 + slotbuf[0] = 0x3b;
22035 +Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf)
22037 + slotbuf[0] = 0x6;
22041 +Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf)
22043 + slotbuf[0] = 0x1006;
22047 +Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf)
22049 + slotbuf[0] = 0xf0200;
22053 +Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf)
22055 + slotbuf[0] = 0x20000;
22059 +Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf)
22061 + slotbuf[0] = 0x200500;
22065 +Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
22067 + slotbuf[0] = 0x200600;
22071 +Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf)
22073 + slotbuf[0] = 0x200400;
22077 +Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf)
22079 + slotbuf[0] = 0x4;
22083 +Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf)
22085 + slotbuf[0] = 0x104;
22089 +Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf)
22091 + slotbuf[0] = 0x204;
22095 +Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf)
22097 + slotbuf[0] = 0x304;
22101 +Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf)
22103 + slotbuf[0] = 0x404;
22107 +Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf)
22109 + slotbuf[0] = 0x1a;
22113 +Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf)
22115 + slotbuf[0] = 0x18;
22119 +Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf)
22121 + slotbuf[0] = 0x19;
22125 +Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf)
22127 + slotbuf[0] = 0x1b;
22131 +Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf)
22133 + slotbuf[0] = 0x10;
22137 +Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf)
22139 + slotbuf[0] = 0x12;
22143 +Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf)
22145 + slotbuf[0] = 0x14;
22149 +Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf)
22151 + slotbuf[0] = 0xc0200;
22155 +Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf)
22157 + slotbuf[0] = 0xd0200;
22161 +Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf)
22163 + slotbuf[0] = 0x200;
22167 +Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
22169 + slotbuf[0] = 0x10200;
22173 +Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf)
22175 + slotbuf[0] = 0x20200;
22179 +Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
22181 + slotbuf[0] = 0x30200;
22185 +Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf)
22187 + slotbuf[0] = 0x600;
22191 +Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
22193 + slotbuf[0] = 0x130;
22197 +Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
22199 + slotbuf[0] = 0x131;
22203 +Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
22205 + slotbuf[0] = 0x116;
22209 +Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
22211 + slotbuf[0] = 0x230;
22215 +Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
22217 + slotbuf[0] = 0x231;
22221 +Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
22223 + slotbuf[0] = 0x216;
22227 +Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
22229 + slotbuf[0] = 0x30;
22233 +Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
22235 + slotbuf[0] = 0x31;
22239 +Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
22241 + slotbuf[0] = 0x16;
22245 +Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
22247 + slotbuf[0] = 0x330;
22251 +Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
22253 + slotbuf[0] = 0x331;
22257 +Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
22259 + slotbuf[0] = 0x316;
22263 +Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
22265 + slotbuf[0] = 0x530;
22269 +Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
22271 + slotbuf[0] = 0x531;
22275 +Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
22277 + slotbuf[0] = 0x516;
22281 +Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf)
22283 + slotbuf[0] = 0xb030;
22287 +Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf)
22289 + slotbuf[0] = 0xd030;
22293 +Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
22295 + slotbuf[0] = 0xe630;
22299 +Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
22301 + slotbuf[0] = 0xe631;
22305 +Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
22307 + slotbuf[0] = 0xe616;
22311 +Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22313 + slotbuf[0] = 0xb130;
22317 +Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22319 + slotbuf[0] = 0xb131;
22323 +Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22325 + slotbuf[0] = 0xb116;
22329 +Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22331 + slotbuf[0] = 0xd130;
22335 +Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22337 + slotbuf[0] = 0xd131;
22341 +Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22343 + slotbuf[0] = 0xd116;
22347 +Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
22349 + slotbuf[0] = 0xb230;
22353 +Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
22355 + slotbuf[0] = 0xb231;
22359 +Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
22361 + slotbuf[0] = 0xb216;
22365 +Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
22367 + slotbuf[0] = 0xd230;
22371 +Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
22373 + slotbuf[0] = 0xd231;
22377 +Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
22379 + slotbuf[0] = 0xd216;
22383 +Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
22385 + slotbuf[0] = 0xb330;
22389 +Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
22391 + slotbuf[0] = 0xb331;
22395 +Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
22397 + slotbuf[0] = 0xb316;
22401 +Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
22403 + slotbuf[0] = 0xd330;
22407 +Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
22409 + slotbuf[0] = 0xd331;
22413 +Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
22415 + slotbuf[0] = 0xd316;
22419 +Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
22421 + slotbuf[0] = 0xb430;
22425 +Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
22427 + slotbuf[0] = 0xb431;
22431 +Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
22433 + slotbuf[0] = 0xb416;
22437 +Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
22439 + slotbuf[0] = 0xd430;
22443 +Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
22445 + slotbuf[0] = 0xd431;
22449 +Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
22451 + slotbuf[0] = 0xd416;
22455 +Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
22457 + slotbuf[0] = 0xb530;
22461 +Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
22463 + slotbuf[0] = 0xb531;
22467 +Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
22469 + slotbuf[0] = 0xb516;
22473 +Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
22475 + slotbuf[0] = 0xd530;
22479 +Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
22481 + slotbuf[0] = 0xd531;
22485 +Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
22487 + slotbuf[0] = 0xd516;
22491 +Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
22493 + slotbuf[0] = 0xc230;
22497 +Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
22499 + slotbuf[0] = 0xc231;
22503 +Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
22505 + slotbuf[0] = 0xc216;
22509 +Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
22511 + slotbuf[0] = 0xc330;
22515 +Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
22517 + slotbuf[0] = 0xc331;
22521 +Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
22523 + slotbuf[0] = 0xc316;
22527 +Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
22529 + slotbuf[0] = 0xc430;
22533 +Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
22535 + slotbuf[0] = 0xc431;
22539 +Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
22541 + slotbuf[0] = 0xc416;
22545 +Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
22547 + slotbuf[0] = 0xc530;
22551 +Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
22553 + slotbuf[0] = 0xc531;
22557 +Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
22559 + slotbuf[0] = 0xc516;
22563 +Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
22565 + slotbuf[0] = 0xee30;
22569 +Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
22571 + slotbuf[0] = 0xee31;
22575 +Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
22577 + slotbuf[0] = 0xee16;
22581 +Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
22583 + slotbuf[0] = 0xc030;
22587 +Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
22589 + slotbuf[0] = 0xc031;
22593 +Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
22595 + slotbuf[0] = 0xc016;
22599 +Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
22601 + slotbuf[0] = 0xe830;
22605 +Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
22607 + slotbuf[0] = 0xe831;
22611 +Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
22613 + slotbuf[0] = 0xe816;
22617 +Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
22619 + slotbuf[0] = 0xf430;
22623 +Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
22625 + slotbuf[0] = 0xf431;
22629 +Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
22631 + slotbuf[0] = 0xf416;
22635 +Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22637 + slotbuf[0] = 0xf530;
22641 +Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22643 + slotbuf[0] = 0xf531;
22647 +Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22649 + slotbuf[0] = 0xf516;
22653 +Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf)
22655 + slotbuf[0] = 0xeb30;
22659 +Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
22661 + slotbuf[0] = 0xe730;
22665 +Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
22667 + slotbuf[0] = 0xe731;
22671 +Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
22673 + slotbuf[0] = 0xe716;
22677 +Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf)
22679 + slotbuf[0] = 0x10300;
22683 +Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf)
22685 + slotbuf[0] = 0x700;
22689 +Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf)
22691 + slotbuf[0] = 0xe230;
22695 +Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf)
22697 + slotbuf[0] = 0xe231;
22701 +Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf)
22703 + slotbuf[0] = 0xe331;
22707 +Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
22709 + slotbuf[0] = 0xe430;
22713 +Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
22715 + slotbuf[0] = 0xe431;
22719 +Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
22721 + slotbuf[0] = 0xe416;
22725 +Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf)
22727 + slotbuf[0] = 0x400;
22731 +Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
22733 + slotbuf[0] = 0xd20f;
22737 +Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
22739 + slotbuf[0] = 0x9030;
22743 +Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
22745 + slotbuf[0] = 0x9031;
22749 +Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
22751 + slotbuf[0] = 0x9016;
22755 +Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
22757 + slotbuf[0] = 0xa030;
22761 +Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
22763 + slotbuf[0] = 0xa031;
22767 +Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
22769 + slotbuf[0] = 0xa016;
22773 +Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22775 + slotbuf[0] = 0x9130;
22779 +Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22781 + slotbuf[0] = 0x9131;
22785 +Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22787 + slotbuf[0] = 0x9116;
22791 +Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22793 + slotbuf[0] = 0xa130;
22797 +Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22799 + slotbuf[0] = 0xa131;
22803 +Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22805 + slotbuf[0] = 0xa116;
22809 +Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
22811 + slotbuf[0] = 0x8030;
22815 +Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
22817 + slotbuf[0] = 0x8031;
22821 +Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
22823 + slotbuf[0] = 0x8016;
22827 +Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22829 + slotbuf[0] = 0x8130;
22833 +Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22835 + slotbuf[0] = 0x8131;
22839 +Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
22841 + slotbuf[0] = 0x8116;
22845 +Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
22847 + slotbuf[0] = 0x6030;
22851 +Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
22853 + slotbuf[0] = 0x6031;
22857 +Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
22859 + slotbuf[0] = 0x6016;
22863 +Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
22865 + slotbuf[0] = 0xe930;
22869 +Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
22871 + slotbuf[0] = 0xe931;
22875 +Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
22877 + slotbuf[0] = 0xe916;
22881 +Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
22883 + slotbuf[0] = 0xec30;
22887 +Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
22889 + slotbuf[0] = 0xec31;
22893 +Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
22895 + slotbuf[0] = 0xec16;
22899 +Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
22901 + slotbuf[0] = 0xed30;
22905 +Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
22907 + slotbuf[0] = 0xed31;
22911 +Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
22913 + slotbuf[0] = 0xed16;
22917 +Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
22919 + slotbuf[0] = 0x6830;
22923 +Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
22925 + slotbuf[0] = 0x6831;
22929 +Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
22931 + slotbuf[0] = 0x6816;
22935 +Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf)
22937 + slotbuf[0] = 0xe1f;
22941 +Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf)
22943 + slotbuf[0] = 0x10e1f;
22947 +Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf)
22949 + slotbuf[0] = 0x5931;
22953 +Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
22955 + slotbuf[0] = 0xea30;
22959 +Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
22961 + slotbuf[0] = 0xea31;
22965 +Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
22967 + slotbuf[0] = 0xea16;
22971 +Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
22973 + slotbuf[0] = 0xf030;
22977 +Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
22979 + slotbuf[0] = 0xf031;
22983 +Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
22985 + slotbuf[0] = 0xf016;
22989 +Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
22991 + slotbuf[0] = 0xc05;
22995 +Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
22997 + slotbuf[0] = 0xd05;
23001 +Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
23003 + slotbuf[0] = 0xb05;
23007 +Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
23009 + slotbuf[0] = 0xf05;
23013 +Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
23015 + slotbuf[0] = 0xe05;
23019 +Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
23021 + slotbuf[0] = 0x405;
23025 +Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
23027 + slotbuf[0] = 0x505;
23031 +Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
23033 + slotbuf[0] = 0x305;
23037 +Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
23039 + slotbuf[0] = 0x705;
23043 +Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
23045 + slotbuf[0] = 0x605;
23049 +Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf)
23051 + slotbuf[0] = 0x34;
23055 +Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf)
23057 + slotbuf[0] = 0x35;
23061 +Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf)
23063 + slotbuf[0] = 0x36;
23067 +Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
23069 + slotbuf[0] = 0x37;
23073 +Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf)
23075 + slotbuf[0] = 0xe04;
23079 +Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf)
23081 + slotbuf[0] = 0xf04;
23085 +Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf)
23087 + slotbuf[0] = 0x32;
23091 +Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf)
23093 + slotbuf[0] = 0x200b00;
23097 +Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf)
23099 + slotbuf[0] = 0x200f00;
23103 +Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf)
23105 + slotbuf[0] = 0x200e00;
23109 +Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
23111 + slotbuf[0] = 0xc30;
23115 +Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
23117 + slotbuf[0] = 0xc31;
23121 +Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
23123 + slotbuf[0] = 0xc16;
23127 +Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf)
23129 + slotbuf[0] = 0x28;
23133 +Opcode_muluh_Slot_inst_encode (xtensa_insnbuf slotbuf)
23135 + slotbuf[0] = 0x2a;
23139 +Opcode_mulsh_Slot_inst_encode (xtensa_insnbuf slotbuf)
23141 + slotbuf[0] = 0x2b;
23145 +Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf)
23147 + slotbuf[0] = 0x1c;
23151 +Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf)
23153 + slotbuf[0] = 0x1d;
23157 -Slot_inst16b_decode (const xtensa_insnbuf insn)
23159 - switch (Field_op0_Slot_inst16b_get (insn))
23162 - switch (Field_i_Slot_inst16b_get (insn))
23165 - return 33; /* movi.n */
23167 - switch (Field_z_Slot_inst16b_get (insn))
23170 - return 28; /* beqz.n */
23172 - return 29; /* bnez.n */
23178 - switch (Field_r_Slot_inst16b_get (insn))
23181 - return 32; /* mov.n */
23183 - switch (Field_t_Slot_inst16b_get (insn))
23186 - return 35; /* ret.n */
23188 - return 15; /* retw.n */
23190 - return 325; /* break.n */
23192 - if (Field_s_Slot_inst16b_get (insn) == 0)
23193 - return 34; /* nop.n */
23196 - if (Field_s_Slot_inst16b_get (insn) == 0)
23197 - return 30; /* ill.n */
23206 +xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = {
23207 + Opcode_excw_Slot_inst_encode, 0, 0
23210 +xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = {
23211 + Opcode_rfe_Slot_inst_encode, 0, 0
23214 +xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = {
23215 + Opcode_rfde_Slot_inst_encode, 0, 0
23218 +xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = {
23219 + Opcode_syscall_Slot_inst_encode, 0, 0
23222 +xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = {
23223 + Opcode_simcall_Slot_inst_encode, 0, 0
23226 +xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = {
23227 + Opcode_call12_Slot_inst_encode, 0, 0
23230 +xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = {
23231 + Opcode_call8_Slot_inst_encode, 0, 0
23234 +xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = {
23235 + Opcode_call4_Slot_inst_encode, 0, 0
23238 +xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = {
23239 + Opcode_callx12_Slot_inst_encode, 0, 0
23242 +xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = {
23243 + Opcode_callx8_Slot_inst_encode, 0, 0
23246 +xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = {
23247 + Opcode_callx4_Slot_inst_encode, 0, 0
23250 +xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = {
23251 + Opcode_entry_Slot_inst_encode, 0, 0
23254 +xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = {
23255 + Opcode_movsp_Slot_inst_encode, 0, 0
23258 +xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = {
23259 + Opcode_rotw_Slot_inst_encode, 0, 0
23262 +xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = {
23263 + Opcode_retw_Slot_inst_encode, 0, 0
23266 +xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = {
23267 + 0, 0, Opcode_retw_n_Slot_inst16b_encode
23270 +xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = {
23271 + Opcode_rfwo_Slot_inst_encode, 0, 0
23274 +xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = {
23275 + Opcode_rfwu_Slot_inst_encode, 0, 0
23278 +xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = {
23279 + Opcode_l32e_Slot_inst_encode, 0, 0
23282 +xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = {
23283 + Opcode_s32e_Slot_inst_encode, 0, 0
23286 +xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = {
23287 + Opcode_rsr_windowbase_Slot_inst_encode, 0, 0
23290 +xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = {
23291 + Opcode_wsr_windowbase_Slot_inst_encode, 0, 0
23294 +xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = {
23295 + Opcode_xsr_windowbase_Slot_inst_encode, 0, 0
23298 +xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = {
23299 + Opcode_rsr_windowstart_Slot_inst_encode, 0, 0
23302 +xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = {
23303 + Opcode_wsr_windowstart_Slot_inst_encode, 0, 0
23306 +xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = {
23307 + Opcode_xsr_windowstart_Slot_inst_encode, 0, 0
23310 +xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = {
23311 + 0, Opcode_add_n_Slot_inst16a_encode, 0
23314 +xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = {
23315 + 0, Opcode_addi_n_Slot_inst16a_encode, 0
23318 +xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = {
23319 + 0, 0, Opcode_beqz_n_Slot_inst16b_encode
23322 +xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = {
23323 + 0, 0, Opcode_bnez_n_Slot_inst16b_encode
23326 +xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = {
23327 + 0, 0, Opcode_ill_n_Slot_inst16b_encode
23330 +xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = {
23331 + 0, Opcode_l32i_n_Slot_inst16a_encode, 0
23334 +xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = {
23335 + 0, 0, Opcode_mov_n_Slot_inst16b_encode
23338 +xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = {
23339 + 0, 0, Opcode_movi_n_Slot_inst16b_encode
23342 +xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = {
23343 + 0, 0, Opcode_nop_n_Slot_inst16b_encode
23346 +xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = {
23347 + 0, 0, Opcode_ret_n_Slot_inst16b_encode
23350 +xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = {
23351 + 0, Opcode_s32i_n_Slot_inst16a_encode, 0
23354 +xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = {
23355 + Opcode_rur_threadptr_Slot_inst_encode, 0, 0
23358 +xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = {
23359 + Opcode_wur_threadptr_Slot_inst_encode, 0, 0
23362 +xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = {
23363 + Opcode_addi_Slot_inst_encode, 0, 0
23366 +xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = {
23367 + Opcode_addmi_Slot_inst_encode, 0, 0
23370 +xtensa_opcode_encode_fn Opcode_add_encode_fns[] = {
23371 + Opcode_add_Slot_inst_encode, 0, 0
23374 +xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = {
23375 + Opcode_sub_Slot_inst_encode, 0, 0
23378 +xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = {
23379 + Opcode_addx2_Slot_inst_encode, 0, 0
23382 +xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = {
23383 + Opcode_addx4_Slot_inst_encode, 0, 0
23386 +xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = {
23387 + Opcode_addx8_Slot_inst_encode, 0, 0
23390 +xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = {
23391 + Opcode_subx2_Slot_inst_encode, 0, 0
23394 +xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = {
23395 + Opcode_subx4_Slot_inst_encode, 0, 0
23398 +xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = {
23399 + Opcode_subx8_Slot_inst_encode, 0, 0
23402 +xtensa_opcode_encode_fn Opcode_and_encode_fns[] = {
23403 + Opcode_and_Slot_inst_encode, 0, 0
23406 +xtensa_opcode_encode_fn Opcode_or_encode_fns[] = {
23407 + Opcode_or_Slot_inst_encode, 0, 0
23410 +xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = {
23411 + Opcode_xor_Slot_inst_encode, 0, 0
23414 +xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = {
23415 + Opcode_beqi_Slot_inst_encode, 0, 0
23418 +xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = {
23419 + Opcode_bnei_Slot_inst_encode, 0, 0
23422 +xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = {
23423 + Opcode_bgei_Slot_inst_encode, 0, 0
23426 +xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = {
23427 + Opcode_blti_Slot_inst_encode, 0, 0
23430 +xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = {
23431 + Opcode_bbci_Slot_inst_encode, 0, 0
23434 +xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = {
23435 + Opcode_bbsi_Slot_inst_encode, 0, 0
23438 +xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = {
23439 + Opcode_bgeui_Slot_inst_encode, 0, 0
23442 +xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = {
23443 + Opcode_bltui_Slot_inst_encode, 0, 0
23446 +xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = {
23447 + Opcode_beq_Slot_inst_encode, 0, 0
23450 +xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = {
23451 + Opcode_bne_Slot_inst_encode, 0, 0
23454 +xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = {
23455 + Opcode_bge_Slot_inst_encode, 0, 0
23458 +xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = {
23459 + Opcode_blt_Slot_inst_encode, 0, 0
23462 +xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = {
23463 + Opcode_bgeu_Slot_inst_encode, 0, 0
23466 +xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = {
23467 + Opcode_bltu_Slot_inst_encode, 0, 0
23470 +xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = {
23471 + Opcode_bany_Slot_inst_encode, 0, 0
23474 +xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = {
23475 + Opcode_bnone_Slot_inst_encode, 0, 0
23478 +xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = {
23479 + Opcode_ball_Slot_inst_encode, 0, 0
23482 +xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = {
23483 + Opcode_bnall_Slot_inst_encode, 0, 0
23486 +xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = {
23487 + Opcode_bbc_Slot_inst_encode, 0, 0
23490 +xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = {
23491 + Opcode_bbs_Slot_inst_encode, 0, 0
23494 +xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = {
23495 + Opcode_beqz_Slot_inst_encode, 0, 0
23498 +xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = {
23499 + Opcode_bnez_Slot_inst_encode, 0, 0
23502 +xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = {
23503 + Opcode_bgez_Slot_inst_encode, 0, 0
23506 +xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = {
23507 + Opcode_bltz_Slot_inst_encode, 0, 0
23510 +xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = {
23511 + Opcode_call0_Slot_inst_encode, 0, 0
23514 +xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = {
23515 + Opcode_callx0_Slot_inst_encode, 0, 0
23518 +xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = {
23519 + Opcode_extui_Slot_inst_encode, 0, 0
23522 +xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = {
23523 + Opcode_ill_Slot_inst_encode, 0, 0
23526 +xtensa_opcode_encode_fn Opcode_j_encode_fns[] = {
23527 + Opcode_j_Slot_inst_encode, 0, 0
23530 +xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = {
23531 + Opcode_jx_Slot_inst_encode, 0, 0
23534 +xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = {
23535 + Opcode_l16ui_Slot_inst_encode, 0, 0
23538 +xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = {
23539 + Opcode_l16si_Slot_inst_encode, 0, 0
23542 +xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = {
23543 + Opcode_l32i_Slot_inst_encode, 0, 0
23546 +xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = {
23547 + Opcode_l32r_Slot_inst_encode, 0, 0
23550 +xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = {
23551 + Opcode_l8ui_Slot_inst_encode, 0, 0
23554 +xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = {
23555 + Opcode_loop_Slot_inst_encode, 0, 0
23558 +xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = {
23559 + Opcode_loopnez_Slot_inst_encode, 0, 0
23562 +xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = {
23563 + Opcode_loopgtz_Slot_inst_encode, 0, 0
23566 +xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = {
23567 + Opcode_movi_Slot_inst_encode, 0, 0
23570 +xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = {
23571 + Opcode_moveqz_Slot_inst_encode, 0, 0
23574 +xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = {
23575 + Opcode_movnez_Slot_inst_encode, 0, 0
23578 +xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = {
23579 + Opcode_movltz_Slot_inst_encode, 0, 0
23582 +xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = {
23583 + Opcode_movgez_Slot_inst_encode, 0, 0
23586 +xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = {
23587 + Opcode_neg_Slot_inst_encode, 0, 0
23590 +xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = {
23591 + Opcode_abs_Slot_inst_encode, 0, 0
23594 +xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = {
23595 + Opcode_nop_Slot_inst_encode, 0, 0
23598 +xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = {
23599 + Opcode_ret_Slot_inst_encode, 0, 0
23602 +xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = {
23603 + Opcode_s16i_Slot_inst_encode, 0, 0
23606 +xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = {
23607 + Opcode_s32i_Slot_inst_encode, 0, 0
23610 +xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = {
23611 + Opcode_s8i_Slot_inst_encode, 0, 0
23614 +xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = {
23615 + Opcode_ssr_Slot_inst_encode, 0, 0
23618 +xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = {
23619 + Opcode_ssl_Slot_inst_encode, 0, 0
23622 +xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = {
23623 + Opcode_ssa8l_Slot_inst_encode, 0, 0
23626 +xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = {
23627 + Opcode_ssa8b_Slot_inst_encode, 0, 0
23630 +xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = {
23631 + Opcode_ssai_Slot_inst_encode, 0, 0
23634 +xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = {
23635 + Opcode_sll_Slot_inst_encode, 0, 0
23638 +xtensa_opcode_encode_fn Opcode_src_encode_fns[] = {
23639 + Opcode_src_Slot_inst_encode, 0, 0
23642 +xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = {
23643 + Opcode_srl_Slot_inst_encode, 0, 0
23646 +xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = {
23647 + Opcode_sra_Slot_inst_encode, 0, 0
23650 +xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = {
23651 + Opcode_slli_Slot_inst_encode, 0, 0
23654 +xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = {
23655 + Opcode_srai_Slot_inst_encode, 0, 0
23658 +xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = {
23659 + Opcode_srli_Slot_inst_encode, 0, 0
23662 +xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = {
23663 + Opcode_memw_Slot_inst_encode, 0, 0
23666 +xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = {
23667 + Opcode_extw_Slot_inst_encode, 0, 0
23670 +xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = {
23671 + Opcode_isync_Slot_inst_encode, 0, 0
23674 +xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = {
23675 + Opcode_rsync_Slot_inst_encode, 0, 0
23678 +xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = {
23679 + Opcode_esync_Slot_inst_encode, 0, 0
23682 +xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = {
23683 + Opcode_dsync_Slot_inst_encode, 0, 0
23686 +xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = {
23687 + Opcode_rsil_Slot_inst_encode, 0, 0
23690 +xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = {
23691 + Opcode_rsr_lend_Slot_inst_encode, 0, 0
23694 +xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = {
23695 + Opcode_wsr_lend_Slot_inst_encode, 0, 0
23698 +xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = {
23699 + Opcode_xsr_lend_Slot_inst_encode, 0, 0
23702 +xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = {
23703 + Opcode_rsr_lcount_Slot_inst_encode, 0, 0
23706 +xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = {
23707 + Opcode_wsr_lcount_Slot_inst_encode, 0, 0
23710 +xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = {
23711 + Opcode_xsr_lcount_Slot_inst_encode, 0, 0
23714 +xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = {
23715 + Opcode_rsr_lbeg_Slot_inst_encode, 0, 0
23718 +xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = {
23719 + Opcode_wsr_lbeg_Slot_inst_encode, 0, 0
23722 +xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = {
23723 + Opcode_xsr_lbeg_Slot_inst_encode, 0, 0
23726 +xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = {
23727 + Opcode_rsr_sar_Slot_inst_encode, 0, 0
23730 +xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = {
23731 + Opcode_wsr_sar_Slot_inst_encode, 0, 0
23734 +xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = {
23735 + Opcode_xsr_sar_Slot_inst_encode, 0, 0
23738 +xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = {
23739 + Opcode_rsr_litbase_Slot_inst_encode, 0, 0
23742 +xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = {
23743 + Opcode_wsr_litbase_Slot_inst_encode, 0, 0
23746 +xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = {
23747 + Opcode_xsr_litbase_Slot_inst_encode, 0, 0
23750 +xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = {
23751 + Opcode_rsr_176_Slot_inst_encode, 0, 0
23754 +xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = {
23755 + Opcode_rsr_208_Slot_inst_encode, 0, 0
23758 +xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = {
23759 + Opcode_rsr_ps_Slot_inst_encode, 0, 0
23762 +xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = {
23763 + Opcode_wsr_ps_Slot_inst_encode, 0, 0
23766 +xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = {
23767 + Opcode_xsr_ps_Slot_inst_encode, 0, 0
23770 +xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = {
23771 + Opcode_rsr_epc1_Slot_inst_encode, 0, 0
23774 +xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = {
23775 + Opcode_wsr_epc1_Slot_inst_encode, 0, 0
23778 +xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = {
23779 + Opcode_xsr_epc1_Slot_inst_encode, 0, 0
23782 +xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = {
23783 + Opcode_rsr_excsave1_Slot_inst_encode, 0, 0
23786 +xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = {
23787 + Opcode_wsr_excsave1_Slot_inst_encode, 0, 0
23790 +xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = {
23791 + Opcode_xsr_excsave1_Slot_inst_encode, 0, 0
23794 +xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = {
23795 + Opcode_rsr_epc2_Slot_inst_encode, 0, 0
23798 +xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = {
23799 + Opcode_wsr_epc2_Slot_inst_encode, 0, 0
23802 +xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = {
23803 + Opcode_xsr_epc2_Slot_inst_encode, 0, 0
23806 +xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = {
23807 + Opcode_rsr_excsave2_Slot_inst_encode, 0, 0
23810 +xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = {
23811 + Opcode_wsr_excsave2_Slot_inst_encode, 0, 0
23814 +xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = {
23815 + Opcode_xsr_excsave2_Slot_inst_encode, 0, 0
23818 +xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = {
23819 + Opcode_rsr_epc3_Slot_inst_encode, 0, 0
23822 +xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = {
23823 + Opcode_wsr_epc3_Slot_inst_encode, 0, 0
23826 +xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = {
23827 + Opcode_xsr_epc3_Slot_inst_encode, 0, 0
23830 +xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = {
23831 + Opcode_rsr_excsave3_Slot_inst_encode, 0, 0
23834 +xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = {
23835 + Opcode_wsr_excsave3_Slot_inst_encode, 0, 0
23838 +xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = {
23839 + Opcode_xsr_excsave3_Slot_inst_encode, 0, 0
23842 +xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = {
23843 + Opcode_rsr_epc4_Slot_inst_encode, 0, 0
23846 +xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = {
23847 + Opcode_wsr_epc4_Slot_inst_encode, 0, 0
23850 +xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = {
23851 + Opcode_xsr_epc4_Slot_inst_encode, 0, 0
23854 +xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = {
23855 + Opcode_rsr_excsave4_Slot_inst_encode, 0, 0
23858 +xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = {
23859 + Opcode_wsr_excsave4_Slot_inst_encode, 0, 0
23862 +xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = {
23863 + Opcode_xsr_excsave4_Slot_inst_encode, 0, 0
23866 +xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = {
23867 + Opcode_rsr_epc5_Slot_inst_encode, 0, 0
23870 +xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = {
23871 + Opcode_wsr_epc5_Slot_inst_encode, 0, 0
23874 +xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = {
23875 + Opcode_xsr_epc5_Slot_inst_encode, 0, 0
23878 +xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = {
23879 + Opcode_rsr_excsave5_Slot_inst_encode, 0, 0
23882 +xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = {
23883 + Opcode_wsr_excsave5_Slot_inst_encode, 0, 0
23886 +xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = {
23887 + Opcode_xsr_excsave5_Slot_inst_encode, 0, 0
23890 +xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = {
23891 + Opcode_rsr_eps2_Slot_inst_encode, 0, 0
23894 +xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = {
23895 + Opcode_wsr_eps2_Slot_inst_encode, 0, 0
23898 +xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = {
23899 + Opcode_xsr_eps2_Slot_inst_encode, 0, 0
23902 +xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = {
23903 + Opcode_rsr_eps3_Slot_inst_encode, 0, 0
23906 +xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = {
23907 + Opcode_wsr_eps3_Slot_inst_encode, 0, 0
23910 +xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = {
23911 + Opcode_xsr_eps3_Slot_inst_encode, 0, 0
23914 +xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = {
23915 + Opcode_rsr_eps4_Slot_inst_encode, 0, 0
23918 +xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = {
23919 + Opcode_wsr_eps4_Slot_inst_encode, 0, 0
23922 +xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = {
23923 + Opcode_xsr_eps4_Slot_inst_encode, 0, 0
23926 +xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = {
23927 + Opcode_rsr_eps5_Slot_inst_encode, 0, 0
23930 +xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = {
23931 + Opcode_wsr_eps5_Slot_inst_encode, 0, 0
23934 +xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = {
23935 + Opcode_xsr_eps5_Slot_inst_encode, 0, 0
23938 +xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = {
23939 + Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0
23942 +xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = {
23943 + Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0
23946 +xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = {
23947 + Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0
23950 +xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = {
23951 + Opcode_rsr_depc_Slot_inst_encode, 0, 0
23954 +xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = {
23955 + Opcode_wsr_depc_Slot_inst_encode, 0, 0
23958 +xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = {
23959 + Opcode_xsr_depc_Slot_inst_encode, 0, 0
23962 +xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = {
23963 + Opcode_rsr_exccause_Slot_inst_encode, 0, 0
23966 +xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = {
23967 + Opcode_wsr_exccause_Slot_inst_encode, 0, 0
23970 +xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = {
23971 + Opcode_xsr_exccause_Slot_inst_encode, 0, 0
23974 +xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = {
23975 + Opcode_rsr_misc0_Slot_inst_encode, 0, 0
23978 +xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = {
23979 + Opcode_wsr_misc0_Slot_inst_encode, 0, 0
23982 +xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = {
23983 + Opcode_xsr_misc0_Slot_inst_encode, 0, 0
23986 +xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = {
23987 + Opcode_rsr_misc1_Slot_inst_encode, 0, 0
23990 +xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = {
23991 + Opcode_wsr_misc1_Slot_inst_encode, 0, 0
23994 +xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = {
23995 + Opcode_xsr_misc1_Slot_inst_encode, 0, 0
23998 +xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = {
23999 + Opcode_rsr_prid_Slot_inst_encode, 0, 0
24002 +xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = {
24003 + Opcode_rsr_vecbase_Slot_inst_encode, 0, 0
24006 +xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = {
24007 + Opcode_wsr_vecbase_Slot_inst_encode, 0, 0
24010 +xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = {
24011 + Opcode_xsr_vecbase_Slot_inst_encode, 0, 0
24014 +xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = {
24015 + Opcode_rfi_Slot_inst_encode, 0, 0
24018 +xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = {
24019 + Opcode_waiti_Slot_inst_encode, 0, 0
24022 +xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = {
24023 + Opcode_rsr_interrupt_Slot_inst_encode, 0, 0
24026 +xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = {
24027 + Opcode_wsr_intset_Slot_inst_encode, 0, 0
24030 +xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = {
24031 + Opcode_wsr_intclear_Slot_inst_encode, 0, 0
24034 +xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = {
24035 + Opcode_rsr_intenable_Slot_inst_encode, 0, 0
24038 +xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = {
24039 + Opcode_wsr_intenable_Slot_inst_encode, 0, 0
24042 +xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = {
24043 + Opcode_xsr_intenable_Slot_inst_encode, 0, 0
24046 +xtensa_opcode_encode_fn Opcode_break_encode_fns[] = {
24047 + Opcode_break_Slot_inst_encode, 0, 0
24050 +xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = {
24051 + 0, 0, Opcode_break_n_Slot_inst16b_encode
24054 +xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = {
24055 + Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0
24058 +xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = {
24059 + Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0
24062 +xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = {
24063 + Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0
24066 +xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = {
24067 + Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0
24070 +xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = {
24071 + Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0
24074 +xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = {
24075 + Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0
24078 +xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = {
24079 + Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0
24083 -Slot_inst16a_decode (const xtensa_insnbuf insn)
24085 - switch (Field_op0_Slot_inst16a_get (insn))
24088 - return 31; /* l32i.n */
24090 - return 36; /* s32i.n */
24092 - return 26; /* add.n */
24094 - return 27; /* addi.n */
24098 +xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = {
24099 + Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0
24103 -Slot_xt_flix64_slot2_decode (const xtensa_insnbuf insn)
24105 - switch (Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn))
24108 - if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 1)
24109 - return 41; /* add */
24110 - if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 5)
24111 - return 42; /* sub */
24112 - if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 2)
24113 - return 43; /* addx2 */
24114 - if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 3)
24115 - return 49; /* and */
24116 - if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 4)
24117 - return 450; /* sext */
24120 - if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 1)
24121 - return 27; /* addi.n */
24122 - if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 2)
24123 - return 44; /* addx4 */
24124 - if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 3)
24125 - return 50; /* or */
24126 - if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 5)
24127 - return 51; /* xor */
24128 - if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 4)
24129 - return 113; /* srli */
24132 - if (Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0 &&
24133 - Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6)
24134 - return 33; /* movi.n */
24135 - if (Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 2 &&
24136 - Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 &&
24137 - Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0)
24138 - return 32; /* mov.n */
24139 - if (Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 3 &&
24140 - Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 &&
24141 - Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0)
24142 - return 97; /* nop */
24143 - if (Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 8 &&
24144 - Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 &&
24145 - Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0)
24146 - return 96; /* abs */
24147 - if (Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 9 &&
24148 - Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 &&
24149 - Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0)
24150 - return 95; /* neg */
24151 - if (Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 5 &&
24152 - Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 &&
24153 - Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0)
24154 - return 110; /* sra */
24155 - if (Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 3 &&
24156 - Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 &&
24157 - Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0)
24158 - return 109; /* srl */
24159 - if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 7)
24160 - return 112; /* srai */
24163 +xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = {
24164 + Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0
24168 -Slot_xt_flix64_slot0_decode (const xtensa_insnbuf insn)
24170 - switch (Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_get (insn))
24173 - if (Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_get (insn) == 2)
24174 - return 78; /* extui */
24175 - switch (Field_op1_Slot_xt_flix64_slot0_get (insn))
24178 - switch (Field_op2_Slot_xt_flix64_slot0_get (insn))
24181 - if (Field_r_Slot_xt_flix64_slot0_get (insn) == 2)
24183 - if (Field_s_Slot_xt_flix64_slot0_get (insn) == 0)
24185 - if (Field_t_Slot_xt_flix64_slot0_get (insn) == 15)
24186 - return 97; /* nop */
24191 - return 49; /* and */
24193 - return 50; /* or */
24195 - return 51; /* xor */
24197 - switch (Field_r_Slot_xt_flix64_slot0_get (insn))
24200 - if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0)
24201 - return 102; /* ssr */
24204 - if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0)
24205 - return 103; /* ssl */
24208 - if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0)
24209 - return 104; /* ssa8l */
24212 - if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0)
24213 - return 105; /* ssa8b */
24216 - if (Field_thi3_Slot_xt_flix64_slot0_get (insn) == 0)
24217 - return 106; /* ssai */
24220 - return 448; /* nsa */
24222 - return 449; /* nsau */
24226 - switch (Field_s_Slot_xt_flix64_slot0_get (insn))
24229 - return 95; /* neg */
24231 - return 96; /* abs */
24235 - return 41; /* add */
24237 - return 43; /* addx2 */
24239 - return 44; /* addx4 */
24241 - return 45; /* addx8 */
24243 - return 42; /* sub */
24245 - return 46; /* subx2 */
24247 - return 47; /* subx4 */
24249 - return 48; /* subx8 */
24253 - if (Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_get (insn) == 1)
24254 - return 112; /* srai */
24255 - if (Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_get (insn) == 0)
24256 - return 111; /* slli */
24257 - switch (Field_op2_Slot_xt_flix64_slot0_get (insn))
24260 - return 113; /* srli */
24262 - return 108; /* src */
24264 - if (Field_s_Slot_xt_flix64_slot0_get (insn) == 0)
24265 - return 109; /* srl */
24268 - if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0)
24269 - return 107; /* sll */
24272 - if (Field_s_Slot_xt_flix64_slot0_get (insn) == 0)
24273 - return 110; /* sra */
24276 - return 296; /* mul16u */
24278 - return 297; /* mul16s */
24282 - if (Field_op2_Slot_xt_flix64_slot0_get (insn) == 8)
24283 - return 461; /* mull */
24286 - switch (Field_op2_Slot_xt_flix64_slot0_get (insn))
24289 - return 450; /* sext */
24291 - return 443; /* clamps */
24293 - return 444; /* min */
24295 - return 445; /* max */
24297 - return 446; /* minu */
24299 - return 447; /* maxu */
24301 - return 91; /* moveqz */
24303 - return 92; /* movnez */
24305 - return 93; /* movltz */
24307 - return 94; /* movgez */
24313 - switch (Field_r_Slot_xt_flix64_slot0_get (insn))
24316 - return 86; /* l8ui */
24318 - return 82; /* l16ui */
24320 - return 84; /* l32i */
24322 - return 101; /* s8i */
24324 - return 99; /* s16i */
24326 - return 100; /* s32i */
24328 - return 83; /* l16si */
24330 - return 90; /* movi */
24332 - return 39; /* addi */
24334 - return 40; /* addmi */
24338 - if (Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_get (insn) == 1)
24339 - return 85; /* l32r */
24340 - if (Field_sae4_Slot_xt_flix64_slot0_get (insn) == 0 &&
24341 - Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_get (insn) == 3 &&
24342 - Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_get (insn) == 0 &&
24343 - Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_get (insn) == 0)
24344 - return 32; /* mov.n */
24347 +xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = {
24348 + Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0
24352 -Slot_xt_flix64_slot1_decode (const xtensa_insnbuf insn)
24354 - if (Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0 &&
24355 - Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 1)
24356 - return 78; /* extui */
24357 - switch (Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn))
24360 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24361 - return 90; /* movi */
24364 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 1)
24365 - return 39; /* addi */
24368 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 1)
24369 - return 40; /* addmi */
24370 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
24371 - Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_get (insn) == 0)
24372 - return 51; /* xor */
24375 - switch (Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn))
24378 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24379 - return 111; /* slli */
24382 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24383 - return 112; /* srai */
24386 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
24387 - Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
24388 - return 107; /* sll */
24391 - switch (Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn))
24394 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24395 - return 41; /* add */
24398 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24399 - return 45; /* addx8 */
24402 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24403 - return 43; /* addx2 */
24406 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24407 - return 49; /* and */
24410 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24411 - return 91; /* moveqz */
24414 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24415 - return 94; /* movgez */
24418 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24419 - return 44; /* addx4 */
24422 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24423 - return 93; /* movltz */
24426 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24427 - return 92; /* movnez */
24430 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24431 - return 296; /* mul16u */
24434 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24435 - return 297; /* mul16s */
24438 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24439 - return 461; /* mull */
24442 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24443 - return 50; /* or */
24446 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24447 - return 450; /* sext */
24450 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24451 - return 108; /* src */
24454 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
24455 - return 113; /* srli */
24458 - if (Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 280 &&
24459 - Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
24460 - Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
24461 - return 32; /* mov.n */
24462 - if (Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 281 &&
24463 - Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
24464 - Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
24465 - return 81; /* jx */
24466 - if (Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 141 &&
24467 - Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
24468 - Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
24469 - return 103; /* ssl */
24470 - if (Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 71 &&
24471 - Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
24472 - Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
24473 - return 97; /* nop */
24474 - if (Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 148 &&
24475 - Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
24476 - Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
24477 - return 95; /* neg */
24478 - if (Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 149 &&
24479 - Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
24480 - Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
24481 - return 110; /* sra */
24482 - if (Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 75 &&
24483 - Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
24484 - Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
24485 - return 109; /* srl */
24486 - if (Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 5 &&
24487 - Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
24488 - Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
24489 - return 42; /* sub */
24490 - if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 3)
24491 - return 80; /* j */
24494 +xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = {
24495 + Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0
24498 +xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = {
24499 + Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0
24503 -Slot_xt_flix64_slot3_decode (const xtensa_insnbuf insn)
24505 - switch (Field_op0_s6_Slot_xt_flix64_slot3_get (insn))
24508 - if (Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_get (insn) == 0)
24509 - return 516; /* bbci.w18 */
24512 - if (Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_get (insn) == 0)
24513 - return 517; /* bbsi.w18 */
24516 - if (Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24517 - return 526; /* ball.w18 */
24520 - if (Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24521 - return 524; /* bany.w18 */
24524 - if (Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24525 - return 528; /* bbc.w18 */
24528 - if (Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24529 - return 529; /* bbs.w18 */
24532 - if (Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24533 - return 518; /* beq.w18 */
24536 - if (Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24537 - return 510; /* beqi.w18 */
24540 - if (Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24541 - return 520; /* bge.w18 */
24544 - if (Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24545 - return 512; /* bgei.w18 */
24548 - if (Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24549 - return 522; /* bgeu.w18 */
24552 - if (Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24553 - return 514; /* bgeui.w18 */
24556 - if (Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24557 - return 521; /* blt.w18 */
24560 - if (Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24561 - return 513; /* blti.w18 */
24564 - if (Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24565 - return 523; /* bltu.w18 */
24568 - if (Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24569 - return 515; /* bltui.w18 */
24572 - if (Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24573 - return 527; /* bnall.w18 */
24576 - if (Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24577 - return 519; /* bne.w18 */
24580 - if (Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24581 - return 511; /* bnei.w18 */
24584 - if (Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24585 - return 525; /* bnone.w18 */
24588 - if (Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24589 - return 506; /* beqz.w18 */
24592 - if (Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24593 - return 508; /* bgez.w18 */
24596 - if (Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24597 - return 509; /* bltz.w18 */
24600 - if (Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24601 - return 507; /* bnez.w18 */
24604 - if (Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
24605 - return 97; /* nop */
24610 +xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = {
24611 + Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0
24615 -/* Instruction slots. */
24616 +xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = {
24617 + Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0
24621 -Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn,
24622 - xtensa_insnbuf slotbuf)
24625 - slotbuf[0] = (insn[0] & 0xffffff);
24627 +xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = {
24628 + Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0
24632 -Slot_x24_Format_inst_0_set (xtensa_insnbuf insn,
24633 - const xtensa_insnbuf slotbuf)
24635 - insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff);
24637 +xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = {
24638 + Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0
24642 -Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn,
24643 - xtensa_insnbuf slotbuf)
24646 - slotbuf[0] = (insn[0] & 0xffff);
24648 +xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = {
24649 + Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0
24653 -Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn,
24654 - const xtensa_insnbuf slotbuf)
24656 - insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
24658 +xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = {
24659 + Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0
24663 -Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn,
24664 - xtensa_insnbuf slotbuf)
24667 - slotbuf[0] = (insn[0] & 0xffff);
24669 +xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = {
24670 + Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0
24674 -Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn,
24675 - const xtensa_insnbuf slotbuf)
24677 - insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
24679 +xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = {
24680 + Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0
24684 -Slot_xt_format1_Format_xt_flix64_slot0_4_get (const xtensa_insnbuf insn,
24685 - xtensa_insnbuf slotbuf)
24688 - slotbuf[0] = ((insn[0] & 0xffffff0) >> 4);
24690 +xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = {
24691 + Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0
24695 -Slot_xt_format1_Format_xt_flix64_slot0_4_set (xtensa_insnbuf insn,
24696 - const xtensa_insnbuf slotbuf)
24698 - insn[0] = (insn[0] & ~0xffffff0) | ((slotbuf[0] & 0xffffff) << 4);
24700 +xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = {
24701 + Opcode_rsr_debugcause_Slot_inst_encode, 0, 0
24705 -Slot_xt_format2_Format_xt_flix64_slot0_4_get (const xtensa_insnbuf insn,
24706 - xtensa_insnbuf slotbuf)
24709 - slotbuf[0] = ((insn[0] & 0xffffff0) >> 4);
24711 +xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = {
24712 + Opcode_wsr_debugcause_Slot_inst_encode, 0, 0
24716 -Slot_xt_format2_Format_xt_flix64_slot0_4_set (xtensa_insnbuf insn,
24717 - const xtensa_insnbuf slotbuf)
24719 - insn[0] = (insn[0] & ~0xffffff0) | ((slotbuf[0] & 0xffffff) << 4);
24721 +xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = {
24722 + Opcode_xsr_debugcause_Slot_inst_encode, 0, 0
24726 -Slot_xt_format1_Format_xt_flix64_slot1_28_get (const xtensa_insnbuf insn,
24727 - xtensa_insnbuf slotbuf)
24730 - slotbuf[0] = ((insn[0] & 0xf0000000) >> 28);
24731 - slotbuf[0] = (slotbuf[0] & ~0xffff0) | ((insn[1] & 0xffff) << 4);
24733 +xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = {
24734 + Opcode_rsr_icount_Slot_inst_encode, 0, 0
24738 -Slot_xt_format1_Format_xt_flix64_slot1_28_set (xtensa_insnbuf insn,
24739 - const xtensa_insnbuf slotbuf)
24741 - insn[0] = (insn[0] & ~0xf0000000) | ((slotbuf[0] & 0xf) << 28);
24742 - insn[1] = (insn[1] & ~0xffff) | ((slotbuf[0] & 0xffff0) >> 4);
24744 +xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = {
24745 + Opcode_wsr_icount_Slot_inst_encode, 0, 0
24749 -Slot_xt_format1_Format_xt_flix64_slot2_48_get (const xtensa_insnbuf insn,
24750 - xtensa_insnbuf slotbuf)
24753 - slotbuf[0] = ((insn[1] & 0xffff0000) >> 16);
24755 +xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = {
24756 + Opcode_xsr_icount_Slot_inst_encode, 0, 0
24760 -Slot_xt_format1_Format_xt_flix64_slot2_48_set (xtensa_insnbuf insn,
24761 - const xtensa_insnbuf slotbuf)
24763 - insn[1] = (insn[1] & ~0xffff0000) | ((slotbuf[0] & 0xffff) << 16);
24765 +xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = {
24766 + Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0
24770 -Slot_xt_format2_Format_xt_flix64_slot3_28_get (const xtensa_insnbuf insn,
24771 - xtensa_insnbuf slotbuf)
24773 - slotbuf[0] = ((insn[0] & 0xf0000000) >> 28);
24774 - slotbuf[0] = (slotbuf[0] & ~0xfffffff0) | ((insn[1] & 0xfffffff) << 4);
24775 - slotbuf[1] = ((insn[1] & 0x70000000) >> 28);
24777 +xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = {
24778 + Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0
24782 -Slot_xt_format2_Format_xt_flix64_slot3_28_set (xtensa_insnbuf insn,
24783 - const xtensa_insnbuf slotbuf)
24785 - insn[0] = (insn[0] & ~0xf0000000) | ((slotbuf[0] & 0xf) << 28);
24786 - insn[1] = (insn[1] & ~0xfffffff) | ((slotbuf[0] & 0xfffffff0) >> 4);
24787 - insn[1] = (insn[1] & ~0x70000000) | ((slotbuf[1] & 0x7) << 28);
24789 +xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = {
24790 + Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0
24793 -static xtensa_get_field_fn
24794 -Slot_inst_get_field_fns[] = {
24795 - Field_t_Slot_inst_get,
24796 - Field_bbi4_Slot_inst_get,
24797 - Field_bbi_Slot_inst_get,
24798 - Field_imm12_Slot_inst_get,
24799 - Field_imm8_Slot_inst_get,
24800 - Field_s_Slot_inst_get,
24801 - Field_imm12b_Slot_inst_get,
24802 - Field_imm16_Slot_inst_get,
24803 - Field_m_Slot_inst_get,
24804 - Field_n_Slot_inst_get,
24805 - Field_offset_Slot_inst_get,
24806 - Field_op0_Slot_inst_get,
24807 - Field_op1_Slot_inst_get,
24808 - Field_op2_Slot_inst_get,
24809 - Field_r_Slot_inst_get,
24810 - Field_sa4_Slot_inst_get,
24811 - Field_sae4_Slot_inst_get,
24812 - Field_sae_Slot_inst_get,
24813 - Field_sal_Slot_inst_get,
24814 - Field_sargt_Slot_inst_get,
24815 - Field_sas4_Slot_inst_get,
24816 - Field_sas_Slot_inst_get,
24817 - Field_sr_Slot_inst_get,
24818 - Field_st_Slot_inst_get,
24819 - Field_thi3_Slot_inst_get,
24820 - Field_imm4_Slot_inst_get,
24821 - Field_mn_Slot_inst_get,
24830 - Field_r3_Slot_inst_get,
24831 - Field_rbit2_Slot_inst_get,
24832 - Field_rhi_Slot_inst_get,
24833 - Field_t3_Slot_inst_get,
24834 - Field_tbit2_Slot_inst_get,
24835 - Field_tlo_Slot_inst_get,
24836 - Field_w_Slot_inst_get,
24837 - Field_y_Slot_inst_get,
24838 - Field_x_Slot_inst_get,
24839 - Field_t2_Slot_inst_get,
24840 - Field_s2_Slot_inst_get,
24841 - Field_r2_Slot_inst_get,
24842 - Field_t4_Slot_inst_get,
24843 - Field_s4_Slot_inst_get,
24844 - Field_r4_Slot_inst_get,
24845 - Field_t8_Slot_inst_get,
24846 - Field_s8_Slot_inst_get,
24847 - Field_r8_Slot_inst_get,
24848 - Field_xt_wbr15_imm_Slot_inst_get,
24849 - Field_xt_wbr18_imm_Slot_inst_get,
24918 - Implicit_Field_ar0_get,
24919 - Implicit_Field_ar4_get,
24920 - Implicit_Field_ar8_get,
24921 - Implicit_Field_ar12_get,
24922 - Implicit_Field_mr0_get,
24923 - Implicit_Field_mr1_get,
24924 - Implicit_Field_mr2_get,
24925 - Implicit_Field_mr3_get,
24926 - Implicit_Field_bt16_get,
24927 - Implicit_Field_bs16_get,
24928 - Implicit_Field_br16_get,
24929 - Implicit_Field_brall_get
24930 +xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = {
24931 + Opcode_rsr_ddr_Slot_inst_encode, 0, 0
24934 +xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = {
24935 + Opcode_wsr_ddr_Slot_inst_encode, 0, 0
24938 -static xtensa_set_field_fn
24939 -Slot_inst_set_field_fns[] = {
24940 - Field_t_Slot_inst_set,
24941 - Field_bbi4_Slot_inst_set,
24942 - Field_bbi_Slot_inst_set,
24943 - Field_imm12_Slot_inst_set,
24944 - Field_imm8_Slot_inst_set,
24945 - Field_s_Slot_inst_set,
24946 - Field_imm12b_Slot_inst_set,
24947 - Field_imm16_Slot_inst_set,
24948 - Field_m_Slot_inst_set,
24949 - Field_n_Slot_inst_set,
24950 - Field_offset_Slot_inst_set,
24951 - Field_op0_Slot_inst_set,
24952 - Field_op1_Slot_inst_set,
24953 - Field_op2_Slot_inst_set,
24954 - Field_r_Slot_inst_set,
24955 - Field_sa4_Slot_inst_set,
24956 - Field_sae4_Slot_inst_set,
24957 - Field_sae_Slot_inst_set,
24958 - Field_sal_Slot_inst_set,
24959 - Field_sargt_Slot_inst_set,
24960 - Field_sas4_Slot_inst_set,
24961 - Field_sas_Slot_inst_set,
24962 - Field_sr_Slot_inst_set,
24963 - Field_st_Slot_inst_set,
24964 - Field_thi3_Slot_inst_set,
24965 - Field_imm4_Slot_inst_set,
24966 - Field_mn_Slot_inst_set,
24975 - Field_r3_Slot_inst_set,
24976 - Field_rbit2_Slot_inst_set,
24977 - Field_rhi_Slot_inst_set,
24978 - Field_t3_Slot_inst_set,
24979 - Field_tbit2_Slot_inst_set,
24980 - Field_tlo_Slot_inst_set,
24981 - Field_w_Slot_inst_set,
24982 - Field_y_Slot_inst_set,
24983 - Field_x_Slot_inst_set,
24984 - Field_t2_Slot_inst_set,
24985 - Field_s2_Slot_inst_set,
24986 - Field_r2_Slot_inst_set,
24987 - Field_t4_Slot_inst_set,
24988 - Field_s4_Slot_inst_set,
24989 - Field_r4_Slot_inst_set,
24990 - Field_t8_Slot_inst_set,
24991 - Field_s8_Slot_inst_set,
24992 - Field_r8_Slot_inst_set,
24993 - Field_xt_wbr15_imm_Slot_inst_set,
24994 - Field_xt_wbr18_imm_Slot_inst_set,
25063 - Implicit_Field_set,
25064 - Implicit_Field_set,
25065 - Implicit_Field_set,
25066 - Implicit_Field_set,
25067 - Implicit_Field_set,
25068 - Implicit_Field_set,
25069 - Implicit_Field_set,
25070 - Implicit_Field_set,
25071 - Implicit_Field_set,
25072 - Implicit_Field_set,
25073 - Implicit_Field_set,
25074 - Implicit_Field_set
25075 +xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = {
25076 + Opcode_xsr_ddr_Slot_inst_encode, 0, 0
25079 -static xtensa_get_field_fn
25080 -Slot_inst16a_get_field_fns[] = {
25081 - Field_t_Slot_inst16a_get,
25086 - Field_s_Slot_inst16a_get,
25092 - Field_op0_Slot_inst16a_get,
25095 - Field_r_Slot_inst16a_get,
25103 - Field_sr_Slot_inst16a_get,
25104 - Field_st_Slot_inst16a_get,
25106 - Field_imm4_Slot_inst16a_get,
25108 - Field_i_Slot_inst16a_get,
25109 - Field_imm6lo_Slot_inst16a_get,
25110 - Field_imm6hi_Slot_inst16a_get,
25111 - Field_imm7lo_Slot_inst16a_get,
25112 - Field_imm7hi_Slot_inst16a_get,
25113 - Field_z_Slot_inst16a_get,
25114 - Field_imm6_Slot_inst16a_get,
25115 - Field_imm7_Slot_inst16a_get,
25125 - Field_t2_Slot_inst16a_get,
25126 - Field_s2_Slot_inst16a_get,
25127 - Field_r2_Slot_inst16a_get,
25128 - Field_t4_Slot_inst16a_get,
25129 - Field_s4_Slot_inst16a_get,
25130 - Field_r4_Slot_inst16a_get,
25131 - Field_t8_Slot_inst16a_get,
25132 - Field_s8_Slot_inst16a_get,
25133 - Field_r8_Slot_inst16a_get,
25204 - Implicit_Field_ar0_get,
25205 - Implicit_Field_ar4_get,
25206 - Implicit_Field_ar8_get,
25207 - Implicit_Field_ar12_get,
25208 - Implicit_Field_mr0_get,
25209 - Implicit_Field_mr1_get,
25210 - Implicit_Field_mr2_get,
25211 - Implicit_Field_mr3_get,
25212 - Implicit_Field_bt16_get,
25213 - Implicit_Field_bs16_get,
25214 - Implicit_Field_br16_get,
25215 - Implicit_Field_brall_get
25216 +xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = {
25217 + Opcode_rfdo_Slot_inst_encode, 0, 0
25220 +xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = {
25221 + Opcode_rfdd_Slot_inst_encode, 0, 0
25224 +xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = {
25225 + Opcode_wsr_mmid_Slot_inst_encode, 0, 0
25228 +xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = {
25229 + Opcode_rsr_ccount_Slot_inst_encode, 0, 0
25232 +xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = {
25233 + Opcode_wsr_ccount_Slot_inst_encode, 0, 0
25236 +xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = {
25237 + Opcode_xsr_ccount_Slot_inst_encode, 0, 0
25240 -static xtensa_set_field_fn
25241 -Slot_inst16a_set_field_fns[] = {
25242 - Field_t_Slot_inst16a_set,
25247 - Field_s_Slot_inst16a_set,
25253 - Field_op0_Slot_inst16a_set,
25256 - Field_r_Slot_inst16a_set,
25264 - Field_sr_Slot_inst16a_set,
25265 - Field_st_Slot_inst16a_set,
25267 - Field_imm4_Slot_inst16a_set,
25269 - Field_i_Slot_inst16a_set,
25270 - Field_imm6lo_Slot_inst16a_set,
25271 - Field_imm6hi_Slot_inst16a_set,
25272 - Field_imm7lo_Slot_inst16a_set,
25273 - Field_imm7hi_Slot_inst16a_set,
25274 - Field_z_Slot_inst16a_set,
25275 - Field_imm6_Slot_inst16a_set,
25276 - Field_imm7_Slot_inst16a_set,
25286 - Field_t2_Slot_inst16a_set,
25287 - Field_s2_Slot_inst16a_set,
25288 - Field_r2_Slot_inst16a_set,
25289 - Field_t4_Slot_inst16a_set,
25290 - Field_s4_Slot_inst16a_set,
25291 - Field_r4_Slot_inst16a_set,
25292 - Field_t8_Slot_inst16a_set,
25293 - Field_s8_Slot_inst16a_set,
25294 - Field_r8_Slot_inst16a_set,
25365 - Implicit_Field_set,
25366 - Implicit_Field_set,
25367 - Implicit_Field_set,
25368 - Implicit_Field_set,
25369 - Implicit_Field_set,
25370 - Implicit_Field_set,
25371 - Implicit_Field_set,
25372 - Implicit_Field_set,
25373 - Implicit_Field_set,
25374 - Implicit_Field_set,
25375 - Implicit_Field_set,
25376 - Implicit_Field_set
25377 +xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = {
25378 + Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0
25381 -static xtensa_get_field_fn
25382 -Slot_inst16b_get_field_fns[] = {
25383 - Field_t_Slot_inst16b_get,
25388 - Field_s_Slot_inst16b_get,
25394 - Field_op0_Slot_inst16b_get,
25397 - Field_r_Slot_inst16b_get,
25405 - Field_sr_Slot_inst16b_get,
25406 - Field_st_Slot_inst16b_get,
25408 - Field_imm4_Slot_inst16b_get,
25410 - Field_i_Slot_inst16b_get,
25411 - Field_imm6lo_Slot_inst16b_get,
25412 - Field_imm6hi_Slot_inst16b_get,
25413 - Field_imm7lo_Slot_inst16b_get,
25414 - Field_imm7hi_Slot_inst16b_get,
25415 - Field_z_Slot_inst16b_get,
25416 - Field_imm6_Slot_inst16b_get,
25417 - Field_imm7_Slot_inst16b_get,
25427 - Field_t2_Slot_inst16b_get,
25428 - Field_s2_Slot_inst16b_get,
25429 - Field_r2_Slot_inst16b_get,
25430 - Field_t4_Slot_inst16b_get,
25431 - Field_s4_Slot_inst16b_get,
25432 - Field_r4_Slot_inst16b_get,
25433 - Field_t8_Slot_inst16b_get,
25434 - Field_s8_Slot_inst16b_get,
25435 - Field_r8_Slot_inst16b_get,
25506 - Implicit_Field_ar0_get,
25507 - Implicit_Field_ar4_get,
25508 - Implicit_Field_ar8_get,
25509 - Implicit_Field_ar12_get,
25510 - Implicit_Field_mr0_get,
25511 - Implicit_Field_mr1_get,
25512 - Implicit_Field_mr2_get,
25513 - Implicit_Field_mr3_get,
25514 - Implicit_Field_bt16_get,
25515 - Implicit_Field_bs16_get,
25516 - Implicit_Field_br16_get,
25517 - Implicit_Field_brall_get
25518 +xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = {
25519 + Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0
25522 +xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = {
25523 + Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0
25526 +xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = {
25527 + Opcode_idtlb_Slot_inst_encode, 0, 0
25530 -static xtensa_set_field_fn
25531 -Slot_inst16b_set_field_fns[] = {
25532 - Field_t_Slot_inst16b_set,
25537 - Field_s_Slot_inst16b_set,
25543 - Field_op0_Slot_inst16b_set,
25546 - Field_r_Slot_inst16b_set,
25554 - Field_sr_Slot_inst16b_set,
25555 - Field_st_Slot_inst16b_set,
25557 - Field_imm4_Slot_inst16b_set,
25559 - Field_i_Slot_inst16b_set,
25560 - Field_imm6lo_Slot_inst16b_set,
25561 - Field_imm6hi_Slot_inst16b_set,
25562 - Field_imm7lo_Slot_inst16b_set,
25563 - Field_imm7hi_Slot_inst16b_set,
25564 - Field_z_Slot_inst16b_set,
25565 - Field_imm6_Slot_inst16b_set,
25566 - Field_imm7_Slot_inst16b_set,
25576 - Field_t2_Slot_inst16b_set,
25577 - Field_s2_Slot_inst16b_set,
25578 - Field_r2_Slot_inst16b_set,
25579 - Field_t4_Slot_inst16b_set,
25580 - Field_s4_Slot_inst16b_set,
25581 - Field_r4_Slot_inst16b_set,
25582 - Field_t8_Slot_inst16b_set,
25583 - Field_s8_Slot_inst16b_set,
25584 - Field_r8_Slot_inst16b_set,
25655 - Implicit_Field_set,
25656 - Implicit_Field_set,
25657 - Implicit_Field_set,
25658 - Implicit_Field_set,
25659 - Implicit_Field_set,
25660 - Implicit_Field_set,
25661 - Implicit_Field_set,
25662 - Implicit_Field_set,
25663 - Implicit_Field_set,
25664 - Implicit_Field_set,
25665 - Implicit_Field_set,
25666 - Implicit_Field_set
25667 +xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = {
25668 + Opcode_pdtlb_Slot_inst_encode, 0, 0
25671 -static xtensa_get_field_fn
25672 -Slot_xt_flix64_slot0_get_field_fns[] = {
25673 - Field_t_Slot_xt_flix64_slot0_get,
25677 - Field_imm8_Slot_xt_flix64_slot0_get,
25678 - Field_s_Slot_xt_flix64_slot0_get,
25679 - Field_imm12b_Slot_xt_flix64_slot0_get,
25680 - Field_imm16_Slot_xt_flix64_slot0_get,
25681 - Field_m_Slot_xt_flix64_slot0_get,
25682 - Field_n_Slot_xt_flix64_slot0_get,
25685 - Field_op1_Slot_xt_flix64_slot0_get,
25686 - Field_op2_Slot_xt_flix64_slot0_get,
25687 - Field_r_Slot_xt_flix64_slot0_get,
25689 - Field_sae4_Slot_xt_flix64_slot0_get,
25690 - Field_sae_Slot_xt_flix64_slot0_get,
25691 - Field_sal_Slot_xt_flix64_slot0_get,
25692 - Field_sargt_Slot_xt_flix64_slot0_get,
25694 - Field_sas_Slot_xt_flix64_slot0_get,
25697 - Field_thi3_Slot_xt_flix64_slot0_get,
25728 - Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_get,
25729 - Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_get,
25730 - Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_get,
25731 - Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_get,
25732 - Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_get,
25733 - Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_get,
25795 - Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_get,
25796 - Implicit_Field_ar0_get,
25797 - Implicit_Field_ar4_get,
25798 - Implicit_Field_ar8_get,
25799 - Implicit_Field_ar12_get,
25800 - Implicit_Field_mr0_get,
25801 - Implicit_Field_mr1_get,
25802 - Implicit_Field_mr2_get,
25803 - Implicit_Field_mr3_get,
25804 - Implicit_Field_bt16_get,
25805 - Implicit_Field_bs16_get,
25806 - Implicit_Field_br16_get,
25807 - Implicit_Field_brall_get
25808 +xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = {
25809 + Opcode_rdtlb0_Slot_inst_encode, 0, 0
25812 +xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = {
25813 + Opcode_rdtlb1_Slot_inst_encode, 0, 0
25816 +xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = {
25817 + Opcode_wdtlb_Slot_inst_encode, 0, 0
25820 +xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = {
25821 + Opcode_iitlb_Slot_inst_encode, 0, 0
25824 +xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = {
25825 + Opcode_pitlb_Slot_inst_encode, 0, 0
25828 +xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = {
25829 + Opcode_ritlb0_Slot_inst_encode, 0, 0
25832 +xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = {
25833 + Opcode_ritlb1_Slot_inst_encode, 0, 0
25836 +xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = {
25837 + Opcode_witlb_Slot_inst_encode, 0, 0
25840 +xtensa_opcode_encode_fn Opcode_min_encode_fns[] = {
25841 + Opcode_min_Slot_inst_encode, 0, 0
25844 +xtensa_opcode_encode_fn Opcode_max_encode_fns[] = {
25845 + Opcode_max_Slot_inst_encode, 0, 0
25848 +xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = {
25849 + Opcode_minu_Slot_inst_encode, 0, 0
25852 +xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = {
25853 + Opcode_maxu_Slot_inst_encode, 0, 0
25856 +xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = {
25857 + Opcode_nsa_Slot_inst_encode, 0, 0
25860 +xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = {
25861 + Opcode_nsau_Slot_inst_encode, 0, 0
25864 +xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = {
25865 + Opcode_sext_Slot_inst_encode, 0, 0
25868 +xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = {
25869 + Opcode_l32ai_Slot_inst_encode, 0, 0
25872 +xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = {
25873 + Opcode_s32ri_Slot_inst_encode, 0, 0
25876 +xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = {
25877 + Opcode_s32c1i_Slot_inst_encode, 0, 0
25880 +xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = {
25881 + Opcode_rsr_scompare1_Slot_inst_encode, 0, 0
25884 +xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = {
25885 + Opcode_wsr_scompare1_Slot_inst_encode, 0, 0
25888 +xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = {
25889 + Opcode_xsr_scompare1_Slot_inst_encode, 0, 0
25892 +xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = {
25893 + Opcode_mull_Slot_inst_encode, 0, 0
25896 +xtensa_opcode_encode_fn Opcode_muluh_encode_fns[] = {
25897 + Opcode_muluh_Slot_inst_encode, 0, 0
25900 +xtensa_opcode_encode_fn Opcode_mulsh_encode_fns[] = {
25901 + Opcode_mulsh_Slot_inst_encode, 0, 0
25904 +xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = {
25905 + Opcode_mul16u_Slot_inst_encode, 0, 0
25908 +xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = {
25909 + Opcode_mul16s_Slot_inst_encode, 0, 0
25913 +/* Opcode table. */
25915 +static xtensa_opcode_internal opcodes[] = {
25916 + { "excw", 0 /* xt_iclass_excw */,
25918 + Opcode_excw_encode_fns, 0, 0 },
25919 + { "rfe", 1 /* xt_iclass_rfe */,
25920 + XTENSA_OPCODE_IS_JUMP,
25921 + Opcode_rfe_encode_fns, 0, 0 },
25922 + { "rfde", 2 /* xt_iclass_rfde */,
25923 + XTENSA_OPCODE_IS_JUMP,
25924 + Opcode_rfde_encode_fns, 0, 0 },
25925 + { "syscall", 3 /* xt_iclass_syscall */,
25927 + Opcode_syscall_encode_fns, 0, 0 },
25928 + { "simcall", 4 /* xt_iclass_simcall */,
25930 + Opcode_simcall_encode_fns, 0, 0 },
25931 + { "call12", 5 /* xt_iclass_call12 */,
25932 + XTENSA_OPCODE_IS_CALL,
25933 + Opcode_call12_encode_fns, 0, 0 },
25934 + { "call8", 6 /* xt_iclass_call8 */,
25935 + XTENSA_OPCODE_IS_CALL,
25936 + Opcode_call8_encode_fns, 0, 0 },
25937 + { "call4", 7 /* xt_iclass_call4 */,
25938 + XTENSA_OPCODE_IS_CALL,
25939 + Opcode_call4_encode_fns, 0, 0 },
25940 + { "callx12", 8 /* xt_iclass_callx12 */,
25941 + XTENSA_OPCODE_IS_CALL,
25942 + Opcode_callx12_encode_fns, 0, 0 },
25943 + { "callx8", 9 /* xt_iclass_callx8 */,
25944 + XTENSA_OPCODE_IS_CALL,
25945 + Opcode_callx8_encode_fns, 0, 0 },
25946 + { "callx4", 10 /* xt_iclass_callx4 */,
25947 + XTENSA_OPCODE_IS_CALL,
25948 + Opcode_callx4_encode_fns, 0, 0 },
25949 + { "entry", 11 /* xt_iclass_entry */,
25951 + Opcode_entry_encode_fns, 0, 0 },
25952 + { "movsp", 12 /* xt_iclass_movsp */,
25954 + Opcode_movsp_encode_fns, 0, 0 },
25955 + { "rotw", 13 /* xt_iclass_rotw */,
25957 + Opcode_rotw_encode_fns, 0, 0 },
25958 + { "retw", 14 /* xt_iclass_retw */,
25959 + XTENSA_OPCODE_IS_JUMP,
25960 + Opcode_retw_encode_fns, 0, 0 },
25961 + { "retw.n", 14 /* xt_iclass_retw */,
25962 + XTENSA_OPCODE_IS_JUMP,
25963 + Opcode_retw_n_encode_fns, 0, 0 },
25964 + { "rfwo", 15 /* xt_iclass_rfwou */,
25965 + XTENSA_OPCODE_IS_JUMP,
25966 + Opcode_rfwo_encode_fns, 0, 0 },
25967 + { "rfwu", 15 /* xt_iclass_rfwou */,
25968 + XTENSA_OPCODE_IS_JUMP,
25969 + Opcode_rfwu_encode_fns, 0, 0 },
25970 + { "l32e", 16 /* xt_iclass_l32e */,
25972 + Opcode_l32e_encode_fns, 0, 0 },
25973 + { "s32e", 17 /* xt_iclass_s32e */,
25975 + Opcode_s32e_encode_fns, 0, 0 },
25976 + { "rsr.windowbase", 18 /* xt_iclass_rsr.windowbase */,
25978 + Opcode_rsr_windowbase_encode_fns, 0, 0 },
25979 + { "wsr.windowbase", 19 /* xt_iclass_wsr.windowbase */,
25981 + Opcode_wsr_windowbase_encode_fns, 0, 0 },
25982 + { "xsr.windowbase", 20 /* xt_iclass_xsr.windowbase */,
25984 + Opcode_xsr_windowbase_encode_fns, 0, 0 },
25985 + { "rsr.windowstart", 21 /* xt_iclass_rsr.windowstart */,
25987 + Opcode_rsr_windowstart_encode_fns, 0, 0 },
25988 + { "wsr.windowstart", 22 /* xt_iclass_wsr.windowstart */,
25990 + Opcode_wsr_windowstart_encode_fns, 0, 0 },
25991 + { "xsr.windowstart", 23 /* xt_iclass_xsr.windowstart */,
25993 + Opcode_xsr_windowstart_encode_fns, 0, 0 },
25994 + { "add.n", 24 /* xt_iclass_add.n */,
25996 + Opcode_add_n_encode_fns, 0, 0 },
25997 + { "addi.n", 25 /* xt_iclass_addi.n */,
25999 + Opcode_addi_n_encode_fns, 0, 0 },
26000 + { "beqz.n", 26 /* xt_iclass_bz6 */,
26001 + XTENSA_OPCODE_IS_BRANCH,
26002 + Opcode_beqz_n_encode_fns, 0, 0 },
26003 + { "bnez.n", 26 /* xt_iclass_bz6 */,
26004 + XTENSA_OPCODE_IS_BRANCH,
26005 + Opcode_bnez_n_encode_fns, 0, 0 },
26006 + { "ill.n", 27 /* xt_iclass_ill.n */,
26008 + Opcode_ill_n_encode_fns, 0, 0 },
26009 + { "l32i.n", 28 /* xt_iclass_loadi4 */,
26011 + Opcode_l32i_n_encode_fns, 0, 0 },
26012 + { "mov.n", 29 /* xt_iclass_mov.n */,
26014 + Opcode_mov_n_encode_fns, 0, 0 },
26015 + { "movi.n", 30 /* xt_iclass_movi.n */,
26017 + Opcode_movi_n_encode_fns, 0, 0 },
26018 + { "nop.n", 31 /* xt_iclass_nopn */,
26020 + Opcode_nop_n_encode_fns, 0, 0 },
26021 + { "ret.n", 32 /* xt_iclass_retn */,
26022 + XTENSA_OPCODE_IS_JUMP,
26023 + Opcode_ret_n_encode_fns, 0, 0 },
26024 + { "s32i.n", 33 /* xt_iclass_storei4 */,
26026 + Opcode_s32i_n_encode_fns, 0, 0 },
26027 + { "rur.threadptr", 34 /* rur_threadptr */,
26029 + Opcode_rur_threadptr_encode_fns, 0, 0 },
26030 + { "wur.threadptr", 35 /* wur_threadptr */,
26032 + Opcode_wur_threadptr_encode_fns, 0, 0 },
26033 + { "addi", 36 /* xt_iclass_addi */,
26035 + Opcode_addi_encode_fns, 0, 0 },
26036 + { "addmi", 37 /* xt_iclass_addmi */,
26038 + Opcode_addmi_encode_fns, 0, 0 },
26039 + { "add", 38 /* xt_iclass_addsub */,
26041 + Opcode_add_encode_fns, 0, 0 },
26042 + { "sub", 38 /* xt_iclass_addsub */,
26044 + Opcode_sub_encode_fns, 0, 0 },
26045 + { "addx2", 38 /* xt_iclass_addsub */,
26047 + Opcode_addx2_encode_fns, 0, 0 },
26048 + { "addx4", 38 /* xt_iclass_addsub */,
26050 + Opcode_addx4_encode_fns, 0, 0 },
26051 + { "addx8", 38 /* xt_iclass_addsub */,
26053 + Opcode_addx8_encode_fns, 0, 0 },
26054 + { "subx2", 38 /* xt_iclass_addsub */,
26056 + Opcode_subx2_encode_fns, 0, 0 },
26057 + { "subx4", 38 /* xt_iclass_addsub */,
26059 + Opcode_subx4_encode_fns, 0, 0 },
26060 + { "subx8", 38 /* xt_iclass_addsub */,
26062 + Opcode_subx8_encode_fns, 0, 0 },
26063 + { "and", 39 /* xt_iclass_bit */,
26065 + Opcode_and_encode_fns, 0, 0 },
26066 + { "or", 39 /* xt_iclass_bit */,
26068 + Opcode_or_encode_fns, 0, 0 },
26069 + { "xor", 39 /* xt_iclass_bit */,
26071 + Opcode_xor_encode_fns, 0, 0 },
26072 + { "beqi", 40 /* xt_iclass_bsi8 */,
26073 + XTENSA_OPCODE_IS_BRANCH,
26074 + Opcode_beqi_encode_fns, 0, 0 },
26075 + { "bnei", 40 /* xt_iclass_bsi8 */,
26076 + XTENSA_OPCODE_IS_BRANCH,
26077 + Opcode_bnei_encode_fns, 0, 0 },
26078 + { "bgei", 40 /* xt_iclass_bsi8 */,
26079 + XTENSA_OPCODE_IS_BRANCH,
26080 + Opcode_bgei_encode_fns, 0, 0 },
26081 + { "blti", 40 /* xt_iclass_bsi8 */,
26082 + XTENSA_OPCODE_IS_BRANCH,
26083 + Opcode_blti_encode_fns, 0, 0 },
26084 + { "bbci", 41 /* xt_iclass_bsi8b */,
26085 + XTENSA_OPCODE_IS_BRANCH,
26086 + Opcode_bbci_encode_fns, 0, 0 },
26087 + { "bbsi", 41 /* xt_iclass_bsi8b */,
26088 + XTENSA_OPCODE_IS_BRANCH,
26089 + Opcode_bbsi_encode_fns, 0, 0 },
26090 + { "bgeui", 42 /* xt_iclass_bsi8u */,
26091 + XTENSA_OPCODE_IS_BRANCH,
26092 + Opcode_bgeui_encode_fns, 0, 0 },
26093 + { "bltui", 42 /* xt_iclass_bsi8u */,
26094 + XTENSA_OPCODE_IS_BRANCH,
26095 + Opcode_bltui_encode_fns, 0, 0 },
26096 + { "beq", 43 /* xt_iclass_bst8 */,
26097 + XTENSA_OPCODE_IS_BRANCH,
26098 + Opcode_beq_encode_fns, 0, 0 },
26099 + { "bne", 43 /* xt_iclass_bst8 */,
26100 + XTENSA_OPCODE_IS_BRANCH,
26101 + Opcode_bne_encode_fns, 0, 0 },
26102 + { "bge", 43 /* xt_iclass_bst8 */,
26103 + XTENSA_OPCODE_IS_BRANCH,
26104 + Opcode_bge_encode_fns, 0, 0 },
26105 + { "blt", 43 /* xt_iclass_bst8 */,
26106 + XTENSA_OPCODE_IS_BRANCH,
26107 + Opcode_blt_encode_fns, 0, 0 },
26108 + { "bgeu", 43 /* xt_iclass_bst8 */,
26109 + XTENSA_OPCODE_IS_BRANCH,
26110 + Opcode_bgeu_encode_fns, 0, 0 },
26111 + { "bltu", 43 /* xt_iclass_bst8 */,
26112 + XTENSA_OPCODE_IS_BRANCH,
26113 + Opcode_bltu_encode_fns, 0, 0 },
26114 + { "bany", 43 /* xt_iclass_bst8 */,
26115 + XTENSA_OPCODE_IS_BRANCH,
26116 + Opcode_bany_encode_fns, 0, 0 },
26117 + { "bnone", 43 /* xt_iclass_bst8 */,
26118 + XTENSA_OPCODE_IS_BRANCH,
26119 + Opcode_bnone_encode_fns, 0, 0 },
26120 + { "ball", 43 /* xt_iclass_bst8 */,
26121 + XTENSA_OPCODE_IS_BRANCH,
26122 + Opcode_ball_encode_fns, 0, 0 },
26123 + { "bnall", 43 /* xt_iclass_bst8 */,
26124 + XTENSA_OPCODE_IS_BRANCH,
26125 + Opcode_bnall_encode_fns, 0, 0 },
26126 + { "bbc", 43 /* xt_iclass_bst8 */,
26127 + XTENSA_OPCODE_IS_BRANCH,
26128 + Opcode_bbc_encode_fns, 0, 0 },
26129 + { "bbs", 43 /* xt_iclass_bst8 */,
26130 + XTENSA_OPCODE_IS_BRANCH,
26131 + Opcode_bbs_encode_fns, 0, 0 },
26132 + { "beqz", 44 /* xt_iclass_bsz12 */,
26133 + XTENSA_OPCODE_IS_BRANCH,
26134 + Opcode_beqz_encode_fns, 0, 0 },
26135 + { "bnez", 44 /* xt_iclass_bsz12 */,
26136 + XTENSA_OPCODE_IS_BRANCH,
26137 + Opcode_bnez_encode_fns, 0, 0 },
26138 + { "bgez", 44 /* xt_iclass_bsz12 */,
26139 + XTENSA_OPCODE_IS_BRANCH,
26140 + Opcode_bgez_encode_fns, 0, 0 },
26141 + { "bltz", 44 /* xt_iclass_bsz12 */,
26142 + XTENSA_OPCODE_IS_BRANCH,
26143 + Opcode_bltz_encode_fns, 0, 0 },
26144 + { "call0", 45 /* xt_iclass_call0 */,
26145 + XTENSA_OPCODE_IS_CALL,
26146 + Opcode_call0_encode_fns, 0, 0 },
26147 + { "callx0", 46 /* xt_iclass_callx0 */,
26148 + XTENSA_OPCODE_IS_CALL,
26149 + Opcode_callx0_encode_fns, 0, 0 },
26150 + { "extui", 47 /* xt_iclass_exti */,
26152 + Opcode_extui_encode_fns, 0, 0 },
26153 + { "ill", 48 /* xt_iclass_ill */,
26155 + Opcode_ill_encode_fns, 0, 0 },
26156 + { "j", 49 /* xt_iclass_jump */,
26157 + XTENSA_OPCODE_IS_JUMP,
26158 + Opcode_j_encode_fns, 0, 0 },
26159 + { "jx", 50 /* xt_iclass_jumpx */,
26160 + XTENSA_OPCODE_IS_JUMP,
26161 + Opcode_jx_encode_fns, 0, 0 },
26162 + { "l16ui", 51 /* xt_iclass_l16ui */,
26164 + Opcode_l16ui_encode_fns, 0, 0 },
26165 + { "l16si", 52 /* xt_iclass_l16si */,
26167 + Opcode_l16si_encode_fns, 0, 0 },
26168 + { "l32i", 53 /* xt_iclass_l32i */,
26170 + Opcode_l32i_encode_fns, 0, 0 },
26171 + { "l32r", 54 /* xt_iclass_l32r */,
26173 + Opcode_l32r_encode_fns, 0, 0 },
26174 + { "l8ui", 55 /* xt_iclass_l8i */,
26176 + Opcode_l8ui_encode_fns, 0, 0 },
26177 + { "loop", 56 /* xt_iclass_loop */,
26178 + XTENSA_OPCODE_IS_LOOP,
26179 + Opcode_loop_encode_fns, 0, 0 },
26180 + { "loopnez", 57 /* xt_iclass_loopz */,
26181 + XTENSA_OPCODE_IS_LOOP,
26182 + Opcode_loopnez_encode_fns, 0, 0 },
26183 + { "loopgtz", 57 /* xt_iclass_loopz */,
26184 + XTENSA_OPCODE_IS_LOOP,
26185 + Opcode_loopgtz_encode_fns, 0, 0 },
26186 + { "movi", 58 /* xt_iclass_movi */,
26188 + Opcode_movi_encode_fns, 0, 0 },
26189 + { "moveqz", 59 /* xt_iclass_movz */,
26191 + Opcode_moveqz_encode_fns, 0, 0 },
26192 + { "movnez", 59 /* xt_iclass_movz */,
26194 + Opcode_movnez_encode_fns, 0, 0 },
26195 + { "movltz", 59 /* xt_iclass_movz */,
26197 + Opcode_movltz_encode_fns, 0, 0 },
26198 + { "movgez", 59 /* xt_iclass_movz */,
26200 + Opcode_movgez_encode_fns, 0, 0 },
26201 + { "neg", 60 /* xt_iclass_neg */,
26203 + Opcode_neg_encode_fns, 0, 0 },
26204 + { "abs", 60 /* xt_iclass_neg */,
26206 + Opcode_abs_encode_fns, 0, 0 },
26207 + { "nop", 61 /* xt_iclass_nop */,
26209 + Opcode_nop_encode_fns, 0, 0 },
26210 + { "ret", 62 /* xt_iclass_return */,
26211 + XTENSA_OPCODE_IS_JUMP,
26212 + Opcode_ret_encode_fns, 0, 0 },
26213 + { "s16i", 63 /* xt_iclass_s16i */,
26215 + Opcode_s16i_encode_fns, 0, 0 },
26216 + { "s32i", 64 /* xt_iclass_s32i */,
26218 + Opcode_s32i_encode_fns, 0, 0 },
26219 + { "s8i", 65 /* xt_iclass_s8i */,
26221 + Opcode_s8i_encode_fns, 0, 0 },
26222 + { "ssr", 66 /* xt_iclass_sar */,
26224 + Opcode_ssr_encode_fns, 0, 0 },
26225 + { "ssl", 66 /* xt_iclass_sar */,
26227 + Opcode_ssl_encode_fns, 0, 0 },
26228 + { "ssa8l", 66 /* xt_iclass_sar */,
26230 + Opcode_ssa8l_encode_fns, 0, 0 },
26231 + { "ssa8b", 66 /* xt_iclass_sar */,
26233 + Opcode_ssa8b_encode_fns, 0, 0 },
26234 + { "ssai", 67 /* xt_iclass_sari */,
26236 + Opcode_ssai_encode_fns, 0, 0 },
26237 + { "sll", 68 /* xt_iclass_shifts */,
26239 + Opcode_sll_encode_fns, 0, 0 },
26240 + { "src", 69 /* xt_iclass_shiftst */,
26242 + Opcode_src_encode_fns, 0, 0 },
26243 + { "srl", 70 /* xt_iclass_shiftt */,
26245 + Opcode_srl_encode_fns, 0, 0 },
26246 + { "sra", 70 /* xt_iclass_shiftt */,
26248 + Opcode_sra_encode_fns, 0, 0 },
26249 + { "slli", 71 /* xt_iclass_slli */,
26251 + Opcode_slli_encode_fns, 0, 0 },
26252 + { "srai", 72 /* xt_iclass_srai */,
26254 + Opcode_srai_encode_fns, 0, 0 },
26255 + { "srli", 73 /* xt_iclass_srli */,
26257 + Opcode_srli_encode_fns, 0, 0 },
26258 + { "memw", 74 /* xt_iclass_memw */,
26260 + Opcode_memw_encode_fns, 0, 0 },
26261 + { "extw", 75 /* xt_iclass_extw */,
26263 + Opcode_extw_encode_fns, 0, 0 },
26264 + { "isync", 76 /* xt_iclass_isync */,
26266 + Opcode_isync_encode_fns, 0, 0 },
26267 + { "rsync", 77 /* xt_iclass_sync */,
26269 + Opcode_rsync_encode_fns, 0, 0 },
26270 + { "esync", 77 /* xt_iclass_sync */,
26272 + Opcode_esync_encode_fns, 0, 0 },
26273 + { "dsync", 77 /* xt_iclass_sync */,
26275 + Opcode_dsync_encode_fns, 0, 0 },
26276 + { "rsil", 78 /* xt_iclass_rsil */,
26278 + Opcode_rsil_encode_fns, 0, 0 },
26279 + { "rsr.lend", 79 /* xt_iclass_rsr.lend */,
26281 + Opcode_rsr_lend_encode_fns, 0, 0 },
26282 + { "wsr.lend", 80 /* xt_iclass_wsr.lend */,
26284 + Opcode_wsr_lend_encode_fns, 0, 0 },
26285 + { "xsr.lend", 81 /* xt_iclass_xsr.lend */,
26287 + Opcode_xsr_lend_encode_fns, 0, 0 },
26288 + { "rsr.lcount", 82 /* xt_iclass_rsr.lcount */,
26290 + Opcode_rsr_lcount_encode_fns, 0, 0 },
26291 + { "wsr.lcount", 83 /* xt_iclass_wsr.lcount */,
26293 + Opcode_wsr_lcount_encode_fns, 0, 0 },
26294 + { "xsr.lcount", 84 /* xt_iclass_xsr.lcount */,
26296 + Opcode_xsr_lcount_encode_fns, 0, 0 },
26297 + { "rsr.lbeg", 85 /* xt_iclass_rsr.lbeg */,
26299 + Opcode_rsr_lbeg_encode_fns, 0, 0 },
26300 + { "wsr.lbeg", 86 /* xt_iclass_wsr.lbeg */,
26302 + Opcode_wsr_lbeg_encode_fns, 0, 0 },
26303 + { "xsr.lbeg", 87 /* xt_iclass_xsr.lbeg */,
26305 + Opcode_xsr_lbeg_encode_fns, 0, 0 },
26306 + { "rsr.sar", 88 /* xt_iclass_rsr.sar */,
26308 + Opcode_rsr_sar_encode_fns, 0, 0 },
26309 + { "wsr.sar", 89 /* xt_iclass_wsr.sar */,
26311 + Opcode_wsr_sar_encode_fns, 0, 0 },
26312 + { "xsr.sar", 90 /* xt_iclass_xsr.sar */,
26314 + Opcode_xsr_sar_encode_fns, 0, 0 },
26315 + { "rsr.litbase", 91 /* xt_iclass_rsr.litbase */,
26317 + Opcode_rsr_litbase_encode_fns, 0, 0 },
26318 + { "wsr.litbase", 92 /* xt_iclass_wsr.litbase */,
26320 + Opcode_wsr_litbase_encode_fns, 0, 0 },
26321 + { "xsr.litbase", 93 /* xt_iclass_xsr.litbase */,
26323 + Opcode_xsr_litbase_encode_fns, 0, 0 },
26324 + { "rsr.176", 94 /* xt_iclass_rsr.176 */,
26326 + Opcode_rsr_176_encode_fns, 0, 0 },
26327 + { "rsr.208", 95 /* xt_iclass_rsr.208 */,
26329 + Opcode_rsr_208_encode_fns, 0, 0 },
26330 + { "rsr.ps", 96 /* xt_iclass_rsr.ps */,
26332 + Opcode_rsr_ps_encode_fns, 0, 0 },
26333 + { "wsr.ps", 97 /* xt_iclass_wsr.ps */,
26335 + Opcode_wsr_ps_encode_fns, 0, 0 },
26336 + { "xsr.ps", 98 /* xt_iclass_xsr.ps */,
26338 + Opcode_xsr_ps_encode_fns, 0, 0 },
26339 + { "rsr.epc1", 99 /* xt_iclass_rsr.epc1 */,
26341 + Opcode_rsr_epc1_encode_fns, 0, 0 },
26342 + { "wsr.epc1", 100 /* xt_iclass_wsr.epc1 */,
26344 + Opcode_wsr_epc1_encode_fns, 0, 0 },
26345 + { "xsr.epc1", 101 /* xt_iclass_xsr.epc1 */,
26347 + Opcode_xsr_epc1_encode_fns, 0, 0 },
26348 + { "rsr.excsave1", 102 /* xt_iclass_rsr.excsave1 */,
26350 + Opcode_rsr_excsave1_encode_fns, 0, 0 },
26351 + { "wsr.excsave1", 103 /* xt_iclass_wsr.excsave1 */,
26353 + Opcode_wsr_excsave1_encode_fns, 0, 0 },
26354 + { "xsr.excsave1", 104 /* xt_iclass_xsr.excsave1 */,
26356 + Opcode_xsr_excsave1_encode_fns, 0, 0 },
26357 + { "rsr.epc2", 105 /* xt_iclass_rsr.epc2 */,
26359 + Opcode_rsr_epc2_encode_fns, 0, 0 },
26360 + { "wsr.epc2", 106 /* xt_iclass_wsr.epc2 */,
26362 + Opcode_wsr_epc2_encode_fns, 0, 0 },
26363 + { "xsr.epc2", 107 /* xt_iclass_xsr.epc2 */,
26365 + Opcode_xsr_epc2_encode_fns, 0, 0 },
26366 + { "rsr.excsave2", 108 /* xt_iclass_rsr.excsave2 */,
26368 + Opcode_rsr_excsave2_encode_fns, 0, 0 },
26369 + { "wsr.excsave2", 109 /* xt_iclass_wsr.excsave2 */,
26371 + Opcode_wsr_excsave2_encode_fns, 0, 0 },
26372 + { "xsr.excsave2", 110 /* xt_iclass_xsr.excsave2 */,
26374 + Opcode_xsr_excsave2_encode_fns, 0, 0 },
26375 + { "rsr.epc3", 111 /* xt_iclass_rsr.epc3 */,
26377 + Opcode_rsr_epc3_encode_fns, 0, 0 },
26378 + { "wsr.epc3", 112 /* xt_iclass_wsr.epc3 */,
26380 + Opcode_wsr_epc3_encode_fns, 0, 0 },
26381 + { "xsr.epc3", 113 /* xt_iclass_xsr.epc3 */,
26383 + Opcode_xsr_epc3_encode_fns, 0, 0 },
26384 + { "rsr.excsave3", 114 /* xt_iclass_rsr.excsave3 */,
26386 + Opcode_rsr_excsave3_encode_fns, 0, 0 },
26387 + { "wsr.excsave3", 115 /* xt_iclass_wsr.excsave3 */,
26389 + Opcode_wsr_excsave3_encode_fns, 0, 0 },
26390 + { "xsr.excsave3", 116 /* xt_iclass_xsr.excsave3 */,
26392 + Opcode_xsr_excsave3_encode_fns, 0, 0 },
26393 + { "rsr.epc4", 117 /* xt_iclass_rsr.epc4 */,
26395 + Opcode_rsr_epc4_encode_fns, 0, 0 },
26396 + { "wsr.epc4", 118 /* xt_iclass_wsr.epc4 */,
26398 + Opcode_wsr_epc4_encode_fns, 0, 0 },
26399 + { "xsr.epc4", 119 /* xt_iclass_xsr.epc4 */,
26401 + Opcode_xsr_epc4_encode_fns, 0, 0 },
26402 + { "rsr.excsave4", 120 /* xt_iclass_rsr.excsave4 */,
26404 + Opcode_rsr_excsave4_encode_fns, 0, 0 },
26405 + { "wsr.excsave4", 121 /* xt_iclass_wsr.excsave4 */,
26407 + Opcode_wsr_excsave4_encode_fns, 0, 0 },
26408 + { "xsr.excsave4", 122 /* xt_iclass_xsr.excsave4 */,
26410 + Opcode_xsr_excsave4_encode_fns, 0, 0 },
26411 + { "rsr.epc5", 123 /* xt_iclass_rsr.epc5 */,
26413 + Opcode_rsr_epc5_encode_fns, 0, 0 },
26414 + { "wsr.epc5", 124 /* xt_iclass_wsr.epc5 */,
26416 + Opcode_wsr_epc5_encode_fns, 0, 0 },
26417 + { "xsr.epc5", 125 /* xt_iclass_xsr.epc5 */,
26419 + Opcode_xsr_epc5_encode_fns, 0, 0 },
26420 + { "rsr.excsave5", 126 /* xt_iclass_rsr.excsave5 */,
26422 + Opcode_rsr_excsave5_encode_fns, 0, 0 },
26423 + { "wsr.excsave5", 127 /* xt_iclass_wsr.excsave5 */,
26425 + Opcode_wsr_excsave5_encode_fns, 0, 0 },
26426 + { "xsr.excsave5", 128 /* xt_iclass_xsr.excsave5 */,
26428 + Opcode_xsr_excsave5_encode_fns, 0, 0 },
26429 + { "rsr.eps2", 129 /* xt_iclass_rsr.eps2 */,
26431 + Opcode_rsr_eps2_encode_fns, 0, 0 },
26432 + { "wsr.eps2", 130 /* xt_iclass_wsr.eps2 */,
26434 + Opcode_wsr_eps2_encode_fns, 0, 0 },
26435 + { "xsr.eps2", 131 /* xt_iclass_xsr.eps2 */,
26437 + Opcode_xsr_eps2_encode_fns, 0, 0 },
26438 + { "rsr.eps3", 132 /* xt_iclass_rsr.eps3 */,
26440 + Opcode_rsr_eps3_encode_fns, 0, 0 },
26441 + { "wsr.eps3", 133 /* xt_iclass_wsr.eps3 */,
26443 + Opcode_wsr_eps3_encode_fns, 0, 0 },
26444 + { "xsr.eps3", 134 /* xt_iclass_xsr.eps3 */,
26446 + Opcode_xsr_eps3_encode_fns, 0, 0 },
26447 + { "rsr.eps4", 135 /* xt_iclass_rsr.eps4 */,
26449 + Opcode_rsr_eps4_encode_fns, 0, 0 },
26450 + { "wsr.eps4", 136 /* xt_iclass_wsr.eps4 */,
26452 + Opcode_wsr_eps4_encode_fns, 0, 0 },
26453 + { "xsr.eps4", 137 /* xt_iclass_xsr.eps4 */,
26455 + Opcode_xsr_eps4_encode_fns, 0, 0 },
26456 + { "rsr.eps5", 138 /* xt_iclass_rsr.eps5 */,
26458 + Opcode_rsr_eps5_encode_fns, 0, 0 },
26459 + { "wsr.eps5", 139 /* xt_iclass_wsr.eps5 */,
26461 + Opcode_wsr_eps5_encode_fns, 0, 0 },
26462 + { "xsr.eps5", 140 /* xt_iclass_xsr.eps5 */,
26464 + Opcode_xsr_eps5_encode_fns, 0, 0 },
26465 + { "rsr.excvaddr", 141 /* xt_iclass_rsr.excvaddr */,
26467 + Opcode_rsr_excvaddr_encode_fns, 0, 0 },
26468 + { "wsr.excvaddr", 142 /* xt_iclass_wsr.excvaddr */,
26470 + Opcode_wsr_excvaddr_encode_fns, 0, 0 },
26471 + { "xsr.excvaddr", 143 /* xt_iclass_xsr.excvaddr */,
26473 + Opcode_xsr_excvaddr_encode_fns, 0, 0 },
26474 + { "rsr.depc", 144 /* xt_iclass_rsr.depc */,
26476 + Opcode_rsr_depc_encode_fns, 0, 0 },
26477 + { "wsr.depc", 145 /* xt_iclass_wsr.depc */,
26479 + Opcode_wsr_depc_encode_fns, 0, 0 },
26480 + { "xsr.depc", 146 /* xt_iclass_xsr.depc */,
26482 + Opcode_xsr_depc_encode_fns, 0, 0 },
26483 + { "rsr.exccause", 147 /* xt_iclass_rsr.exccause */,
26485 + Opcode_rsr_exccause_encode_fns, 0, 0 },
26486 + { "wsr.exccause", 148 /* xt_iclass_wsr.exccause */,
26488 + Opcode_wsr_exccause_encode_fns, 0, 0 },
26489 + { "xsr.exccause", 149 /* xt_iclass_xsr.exccause */,
26491 + Opcode_xsr_exccause_encode_fns, 0, 0 },
26492 + { "rsr.misc0", 150 /* xt_iclass_rsr.misc0 */,
26494 + Opcode_rsr_misc0_encode_fns, 0, 0 },
26495 + { "wsr.misc0", 151 /* xt_iclass_wsr.misc0 */,
26497 + Opcode_wsr_misc0_encode_fns, 0, 0 },
26498 + { "xsr.misc0", 152 /* xt_iclass_xsr.misc0 */,
26500 + Opcode_xsr_misc0_encode_fns, 0, 0 },
26501 + { "rsr.misc1", 153 /* xt_iclass_rsr.misc1 */,
26503 + Opcode_rsr_misc1_encode_fns, 0, 0 },
26504 + { "wsr.misc1", 154 /* xt_iclass_wsr.misc1 */,
26506 + Opcode_wsr_misc1_encode_fns, 0, 0 },
26507 + { "xsr.misc1", 155 /* xt_iclass_xsr.misc1 */,
26509 + Opcode_xsr_misc1_encode_fns, 0, 0 },
26510 + { "rsr.prid", 156 /* xt_iclass_rsr.prid */,
26512 + Opcode_rsr_prid_encode_fns, 0, 0 },
26513 + { "rsr.vecbase", 157 /* xt_iclass_rsr.vecbase */,
26515 + Opcode_rsr_vecbase_encode_fns, 0, 0 },
26516 + { "wsr.vecbase", 158 /* xt_iclass_wsr.vecbase */,
26518 + Opcode_wsr_vecbase_encode_fns, 0, 0 },
26519 + { "xsr.vecbase", 159 /* xt_iclass_xsr.vecbase */,
26521 + Opcode_xsr_vecbase_encode_fns, 0, 0 },
26522 + { "rfi", 160 /* xt_iclass_rfi */,
26523 + XTENSA_OPCODE_IS_JUMP,
26524 + Opcode_rfi_encode_fns, 0, 0 },
26525 + { "waiti", 161 /* xt_iclass_wait */,
26527 + Opcode_waiti_encode_fns, 0, 0 },
26528 + { "rsr.interrupt", 162 /* xt_iclass_rsr.interrupt */,
26530 + Opcode_rsr_interrupt_encode_fns, 0, 0 },
26531 + { "wsr.intset", 163 /* xt_iclass_wsr.intset */,
26533 + Opcode_wsr_intset_encode_fns, 0, 0 },
26534 + { "wsr.intclear", 164 /* xt_iclass_wsr.intclear */,
26536 + Opcode_wsr_intclear_encode_fns, 0, 0 },
26537 + { "rsr.intenable", 165 /* xt_iclass_rsr.intenable */,
26539 + Opcode_rsr_intenable_encode_fns, 0, 0 },
26540 + { "wsr.intenable", 166 /* xt_iclass_wsr.intenable */,
26542 + Opcode_wsr_intenable_encode_fns, 0, 0 },
26543 + { "xsr.intenable", 167 /* xt_iclass_xsr.intenable */,
26545 + Opcode_xsr_intenable_encode_fns, 0, 0 },
26546 + { "break", 168 /* xt_iclass_break */,
26548 + Opcode_break_encode_fns, 0, 0 },
26549 + { "break.n", 169 /* xt_iclass_break.n */,
26551 + Opcode_break_n_encode_fns, 0, 0 },
26552 + { "rsr.dbreaka0", 170 /* xt_iclass_rsr.dbreaka0 */,
26554 + Opcode_rsr_dbreaka0_encode_fns, 0, 0 },
26555 + { "wsr.dbreaka0", 171 /* xt_iclass_wsr.dbreaka0 */,
26557 + Opcode_wsr_dbreaka0_encode_fns, 0, 0 },
26558 + { "xsr.dbreaka0", 172 /* xt_iclass_xsr.dbreaka0 */,
26560 + Opcode_xsr_dbreaka0_encode_fns, 0, 0 },
26561 + { "rsr.dbreakc0", 173 /* xt_iclass_rsr.dbreakc0 */,
26563 + Opcode_rsr_dbreakc0_encode_fns, 0, 0 },
26564 + { "wsr.dbreakc0", 174 /* xt_iclass_wsr.dbreakc0 */,
26566 + Opcode_wsr_dbreakc0_encode_fns, 0, 0 },
26567 + { "xsr.dbreakc0", 175 /* xt_iclass_xsr.dbreakc0 */,
26569 + Opcode_xsr_dbreakc0_encode_fns, 0, 0 },
26570 + { "rsr.dbreaka1", 176 /* xt_iclass_rsr.dbreaka1 */,
26572 + Opcode_rsr_dbreaka1_encode_fns, 0, 0 },
26573 + { "wsr.dbreaka1", 177 /* xt_iclass_wsr.dbreaka1 */,
26575 + Opcode_wsr_dbreaka1_encode_fns, 0, 0 },
26576 + { "xsr.dbreaka1", 178 /* xt_iclass_xsr.dbreaka1 */,
26578 + Opcode_xsr_dbreaka1_encode_fns, 0, 0 },
26579 + { "rsr.dbreakc1", 179 /* xt_iclass_rsr.dbreakc1 */,
26581 + Opcode_rsr_dbreakc1_encode_fns, 0, 0 },
26582 + { "wsr.dbreakc1", 180 /* xt_iclass_wsr.dbreakc1 */,
26584 + Opcode_wsr_dbreakc1_encode_fns, 0, 0 },
26585 + { "xsr.dbreakc1", 181 /* xt_iclass_xsr.dbreakc1 */,
26587 + Opcode_xsr_dbreakc1_encode_fns, 0, 0 },
26588 + { "rsr.ibreaka0", 182 /* xt_iclass_rsr.ibreaka0 */,
26590 + Opcode_rsr_ibreaka0_encode_fns, 0, 0 },
26591 + { "wsr.ibreaka0", 183 /* xt_iclass_wsr.ibreaka0 */,
26593 + Opcode_wsr_ibreaka0_encode_fns, 0, 0 },
26594 + { "xsr.ibreaka0", 184 /* xt_iclass_xsr.ibreaka0 */,
26596 + Opcode_xsr_ibreaka0_encode_fns, 0, 0 },
26597 + { "rsr.ibreaka1", 185 /* xt_iclass_rsr.ibreaka1 */,
26599 + Opcode_rsr_ibreaka1_encode_fns, 0, 0 },
26600 + { "wsr.ibreaka1", 186 /* xt_iclass_wsr.ibreaka1 */,
26602 + Opcode_wsr_ibreaka1_encode_fns, 0, 0 },
26603 + { "xsr.ibreaka1", 187 /* xt_iclass_xsr.ibreaka1 */,
26605 + Opcode_xsr_ibreaka1_encode_fns, 0, 0 },
26606 + { "rsr.ibreakenable", 188 /* xt_iclass_rsr.ibreakenable */,
26608 + Opcode_rsr_ibreakenable_encode_fns, 0, 0 },
26609 + { "wsr.ibreakenable", 189 /* xt_iclass_wsr.ibreakenable */,
26611 + Opcode_wsr_ibreakenable_encode_fns, 0, 0 },
26612 + { "xsr.ibreakenable", 190 /* xt_iclass_xsr.ibreakenable */,
26614 + Opcode_xsr_ibreakenable_encode_fns, 0, 0 },
26615 + { "rsr.debugcause", 191 /* xt_iclass_rsr.debugcause */,
26617 + Opcode_rsr_debugcause_encode_fns, 0, 0 },
26618 + { "wsr.debugcause", 192 /* xt_iclass_wsr.debugcause */,
26620 + Opcode_wsr_debugcause_encode_fns, 0, 0 },
26621 + { "xsr.debugcause", 193 /* xt_iclass_xsr.debugcause */,
26623 + Opcode_xsr_debugcause_encode_fns, 0, 0 },
26624 + { "rsr.icount", 194 /* xt_iclass_rsr.icount */,
26626 + Opcode_rsr_icount_encode_fns, 0, 0 },
26627 + { "wsr.icount", 195 /* xt_iclass_wsr.icount */,
26629 + Opcode_wsr_icount_encode_fns, 0, 0 },
26630 + { "xsr.icount", 196 /* xt_iclass_xsr.icount */,
26632 + Opcode_xsr_icount_encode_fns, 0, 0 },
26633 + { "rsr.icountlevel", 197 /* xt_iclass_rsr.icountlevel */,
26635 + Opcode_rsr_icountlevel_encode_fns, 0, 0 },
26636 + { "wsr.icountlevel", 198 /* xt_iclass_wsr.icountlevel */,
26638 + Opcode_wsr_icountlevel_encode_fns, 0, 0 },
26639 + { "xsr.icountlevel", 199 /* xt_iclass_xsr.icountlevel */,
26641 + Opcode_xsr_icountlevel_encode_fns, 0, 0 },
26642 + { "rsr.ddr", 200 /* xt_iclass_rsr.ddr */,
26644 + Opcode_rsr_ddr_encode_fns, 0, 0 },
26645 + { "wsr.ddr", 201 /* xt_iclass_wsr.ddr */,
26647 + Opcode_wsr_ddr_encode_fns, 0, 0 },
26648 + { "xsr.ddr", 202 /* xt_iclass_xsr.ddr */,
26650 + Opcode_xsr_ddr_encode_fns, 0, 0 },
26651 + { "rfdo", 203 /* xt_iclass_rfdo */,
26652 + XTENSA_OPCODE_IS_JUMP,
26653 + Opcode_rfdo_encode_fns, 0, 0 },
26654 + { "rfdd", 204 /* xt_iclass_rfdd */,
26655 + XTENSA_OPCODE_IS_JUMP,
26656 + Opcode_rfdd_encode_fns, 0, 0 },
26657 + { "wsr.mmid", 205 /* xt_iclass_wsr.mmid */,
26659 + Opcode_wsr_mmid_encode_fns, 0, 0 },
26660 + { "rsr.ccount", 206 /* xt_iclass_rsr.ccount */,
26662 + Opcode_rsr_ccount_encode_fns, 0, 0 },
26663 + { "wsr.ccount", 207 /* xt_iclass_wsr.ccount */,
26665 + Opcode_wsr_ccount_encode_fns, 0, 0 },
26666 + { "xsr.ccount", 208 /* xt_iclass_xsr.ccount */,
26668 + Opcode_xsr_ccount_encode_fns, 0, 0 },
26669 + { "rsr.ccompare0", 209 /* xt_iclass_rsr.ccompare0 */,
26671 + Opcode_rsr_ccompare0_encode_fns, 0, 0 },
26672 + { "wsr.ccompare0", 210 /* xt_iclass_wsr.ccompare0 */,
26674 + Opcode_wsr_ccompare0_encode_fns, 0, 0 },
26675 + { "xsr.ccompare0", 211 /* xt_iclass_xsr.ccompare0 */,
26677 + Opcode_xsr_ccompare0_encode_fns, 0, 0 },
26678 + { "idtlb", 212 /* xt_iclass_idtlb */,
26680 + Opcode_idtlb_encode_fns, 0, 0 },
26681 + { "pdtlb", 213 /* xt_iclass_rdtlb */,
26683 + Opcode_pdtlb_encode_fns, 0, 0 },
26684 + { "rdtlb0", 213 /* xt_iclass_rdtlb */,
26686 + Opcode_rdtlb0_encode_fns, 0, 0 },
26687 + { "rdtlb1", 213 /* xt_iclass_rdtlb */,
26689 + Opcode_rdtlb1_encode_fns, 0, 0 },
26690 + { "wdtlb", 214 /* xt_iclass_wdtlb */,
26692 + Opcode_wdtlb_encode_fns, 0, 0 },
26693 + { "iitlb", 215 /* xt_iclass_iitlb */,
26695 + Opcode_iitlb_encode_fns, 0, 0 },
26696 + { "pitlb", 216 /* xt_iclass_ritlb */,
26698 + Opcode_pitlb_encode_fns, 0, 0 },
26699 + { "ritlb0", 216 /* xt_iclass_ritlb */,
26701 + Opcode_ritlb0_encode_fns, 0, 0 },
26702 + { "ritlb1", 216 /* xt_iclass_ritlb */,
26704 + Opcode_ritlb1_encode_fns, 0, 0 },
26705 + { "witlb", 217 /* xt_iclass_witlb */,
26707 + Opcode_witlb_encode_fns, 0, 0 },
26708 + { "min", 218 /* xt_iclass_minmax */,
26710 + Opcode_min_encode_fns, 0, 0 },
26711 + { "max", 218 /* xt_iclass_minmax */,
26713 + Opcode_max_encode_fns, 0, 0 },
26714 + { "minu", 218 /* xt_iclass_minmax */,
26716 + Opcode_minu_encode_fns, 0, 0 },
26717 + { "maxu", 218 /* xt_iclass_minmax */,
26719 + Opcode_maxu_encode_fns, 0, 0 },
26720 + { "nsa", 219 /* xt_iclass_nsa */,
26722 + Opcode_nsa_encode_fns, 0, 0 },
26723 + { "nsau", 219 /* xt_iclass_nsa */,
26725 + Opcode_nsau_encode_fns, 0, 0 },
26726 + { "sext", 220 /* xt_iclass_sx */,
26728 + Opcode_sext_encode_fns, 0, 0 },
26729 + { "l32ai", 221 /* xt_iclass_l32ai */,
26731 + Opcode_l32ai_encode_fns, 0, 0 },
26732 + { "s32ri", 222 /* xt_iclass_s32ri */,
26734 + Opcode_s32ri_encode_fns, 0, 0 },
26735 + { "s32c1i", 223 /* xt_iclass_s32c1i */,
26737 + Opcode_s32c1i_encode_fns, 0, 0 },
26738 + { "rsr.scompare1", 224 /* xt_iclass_rsr.scompare1 */,
26740 + Opcode_rsr_scompare1_encode_fns, 0, 0 },
26741 + { "wsr.scompare1", 225 /* xt_iclass_wsr.scompare1 */,
26743 + Opcode_wsr_scompare1_encode_fns, 0, 0 },
26744 + { "xsr.scompare1", 226 /* xt_iclass_xsr.scompare1 */,
26746 + Opcode_xsr_scompare1_encode_fns, 0, 0 },
26747 + { "mull", 227 /* xt_mul32 */,
26749 + Opcode_mull_encode_fns, 0, 0 },
26750 + { "muluh", 227 /* xt_mul32 */,
26752 + Opcode_muluh_encode_fns, 0, 0 },
26753 + { "mulsh", 227 /* xt_mul32 */,
26755 + Opcode_mulsh_encode_fns, 0, 0 },
26756 + { "mul16u", 227 /* xt_mul32 */,
26758 + Opcode_mul16u_encode_fns, 0, 0 },
26759 + { "mul16s", 227 /* xt_mul32 */,
26761 + Opcode_mul16s_encode_fns, 0, 0 }
26764 -static xtensa_set_field_fn
26765 -Slot_xt_flix64_slot0_set_field_fns[] = {
26766 - Field_t_Slot_xt_flix64_slot0_set,
26770 - Field_imm8_Slot_xt_flix64_slot0_set,
26771 - Field_s_Slot_xt_flix64_slot0_set,
26772 - Field_imm12b_Slot_xt_flix64_slot0_set,
26773 - Field_imm16_Slot_xt_flix64_slot0_set,
26774 - Field_m_Slot_xt_flix64_slot0_set,
26775 - Field_n_Slot_xt_flix64_slot0_set,
26778 - Field_op1_Slot_xt_flix64_slot0_set,
26779 - Field_op2_Slot_xt_flix64_slot0_set,
26780 - Field_r_Slot_xt_flix64_slot0_set,
26782 - Field_sae4_Slot_xt_flix64_slot0_set,
26783 - Field_sae_Slot_xt_flix64_slot0_set,
26784 - Field_sal_Slot_xt_flix64_slot0_set,
26785 - Field_sargt_Slot_xt_flix64_slot0_set,
26787 - Field_sas_Slot_xt_flix64_slot0_set,
26790 - Field_thi3_Slot_xt_flix64_slot0_set,
26821 - Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_set,
26822 - Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_set,
26823 - Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_set,
26824 - Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_set,
26825 - Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_set,
26826 - Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_set,
26888 - Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_set,
26889 - Implicit_Field_set,
26890 - Implicit_Field_set,
26891 - Implicit_Field_set,
26892 - Implicit_Field_set,
26893 - Implicit_Field_set,
26894 - Implicit_Field_set,
26895 - Implicit_Field_set,
26896 - Implicit_Field_set,
26897 - Implicit_Field_set,
26898 - Implicit_Field_set,
26899 - Implicit_Field_set,
26900 - Implicit_Field_set
26903 +/* Slot-specific opcode decode functions. */
26905 -static xtensa_get_field_fn
26906 -Slot_xt_flix64_slot1_get_field_fns[] = {
26907 - Field_t_Slot_xt_flix64_slot1_get,
26911 - Field_imm8_Slot_xt_flix64_slot1_get,
26912 - Field_s_Slot_xt_flix64_slot1_get,
26913 - Field_imm12b_Slot_xt_flix64_slot1_get,
26917 - Field_offset_Slot_xt_flix64_slot1_get,
26920 - Field_op2_Slot_xt_flix64_slot1_get,
26921 - Field_r_Slot_xt_flix64_slot1_get,
26924 - Field_sae_Slot_xt_flix64_slot1_get,
26925 - Field_sal_Slot_xt_flix64_slot1_get,
26926 - Field_sargt_Slot_xt_flix64_slot1_get,
26968 - Field_op0_s4_Slot_xt_flix64_slot1_get,
26969 - Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_get,
26970 - Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26971 - Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26972 - Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26973 - Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26974 - Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26975 - Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26976 - Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26977 - Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26978 - Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26979 - Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26980 - Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26981 - Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26982 - Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26983 - Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26984 - Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26985 - Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26986 - Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26987 - Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26988 - Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_get,
26989 - Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_get,
27030 - Implicit_Field_ar0_get,
27031 - Implicit_Field_ar4_get,
27032 - Implicit_Field_ar8_get,
27033 - Implicit_Field_ar12_get,
27034 - Implicit_Field_mr0_get,
27035 - Implicit_Field_mr1_get,
27036 - Implicit_Field_mr2_get,
27037 - Implicit_Field_mr3_get,
27038 - Implicit_Field_bt16_get,
27039 - Implicit_Field_bs16_get,
27040 - Implicit_Field_br16_get,
27041 - Implicit_Field_brall_get
27044 +Slot_inst_decode (const xtensa_insnbuf insn)
27046 + switch (Field_op0_Slot_inst_get (insn))
27049 + switch (Field_op1_Slot_inst_get (insn))
27052 + switch (Field_op2_Slot_inst_get (insn))
27055 + switch (Field_r_Slot_inst_get (insn))
27058 + switch (Field_m_Slot_inst_get (insn))
27061 + if (Field_s_Slot_inst_get (insn) == 0 &&
27062 + Field_n_Slot_inst_get (insn) == 0)
27063 + return 79; /* ill */
27066 + switch (Field_n_Slot_inst_get (insn))
27069 + return 98; /* ret */
27071 + return 14; /* retw */
27073 + return 81; /* jx */
27077 + switch (Field_n_Slot_inst_get (insn))
27080 + return 77; /* callx0 */
27082 + return 10; /* callx4 */
27084 + return 9; /* callx8 */
27086 + return 8; /* callx12 */
27092 + return 12; /* movsp */
27094 + if (Field_s_Slot_inst_get (insn) == 0)
27096 + switch (Field_t_Slot_inst_get (insn))
27099 + return 116; /* isync */
27101 + return 117; /* rsync */
27103 + return 118; /* esync */
27105 + return 119; /* dsync */
27107 + return 0; /* excw */
27109 + return 114; /* memw */
27111 + return 115; /* extw */
27113 + return 97; /* nop */
27118 + switch (Field_t_Slot_inst_get (insn))
27121 + switch (Field_s_Slot_inst_get (insn))
27124 + return 1; /* rfe */
27126 + return 2; /* rfde */
27128 + return 16; /* rfwo */
27130 + return 17; /* rfwu */
27134 + return 202; /* rfi */
27138 + return 210; /* break */
27140 + switch (Field_s_Slot_inst_get (insn))
27143 + if (Field_t_Slot_inst_get (insn) == 0)
27144 + return 3; /* syscall */
27147 + if (Field_t_Slot_inst_get (insn) == 0)
27148 + return 4; /* simcall */
27153 + return 120; /* rsil */
27155 + if (Field_t_Slot_inst_get (insn) == 0)
27156 + return 203; /* waiti */
27161 + return 49; /* and */
27163 + return 50; /* or */
27165 + return 51; /* xor */
27167 + switch (Field_r_Slot_inst_get (insn))
27170 + if (Field_t_Slot_inst_get (insn) == 0)
27171 + return 102; /* ssr */
27174 + if (Field_t_Slot_inst_get (insn) == 0)
27175 + return 103; /* ssl */
27178 + if (Field_t_Slot_inst_get (insn) == 0)
27179 + return 104; /* ssa8l */
27182 + if (Field_t_Slot_inst_get (insn) == 0)
27183 + return 105; /* ssa8b */
27186 + if (Field_thi3_Slot_inst_get (insn) == 0)
27187 + return 106; /* ssai */
27190 + if (Field_s_Slot_inst_get (insn) == 0)
27191 + return 13; /* rotw */
27194 + return 268; /* nsa */
27196 + return 269; /* nsau */
27200 + switch (Field_r_Slot_inst_get (insn))
27203 + return 261; /* ritlb0 */
27205 + if (Field_t_Slot_inst_get (insn) == 0)
27206 + return 259; /* iitlb */
27209 + return 260; /* pitlb */
27211 + return 263; /* witlb */
27213 + return 262; /* ritlb1 */
27215 + return 256; /* rdtlb0 */
27217 + if (Field_t_Slot_inst_get (insn) == 0)
27218 + return 254; /* idtlb */
27221 + return 255; /* pdtlb */
27223 + return 258; /* wdtlb */
27225 + return 257; /* rdtlb1 */
27229 + switch (Field_s_Slot_inst_get (insn))
27232 + return 95; /* neg */
27234 + return 96; /* abs */
27238 + return 41; /* add */
27240 + return 43; /* addx2 */
27242 + return 44; /* addx4 */
27244 + return 45; /* addx8 */
27246 + return 42; /* sub */
27248 + return 46; /* subx2 */
27250 + return 47; /* subx4 */
27252 + return 48; /* subx8 */
27256 + switch (Field_op2_Slot_inst_get (insn))
27260 + return 111; /* slli */
27263 + return 112; /* srai */
27265 + return 113; /* srli */
27267 + switch (Field_sr_Slot_inst_get (insn))
27270 + return 129; /* xsr.lbeg */
27272 + return 123; /* xsr.lend */
27274 + return 126; /* xsr.lcount */
27276 + return 132; /* xsr.sar */
27278 + return 135; /* xsr.litbase */
27280 + return 276; /* xsr.scompare1 */
27282 + return 22; /* xsr.windowbase */
27284 + return 25; /* xsr.windowstart */
27286 + return 232; /* xsr.ibreakenable */
27288 + return 244; /* xsr.ddr */
27290 + return 226; /* xsr.ibreaka0 */
27292 + return 229; /* xsr.ibreaka1 */
27294 + return 214; /* xsr.dbreaka0 */
27296 + return 220; /* xsr.dbreaka1 */
27298 + return 217; /* xsr.dbreakc0 */
27300 + return 223; /* xsr.dbreakc1 */
27302 + return 143; /* xsr.epc1 */
27304 + return 149; /* xsr.epc2 */
27306 + return 155; /* xsr.epc3 */
27308 + return 161; /* xsr.epc4 */
27310 + return 167; /* xsr.epc5 */
27312 + return 188; /* xsr.depc */
27314 + return 173; /* xsr.eps2 */
27316 + return 176; /* xsr.eps3 */
27318 + return 179; /* xsr.eps4 */
27320 + return 182; /* xsr.eps5 */
27322 + return 146; /* xsr.excsave1 */
27324 + return 152; /* xsr.excsave2 */
27326 + return 158; /* xsr.excsave3 */
27328 + return 164; /* xsr.excsave4 */
27330 + return 170; /* xsr.excsave5 */
27332 + return 209; /* xsr.intenable */
27334 + return 140; /* xsr.ps */
27336 + return 201; /* xsr.vecbase */
27338 + return 191; /* xsr.exccause */
27340 + return 235; /* xsr.debugcause */
27342 + return 250; /* xsr.ccount */
27344 + return 238; /* xsr.icount */
27346 + return 241; /* xsr.icountlevel */
27348 + return 185; /* xsr.excvaddr */
27350 + return 253; /* xsr.ccompare0 */
27352 + return 194; /* xsr.misc0 */
27354 + return 197; /* xsr.misc1 */
27358 + return 108; /* src */
27360 + if (Field_s_Slot_inst_get (insn) == 0)
27361 + return 109; /* srl */
27364 + if (Field_t_Slot_inst_get (insn) == 0)
27365 + return 107; /* sll */
27368 + if (Field_s_Slot_inst_get (insn) == 0)
27369 + return 110; /* sra */
27372 + return 280; /* mul16u */
27374 + return 281; /* mul16s */
27376 + switch (Field_r_Slot_inst_get (insn))
27379 + if (Field_t_Slot_inst_get (insn) == 0)
27380 + return 245; /* rfdo */
27381 + if (Field_t_Slot_inst_get (insn) == 1)
27382 + return 246; /* rfdd */
27389 + switch (Field_op2_Slot_inst_get (insn))
27392 + return 277; /* mull */
27394 + return 278; /* muluh */
27396 + return 279; /* mulsh */
27400 + switch (Field_op2_Slot_inst_get (insn))
27403 + switch (Field_sr_Slot_inst_get (insn))
27406 + return 127; /* rsr.lbeg */
27408 + return 121; /* rsr.lend */
27410 + return 124; /* rsr.lcount */
27412 + return 130; /* rsr.sar */
27414 + return 133; /* rsr.litbase */
27416 + return 274; /* rsr.scompare1 */
27418 + return 20; /* rsr.windowbase */
27420 + return 23; /* rsr.windowstart */
27422 + return 230; /* rsr.ibreakenable */
27424 + return 242; /* rsr.ddr */
27426 + return 224; /* rsr.ibreaka0 */
27428 + return 227; /* rsr.ibreaka1 */
27430 + return 212; /* rsr.dbreaka0 */
27432 + return 218; /* rsr.dbreaka1 */
27434 + return 215; /* rsr.dbreakc0 */
27436 + return 221; /* rsr.dbreakc1 */
27438 + return 136; /* rsr.176 */
27440 + return 141; /* rsr.epc1 */
27442 + return 147; /* rsr.epc2 */
27444 + return 153; /* rsr.epc3 */
27446 + return 159; /* rsr.epc4 */
27448 + return 165; /* rsr.epc5 */
27450 + return 186; /* rsr.depc */
27452 + return 171; /* rsr.eps2 */
27454 + return 174; /* rsr.eps3 */
27456 + return 177; /* rsr.eps4 */
27458 + return 180; /* rsr.eps5 */
27460 + return 137; /* rsr.208 */
27462 + return 144; /* rsr.excsave1 */
27464 + return 150; /* rsr.excsave2 */
27466 + return 156; /* rsr.excsave3 */
27468 + return 162; /* rsr.excsave4 */
27470 + return 168; /* rsr.excsave5 */
27472 + return 204; /* rsr.interrupt */
27474 + return 207; /* rsr.intenable */
27476 + return 138; /* rsr.ps */
27478 + return 199; /* rsr.vecbase */
27480 + return 189; /* rsr.exccause */
27482 + return 233; /* rsr.debugcause */
27484 + return 248; /* rsr.ccount */
27486 + return 198; /* rsr.prid */
27488 + return 236; /* rsr.icount */
27490 + return 239; /* rsr.icountlevel */
27492 + return 183; /* rsr.excvaddr */
27494 + return 251; /* rsr.ccompare0 */
27496 + return 192; /* rsr.misc0 */
27498 + return 195; /* rsr.misc1 */
27502 + switch (Field_sr_Slot_inst_get (insn))
27505 + return 128; /* wsr.lbeg */
27507 + return 122; /* wsr.lend */
27509 + return 125; /* wsr.lcount */
27511 + return 131; /* wsr.sar */
27513 + return 134; /* wsr.litbase */
27515 + return 275; /* wsr.scompare1 */
27517 + return 21; /* wsr.windowbase */
27519 + return 24; /* wsr.windowstart */
27521 + return 247; /* wsr.mmid */
27523 + return 231; /* wsr.ibreakenable */
27525 + return 243; /* wsr.ddr */
27527 + return 225; /* wsr.ibreaka0 */
27529 + return 228; /* wsr.ibreaka1 */
27531 + return 213; /* wsr.dbreaka0 */
27533 + return 219; /* wsr.dbreaka1 */
27535 + return 216; /* wsr.dbreakc0 */
27537 + return 222; /* wsr.dbreakc1 */
27539 + return 142; /* wsr.epc1 */
27541 + return 148; /* wsr.epc2 */
27543 + return 154; /* wsr.epc3 */
27545 + return 160; /* wsr.epc4 */
27547 + return 166; /* wsr.epc5 */
27549 + return 187; /* wsr.depc */
27551 + return 172; /* wsr.eps2 */
27553 + return 175; /* wsr.eps3 */
27555 + return 178; /* wsr.eps4 */
27557 + return 181; /* wsr.eps5 */
27559 + return 145; /* wsr.excsave1 */
27561 + return 151; /* wsr.excsave2 */
27563 + return 157; /* wsr.excsave3 */
27565 + return 163; /* wsr.excsave4 */
27567 + return 169; /* wsr.excsave5 */
27569 + return 205; /* wsr.intset */
27571 + return 206; /* wsr.intclear */
27573 + return 208; /* wsr.intenable */
27575 + return 139; /* wsr.ps */
27577 + return 200; /* wsr.vecbase */
27579 + return 190; /* wsr.exccause */
27581 + return 234; /* wsr.debugcause */
27583 + return 249; /* wsr.ccount */
27585 + return 237; /* wsr.icount */
27587 + return 240; /* wsr.icountlevel */
27589 + return 184; /* wsr.excvaddr */
27591 + return 252; /* wsr.ccompare0 */
27593 + return 193; /* wsr.misc0 */
27595 + return 196; /* wsr.misc1 */
27599 + return 270; /* sext */
27601 + return 264; /* min */
27603 + return 265; /* max */
27605 + return 266; /* minu */
27607 + return 267; /* maxu */
27609 + return 91; /* moveqz */
27611 + return 92; /* movnez */
27613 + return 93; /* movltz */
27615 + return 94; /* movgez */
27617 + if (Field_st_Slot_inst_get (insn) == 231)
27618 + return 37; /* rur.threadptr */
27621 + if (Field_sr_Slot_inst_get (insn) == 231)
27622 + return 38; /* wur.threadptr */
27628 + return 78; /* extui */
27630 + switch (Field_op2_Slot_inst_get (insn))
27633 + return 18; /* l32e */
27635 + return 19; /* s32e */
27641 + return 85; /* l32r */
27643 + switch (Field_r_Slot_inst_get (insn))
27646 + return 86; /* l8ui */
27648 + return 82; /* l16ui */
27650 + return 84; /* l32i */
27652 + return 101; /* s8i */
27654 + return 99; /* s16i */
27656 + return 100; /* s32i */
27658 + return 83; /* l16si */
27660 + return 90; /* movi */
27662 + return 271; /* l32ai */
27664 + return 39; /* addi */
27666 + return 40; /* addmi */
27668 + return 273; /* s32c1i */
27670 + return 272; /* s32ri */
27674 + switch (Field_n_Slot_inst_get (insn))
27677 + return 76; /* call0 */
27679 + return 7; /* call4 */
27681 + return 6; /* call8 */
27683 + return 5; /* call12 */
27687 + switch (Field_n_Slot_inst_get (insn))
27690 + return 80; /* j */
27692 + switch (Field_m_Slot_inst_get (insn))
27695 + return 72; /* beqz */
27697 + return 73; /* bnez */
27699 + return 75; /* bltz */
27701 + return 74; /* bgez */
27705 + switch (Field_m_Slot_inst_get (insn))
27708 + return 52; /* beqi */
27710 + return 53; /* bnei */
27712 + return 55; /* blti */
27714 + return 54; /* bgei */
27718 + switch (Field_m_Slot_inst_get (insn))
27721 + return 11; /* entry */
27723 + switch (Field_r_Slot_inst_get (insn))
27726 + return 87; /* loop */
27728 + return 88; /* loopnez */
27730 + return 89; /* loopgtz */
27734 + return 59; /* bltui */
27736 + return 58; /* bgeui */
27742 + switch (Field_r_Slot_inst_get (insn))
27745 + return 67; /* bnone */
27747 + return 60; /* beq */
27749 + return 63; /* blt */
27751 + return 65; /* bltu */
27753 + return 68; /* ball */
27755 + return 70; /* bbc */
27758 + return 56; /* bbci */
27760 + return 66; /* bany */
27762 + return 61; /* bne */
27764 + return 62; /* bge */
27766 + return 64; /* bgeu */
27768 + return 69; /* bnall */
27770 + return 71; /* bbs */
27773 + return 57; /* bbsi */
27780 -static xtensa_set_field_fn
27781 -Slot_xt_flix64_slot1_set_field_fns[] = {
27782 - Field_t_Slot_xt_flix64_slot1_set,
27786 - Field_imm8_Slot_xt_flix64_slot1_set,
27787 - Field_s_Slot_xt_flix64_slot1_set,
27788 - Field_imm12b_Slot_xt_flix64_slot1_set,
27792 - Field_offset_Slot_xt_flix64_slot1_set,
27795 - Field_op2_Slot_xt_flix64_slot1_set,
27796 - Field_r_Slot_xt_flix64_slot1_set,
27799 - Field_sae_Slot_xt_flix64_slot1_set,
27800 - Field_sal_Slot_xt_flix64_slot1_set,
27801 - Field_sargt_Slot_xt_flix64_slot1_set,
27843 - Field_op0_s4_Slot_xt_flix64_slot1_set,
27844 - Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_set,
27845 - Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27846 - Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27847 - Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27848 - Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27849 - Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27850 - Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27851 - Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27852 - Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27853 - Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27854 - Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27855 - Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27856 - Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27857 - Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27858 - Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27859 - Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27860 - Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27861 - Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27862 - Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27863 - Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27864 - Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_set,
27905 - Implicit_Field_set,
27906 - Implicit_Field_set,
27907 - Implicit_Field_set,
27908 - Implicit_Field_set,
27909 - Implicit_Field_set,
27910 - Implicit_Field_set,
27911 - Implicit_Field_set,
27912 - Implicit_Field_set,
27913 - Implicit_Field_set,
27914 - Implicit_Field_set,
27915 - Implicit_Field_set,
27916 - Implicit_Field_set
27919 +Slot_inst16b_decode (const xtensa_insnbuf insn)
27921 + switch (Field_op0_Slot_inst16b_get (insn))
27924 + switch (Field_i_Slot_inst16b_get (insn))
27927 + return 33; /* movi.n */
27929 + switch (Field_z_Slot_inst16b_get (insn))
27932 + return 28; /* beqz.n */
27934 + return 29; /* bnez.n */
27940 + switch (Field_r_Slot_inst16b_get (insn))
27943 + return 32; /* mov.n */
27945 + switch (Field_t_Slot_inst16b_get (insn))
27948 + return 35; /* ret.n */
27950 + return 15; /* retw.n */
27952 + return 211; /* break.n */
27954 + if (Field_s_Slot_inst16b_get (insn) == 0)
27955 + return 34; /* nop.n */
27958 + if (Field_s_Slot_inst16b_get (insn) == 0)
27959 + return 30; /* ill.n */
27970 +Slot_inst16a_decode (const xtensa_insnbuf insn)
27972 + switch (Field_op0_Slot_inst16a_get (insn))
27975 + return 31; /* l32i.n */
27977 + return 36; /* s32i.n */
27979 + return 26; /* add.n */
27981 + return 27; /* addi.n */
27986 -static xtensa_get_field_fn
27987 -Slot_xt_flix64_slot2_get_field_fns[] = {
27988 - Field_t_Slot_xt_flix64_slot2_get,
27993 - Field_s_Slot_xt_flix64_slot2_get,
28002 - Field_r_Slot_xt_flix64_slot2_get,
28007 - Field_sargt_Slot_xt_flix64_slot2_get,
28022 - Field_imm7_Slot_xt_flix64_slot2_get,
28071 - Field_op0_s5_Slot_xt_flix64_slot2_get,
28072 - Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_get,
28073 - Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_get,
28074 - Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_get,
28075 - Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_get,
28076 - Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_get,
28077 - Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_get,
28078 - Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_get,
28079 - Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_get,
28080 - Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_get,
28081 - Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_get,
28082 - Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_get,
28083 - Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_get,
28084 - Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_get,
28111 - Implicit_Field_ar0_get,
28112 - Implicit_Field_ar4_get,
28113 - Implicit_Field_ar8_get,
28114 - Implicit_Field_ar12_get,
28115 - Implicit_Field_mr0_get,
28116 - Implicit_Field_mr1_get,
28117 - Implicit_Field_mr2_get,
28118 - Implicit_Field_mr3_get,
28119 - Implicit_Field_bt16_get,
28120 - Implicit_Field_bs16_get,
28121 - Implicit_Field_br16_get,
28122 - Implicit_Field_brall_get
28125 +/* Instruction slots. */
28127 -static xtensa_set_field_fn
28128 -Slot_xt_flix64_slot2_set_field_fns[] = {
28129 - Field_t_Slot_xt_flix64_slot2_set,
28134 - Field_s_Slot_xt_flix64_slot2_set,
28143 - Field_r_Slot_xt_flix64_slot2_set,
28148 - Field_sargt_Slot_xt_flix64_slot2_set,
28163 - Field_imm7_Slot_xt_flix64_slot2_set,
28212 - Field_op0_s5_Slot_xt_flix64_slot2_set,
28213 - Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_set,
28214 - Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_set,
28215 - Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_set,
28216 - Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_set,
28217 - Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_set,
28218 - Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_set,
28219 - Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_set,
28220 - Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_set,
28221 - Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_set,
28222 - Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_set,
28223 - Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_set,
28224 - Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_set,
28225 - Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_set,
28237 +Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn,
28238 + xtensa_insnbuf slotbuf)
28240 + slotbuf[0] = (insn[0] & 0xffffff);
28244 +Slot_x24_Format_inst_0_set (xtensa_insnbuf insn,
28245 + const xtensa_insnbuf slotbuf)
28247 + insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff);
28251 +Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn,
28252 + xtensa_insnbuf slotbuf)
28254 + slotbuf[0] = ((insn[0] & 0xffff00) >> 8);
28258 +Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn,
28259 + const xtensa_insnbuf slotbuf)
28261 + insn[0] = (insn[0] & ~0xffff00) | ((slotbuf[0] & 0xffff) << 8);
28265 +Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn,
28266 + xtensa_insnbuf slotbuf)
28268 + slotbuf[0] = ((insn[0] & 0xffff00) >> 8);
28272 +Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn,
28273 + const xtensa_insnbuf slotbuf)
28275 + insn[0] = (insn[0] & ~0xffff00) | ((slotbuf[0] & 0xffff) << 8);
28278 +static xtensa_get_field_fn
28279 +Slot_inst_get_field_fns[] = {
28280 + Field_t_Slot_inst_get,
28281 + Field_bbi4_Slot_inst_get,
28282 + Field_bbi_Slot_inst_get,
28283 + Field_imm12_Slot_inst_get,
28284 + Field_imm8_Slot_inst_get,
28285 + Field_s_Slot_inst_get,
28286 + Field_imm12b_Slot_inst_get,
28287 + Field_imm16_Slot_inst_get,
28288 + Field_m_Slot_inst_get,
28289 + Field_n_Slot_inst_get,
28290 + Field_offset_Slot_inst_get,
28291 + Field_op0_Slot_inst_get,
28292 + Field_op1_Slot_inst_get,
28293 + Field_op2_Slot_inst_get,
28294 + Field_r_Slot_inst_get,
28295 + Field_sa4_Slot_inst_get,
28296 + Field_sae4_Slot_inst_get,
28297 + Field_sae_Slot_inst_get,
28298 + Field_sal_Slot_inst_get,
28299 + Field_sargt_Slot_inst_get,
28300 + Field_sas4_Slot_inst_get,
28301 + Field_sas_Slot_inst_get,
28302 + Field_sr_Slot_inst_get,
28303 + Field_st_Slot_inst_get,
28304 + Field_thi3_Slot_inst_get,
28305 + Field_imm4_Slot_inst_get,
28306 + Field_mn_Slot_inst_get,
28310 @@ -20837,6 +9122,43 @@ Slot_xt_flix64_slot2_set_field_fns[] = {
28314 + Field_xt_wbr15_imm_Slot_inst_get,
28315 + Field_xt_wbr18_imm_Slot_inst_get,
28316 + Implicit_Field_ar0_get,
28317 + Implicit_Field_ar4_get,
28318 + Implicit_Field_ar8_get,
28319 + Implicit_Field_ar12_get
28322 +static xtensa_set_field_fn
28323 +Slot_inst_set_field_fns[] = {
28324 + Field_t_Slot_inst_set,
28325 + Field_bbi4_Slot_inst_set,
28326 + Field_bbi_Slot_inst_set,
28327 + Field_imm12_Slot_inst_set,
28328 + Field_imm8_Slot_inst_set,
28329 + Field_s_Slot_inst_set,
28330 + Field_imm12b_Slot_inst_set,
28331 + Field_imm16_Slot_inst_set,
28332 + Field_m_Slot_inst_set,
28333 + Field_n_Slot_inst_set,
28334 + Field_offset_Slot_inst_set,
28335 + Field_op0_Slot_inst_set,
28336 + Field_op1_Slot_inst_set,
28337 + Field_op2_Slot_inst_set,
28338 + Field_r_Slot_inst_set,
28339 + Field_sa4_Slot_inst_set,
28340 + Field_sae4_Slot_inst_set,
28341 + Field_sae_Slot_inst_set,
28342 + Field_sal_Slot_inst_set,
28343 + Field_sargt_Slot_inst_set,
28344 + Field_sas4_Slot_inst_set,
28345 + Field_sas_Slot_inst_set,
28346 + Field_sr_Slot_inst_set,
28347 + Field_st_Slot_inst_set,
28348 + Field_thi3_Slot_inst_set,
28349 + Field_imm4_Slot_inst_set,
28350 + Field_mn_Slot_inst_set,
28354 @@ -20845,14 +9167,8 @@ Slot_xt_flix64_slot2_set_field_fns[] = {
28358 - Implicit_Field_set,
28359 - Implicit_Field_set,
28360 - Implicit_Field_set,
28361 - Implicit_Field_set,
28362 - Implicit_Field_set,
28363 - Implicit_Field_set,
28364 - Implicit_Field_set,
28365 - Implicit_Field_set,
28366 + Field_xt_wbr15_imm_Slot_inst_set,
28367 + Field_xt_wbr18_imm_Slot_inst_set,
28368 Implicit_Field_set,
28369 Implicit_Field_set,
28370 Implicit_Field_set,
28371 @@ -20860,94 +9176,22 @@ Slot_xt_flix64_slot2_set_field_fns[] = {
28374 static xtensa_get_field_fn
28375 -Slot_xt_flix64_slot3_get_field_fns[] = {
28376 - Field_t_Slot_xt_flix64_slot3_get,
28378 - Field_bbi_Slot_xt_flix64_slot3_get,
28381 - Field_s_Slot_xt_flix64_slot3_get,
28390 - Field_r_Slot_xt_flix64_slot3_get,
28430 - Field_xt_wbr18_imm_Slot_xt_flix64_slot3_get,
28452 +Slot_inst16a_get_field_fns[] = {
28453 + Field_t_Slot_inst16a_get,
28458 + Field_s_Slot_inst16a_get,
28464 + Field_op0_Slot_inst16a_get,
28467 + Field_r_Slot_inst16a_get,
28471 @@ -20955,93 +9199,44 @@ Slot_xt_flix64_slot3_get_field_fns[] = {
28475 + Field_sr_Slot_inst16a_get,
28476 + Field_st_Slot_inst16a_get,
28478 + Field_imm4_Slot_inst16a_get,
28480 + Field_i_Slot_inst16a_get,
28481 + Field_imm6lo_Slot_inst16a_get,
28482 + Field_imm6hi_Slot_inst16a_get,
28483 + Field_imm7lo_Slot_inst16a_get,
28484 + Field_imm7hi_Slot_inst16a_get,
28485 + Field_z_Slot_inst16a_get,
28486 + Field_imm6_Slot_inst16a_get,
28487 + Field_imm7_Slot_inst16a_get,
28489 - Field_op0_s6_Slot_xt_flix64_slot3_get,
28490 - Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28491 - Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_get,
28492 - Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28493 - Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28494 - Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28495 - Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28496 - Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28497 - Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28498 - Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28499 - Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28500 - Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28501 - Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28502 - Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28503 - Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28504 - Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28505 - Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28506 - Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28507 - Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28508 - Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28509 - Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28510 - Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28511 - Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28512 - Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28513 - Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_get,
28515 Implicit_Field_ar0_get,
28516 Implicit_Field_ar4_get,
28517 Implicit_Field_ar8_get,
28518 - Implicit_Field_ar12_get,
28519 - Implicit_Field_mr0_get,
28520 - Implicit_Field_mr1_get,
28521 - Implicit_Field_mr2_get,
28522 - Implicit_Field_mr3_get,
28523 - Implicit_Field_bt16_get,
28524 - Implicit_Field_bs16_get,
28525 - Implicit_Field_br16_get,
28526 - Implicit_Field_brall_get
28527 + Implicit_Field_ar12_get
28530 static xtensa_set_field_fn
28531 -Slot_xt_flix64_slot3_set_field_fns[] = {
28532 - Field_t_Slot_xt_flix64_slot3_set,
28534 - Field_bbi_Slot_xt_flix64_slot3_set,
28537 - Field_s_Slot_xt_flix64_slot3_set,
28546 - Field_r_Slot_xt_flix64_slot3_set,
28563 +Slot_inst16a_set_field_fns[] = {
28564 + Field_t_Slot_inst16a_set,
28569 + Field_s_Slot_inst16a_set,
28575 + Field_op0_Slot_inst16a_set,
28578 + Field_r_Slot_inst16a_set,
28582 @@ -21049,22 +9244,44 @@ Slot_xt_flix64_slot3_set_field_fns[] = {
28586 + Field_sr_Slot_inst16a_set,
28587 + Field_st_Slot_inst16a_set,
28589 + Field_imm4_Slot_inst16a_set,
28591 + Field_i_Slot_inst16a_set,
28592 + Field_imm6lo_Slot_inst16a_set,
28593 + Field_imm6hi_Slot_inst16a_set,
28594 + Field_imm7lo_Slot_inst16a_set,
28595 + Field_imm7hi_Slot_inst16a_set,
28596 + Field_z_Slot_inst16a_set,
28597 + Field_imm6_Slot_inst16a_set,
28598 + Field_imm7_Slot_inst16a_set,
28601 + Implicit_Field_set,
28602 + Implicit_Field_set,
28603 + Implicit_Field_set,
28604 + Implicit_Field_set
28607 +static xtensa_get_field_fn
28608 +Slot_inst16b_get_field_fns[] = {
28609 + Field_t_Slot_inst16b_get,
28611 - Field_xt_wbr18_imm_Slot_xt_flix64_slot3_set,
28615 + Field_s_Slot_inst16b_get,
28621 + Field_op0_Slot_inst16b_get,
28624 + Field_r_Slot_inst16b_get,
28628 @@ -21072,21 +9289,44 @@ Slot_xt_flix64_slot3_set_field_fns[] = {
28632 + Field_sr_Slot_inst16b_get,
28633 + Field_st_Slot_inst16b_get,
28635 + Field_imm4_Slot_inst16b_get,
28637 + Field_i_Slot_inst16b_get,
28638 + Field_imm6lo_Slot_inst16b_get,
28639 + Field_imm6hi_Slot_inst16b_get,
28640 + Field_imm7lo_Slot_inst16b_get,
28641 + Field_imm7hi_Slot_inst16b_get,
28642 + Field_z_Slot_inst16b_get,
28643 + Field_imm6_Slot_inst16b_get,
28644 + Field_imm7_Slot_inst16b_get,
28647 + Implicit_Field_ar0_get,
28648 + Implicit_Field_ar4_get,
28649 + Implicit_Field_ar8_get,
28650 + Implicit_Field_ar12_get
28653 +static xtensa_set_field_fn
28654 +Slot_inst16b_set_field_fns[] = {
28655 + Field_t_Slot_inst16b_set,
28660 + Field_s_Slot_inst16b_set,
28666 + Field_op0_Slot_inst16b_set,
28669 + Field_r_Slot_inst16b_set,
28673 @@ -21094,46 +9334,24 @@ Slot_xt_flix64_slot3_set_field_fns[] = {
28677 + Field_sr_Slot_inst16b_set,
28678 + Field_st_Slot_inst16b_set,
28680 + Field_imm4_Slot_inst16b_set,
28682 + Field_i_Slot_inst16b_set,
28683 + Field_imm6lo_Slot_inst16b_set,
28684 + Field_imm6hi_Slot_inst16b_set,
28685 + Field_imm7lo_Slot_inst16b_set,
28686 + Field_imm7hi_Slot_inst16b_set,
28687 + Field_z_Slot_inst16b_set,
28688 + Field_imm6_Slot_inst16b_set,
28689 + Field_imm7_Slot_inst16b_set,
28691 - Field_op0_s6_Slot_xt_flix64_slot3_set,
28692 - Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28693 - Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_set,
28694 - Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28695 - Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28696 - Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28697 - Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28698 - Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28699 - Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28700 - Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28701 - Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28702 - Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28703 - Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28704 - Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28705 - Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28706 - Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28707 - Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28708 - Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28709 - Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28710 - Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28711 - Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28712 - Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28713 - Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28714 - Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28715 - Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_set,
28717 Implicit_Field_set,
28718 Implicit_Field_set,
28719 Implicit_Field_set,
28720 - Implicit_Field_set,
28721 - Implicit_Field_set,
28722 - Implicit_Field_set,
28723 - Implicit_Field_set,
28724 - Implicit_Field_set,
28725 - Implicit_Field_set,
28726 - Implicit_Field_set,
28727 - Implicit_Field_set,
28731 @@ -21149,27 +9367,7 @@ static xtensa_slot_internal slots[] = {
28732 { "Inst16b", "x16b", 0,
28733 Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set,
28734 Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns,
28735 - Slot_inst16b_decode, "nop.n" },
28736 - { "xt_flix64_slot0", "xt_format1", 0,
28737 - Slot_xt_format1_Format_xt_flix64_slot0_4_get, Slot_xt_format1_Format_xt_flix64_slot0_4_set,
28738 - Slot_xt_flix64_slot0_get_field_fns, Slot_xt_flix64_slot0_set_field_fns,
28739 - Slot_xt_flix64_slot0_decode, "nop" },
28740 - { "xt_flix64_slot0", "xt_format2", 0,
28741 - Slot_xt_format2_Format_xt_flix64_slot0_4_get, Slot_xt_format2_Format_xt_flix64_slot0_4_set,
28742 - Slot_xt_flix64_slot0_get_field_fns, Slot_xt_flix64_slot0_set_field_fns,
28743 - Slot_xt_flix64_slot0_decode, "nop" },
28744 - { "xt_flix64_slot1", "xt_format1", 1,
28745 - Slot_xt_format1_Format_xt_flix64_slot1_28_get, Slot_xt_format1_Format_xt_flix64_slot1_28_set,
28746 - Slot_xt_flix64_slot1_get_field_fns, Slot_xt_flix64_slot1_set_field_fns,
28747 - Slot_xt_flix64_slot1_decode, "nop" },
28748 - { "xt_flix64_slot2", "xt_format1", 2,
28749 - Slot_xt_format1_Format_xt_flix64_slot2_48_get, Slot_xt_format1_Format_xt_flix64_slot2_48_set,
28750 - Slot_xt_flix64_slot2_get_field_fns, Slot_xt_flix64_slot2_set_field_fns,
28751 - Slot_xt_flix64_slot2_decode, "nop" },
28752 - { "xt_flix64_slot3", "xt_format2", 1,
28753 - Slot_xt_format2_Format_xt_flix64_slot3_28_get, Slot_xt_format2_Format_xt_flix64_slot3_28_set,
28754 - Slot_xt_flix64_slot3_get_field_fns, Slot_xt_flix64_slot3_set_field_fns,
28755 - Slot_xt_flix64_slot3_decode, "nop" }
28756 + Slot_inst16b_decode, "nop.n" }
28760 @@ -21179,35 +9377,18 @@ static void
28761 Format_x24_encode (xtensa_insnbuf insn)
28768 Format_x16a_encode (xtensa_insnbuf insn)
28772 + insn[0] = 0x800000;
28776 Format_x16b_encode (xtensa_insnbuf insn)
28783 -Format_xt_format1_encode (xtensa_insnbuf insn)
28790 -Format_xt_format2_encode (xtensa_insnbuf insn)
28794 + insn[0] = 0xc00000;
28797 static int Format_x24_slots[] = { 0 };
28798 @@ -21216,32 +9397,22 @@ static int Format_x16a_slots[] = { 1 };
28800 static int Format_x16b_slots[] = { 2 };
28802 -static int Format_xt_format1_slots[] = { 3, 5, 6 };
28804 -static int Format_xt_format2_slots[] = { 4, 7 };
28806 static xtensa_format_internal formats[] = {
28807 { "x24", 3, Format_x24_encode, 1, Format_x24_slots },
28808 { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots },
28809 - { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots },
28810 - { "xt_format1", 8, Format_xt_format1_encode, 3, Format_xt_format1_slots },
28811 - { "xt_format2", 8, Format_xt_format2_encode, 2, Format_xt_format2_slots }
28812 + { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots }
28817 format_decoder (const xtensa_insnbuf insn)
28819 - if ((insn[0] & 0x8) == 0 && (insn[1] & 0) == 0)
28820 + if ((insn[0] & 0x800000) == 0)
28821 return 0; /* x24 */
28822 - if ((insn[0] & 0xc) == 0x8 && (insn[1] & 0) == 0)
28823 + if ((insn[0] & 0xc00000) == 0x800000)
28824 return 1; /* x16a */
28825 - if ((insn[0] & 0xe) == 0xc && (insn[1] & 0) == 0)
28826 + if ((insn[0] & 0xe00000) == 0xc00000)
28827 return 2; /* x16b */
28828 - if ((insn[0] & 0xf) == 0xe && (insn[1] & 0) == 0)
28829 - return 3; /* xt_format1 */
28830 - if ((insn[0] & 0xf) == 0xf && (insn[1] & 0x80000000) == 0)
28831 - return 4; /* xt_format2 */
28835 @@ -21260,14 +9431,14 @@ static int length_table[16] = {
28846 length_decoder (const unsigned char *insn)
28848 - int op0 = insn[0] & 0xf;
28849 + int op0 = (insn[0] >> 4) & 0xf;
28850 return length_table[op0];
28853 @@ -21275,15 +9446,15 @@ length_decoder (const unsigned char *insn)
28854 /* Top-level ISA structure. */
28856 xtensa_isa_internal xtensa_modules = {
28857 - 0 /* little-endian */,
28858 - 8 /* insn_size */, 0,
28859 - 5, formats, format_decoder, length_decoder,
28861 - 135 /* num_fields */,
28866 + 1 /* big-endian */,
28867 + 3 /* insn_size */, 0,
28868 + 3, formats, format_decoder, length_decoder,
28870 + 41 /* num_fields */,
28875 NUM_STATES, states, 0,
28876 NUM_SYSREGS, sysregs, 0,
28877 { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 },
28878 diff --git a/include/xtensa-config.h b/include/xtensa-config.h
28879 index 30f4f41..fe9b051 100644
28880 --- a/include/xtensa-config.h
28881 +++ b/include/xtensa-config.h
28883 #define XCHAL_HAVE_L32R 1
28885 #undef XSHAL_USE_ABSOLUTE_LITERALS
28886 -#define XSHAL_USE_ABSOLUTE_LITERALS 0
28888 -#undef XSHAL_HAVE_TEXT_SECTION_LITERALS
28889 -#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */
28890 +#define XSHAL_USE_ABSOLUTE_LITERALS 1
28892 #undef XCHAL_HAVE_MAC16
28893 #define XCHAL_HAVE_MAC16 0
28894 @@ -59,10 +56,10 @@
28895 #define XCHAL_HAVE_MUL32 1
28897 #undef XCHAL_HAVE_MUL32_HIGH
28898 -#define XCHAL_HAVE_MUL32_HIGH 0
28899 +#define XCHAL_HAVE_MUL32_HIGH 1
28901 #undef XCHAL_HAVE_DIV32
28902 -#define XCHAL_HAVE_DIV32 1
28903 +#define XCHAL_HAVE_DIV32 0
28905 #undef XCHAL_HAVE_NSA
28906 #define XCHAL_HAVE_NSA 1
28907 @@ -103,8 +100,6 @@
28908 #undef XCHAL_HAVE_FP_RSQRT
28909 #define XCHAL_HAVE_FP_RSQRT 0
28911 -#undef XCHAL_HAVE_DFP_accel
28912 -#define XCHAL_HAVE_DFP_accel 0
28913 #undef XCHAL_HAVE_WINDOWED
28914 #define XCHAL_HAVE_WINDOWED 1
28916 @@ -119,32 +114,32 @@
28919 #undef XCHAL_ICACHE_SIZE
28920 -#define XCHAL_ICACHE_SIZE 16384
28921 +#define XCHAL_ICACHE_SIZE 0
28923 #undef XCHAL_DCACHE_SIZE
28924 -#define XCHAL_DCACHE_SIZE 16384
28925 +#define XCHAL_DCACHE_SIZE 0
28927 #undef XCHAL_ICACHE_LINESIZE
28928 -#define XCHAL_ICACHE_LINESIZE 32
28929 +#define XCHAL_ICACHE_LINESIZE 16
28931 #undef XCHAL_DCACHE_LINESIZE
28932 -#define XCHAL_DCACHE_LINESIZE 32
28933 +#define XCHAL_DCACHE_LINESIZE 16
28935 #undef XCHAL_ICACHE_LINEWIDTH
28936 -#define XCHAL_ICACHE_LINEWIDTH 5
28937 +#define XCHAL_ICACHE_LINEWIDTH 4
28939 #undef XCHAL_DCACHE_LINEWIDTH
28940 -#define XCHAL_DCACHE_LINEWIDTH 5
28941 +#define XCHAL_DCACHE_LINEWIDTH 4
28943 #undef XCHAL_DCACHE_IS_WRITEBACK
28944 -#define XCHAL_DCACHE_IS_WRITEBACK 1
28945 +#define XCHAL_DCACHE_IS_WRITEBACK 0
28948 #undef XCHAL_HAVE_MMU
28949 #define XCHAL_HAVE_MMU 1
28951 #undef XCHAL_MMU_MIN_PTE_PAGE_SIZE
28952 -#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12
28953 +#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 29
28956 #undef XCHAL_HAVE_DEBUG
28957 @@ -157,8 +152,11 @@
28958 #define XCHAL_NUM_DBREAK 2
28960 #undef XCHAL_DEBUGLEVEL
28961 -#define XCHAL_DEBUGLEVEL 6
28962 +#define XCHAL_DEBUGLEVEL 4
28965 +#undef XCHAL_EXCM_LEVEL
28966 +#define XCHAL_EXCM_LEVEL 3
28968 #undef XCHAL_MAX_INSTRUCTION_SIZE
28969 #define XCHAL_MAX_INSTRUCTION_SIZE 3
28973 diff --git a/gas/config/tc-xtensa.c b/gas/config/tc-xtensa.c
28974 index d062044..ca261ae 100644
28975 --- a/gas/config/tc-xtensa.c
28976 +++ b/gas/config/tc-xtensa.c
28977 @@ -2228,7 +2228,7 @@ xg_reverse_shift_count (char **cnt_argp)
28978 cnt_arg = *cnt_argp;
28980 /* replace the argument with "31-(argument)" */
28981 - new_arg = concat ("31-(", cnt_argp, ")", (char *) NULL);
28982 + new_arg = concat ("31-(", cnt_arg, ")", (char *) NULL);
28985 *cnt_argp = new_arg;