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adba5f08 DM |
1 | ;;; GNU Guix --- Functional package management for GNU |
2 | ;;; Copyright © 2016 Danny Milosavljevic <dannym@scratchpost.org> | |
d109b1e8 | 3 | ;;; Copyright © 2016, 2017 Theodoros Foradis <theodoros@foradis.org> |
91d2e6f9 | 4 | ;;; Copyright © 2018–2021 Tobias Geerinckx-Rice <me@tobias.gr> |
c2cf286c | 5 | ;;; Copyright © 2019 Amin Bandali <bandali@gnu.org> |
44a4810a | 6 | ;;; Copyright © 2020 Vinicius Monego <monego@posteo.net> |
1a0907ab | 7 | ;;; Copyright © 2021 Andrew Miloradovsky <andrew@interpretmath.pw> |
adba5f08 DM |
8 | ;;; |
9 | ;;; This file is part of GNU Guix. | |
10 | ;;; | |
11 | ;;; GNU Guix is free software; you can redistribute it and/or modify it | |
12 | ;;; under the terms of the GNU General Public License as published by | |
13 | ;;; the Free Software Foundation; either version 3 of the License, or (at | |
14 | ;;; your option) any later version. | |
15 | ;;; | |
16 | ;;; GNU Guix is distributed in the hope that it will be useful, but | |
17 | ;;; WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | ;;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | ;;; GNU General Public License for more details. | |
20 | ;;; | |
21 | ;;; You should have received a copy of the GNU General Public License | |
22 | ;;; along with GNU Guix. If not, see <http://www.gnu.org/licenses/>. | |
23 | ||
24 | (define-module (gnu packages fpga) | |
25 | #:use-module ((guix licenses) #:prefix license:) | |
26 | #:use-module (guix packages) | |
27 | #:use-module (guix download) | |
28 | #:use-module (guix git-download) | |
29 | #:use-module (guix build-system gnu) | |
30 | #:use-module (guix build-system cmake) | |
2b5eaf0e | 31 | #:use-module (guix build-system python) |
adba5f08 | 32 | #:use-module (gnu packages) |
492826ec DM |
33 | #:use-module (gnu packages autotools) |
34 | #:use-module (gnu packages base) | |
148585c2 | 35 | #:use-module (gnu packages compression) |
adba5f08 DM |
36 | #:use-module (gnu packages pkg-config) |
37 | #:use-module (gnu packages tcl) | |
38 | #:use-module (gnu packages readline) | |
39 | #:use-module (gnu packages python) | |
44a4810a | 40 | #:use-module (gnu packages python-xyz) |
adba5f08 | 41 | #:use-module (gnu packages bison) |
492826ec | 42 | #:use-module (gnu packages check) |
adba5f08 | 43 | #:use-module (gnu packages flex) |
492826ec | 44 | #:use-module (gnu packages gettext) |
adc2f048 | 45 | #:use-module (gnu packages gtk) |
f90f6b68 | 46 | #:use-module (gnu packages graphviz) |
adba5f08 | 47 | #:use-module (gnu packages libffi) |
f90f6b68 | 48 | #:use-module (gnu packages linux) |
492826ec | 49 | #:use-module (gnu packages llvm) |
85cdab64 | 50 | #:use-module (gnu packages maths) |
adba5f08 DM |
51 | #:use-module (gnu packages perl) |
52 | #:use-module (gnu packages ghostscript) | |
adc2f048 | 53 | #:use-module (gnu packages gperf) |
adba5f08 DM |
54 | #:use-module (gnu packages gawk) |
55 | #:use-module (gnu packages version-control) | |
363989e6 | 56 | #:use-module (gnu packages qt) |
57 | #:use-module (gnu packages boost) | |
58 | #:use-module (gnu packages algebra) | |
adba5f08 DM |
59 | #:use-module (gnu packages libftdi)) |
60 | ||
61 | (define-public abc | |
62 | (let ((commit "5ae4b975c49c") | |
63 | (revision "1")) | |
64 | (package | |
65 | (name "abc") | |
ec299312 | 66 | (version (git-version "0.0" revision commit)) |
adba5f08 DM |
67 | (source (origin |
68 | (method url-fetch) | |
69 | (uri | |
70 | (string-append "https://bitbucket.org/alanmi/abc/get/" commit ".zip")) | |
71 | (file-name (string-append name "-" version "-checkout.zip")) | |
72 | (sha256 | |
ec299312 JK |
73 | (base32 |
74 | "1syygi1x40rdryih3galr4q8yg1w5bvdzl75hd27v1xq0l5bz3d0")))) | |
adba5f08 DM |
75 | (build-system gnu-build-system) |
76 | (native-inputs | |
77 | `(("unzip" ,unzip))) | |
78 | (inputs | |
79 | `(("readline" ,readline))) | |
80 | (arguments | |
81 | `(#:tests? #f ; no check target | |
82 | #:phases | |
83 | (modify-phases %standard-phases | |
84 | (delete 'configure) | |
85 | (replace 'install | |
86 | (lambda* (#:key outputs #:allow-other-keys) | |
87 | (let* ((out (assoc-ref outputs "out")) | |
88 | (out-bin (string-append out "/bin"))) | |
89 | (install-file "abc" out-bin))))))) | |
3bc9f9e7 | 90 | (home-page "https://people.eecs.berkeley.edu/~alanmi/abc/") |
adba5f08 DM |
91 | (synopsis "Sequential logic synthesis and formal verification") |
92 | (description "ABC is a program for sequential logic synthesis and | |
93 | formal verification.") | |
94 | (license | |
95 | (license:non-copyleft "https://fedoraproject.org/wiki/Licensing:MIT#Modern_Variants"))))) | |
44721336 DM |
96 | |
97 | (define-public iverilog | |
98 | (package | |
99 | (name "iverilog") | |
f27cb0f1 | 100 | (version "10.3") |
44721336 DM |
101 | (source (origin |
102 | (method url-fetch) | |
103 | (uri | |
104 | (string-append "ftp://ftp.icarus.com/pub/eda/verilog/v10/" | |
105 | "verilog-" version ".tar.gz")) | |
106 | (sha256 | |
f27cb0f1 TGR |
107 | (base32 |
108 | "1vv88ckvfwq7mrysyjnilsrcrzm9d173kp9w5ivwh6rdw7klbgc6")))) | |
44721336 DM |
109 | (build-system gnu-build-system) |
110 | (native-inputs | |
111 | `(("flex" ,flex) | |
112 | ("bison" ,bison) | |
f27cb0f1 | 113 | ("ghostscript" ,ghostscript))) ; ps2pdf |
44721336 DM |
114 | (home-page "http://iverilog.icarus.com/") |
115 | (synopsis "FPGA Verilog simulation and synthesis tool") | |
116 | (description "Icarus Verilog is a Verilog simulation and synthesis tool. | |
117 | It operates as a compiler, compiling source code written in Verilog | |
118 | (IEEE-1364) into some target format. | |
119 | For batch simulation, the compiler can generate an intermediate form | |
120 | called vvp assembly. | |
77659ff3 | 121 | This intermediate form is executed by @command{vvp}. |
44721336 DM |
122 | For synthesis, the compiler generates netlists in the desired format.") |
123 | ;; GPL2 only because of: | |
124 | ;; - ./driver/iverilog.man.in | |
125 | ;; - ./iverilog-vpi.man.in | |
126 | ;; - ./tgt-fpga/iverilog-fpga.man | |
127 | ;; - ./vvp/vvp.man.in | |
128 | ;; Otherwise would be GPL2+. | |
129 | ;; You have to accept both GPL2 and LGPL2.1+. | |
130 | (license (list license:gpl2 license:lgpl2.1+)))) | |
92fc940f DM |
131 | |
132 | (define-public yosys | |
133 | (package | |
134 | (name "yosys") | |
922c8486 | 135 | (version "0.9") |
92fc940f | 136 | (source (origin |
21fc352b TGR |
137 | (method git-fetch) |
138 | (uri (git-reference | |
b0e7b699 | 139 | (url "https://github.com/cliffordwolf/yosys") |
21fc352b TGR |
140 | (commit (string-append "yosys-" version)) |
141 | (recursive? #t))) ; for the ‘iverilog’ submodule | |
92fc940f DM |
142 | (sha256 |
143 | (base32 | |
922c8486 | 144 | "0lb9r055h8y1vj2z8gm4ip0v06j5mk7f9zx9gi67kkqb7g4rhjli")) |
21fc352b | 145 | (file-name (git-file-name name version)) |
92fc940f DM |
146 | (modules '((guix build utils))) |
147 | (snippet | |
6cbee49d MW |
148 | '(begin |
149 | (substitute* "Makefile" | |
150 | (("ABCREV = .*") "ABCREV = default\n")) | |
151 | #t)))) | |
92fc940f DM |
152 | (build-system gnu-build-system) |
153 | (arguments | |
154 | `(#:test-target "test" | |
155 | #:make-flags (list "CC=gcc" | |
156 | "CXX=g++" | |
157 | (string-append "PREFIX=" %output)) | |
158 | #:phases | |
159 | (modify-phases %standard-phases | |
f90f6b68 TF |
160 | (add-before 'configure 'fix-paths |
161 | (lambda _ | |
162 | (substitute* "./passes/cmds/show.cc" | |
163 | (("exec xdot") (string-append "exec " (which "xdot"))) | |
164 | (("dot -") (string-append (which "dot") " -")) | |
165 | (("fuser") (which "fuser"))) | |
166 | #t)) | |
92fc940f DM |
167 | (replace 'configure |
168 | (lambda* (#:key inputs (make-flags '()) #:allow-other-keys) | |
99f6ef9a | 169 | (apply invoke "make" "config-gcc" make-flags))) |
92fc940f DM |
170 | (add-after 'configure 'prepare-abc |
171 | (lambda* (#:key inputs #:allow-other-keys) | |
172 | (let* ((sourceabc (assoc-ref inputs "abc")) | |
173 | (sourcebin (string-append sourceabc "/bin")) | |
174 | (source (string-append sourcebin "/abc"))) | |
175 | (mkdir-p "abc") | |
176 | (call-with-output-file "abc/Makefile" | |
177 | (lambda (port) | |
178 | (format port ".PHONY: all\nall:\n\tcp -f abc abc-default\n"))) | |
179 | (copy-file source "abc/abc") | |
99f6ef9a | 180 | (invoke "chmod" "+w" "abc/abc")))) |
92fc940f DM |
181 | (add-before 'check 'fix-iverilog-references |
182 | (lambda* (#:key inputs native-inputs #:allow-other-keys) | |
183 | (let* ((xinputs (or native-inputs inputs)) | |
184 | (xdirname (assoc-ref xinputs "iverilog")) | |
185 | (iverilog (string-append xdirname "/bin/iverilog"))) | |
186 | (substitute* '("./manual/CHAPTER_StateOfTheArt/synth.sh" | |
187 | "./manual/CHAPTER_StateOfTheArt/validate_tb.sh" | |
188 | "./techlibs/ice40/tests/test_bram.sh" | |
189 | "./techlibs/ice40/tests/test_ffs.sh" | |
190 | "./techlibs/xilinx/tests/bram1.sh" | |
191 | "./techlibs/xilinx/tests/bram2.sh" | |
192 | "./tests/bram/run-single.sh" | |
193 | "./tests/realmath/run-test.sh" | |
194 | "./tests/simple/run-test.sh" | |
195 | "./tests/techmap/mem_simple_4x1_runtest.sh" | |
196 | "./tests/tools/autotest.sh" | |
197 | "./tests/vloghtb/common.sh") | |
198 | (("if ! which iverilog") "if ! true") | |
199 | (("iverilog ") (string-append iverilog " ")) | |
200 | (("iverilog_bin=\".*\"") (string-append "iverilog_bin=\"" | |
201 | iverilog "\""))) | |
202 | #t)))))) | |
92fc940f DM |
203 | (native-inputs |
204 | `(("pkg-config" ,pkg-config) | |
205 | ("python" ,python) | |
206 | ("bison" ,bison) | |
207 | ("flex" ,flex) | |
208 | ("gawk" , gawk) ; for the tests and "make" progress pretty-printing | |
209 | ("tcl" ,tcl) ; tclsh for the tests | |
210 | ("iverilog" ,iverilog))) ; for the tests | |
211 | (inputs | |
212 | `(("tcl" ,tcl) | |
213 | ("readline" ,readline) | |
214 | ("libffi" ,libffi) | |
f90f6b68 TF |
215 | ("graphviz" ,graphviz) |
216 | ("psmisc" ,psmisc) | |
217 | ("xdot" ,xdot) | |
92fc940f | 218 | ("abc" ,abc))) |
85cdab64 TF |
219 | (propagated-inputs |
220 | `(("z3" ,z3))) ; should be in path for yosys-smtbmc | |
92fc940f DM |
221 | (home-page "http://www.clifford.at/yosys/") |
222 | (synopsis "FPGA Verilog RTL synthesizer") | |
223 | (description "Yosys synthesizes Verilog-2005.") | |
224 | (license license:isc))) | |
36aa11c7 DM |
225 | |
226 | (define-public icestorm | |
179be4bb | 227 | (let ((commit "0ec00d892a91cc68e45479b46161f649caea2933") |
228 | (revision "3")) | |
36aa11c7 DM |
229 | (package |
230 | (name "icestorm") | |
ec299312 | 231 | (version (git-version "0.0" revision commit)) |
36aa11c7 DM |
232 | (source (origin |
233 | (method git-fetch) | |
234 | (uri (git-reference | |
b0e7b699 | 235 | (url "https://github.com/cliffordwolf/icestorm") |
36aa11c7 | 236 | (commit commit))) |
ec299312 | 237 | (file-name (git-file-name name version)) |
36aa11c7 DM |
238 | (sha256 |
239 | (base32 | |
179be4bb | 240 | "1qlh99fafb7xga702k64fmc9m700nsddrfgcq4x8qn8fplsb64f1")))) |
36aa11c7 DM |
241 | (build-system gnu-build-system) |
242 | (arguments | |
243 | `(#:tests? #f ; no unit tests that don't need an FPGA exist. | |
244 | #:make-flags (list "CC=gcc" "CXX=g++" | |
245 | (string-append "PREFIX=" (assoc-ref %outputs "out"))) | |
246 | #:phases | |
247 | (modify-phases %standard-phases | |
248 | (add-after 'unpack 'remove-usr-local | |
249 | (lambda _ | |
250 | (substitute* "iceprog/Makefile" | |
251 | (("-I/usr/local/include") "") | |
252 | (("-L/usr/local/lib") "")) | |
253 | #t)) | |
b500dc2e TF |
254 | (add-after 'remove-usr-local 'fix-usr-local |
255 | (lambda* (#:key outputs #:allow-other-keys) | |
256 | (substitute* "icebox/icebox_vlog.py" | |
257 | (("/usr/local/share") (string-append (assoc-ref outputs "out") "/share"))) | |
258 | #t)) | |
36aa11c7 DM |
259 | (delete 'configure)))) |
260 | (inputs | |
261 | `(("libftdi" ,libftdi))) | |
262 | (native-inputs | |
263 | `(("python-3" ,python) | |
264 | ("pkg-config" ,pkg-config))) | |
265 | (home-page "http://www.clifford.at/icestorm/") | |
266 | (synopsis "Project IceStorm - Lattice iCE40 FPGAs bitstream tools") | |
267 | (description "Project IceStorm - Lattice iCE40 FPGAs Bitstream Tools. | |
268 | Includes the actual FTDI connector.") | |
269 | (license license:isc)))) | |
bca3797b | 270 | |
363989e6 | 271 | (define-public nextpnr-ice40 |
09d18c67 MFG |
272 | (let [(commit "fbe486df459909065d6852a7495a212dfd2accef") |
273 | (revision "1")] | |
29bf0aa3 EF |
274 | (package |
275 | (name "nextpnr-ice40") | |
276 | (version (git-version "0.0.0" revision commit)) | |
277 | (source | |
278 | (origin | |
279 | (method git-fetch) | |
280 | (uri (git-reference | |
281 | (url "git://github.com/YosysHQ/nextpnr") | |
282 | (commit commit))) | |
283 | (file-name (git-file-name name version)) | |
284 | (sha256 | |
285 | (base32 | |
09d18c67 | 286 | "1fmxsywgs45g88ra7ips5s2niiiwrkyxdcy742ws18dfk2y4vi9c")))) |
29bf0aa3 | 287 | (inputs |
7dffabf8 | 288 | `(("boost" ,boost) |
29bf0aa3 | 289 | ("eigen" ,eigen) |
7dffabf8 | 290 | ("icestorm" ,icestorm) |
29bf0aa3 | 291 | ("python" ,python) |
7dffabf8 EF |
292 | ("qtbase" ,qtbase) |
293 | ("yosys" ,yosys))) | |
29bf0aa3 EF |
294 | (build-system cmake-build-system) |
295 | (arguments | |
296 | `(#:configure-flags `("-DARCH=ice40" | |
297 | ,(string-append "-DICEBOX_ROOT=" | |
298 | (assoc-ref %build-inputs "icestorm") | |
299 | "/share/icebox")) | |
300 | #:tests? #f)) | |
301 | (synopsis "Place-and-Route tool for FPGAs") | |
302 | (description "Nextpnr aims to be a vendor neutral, timing driven, | |
a4649802 | 303 | FOSS FPGA place and route tool.") |
29bf0aa3 EF |
304 | (home-page "https://github.com/YosysHQ/nextpnr") |
305 | (license license:expat)))) | |
363989e6 | 306 | |
bca3797b | 307 | (define-public arachne-pnr |
e82baf69 AB |
308 | (let ((commit "840bdfdeb38809f9f6af4d89dd7b22959b176fdd") |
309 | (revision "2")) | |
bca3797b DM |
310 | (package |
311 | (name "arachne-pnr") | |
312 | (version (string-append "0.0-" revision "-" (string-take commit 9))) | |
313 | (source (origin | |
314 | (method git-fetch) | |
315 | (uri (git-reference | |
b0e7b699 | 316 | (url "https://github.com/YosysHQ/arachne-pnr") |
bca3797b | 317 | (commit commit))) |
ec299312 | 318 | (file-name (git-file-name name version)) |
bca3797b DM |
319 | (sha256 |
320 | (base32 | |
e82baf69 | 321 | "1dqvjvgvsridybishv4pnigw9gypxh7r7nrqp9z9qq92v7c5rxzl")))) |
bca3797b DM |
322 | (build-system gnu-build-system) |
323 | (arguments | |
324 | `(#:test-target "test" | |
eccd3f6d DM |
325 | #:make-flags |
326 | (list (string-append "DESTDIR=" (assoc-ref %outputs "out")) | |
327 | (string-append "ICEBOX=" (string-append | |
328 | (assoc-ref %build-inputs "icestorm") | |
329 | "/share/icebox"))) | |
bca3797b DM |
330 | #:phases (modify-phases %standard-phases |
331 | (replace 'configure | |
332 | (lambda* (#:key outputs inputs #:allow-other-keys) | |
bca3797b DM |
333 | (substitute* '("./tests/fsm/generate.py" |
334 | "./tests/combinatorial/generate.py") | |
335 | (("#!/usr/bin/python") "#!/usr/bin/python2")) | |
336 | #t))))) | |
337 | (inputs | |
338 | `(("icestorm" ,icestorm))) | |
339 | (native-inputs | |
340 | `(("git" ,git) ; for determining its own version string | |
341 | ("yosys" ,yosys) ; for tests | |
342 | ("perl" ,perl) ; for shasum | |
343 | ("python-2" ,python-2))) ; for tests | |
e82baf69 | 344 | (home-page "https://github.com/YosysHQ/arachne-pnr") |
bca3797b DM |
345 | (synopsis "Place-and-Route tool for FPGAs") |
346 | (description "Arachne-PNR is a Place-and-Route Tool For FPGAs.") | |
347 | (license license:gpl2)))) | |
adc2f048 DM |
348 | |
349 | (define-public gtkwave | |
350 | (package | |
351 | (name "gtkwave") | |
91d2e6f9 | 352 | (version "3.3.108") |
82f81ffa TGR |
353 | (source |
354 | (origin | |
355 | (method url-fetch) | |
356 | (uri (list (string-append "mirror://sourceforge/gtkwave/" | |
357 | "gtkwave-" version "/" | |
358 | "gtkwave-" version ".tar.gz") | |
359 | (string-append "http://gtkwave.sourceforge.net/" | |
360 | "gtkwave-" version ".tar.gz"))) | |
361 | (sha256 | |
91d2e6f9 | 362 | (base32 "0fzbap72zm4ka6n85j0873fpaarrx199ay0kjw1avrs20hs4gr7c")))) |
adc2f048 DM |
363 | (build-system gnu-build-system) |
364 | (native-inputs | |
365 | `(("gperf" ,gperf) | |
366 | ("pkg-config" ,pkg-config))) | |
367 | (inputs | |
368 | `(("tcl" ,tcl) | |
369 | ("tk" ,tk) | |
370 | ("gtk+-2" ,gtk+-2))) | |
371 | (arguments | |
372 | `(#:configure-flags | |
373 | (list (string-append "--with-tcl=" | |
374 | (assoc-ref %build-inputs "tcl") | |
375 | "/lib") | |
376 | (string-append "--with-tk=" | |
377 | (assoc-ref %build-inputs "tk") | |
378 | "/lib")))) | |
379 | ||
380 | (synopsis "Waveform viewer for FPGA simulator trace files") | |
381 | (description "This package is a waveform viewer for FPGA | |
1e6191bb | 382 | simulator trace files (@dfn{FST}).") |
adc2f048 | 383 | (home-page "http://gtkwave.sourceforge.net/") |
1e6191bb | 384 | ;; Exception against free government use in tcl_np.c and tcl_np.h. |
adc2f048 | 385 | (license (list license:gpl2+ license:expat license:tcl/tk)))) |
2b5eaf0e | 386 | |
44a4810a VM |
387 | (define-public python-migen |
388 | (package | |
389 | (name "python-migen") | |
390 | (version "0.9.2") | |
391 | (source | |
392 | (origin | |
393 | ;; Tests fail in the PyPI tarball due to missing files. | |
394 | (method git-fetch) | |
395 | (uri (git-reference | |
396 | (url "https://github.com/m-labs/migen") | |
397 | (commit version))) | |
398 | (file-name (git-file-name name version)) | |
399 | (sha256 | |
400 | (base32 "1kq11if64zj84gv4w1q7l16fp17xjxl2wv5hc9dibr1z3m1gy67l")))) | |
401 | (build-system python-build-system) | |
402 | (propagated-inputs | |
403 | `(("python-colorama" ,python-colorama))) | |
404 | (home-page "https://m-labs.hk/gateware/migen/") | |
405 | (synopsis "Python toolbox for building complex digital hardware") | |
406 | (description | |
407 | "Migen FHDL is a Python library that replaces the event-driven | |
408 | paradigm of Verilog and VHDL with the notions of combinatorial and | |
409 | synchronous statements, has arithmetic rules that make integers always | |
410 | behave like mathematical integers, and allows the design's logic to be | |
411 | constructed by a Python program.") | |
412 | (license license:bsd-2))) | |
413 | ||
2b5eaf0e DM |
414 | (define-public python-myhdl |
415 | (package | |
416 | (name "python-myhdl") | |
417 | (version "0.11") | |
418 | (source | |
419 | (origin | |
420 | (method url-fetch) | |
421 | (uri (pypi-uri "myhdl" version)) | |
422 | (sha256 | |
423 | (base32 | |
424 | "04fi59cyn5dsci0ai7djg74ybkqfcjzhj1jfmac2xanbcrw9j3yk")))) | |
425 | (build-system python-build-system) | |
426 | (home-page "http://www.myhdl.org/") | |
427 | (synopsis "Python as a Hardware Description Language") | |
428 | (description "This package provides a library to turn Python into | |
429 | a hardware description and verification language. ") | |
430 | (license license:lgpl2.1+))) | |
492826ec DM |
431 | |
432 | (define-public nvc | |
433 | (package | |
434 | (name "nvc") | |
435 | (version "1.5.0") | |
436 | (source (origin | |
437 | (method git-fetch) | |
438 | (uri (git-reference | |
439 | (url "https://github.com/nickg/nvc.git") | |
440 | (commit (string-append "r" version)))) | |
441 | (file-name (string-append name "-" version "-checkout")) | |
442 | (sha256 | |
443 | (base32 | |
444 | "0dd1xany6qhh2qsfw8ba0ky7y86h19yr4hlk0r5i2bvwsg4355v9")))) | |
445 | (build-system gnu-build-system) | |
446 | (arguments | |
447 | `(#:parallel-build? #f ; https://github.com/nickg/nvc/issues/409 | |
448 | #:configure-flags | |
449 | '("--enable-vhpi") | |
450 | #:phases | |
451 | (modify-phases %standard-phases | |
452 | (add-after 'unpack 'clean-up | |
453 | (lambda _ | |
454 | (delete-file "autogen.sh") | |
455 | #t))))) | |
456 | (native-inputs | |
457 | `(("automake" ,automake) | |
458 | ("autoconf" ,autoconf) | |
459 | ("flex" ,flex) | |
460 | ("gettext" ,gnu-gettext) | |
461 | ("libtool" ,libtool) | |
462 | ("pkg-config" ,pkg-config) | |
463 | ("which" ,which) | |
464 | ("check" ,check))) ; for the tests | |
465 | (inputs | |
466 | `(("llvm" ,llvm-9))) | |
467 | (synopsis "VHDL compiler and simulator") | |
468 | (description "This package provides a VHDL compiler and simulator.") | |
469 | (home-page "https://github.com/nickg/nvc") | |
470 | (license license:gpl3+))) | |
fc4834f8 AM |
471 | |
472 | (define-public systemc | |
473 | (package | |
474 | (name "systemc") | |
475 | (version "2.3.3") | |
476 | (source | |
477 | (origin | |
478 | (method url-fetch) | |
479 | (uri (string-append | |
480 | "https://accellera.org/images/downloads/standards/" | |
481 | "systemc/systemc-" version ".tar.gz")) | |
482 | (sha256 | |
483 | (base32 "0gvv3xmhiwx1izmzy06yslzqzh6ygrgmw53xqfmyvbz5a6ivk0ap")))) | |
484 | (native-inputs `(("perl" ,perl))) | |
485 | (build-system gnu-build-system) | |
486 | (arguments '(#:configure-flags '("--enable-debug"))) | |
487 | (home-page "https://accellera.org/community/systemc") | |
488 | (synopsis "Library for event-driven simulation") | |
489 | (description | |
490 | "SystemC is a C++ library for modeling concurrent systems, and the | |
491 | reference implementation of IEEE 1666-2011. It provides a notion of timing as | |
492 | well as an event-driven simulations environment. Due to its concurrent and | |
493 | sequential nature, SystemC allows the description and integration of complex | |
494 | hardware and software components. To some extent, SystemC can be seen as | |
495 | a Hardware Description Language. However, unlike VHDL or Verilog, SystemC | |
496 | provides sophisticated mechanisms that offer high abstraction levels on | |
497 | components interfaces. This, in turn, facilitates the integration of systems | |
498 | using different abstraction levels.") | |
499 | ;; homepages.cae.wisc.edu/~ece734/SystemC/Esperan_SystemC_tutorial.pdf | |
500 | (license license:asl2.0))) | |
1a0907ab AM |
501 | |
502 | (define-public verilator | |
503 | (package | |
504 | (name "verilator") | |
1462a11d | 505 | (version "4.110") |
1a0907ab AM |
506 | (source |
507 | (origin | |
508 | (method git-fetch) | |
509 | (uri (git-reference | |
510 | (url "https://github.com/verilator/verilator") | |
511 | (commit (string-append "v" version)))) | |
512 | (file-name (git-file-name name version)) | |
513 | (sha256 | |
1462a11d | 514 | (base32 "1lm2nyn7wzxj5y0ffwazhb4ygnmqf4d61sl937vmnmrpvdihsrrq")))) |
1a0907ab AM |
515 | (native-inputs |
516 | `(("autoconf" ,autoconf) | |
517 | ("automake" ,automake) | |
518 | ("bison" ,bison) | |
519 | ("flex" ,flex) | |
520 | ("gettext" ,gettext-minimal) | |
521 | ("python" ,python))) | |
522 | (inputs | |
523 | `(("perl" ,perl) | |
524 | ("systemc" ,systemc))) | |
525 | (build-system gnu-build-system) | |
526 | (arguments | |
527 | '(#:configure-flags | |
528 | (list (string-append "LDFLAGS=-L" | |
529 | (assoc-ref %build-inputs "systemc") | |
530 | "/lib-linux64")) | |
531 | #:make-flags | |
532 | (list (string-append "LDFLAGS=-L" | |
533 | (assoc-ref %build-inputs "systemc") | |
534 | "/lib-linux64")) | |
535 | #:phases | |
536 | (modify-phases %standard-phases | |
537 | (replace 'bootstrap | |
538 | (lambda _ (invoke "autoconf")))) | |
539 | #:test-target "test")) | |
540 | ;; #error "Something failed during ./configure as config_build.h is incomplete. | |
541 | ;; Perhaps you used autoreconf, don't." -- so we won't. ^^ | |
542 | (home-page "https://www.veripool.org/projects/verilator/") | |
543 | (synopsis "Fast Verilog/SystemVerilog simulator") | |
544 | (description | |
545 | "Verilator is invoked with parameters similar to GCC or Synopsys’s VCS. | |
546 | It ``Verilates'' the specified Verilog or SystemVerilog code by reading it, | |
547 | performing lint checks, and optionally inserting assertion checks and | |
548 | coverage-analysis points. It outputs single- or multi-threaded @file{.cpp} | |
549 | and @file{.h} files, the ``Verilated'' code. | |
550 | ||
551 | The user writes a little C++/SystemC wrapper file, which instantiates the | |
552 | Verilated model of the user’s top level module. These C++/SystemC files are | |
553 | then compiled by a C++ compiler (GCC/Clang/etc.). The resulting executable | |
554 | performs the design simulation. Verilator also supports linking its generated | |
555 | libraries, optionally encrypted, into other simulators.") | |
556 | (license license:lgpl3))) |