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[clinton/Smoothieware.git] / src / libs / LPC17xx / sLPC17xx.h
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df27a6a3
MM		 1/******************************************************************************
2 * @file: LPC17xx.h
3 * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
4 * NXP LPC17xx Device Series
5 * @version: V1.04
6 * @date: 2. July 2009
7 *----------------------------------------------------------------------------
8 *
9 * Copyright (C) 2008 ARM Limited. All rights reserved.
10 *
11 * ARM Limited (ARM) is supplying this software for use with Cortex-M3
12 * processor based microcontrollers. This file can be freely distributed
13 * within development tools that are supporting such ARM based processors.
14 *
15 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
16 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
18 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
19 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
20 *
21 ******************************************************************************/
22\r
23\r
24#ifndef __LPC17xx_H__
25#define __LPC17xx_H__
26\r
27/*
28 * ==========================================================================
29 * ---------- Interrupt Number Definition -----------------------------------
30 * ==========================================================================
31 */
32\r
33typedef enum IRQn
34{
35/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
36 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
37 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
38 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
39 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
40 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
41 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
42 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
43 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
44\r
45/****** LPC17xx Specific Interrupt Numbers *******************************************************/
46 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
47 TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
48 TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
49 TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
50 TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
51 UART0_IRQn = 5, /*!< UART0 Interrupt */
52 UART1_IRQn = 6, /*!< UART1 Interrupt */
53 UART2_IRQn = 7, /*!< UART2 Interrupt */
54 UART3_IRQn = 8, /*!< UART3 Interrupt */
55 PWM1_IRQn = 9, /*!< PWM1 Interrupt */
56 I2C0_IRQn = 10, /*!< I2C0 Interrupt */
57 I2C1_IRQn = 11, /*!< I2C1 Interrupt */
58 I2C2_IRQn = 12, /*!< I2C2 Interrupt */
59 SPI_IRQn = 13, /*!< SPI Interrupt */
60 SSP0_IRQn = 14, /*!< SSP0 Interrupt */
61 SSP1_IRQn = 15, /*!< SSP1 Interrupt */
62 PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
63 RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
64 EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
65 EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
66 EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
67 EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
68 ADC_IRQn = 22, /*!< A/D Converter Interrupt */
69 BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
70 USB_IRQn = 24, /*!< USB Interrupt */
71 CAN_IRQn = 25, /*!< CAN Interrupt */
72 DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
73 I2S_IRQn = 27, /*!< I2S Interrupt */
74 ENET_IRQn = 28, /*!< Ethernet Interrupt */
75 RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */
76 MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
77 QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
78 PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
79} IRQn_Type;
80\r
81\r
82/*
83 * ==========================================================================
84 * ----------- Processor and Core Peripheral Section ------------------------
85 * ==========================================================================
86 */
87\r
88/* Configuration of the Cortex-M3 Processor and Core Peripherals */
89#define __MPU_PRESENT 1 /*!< MPU present or not */
90#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
91#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
92\r
93\r
94#include "score_cm3.h" /* Cortex-M3 processor and core peripherals */
95//#include "system_LPC17xx.h" /* System Header */
96\r
97\r
98/******************************************************************************/
99/* Device Specific Peripheral registers structures */
100/******************************************************************************/
101\r
102#if defined ( __CC_ARM )
103#pragma anon_unions
104#endif
105\r
106/*------------- System Control (SC) ------------------------------------------*/
107typedef struct
108{
109 __IO uint32_t FLASHCFG; /* Flash Accelerator Module */
110 uint32_t RESERVED0[31];
111 __IO uint32_t PLL0CON; /* Clocking and Power Control */
112 __IO uint32_t PLL0CFG;
113 __I uint32_t PLL0STAT;
114 __O uint32_t PLL0FEED;
115 uint32_t RESERVED1[4];
116 __IO uint32_t PLL1CON;
117 __IO uint32_t PLL1CFG;
118 __I uint32_t PLL1STAT;
119 __O uint32_t PLL1FEED;
120 uint32_t RESERVED2[4];
121 __IO uint32_t PCON;
122 __IO uint32_t PCONP;
123 uint32_t RESERVED3[15];
124 __IO uint32_t CCLKCFG;
125 __IO uint32_t USBCLKCFG;
126 __IO uint32_t CLKSRCSEL;
127 uint32_t RESERVED4[12];
128 __IO uint32_t EXTINT; /* External Interrupts */
129 uint32_t RESERVED5;
130 __IO uint32_t EXTMODE;
131 __IO uint32_t EXTPOLAR;
132 uint32_t RESERVED6[12];
133 __IO uint32_t RSID; /* Reset */
134 uint32_t RESERVED7[7];
135 __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
136 __IO uint32_t IRCTRIM; /* Clock Dividers */
137 __IO uint32_t PCLKSEL0;
138 __IO uint32_t PCLKSEL1;
139 uint32_t RESERVED8[4];
140 __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
141 uint32_t RESERVED9;
142 __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
143 } LPC_SC_TypeDef;
144\r
145/*------------- Pin Connect Block (PINCON) -----------------------------------*/
146typedef struct
147{
148 __IO uint32_t PINSEL0;
149 __IO uint32_t PINSEL1;
150 __IO uint32_t PINSEL2;
151 __IO uint32_t PINSEL3;
152 __IO uint32_t PINSEL4;
153 __IO uint32_t PINSEL5;
154 __IO uint32_t PINSEL6;
155 __IO uint32_t PINSEL7;
156 __IO uint32_t PINSEL8;
157 __IO uint32_t PINSEL9;
158 __IO uint32_t PINSEL10;
159 uint32_t RESERVED0[5];
160 __IO uint32_t PINMODE0;
161 __IO uint32_t PINMODE1;
162 __IO uint32_t PINMODE2;
163 __IO uint32_t PINMODE3;
164 __IO uint32_t PINMODE4;
165 __IO uint32_t PINMODE5;
166 __IO uint32_t PINMODE6;
167 __IO uint32_t PINMODE7;
168 __IO uint32_t PINMODE8;
169 __IO uint32_t PINMODE9;
170 __IO uint32_t PINMODE_OD0;
171 __IO uint32_t PINMODE_OD1;
172 __IO uint32_t PINMODE_OD2;
173 __IO uint32_t PINMODE_OD3;
174 __IO uint32_t PINMODE_OD4;
175 __IO uint32_t I2CPADCFG;
176} LPC_PINCON_TypeDef;
177\r
178/*------------- General Purpose Input/Output (GPIO) --------------------------*/
179typedef struct
180{
181 __IO uint32_t FIODIR;
182 uint32_t RESERVED0[3];
183 __IO uint32_t FIOMASK;
184 __IO uint32_t FIOPIN;
185 __IO uint32_t FIOSET;
186 __O uint32_t FIOCLR;
187} LPC_GPIO_TypeDef;
188\r
189typedef struct
190{
191 __I uint32_t IntStatus;
192 __I uint32_t IO0IntStatR;
193 __I uint32_t IO0IntStatF;
194 __O uint32_t IO0IntClr;
195 __IO uint32_t IO0IntEnR;
196 __IO uint32_t IO0IntEnF;
197 uint32_t RESERVED0[3];
198 __I uint32_t IO2IntStatR;
199 __I uint32_t IO2IntStatF;
200 __O uint32_t IO2IntClr;
201 __IO uint32_t IO2IntEnR;
202 __IO uint32_t IO2IntEnF;
203} LPC_GPIOINT_TypeDef;
204\r
205/*------------- Timer (TIM) --------------------------------------------------*/
206typedef struct
207{
208 __IO uint32_t IR;
209 __IO uint32_t TCR;
210 __IO uint32_t TC;
211 __IO uint32_t PR;
212 __IO uint32_t PC;
213 __IO uint32_t MCR;
214 __IO uint32_t MR0;
215 __IO uint32_t MR1;
216 __IO uint32_t MR2;
217 __IO uint32_t MR3;
218 __IO uint32_t CCR;
219 __I uint32_t CR0;
220 __I uint32_t CR1;
221 uint32_t RESERVED0[2];
222 __IO uint32_t EMR;
223 uint32_t RESERVED1[12];
224 __IO uint32_t CTCR;
225} LPC_TIM_TypeDef;
226\r
227/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
228typedef struct
229{
230 __IO uint32_t IR;
231 __IO uint32_t TCR;
232 __IO uint32_t TC;
233 __IO uint32_t PR;
234 __IO uint32_t PC;
235 __IO uint32_t MCR;
236 __IO uint32_t MR0;
237 __IO uint32_t MR1;
238 __IO uint32_t MR2;
239 __IO uint32_t MR3;
240 __IO uint32_t CCR;
241 __I uint32_t CR0;
242 __I uint32_t CR1;
243 __I uint32_t CR2;
244 __I uint32_t CR3;
245 uint32_t RESERVED0;
246 __IO uint32_t MR4;
247 __IO uint32_t MR5;
248 __IO uint32_t MR6;
249 __IO uint32_t PCR;
250 __IO uint32_t LER;
251 uint32_t RESERVED1[7];
252 __IO uint32_t CTCR;
253} LPC_PWM_TypeDef;
254\r
255/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
256typedef struct
257{
258 union {
259 __I uint8_t RBR;
260 __O uint8_t THR;
261 __IO uint8_t DLL;
262 uint32_t RESERVED0;
263 };
264 union {
265 __IO uint8_t DLM;
266 __IO uint32_t IER;
267 };
268 union {
269 __I uint32_t IIR;
270 __O uint8_t FCR;
271 };
272 __IO uint8_t LCR;
273 uint8_t RESERVED1[7];
274 __I uint8_t LSR;
275 uint8_t RESERVED2[7];
276 __IO uint8_t SCR;
277 uint8_t RESERVED3[3];
278 __IO uint32_t ACR;
279 __IO uint8_t ICR;
280 uint8_t RESERVED4[3];
281 __IO uint8_t FDR;
282 uint8_t RESERVED5[7];
283 __IO uint8_t TER;
284 uint8_t RESERVED6[39];
285 __I uint8_t FIFOLVL;
286} LPC_UART_TypeDef;
287\r
288typedef struct
289{
290 union {
291 __I uint8_t RBR;
292 __O uint8_t THR;
293 __IO uint8_t DLL;
294 uint32_t RESERVED0;
295 };
296 union {
297 __IO uint8_t DLM;
298 __IO uint32_t IER;
299 };
300 union {
301 __I uint32_t IIR;
302 __O uint8_t FCR;
303 };
304 __IO uint8_t LCR;
305 uint8_t RESERVED1[7];
306 __I uint8_t LSR;
307 uint8_t RESERVED2[7];
308 __IO uint8_t SCR;
309 uint8_t RESERVED3[3];
310 __IO uint32_t ACR;
311 __IO uint8_t ICR;
312 uint8_t RESERVED4[3];
313 __IO uint8_t FDR;
314 uint8_t RESERVED5[7];
315 __IO uint8_t TER;
316 uint8_t RESERVED6[39];
317 __I uint8_t FIFOLVL;
318 uint8_t RESERVED7[363];
319 __IO uint32_t DMAREQSEL;
320} LPC_UART0_TypeDef;
321\r
322typedef struct
323{
324 union {
325 __I uint8_t RBR;
326 __O uint8_t THR;
327 __IO uint8_t DLL;
328 uint32_t RESERVED0;
329 };
330 union {
331 __IO uint8_t DLM;
332 __IO uint32_t IER;
333 };
334 union {
335 __I uint32_t IIR;
336 __O uint8_t FCR;
337 };
338 __IO uint8_t LCR;
339 uint8_t RESERVED1[3];
340 __IO uint8_t MCR;
341 uint8_t RESERVED2[3];
342 __I uint8_t LSR;
343 uint8_t RESERVED3[3];
344 __I uint8_t MSR;
345 uint8_t RESERVED4[3];
346 __IO uint8_t SCR;
347 uint8_t RESERVED5[3];
348 __IO uint32_t ACR;
349 uint32_t RESERVED6;
350 __IO uint32_t FDR;
351 uint32_t RESERVED7;
352 __IO uint8_t TER;
353 uint8_t RESERVED8[27];
354 __IO uint8_t RS485CTRL;
355 uint8_t RESERVED9[3];
356 __IO uint8_t ADRMATCH;
357 uint8_t RESERVED10[3];
358 __IO uint8_t RS485DLY;
359 uint8_t RESERVED11[3];
360 __I uint8_t FIFOLVL;
361} LPC_UART1_TypeDef;
362\r
363/*------------- Serial Peripheral Interface (SPI) ----------------------------*/
364typedef struct
365{
366 __IO uint32_t SPCR;
367 __I uint32_t SPSR;
368 __IO uint32_t SPDR;
369 __IO uint32_t SPCCR;
370 uint32_t RESERVED0[3];
371 __IO uint32_t SPINT;
372} LPC_SPI_TypeDef;
373\r
374/*------------- Synchronous Serial Communication (SSP) -----------------------*/
375typedef struct
376{
377 __IO uint32_t CR0;
378 __IO uint32_t CR1;
379 __IO uint32_t DR;
380 __I uint32_t SR;
381 __IO uint32_t CPSR;
382 __IO uint32_t IMSC;
383 __IO uint32_t RIS;
384 __IO uint32_t MIS;
385 __IO uint32_t ICR;
386 __IO uint32_t DMACR;
387} LPC_SSP_TypeDef;
388\r
389/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
390typedef struct
391{
392 __IO uint32_t I2CONSET;
393 __I uint32_t I2STAT;
394 __IO uint32_t I2DAT;
395 __IO uint32_t I2ADR0;
396 __IO uint32_t I2SCLH;
397 __IO uint32_t I2SCLL;
398 __O uint32_t I2CONCLR;
399 __IO uint32_t MMCTRL;
400 __IO uint32_t I2ADR1;
401 __IO uint32_t I2ADR2;
402 __IO uint32_t I2ADR3;
403 __I uint32_t I2DATA_BUFFER;
404 __IO uint32_t I2MASK0;
405 __IO uint32_t I2MASK1;
406 __IO uint32_t I2MASK2;
407 __IO uint32_t I2MASK3;
408} LPC_I2C_TypeDef;
409\r
410/*------------- Inter IC Sound (I2S) -----------------------------------------*/
411typedef struct
412{
413 __IO uint32_t I2SDAO;
414 __IO uint32_t I2SDAI;
415 __O uint32_t I2STXFIFO;
416 __I uint32_t I2SRXFIFO;
417 __I uint32_t I2SSTATE;
418 __IO uint32_t I2SDMA1;
419 __IO uint32_t I2SDMA2;
420 __IO uint32_t I2SIRQ;
421 __IO uint32_t I2STXRATE;
422 __IO uint32_t I2SRXRATE;
423 __IO uint32_t I2STXBITRATE;
424 __IO uint32_t I2SRXBITRATE;
425 __IO uint32_t I2STXMODE;
426 __IO uint32_t I2SRXMODE;
427} LPC_I2S_TypeDef;
428\r
429/*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
430typedef struct
431{
432 __IO uint32_t RICOMPVAL;
433 __IO uint32_t RIMASK;
434 __IO uint8_t RICTRL;
435 uint8_t RESERVED0[3];
436 __IO uint32_t RICOUNTER;
437} LPC_RIT_TypeDef;
438\r
439/*------------- Real-Time Clock (RTC) ----------------------------------------*/
440typedef struct
441{
442 __IO uint8_t ILR;
443 uint8_t RESERVED0[7];
444 __IO uint8_t CCR;
445 uint8_t RESERVED1[3];
446 __IO uint8_t CIIR;
447 uint8_t RESERVED2[3];
448 __IO uint8_t AMR;
449 uint8_t RESERVED3[3];
450 __I uint32_t CTIME0;
451 __I uint32_t CTIME1;
452 __I uint32_t CTIME2;
453 __IO uint8_t SEC;
454 uint8_t RESERVED4[3];
455 __IO uint8_t MIN;
456 uint8_t RESERVED5[3];
457 __IO uint8_t HOUR;
458 uint8_t RESERVED6[3];
459 __IO uint8_t DOM;
460 uint8_t RESERVED7[3];
461 __IO uint8_t DOW;
462 uint8_t RESERVED8[3];
463 __IO uint16_t DOY;
464 uint16_t RESERVED9;
465 __IO uint8_t MONTH;
466 uint8_t RESERVED10[3];
467 __IO uint16_t YEAR;
468 uint16_t RESERVED11;
469 __IO uint32_t CALIBRATION;
470 __IO uint32_t GPREG0;
471 __IO uint32_t GPREG1;
472 __IO uint32_t GPREG2;
473 __IO uint32_t GPREG3;
474 __IO uint32_t GPREG4;
475 __IO uint8_t RTC_AUXEN;
476 uint8_t RESERVED12[3];
477 __IO uint8_t RTC_AUX;
478 uint8_t RESERVED13[3];
479 __IO uint8_t ALSEC;
480 uint8_t RESERVED14[3];
481 __IO uint8_t ALMIN;
482 uint8_t RESERVED15[3];
483 __IO uint8_t ALHOUR;
484 uint8_t RESERVED16[3];
485 __IO uint8_t ALDOM;
486 uint8_t RESERVED17[3];
487 __IO uint8_t ALDOW;
488 uint8_t RESERVED18[3];
489 __IO uint16_t ALDOY;
490 uint16_t RESERVED19;
491 __IO uint8_t ALMON;
492 uint8_t RESERVED20[3];
493 __IO uint16_t ALYEAR;
494 uint16_t RESERVED21;
495} LPC_RTC_TypeDef;
496\r
497/*------------- Watchdog Timer (WDT) -----------------------------------------*/
498typedef struct
499{
500 __IO uint8_t WDMOD;
501 uint8_t RESERVED0[3];
502 __IO uint32_t WDTC;
503 __O uint8_t WDFEED;
504 uint8_t RESERVED1[3];
505 __I uint32_t WDTV;
506 __IO uint32_t WDCLKSEL;
507} LPC_WDT_TypeDef;
508\r
509/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
510typedef struct
511{
512 __IO uint32_t ADCR;
513 __IO uint32_t ADGDR;
514 uint32_t RESERVED0;
515 __IO uint32_t ADINTEN;
516 __I uint32_t ADDR0;
517 __I uint32_t ADDR1;
518 __I uint32_t ADDR2;
519 __I uint32_t ADDR3;
520 __I uint32_t ADDR4;
521 __I uint32_t ADDR5;
522 __I uint32_t ADDR6;
523 __I uint32_t ADDR7;
524 __I uint32_t ADSTAT;
525 __IO uint32_t ADTRM;
526} LPC_ADC_TypeDef;
527\r
528/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
529typedef struct
530{
531 __IO uint32_t DACR;
532 __IO uint32_t DACCTRL;
533 __IO uint16_t DACCNTVAL;
534} LPC_DAC_TypeDef;
535\r
536/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
537typedef struct
538{
539 __I uint32_t MCCON;
540 __O uint32_t MCCON_SET;
541 __O uint32_t MCCON_CLR;
542 __I uint32_t MCCAPCON;
543 __O uint32_t MCCAPCON_SET;
544 __O uint32_t MCCAPCON_CLR;
545 __IO uint32_t MCTIM0;
546 __IO uint32_t MCTIM1;
547 __IO uint32_t MCTIM2;
548 __IO uint32_t MCPER0;
549 __IO uint32_t MCPER1;
550 __IO uint32_t MCPER2;
551 __IO uint32_t MCPW0;
552 __IO uint32_t MCPW1;
553 __IO uint32_t MCPW2;
554 __IO uint32_t MCDEADTIME;
555 __IO uint32_t MCCCP;
556 __IO uint32_t MCCR0;
557 __IO uint32_t MCCR1;
558 __IO uint32_t MCCR2;
559 __I uint32_t MCINTEN;
560 __O uint32_t MCINTEN_SET;
561 __O uint32_t MCINTEN_CLR;
562 __I uint32_t MCCNTCON;
563 __O uint32_t MCCNTCON_SET;
564 __O uint32_t MCCNTCON_CLR;
565 __I uint32_t MCINTFLAG;
566 __O uint32_t MCINTFLAG_SET;
567 __O uint32_t MCINTFLAG_CLR;
568 __O uint32_t MCCAP_CLR;
569} LPC_MCPWM_TypeDef;
570\r
571/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
572typedef struct
573{
574 __O uint32_t QEICON;
575 __I uint32_t QEISTAT;
576 __IO uint32_t QEICONF;
577 __I uint32_t QEIPOS;
578 __IO uint32_t QEIMAXPOS;
579 __IO uint32_t CMPOS0;
580 __IO uint32_t CMPOS1;
581 __IO uint32_t CMPOS2;
582 __I uint32_t INXCNT;
583 __IO uint32_t INXCMP;
584 __IO uint32_t QEILOAD;
585 __I uint32_t QEITIME;
586 __I uint32_t QEIVEL;
587 __I uint32_t QEICAP;
588 __IO uint32_t VELCOMP;
589 __IO uint32_t FILTER;
590 uint32_t RESERVED0[998];
591 __O uint32_t QEIIEC;
592 __O uint32_t QEIIES;
593 __I uint32_t QEIINTSTAT;
594 __I uint32_t QEIIE;
595 __O uint32_t QEICLR;
596 __O uint32_t QEISET;
597} LPC_QEI_TypeDef;
598\r
599/*------------- Controller Area Network (CAN) --------------------------------*/
600typedef struct
601{
602 __IO uint32_t mask[512]; /* ID Masks */
603} LPC_CANAF_RAM_TypeDef;
604\r
605typedef struct /* Acceptance Filter Registers */
606{
607 __IO uint32_t AFMR;
608 __IO uint32_t SFF_sa;
609 __IO uint32_t SFF_GRP_sa;
610 __IO uint32_t EFF_sa;
611 __IO uint32_t EFF_GRP_sa;
612 __IO uint32_t ENDofTable;
613 __I uint32_t LUTerrAd;
614 __I uint32_t LUTerr;
615 __IO uint32_t FCANIE;
616 __IO uint32_t FCANIC0;
617 __IO uint32_t FCANIC1;
618} LPC_CANAF_TypeDef;
619\r
620typedef struct /* Central Registers */
621{
622 __I uint32_t CANTxSR;
623 __I uint32_t CANRxSR;
624 __I uint32_t CANMSR;
625} LPC_CANCR_TypeDef;
626\r
627typedef struct /* Controller Registers */
628{
629 __IO uint32_t MOD;
630 __O uint32_t CMR;
631 __IO uint32_t GSR;
632 __I uint32_t ICR;
633 __IO uint32_t IER;
634 __IO uint32_t BTR;
635 __IO uint32_t EWL;
636 __I uint32_t SR;
637 __IO uint32_t RFS;
638 __IO uint32_t RID;
639 __IO uint32_t RDA;
640 __IO uint32_t RDB;
641 __IO uint32_t TFI1;
642 __IO uint32_t TID1;
643 __IO uint32_t TDA1;
644 __IO uint32_t TDB1;
645 __IO uint32_t TFI2;
646 __IO uint32_t TID2;
647 __IO uint32_t TDA2;
648 __IO uint32_t TDB2;
649 __IO uint32_t TFI3;
650 __IO uint32_t TID3;
651 __IO uint32_t TDA3;
652 __IO uint32_t TDB3;
653} LPC_CAN_TypeDef;
654\r
655/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
656typedef struct /* Common Registers */
657{
658 __I uint32_t DMACIntStat;
659 __I uint32_t DMACIntTCStat;
660 __O uint32_t DMACIntTCClear;
661 __I uint32_t DMACIntErrStat;
662 __O uint32_t DMACIntErrClr;
663 __I uint32_t DMACRawIntTCStat;
664 __I uint32_t DMACRawIntErrStat;
665 __I uint32_t DMACEnbldChns;
666 __IO uint32_t DMACSoftBReq;
667 __IO uint32_t DMACSoftSReq;
668 __IO uint32_t DMACSoftLBReq;
669 __IO uint32_t DMACSoftLSReq;
670 __IO uint32_t DMACConfig;
671 __IO uint32_t DMACSync;
672} LPC_GPDMA_TypeDef;
673\r
674typedef struct /* Channel Registers */
675{
676 __IO uint32_t DMACCSrcAddr;
677 __IO uint32_t DMACCDestAddr;
678 __IO uint32_t DMACCLLI;
679 __IO uint32_t DMACCControl;
680 __IO uint32_t DMACCConfig;
681} LPC_GPDMACH_TypeDef;
682\r
683/*------------- Universal Serial Bus (USB) -----------------------------------*/
684typedef struct
685{
686 __I uint32_t HcRevision; /* USB Host Registers */
687 __IO uint32_t HcControl;
688 __IO uint32_t HcCommandStatus;
689 __IO uint32_t HcInterruptStatus;
690 __IO uint32_t HcInterruptEnable;
691 __IO uint32_t HcInterruptDisable;
692 __IO uint32_t HcHCCA;
693 __I uint32_t HcPeriodCurrentED;
694 __IO uint32_t HcControlHeadED;
695 __IO uint32_t HcControlCurrentED;
696 __IO uint32_t HcBulkHeadED;
697 __IO uint32_t HcBulkCurrentED;
698 __I uint32_t HcDoneHead;
699 __IO uint32_t HcFmInterval;
700 __I uint32_t HcFmRemaining;
701 __I uint32_t HcFmNumber;
702 __IO uint32_t HcPeriodicStart;
703 __IO uint32_t HcLSTreshold;
704 __IO uint32_t HcRhDescriptorA;
705 __IO uint32_t HcRhDescriptorB;
706 __IO uint32_t HcRhStatus;
707 __IO uint32_t HcRhPortStatus1;
708 __IO uint32_t HcRhPortStatus2;
709 uint32_t RESERVED0[40];
710 __I uint32_t Module_ID;
711\r
712 __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
713 __IO uint32_t OTGIntEn;
714 __O uint32_t OTGIntSet;
715 __O uint32_t OTGIntClr;
716 __IO uint32_t OTGStCtrl;
717 __IO uint32_t OTGTmr;
718 uint32_t RESERVED1[58];
719\r
720 __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
721 __IO uint32_t USBDevIntEn;
722 __O uint32_t USBDevIntClr;
723 __O uint32_t USBDevIntSet;
724\r
725 __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
726 __I uint32_t USBCmdData;
727\r
728 __I uint32_t USBRxData; /* USB Device Transfer Registers */
729 __O uint32_t USBTxData;
730 __I uint32_t USBRxPLen;
731 __O uint32_t USBTxPLen;
732 __IO uint32_t USBCtrl;
733 __O uint32_t USBDevIntPri;
734\r
735 __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
736 __IO uint32_t USBEpIntEn;
737 __O uint32_t USBEpIntClr;
738 __O uint32_t USBEpIntSet;
739 __O uint32_t USBEpIntPri;
740\r
741 __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
742 __O uint32_t USBEpInd;
743 __IO uint32_t USBMaxPSize;
744\r
745 __I uint32_t USBDMARSt; /* USB Device DMA Registers */
746 __O uint32_t USBDMARClr;
747 __O uint32_t USBDMARSet;
748 uint32_t RESERVED2[9];
749 __IO uint32_t USBUDCAH;
750 __I uint32_t USBEpDMASt;
751 __O uint32_t USBEpDMAEn;
752 __O uint32_t USBEpDMADis;
753 __I uint32_t USBDMAIntSt;
754 __IO uint32_t USBDMAIntEn;
755 uint32_t RESERVED3[2];
756 __I uint32_t USBEoTIntSt;
757 __O uint32_t USBEoTIntClr;
758 __O uint32_t USBEoTIntSet;
759 __I uint32_t USBNDDRIntSt;
760 __O uint32_t USBNDDRIntClr;
761 __O uint32_t USBNDDRIntSet;
762 __I uint32_t USBSysErrIntSt;
763 __O uint32_t USBSysErrIntClr;
764 __O uint32_t USBSysErrIntSet;
765 uint32_t RESERVED4[15];
766\r
767 __I uint32_t I2C_RX; /* USB OTG I2C Registers */
768 __O uint32_t I2C_WO;
769 __I uint32_t I2C_STS;
770 __IO uint32_t I2C_CTL;
771 __IO uint32_t I2C_CLKHI;
772 __O uint32_t I2C_CLKLO;
773 uint32_t RESERVED5[823];
774\r
775 union {
776 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
777 __IO uint32_t OTGClkCtrl;
778 };
779 union {
780 __I uint32_t USBClkSt;
781 __I uint32_t OTGClkSt;
782 };
783} LPC_USB_TypeDef;
784\r
785/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
786typedef struct
787{
788 __IO uint32_t MAC1; /* MAC Registers */
789 __IO uint32_t MAC2;
790 __IO uint32_t IPGT;
791 __IO uint32_t IPGR;
792 __IO uint32_t CLRT;
793 __IO uint32_t MAXF;
794 __IO uint32_t SUPP;
795 __IO uint32_t TEST;
796 __IO uint32_t MCFG;
797 __IO uint32_t MCMD;
798 __IO uint32_t MADR;
799 __O uint32_t MWTD;
800 __I uint32_t MRDD;
801 __I uint32_t MIND;
802 uint32_t RESERVED0[2];
803 __IO uint32_t SA0;
804 __IO uint32_t SA1;
805 __IO uint32_t SA2;
806 uint32_t RESERVED1[45];
807 __IO uint32_t Command; /* Control Registers */
808 __I uint32_t Status;
809 __IO uint32_t RxDescriptor;
810 __IO uint32_t RxStatus;
811 __IO uint32_t RxDescriptorNumber;
812 __I uint32_t RxProduceIndex;
813 __IO uint32_t RxConsumeIndex;
814 __IO uint32_t TxDescriptor;
815 __IO uint32_t TxStatus;
816 __IO uint32_t TxDescriptorNumber;
817 __IO uint32_t TxProduceIndex;
818 __I uint32_t TxConsumeIndex;
819 uint32_t RESERVED2[10];
820 __I uint32_t TSV0;
821 __I uint32_t TSV1;
822 __I uint32_t RSV;
823 uint32_t RESERVED3[3];
824 __IO uint32_t FlowControlCounter;
825 __I uint32_t FlowControlStatus;
826 uint32_t RESERVED4[34];
827 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
828 __IO uint32_t RxFilterWoLStatus;
829 __IO uint32_t RxFilterWoLClear;
830 uint32_t RESERVED5;
831 __IO uint32_t HashFilterL;
832 __IO uint32_t HashFilterH;
833 uint32_t RESERVED6[882];
834 __I uint32_t IntStatus; /* Module Control Registers */
835 __IO uint32_t IntEnable;
836 __O uint32_t IntClear;
837 __O uint32_t IntSet;
838 uint32_t RESERVED7;
839 __IO uint32_t PowerDown;
840 uint32_t RESERVED8;
841 __IO uint32_t Module_ID;
842} LPC_EMAC_TypeDef;
843\r
844#if defined ( __CC_ARM )
845#pragma anon_unions
846#endif
847\r
848\r
849/******************************************************************************/
850/* Peripheral memory map */
851/******************************************************************************/
852/* Base addresses */
853#define LPC_FLASH_BASE (0x00000000UL)
854#define LPC_RAM_BASE (0x10000000UL)
855#define LPC_GPIO_BASE (0x2009C000UL)
856#define LPC_APB0_BASE (0x40000000UL)
857#define LPC_APB1_BASE (0x40080000UL)
858#define LPC_AHB_BASE (0x50000000UL)
859#define LPC_CM3_BASE (0xE0000000UL)
860\r
861/* APB0 peripherals */
862#define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
863#define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
864#define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
865#define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
866#define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
867#define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
868#define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
869#define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000)
870#define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
871#define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
872#define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000)
873#define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
874#define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
875#define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
876#define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
877#define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
878#define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
879#define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
880#define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
881\r
882/* APB1 peripherals */
883#define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
884#define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
885#define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
886#define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
887#define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
888#define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
889#define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
890#define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
891#define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000)
892#define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
893#define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
894#define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
895\r
896/* AHB peripherals */
897#define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000)
898#define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000)
899#define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100)
900#define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120)
901#define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140)
902#define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160)
903#define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180)
904#define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0)
905#define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0)
906#define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0)
907#define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
908\r
909/* GPIOs */
910#define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000)
911#define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020)
912#define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040)
913#define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060)
914#define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080)
915\r
916\r
917/******************************************************************************/
918/* Peripheral declaration */
919/******************************************************************************/
920#define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
921#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
922#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
923#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
924#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
925#define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
926#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
927#define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
928#define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
929#define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
930#define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
931#define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE )
932#define LPC_UART0 ((LPC_UART0_TypeDef *) LPC_UART0_BASE )
933#define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
934#define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
935#define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
936#define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
937#define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
938#define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
939#define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
940#define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
941#define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE )
942#define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
943#define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
944#define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE )
945#define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
946#define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
947#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
948#define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
949#define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
950#define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
951#define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
952#define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
953#define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
954#define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
955#define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
956#define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
957#define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
958#define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
959#define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
960#define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
961#define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
962#define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
963#define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
964#define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
965#define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
966#define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
967\r
968#endif // __LPC17xx_H__
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