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remove CONS macro in VM; use scm_cons instead
[bpt/guile.git] / libguile / vm-i-scheme.c
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776491ca 1/* Copyright (C) 2001, 2009, 2010, 2011, 2012, 2013 Free Software Foundation, Inc.
a98cef7e 2 *
560b9c25 3 * This library is free software; you can redistribute it and/or
53befeb7
NJ		 4 * modify it under the terms of the GNU Lesser General Public License
5 * as published by the Free Software Foundation; either version 3 of
6 * the License, or (at your option) any later version.
a98cef7e 7 *
53befeb7
NJ		 8 * This library is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
560b9c25
AW		 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * Lesser General Public License for more details.
a98cef7e 12 *
560b9c25
AW		 13 * You should have received a copy of the GNU Lesser General Public
14 * License along with this library; if not, write to the Free Software
53befeb7
NJ		 15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
16 * 02110-1301 USA
560b9c25 17 */
a98cef7e
KN		 18
19/* This file is included in vm_engine.c */
20
a80be762
KN		 21\f
22/*
23 * Predicates
24 */
25
93d197be 26#define ARGS1(a1) SCM a1 = sp[0];
11ea1aba
AW		 27#define ARGS2(a1,a2) SCM a1 = sp[-1], a2 = sp[0]; sp--; NULLSTACK (1);
28#define ARGS3(a1,a2,a3) SCM a1 = sp[-2], a2 = sp[-1], a3 = sp[0]; sp -= 2; NULLSTACK (2);
93d197be
AW		 29
30#define RETURN(x) do { *sp = x; NEXT; } while (0)
31
827dc8dc 32VM_DEFINE_FUNCTION (128, not, "not", 1)
a98cef7e 33{
a80be762 34 ARGS1 (x);
2533f10b 35 RETURN (scm_from_bool (scm_is_false (x)));
17e90c5e
KN		 36}
37
827dc8dc 38VM_DEFINE_FUNCTION (129, not_not, "not-not", 1)
17e90c5e 39{
a80be762 40 ARGS1 (x);
2533f10b 41 RETURN (scm_from_bool (!scm_is_false (x)));
17e90c5e
KN		 42}
43
827dc8dc 44VM_DEFINE_FUNCTION (130, eq, "eq?", 2)
17e90c5e 45{
a80be762 46 ARGS2 (x, y);
5c8cefe5 47 RETURN (scm_from_bool (scm_is_eq (x, y)));
17e90c5e
KN		 48}
49
827dc8dc 50VM_DEFINE_FUNCTION (131, not_eq, "not-eq?", 2)
17e90c5e 51{
a80be762 52 ARGS2 (x, y);
5c8cefe5 53 RETURN (scm_from_bool (!scm_is_eq (x, y)));
17e90c5e
KN		 54}
55
827dc8dc 56VM_DEFINE_FUNCTION (132, nullp, "null?", 1)
17e90c5e 57{
a80be762 58 ARGS1 (x);
2533f10b 59 RETURN (scm_from_bool (scm_is_null (x)));
a98cef7e
KN		 60}
61
827dc8dc 62VM_DEFINE_FUNCTION (133, not_nullp, "not-null?", 1)
a98cef7e 63{
a80be762 64 ARGS1 (x);
2533f10b 65 RETURN (scm_from_bool (!scm_is_null (x)));
a80be762
KN		 66}
67
9348168e
BT		 68VM_DEFINE_FUNCTION (134, nilp, "nil?", 1)
69{
70 ARGS1 (x);
71 RETURN (scm_from_bool (scm_is_lisp_false (x)));
72}
73
74VM_DEFINE_FUNCTION (135, not_nilp, "not-nil?", 1)
75{
76 ARGS1 (x);
77 RETURN (scm_from_bool (!scm_is_lisp_false (x)));
78}
79
80VM_DEFINE_FUNCTION (136, eqv, "eqv?", 2)
a80be762
KN		 81{
82 ARGS2 (x, y);
5c8cefe5 83 if (scm_is_eq (x, y))
a80be762
KN		 84 RETURN (SCM_BOOL_T);
85 if (SCM_IMP (x) || SCM_IMP (y))
86 RETURN (SCM_BOOL_F);
1865ad56 87 SYNC_REGISTER ();
a80be762
KN		 88 RETURN (scm_eqv_p (x, y));
89}
90
9348168e 91VM_DEFINE_FUNCTION (137, equal, "equal?", 2)
a80be762
KN		 92{
93 ARGS2 (x, y);
5c8cefe5 94 if (scm_is_eq (x, y))
a80be762
KN		 95 RETURN (SCM_BOOL_T);
96 if (SCM_IMP (x) || SCM_IMP (y))
97 RETURN (SCM_BOOL_F);
1865ad56 98 SYNC_REGISTER ();
a80be762 99 RETURN (scm_equal_p (x, y));
a98cef7e
KN		 100}
101
9348168e 102VM_DEFINE_FUNCTION (138, pairp, "pair?", 1)
a98cef7e 103{
a80be762 104 ARGS1 (x);
5c8cefe5 105 RETURN (scm_from_bool (scm_is_pair (x)));
a98cef7e
KN		 106}
107
9348168e 108VM_DEFINE_FUNCTION (139, listp, "list?", 1)
a98cef7e 109{
a80be762 110 ARGS1 (x);
9bd48cb1 111 RETURN (scm_from_bool (scm_ilength (x) >= 0));
a98cef7e
KN		 112}
113
9348168e 114VM_DEFINE_FUNCTION (140, symbolp, "symbol?", 1)
cf45ff03
AW		 115{
116 ARGS1 (x);
117 RETURN (scm_from_bool (scm_is_symbol (x)));
118}
119
9348168e 120VM_DEFINE_FUNCTION (141, vectorp, "vector?", 1)
cf45ff03
AW		 121{
122 ARGS1 (x);
123 RETURN (scm_from_bool (SCM_I_IS_VECTOR (x)));
124}
125
a80be762
KN		 126\f
127/*
128 * Basic data
129 */
130
9348168e 131VM_DEFINE_FUNCTION (142, cons, "cons", 2)
a98cef7e 132{
a80be762 133 ARGS2 (x, y);
52182d52
AW		 134 SYNC_BEFORE_GC ();
135 x = scm_cons (x, y);
a80be762 136 RETURN (x);
a98cef7e
KN		 137}
138
41e49280 139#define VM_VALIDATE_CONS(x, proc) \
53bdfcf0 140 VM_ASSERT (scm_is_pair (x), vm_error_not_a_pair (proc, x))
5e390de6 141
9348168e 142VM_DEFINE_FUNCTION (143, car, "car", 1)
a98cef7e 143{
a80be762 144 ARGS1 (x);
41e49280 145 VM_VALIDATE_CONS (x, "car");
a80be762 146 RETURN (SCM_CAR (x));
a98cef7e
KN		 147}
148
9348168e 149VM_DEFINE_FUNCTION (144, cdr, "cdr", 1)
a98cef7e 150{
a80be762 151 ARGS1 (x);
41e49280 152 VM_VALIDATE_CONS (x, "cdr");
a80be762 153 RETURN (SCM_CDR (x));
a98cef7e
KN		 154}
155
9348168e 156VM_DEFINE_INSTRUCTION (145, set_car, "set-car!", 0, 2, 0)
a98cef7e 157{
60ed31d2 158 SCM x, y;
eae2438d 159 POP2 (y, x);
41e49280 160 VM_VALIDATE_CONS (x, "set-car!");
a80be762 161 SCM_SETCAR (x, y);
60ed31d2 162 NEXT;
a98cef7e
KN		 163}
164
9348168e 165VM_DEFINE_INSTRUCTION (146, set_cdr, "set-cdr!", 0, 2, 0)
a98cef7e 166{
60ed31d2 167 SCM x, y;
eae2438d 168 POP2 (y, x);
41e49280 169 VM_VALIDATE_CONS (x, "set-cdr!");
a80be762 170 SCM_SETCDR (x, y);
60ed31d2 171 NEXT;
a98cef7e
KN		 172}
173
a80be762
KN		 174\f
175/*
176 * Numeric relational tests
177 */
178
179#undef REL
b2b33168
AW		 180#define REL(crel,srel) \
181 { \
182 ARGS2 (x, y); \
183 if (SCM_I_INUMP (x) && SCM_I_INUMP (y)) \
184 RETURN (scm_from_bool (((scm_t_signed_bits) SCM_UNPACK (x)) \
185 crel ((scm_t_signed_bits) SCM_UNPACK (y)))); \
186 SYNC_REGISTER (); \
187 RETURN (srel (x, y)); \
188 }
a80be762 189
9348168e 190VM_DEFINE_FUNCTION (147, ee, "ee?", 2)
a80be762
KN		 191{
192 REL (==, scm_num_eq_p);
193}
194
9348168e 195VM_DEFINE_FUNCTION (148, lt, "lt?", 2)
a80be762
KN		 196{
197 REL (<, scm_less_p);
198}
199
9348168e 200VM_DEFINE_FUNCTION (149, le, "le?", 2)
a80be762
KN		 201{
202 REL (<=, scm_leq_p);
203}
204
9348168e 205VM_DEFINE_FUNCTION (150, gt, "gt?", 2)
a80be762
KN		 206{
207 REL (>, scm_gr_p);
208}
209
9348168e 210VM_DEFINE_FUNCTION (151, ge, "ge?", 2)
a80be762
KN		 211{
212 REL (>=, scm_geq_p);
213}
214
215\f
216/*
217 * Numeric functions
218 */
219
e78d4bf9 220/* The maximum/minimum tagged integers. */
0c57673a
LC		 221#undef INUM_MAX
222#undef INUM_MIN
e78d4bf9
LC		 223#define INUM_MAX (INTPTR_MAX - 1)
224#define INUM_MIN (INTPTR_MIN + scm_tc2_int)
225
a80be762
KN		 226#undef FUNC2
227#define FUNC2(CFUNC,SFUNC) \
228{ \
d8eeb67c 229 ARGS2 (x, y); \
2d80426a 230 if (SCM_I_INUMP (x) && SCM_I_INUMP (y)) \
a80be762 231 { \
c0ee3245 232 scm_t_int64 n = SCM_I_INUM (x) CFUNC SCM_I_INUM (y);\
a80be762 233 if (SCM_FIXABLE (n)) \
2d80426a 234 RETURN (SCM_I_MAKINUM (n)); \
a80be762 235 } \
b2642276 236 SYNC_REGISTER (); \
a80be762
KN		 237 RETURN (SFUNC (x, y)); \
238}
239
0c57673a
LC		 240/* Assembly tagged integer arithmetic routines. This code uses the
241 `asm goto' feature introduced in GCC 4.5. */
242
243#if defined __x86_64__ && SCM_GNUC_PREREQ (4, 5)
244
245/* The macros below check the CPU's overflow flag to improve fixnum
246 arithmetic. The %rcx register is explicitly clobbered because `asm
247 goto' can't have outputs, in which case the `r' constraint could be
248 used to let the register allocator choose a register.
249
250 TODO: Use `cold' label attribute in GCC 4.6.
251 http://gcc.gnu.org/ml/gcc-patches/2010-10/msg01777.html */
252
253# define ASM_ADD(x, y) \
254 { \
255 asm volatile goto ("mov %1, %%rcx; " \
256 "test %[tag], %%cl; je %l[slow_add]; " \
257 "test %[tag], %0; je %l[slow_add]; " \
258 "add %0, %%rcx; jo %l[slow_add]; " \
259 "sub %[tag], %%rcx; " \
260 "mov %%rcx, (%[vsp])\n" \
261 : /* no outputs */ \
262 : "r" (x), "r" (y), \
263 [vsp] "r" (sp), [tag] "i" (scm_tc2_int) \
264 : "rcx", "memory" \
265 : slow_add); \
266 NEXT; \
267 } \
268 slow_add: \
269 do { } while (0)
270
271# define ASM_SUB(x, y) \
272 { \
273 asm volatile goto ("mov %0, %%rcx; " \
274 "test %[tag], %%cl; je %l[slow_sub]; " \
275 "test %[tag], %1; je %l[slow_sub]; " \
276 "sub %1, %%rcx; jo %l[slow_sub]; " \
277 "add %[tag], %%rcx; " \
278 "mov %%rcx, (%[vsp])\n" \
279 : /* no outputs */ \
280 : "r" (x), "r" (y), \
281 [vsp] "r" (sp), [tag] "i" (scm_tc2_int) \
282 : "rcx", "memory" \
283 : slow_sub); \
284 NEXT; \
285 } \
286 slow_sub: \
287 do { } while (0)
288
289#endif
290
291
9348168e 292VM_DEFINE_FUNCTION (152, add, "add", 2)
a80be762 293{
0c57673a 294#ifndef ASM_ADD
a80be762 295 FUNC2 (+, scm_sum);
0c57673a
LC		 296#else
297 ARGS2 (x, y);
298 ASM_ADD (x, y);
299 SYNC_REGISTER ();
300 RETURN (scm_sum (x, y));
301#endif
a80be762
KN		 302}
303
9348168e 304VM_DEFINE_FUNCTION (153, add1, "add1", 1)
7382f23e
AW		 305{
306 ARGS1 (x);
e78d4bf9
LC		 307
308 /* Check for overflow. */
b2b33168 309 if (SCM_LIKELY ((scm_t_intptr) SCM_UNPACK (x) < INUM_MAX))
7382f23e 310 {
e78d4bf9
LC		 311 SCM result;
312
313 /* Add the integers without untagging. */
b2b33168
AW		 314 result = SCM_PACK ((scm_t_intptr) SCM_UNPACK (x)
315 + (scm_t_intptr) SCM_UNPACK (SCM_I_MAKINUM (1))
e78d4bf9
LC		 316 - scm_tc2_int);
317
318 if (SCM_LIKELY (SCM_I_INUMP (result)))
319 RETURN (result);
7382f23e 320 }
e78d4bf9 321
7382f23e
AW		 322 SYNC_REGISTER ();
323 RETURN (scm_sum (x, SCM_I_MAKINUM (1)));
324}
325
9348168e 326VM_DEFINE_FUNCTION (154, sub, "sub", 2)
a80be762 327{
0c57673a 328#ifndef ASM_SUB
a80be762 329 FUNC2 (-, scm_difference);
0c57673a
LC		 330#else
331 ARGS2 (x, y);
332 ASM_SUB (x, y);
333 SYNC_REGISTER ();
334 RETURN (scm_difference (x, y));
335#endif
a80be762
KN		 336}
337
9348168e 338VM_DEFINE_FUNCTION (155, sub1, "sub1", 1)
7382f23e
AW		 339{
340 ARGS1 (x);
e78d4bf9
LC		 341
342 /* Check for underflow. */
b2b33168 343 if (SCM_LIKELY ((scm_t_intptr) SCM_UNPACK (x) > INUM_MIN))
7382f23e 344 {
e78d4bf9
LC		 345 SCM result;
346
347 /* Substract the integers without untagging. */
b2b33168
AW		 348 result = SCM_PACK ((scm_t_intptr) SCM_UNPACK (x)
349 - (scm_t_intptr) SCM_UNPACK (SCM_I_MAKINUM (1))
e78d4bf9
LC		 350 + scm_tc2_int);
351
352 if (SCM_LIKELY (SCM_I_INUMP (result)))
353 RETURN (result);
7382f23e 354 }
e78d4bf9 355
7382f23e
AW		 356 SYNC_REGISTER ();
357 RETURN (scm_difference (x, SCM_I_MAKINUM (1)));
358}
359
0c57673a
LC		 360# undef ASM_ADD
361# undef ASM_SUB
362
9348168e 363VM_DEFINE_FUNCTION (156, mul, "mul", 2)
a80be762
KN		 364{
365 ARGS2 (x, y);
1865ad56 366 SYNC_REGISTER ();
a80be762
KN		 367 RETURN (scm_product (x, y));
368}
369
9348168e 370VM_DEFINE_FUNCTION (157, div, "div", 2)
a80be762
KN		 371{
372 ARGS2 (x, y);
1865ad56 373 SYNC_REGISTER ();
a80be762
KN		 374 RETURN (scm_divide (x, y));
375}
376
9348168e 377VM_DEFINE_FUNCTION (158, quo, "quo", 2)
a80be762
KN		 378{
379 ARGS2 (x, y);
1865ad56 380 SYNC_REGISTER ();
a80be762
KN		 381 RETURN (scm_quotient (x, y));
382}
383
9348168e 384VM_DEFINE_FUNCTION (159, rem, "rem", 2)
a80be762
KN		 385{
386 ARGS2 (x, y);
1865ad56 387 SYNC_REGISTER ();
a80be762
KN		 388 RETURN (scm_remainder (x, y));
389}
390
9348168e 391VM_DEFINE_FUNCTION (160, mod, "mod", 2)
a80be762
KN		 392{
393 ARGS2 (x, y);
1865ad56 394 SYNC_REGISTER ();
a80be762
KN		 395 RETURN (scm_modulo (x, y));
396}
397
9348168e 398VM_DEFINE_FUNCTION (161, ash, "ash", 2)
b10d9330
AW		 399{
400 ARGS2 (x, y);
401 if (SCM_I_INUMP (x) && SCM_I_INUMP (y))
402 {
403 if (SCM_I_INUM (y) < 0)
8ecd1943 404 /* Right shift, will be a fixnum. */
b10d9330 405 RETURN (SCM_I_MAKINUM (SCM_I_INUM (x) >> -SCM_I_INUM (y)));
8ecd1943
AW		 406 else
407 /* Left shift. See comments in scm_ash. */
408 {
e25f3727 409 scm_t_signed_bits nn, bits_to_shift;
8ecd1943
AW		 410
411 nn = SCM_I_INUM (x);
412 bits_to_shift = SCM_I_INUM (y);
413
414 if (bits_to_shift < SCM_I_FIXNUM_BIT-1
e25f3727 415 && ((scm_t_bits)
8ecd1943
AW		 416 (SCM_SRS (nn, (SCM_I_FIXNUM_BIT-1 - bits_to_shift)) + 1)
417 <= 1))
418 RETURN (SCM_I_MAKINUM (nn << bits_to_shift));
419 /* fall through */
420 }
b10d9330
AW		 421 /* fall through */
422 }
423 SYNC_REGISTER ();
424 RETURN (scm_ash (x, y));
425}
426
9348168e 427VM_DEFINE_FUNCTION (162, logand, "logand", 2)
b10d9330
AW		 428{
429 ARGS2 (x, y);
430 if (SCM_I_INUMP (x) && SCM_I_INUMP (y))
431 RETURN (SCM_I_MAKINUM (SCM_I_INUM (x) & SCM_I_INUM (y)));
432 SYNC_REGISTER ();
433 RETURN (scm_logand (x, y));
434}
435
9348168e 436VM_DEFINE_FUNCTION (163, logior, "logior", 2)
b10d9330
AW		 437{
438 ARGS2 (x, y);
439 if (SCM_I_INUMP (x) && SCM_I_INUMP (y))
440 RETURN (SCM_I_MAKINUM (SCM_I_INUM (x) | SCM_I_INUM (y)));
441 SYNC_REGISTER ();
442 RETURN (scm_logior (x, y));
443}
444
9348168e 445VM_DEFINE_FUNCTION (164, logxor, "logxor", 2)
b10d9330
AW		 446{
447 ARGS2 (x, y);
448 if (SCM_I_INUMP (x) && SCM_I_INUMP (y))
449 RETURN (SCM_I_MAKINUM (SCM_I_INUM (x) ^ SCM_I_INUM (y)));
450 SYNC_REGISTER ();
451 RETURN (scm_logxor (x, y));
452}
453
1e4b834a 454\f
d5a4f51f
AW		 455/*
456 * Strings
457 */
458
5ddd9645 459VM_DEFINE_FUNCTION (165, string_length, "string-length", 1)
d5a4f51f
AW		 460{
461 ARGS1 (str);
462 if (SCM_LIKELY (scm_is_string (str)))
463 RETURN (SCM_I_MAKINUM (scm_i_string_length (str)));
464 else
465 {
466 SYNC_REGISTER ();
467 RETURN (scm_string_length (str));
468 }
469}
470
5ddd9645 471VM_DEFINE_FUNCTION (166, string_ref, "string-ref", 2)
d5a4f51f
AW		 472{
473 scm_t_signed_bits i = 0;
474 ARGS2 (str, idx);
475 if (SCM_LIKELY (scm_is_string (str)
476 && SCM_I_INUMP (idx)
477 && ((i = SCM_I_INUM (idx)) >= 0)
478 && i < scm_i_string_length (str)))
479 RETURN (SCM_MAKE_CHAR (scm_i_string_ref (str, i)));
480 else
481 {
482 SYNC_REGISTER ();
483 RETURN (scm_string_ref (str, idx));
484 }
485}
486
487/* No string-set! instruction, as there is no good fast path there. */
488
489\f
1e4b834a 490/*
827dc8dc 491 * Vectors and arrays
1e4b834a 492 */
aec4a84a 493
5ddd9645 494VM_DEFINE_FUNCTION (167, vector_length, "vector-length", 1)
d5a4f51f
AW		 495{
496 ARGS1 (vect);
497 if (SCM_LIKELY (SCM_I_IS_VECTOR (vect)))
498 RETURN (SCM_I_MAKINUM (SCM_I_VECTOR_LENGTH (vect)));
499 else
500 {
501 SYNC_REGISTER ();
502 RETURN (scm_vector_length (vect));
503 }
504}
505
5ddd9645 506VM_DEFINE_FUNCTION (168, vector_ref, "vector-ref", 2)
d6f1ce3d 507{
e25f3727 508 scm_t_signed_bits i = 0;
d6f1ce3d 509 ARGS2 (vect, idx);
7b702b53 510 if (SCM_LIKELY (SCM_I_IS_NONWEAK_VECTOR (vect)
d6f1ce3d
AW		 511 && SCM_I_INUMP (idx)
512 && ((i = SCM_I_INUM (idx)) >= 0)
513 && i < SCM_I_VECTOR_LENGTH (vect)))
514 RETURN (SCM_I_VECTOR_ELTS (vect)[i]);
515 else
9b29d607
AW		 516 {
517 SYNC_REGISTER ();
518 RETURN (scm_vector_ref (vect, idx));
519 }
d6f1ce3d
AW		 520}
521
5ddd9645 522VM_DEFINE_INSTRUCTION (169, vector_set, "vector-set", 0, 3, 0)
d6f1ce3d 523{
e25f3727 524 scm_t_signed_bits i = 0;
d6f1ce3d 525 SCM vect, idx, val;
eae2438d 526 POP3 (val, idx, vect);
7b702b53 527 if (SCM_LIKELY (SCM_I_IS_NONWEAK_VECTOR (vect)
d6f1ce3d
AW		 528 && SCM_I_INUMP (idx)
529 && ((i = SCM_I_INUM (idx)) >= 0)
530 && i < SCM_I_VECTOR_LENGTH (vect)))
531 SCM_I_VECTOR_WELTS (vect)[i] = val;
532 else
9b29d607
AW		 533 {
534 SYNC_REGISTER ();
535 scm_vector_set_x (vect, idx, val);
536 }
d6f1ce3d
AW		 537 NEXT;
538}
539
5ddd9645 540VM_DEFINE_INSTRUCTION (170, make_array, "make-array", 3, -1, 1)
827dc8dc
AW		 541{
542 scm_t_uint32 len;
543 SCM shape, ret;
544
545 len = FETCH ();
546 len = (len << 8) + FETCH ();
547 len = (len << 8) + FETCH ();
548 POP (shape);
549 SYNC_REGISTER ();
384dce46 550 PRE_CHECK_UNDERFLOW (len);
827dc8dc
AW		 551 ret = scm_from_contiguous_array (shape, sp - len + 1, len);
552 DROPN (len);
553 PUSH (ret);
554 NEXT;
555}
556
557\f
558/*
559 * Structs
560 */
41e49280 561#define VM_VALIDATE_STRUCT(obj, proc) \
776491ca 562 VM_ASSERT (SCM_STRUCTP (obj), vm_error_not_a_struct (proc, obj))
827dc8dc 563
5ddd9645 564VM_DEFINE_FUNCTION (171, struct_p, "struct?", 1)
827dc8dc
AW		 565{
566 ARGS1 (obj);
567 RETURN (scm_from_bool (SCM_STRUCTP (obj)));
568}
569
5ddd9645 570VM_DEFINE_FUNCTION (172, struct_vtable, "struct-vtable", 1)
827dc8dc
AW		 571{
572 ARGS1 (obj);
41e49280 573 VM_VALIDATE_STRUCT (obj, "struct_vtable");
827dc8dc
AW		 574 RETURN (SCM_STRUCT_VTABLE (obj));
575}
576
5ddd9645 577VM_DEFINE_INSTRUCTION (173, make_struct, "make-struct", 2, -1, 1)
827dc8dc
AW		 578{
579 unsigned h = FETCH ();
580 unsigned l = FETCH ();
9a974fd3
AW		 581 scm_t_bits n = ((h << 8U) + l);
582 SCM vtable = sp[-(n - 1)];
583 const SCM *inits = sp - n + 2;
584 SCM ret;
827dc8dc 585
9823fd39
LC		 586 SYNC_REGISTER ();
587
827dc8dc
AW		 588 if (SCM_LIKELY (SCM_STRUCTP (vtable)
589 && SCM_VTABLE_FLAG_IS_SET (vtable, SCM_VTABLE_FLAG_SIMPLE)
9a974fd3
AW		 590 && (SCM_STRUCT_DATA_REF (vtable, scm_vtable_index_size) + 1
591 == n)
592 && !SCM_VTABLE_INSTANCE_FINALIZER (vtable)))
827dc8dc 593 {
9a974fd3
AW		 594 /* Verily, we are making a simple struct with the right number of
595 initializers, and no finalizer. */
596 ret = scm_words ((scm_t_bits)SCM_STRUCT_DATA (vtable) | scm_tc3_struct,
597 n + 1);
598 SCM_SET_CELL_WORD_1 (ret, (scm_t_bits)SCM_CELL_OBJECT_LOC (ret, 2));
599 memcpy (SCM_STRUCT_DATA (ret), inits, (n - 1) * sizeof (SCM));
827dc8dc 600 }
9a974fd3
AW		 601 else
602 ret = scm_c_make_structv (vtable, 0, n - 1, (scm_t_bits *) inits);
603
c99865c1 604 DROPN (n);
9a974fd3 605 PUSH (ret);
827dc8dc 606
9a974fd3 607 NEXT;
827dc8dc
AW		 608}
609
5ddd9645 610VM_DEFINE_FUNCTION (174, struct_ref, "struct-ref", 2)
827dc8dc
AW		 611{
612 ARGS2 (obj, pos);
613
614 if (SCM_LIKELY (SCM_STRUCTP (obj)
615 && SCM_STRUCT_VTABLE_FLAG_IS_SET (obj,
616 SCM_VTABLE_FLAG_SIMPLE)
617 && SCM_I_INUMP (pos)))
618 {
619 SCM vtable;
620 scm_t_bits index, len;
621
e25f3727
AW		 622 /* True, an inum is a signed value, but cast to unsigned it will
623 certainly be more than the length, so we will fall through if
624 index is negative. */
827dc8dc
AW		 625 index = SCM_I_INUM (pos);
626 vtable = SCM_STRUCT_VTABLE (obj);
627 len = SCM_STRUCT_DATA_REF (vtable, scm_vtable_index_size);
628
629 if (SCM_LIKELY (index < len))
630 {
631 scm_t_bits *data = SCM_STRUCT_DATA (obj);
632 RETURN (SCM_PACK (data[index]));
633 }
634 }
635
9823fd39 636 SYNC_REGISTER ();
827dc8dc
AW		 637 RETURN (scm_struct_ref (obj, pos));
638}
639
5ddd9645 640VM_DEFINE_FUNCTION (175, struct_set, "struct-set", 3)
827dc8dc
AW		 641{
642 ARGS3 (obj, pos, val);
643
644 if (SCM_LIKELY (SCM_STRUCTP (obj)
645 && SCM_STRUCT_VTABLE_FLAG_IS_SET (obj,
646 SCM_VTABLE_FLAG_SIMPLE)
647 && SCM_STRUCT_VTABLE_FLAG_IS_SET (obj,
648 SCM_VTABLE_FLAG_SIMPLE_RW)
649 && SCM_I_INUMP (pos)))
650 {
651 SCM vtable;
652 scm_t_bits index, len;
653
e25f3727 654 /* See above regarding index being >= 0. */
827dc8dc
AW		 655 index = SCM_I_INUM (pos);
656 vtable = SCM_STRUCT_VTABLE (obj);
657 len = SCM_STRUCT_DATA_REF (vtable, scm_vtable_index_size);
658 if (SCM_LIKELY (index < len))
659 {
660 scm_t_bits *data = SCM_STRUCT_DATA (obj);
661 data[index] = SCM_UNPACK (val);
662 RETURN (val);
663 }
664 }
665
9823fd39 666 SYNC_REGISTER ();
827dc8dc
AW		 667 RETURN (scm_struct_set_x (obj, pos, val));
668}
669
670\f
671/*
672 * GOOPS support
673 */
5ddd9645 674VM_DEFINE_FUNCTION (176, class_of, "class-of", 1)
827dc8dc
AW		 675{
676 ARGS1 (obj);
1a461493
AW		 677 if (SCM_INSTANCEP (obj))
678 RETURN (SCM_CLASS_OF (obj));
679 SYNC_REGISTER ();
680 RETURN (scm_class_of (obj));
827dc8dc
AW		 681}
682
e25f3727 683/* FIXME: No checking whatsoever. */
5ddd9645 684VM_DEFINE_FUNCTION (177, slot_ref, "slot-ref", 2)
827dc8dc
AW		 685{
686 size_t slot;
687 ARGS2 (instance, idx);
688 slot = SCM_I_INUM (idx);
689 RETURN (SCM_PACK (SCM_STRUCT_DATA (instance) [slot]));
690}
691
e25f3727 692/* FIXME: No checking whatsoever. */
5ddd9645 693VM_DEFINE_INSTRUCTION (178, slot_set, "slot-set", 0, 3, 0)
827dc8dc
AW		 694{
695 SCM instance, idx, val;
696 size_t slot;
eae2438d 697 POP3 (val, idx, instance);
827dc8dc
AW		 698 slot = SCM_I_INUM (idx);
699 SCM_STRUCT_DATA (instance) [slot] = SCM_UNPACK (val);
700 NEXT;
701}
702
703\f
704/*
705 * Bytevectors
706 */
41e49280 707#define VM_VALIDATE_BYTEVECTOR(x, proc) \
53bdfcf0 708 VM_ASSERT (SCM_BYTEVECTOR_P (x), vm_error_not_a_bytevector (proc, x))
e6eb2467
AW		 709
710#define BV_REF_WITH_ENDIANNESS(stem, fn_stem) \
711{ \
712 SCM endianness; \
713 POP (endianness); \
714 if (scm_is_eq (endianness, scm_i_native_endianness)) \
715 goto VM_LABEL (bv_##stem##_native_ref); \
716 { \
717 ARGS2 (bv, idx); \
9823fd39 718 SYNC_REGISTER (); \
e6eb2467
AW		 719 RETURN (scm_bytevector_##fn_stem##_ref (bv, idx, endianness)); \
720 } \
721}
722
daccfef4
LC		 723/* Return true (non-zero) if PTR has suitable alignment for TYPE. */
724#define ALIGNED_P(ptr, type) \
1002c774 725 ((scm_t_uintptr) (ptr) % alignof_type (type) == 0)
daccfef4 726
5ddd9645 727VM_DEFINE_FUNCTION (179, bv_u16_ref, "bv-u16-ref", 3)
e6eb2467 728BV_REF_WITH_ENDIANNESS (u16, u16)
5ddd9645 729VM_DEFINE_FUNCTION (180, bv_s16_ref, "bv-s16-ref", 3)
e6eb2467 730BV_REF_WITH_ENDIANNESS (s16, s16)
5ddd9645 731VM_DEFINE_FUNCTION (181, bv_u32_ref, "bv-u32-ref", 3)
e6eb2467 732BV_REF_WITH_ENDIANNESS (u32, u32)
5ddd9645 733VM_DEFINE_FUNCTION (182, bv_s32_ref, "bv-s32-ref", 3)
e6eb2467 734BV_REF_WITH_ENDIANNESS (s32, s32)
5ddd9645 735VM_DEFINE_FUNCTION (183, bv_u64_ref, "bv-u64-ref", 3)
e6eb2467 736BV_REF_WITH_ENDIANNESS (u64, u64)
5ddd9645 737VM_DEFINE_FUNCTION (184, bv_s64_ref, "bv-s64-ref", 3)
e6eb2467 738BV_REF_WITH_ENDIANNESS (s64, s64)
5ddd9645 739VM_DEFINE_FUNCTION (185, bv_f32_ref, "bv-f32-ref", 3)
e6eb2467 740BV_REF_WITH_ENDIANNESS (f32, ieee_single)
5ddd9645 741VM_DEFINE_FUNCTION (186, bv_f64_ref, "bv-f64-ref", 3)
e6eb2467
AW		 742BV_REF_WITH_ENDIANNESS (f64, ieee_double)
743
744#undef BV_REF_WITH_ENDIANNESS
745
9823fd39
LC		 746#define BV_FIXABLE_INT_REF(stem, fn_stem, type, size) \
747{ \
e25f3727 748 scm_t_signed_bits i; \
daccfef4 749 const scm_t_ ## type *int_ptr; \
9823fd39 750 ARGS2 (bv, idx); \
daccfef4 751 \
41e49280 752 VM_VALIDATE_BYTEVECTOR (bv, "bv-" #stem "-ref"); \
daccfef4
LC		 753 i = SCM_I_INUM (idx); \
754 int_ptr = (scm_t_ ## type *) (SCM_BYTEVECTOR_CONTENTS (bv) + i); \
755 \
9823fd39 756 if (SCM_LIKELY (SCM_I_INUMP (idx) \
daccfef4 757 && (i >= 0) \
9823fd39 758 && (i + size <= SCM_BYTEVECTOR_LENGTH (bv)) \
daccfef4
LC		 759 && (ALIGNED_P (int_ptr, scm_t_ ## type)))) \
760 RETURN (SCM_I_MAKINUM (*int_ptr)); \
9823fd39
LC		 761 else \
762 { \
763 SYNC_REGISTER (); \
764 RETURN (scm_bytevector_ ## fn_stem ## _ref (bv, idx)); \
765 } \
766}
767
768#define BV_INT_REF(stem, type, size) \
769{ \
e25f3727 770 scm_t_signed_bits i; \
daccfef4 771 const scm_t_ ## type *int_ptr; \
9823fd39 772 ARGS2 (bv, idx); \
daccfef4 773 \
41e49280 774 VM_VALIDATE_BYTEVECTOR (bv, "bv-" #stem "-ref"); \
daccfef4
LC		 775 i = SCM_I_INUM (idx); \
776 int_ptr = (scm_t_ ## type *) (SCM_BYTEVECTOR_CONTENTS (bv) + i); \
777 \
9823fd39 778 if (SCM_LIKELY (SCM_I_INUMP (idx) \
daccfef4 779 && (i >= 0) \
9823fd39 780 && (i + size <= SCM_BYTEVECTOR_LENGTH (bv)) \
daccfef4
LC		 781 && (ALIGNED_P (int_ptr, scm_t_ ## type)))) \
782 { \
783 scm_t_ ## type x = *int_ptr; \
9823fd39
LC		 784 if (SCM_FIXABLE (x)) \
785 RETURN (SCM_I_MAKINUM (x)); \
786 else \
787 { \
788 SYNC_REGISTER (); \
789 RETURN (scm_from_ ## type (x)); \
790 } \
791 } \
792 else \
793 { \
794 SYNC_REGISTER (); \
795 RETURN (scm_bytevector_ ## stem ## _native_ref (bv, idx)); \
796 } \
797}
798
799#define BV_FLOAT_REF(stem, fn_stem, type, size) \
800{ \
e25f3727 801 scm_t_signed_bits i; \
daccfef4 802 const type *float_ptr; \
9823fd39 803 ARGS2 (bv, idx); \
daccfef4 804 \
41e49280 805 VM_VALIDATE_BYTEVECTOR (bv, "bv-" #stem "-ref"); \
daccfef4
LC		 806 i = SCM_I_INUM (idx); \
807 float_ptr = (type *) (SCM_BYTEVECTOR_CONTENTS (bv) + i); \
808 \
9823fd39
LC		 809 SYNC_REGISTER (); \
810 if (SCM_LIKELY (SCM_I_INUMP (idx) \
daccfef4 811 && (i >= 0) \
9823fd39 812 && (i + size <= SCM_BYTEVECTOR_LENGTH (bv)) \
daccfef4
LC		 813 && (ALIGNED_P (float_ptr, type)))) \
814 RETURN (scm_from_double (*float_ptr)); \
9823fd39
LC		 815 else \
816 RETURN (scm_bytevector_ ## fn_stem ## _native_ref (bv, idx)); \
e6eb2467
AW		 817}
818
5ddd9645 819VM_DEFINE_FUNCTION (187, bv_u8_ref, "bv-u8-ref", 2)
e6eb2467 820BV_FIXABLE_INT_REF (u8, u8, uint8, 1)
5ddd9645 821VM_DEFINE_FUNCTION (188, bv_s8_ref, "bv-s8-ref", 2)
e6eb2467 822BV_FIXABLE_INT_REF (s8, s8, int8, 1)
5ddd9645 823VM_DEFINE_FUNCTION (189, bv_u16_native_ref, "bv-u16-native-ref", 2)
e6eb2467 824BV_FIXABLE_INT_REF (u16, u16_native, uint16, 2)
5ddd9645 825VM_DEFINE_FUNCTION (190, bv_s16_native_ref, "bv-s16-native-ref", 2)
e6eb2467 826BV_FIXABLE_INT_REF (s16, s16_native, int16, 2)
5ddd9645 827VM_DEFINE_FUNCTION (191, bv_u32_native_ref, "bv-u32-native-ref", 2)
dddacb23
LC		 828#if SIZEOF_VOID_P > 4
829BV_FIXABLE_INT_REF (u32, u32_native, uint32, 4)
830#else
e6eb2467 831BV_INT_REF (u32, uint32, 4)
dddacb23 832#endif
5ddd9645 833VM_DEFINE_FUNCTION (192, bv_s32_native_ref, "bv-s32-native-ref", 2)
dddacb23
LC		 834#if SIZEOF_VOID_P > 4
835BV_FIXABLE_INT_REF (s32, s32_native, int32, 4)
836#else
e6eb2467 837BV_INT_REF (s32, int32, 4)
dddacb23 838#endif
5ddd9645 839VM_DEFINE_FUNCTION (193, bv_u64_native_ref, "bv-u64-native-ref", 2)
e6eb2467 840BV_INT_REF (u64, uint64, 8)
5ddd9645 841VM_DEFINE_FUNCTION (194, bv_s64_native_ref, "bv-s64-native-ref", 2)
e6eb2467 842BV_INT_REF (s64, int64, 8)
5ddd9645 843VM_DEFINE_FUNCTION (195, bv_f32_native_ref, "bv-f32-native-ref", 2)
e6eb2467 844BV_FLOAT_REF (f32, ieee_single, float, 4)
5ddd9645 845VM_DEFINE_FUNCTION (196, bv_f64_native_ref, "bv-f64-native-ref", 2)
e6eb2467
AW		 846BV_FLOAT_REF (f64, ieee_double, double, 8)
847
848#undef BV_FIXABLE_INT_REF
849#undef BV_INT_REF
850#undef BV_FLOAT_REF
851
852
853
854#define BV_SET_WITH_ENDIANNESS(stem, fn_stem) \
855{ \
856 SCM endianness; \
857 POP (endianness); \
858 if (scm_is_eq (endianness, scm_i_native_endianness)) \
859 goto VM_LABEL (bv_##stem##_native_set); \
860 { \
eae2438d 861 SCM bv, idx, val; POP3 (val, idx, bv); \
ad301b6d 862 SYNC_REGISTER (); \
d6f1ce3d
AW		 863 scm_bytevector_##fn_stem##_set_x (bv, idx, val, endianness); \
864 NEXT; \
e6eb2467
AW		 865 } \
866}
867
5ddd9645 868VM_DEFINE_INSTRUCTION (197, bv_u16_set, "bv-u16-set", 0, 4, 0)
e6eb2467 869BV_SET_WITH_ENDIANNESS (u16, u16)
5ddd9645 870VM_DEFINE_INSTRUCTION (198, bv_s16_set, "bv-s16-set", 0, 4, 0)
e6eb2467 871BV_SET_WITH_ENDIANNESS (s16, s16)
5ddd9645 872VM_DEFINE_INSTRUCTION (199, bv_u32_set, "bv-u32-set", 0, 4, 0)
e6eb2467 873BV_SET_WITH_ENDIANNESS (u32, u32)
5ddd9645 874VM_DEFINE_INSTRUCTION (200, bv_s32_set, "bv-s32-set", 0, 4, 0)
e6eb2467 875BV_SET_WITH_ENDIANNESS (s32, s32)
5ddd9645 876VM_DEFINE_INSTRUCTION (201, bv_u64_set, "bv-u64-set", 0, 4, 0)
e6eb2467 877BV_SET_WITH_ENDIANNESS (u64, u64)
5ddd9645 878VM_DEFINE_INSTRUCTION (202, bv_s64_set, "bv-s64-set", 0, 4, 0)
e6eb2467 879BV_SET_WITH_ENDIANNESS (s64, s64)
5ddd9645 880VM_DEFINE_INSTRUCTION (203, bv_f32_set, "bv-f32-set", 0, 4, 0)
e6eb2467 881BV_SET_WITH_ENDIANNESS (f32, ieee_single)
5ddd9645 882VM_DEFINE_INSTRUCTION (204, bv_f64_set, "bv-f64-set", 0, 4, 0)
e6eb2467
AW		 883BV_SET_WITH_ENDIANNESS (f64, ieee_double)
884
885#undef BV_SET_WITH_ENDIANNESS
886
daccfef4
LC		 887#define BV_FIXABLE_INT_SET(stem, fn_stem, type, min, max, size) \
888{ \
e25f3727 889 scm_t_signed_bits i, j = 0; \
daccfef4
LC		 890 SCM bv, idx, val; \
891 scm_t_ ## type *int_ptr; \
892 \
eae2438d 893 POP3 (val, idx, bv); \
41e49280 894 VM_VALIDATE_BYTEVECTOR (bv, "bv-" #stem "-set"); \
daccfef4
LC		 895 i = SCM_I_INUM (idx); \
896 int_ptr = (scm_t_ ## type *) (SCM_BYTEVECTOR_CONTENTS (bv) + i); \
897 \
898 if (SCM_LIKELY (SCM_I_INUMP (idx) \
899 && (i >= 0) \
900 && (i + size <= SCM_BYTEVECTOR_LENGTH (bv)) \
901 && (ALIGNED_P (int_ptr, scm_t_ ## type)) \
902 && (SCM_I_INUMP (val)) \
903 && ((j = SCM_I_INUM (val)) >= min) \
904 && (j <= max))) \
905 *int_ptr = (scm_t_ ## type) j; \
906 else \
ad301b6d
AW		 907 { \
908 SYNC_REGISTER (); \
909 scm_bytevector_ ## fn_stem ## _set_x (bv, idx, val); \
910 } \
daccfef4
LC		 911 NEXT; \
912}
913
914#define BV_INT_SET(stem, type, size) \
915{ \
e25f3727 916 scm_t_signed_bits i = 0; \
daccfef4
LC		 917 SCM bv, idx, val; \
918 scm_t_ ## type *int_ptr; \
919 \
eae2438d 920 POP3 (val, idx, bv); \
41e49280 921 VM_VALIDATE_BYTEVECTOR (bv, "bv-" #stem "-set"); \
daccfef4
LC		 922 i = SCM_I_INUM (idx); \
923 int_ptr = (scm_t_ ## type *) (SCM_BYTEVECTOR_CONTENTS (bv) + i); \
924 \
925 if (SCM_LIKELY (SCM_I_INUMP (idx) \
926 && (i >= 0) \
927 && (i + size <= SCM_BYTEVECTOR_LENGTH (bv)) \
928 && (ALIGNED_P (int_ptr, scm_t_ ## type)))) \
929 *int_ptr = scm_to_ ## type (val); \
930 else \
ad301b6d
AW		 931 { \
932 SYNC_REGISTER (); \
933 scm_bytevector_ ## stem ## _native_set_x (bv, idx, val); \
934 } \
935 NEXT; \
daccfef4
LC		 936}
937
ad301b6d
AW		 938#define BV_FLOAT_SET(stem, fn_stem, type, size) \
939{ \
940 scm_t_signed_bits i = 0; \
941 SCM bv, idx, val; \
942 type *float_ptr; \
943 \
eae2438d 944 POP3 (val, idx, bv); \
ad301b6d
AW		 945 VM_VALIDATE_BYTEVECTOR (bv, "bv-" #stem "-set"); \
946 i = SCM_I_INUM (idx); \
947 float_ptr = (type *) (SCM_BYTEVECTOR_CONTENTS (bv) + i); \
948 \
949 if (SCM_LIKELY (SCM_I_INUMP (idx) \
950 && (i >= 0) \
951 && (i + size <= SCM_BYTEVECTOR_LENGTH (bv)) \
952 && (ALIGNED_P (float_ptr, type)))) \
953 *float_ptr = scm_to_double (val); \
954 else \
955 { \
956 SYNC_REGISTER (); \
957 scm_bytevector_ ## fn_stem ## _native_set_x (bv, idx, val); \
958 } \
959 NEXT; \
e6eb2467
AW		 960}
961
5ddd9645 962VM_DEFINE_INSTRUCTION (205, bv_u8_set, "bv-u8-set", 0, 3, 0)
e6eb2467 963BV_FIXABLE_INT_SET (u8, u8, uint8, 0, SCM_T_UINT8_MAX, 1)
5ddd9645 964VM_DEFINE_INSTRUCTION (206, bv_s8_set, "bv-s8-set", 0, 3, 0)
e6eb2467 965BV_FIXABLE_INT_SET (s8, s8, int8, SCM_T_INT8_MIN, SCM_T_INT8_MAX, 1)
5ddd9645 966VM_DEFINE_INSTRUCTION (207, bv_u16_native_set, "bv-u16-native-set", 0, 3, 0)
d6f1ce3d 967BV_FIXABLE_INT_SET (u16, u16_native, uint16, 0, SCM_T_UINT16_MAX, 2)
5ddd9645 968VM_DEFINE_INSTRUCTION (208, bv_s16_native_set, "bv-s16-native-set", 0, 3, 0)
d6f1ce3d 969BV_FIXABLE_INT_SET (s16, s16_native, int16, SCM_T_INT16_MIN, SCM_T_INT16_MAX, 2)
5ddd9645 970VM_DEFINE_INSTRUCTION (209, bv_u32_native_set, "bv-u32-native-set", 0, 3, 0)
dddacb23
LC		 971#if SIZEOF_VOID_P > 4
972BV_FIXABLE_INT_SET (u32, u32_native, uint32, 0, SCM_T_UINT32_MAX, 4)
973#else
e6eb2467 974BV_INT_SET (u32, uint32, 4)
dddacb23 975#endif
5ddd9645 976VM_DEFINE_INSTRUCTION (210, bv_s32_native_set, "bv-s32-native-set", 0, 3, 0)
dddacb23
LC		 977#if SIZEOF_VOID_P > 4
978BV_FIXABLE_INT_SET (s32, s32_native, int32, SCM_T_INT32_MIN, SCM_T_INT32_MAX, 4)
979#else
e6eb2467 980BV_INT_SET (s32, int32, 4)
dddacb23 981#endif
5ddd9645 982VM_DEFINE_INSTRUCTION (211, bv_u64_native_set, "bv-u64-native-set", 0, 3, 0)
e6eb2467 983BV_INT_SET (u64, uint64, 8)
5ddd9645 984VM_DEFINE_INSTRUCTION (212, bv_s64_native_set, "bv-s64-native-set", 0, 3, 0)
e6eb2467 985BV_INT_SET (s64, int64, 8)
5ddd9645 986VM_DEFINE_INSTRUCTION (213, bv_f32_native_set, "bv-f32-native-set", 0, 3, 0)
e6eb2467 987BV_FLOAT_SET (f32, ieee_single, float, 4)
5ddd9645 988VM_DEFINE_INSTRUCTION (214, bv_f64_native_set, "bv-f64-native-set", 0, 3, 0)
e6eb2467
AW		 989BV_FLOAT_SET (f64, ieee_double, double, 8)
990
991#undef BV_FIXABLE_INT_SET
992#undef BV_INT_SET
993#undef BV_FLOAT_SET
994
53e28ed9
AW		 995/*
996(defun renumber-ops ()
997 "start from top of buffer and renumber 'VM_DEFINE_FOO (\n' sequences"
998 (interactive "")
999 (save-excursion
827dc8dc 1000 (let ((counter 127)) (goto-char (point-min))
53e28ed9
AW		 1001 (while (re-search-forward "^VM_DEFINE_[^ ]+ (\\([^,]+\\)," (point-max) t)
1002 (replace-match
1003 (number-to-string (setq counter (1+ counter)))
1004 t t nil 1)))))
1005*/
1e4b834a 1006
17e90c5e
KN		 1007/*
1008 Local Variables:
1009 c-file-style: "gnu"
1010 End:
1011*/
Unnamed repository; edit this file 'description' to name the repository.