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Merge remote-tracking branch 'origin/stable-2.0'
[bpt/guile.git] / libguile / vm-i-scheme.c
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53bdfcf0 1/* Copyright (C) 2001, 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
a98cef7e 2 *
560b9c25 3 * This library is free software; you can redistribute it and/or
53befeb7
NJ		 4 * modify it under the terms of the GNU Lesser General Public License
5 * as published by the Free Software Foundation; either version 3 of
6 * the License, or (at your option) any later version.
a98cef7e 7 *
53befeb7
NJ		 8 * This library is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
560b9c25
AW		 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * Lesser General Public License for more details.
a98cef7e 12 *
560b9c25
AW		 13 * You should have received a copy of the GNU Lesser General Public
14 * License along with this library; if not, write to the Free Software
53befeb7
NJ		 15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
16 * 02110-1301 USA
560b9c25 17 */
a98cef7e
KN		 18
19/* This file is included in vm_engine.c */
20
a80be762
KN		 21\f
22/*
23 * Predicates
24 */
25
93d197be 26#define ARGS1(a1) SCM a1 = sp[0];
11ea1aba
AW		 27#define ARGS2(a1,a2) SCM a1 = sp[-1], a2 = sp[0]; sp--; NULLSTACK (1);
28#define ARGS3(a1,a2,a3) SCM a1 = sp[-2], a2 = sp[-1], a3 = sp[0]; sp -= 2; NULLSTACK (2);
93d197be
AW		 29
30#define RETURN(x) do { *sp = x; NEXT; } while (0)
31
827dc8dc 32VM_DEFINE_FUNCTION (128, not, "not", 1)
a98cef7e 33{
a80be762 34 ARGS1 (x);
2533f10b 35 RETURN (scm_from_bool (scm_is_false (x)));
17e90c5e
KN		 36}
37
827dc8dc 38VM_DEFINE_FUNCTION (129, not_not, "not-not", 1)
17e90c5e 39{
a80be762 40 ARGS1 (x);
2533f10b 41 RETURN (scm_from_bool (!scm_is_false (x)));
17e90c5e
KN		 42}
43
827dc8dc 44VM_DEFINE_FUNCTION (130, eq, "eq?", 2)
17e90c5e 45{
a80be762 46 ARGS2 (x, y);
5c8cefe5 47 RETURN (scm_from_bool (scm_is_eq (x, y)));
17e90c5e
KN		 48}
49
827dc8dc 50VM_DEFINE_FUNCTION (131, not_eq, "not-eq?", 2)
17e90c5e 51{
a80be762 52 ARGS2 (x, y);
5c8cefe5 53 RETURN (scm_from_bool (!scm_is_eq (x, y)));
17e90c5e
KN		 54}
55
827dc8dc 56VM_DEFINE_FUNCTION (132, nullp, "null?", 1)
17e90c5e 57{
a80be762 58 ARGS1 (x);
2533f10b 59 RETURN (scm_from_bool (scm_is_null (x)));
a98cef7e
KN		 60}
61
827dc8dc 62VM_DEFINE_FUNCTION (133, not_nullp, "not-null?", 1)
a98cef7e 63{
a80be762 64 ARGS1 (x);
2533f10b 65 RETURN (scm_from_bool (!scm_is_null (x)));
a80be762
KN		 66}
67
9348168e
BT		 68VM_DEFINE_FUNCTION (134, nilp, "nil?", 1)
69{
70 ARGS1 (x);
71 RETURN (scm_from_bool (scm_is_lisp_false (x)));
72}
73
74VM_DEFINE_FUNCTION (135, not_nilp, "not-nil?", 1)
75{
76 ARGS1 (x);
77 RETURN (scm_from_bool (!scm_is_lisp_false (x)));
78}
79
80VM_DEFINE_FUNCTION (136, eqv, "eqv?", 2)
a80be762
KN		 81{
82 ARGS2 (x, y);
5c8cefe5 83 if (scm_is_eq (x, y))
a80be762
KN		 84 RETURN (SCM_BOOL_T);
85 if (SCM_IMP (x) || SCM_IMP (y))
86 RETURN (SCM_BOOL_F);
1865ad56 87 SYNC_REGISTER ();
a80be762
KN		 88 RETURN (scm_eqv_p (x, y));
89}
90
9348168e 91VM_DEFINE_FUNCTION (137, equal, "equal?", 2)
a80be762
KN		 92{
93 ARGS2 (x, y);
5c8cefe5 94 if (scm_is_eq (x, y))
a80be762
KN		 95 RETURN (SCM_BOOL_T);
96 if (SCM_IMP (x) || SCM_IMP (y))
97 RETURN (SCM_BOOL_F);
1865ad56 98 SYNC_REGISTER ();
a80be762 99 RETURN (scm_equal_p (x, y));
a98cef7e
KN		 100}
101
9348168e 102VM_DEFINE_FUNCTION (138, pairp, "pair?", 1)
a98cef7e 103{
a80be762 104 ARGS1 (x);
5c8cefe5 105 RETURN (scm_from_bool (scm_is_pair (x)));
a98cef7e
KN		 106}
107
9348168e 108VM_DEFINE_FUNCTION (139, listp, "list?", 1)
a98cef7e 109{
a80be762 110 ARGS1 (x);
9bd48cb1 111 RETURN (scm_from_bool (scm_ilength (x) >= 0));
a98cef7e
KN		 112}
113
9348168e 114VM_DEFINE_FUNCTION (140, symbolp, "symbol?", 1)
cf45ff03
AW		 115{
116 ARGS1 (x);
117 RETURN (scm_from_bool (scm_is_symbol (x)));
118}
119
9348168e 120VM_DEFINE_FUNCTION (141, vectorp, "vector?", 1)
cf45ff03
AW		 121{
122 ARGS1 (x);
123 RETURN (scm_from_bool (SCM_I_IS_VECTOR (x)));
124}
125
a80be762
KN		 126\f
127/*
128 * Basic data
129 */
130
9348168e 131VM_DEFINE_FUNCTION (142, cons, "cons", 2)
a98cef7e 132{
a80be762
KN		 133 ARGS2 (x, y);
134 CONS (x, x, y);
135 RETURN (x);
a98cef7e
KN		 136}
137
41e49280 138#define VM_VALIDATE_CONS(x, proc) \
53bdfcf0 139 VM_ASSERT (scm_is_pair (x), vm_error_not_a_pair (proc, x))
5e390de6 140
9348168e 141VM_DEFINE_FUNCTION (143, car, "car", 1)
a98cef7e 142{
a80be762 143 ARGS1 (x);
41e49280 144 VM_VALIDATE_CONS (x, "car");
a80be762 145 RETURN (SCM_CAR (x));
a98cef7e
KN		 146}
147
9348168e 148VM_DEFINE_FUNCTION (144, cdr, "cdr", 1)
a98cef7e 149{
a80be762 150 ARGS1 (x);
41e49280 151 VM_VALIDATE_CONS (x, "cdr");
a80be762 152 RETURN (SCM_CDR (x));
a98cef7e
KN		 153}
154
9348168e 155VM_DEFINE_INSTRUCTION (145, set_car, "set-car!", 0, 2, 0)
a98cef7e 156{
60ed31d2 157 SCM x, y;
eae2438d 158 POP2 (y, x);
41e49280 159 VM_VALIDATE_CONS (x, "set-car!");
a80be762 160 SCM_SETCAR (x, y);
60ed31d2 161 NEXT;
a98cef7e
KN		 162}
163
9348168e 164VM_DEFINE_INSTRUCTION (146, set_cdr, "set-cdr!", 0, 2, 0)
a98cef7e 165{
60ed31d2 166 SCM x, y;
eae2438d 167 POP2 (y, x);
41e49280 168 VM_VALIDATE_CONS (x, "set-cdr!");
a80be762 169 SCM_SETCDR (x, y);
60ed31d2 170 NEXT;
a98cef7e
KN		 171}
172
a80be762
KN		 173\f
174/*
175 * Numeric relational tests
176 */
177
178#undef REL
b2b33168
AW		 179#define REL(crel,srel) \
180 { \
181 ARGS2 (x, y); \
182 if (SCM_I_INUMP (x) && SCM_I_INUMP (y)) \
183 RETURN (scm_from_bool (((scm_t_signed_bits) SCM_UNPACK (x)) \
184 crel ((scm_t_signed_bits) SCM_UNPACK (y)))); \
185 SYNC_REGISTER (); \
186 RETURN (srel (x, y)); \
187 }
a80be762 188
9348168e 189VM_DEFINE_FUNCTION (147, ee, "ee?", 2)
a80be762
KN		 190{
191 REL (==, scm_num_eq_p);
192}
193
9348168e 194VM_DEFINE_FUNCTION (148, lt, "lt?", 2)
a80be762
KN		 195{
196 REL (<, scm_less_p);
197}
198
9348168e 199VM_DEFINE_FUNCTION (149, le, "le?", 2)
a80be762
KN		 200{
201 REL (<=, scm_leq_p);
202}
203
9348168e 204VM_DEFINE_FUNCTION (150, gt, "gt?", 2)
a80be762
KN		 205{
206 REL (>, scm_gr_p);
207}
208
9348168e 209VM_DEFINE_FUNCTION (151, ge, "ge?", 2)
a80be762
KN		 210{
211 REL (>=, scm_geq_p);
212}
213
214\f
215/*
216 * Numeric functions
217 */
218
e78d4bf9 219/* The maximum/minimum tagged integers. */
0c57673a
LC		 220#undef INUM_MAX
221#undef INUM_MIN
e78d4bf9
LC		 222#define INUM_MAX (INTPTR_MAX - 1)
223#define INUM_MIN (INTPTR_MIN + scm_tc2_int)
224
a80be762
KN		 225#undef FUNC2
226#define FUNC2(CFUNC,SFUNC) \
227{ \
d8eeb67c 228 ARGS2 (x, y); \
2d80426a 229 if (SCM_I_INUMP (x) && SCM_I_INUMP (y)) \
a80be762 230 { \
c0ee3245 231 scm_t_int64 n = SCM_I_INUM (x) CFUNC SCM_I_INUM (y);\
a80be762 232 if (SCM_FIXABLE (n)) \
2d80426a 233 RETURN (SCM_I_MAKINUM (n)); \
a80be762 234 } \
b2642276 235 SYNC_REGISTER (); \
a80be762
KN		 236 RETURN (SFUNC (x, y)); \
237}
238
0c57673a
LC		 239/* Assembly tagged integer arithmetic routines. This code uses the
240 `asm goto' feature introduced in GCC 4.5. */
241
242#if defined __x86_64__ && SCM_GNUC_PREREQ (4, 5)
243
244/* The macros below check the CPU's overflow flag to improve fixnum
245 arithmetic. The %rcx register is explicitly clobbered because `asm
246 goto' can't have outputs, in which case the `r' constraint could be
247 used to let the register allocator choose a register.
248
249 TODO: Use `cold' label attribute in GCC 4.6.
250 http://gcc.gnu.org/ml/gcc-patches/2010-10/msg01777.html */
251
252# define ASM_ADD(x, y) \
253 { \
254 asm volatile goto ("mov %1, %%rcx; " \
255 "test %[tag], %%cl; je %l[slow_add]; " \
256 "test %[tag], %0; je %l[slow_add]; " \
257 "add %0, %%rcx; jo %l[slow_add]; " \
258 "sub %[tag], %%rcx; " \
259 "mov %%rcx, (%[vsp])\n" \
260 : /* no outputs */ \
261 : "r" (x), "r" (y), \
262 [vsp] "r" (sp), [tag] "i" (scm_tc2_int) \
263 : "rcx", "memory" \
264 : slow_add); \
265 NEXT; \
266 } \
267 slow_add: \
268 do { } while (0)
269
270# define ASM_SUB(x, y) \
271 { \
272 asm volatile goto ("mov %0, %%rcx; " \
273 "test %[tag], %%cl; je %l[slow_sub]; " \
274 "test %[tag], %1; je %l[slow_sub]; " \
275 "sub %1, %%rcx; jo %l[slow_sub]; " \
276 "add %[tag], %%rcx; " \
277 "mov %%rcx, (%[vsp])\n" \
278 : /* no outputs */ \
279 : "r" (x), "r" (y), \
280 [vsp] "r" (sp), [tag] "i" (scm_tc2_int) \
281 : "rcx", "memory" \
282 : slow_sub); \
283 NEXT; \
284 } \
285 slow_sub: \
286 do { } while (0)
287
288#endif
289
290
9348168e 291VM_DEFINE_FUNCTION (152, add, "add", 2)
a80be762 292{
0c57673a 293#ifndef ASM_ADD
a80be762 294 FUNC2 (+, scm_sum);
0c57673a
LC		 295#else
296 ARGS2 (x, y);
297 ASM_ADD (x, y);
298 SYNC_REGISTER ();
299 RETURN (scm_sum (x, y));
300#endif
a80be762
KN		 301}
302
9348168e 303VM_DEFINE_FUNCTION (153, add1, "add1", 1)
7382f23e
AW		 304{
305 ARGS1 (x);
e78d4bf9
LC		 306
307 /* Check for overflow. */
b2b33168 308 if (SCM_LIKELY ((scm_t_intptr) SCM_UNPACK (x) < INUM_MAX))
7382f23e 309 {
e78d4bf9
LC		 310 SCM result;
311
312 /* Add the integers without untagging. */
b2b33168
AW		 313 result = SCM_PACK ((scm_t_intptr) SCM_UNPACK (x)
314 + (scm_t_intptr) SCM_UNPACK (SCM_I_MAKINUM (1))
e78d4bf9
LC		 315 - scm_tc2_int);
316
317 if (SCM_LIKELY (SCM_I_INUMP (result)))
318 RETURN (result);
7382f23e 319 }
e78d4bf9 320
7382f23e
AW		 321 SYNC_REGISTER ();
322 RETURN (scm_sum (x, SCM_I_MAKINUM (1)));
323}
324
9348168e 325VM_DEFINE_FUNCTION (154, sub, "sub", 2)
a80be762 326{
0c57673a 327#ifndef ASM_SUB
a80be762 328 FUNC2 (-, scm_difference);
0c57673a
LC		 329#else
330 ARGS2 (x, y);
331 ASM_SUB (x, y);
332 SYNC_REGISTER ();
333 RETURN (scm_difference (x, y));
334#endif
a80be762
KN		 335}
336
9348168e 337VM_DEFINE_FUNCTION (155, sub1, "sub1", 1)
7382f23e
AW		 338{
339 ARGS1 (x);
e78d4bf9
LC		 340
341 /* Check for underflow. */
b2b33168 342 if (SCM_LIKELY ((scm_t_intptr) SCM_UNPACK (x) > INUM_MIN))
7382f23e 343 {
e78d4bf9
LC		 344 SCM result;
345
346 /* Substract the integers without untagging. */
b2b33168
AW		 347 result = SCM_PACK ((scm_t_intptr) SCM_UNPACK (x)
348 - (scm_t_intptr) SCM_UNPACK (SCM_I_MAKINUM (1))
e78d4bf9
LC		 349 + scm_tc2_int);
350
351 if (SCM_LIKELY (SCM_I_INUMP (result)))
352 RETURN (result);
7382f23e 353 }
e78d4bf9 354
7382f23e
AW		 355 SYNC_REGISTER ();
356 RETURN (scm_difference (x, SCM_I_MAKINUM (1)));
357}
358
0c57673a
LC		 359# undef ASM_ADD
360# undef ASM_SUB
361
9348168e 362VM_DEFINE_FUNCTION (156, mul, "mul", 2)
a80be762
KN		 363{
364 ARGS2 (x, y);
1865ad56 365 SYNC_REGISTER ();
a80be762
KN		 366 RETURN (scm_product (x, y));
367}
368
9348168e 369VM_DEFINE_FUNCTION (157, div, "div", 2)
a80be762
KN		 370{
371 ARGS2 (x, y);
1865ad56 372 SYNC_REGISTER ();
a80be762
KN		 373 RETURN (scm_divide (x, y));
374}
375
9348168e 376VM_DEFINE_FUNCTION (158, quo, "quo", 2)
a80be762
KN		 377{
378 ARGS2 (x, y);
1865ad56 379 SYNC_REGISTER ();
a80be762
KN		 380 RETURN (scm_quotient (x, y));
381}
382
9348168e 383VM_DEFINE_FUNCTION (159, rem, "rem", 2)
a80be762
KN		 384{
385 ARGS2 (x, y);
1865ad56 386 SYNC_REGISTER ();
a80be762
KN		 387 RETURN (scm_remainder (x, y));
388}
389
9348168e 390VM_DEFINE_FUNCTION (160, mod, "mod", 2)
a80be762
KN		 391{
392 ARGS2 (x, y);
1865ad56 393 SYNC_REGISTER ();
a80be762
KN		 394 RETURN (scm_modulo (x, y));
395}
396
9348168e 397VM_DEFINE_FUNCTION (161, ash, "ash", 2)
b10d9330
AW		 398{
399 ARGS2 (x, y);
400 if (SCM_I_INUMP (x) && SCM_I_INUMP (y))
401 {
402 if (SCM_I_INUM (y) < 0)
8ecd1943 403 /* Right shift, will be a fixnum. */
b10d9330 404 RETURN (SCM_I_MAKINUM (SCM_I_INUM (x) >> -SCM_I_INUM (y)));
8ecd1943
AW		 405 else
406 /* Left shift. See comments in scm_ash. */
407 {
e25f3727 408 scm_t_signed_bits nn, bits_to_shift;
8ecd1943
AW		 409
410 nn = SCM_I_INUM (x);
411 bits_to_shift = SCM_I_INUM (y);
412
413 if (bits_to_shift < SCM_I_FIXNUM_BIT-1
e25f3727 414 && ((scm_t_bits)
8ecd1943
AW		 415 (SCM_SRS (nn, (SCM_I_FIXNUM_BIT-1 - bits_to_shift)) + 1)
416 <= 1))
417 RETURN (SCM_I_MAKINUM (nn << bits_to_shift));
418 /* fall through */
419 }
b10d9330
AW		 420 /* fall through */
421 }
422 SYNC_REGISTER ();
423 RETURN (scm_ash (x, y));
424}
425
9348168e 426VM_DEFINE_FUNCTION (162, logand, "logand", 2)
b10d9330
AW		 427{
428 ARGS2 (x, y);
429 if (SCM_I_INUMP (x) && SCM_I_INUMP (y))
430 RETURN (SCM_I_MAKINUM (SCM_I_INUM (x) & SCM_I_INUM (y)));
431 SYNC_REGISTER ();
432 RETURN (scm_logand (x, y));
433}
434
9348168e 435VM_DEFINE_FUNCTION (163, logior, "logior", 2)
b10d9330
AW		 436{
437 ARGS2 (x, y);
438 if (SCM_I_INUMP (x) && SCM_I_INUMP (y))
439 RETURN (SCM_I_MAKINUM (SCM_I_INUM (x) | SCM_I_INUM (y)));
440 SYNC_REGISTER ();
441 RETURN (scm_logior (x, y));
442}
443
9348168e 444VM_DEFINE_FUNCTION (164, logxor, "logxor", 2)
b10d9330
AW		 445{
446 ARGS2 (x, y);
447 if (SCM_I_INUMP (x) && SCM_I_INUMP (y))
448 RETURN (SCM_I_MAKINUM (SCM_I_INUM (x) ^ SCM_I_INUM (y)));
449 SYNC_REGISTER ();
450 RETURN (scm_logxor (x, y));
451}
452
1e4b834a 453\f
d5a4f51f
AW		 454/*
455 * Strings
456 */
457
5ddd9645 458VM_DEFINE_FUNCTION (165, string_length, "string-length", 1)
d5a4f51f
AW		 459{
460 ARGS1 (str);
461 if (SCM_LIKELY (scm_is_string (str)))
462 RETURN (SCM_I_MAKINUM (scm_i_string_length (str)));
463 else
464 {
465 SYNC_REGISTER ();
466 RETURN (scm_string_length (str));
467 }
468}
469
5ddd9645 470VM_DEFINE_FUNCTION (166, string_ref, "string-ref", 2)
d5a4f51f
AW		 471{
472 scm_t_signed_bits i = 0;
473 ARGS2 (str, idx);
474 if (SCM_LIKELY (scm_is_string (str)
475 && SCM_I_INUMP (idx)
476 && ((i = SCM_I_INUM (idx)) >= 0)
477 && i < scm_i_string_length (str)))
478 RETURN (SCM_MAKE_CHAR (scm_i_string_ref (str, i)));
479 else
480 {
481 SYNC_REGISTER ();
482 RETURN (scm_string_ref (str, idx));
483 }
484}
485
486/* No string-set! instruction, as there is no good fast path there. */
487
488\f
1e4b834a 489/*
827dc8dc 490 * Vectors and arrays
1e4b834a 491 */
aec4a84a 492
5ddd9645 493VM_DEFINE_FUNCTION (167, vector_length, "vector-length", 1)
d5a4f51f
AW		 494{
495 ARGS1 (vect);
496 if (SCM_LIKELY (SCM_I_IS_VECTOR (vect)))
497 RETURN (SCM_I_MAKINUM (SCM_I_VECTOR_LENGTH (vect)));
498 else
499 {
500 SYNC_REGISTER ();
501 RETURN (scm_vector_length (vect));
502 }
503}
504
5ddd9645 505VM_DEFINE_FUNCTION (168, vector_ref, "vector-ref", 2)
d6f1ce3d 506{
e25f3727 507 scm_t_signed_bits i = 0;
d6f1ce3d 508 ARGS2 (vect, idx);
7b702b53 509 if (SCM_LIKELY (SCM_I_IS_NONWEAK_VECTOR (vect)
d6f1ce3d
AW		 510 && SCM_I_INUMP (idx)
511 && ((i = SCM_I_INUM (idx)) >= 0)
512 && i < SCM_I_VECTOR_LENGTH (vect)))
513 RETURN (SCM_I_VECTOR_ELTS (vect)[i]);
514 else
9b29d607
AW		 515 {
516 SYNC_REGISTER ();
517 RETURN (scm_vector_ref (vect, idx));
518 }
d6f1ce3d
AW		 519}
520
5ddd9645 521VM_DEFINE_INSTRUCTION (169, vector_set, "vector-set", 0, 3, 0)
d6f1ce3d 522{
e25f3727 523 scm_t_signed_bits i = 0;
d6f1ce3d 524 SCM vect, idx, val;
eae2438d 525 POP3 (val, idx, vect);
7b702b53 526 if (SCM_LIKELY (SCM_I_IS_NONWEAK_VECTOR (vect)
d6f1ce3d
AW		 527 && SCM_I_INUMP (idx)
528 && ((i = SCM_I_INUM (idx)) >= 0)
529 && i < SCM_I_VECTOR_LENGTH (vect)))
530 SCM_I_VECTOR_WELTS (vect)[i] = val;
531 else
9b29d607
AW		 532 {
533 SYNC_REGISTER ();
534 scm_vector_set_x (vect, idx, val);
535 }
d6f1ce3d
AW		 536 NEXT;
537}
538
5ddd9645 539VM_DEFINE_INSTRUCTION (170, make_array, "make-array", 3, -1, 1)
827dc8dc
AW		 540{
541 scm_t_uint32 len;
542 SCM shape, ret;
543
544 len = FETCH ();
545 len = (len << 8) + FETCH ();
546 len = (len << 8) + FETCH ();
547 POP (shape);
548 SYNC_REGISTER ();
384dce46 549 PRE_CHECK_UNDERFLOW (len);
827dc8dc
AW		 550 ret = scm_from_contiguous_array (shape, sp - len + 1, len);
551 DROPN (len);
552 PUSH (ret);
553 NEXT;
554}
555
556\f
557/*
558 * Structs
559 */
41e49280 560#define VM_VALIDATE_STRUCT(obj, proc) \
53bdfcf0 561 VM_ASSERT (SCM_STRUCTP (obj), vm_error_not_a_pair (proc, obj))
827dc8dc 562
5ddd9645 563VM_DEFINE_FUNCTION (171, struct_p, "struct?", 1)
827dc8dc
AW		 564{
565 ARGS1 (obj);
566 RETURN (scm_from_bool (SCM_STRUCTP (obj)));
567}
568
5ddd9645 569VM_DEFINE_FUNCTION (172, struct_vtable, "struct-vtable", 1)
827dc8dc
AW		 570{
571 ARGS1 (obj);
41e49280 572 VM_VALIDATE_STRUCT (obj, "struct_vtable");
827dc8dc
AW		 573 RETURN (SCM_STRUCT_VTABLE (obj));
574}
575
5ddd9645 576VM_DEFINE_INSTRUCTION (173, make_struct, "make-struct", 2, -1, 1)
827dc8dc
AW		 577{
578 unsigned h = FETCH ();
579 unsigned l = FETCH ();
9a974fd3
AW		 580 scm_t_bits n = ((h << 8U) + l);
581 SCM vtable = sp[-(n - 1)];
582 const SCM *inits = sp - n + 2;
583 SCM ret;
827dc8dc 584
9823fd39
LC		 585 SYNC_REGISTER ();
586
827dc8dc
AW		 587 if (SCM_LIKELY (SCM_STRUCTP (vtable)
588 && SCM_VTABLE_FLAG_IS_SET (vtable, SCM_VTABLE_FLAG_SIMPLE)
9a974fd3
AW		 589 && (SCM_STRUCT_DATA_REF (vtable, scm_vtable_index_size) + 1
590 == n)
591 && !SCM_VTABLE_INSTANCE_FINALIZER (vtable)))
827dc8dc 592 {
9a974fd3
AW		 593 /* Verily, we are making a simple struct with the right number of
594 initializers, and no finalizer. */
595 ret = scm_words ((scm_t_bits)SCM_STRUCT_DATA (vtable) | scm_tc3_struct,
596 n + 1);
597 SCM_SET_CELL_WORD_1 (ret, (scm_t_bits)SCM_CELL_OBJECT_LOC (ret, 2));
598 memcpy (SCM_STRUCT_DATA (ret), inits, (n - 1) * sizeof (SCM));
827dc8dc 599 }
9a974fd3
AW		 600 else
601 ret = scm_c_make_structv (vtable, 0, n - 1, (scm_t_bits *) inits);
602
c99865c1 603 DROPN (n);
9a974fd3 604 PUSH (ret);
827dc8dc 605
9a974fd3 606 NEXT;
827dc8dc
AW		 607}
608
5ddd9645 609VM_DEFINE_FUNCTION (174, struct_ref, "struct-ref", 2)
827dc8dc
AW		 610{
611 ARGS2 (obj, pos);
612
613 if (SCM_LIKELY (SCM_STRUCTP (obj)
614 && SCM_STRUCT_VTABLE_FLAG_IS_SET (obj,
615 SCM_VTABLE_FLAG_SIMPLE)
616 && SCM_I_INUMP (pos)))
617 {
618 SCM vtable;
619 scm_t_bits index, len;
620
e25f3727
AW		 621 /* True, an inum is a signed value, but cast to unsigned it will
622 certainly be more than the length, so we will fall through if
623 index is negative. */
827dc8dc
AW		 624 index = SCM_I_INUM (pos);
625 vtable = SCM_STRUCT_VTABLE (obj);
626 len = SCM_STRUCT_DATA_REF (vtable, scm_vtable_index_size);
627
628 if (SCM_LIKELY (index < len))
629 {
630 scm_t_bits *data = SCM_STRUCT_DATA (obj);
631 RETURN (SCM_PACK (data[index]));
632 }
633 }
634
9823fd39 635 SYNC_REGISTER ();
827dc8dc
AW		 636 RETURN (scm_struct_ref (obj, pos));
637}
638
5ddd9645 639VM_DEFINE_FUNCTION (175, struct_set, "struct-set", 3)
827dc8dc
AW		 640{
641 ARGS3 (obj, pos, val);
642
643 if (SCM_LIKELY (SCM_STRUCTP (obj)
644 && SCM_STRUCT_VTABLE_FLAG_IS_SET (obj,
645 SCM_VTABLE_FLAG_SIMPLE)
646 && SCM_STRUCT_VTABLE_FLAG_IS_SET (obj,
647 SCM_VTABLE_FLAG_SIMPLE_RW)
648 && SCM_I_INUMP (pos)))
649 {
650 SCM vtable;
651 scm_t_bits index, len;
652
e25f3727 653 /* See above regarding index being >= 0. */
827dc8dc
AW		 654 index = SCM_I_INUM (pos);
655 vtable = SCM_STRUCT_VTABLE (obj);
656 len = SCM_STRUCT_DATA_REF (vtable, scm_vtable_index_size);
657 if (SCM_LIKELY (index < len))
658 {
659 scm_t_bits *data = SCM_STRUCT_DATA (obj);
660 data[index] = SCM_UNPACK (val);
661 RETURN (val);
662 }
663 }
664
9823fd39 665 SYNC_REGISTER ();
827dc8dc
AW		 666 RETURN (scm_struct_set_x (obj, pos, val));
667}
668
669\f
670/*
671 * GOOPS support
672 */
5ddd9645 673VM_DEFINE_FUNCTION (176, class_of, "class-of", 1)
827dc8dc
AW		 674{
675 ARGS1 (obj);
1a461493
AW		 676 if (SCM_INSTANCEP (obj))
677 RETURN (SCM_CLASS_OF (obj));
678 SYNC_REGISTER ();
679 RETURN (scm_class_of (obj));
827dc8dc
AW		 680}
681
e25f3727 682/* FIXME: No checking whatsoever. */
5ddd9645 683VM_DEFINE_FUNCTION (177, slot_ref, "slot-ref", 2)
827dc8dc
AW		 684{
685 size_t slot;
686 ARGS2 (instance, idx);
687 slot = SCM_I_INUM (idx);
688 RETURN (SCM_PACK (SCM_STRUCT_DATA (instance) [slot]));
689}
690
e25f3727 691/* FIXME: No checking whatsoever. */
5ddd9645 692VM_DEFINE_INSTRUCTION (178, slot_set, "slot-set", 0, 3, 0)
827dc8dc
AW		 693{
694 SCM instance, idx, val;
695 size_t slot;
eae2438d 696 POP3 (val, idx, instance);
827dc8dc
AW		 697 slot = SCM_I_INUM (idx);
698 SCM_STRUCT_DATA (instance) [slot] = SCM_UNPACK (val);
699 NEXT;
700}
701
702\f
703/*
704 * Bytevectors
705 */
41e49280 706#define VM_VALIDATE_BYTEVECTOR(x, proc) \
53bdfcf0 707 VM_ASSERT (SCM_BYTEVECTOR_P (x), vm_error_not_a_bytevector (proc, x))
e6eb2467
AW		 708
709#define BV_REF_WITH_ENDIANNESS(stem, fn_stem) \
710{ \
711 SCM endianness; \
712 POP (endianness); \
713 if (scm_is_eq (endianness, scm_i_native_endianness)) \
714 goto VM_LABEL (bv_##stem##_native_ref); \
715 { \
716 ARGS2 (bv, idx); \
9823fd39 717 SYNC_REGISTER (); \
e6eb2467
AW		 718 RETURN (scm_bytevector_##fn_stem##_ref (bv, idx, endianness)); \
719 } \
720}
721
daccfef4
LC		 722/* Return true (non-zero) if PTR has suitable alignment for TYPE. */
723#define ALIGNED_P(ptr, type) \
1002c774 724 ((scm_t_uintptr) (ptr) % alignof_type (type) == 0)
daccfef4 725
5ddd9645 726VM_DEFINE_FUNCTION (179, bv_u16_ref, "bv-u16-ref", 3)
e6eb2467 727BV_REF_WITH_ENDIANNESS (u16, u16)
5ddd9645 728VM_DEFINE_FUNCTION (180, bv_s16_ref, "bv-s16-ref", 3)
e6eb2467 729BV_REF_WITH_ENDIANNESS (s16, s16)
5ddd9645 730VM_DEFINE_FUNCTION (181, bv_u32_ref, "bv-u32-ref", 3)
e6eb2467 731BV_REF_WITH_ENDIANNESS (u32, u32)
5ddd9645 732VM_DEFINE_FUNCTION (182, bv_s32_ref, "bv-s32-ref", 3)
e6eb2467 733BV_REF_WITH_ENDIANNESS (s32, s32)
5ddd9645 734VM_DEFINE_FUNCTION (183, bv_u64_ref, "bv-u64-ref", 3)
e6eb2467 735BV_REF_WITH_ENDIANNESS (u64, u64)
5ddd9645 736VM_DEFINE_FUNCTION (184, bv_s64_ref, "bv-s64-ref", 3)
e6eb2467 737BV_REF_WITH_ENDIANNESS (s64, s64)
5ddd9645 738VM_DEFINE_FUNCTION (185, bv_f32_ref, "bv-f32-ref", 3)
e6eb2467 739BV_REF_WITH_ENDIANNESS (f32, ieee_single)
5ddd9645 740VM_DEFINE_FUNCTION (186, bv_f64_ref, "bv-f64-ref", 3)
e6eb2467
AW		 741BV_REF_WITH_ENDIANNESS (f64, ieee_double)
742
743#undef BV_REF_WITH_ENDIANNESS
744
9823fd39
LC		 745#define BV_FIXABLE_INT_REF(stem, fn_stem, type, size) \
746{ \
e25f3727 747 scm_t_signed_bits i; \
daccfef4 748 const scm_t_ ## type *int_ptr; \
9823fd39 749 ARGS2 (bv, idx); \
daccfef4 750 \
41e49280 751 VM_VALIDATE_BYTEVECTOR (bv, "bv-" #stem "-ref"); \
daccfef4
LC		 752 i = SCM_I_INUM (idx); \
753 int_ptr = (scm_t_ ## type *) (SCM_BYTEVECTOR_CONTENTS (bv) + i); \
754 \
9823fd39 755 if (SCM_LIKELY (SCM_I_INUMP (idx) \
daccfef4 756 && (i >= 0) \
9823fd39 757 && (i + size <= SCM_BYTEVECTOR_LENGTH (bv)) \
daccfef4
LC		 758 && (ALIGNED_P (int_ptr, scm_t_ ## type)))) \
759 RETURN (SCM_I_MAKINUM (*int_ptr)); \
9823fd39
LC		 760 else \
761 { \
762 SYNC_REGISTER (); \
763 RETURN (scm_bytevector_ ## fn_stem ## _ref (bv, idx)); \
764 } \
765}
766
767#define BV_INT_REF(stem, type, size) \
768{ \
e25f3727 769 scm_t_signed_bits i; \
daccfef4 770 const scm_t_ ## type *int_ptr; \
9823fd39 771 ARGS2 (bv, idx); \
daccfef4 772 \
41e49280 773 VM_VALIDATE_BYTEVECTOR (bv, "bv-" #stem "-ref"); \
daccfef4
LC		 774 i = SCM_I_INUM (idx); \
775 int_ptr = (scm_t_ ## type *) (SCM_BYTEVECTOR_CONTENTS (bv) + i); \
776 \
9823fd39 777 if (SCM_LIKELY (SCM_I_INUMP (idx) \
daccfef4 778 && (i >= 0) \
9823fd39 779 && (i + size <= SCM_BYTEVECTOR_LENGTH (bv)) \
daccfef4
LC		 780 && (ALIGNED_P (int_ptr, scm_t_ ## type)))) \
781 { \
782 scm_t_ ## type x = *int_ptr; \
9823fd39
LC		 783 if (SCM_FIXABLE (x)) \
784 RETURN (SCM_I_MAKINUM (x)); \
785 else \
786 { \
787 SYNC_REGISTER (); \
788 RETURN (scm_from_ ## type (x)); \
789 } \
790 } \
791 else \
792 { \
793 SYNC_REGISTER (); \
794 RETURN (scm_bytevector_ ## stem ## _native_ref (bv, idx)); \
795 } \
796}
797
798#define BV_FLOAT_REF(stem, fn_stem, type, size) \
799{ \
e25f3727 800 scm_t_signed_bits i; \
daccfef4 801 const type *float_ptr; \
9823fd39 802 ARGS2 (bv, idx); \
daccfef4 803 \
41e49280 804 VM_VALIDATE_BYTEVECTOR (bv, "bv-" #stem "-ref"); \
daccfef4
LC		 805 i = SCM_I_INUM (idx); \
806 float_ptr = (type *) (SCM_BYTEVECTOR_CONTENTS (bv) + i); \
807 \
9823fd39
LC		 808 SYNC_REGISTER (); \
809 if (SCM_LIKELY (SCM_I_INUMP (idx) \
daccfef4 810 && (i >= 0) \
9823fd39 811 && (i + size <= SCM_BYTEVECTOR_LENGTH (bv)) \
daccfef4
LC		 812 && (ALIGNED_P (float_ptr, type)))) \
813 RETURN (scm_from_double (*float_ptr)); \
9823fd39
LC		 814 else \
815 RETURN (scm_bytevector_ ## fn_stem ## _native_ref (bv, idx)); \
e6eb2467
AW		 816}
817
5ddd9645 818VM_DEFINE_FUNCTION (187, bv_u8_ref, "bv-u8-ref", 2)
e6eb2467 819BV_FIXABLE_INT_REF (u8, u8, uint8, 1)
5ddd9645 820VM_DEFINE_FUNCTION (188, bv_s8_ref, "bv-s8-ref", 2)
e6eb2467 821BV_FIXABLE_INT_REF (s8, s8, int8, 1)
5ddd9645 822VM_DEFINE_FUNCTION (189, bv_u16_native_ref, "bv-u16-native-ref", 2)
e6eb2467 823BV_FIXABLE_INT_REF (u16, u16_native, uint16, 2)
5ddd9645 824VM_DEFINE_FUNCTION (190, bv_s16_native_ref, "bv-s16-native-ref", 2)
e6eb2467 825BV_FIXABLE_INT_REF (s16, s16_native, int16, 2)
5ddd9645 826VM_DEFINE_FUNCTION (191, bv_u32_native_ref, "bv-u32-native-ref", 2)
dddacb23
LC		 827#if SIZEOF_VOID_P > 4
828BV_FIXABLE_INT_REF (u32, u32_native, uint32, 4)
829#else
e6eb2467 830BV_INT_REF (u32, uint32, 4)
dddacb23 831#endif
5ddd9645 832VM_DEFINE_FUNCTION (192, bv_s32_native_ref, "bv-s32-native-ref", 2)
dddacb23
LC		 833#if SIZEOF_VOID_P > 4
834BV_FIXABLE_INT_REF (s32, s32_native, int32, 4)
835#else
e6eb2467 836BV_INT_REF (s32, int32, 4)
dddacb23 837#endif
5ddd9645 838VM_DEFINE_FUNCTION (193, bv_u64_native_ref, "bv-u64-native-ref", 2)
e6eb2467 839BV_INT_REF (u64, uint64, 8)
5ddd9645 840VM_DEFINE_FUNCTION (194, bv_s64_native_ref, "bv-s64-native-ref", 2)
e6eb2467 841BV_INT_REF (s64, int64, 8)
5ddd9645 842VM_DEFINE_FUNCTION (195, bv_f32_native_ref, "bv-f32-native-ref", 2)
e6eb2467 843BV_FLOAT_REF (f32, ieee_single, float, 4)
5ddd9645 844VM_DEFINE_FUNCTION (196, bv_f64_native_ref, "bv-f64-native-ref", 2)
e6eb2467
AW		 845BV_FLOAT_REF (f64, ieee_double, double, 8)
846
847#undef BV_FIXABLE_INT_REF
848#undef BV_INT_REF
849#undef BV_FLOAT_REF
850
851
852
853#define BV_SET_WITH_ENDIANNESS(stem, fn_stem) \
854{ \
855 SCM endianness; \
856 POP (endianness); \
857 if (scm_is_eq (endianness, scm_i_native_endianness)) \
858 goto VM_LABEL (bv_##stem##_native_set); \
859 { \
eae2438d 860 SCM bv, idx, val; POP3 (val, idx, bv); \
ad301b6d 861 SYNC_REGISTER (); \
d6f1ce3d
AW		 862 scm_bytevector_##fn_stem##_set_x (bv, idx, val, endianness); \
863 NEXT; \
e6eb2467
AW		 864 } \
865}
866
5ddd9645 867VM_DEFINE_INSTRUCTION (197, bv_u16_set, "bv-u16-set", 0, 4, 0)
e6eb2467 868BV_SET_WITH_ENDIANNESS (u16, u16)
5ddd9645 869VM_DEFINE_INSTRUCTION (198, bv_s16_set, "bv-s16-set", 0, 4, 0)
e6eb2467 870BV_SET_WITH_ENDIANNESS (s16, s16)
5ddd9645 871VM_DEFINE_INSTRUCTION (199, bv_u32_set, "bv-u32-set", 0, 4, 0)
e6eb2467 872BV_SET_WITH_ENDIANNESS (u32, u32)
5ddd9645 873VM_DEFINE_INSTRUCTION (200, bv_s32_set, "bv-s32-set", 0, 4, 0)
e6eb2467 874BV_SET_WITH_ENDIANNESS (s32, s32)
5ddd9645 875VM_DEFINE_INSTRUCTION (201, bv_u64_set, "bv-u64-set", 0, 4, 0)
e6eb2467 876BV_SET_WITH_ENDIANNESS (u64, u64)
5ddd9645 877VM_DEFINE_INSTRUCTION (202, bv_s64_set, "bv-s64-set", 0, 4, 0)
e6eb2467 878BV_SET_WITH_ENDIANNESS (s64, s64)
5ddd9645 879VM_DEFINE_INSTRUCTION (203, bv_f32_set, "bv-f32-set", 0, 4, 0)
e6eb2467 880BV_SET_WITH_ENDIANNESS (f32, ieee_single)
5ddd9645 881VM_DEFINE_INSTRUCTION (204, bv_f64_set, "bv-f64-set", 0, 4, 0)
e6eb2467
AW		 882BV_SET_WITH_ENDIANNESS (f64, ieee_double)
883
884#undef BV_SET_WITH_ENDIANNESS
885
daccfef4
LC		 886#define BV_FIXABLE_INT_SET(stem, fn_stem, type, min, max, size) \
887{ \
e25f3727 888 scm_t_signed_bits i, j = 0; \
daccfef4
LC		 889 SCM bv, idx, val; \
890 scm_t_ ## type *int_ptr; \
891 \
eae2438d 892 POP3 (val, idx, bv); \
41e49280 893 VM_VALIDATE_BYTEVECTOR (bv, "bv-" #stem "-set"); \
daccfef4
LC		 894 i = SCM_I_INUM (idx); \
895 int_ptr = (scm_t_ ## type *) (SCM_BYTEVECTOR_CONTENTS (bv) + i); \
896 \
897 if (SCM_LIKELY (SCM_I_INUMP (idx) \
898 && (i >= 0) \
899 && (i + size <= SCM_BYTEVECTOR_LENGTH (bv)) \
900 && (ALIGNED_P (int_ptr, scm_t_ ## type)) \
901 && (SCM_I_INUMP (val)) \
902 && ((j = SCM_I_INUM (val)) >= min) \
903 && (j <= max))) \
904 *int_ptr = (scm_t_ ## type) j; \
905 else \
ad301b6d
AW		 906 { \
907 SYNC_REGISTER (); \
908 scm_bytevector_ ## fn_stem ## _set_x (bv, idx, val); \
909 } \
daccfef4
LC		 910 NEXT; \
911}
912
913#define BV_INT_SET(stem, type, size) \
914{ \
e25f3727 915 scm_t_signed_bits i = 0; \
daccfef4
LC		 916 SCM bv, idx, val; \
917 scm_t_ ## type *int_ptr; \
918 \
eae2438d 919 POP3 (val, idx, bv); \
41e49280 920 VM_VALIDATE_BYTEVECTOR (bv, "bv-" #stem "-set"); \
daccfef4
LC		 921 i = SCM_I_INUM (idx); \
922 int_ptr = (scm_t_ ## type *) (SCM_BYTEVECTOR_CONTENTS (bv) + i); \
923 \
924 if (SCM_LIKELY (SCM_I_INUMP (idx) \
925 && (i >= 0) \
926 && (i + size <= SCM_BYTEVECTOR_LENGTH (bv)) \
927 && (ALIGNED_P (int_ptr, scm_t_ ## type)))) \
928 *int_ptr = scm_to_ ## type (val); \
929 else \
ad301b6d
AW		 930 { \
931 SYNC_REGISTER (); \
932 scm_bytevector_ ## stem ## _native_set_x (bv, idx, val); \
933 } \
934 NEXT; \
daccfef4
LC		 935}
936
ad301b6d
AW		 937#define BV_FLOAT_SET(stem, fn_stem, type, size) \
938{ \
939 scm_t_signed_bits i = 0; \
940 SCM bv, idx, val; \
941 type *float_ptr; \
942 \
eae2438d 943 POP3 (val, idx, bv); \
ad301b6d
AW		 944 VM_VALIDATE_BYTEVECTOR (bv, "bv-" #stem "-set"); \
945 i = SCM_I_INUM (idx); \
946 float_ptr = (type *) (SCM_BYTEVECTOR_CONTENTS (bv) + i); \
947 \
948 if (SCM_LIKELY (SCM_I_INUMP (idx) \
949 && (i >= 0) \
950 && (i + size <= SCM_BYTEVECTOR_LENGTH (bv)) \
951 && (ALIGNED_P (float_ptr, type)))) \
952 *float_ptr = scm_to_double (val); \
953 else \
954 { \
955 SYNC_REGISTER (); \
956 scm_bytevector_ ## fn_stem ## _native_set_x (bv, idx, val); \
957 } \
958 NEXT; \
e6eb2467
AW		 959}
960
5ddd9645 961VM_DEFINE_INSTRUCTION (205, bv_u8_set, "bv-u8-set", 0, 3, 0)
e6eb2467 962BV_FIXABLE_INT_SET (u8, u8, uint8, 0, SCM_T_UINT8_MAX, 1)
5ddd9645 963VM_DEFINE_INSTRUCTION (206, bv_s8_set, "bv-s8-set", 0, 3, 0)
e6eb2467 964BV_FIXABLE_INT_SET (s8, s8, int8, SCM_T_INT8_MIN, SCM_T_INT8_MAX, 1)
5ddd9645 965VM_DEFINE_INSTRUCTION (207, bv_u16_native_set, "bv-u16-native-set", 0, 3, 0)
d6f1ce3d 966BV_FIXABLE_INT_SET (u16, u16_native, uint16, 0, SCM_T_UINT16_MAX, 2)
5ddd9645 967VM_DEFINE_INSTRUCTION (208, bv_s16_native_set, "bv-s16-native-set", 0, 3, 0)
d6f1ce3d 968BV_FIXABLE_INT_SET (s16, s16_native, int16, SCM_T_INT16_MIN, SCM_T_INT16_MAX, 2)
5ddd9645 969VM_DEFINE_INSTRUCTION (209, bv_u32_native_set, "bv-u32-native-set", 0, 3, 0)
dddacb23
LC		 970#if SIZEOF_VOID_P > 4
971BV_FIXABLE_INT_SET (u32, u32_native, uint32, 0, SCM_T_UINT32_MAX, 4)
972#else
e6eb2467 973BV_INT_SET (u32, uint32, 4)
dddacb23 974#endif
5ddd9645 975VM_DEFINE_INSTRUCTION (210, bv_s32_native_set, "bv-s32-native-set", 0, 3, 0)
dddacb23
LC		 976#if SIZEOF_VOID_P > 4
977BV_FIXABLE_INT_SET (s32, s32_native, int32, SCM_T_INT32_MIN, SCM_T_INT32_MAX, 4)
978#else
e6eb2467 979BV_INT_SET (s32, int32, 4)
dddacb23 980#endif
5ddd9645 981VM_DEFINE_INSTRUCTION (211, bv_u64_native_set, "bv-u64-native-set", 0, 3, 0)
e6eb2467 982BV_INT_SET (u64, uint64, 8)
5ddd9645 983VM_DEFINE_INSTRUCTION (212, bv_s64_native_set, "bv-s64-native-set", 0, 3, 0)
e6eb2467 984BV_INT_SET (s64, int64, 8)
5ddd9645 985VM_DEFINE_INSTRUCTION (213, bv_f32_native_set, "bv-f32-native-set", 0, 3, 0)
e6eb2467 986BV_FLOAT_SET (f32, ieee_single, float, 4)
5ddd9645 987VM_DEFINE_INSTRUCTION (214, bv_f64_native_set, "bv-f64-native-set", 0, 3, 0)
e6eb2467
AW		 988BV_FLOAT_SET (f64, ieee_double, double, 8)
989
990#undef BV_FIXABLE_INT_SET
991#undef BV_INT_SET
992#undef BV_FLOAT_SET
993
53e28ed9
AW		 994/*
995(defun renumber-ops ()
996 "start from top of buffer and renumber 'VM_DEFINE_FOO (\n' sequences"
997 (interactive "")
998 (save-excursion
827dc8dc 999 (let ((counter 127)) (goto-char (point-min))
53e28ed9
AW		 1000 (while (re-search-forward "^VM_DEFINE_[^ ]+ (\\([^,]+\\)," (point-max) t)
1001 (replace-match
1002 (number-to-string (setq counter (1+ counter)))
1003 t t nil 1)))))
1004*/
1e4b834a 1005
17e90c5e
KN		 1006/*
1007 Local Variables:
1008 c-file-style: "gnu"
1009 End:
1010*/
Unnamed repository; edit this file 'description' to name the repository.