tests/proto_ver2.res

   1 /*
   2  *
   3  * IPACX specific routines
   4  *
   5  * Author       Joerg Petersohn
   6  * Derived from hisax_isac.c, isac.c, hscx.c and others
   7  *
   8  * This software may be used and distributed according to the terms
   9  * of the GNU General Public License, incorporated herein by reference.
  10  *
  11  */
  12 #include <linux/kernel.h>
  13 #include <linux/config.h>
  14 #include <linux/init.h>
  15 #include <linux/workqueue.h>
  16 #include "hisax_if.h"
  17 #include "hisax.h"
  18 #include "isdnl1.h"
  19 #include "ipacx.h"
  20
  21 #define DBUSY_TIMER_VALUE 80
  22 #define TIMER3_VALUE      7000
  23 #define MAX_DFRAME_LEN_L1 300
  24 #define B_FIFO_SIZE       64
  25 #define D_FIFO_SIZE       32
  26 static spinlock_t ipacx_lock = SPIN_LOCK_UNLOCKED;
  27
  28 // ipacx interrupt mask values
  29 #define _MASK_IMASK     0x2E  // global mask
  30 #define _MASKB_IMASK    0x0B
  31 #define _MASKD_IMASK    0x03  // all on
  32
  33 //----------------------------------------------------------
  34 // local function declarations
  35 //----------------------------------------------------------
  36 static void ph_command(struct IsdnCardState *cs, unsigned int command);
  37 static inline void cic_int(struct IsdnCardState *cs);
  38 static void dch_l2l1(struct PStack *st, int pr, void *arg);
  39 static void dbusy_timer_handler(struct IsdnCardState *cs);
  40 static void ipacx_new_ph(struct IsdnCardState *cs);
  41 static void dch_bh(void *data);
  42 static void dch_sched_event(struct IsdnCardState *cs, int event);
  43 static void dch_empty_fifo(struct IsdnCardState *cs, int count);
  44 static void dch_fill_fifo(struct IsdnCardState *cs);
  45 static inline void dch_int(struct IsdnCardState *cs);
  46 static void __devinit dch_setstack(struct PStack *st, struct IsdnCardState *cs);
  47 static void __devinit dch_init(struct IsdnCardState *cs);
  48 static void bch_l2l1(struct PStack *st, int pr, void *arg);
  49 static void bch_empty_fifo(struct BCState *bcs, int count);
  50 static void bch_fill_fifo(struct BCState *bcs);
  51 static void bch_int(struct IsdnCardState *cs, u_char hscx);
  52 static void bch_mode(struct BCState *bcs, int mode, int bc);
  53 static void bch_close_state(struct BCState *bcs);
  54 static int bch_open_state(struct IsdnCardState *cs, struct BCState *bcs);
  55 static int bch_setstack(struct PStack *st, struct BCState *bcs);
  56 static void __devinit bch_init(struct IsdnCardState *cs, int hscx);
  57 static void __init clear_pending_ints(struct IsdnCardState *cs);
  58
  59 //----------------------------------------------------------
  60 // Issue Layer 1 command to chip
  61 //----------------------------------------------------------
  62 static void
  63 ph_command(struct IsdnCardState *cs, unsigned int command)
  64 {
  65         if (cs->debug &L1_DEB_ISAC)
  66                 debugl1(cs, "ph_command (%#x) in (%#x)", command,
  67                         cs->dc.isac.ph_state);
  68         cs->writeisac(cs, IPACX_CIX0, (command << 4) | 0x0E);
  69 }
  70
  71 //----------------------------------------------------------
  72 // Transceiver interrupt handler
  73 //----------------------------------------------------------
  74 static inline void
  75 cic_int(struct IsdnCardState *cs)
  76 {
  77         u_char event;
  78
  79         event = cs->readisac(cs, IPACX_CIR0) >> 4;
  80         if (cs->debug &L1_DEB_ISAC) debugl1(cs, "cic_int(event=%#x)", event);
  81   cs->dc.isac.ph_state = event;
  82   dch_sched_event(cs, D_L1STATECHANGE);
  83 }
  84
  85 //==========================================================
  86 // D channel functions
  87 //==========================================================
  88
  89 //----------------------------------------------------------
  90 // Command entry point
  91 //----------------------------------------------------------
  92 static void
  93 dch_l2l1(struct PStack *st, int pr, void *arg)
  94 {
  95         struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware;
  96         struct sk_buff *skb = arg;
  97   u_char cda1_cr, cda2_cr;
  98
  99         switch (pr) {
 100                 case (PH_DATA |REQUEST):
 101                         if (cs->debug &DEB_DLOG_HEX)     LogFrame(cs, skb->data, skb->len);
 102                         if (cs->debug &DEB_DLOG_VERBOSE) dlogframe(cs, skb, 0);
 103                         if (cs->tx_skb) {
 104                                 skb_queue_tail(&cs->sq, skb);
 105 #ifdef L2FRAME_DEBUG
 106                                 if (cs->debug &L1_DEB_LAPD) Logl2Frame(cs, skb, "PH_DATA Queued", 0);
 107 #endif
 108                         } else {
 109                                 cs->tx_skb = skb;
 110                                 cs->tx_cnt = 0;
 111 #ifdef L2FRAME_DEBUG
 112                                 if (cs->debug &L1_DEB_LAPD) Logl2Frame(cs, skb, "PH_DATA", 0);
 113 #endif
 114                                 dch_fill_fifo(cs);
 115                         }
 116                         break;
 117
 118                 case (PH_PULL |INDICATION):
 119                         if (cs->tx_skb) {
 120                                 if (cs->debug & L1_DEB_WARN)
 121                                         debugl1(cs, " l2l1 tx_skb exist this shouldn't happen");
 122                                 skb_queue_tail(&cs->sq, skb);
 123                                 break;
 124                         }
 125                         if (cs->debug & DEB_DLOG_HEX)     LogFrame(cs, skb->data, skb->len);
 126                         if (cs->debug & DEB_DLOG_VERBOSE) dlogframe(cs, skb, 0);
 127                         cs->tx_skb = skb;
 128                         cs->tx_cnt = 0;
 129 #ifdef L2FRAME_DEBUG
 130                         if (cs->debug & L1_DEB_LAPD) Logl2Frame(cs, skb, "PH_DATA_PULLED", 0);
 131 #endif
 132                         dch_fill_fifo(cs);
 133                         break;
 134
 135                 case (PH_PULL | REQUEST):
 136 #ifdef L2FRAME_DEBUG
 137                         if (cs->debug & L1_DEB_LAPD) debugl1(cs, "-> PH_REQUEST_PULL");
 138 #endif
 139                         if (!cs->tx_skb) {
 140                                 clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
 141                                 st->l2.l1l2(st, PH_PULL | CONFIRM, NULL);
 142                         } else
 143                                 set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
 144                         break;
 145
 146                 case (HW_RESET | REQUEST):
 147                 case (HW_ENABLE | REQUEST):
 148                         ph_command(cs, IPACX_CMD_TIM);
 149                         break;
 150
 151                 case (HW_INFO3 | REQUEST):
 152                         ph_command(cs, IPACX_CMD_AR8);
 153                         break;
 154
 155                 case (HW_TESTLOOP | REQUEST):
 156       cs->writeisac(cs, IPACX_CDA_TSDP10, 0x80); // Timeslot 0 is B1
 157       cs->writeisac(cs, IPACX_CDA_TSDP11, 0x81); // Timeslot 0 is B1
 158       cda1_cr = cs->readisac(cs, IPACX_CDA1_CR);
 159       cda2_cr = cs->readisac(cs, IPACX_CDA2_CR);
 160                         if ((long)arg &1) { // loop B1
 161         cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr |0x0a);
 162       }
 163       else {  // B1 off
 164         cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr &~0x0a);
 165       }
 166                         if ((long)arg &2) { // loop B2
 167         cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr |0x14);
 168       }
 169       else {  // B2 off
 170         cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr &~0x14);
 171       }
 172                         break;
 173
 174                 case (HW_DEACTIVATE | RESPONSE):
 175                         skb_queue_purge(&cs->rq);
 176                         skb_queue_purge(&cs->sq);
 177                         if (cs->tx_skb) {
 178                                 dev_kfree_skb_any(cs->tx_skb);
 179                                 cs->tx_skb = NULL;
 180                         }
 181                         if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
 182                                 del_timer(&cs->dbusytimer);
 183                         break;
 184
 185                 default:
 186                         if (cs->debug &L1_DEB_WARN) debugl1(cs, "dch_l2l1 unknown %04x", pr);
 187                         break;
 188         }
 189 }
 190
 191 //----------------------------------------------------------
 192 //----------------------------------------------------------
 193 static void
 194 dbusy_timer_handler(struct IsdnCardState *cs)
 195 {
 196         struct PStack *st;
 197         int     rbchd, stard;
 198
 199         if (test_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {
 200                 rbchd = cs->readisac(cs, IPACX_RBCHD);
 201                 stard = cs->readisac(cs, IPACX_STARD);
 202                 if (cs->debug)
 203       debugl1(cs, "D-Channel Busy RBCHD %02x STARD %02x", rbchd, stard);
 204                 if (!(stard &0x40)) { // D-Channel Busy
 205                         set_bit(FLG_L1_DBUSY, &cs->HW_Flags);
 206       for (st = cs->stlist; st; st = st->next) {
 207                                 st->l2.l1l2(st, PH_PAUSE | INDICATION, NULL); // flow control on
 208                         }
 209                 } else {
 210                         // seems we lost an interrupt; reset transceiver */
 211                         clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags);
 212                         if (cs->tx_skb) {
 213                                 dev_kfree_skb_any(cs->tx_skb);
 214                                 cs->tx_cnt = 0;
 215                                 cs->tx_skb = NULL;
 216                         } else {
 217                                 printk(KERN_WARNING "HiSax: ISAC D-Channel Busy no skb\n");
 218                                 debugl1(cs, "D-Channel Busy no skb");
 219                         }
 220                         cs->writeisac(cs, IPACX_CMDRD, 0x01); // Tx reset, generates XPR
 221                 }
 222         }
 223 }
 224
 225 //----------------------------------------------------------
 226 // L1 state machine intermediate layer to isdnl1 module
 227 //----------------------------------------------------------
 228 static void
 229 ipacx_new_ph(struct IsdnCardState *cs)
 230 {
 231         switch (cs->dc.isac.ph_state) {
 232                 case (IPACX_IND_RES):
 233                         ph_command(cs, IPACX_CMD_DI);
 234                         l1_msg(cs, HW_RESET | INDICATION, NULL);
 235                         break;
 236
 237                 case (IPACX_IND_DC):
 238                         l1_msg(cs, HW_DEACTIVATE | CONFIRM, NULL);
 239                         break;
 240
 241                 case (IPACX_IND_DR):
 242                         l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL);
 243                         break;
 244
 245                 case (IPACX_IND_PU):
 246                         l1_msg(cs, HW_POWERUP | CONFIRM, NULL);
 247                         break;
 248
 249                 case (IPACX_IND_RSY):
 250                         l1_msg(cs, HW_RSYNC | INDICATION, NULL);
 251                         break;
 252
 253                 case (IPACX_IND_AR):
 254                         l1_msg(cs, HW_INFO2 | INDICATION, NULL);
 255                         break;
 256
 257                 case (IPACX_IND_AI8):
 258                         l1_msg(cs, HW_INFO4_P8 | INDICATION, NULL);
 259                         break;
 260
 261                 case (IPACX_IND_AI10):
 262                         l1_msg(cs, HW_INFO4_P10 | INDICATION, NULL);
 263                         break;
 264
 265                 default:
 266                         break;
 267         }
 268 }
 269
 270 //----------------------------------------------------------
 271 // bottom half handler for D channel
 272 //----------------------------------------------------------
 273 static void
 274 dch_bh(void *data)
 275 {
 276         struct IsdnCardState *cs = data;
 277         struct PStack *st;
 278
 279         if (!cs) return;
 280
 281         if (test_and_clear_bit(D_CLEARBUSY, &cs->event)) {
 282                 if (cs->debug) debugl1(cs, "D-Channel Busy cleared");
 283                 for (st = cs->stlist; st; st = st->next) {
 284                         st->l2.l1l2(st, PH_PAUSE | CONFIRM, NULL);
 285                 }
 286         }
 287
 288         if (test_and_clear_bit(D_RCVBUFREADY, &cs->event)) {
 289                 DChannel_proc_rcv(cs);
 290   }
 291
 292         if (test_and_clear_bit(D_XMTBUFREADY, &cs->event)) {
 293                 DChannel_proc_xmt(cs);
 294   }
 295
 296         if (test_and_clear_bit(D_L1STATECHANGE, &cs->event)) {
 297     ipacx_new_ph(cs);
 298   }
 299 }
 300
 301 //----------------------------------------------------------
 302 // proceed with bottom half handler dch_bh()
 303 //----------------------------------------------------------
 304 static void
 305 dch_sched_event(struct IsdnCardState *cs, int event)
 306 {
 307         set_bit(event, &cs->event);
 308         schedule_work(&cs->work);
 309 }
 310
 311 //----------------------------------------------------------
 312 // Fill buffer from receive FIFO
 313 //----------------------------------------------------------
 314 static void
 315 dch_empty_fifo(struct IsdnCardState *cs, int count)
 316 {
 317         unsigned long flags;
 318         u_char *ptr;
 319
 320         if ((cs->debug &L1_DEB_ISAC) && !(cs->debug &L1_DEB_ISAC_FIFO))
 321                 debugl1(cs, "dch_empty_fifo()");
 322
 323   // message too large, remove
 324         if ((cs->rcvidx + count) >= MAX_DFRAME_LEN_L1) {
 325                 if (cs->debug &L1_DEB_WARN)
 326                         debugl1(cs, "dch_empty_fifo() incoming message too large");
 327           cs->writeisac(cs, IPACX_CMDRD, 0x80); // RMC
 328                 cs->rcvidx = 0;
 329                 return;
 330         }
 331
 332         ptr = cs->rcvbuf + cs->rcvidx;
 333         cs->rcvidx += count;
 334
 335         spin_lock_irqsave(&ipacx_lock, flags);
 336         cs->readisacfifo(cs, ptr, count);
 337         cs->writeisac(cs, IPACX_CMDRD, 0x80); // RMC
 338         spin_unlock_irqrestore(&ipacx_lock, flags);
 339
 340         if (cs->debug &L1_DEB_ISAC_FIFO) {
 341                 char *t = cs->dlog;
 342
 343                 t += sprintf(t, "dch_empty_fifo() cnt %d", count);
 344                 QuickHex(t, ptr, count);
 345                 debugl1(cs, cs->dlog);
 346         }
 347 }
 348
 349 //----------------------------------------------------------
 350 // Fill transmit FIFO
 351 //----------------------------------------------------------
 352 static void
 353 dch_fill_fifo(struct IsdnCardState *cs)
 354 {
 355         unsigned long flags;
 356         int count;
 357         u_char cmd, *ptr;
 358
 359         if ((cs->debug &L1_DEB_ISAC) && !(cs->debug &L1_DEB_ISAC_FIFO))
 360                 debugl1(cs, "dch_fill_fifo()");
 361
 362         if (!cs->tx_skb) return;
 363         count = cs->tx_skb->len;
 364         if (count <= 0) return;
 365
 366         if (count > D_FIFO_SIZE) {
 367                 count = D_FIFO_SIZE;
 368                 cmd   = 0x08; // XTF
 369         } else {
 370                 cmd   = 0x0A; // XTF | XME
 371         }
 372
 373         spin_lock_irqsave(&ipacx_lock, flags);
 374         ptr = cs->tx_skb->data;
 375         skb_pull(cs->tx_skb, count);
 376         cs->tx_cnt += count;
 377         cs->writeisacfifo(cs, ptr, count);
 378         cs->writeisac(cs, IPACX_CMDRD, cmd);
 379
 380   // set timeout for transmission contol
 381         if (test_and_set_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {
 382                 debugl1(cs, "dch_fill_fifo dbusytimer running");
 383                 del_timer(&cs->dbusytimer);
 384         }
 385         init_timer(&cs->dbusytimer);
 386         cs->dbusytimer.expires = jiffies + ((DBUSY_TIMER_VALUE * HZ)/1000);
 387         add_timer(&cs->dbusytimer);
 388         spin_unlock_irqrestore(&ipacx_lock, flags);
 389
 390         if (cs->debug &L1_DEB_ISAC_FIFO) {
 391                 char *t = cs->dlog;
 392
 393                 t += sprintf(t, "dch_fill_fifo() cnt %d", count);
 394                 QuickHex(t, ptr, count);
 395                 debugl1(cs, cs->dlog);
 396         }
 397 }
 398
 399 //----------------------------------------------------------
 400 // D channel interrupt handler
 401 //----------------------------------------------------------
 402 static inline void
 403 dch_int(struct IsdnCardState *cs)
 404 {
 405         struct sk_buff *skb;
 406         u_char istad, rstad;
 407         unsigned long flags;
 408         int count;
 409
 410         istad = cs->readisac(cs, IPACX_ISTAD);
 411
 412         if (istad &0x80) {  // RME
 413           rstad = cs->readisac(cs, IPACX_RSTAD);
 414                 if ((rstad &0xf0) != 0xa0) { // !(VFR && !RDO && CRC && !RAB)
 415                         if (!(rstad &0x80))
 416                                 if (cs->debug &L1_DEB_WARN)
 417           debugl1(cs, "dch_int(): invalid frame");
 418                         if ((rstad &0x40))
 419                                 if (cs->debug &L1_DEB_WARN)
 420           debugl1(cs, "dch_int(): RDO");
 421                         if (!(rstad &0x20))
 422                                 if (cs->debug &L1_DEB_WARN)
 423           debugl1(cs, "dch_int(): CRC error");
 424             cs->writeisac(cs, IPACX_CMDRD, 0x80);  // RMC
 425                 } else {  // received frame ok
 426                         count = cs->readisac(cs, IPACX_RBCLD);
 427       if (count) count--; // RSTAB is last byte
 428                         count &= D_FIFO_SIZE-1;
 429                         if (count == 0) count = D_FIFO_SIZE;
 430                         dch_empty_fifo(cs, count);
 431                         spin_lock_irqsave(&ipacx_lock, flags);
 432                         if ((count = cs->rcvidx) > 0) {
 433               cs->rcvidx = 0;
 434                                 if (!(skb = dev_alloc_skb(count)))
 435                                         printk(KERN_WARNING "HiSax dch_int(): receive out of memory\n");
 436                                 else {
 437                                         memcpy(skb_put(skb, count), cs->rcvbuf, count);
 438                                         skb_queue_tail(&cs->rq, skb);
 439                                 }
 440                         }
 441                         spin_unlock_irqrestore(&ipacx_lock, flags);
 442     }
 443           cs->rcvidx = 0;
 444                 dch_sched_event(cs, D_RCVBUFREADY);
 445         }
 446
 447         if (istad &0x40) {  // RPF
 448                 dch_empty_fifo(cs, D_FIFO_SIZE);
 449         }
 450
 451         if (istad &0x20) {  // RFO
 452                 if (cs->debug &L1_DEB_WARN) debugl1(cs, "dch_int(): RFO");
 453           cs->writeisac(cs, IPACX_CMDRD, 0x40); //RRES
 454         }
 455
 456   if (istad &0x10) {  // XPR
 457                 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
 458                         del_timer(&cs->dbusytimer);
 459                 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
 460                         dch_sched_event(cs, D_CLEARBUSY);
 461     if (cs->tx_skb) {
 462       if (cs->tx_skb->len) {
 463         dch_fill_fifo(cs);
 464         goto afterXPR;
 465       }
 466       else {
 467         dev_kfree_skb_irq(cs->tx_skb);
 468         cs->tx_skb = NULL;
 469         cs->tx_cnt = 0;
 470       }
 471     }
 472     if ((cs->tx_skb = skb_dequeue(&cs->sq))) {
 473       cs->tx_cnt = 0;
 474       dch_fill_fifo(cs);
 475     }
 476     else {
 477       dch_sched_event(cs, D_XMTBUFREADY);
 478     }
 479   }
 480   afterXPR:
 481
 482         if (istad &0x0C) {  // XDU or XMR
 483                 if (cs->debug &L1_DEB_WARN) debugl1(cs, "dch_int(): XDU");
 484           if (cs->tx_skb) {
 485             skb_push(cs->tx_skb, cs->tx_cnt); // retransmit
 486             cs->tx_cnt = 0;
 487                         dch_fill_fifo(cs);
 488                 } else {
 489                         printk(KERN_WARNING "HiSax: ISAC XDU no skb\n");
 490                         debugl1(cs, "ISAC XDU no skb");
 491                 }
 492   }
 493 }
 494
 495 //----------------------------------------------------------
 496 //----------------------------------------------------------
 497 static void __devinit
 498 dch_setstack(struct PStack *st, struct IsdnCardState *cs)
 499 {
 500         st->l1.l1hw = dch_l2l1;
 501 }
 502
 503 //----------------------------------------------------------
 504 //----------------------------------------------------------
 505 static void __devinit
 506 dch_init(struct IsdnCardState *cs)
 507 {
 508         printk(KERN_INFO "HiSax: IPACX ISDN driver v0.1.0\n");
 509
 510         INIT_WORK(&cs->work, dch_bh, cs);
 511         cs->setstack_d      = dch_setstack;
 512
 513         cs->dbusytimer.function = (void *) dbusy_timer_handler;
 514         cs->dbusytimer.data = (long) cs;
 515         init_timer(&cs->dbusytimer);
 516
 517   cs->writeisac(cs, IPACX_TR_CONF0, 0x00);  // clear LDD
 518   cs->writeisac(cs, IPACX_TR_CONF2, 0x00);  // enable transmitter
 519   cs->writeisac(cs, IPACX_MODED,    0xC9);  // transparent mode 0, RAC, stop/go
 520   cs->writeisac(cs, IPACX_MON_CR,   0x00);  // disable monitor channel
 521 }
 522
 523
 524 //==========================================================
 525 // B channel functions
 526 //==========================================================
 527
 528 //----------------------------------------------------------
 529 // Entry point for commands
 530 //----------------------------------------------------------
 531 static void
 532 bch_l2l1(struct PStack *st, int pr, void *arg)
 533 {
 534         struct sk_buff *skb = arg;
 535         unsigned long flags;
 536
 537         switch (pr) {
 538                 case (PH_DATA | REQUEST):
 539                         spin_lock_irqsave(&ipacx_lock, flags);
 540                         if (st->l1.bcs->tx_skb) {
 541                                 skb_queue_tail(&st->l1.bcs->squeue, skb);
 542                                 spin_unlock_irqrestore(&ipacx_lock, flags);
 543                         } else {
 544                                 st->l1.bcs->tx_skb = skb;
 545                                 set_bit(BC_FLG_BUSY, &st->l1.bcs->Flag);
 546                                 st->l1.bcs->hw.hscx.count = 0;
 547                                 spin_unlock_irqrestore(&ipacx_lock, flags);
 548         bch_fill_fifo(st->l1.bcs);
 549                         }
 550                         break;
 551                 case (PH_PULL | INDICATION):
 552                         if (st->l1.bcs->tx_skb) {
 553                                 printk(KERN_WARNING "HiSax bch_l2l1(): this shouldn't happen\n");
 554                                 break;
 555                         }
 556                         set_bit(BC_FLG_BUSY, &st->l1.bcs->Flag);
 557                         st->l1.bcs->tx_skb = skb;
 558                         st->l1.bcs->hw.hscx.count = 0;
 559       bch_fill_fifo(st->l1.bcs);
 560                         break;
 561                 case (PH_PULL | REQUEST):
 562                         if (!st->l1.bcs->tx_skb) {
 563                                 clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
 564                                 st->l2.l1l2(st, PH_PULL | CONFIRM, NULL);
 565                         } else
 566                                 set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
 567                         break;
 568                 case (PH_ACTIVATE | REQUEST):
 569                         set_bit(BC_FLG_ACTIV, &st->l1.bcs->Flag);
 570                         bch_mode(st->l1.bcs, st->l1.mode, st->l1.bc);
 571                         l1_msg_b(st, pr, arg);
 572                         break;
 573                 case (PH_DEACTIVATE | REQUEST):
 574                         l1_msg_b(st, pr, arg);
 575                         break;
 576                 case (PH_DEACTIVATE | CONFIRM):
 577                         clear_bit(BC_FLG_ACTIV, &st->l1.bcs->Flag);
 578                         clear_bit(BC_FLG_BUSY, &st->l1.bcs->Flag);
 579                         bch_mode(st->l1.bcs, 0, st->l1.bc);
 580                         st->l2.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL);
 581                         break;
 582         }
 583 }
 584
 585
 586 //----------------------------------------------------------
 587 // Read B channel fifo to receive buffer
 588 //----------------------------------------------------------
 589 static void
 590 bch_empty_fifo(struct BCState *bcs, int count)
 591 {
 592         u_char *ptr, hscx;
 593         struct IsdnCardState *cs;
 594         unsigned long flags;
 595         int cnt;
 596
 597         cs = bcs->cs;
 598   hscx = bcs->hw.hscx.hscx;
 599         if ((cs->debug &L1_DEB_HSCX) && !(cs->debug &L1_DEB_HSCX_FIFO))
 600                 debugl1(cs, "bch_empty_fifo()");
 601
 602   // message too large, remove
 603         if (bcs->hw.hscx.rcvidx + count > HSCX_BUFMAX) {
 604                 if (cs->debug &L1_DEB_WARN)
 605                         debugl1(cs, "bch_empty_fifo() incoming packet too large");
 606           cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x80);  // RMC
 607                 bcs->hw.hscx.rcvidx = 0;
 608                 return;
 609         }
 610
 611   // Read data uninterruptible
 612         spin_lock_irqsave(&ipacx_lock, flags);
 613         ptr = bcs->hw.hscx.rcvbuf + bcs->hw.hscx.rcvidx;
 614         cnt = count;
 615         while (cnt--) *ptr++ = cs->BC_Read_Reg(cs, hscx, IPACX_RFIFOB);
 616         cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x80);  // RMC
 617
 618         ptr = bcs->hw.hscx.rcvbuf + bcs->hw.hscx.rcvidx;
 619         bcs->hw.hscx.rcvidx += count;
 620         spin_unlock_irqrestore(&ipacx_lock, flags);
 621
 622         if (cs->debug &L1_DEB_HSCX_FIFO) {
 623                 char *t = bcs->blog;
 624
 625                 t += sprintf(t, "bch_empty_fifo() B-%d cnt %d", hscx, count);
 626                 QuickHex(t, ptr, count);
 627                 debugl1(cs, bcs->blog);
 628         }
 629 }
 630
 631 //----------------------------------------------------------
 632 // Fill buffer to transmit FIFO
 633 //----------------------------------------------------------
 634 static void
 635 bch_fill_fifo(struct BCState *bcs)
 636 {
 637         struct IsdnCardState *cs;
 638         int more, count, cnt;
 639         u_char *ptr, *p, hscx;
 640         unsigned long flags;
 641
 642         cs = bcs->cs;
 643         if ((cs->debug &L1_DEB_HSCX) && !(cs->debug &L1_DEB_HSCX_FIFO))
 644                 debugl1(cs, "bch_fill_fifo()");
 645
 646         if (!bcs->tx_skb)           return;
 647         if (bcs->tx_skb->len <= 0)  return;
 648
 649         hscx = bcs->hw.hscx.hscx;
 650         more = (bcs->mode == L1_MODE_TRANS) ? 1 : 0;
 651         if (bcs->tx_skb->len > B_FIFO_SIZE) {
 652                 more  = 1;
 653                 count = B_FIFO_SIZE;
 654         } else {
 655                 count = bcs->tx_skb->len;
 656         }
 657         cnt = count;
 658
 659         spin_lock_irqsave(&ipacx_lock, flags);
 660         p = ptr = bcs->tx_skb->data;
 661         skb_pull(bcs->tx_skb, count);
 662         bcs->tx_cnt -= count;
 663         bcs->hw.hscx.count += count;
 664         while (cnt--) cs->BC_Write_Reg(cs, hscx, IPACX_XFIFOB, *p++);
 665         cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, (more ? 0x08 : 0x0a));
 666         spin_unlock_irqrestore(&ipacx_lock, flags);
 667
 668         if (cs->debug &L1_DEB_HSCX_FIFO) {
 669                 char *t = bcs->blog;
 670
 671                 t += sprintf(t, "chb_fill_fifo() B-%d cnt %d", hscx, count);
 672                 QuickHex(t, ptr, count);
 673                 debugl1(cs, bcs->blog);
 674         }
 675 }
 676
 677 //----------------------------------------------------------
 678 // B channel interrupt handler
 679 //----------------------------------------------------------
 680 static void
 681 bch_int(struct IsdnCardState *cs, u_char hscx)
 682 {
 683         u_char istab;
 684         struct BCState *bcs;
 685         struct sk_buff *skb;
 686         int count;
 687         u_char rstab;
 688
 689         bcs = cs->bcs + hscx;
 690         istab = cs->BC_Read_Reg(cs, hscx, IPACX_ISTAB);
 691         if (!test_bit(BC_FLG_INIT, &bcs->Flag)) return;
 692
 693         if (istab &0x80) {      // RME
 694                 rstab = cs->BC_Read_Reg(cs, hscx, IPACX_RSTAB);
 695                 if ((rstab &0xf0) != 0xa0) { // !(VFR && !RDO && CRC && !RAB)
 696                         if (!(rstab &0x80))
 697                                 if (cs->debug &L1_DEB_WARN)
 698           debugl1(cs, "bch_int() B-%d: invalid frame", hscx);
 699                         if ((rstab &0x40) && (bcs->mode != L1_MODE_NULL))
 700                                 if (cs->debug &L1_DEB_WARN)
 701           debugl1(cs, "bch_int() B-%d: RDO mode=%d", hscx, bcs->mode);
 702                         if (!(rstab &0x20))
 703                                 if (cs->debug &L1_DEB_WARN)
 704           debugl1(cs, "bch_int() B-%d: CRC error", hscx);
 705             cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x80);  // RMC
 706                 }
 707     else {  // received frame ok
 708                         count = cs->BC_Read_Reg(cs, hscx, IPACX_RBCLB) &(B_FIFO_SIZE-1);
 709                         if (count == 0) count = B_FIFO_SIZE;
 710                         bch_empty_fifo(bcs, count);
 711                         if ((count = bcs->hw.hscx.rcvidx - 1) > 0) {
 712                                 if (cs->debug &L1_DEB_HSCX_FIFO)
 713                                         debugl1(cs, "bch_int Frame %d", count);
 714                                 if (!(skb = dev_alloc_skb(count)))
 715                                         printk(KERN_WARNING "HiSax bch_int(): receive frame out of memory\n");
 716                                 else {
 717                                         memcpy(skb_put(skb, count), bcs->hw.hscx.rcvbuf, count);
 718                                         skb_queue_tail(&bcs->rqueue, skb);
 719                                 }
 720                         }
 721                 }
 722                 bcs->hw.hscx.rcvidx = 0;
 723                 bch_sched_event(bcs, B_RCVBUFREADY);
 724         }
 725
 726         if (istab &0x40) {      // RPF
 727                 bch_empty_fifo(bcs, B_FIFO_SIZE);
 728
 729                 if (bcs->mode == L1_MODE_TRANS) { // queue every chunk
 730                         // receive transparent audio data
 731                         if (!(skb = dev_alloc_skb(B_FIFO_SIZE)))
 732                                 printk(KERN_WARNING "HiSax bch_int(): receive transparent out of memory\n");
 733                         else {
 734                                 memcpy(skb_put(skb, B_FIFO_SIZE), bcs->hw.hscx.rcvbuf, B_FIFO_SIZE);
 735                                 skb_queue_tail(&bcs->rqueue, skb);
 736                         }
 737                         bcs->hw.hscx.rcvidx = 0;
 738                         bch_sched_event(bcs, B_RCVBUFREADY);
 739                 }
 740         }
 741
 742         if (istab &0x20) {      // RFO
 743                 if (cs->debug &L1_DEB_WARN)
 744                         debugl1(cs, "bch_int() B-%d: RFO error", hscx);
 745                 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x40);  // RRES
 746         }
 747
 748         if (istab &0x10) {      // XPR
 749                 if (bcs->tx_skb) {
 750                         if (bcs->tx_skb->len) {
 751                                 bch_fill_fifo(bcs);
 752                                 goto afterXPR;
 753                         }
 754                         skb_queue_tail(&bcs->cmpl_queue, bcs->tx_skb);
 755                         bch_sched_event(bcs, B_CMPLREADY);
 756                         bcs->hw.hscx.count = 0;
 757                 }
 758                 if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
 759                         bcs->hw.hscx.count = 0;
 760                         set_bit(BC_FLG_BUSY, &bcs->Flag);
 761                         bch_fill_fifo(bcs);
 762                 } else {
 763                         clear_bit(BC_FLG_BUSY, &bcs->Flag);
 764                         bch_sched_event(bcs, B_XMTBUFREADY);
 765                 }
 766         }
 767   afterXPR:
 768
 769         if (istab &0x04) {      // XDU
 770     if (bcs->mode == L1_MODE_TRANS) {
 771                         bch_fill_fifo(bcs);
 772     }
 773     else {
 774       if (bcs->tx_skb) {  // restart transmitting the whole frame
 775         skb_push(bcs->tx_skb, bcs->hw.hscx.count);
 776         bcs->tx_cnt += bcs->hw.hscx.count;
 777         bcs->hw.hscx.count = 0;
 778       }
 779             cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x01);  // XRES
 780       if (cs->debug &L1_DEB_WARN)
 781         debugl1(cs, "bch_int() B-%d XDU error", hscx);
 782     }
 783         }
 784 }
 785
 786 //----------------------------------------------------------
 787 //----------------------------------------------------------
 788 static void
 789 bch_mode(struct BCState *bcs, int mode, int bc)
 790 {
 791         struct IsdnCardState *cs = bcs->cs;
 792         int hscx = bcs->hw.hscx.hscx;
 793
 794         bc = bc ? 1 : 0;  // in case bc is greater than 1
 795         if (cs->debug & L1_DEB_HSCX)
 796                 debugl1(cs, "mode_bch() switch B-% mode %d chan %d", hscx, mode, bc);
 797         bcs->mode = mode;
 798         bcs->channel = bc;
 799
 800   // map controller to according timeslot
 801   if (!hscx)
 802   {
 803     cs->writeisac(cs, IPACX_BCHA_TSDP_BC1, 0x80 | bc);
 804     cs->writeisac(cs, IPACX_BCHA_CR,       0x88);
 805   }
 806   else
 807   {
 808     cs->writeisac(cs, IPACX_BCHB_TSDP_BC1, 0x80 | bc);
 809     cs->writeisac(cs, IPACX_BCHB_CR,       0x88);
 810   }
 811
 812         switch (mode) {
 813                 case (L1_MODE_NULL):
 814                     cs->BC_Write_Reg(cs, hscx, IPACX_MODEB, 0xC0);  // rec off
 815                     cs->BC_Write_Reg(cs, hscx, IPACX_EXMB,  0x30);  // std adj.
 816                     cs->BC_Write_Reg(cs, hscx, IPACX_MASKB, 0xFF);  // ints off
 817                     cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x41);  // validate adjustments
 818                     break;
 819                 case (L1_MODE_TRANS):
 820                     cs->BC_Write_Reg(cs, hscx, IPACX_MODEB, 0x88);  // ext transp mode
 821                     cs->BC_Write_Reg(cs, hscx, IPACX_EXMB,  0x00);  // xxx00000
 822                     cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x41);  // validate adjustments
 823                     cs->BC_Write_Reg(cs, hscx, IPACX_MASKB, _MASKB_IMASK);
 824                     break;
 825                 case (L1_MODE_HDLC):
 826                     cs->BC_Write_Reg(cs, hscx, IPACX_MODEB, 0xC8);  // transp mode 0
 827                     cs->BC_Write_Reg(cs, hscx, IPACX_EXMB,  0x01);  // idle=hdlc flags crc enabled
 828                     cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x41);  // validate adjustments
 829                     cs->BC_Write_Reg(cs, hscx, IPACX_MASKB, _MASKB_IMASK);
 830                     break;
 831         }
 832 }
 833
 834 //----------------------------------------------------------
 835 //----------------------------------------------------------
 836 static void
 837 bch_close_state(struct BCState *bcs)
 838 {
 839         bch_mode(bcs, 0, bcs->channel);
 840         if (test_and_clear_bit(BC_FLG_INIT, &bcs->Flag)) {
 841                 if (bcs->hw.hscx.rcvbuf) {
 842                         kfree(bcs->hw.hscx.rcvbuf);
 843                         bcs->hw.hscx.rcvbuf = NULL;
 844                 }
 845                 if (bcs->blog) {
 846                         kfree(bcs->blog);
 847                         bcs->blog = NULL;
 848                 }
 849                 skb_queue_purge(&bcs->rqueue);
 850                 skb_queue_purge(&bcs->squeue);
 851                 if (bcs->tx_skb) {
 852                         dev_kfree_skb_any(bcs->tx_skb);
 853                         bcs->tx_skb = NULL;
 854                         clear_bit(BC_FLG_BUSY, &bcs->Flag);
 855                 }
 856         }
 857 }
 858
 859 //----------------------------------------------------------
 860 //----------------------------------------------------------
 861 static int
 862 bch_open_state(struct IsdnCardState *cs, struct BCState *bcs)
 863 {
 864         if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
 865                 if (!(bcs->hw.hscx.rcvbuf = kmalloc(HSCX_BUFMAX, GFP_ATOMIC))) {
 866                         printk(KERN_WARNING
 867                                 "HiSax open_bchstate(): No memory for hscx.rcvbuf\n");
 868                         clear_bit(BC_FLG_INIT, &bcs->Flag);
 869                         return (1);
 870                 }
 871                 if (!(bcs->blog = kmalloc(MAX_BLOG_SPACE, GFP_ATOMIC))) {
 872                         printk(KERN_WARNING
 873                                 "HiSax open_bchstate: No memory for bcs->blog\n");
 874                         clear_bit(BC_FLG_INIT, &bcs->Flag);
 875                         kfree(bcs->hw.hscx.rcvbuf);
 876                         bcs->hw.hscx.rcvbuf = NULL;
 877                         return (2);
 878                 }
 879                 skb_queue_head_init(&bcs->rqueue);
 880                 skb_queue_head_init(&bcs->squeue);
 881         }
 882         bcs->tx_skb = NULL;
 883         clear_bit(BC_FLG_BUSY, &bcs->Flag);
 884         bcs->event = 0;
 885         bcs->hw.hscx.rcvidx = 0;
 886         bcs->tx_cnt = 0;
 887         return (0);
 888 }
 889
 890 //----------------------------------------------------------
 891 //----------------------------------------------------------
 892 static int
 893 bch_setstack(struct PStack *st, struct BCState *bcs)
 894 {
 895         bcs->channel = st->l1.bc;
 896         if (bch_open_state(st->l1.hardware, bcs)) return (-1);
 897         st->l1.bcs = bcs;
 898         st->l1.l2l1 = bch_l2l1;
 899         setstack_manager(st);
 900         bcs->st = st;
 901         setstack_l1_B(st);
 902         return (0);
 903 }
 904
 905 //----------------------------------------------------------
 906 //----------------------------------------------------------
 907 static void __devinit
 908 bch_init(struct IsdnCardState *cs, int hscx)
 909 {
 910         cs->bcs[hscx].BC_SetStack   = bch_setstack;
 911         cs->bcs[hscx].BC_Close      = bch_close_state;
 912         cs->bcs[hscx].hw.hscx.hscx  = hscx;
 913         cs->bcs[hscx].cs            = cs;
 914         bch_mode(cs->bcs + hscx, 0, hscx);
 915 }
 916
 917
 918 //==========================================================
 919 // Shared functions
 920 //==========================================================
 921
 922 //----------------------------------------------------------
 923 // Main interrupt handler
 924 //----------------------------------------------------------
 925 void
 926 interrupt_ipacx(struct IsdnCardState *cs)
 927 {
 928         u_char ista;
 929
 930         while ((ista = cs->readisac(cs, IPACX_ISTA))) {
 931                 if (ista &0x80) bch_int(cs, 0); // B channel interrupts
 932                 if (ista &0x40) bch_int(cs, 1);
 933                 if (ista &0x01) dch_int(cs);    // D channel
 934                 if (ista &0x10) cic_int(cs);    // Layer 1 state
 935         }
 936 }
 937
 938 //----------------------------------------------------------
 939 // Clears chip interrupt status
 940 //----------------------------------------------------------
 941 static void __init
 942 clear_pending_ints(struct IsdnCardState *cs)
 943 {
 944         int ista;
 945
 946   // all interrupts off
 947   cs->writeisac(cs, IPACX_MASK, 0xff);
 948         cs->writeisac(cs, IPACX_MASKD, 0xff);
 949         cs->BC_Write_Reg(cs, 0, IPACX_MASKB, 0xff);
 950         cs->BC_Write_Reg(cs, 1, IPACX_MASKB, 0xff);
 951
 952   ista = cs->readisac(cs, IPACX_ISTA);
 953   if (ista &0x80) cs->BC_Read_Reg(cs, 0, IPACX_ISTAB);
 954   if (ista &0x40) cs->BC_Read_Reg(cs, 1, IPACX_ISTAB);
 955   if (ista &0x10) cs->readisac(cs, IPACX_CIR0);
 956   if (ista &0x01) cs->readisac(cs, IPACX_ISTAD);
 957 }
 958
 959 //----------------------------------------------------------
 960 // Does chip configuration work
 961 // Work to do depends on bit mask in part
 962 //----------------------------------------------------------
 963 void __init
 964 init_ipacx(struct IsdnCardState *cs, int part)
 965 {
 966         if (part &1) {  // initialise chip
 967                 clear_pending_ints(cs);
 968                 bch_init(cs, 0);
 969                 bch_init(cs, 1);
 970                 dch_init(cs);
 971         }
 972         if (part &2) {  // reenable all interrupts and start chip
 973                 cs->BC_Write_Reg(cs, 0, IPACX_MASKB, _MASKB_IMASK);
 974                 cs->BC_Write_Reg(cs, 1, IPACX_MASKB, _MASKB_IMASK);
 975                 cs->writeisac(cs, IPACX_MASKD, _MASKD_IMASK);
 976                 cs->writeisac(cs, IPACX_MASK, _MASK_IMASK); // global mask register
 977
 978     // reset HDLC Transmitters/receivers
 979                 cs->writeisac(cs, IPACX_CMDRD, 0x41);
 980     cs->BC_Write_Reg(cs, 0, IPACX_CMDRB, 0x41);
 981     cs->BC_Write_Reg(cs, 1, IPACX_CMDRB, 0x41);
 982         ph_command(cs, IPACX_CMD_RES);
 983         }
 984 }
 985
 986 //----------------- end of file -----------------------
 987