gnu/packages/fpga.scm

   1 ;;; GNU Guix --- Functional package management for GNU
   2 ;;; Copyright © 2016 Danny Milosavljevic <dannym@scratchpost.org>
   3 ;;; Copyright © 2016, 2017 Theodoros Foradis <theodoros@foradis.org>
   4 ;;; Copyright © 2018–2021 Tobias Geerinckx-Rice <me@tobias.gr>
   5 ;;; Copyright © 2019 Amin Bandali <bandali@gnu.org>
   6 ;;; Copyright © 2020 Vinicius Monego <monego@posteo.net>
   7 ;;; Copyright © 2021 Andrew Miloradovsky <andrew@interpretmath.pw>
   8 ;;;
   9 ;;; This file is part of GNU Guix.
  10 ;;;
  11 ;;; GNU Guix is free software; you can redistribute it and/or modify it
  12 ;;; under the terms of the GNU General Public License as published by
  13 ;;; the Free Software Foundation; either version 3 of the License, or (at
  14 ;;; your option) any later version.
  15 ;;;
  16 ;;; GNU Guix is distributed in the hope that it will be useful, but
  17 ;;; WITHOUT ANY WARRANTY; without even the implied warranty of
  18 ;;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19 ;;; GNU General Public License for more details.
  20 ;;;
  21 ;;; You should have received a copy of the GNU General Public License
  22 ;;; along with GNU Guix.  If not, see <http://www.gnu.org/licenses/>.
  23
  24 (define-module (gnu packages fpga)
  25   #:use-module ((guix licenses) #:prefix license:)
  26   #:use-module (guix packages)
  27   #:use-module (guix download)
  28   #:use-module (guix git-download)
  29   #:use-module (guix build-system gnu)
  30   #:use-module (guix build-system cmake)
  31   #:use-module (guix build-system python)
  32   #:use-module (gnu packages)
  33   #:use-module (gnu packages autotools)
  34   #:use-module (gnu packages base)
  35   #:use-module (gnu packages compression)
  36   #:use-module (gnu packages pkg-config)
  37   #:use-module (gnu packages tcl)
  38   #:use-module (gnu packages readline)
  39   #:use-module (gnu packages python)
  40   #:use-module (gnu packages python-xyz)
  41   #:use-module (gnu packages bison)
  42   #:use-module (gnu packages check)
  43   #:use-module (gnu packages flex)
  44   #:use-module (gnu packages gettext)
  45   #:use-module (gnu packages gtk)
  46   #:use-module (gnu packages graphviz)
  47   #:use-module (gnu packages libffi)
  48   #:use-module (gnu packages linux)
  49   #:use-module (gnu packages llvm)
  50   #:use-module (gnu packages maths)
  51   #:use-module (gnu packages perl)
  52   #:use-module (gnu packages ghostscript)
  53   #:use-module (gnu packages gperf)
  54   #:use-module (gnu packages gawk)
  55   #:use-module (gnu packages version-control)
  56   #:use-module (gnu packages qt)
  57   #:use-module (gnu packages boost)
  58   #:use-module (gnu packages algebra)
  59   #:use-module (gnu packages libftdi))
  60
  61 (define-public abc
  62  (let ((commit "5ae4b975c49c")
  63        (revision "1"))
  64   (package
  65     (name "abc")
  66     (version (git-version "0.0" revision commit))
  67     (source (origin
  68               (method url-fetch)
  69               (uri
  70                (string-append "https://bitbucket.org/alanmi/abc/get/" commit ".zip"))
  71               (file-name (string-append name "-" version "-checkout.zip"))
  72               (sha256
  73                (base32
  74                 "1syygi1x40rdryih3galr4q8yg1w5bvdzl75hd27v1xq0l5bz3d0"))))
  75     (build-system gnu-build-system)
  76     (native-inputs
  77      (list unzip))
  78     (inputs
  79      (list readline))
  80     (arguments
  81      `(#:tests? #f ; no check target
  82        #:phases
  83        (modify-phases %standard-phases
  84          (delete 'configure)
  85          (replace 'install
  86            (lambda* (#:key outputs #:allow-other-keys)
  87              (let* ((out (assoc-ref outputs "out"))
  88                     (out-bin (string-append out "/bin")))
  89                (install-file "abc" out-bin)))))))
  90     (home-page "https://people.eecs.berkeley.edu/~alanmi/abc/")
  91     (synopsis "Sequential logic synthesis and formal verification")
  92     (description "ABC is a program for sequential logic synthesis and
  93 formal verification.")
  94     (license
  95       (license:non-copyleft "https://fedoraproject.org/wiki/Licensing:MIT#Modern_Variants")))))
  96
  97 (define-public iverilog
  98   (package
  99     (name "iverilog")
 100     (version "10.3")
 101     (source (origin
 102               (method url-fetch)
 103               (uri
 104                (string-append "ftp://ftp.icarus.com/pub/eda/verilog/v10/"
 105                               "verilog-" version ".tar.gz"))
 106               (sha256
 107                (base32
 108                 "1vv88ckvfwq7mrysyjnilsrcrzm9d173kp9w5ivwh6rdw7klbgc6"))))
 109     (build-system gnu-build-system)
 110     (native-inputs
 111      (list flex bison ghostscript))   ; ps2pdf
 112     (home-page "http://iverilog.icarus.com/")
 113     (synopsis "FPGA Verilog simulation and synthesis tool")
 114     (description "Icarus Verilog is a Verilog simulation and synthesis tool.
 115 It operates as a compiler, compiling source code written in Verilog
 116 (IEEE-1364) into some target format.
 117 For batch simulation, the compiler can generate an intermediate form
 118 called vvp assembly.
 119 This intermediate form is executed by @command{vvp}.
 120 For synthesis, the compiler generates netlists in the desired format.")
 121     ;; GPL2 only because of:
 122     ;; - ./driver/iverilog.man.in
 123     ;; - ./iverilog-vpi.man.in
 124     ;; - ./tgt-fpga/iverilog-fpga.man
 125     ;; - ./vvp/vvp.man.in
 126     ;; Otherwise would be GPL2+.
 127     ;; You have to accept both GPL2 and LGPL2.1+.
 128     (license (list license:gpl2 license:lgpl2.1+))))
 129
 130 (define-public yosys
 131   (package
 132     (name "yosys")
 133     (version "0.9")
 134     (source (origin
 135               (method git-fetch)
 136               (uri (git-reference
 137                     (url "https://github.com/cliffordwolf/yosys")
 138                     (commit (string-append "yosys-" version))
 139                     (recursive? #t))) ; for the ‘iverilog’ submodule
 140               (sha256
 141                 (base32
 142                    "0lb9r055h8y1vj2z8gm4ip0v06j5mk7f9zx9gi67kkqb7g4rhjli"))
 143               (file-name (git-file-name name version))
 144               (modules '((guix build utils)))
 145               (snippet
 146                '(begin
 147                   (substitute* "Makefile"
 148                     (("ABCREV = .*") "ABCREV = default\n"))
 149                   #t))))
 150     (build-system gnu-build-system)
 151     (arguments
 152      `(#:test-target "test"
 153        #:make-flags (list "CC=gcc"
 154                           "CXX=g++"
 155                           (string-append "PREFIX=" %output))
 156        #:phases
 157        (modify-phases %standard-phases
 158          (add-before 'configure 'fix-paths
 159            (lambda _
 160              (substitute* "./passes/cmds/show.cc"
 161                (("exec xdot") (string-append "exec " (which "xdot")))
 162                (("dot -") (string-append (which "dot") " -"))
 163                (("fuser") (which "fuser")))
 164              #t))
 165          (replace 'configure
 166            (lambda* (#:key inputs (make-flags '()) #:allow-other-keys)
 167              (apply invoke "make" "config-gcc" make-flags)))
 168          (add-after 'configure 'prepare-abc
 169            (lambda* (#:key inputs #:allow-other-keys)
 170              (let* ((sourceabc (assoc-ref inputs "abc"))
 171                     (sourcebin (string-append sourceabc "/bin"))
 172                     (source (string-append sourcebin "/abc")))
 173                    (mkdir-p "abc")
 174                    (call-with-output-file "abc/Makefile"
 175                      (lambda (port)
 176                        (format port ".PHONY: all\nall:\n\tcp -f abc abc-default\n")))
 177                    (copy-file source "abc/abc")
 178                    (invoke "chmod" "+w" "abc/abc"))))
 179           (add-before 'check 'fix-iverilog-references
 180              (lambda* (#:key inputs native-inputs #:allow-other-keys)
 181                (let* ((xinputs (or native-inputs inputs))
 182                       (xdirname (assoc-ref xinputs "iverilog"))
 183                       (iverilog (string-append xdirname "/bin/iverilog")))
 184                      (substitute* '("./manual/CHAPTER_StateOfTheArt/synth.sh"
 185                                     "./manual/CHAPTER_StateOfTheArt/validate_tb.sh"
 186                                     "./techlibs/ice40/tests/test_bram.sh"
 187                                     "./techlibs/ice40/tests/test_ffs.sh"
 188                                     "./techlibs/xilinx/tests/bram1.sh"
 189                                     "./techlibs/xilinx/tests/bram2.sh"
 190                                     "./tests/bram/run-single.sh"
 191                                     "./tests/realmath/run-test.sh"
 192                                     "./tests/simple/run-test.sh"
 193                                     "./tests/techmap/mem_simple_4x1_runtest.sh"
 194                                     "./tests/tools/autotest.sh"
 195                                     "./tests/vloghtb/common.sh")
 196                         (("if ! which iverilog") "if ! true")
 197                         (("iverilog ") (string-append iverilog " "))
 198                         (("iverilog_bin=\".*\"") (string-append "iverilog_bin=\""
 199                                                                 iverilog "\"")))
 200                      #t))))))
 201     (native-inputs
 202      (list pkg-config
 203            python
 204            bison
 205            flex
 206            gawk ; for the tests and "make" progress pretty-printing
 207            tcl ; tclsh for the tests
 208            iverilog)) ; for the tests
 209     (inputs
 210      (list tcl
 211            readline
 212            libffi
 213            graphviz
 214            psmisc
 215            xdot
 216            abc))
 217     (propagated-inputs
 218      (list z3)) ; should be in path for yosys-smtbmc
 219     (home-page "http://www.clifford.at/yosys/")
 220     (synopsis "FPGA Verilog RTL synthesizer")
 221     (description "Yosys synthesizes Verilog-2005.")
 222     (license license:isc)))
 223
 224 (define-public icestorm
 225   (let ((commit "0ec00d892a91cc68e45479b46161f649caea2933")
 226         (revision "3"))
 227    (package
 228     (name "icestorm")
 229     (version (git-version "0.0" revision commit))
 230     (source (origin
 231               (method git-fetch)
 232               (uri (git-reference
 233                      (url "https://github.com/cliffordwolf/icestorm")
 234                      (commit commit)))
 235               (file-name (git-file-name name version))
 236               (sha256
 237                 (base32
 238                    "1qlh99fafb7xga702k64fmc9m700nsddrfgcq4x8qn8fplsb64f1"))))
 239     (build-system gnu-build-system)
 240     (arguments
 241      `(#:tests? #f ; no unit tests that don't need an FPGA exist.
 242        #:make-flags (list "CC=gcc" "CXX=g++"
 243                           (string-append "PREFIX=" (assoc-ref %outputs "out")))
 244        #:phases
 245         (modify-phases %standard-phases
 246           (add-after 'unpack 'remove-usr-local
 247             (lambda _
 248               (substitute* "iceprog/Makefile"
 249                 (("-I/usr/local/include") "")
 250                 (("-L/usr/local/lib") ""))
 251               #t))
 252           (add-after 'remove-usr-local 'fix-usr-local
 253             (lambda* (#:key outputs #:allow-other-keys)
 254               (substitute* "icebox/icebox_vlog.py"
 255                 (("/usr/local/share") (string-append (assoc-ref outputs "out") "/share")))
 256               #t))
 257           (delete 'configure))))
 258     (inputs
 259      (list libftdi))
 260     (native-inputs
 261      `(("python-3" ,python)
 262        ("pkg-config" ,pkg-config)))
 263     (home-page "http://www.clifford.at/icestorm/")
 264     (synopsis "Project IceStorm - Lattice iCE40 FPGAs bitstream tools")
 265     (description "Project IceStorm - Lattice iCE40 FPGAs Bitstream Tools.
 266 Includes the actual FTDI connector.")
 267     (license license:isc))))
 268
 269 (define-public nextpnr-ice40
 270   (let [(commit "fbe486df459909065d6852a7495a212dfd2accef")
 271         (revision "1")]
 272     (package
 273       (name "nextpnr-ice40")
 274       (version (git-version "0.0.0" revision commit))
 275       (source
 276         (origin
 277           (method git-fetch)
 278           (uri (git-reference
 279                  (url "git://github.com/YosysHQ/nextpnr")
 280                  (commit commit)))
 281           (file-name (git-file-name name version))
 282           (sha256
 283            (base32
 284             "1fmxsywgs45g88ra7ips5s2niiiwrkyxdcy742ws18dfk2y4vi9c"))))
 285       (inputs
 286        (list boost
 287              eigen
 288              icestorm
 289              python
 290              qtbase-5
 291              yosys))
 292       (build-system cmake-build-system)
 293       (arguments
 294        `(#:configure-flags `("-DARCH=ice40"
 295                              ,(string-append "-DICEBOX_ROOT="
 296                                              (assoc-ref %build-inputs "icestorm")
 297                                              "/share/icebox"))
 298          #:tests? #f))
 299       (synopsis "Place-and-Route tool for FPGAs")
 300       (description "Nextpnr aims to be a vendor neutral, timing driven,
 301 FOSS FPGA place and route tool.")
 302       (home-page "https://github.com/YosysHQ/nextpnr")
 303       (license license:expat))))
 304
 305 (define-public arachne-pnr
 306   (let ((commit "840bdfdeb38809f9f6af4d89dd7b22959b176fdd")
 307         (revision "2"))
 308    (package
 309     (name "arachne-pnr")
 310     (version (string-append "0.0-" revision "-" (string-take commit 9)))
 311     (source (origin
 312               (method git-fetch)
 313               (uri (git-reference
 314                      (url "https://github.com/YosysHQ/arachne-pnr")
 315                      (commit commit)))
 316               (file-name (git-file-name name version))
 317               (sha256
 318                 (base32
 319                    "1dqvjvgvsridybishv4pnigw9gypxh7r7nrqp9z9qq92v7c5rxzl"))))
 320     (build-system gnu-build-system)
 321     (arguments
 322      `(#:test-target "test"
 323        #:make-flags
 324        (list (string-append "DESTDIR=" (assoc-ref %outputs "out"))
 325              (string-append "ICEBOX=" (string-append
 326                                        (assoc-ref %build-inputs "icestorm")
 327                                        "/share/icebox")))
 328        #:phases (modify-phases %standard-phases
 329        (replace 'configure
 330          (lambda* (#:key outputs inputs #:allow-other-keys)
 331            (substitute* '("./tests/fsm/generate.py"
 332                           "./tests/combinatorial/generate.py")
 333              (("#!/usr/bin/python") "#!/usr/bin/python2"))
 334            #t)))))
 335     (inputs
 336      (list icestorm))
 337     (native-inputs
 338      `(("git" ,git)  ; for determining its own version string
 339        ("yosys" ,yosys) ; for tests
 340        ("perl" ,perl) ; for shasum
 341        ("python-2" ,python-2))) ; for tests
 342     (home-page "https://github.com/YosysHQ/arachne-pnr")
 343     (synopsis "Place-and-Route tool for FPGAs")
 344     (description "Arachne-PNR is a Place-and-Route Tool For FPGAs.")
 345     (license license:gpl2))))
 346
 347 (define-public gtkwave
 348   (package
 349     (name "gtkwave")
 350     (version "3.3.111")
 351     (source
 352      (origin
 353        (method url-fetch)
 354        (uri (list (string-append "mirror://sourceforge/gtkwave/"
 355                                  "gtkwave-" version "/"
 356                                  "gtkwave-" version ".tar.gz")
 357                   (string-append "http://gtkwave.sourceforge.net/"
 358                                  "gtkwave-" version ".tar.gz")))
 359        (sha256
 360         (base32 "15n2gv2hd7h23cci95ij7yr71fkxppb209sfdsmmngh3fik09rpn"))))
 361     (build-system gnu-build-system)
 362     (native-inputs
 363      (list gperf pkg-config))
 364     (inputs
 365      `(("tcl" ,tcl)
 366        ("tk" ,tk)
 367        ("gtk+-2" ,gtk+-2)))
 368     (arguments
 369      `(#:configure-flags
 370        (list (string-append "--with-tcl="
 371                             (assoc-ref %build-inputs "tcl")
 372                             "/lib")
 373              (string-append "--with-tk="
 374                             (assoc-ref %build-inputs "tk")
 375                             "/lib"))))
 376
 377     (synopsis "Waveform viewer for FPGA simulator trace files")
 378     (description "This package is a waveform viewer for FPGA
 379 simulator trace files (@dfn{FST}).")
 380     (home-page "http://gtkwave.sourceforge.net/")
 381     ;; Exception against free government use in tcl_np.c and tcl_np.h.
 382     (license (list license:gpl2+ license:expat license:tcl/tk))))
 383
 384 (define-public python-migen
 385   (package
 386     (name "python-migen")
 387     (version "0.9.2")
 388     (source
 389      (origin
 390        ;; Tests fail in the PyPI tarball due to missing files.
 391        (method git-fetch)
 392        (uri (git-reference
 393              (url "https://github.com/m-labs/migen")
 394              (commit version)))
 395        (file-name (git-file-name name version))
 396        (sha256
 397         (base32 "1kq11if64zj84gv4w1q7l16fp17xjxl2wv5hc9dibr1z3m1gy67l"))))
 398     (build-system python-build-system)
 399     (propagated-inputs
 400      (list python-colorama))
 401     (home-page "https://m-labs.hk/gateware/migen/")
 402     (synopsis "Python toolbox for building complex digital hardware")
 403     (description
 404      "Migen FHDL is a Python library that replaces the event-driven
 405 paradigm of Verilog and VHDL with the notions of combinatorial and
 406 synchronous statements, has arithmetic rules that make integers always
 407 behave like mathematical integers, and allows the design's logic to be
 408 constructed by a Python program.")
 409     (license license:bsd-2)))
 410
 411 (define-public python-myhdl
 412   (package
 413     (name "python-myhdl")
 414     (version "0.11")
 415     (source
 416       (origin
 417         (method url-fetch)
 418         (uri (pypi-uri "myhdl" version))
 419         (sha256
 420           (base32
 421             "04fi59cyn5dsci0ai7djg74ybkqfcjzhj1jfmac2xanbcrw9j3yk"))))
 422     (build-system python-build-system)
 423     (home-page "http://www.myhdl.org/")
 424     (synopsis "Python as a Hardware Description Language")
 425     (description "This package provides a library to turn Python into
 426 a hardware description and verification language. ")
 427     (license license:lgpl2.1+)))
 428
 429 (define-public nvc
 430   (package
 431     (name "nvc")
 432     (version "1.5.3")
 433     (source (origin
 434               (method git-fetch)
 435               (uri (git-reference
 436                      (url "https://github.com/nickg/nvc.git")
 437                      (commit (string-append "r" version))))
 438               (file-name (string-append name "-" version "-checkout"))
 439               (sha256
 440                (base32
 441                 "1gjpwblp8isplyad3b6fl7cb5qv1rn3lf9qgf4l139y97cp2mm4s"))))
 442     (build-system gnu-build-system)
 443     (arguments
 444      `(#:configure-flags
 445        '("--enable-vhpi")
 446        #:phases
 447        (modify-phases %standard-phases
 448          (add-after 'unpack 'clean-up
 449            (lambda _
 450              (delete-file "autogen.sh"))))))
 451     (native-inputs
 452      (list automake
 453            autoconf
 454            flex
 455            gnu-gettext
 456            libtool
 457            pkg-config
 458            which
 459            check)) ; for the tests
 460     (inputs
 461      (list llvm-9))
 462     (synopsis "VHDL compiler and simulator")
 463     (description "This package provides a VHDL compiler and simulator.")
 464     (home-page "https://github.com/nickg/nvc")
 465     (license license:gpl3+)))
 466
 467 (define-public systemc
 468   (package
 469     (name "systemc")
 470     (version "2.3.3")
 471     (source
 472      (origin
 473        (method url-fetch)
 474        (uri (string-append
 475              "https://accellera.org/images/downloads/standards/"
 476              "systemc/systemc-" version ".tar.gz"))
 477        (sha256
 478         (base32 "0gvv3xmhiwx1izmzy06yslzqzh6ygrgmw53xqfmyvbz5a6ivk0ap"))))
 479     (native-inputs (list perl))
 480     (build-system gnu-build-system)
 481     (arguments '(#:configure-flags '("--enable-debug")))
 482     (home-page "https://accellera.org/community/systemc")
 483     (synopsis "Library for event-driven simulation")
 484     (description
 485      "SystemC is a C++ library for modeling concurrent systems, and the
 486 reference implementation of IEEE 1666-2011.  It provides a notion of timing as
 487 well as an event-driven simulations environment.  Due to its concurrent and
 488 sequential nature, SystemC allows the description and integration of complex
 489 hardware and software components.  To some extent, SystemC can be seen as
 490 a Hardware Description Language.  However, unlike VHDL or Verilog, SystemC
 491 provides sophisticated mechanisms that offer high abstraction levels on
 492 components interfaces.  This, in turn, facilitates the integration of systems
 493 using different abstraction levels.")
 494     ;; homepages.cae.wisc.edu/~ece734/SystemC/Esperan_SystemC_tutorial.pdf
 495     (license license:asl2.0)))
 496
 497 (define-public verilator
 498   (package
 499     (name "verilator")
 500     (version "4.204")
 501     (source
 502      (origin
 503        (method git-fetch)
 504        (uri (git-reference
 505              (url "https://github.com/verilator/verilator")
 506              (commit (string-append "v" version))))
 507        (file-name (git-file-name name version))
 508        (sha256
 509         (base32 "0cji5c8870h895l2vxnz8g6z7msv23dzbjaf98va7kva0qlfy2fz"))))
 510     (native-inputs
 511      `(("autoconf" ,autoconf)
 512        ("automake" ,automake)
 513        ("bison" ,bison)
 514        ("flex" ,flex)
 515        ("gettext" ,gettext-minimal)
 516        ("python" ,python)))
 517     (inputs
 518      (list perl systemc))
 519     (build-system gnu-build-system)
 520     (arguments
 521      '(#:configure-flags
 522        (list (string-append "LDFLAGS=-L"
 523                             (assoc-ref %build-inputs "systemc")
 524                             "/lib-linux64"))
 525        #:make-flags
 526        (list (string-append "LDFLAGS=-L"
 527                             (assoc-ref %build-inputs "systemc")
 528                             "/lib-linux64"))
 529        #:phases
 530        (modify-phases %standard-phases
 531          (replace 'bootstrap
 532            (lambda _ (invoke "autoconf"))))
 533        #:test-target "test"))
 534     ;; #error "Something failed during ./configure as config_build.h is incomplete.
 535     ;; Perhaps you used autoreconf, don't." -- so we won't. ^^
 536     (home-page "https://www.veripool.org/projects/verilator/")
 537     (synopsis "Fast Verilog/SystemVerilog simulator")
 538     (description
 539      "Verilator is invoked with parameters similar to GCC or Synopsys’s VCS.
 540 It ``Verilates'' the specified Verilog or SystemVerilog code by reading it,
 541 performing lint checks, and optionally inserting assertion checks and
 542 coverage-analysis points.  It outputs single- or multi-threaded @file{.cpp}
 543 and @file{.h} files, the ``Verilated'' code.
 544
 545 The user writes a little C++/SystemC wrapper file, which instantiates the
 546 Verilated model of the user’s top level module.  These C++/SystemC files are
 547 then compiled by a C++ compiler (GCC/Clang/etc.).  The resulting executable
 548 performs the design simulation.  Verilator also supports linking its generated
 549 libraries, optionally encrypted, into other simulators.")
 550     (license license:lgpl3)))