Commit | Line | Data |
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c850980a JPM |
1 | #include "cpudefs.h" |
2 | #include "cpuextra.h" | |
3 | #include "inlines.h" | |
4 | #include "cputbl.h" | |
5 | #define CPUFUNC(x) x##_ff | |
6 | #ifdef NOFLAGS | |
7 | #include "noflags.h" | |
8 | #endif | |
9 | ||
10 | const int areg_byteinc[] = { 1, 1, 1, 1, 1, 1, 1, 2 }; | |
11 | const int imm8_table[] = { 8, 1, 2, 3, 4, 5, 6, 7 }; | |
12 | ||
13 | const int movem_index1[256] = { | |
14 | 0x08, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, | |
15 | 0x04, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, | |
16 | 0x05, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, | |
17 | 0x04, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, | |
18 | 0x06, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, | |
19 | 0x04, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, | |
20 | 0x05, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, | |
21 | 0x04, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, | |
22 | 0x07, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, | |
23 | 0x04, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, | |
24 | 0x05, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, | |
25 | 0x04, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, | |
26 | 0x06, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, | |
27 | 0x04, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, | |
28 | 0x05, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, | |
29 | 0x04, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, 0x03, 0x00, 0x01, 0x00, 0x02, 0x00, 0x01, 0x00, | |
30 | }; | |
31 | ||
32 | const int movem_index2[256] = { | |
33 | 0xFFFFFFFF, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, 0x04, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, | |
34 | 0x03, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, 0x04, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, | |
35 | 0x02, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, 0x04, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, | |
36 | 0x03, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, 0x04, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, | |
37 | 0x01, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, 0x04, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, | |
38 | 0x03, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, 0x04, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, | |
39 | 0x02, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, 0x04, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, | |
40 | 0x03, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, 0x04, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, | |
41 | 0x00, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, 0x04, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, | |
42 | 0x03, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, 0x04, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, | |
43 | 0x02, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, 0x04, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, | |
44 | 0x03, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, 0x04, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, | |
45 | 0x01, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, 0x04, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, | |
46 | 0x03, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, 0x04, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, | |
47 | 0x02, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, 0x04, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, | |
48 | 0x03, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, 0x04, 0x07, 0x06, 0x07, 0x05, 0x07, 0x06, 0x07, | |
49 | }; | |
50 | ||
51 | const int movem_next[256] = { | |
52 | 0x00, 0x00, 0x00, 0x02, 0x00, 0x04, 0x04, 0x06, 0x00, 0x08, 0x08, 0x0A, 0x08, 0x0C, 0x0C, 0x0E, | |
53 | 0x00, 0x10, 0x10, 0x12, 0x10, 0x14, 0x14, 0x16, 0x10, 0x18, 0x18, 0x1A, 0x18, 0x1C, 0x1C, 0x1E, | |
54 | 0x00, 0x20, 0x20, 0x22, 0x20, 0x24, 0x24, 0x26, 0x20, 0x28, 0x28, 0x2A, 0x28, 0x2C, 0x2C, 0x2E, | |
55 | 0x20, 0x30, 0x30, 0x32, 0x30, 0x34, 0x34, 0x36, 0x30, 0x38, 0x38, 0x3A, 0x38, 0x3C, 0x3C, 0x3E, | |
56 | 0x00, 0x40, 0x40, 0x42, 0x40, 0x44, 0x44, 0x46, 0x40, 0x48, 0x48, 0x4A, 0x48, 0x4C, 0x4C, 0x4E, | |
57 | 0x40, 0x50, 0x50, 0x52, 0x50, 0x54, 0x54, 0x56, 0x50, 0x58, 0x58, 0x5A, 0x58, 0x5C, 0x5C, 0x5E, | |
58 | 0x40, 0x60, 0x60, 0x62, 0x60, 0x64, 0x64, 0x66, 0x60, 0x68, 0x68, 0x6A, 0x68, 0x6C, 0x6C, 0x6E, | |
59 | 0x60, 0x70, 0x70, 0x72, 0x70, 0x74, 0x74, 0x76, 0x70, 0x78, 0x78, 0x7A, 0x78, 0x7C, 0x7C, 0x7E, | |
60 | 0x00, 0x80, 0x80, 0x82, 0x80, 0x84, 0x84, 0x86, 0x80, 0x88, 0x88, 0x8A, 0x88, 0x8C, 0x8C, 0x8E, | |
61 | 0x80, 0x90, 0x90, 0x92, 0x90, 0x94, 0x94, 0x96, 0x90, 0x98, 0x98, 0x9A, 0x98, 0x9C, 0x9C, 0x9E, | |
62 | 0x80, 0xA0, 0xA0, 0xA2, 0xA0, 0xA4, 0xA4, 0xA6, 0xA0, 0xA8, 0xA8, 0xAA, 0xA8, 0xAC, 0xAC, 0xAE, | |
63 | 0xA0, 0xB0, 0xB0, 0xB2, 0xB0, 0xB4, 0xB4, 0xB6, 0xB0, 0xB8, 0xB8, 0xBA, 0xB8, 0xBC, 0xBC, 0xBE, | |
64 | 0x80, 0xC0, 0xC0, 0xC2, 0xC0, 0xC4, 0xC4, 0xC6, 0xC0, 0xC8, 0xC8, 0xCA, 0xC8, 0xCC, 0xCC, 0xCE, | |
65 | 0xC0, 0xD0, 0xD0, 0xD2, 0xD0, 0xD4, 0xD4, 0xD6, 0xD0, 0xD8, 0xD8, 0xDA, 0xD8, 0xDC, 0xDC, 0xDE, | |
66 | 0xC0, 0xE0, 0xE0, 0xE2, 0xE0, 0xE4, 0xE4, 0xE6, 0xE0, 0xE8, 0xE8, 0xEA, 0xE8, 0xEC, 0xEC, 0xEE, | |
67 | 0xE0, 0xF0, 0xF0, 0xF2, 0xF0, 0xF4, 0xF4, 0xF6, 0xF0, 0xF8, 0xF8, 0xFA, 0xF8, 0xFC, 0xFC, 0xFE, | |
68 | }; | |
69 | ||
70 | ||
71 | #if !defined(PART_1) && !defined(PART_2) && !defined(PART_3) && !defined(PART_4) && !defined(PART_5) && !defined(PART_6) && !defined(PART_7) && !defined(PART_8) | |
72 | #define PART_1 1 | |
73 | #define PART_2 1 | |
74 | #define PART_3 1 | |
75 | #define PART_4 1 | |
76 | #define PART_5 1 | |
77 | #define PART_6 1 | |
78 | #define PART_7 1 | |
79 | #define PART_8 1 | |
80 | #endif | |
81 | ||
82 | #ifdef PART_1 | |
83 | unsigned long CPUFUNC(op_0_4)(uint32_t opcode) /* OR */ | |
84 | { | |
85 | uint32_t dstreg = opcode & 7; | |
86 | OpcodeFamily = 1; CurrentInstrCycles = 8; | |
87 | {{ int8_t src = get_ibyte(2); | |
88 | { int8_t dst = m68k_dreg(regs, dstreg); | |
89 | src |= dst; | |
90 | CLEAR_CZNV; | |
91 | SET_ZFLG (((int8_t)(src)) == 0); | |
92 | SET_NFLG (((int8_t)(src)) < 0); | |
93 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
94 | }}}m68k_incpc(4); | |
95 | return 8; | |
96 | } | |
97 | unsigned long CPUFUNC(op_10_4)(uint32_t opcode) /* OR */ | |
98 | { | |
99 | uint32_t dstreg = opcode & 7; | |
100 | OpcodeFamily = 1; CurrentInstrCycles = 16; | |
101 | {{ int8_t src = get_ibyte(2); | |
102 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
103 | { int8_t dst = m68k_read_memory_8(dsta); | |
104 | src |= dst; | |
105 | CLEAR_CZNV; | |
106 | SET_ZFLG (((int8_t)(src)) == 0); | |
107 | SET_NFLG (((int8_t)(src)) < 0); | |
108 | m68k_write_memory_8(dsta,src); | |
109 | }}}}m68k_incpc(4); | |
110 | return 16; | |
111 | } | |
112 | unsigned long CPUFUNC(op_18_4)(uint32_t opcode) /* OR */ | |
113 | { | |
114 | uint32_t dstreg = opcode & 7; | |
115 | OpcodeFamily = 1; CurrentInstrCycles = 16; | |
116 | {{ int8_t src = get_ibyte(2); | |
117 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
118 | { int8_t dst = m68k_read_memory_8(dsta); | |
119 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
120 | src |= dst; | |
121 | CLEAR_CZNV; | |
122 | SET_ZFLG (((int8_t)(src)) == 0); | |
123 | SET_NFLG (((int8_t)(src)) < 0); | |
124 | m68k_write_memory_8(dsta,src); | |
125 | }}}}m68k_incpc(4); | |
126 | return 16; | |
127 | } | |
128 | unsigned long CPUFUNC(op_20_4)(uint32_t opcode) /* OR */ | |
129 | { | |
130 | uint32_t dstreg = opcode & 7; | |
131 | OpcodeFamily = 1; CurrentInstrCycles = 18; | |
132 | {{ int8_t src = get_ibyte(2); | |
133 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
134 | { int8_t dst = m68k_read_memory_8(dsta); | |
135 | m68k_areg (regs, dstreg) = dsta; | |
136 | src |= dst; | |
137 | CLEAR_CZNV; | |
138 | SET_ZFLG (((int8_t)(src)) == 0); | |
139 | SET_NFLG (((int8_t)(src)) < 0); | |
140 | m68k_write_memory_8(dsta,src); | |
141 | }}}}m68k_incpc(4); | |
142 | return 18; | |
143 | } | |
144 | unsigned long CPUFUNC(op_28_4)(uint32_t opcode) /* OR */ | |
145 | { | |
146 | uint32_t dstreg = opcode & 7; | |
147 | OpcodeFamily = 1; CurrentInstrCycles = 20; | |
148 | {{ int8_t src = get_ibyte(2); | |
149 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); | |
150 | { int8_t dst = m68k_read_memory_8(dsta); | |
151 | src |= dst; | |
152 | CLEAR_CZNV; | |
153 | SET_ZFLG (((int8_t)(src)) == 0); | |
154 | SET_NFLG (((int8_t)(src)) < 0); | |
155 | m68k_write_memory_8(dsta,src); | |
156 | }}}}m68k_incpc(6); | |
157 | return 20; | |
158 | } | |
159 | unsigned long CPUFUNC(op_30_4)(uint32_t opcode) /* OR */ | |
160 | { | |
161 | uint32_t dstreg = opcode & 7; | |
162 | OpcodeFamily = 1; CurrentInstrCycles = 22; | |
163 | {{ int8_t src = get_ibyte(2); | |
164 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); | |
165 | BusCyclePenalty += 2; | |
166 | { int8_t dst = m68k_read_memory_8(dsta); | |
167 | src |= dst; | |
168 | CLEAR_CZNV; | |
169 | SET_ZFLG (((int8_t)(src)) == 0); | |
170 | SET_NFLG (((int8_t)(src)) < 0); | |
171 | m68k_write_memory_8(dsta,src); | |
172 | }}}}m68k_incpc(6); | |
173 | return 22; | |
174 | } | |
175 | unsigned long CPUFUNC(op_38_4)(uint32_t opcode) /* OR */ | |
176 | { | |
177 | OpcodeFamily = 1; CurrentInstrCycles = 20; | |
178 | {{ int8_t src = get_ibyte(2); | |
179 | { uint32_t dsta = (int32_t)(int16_t)get_iword(4); | |
180 | { int8_t dst = m68k_read_memory_8(dsta); | |
181 | src |= dst; | |
182 | CLEAR_CZNV; | |
183 | SET_ZFLG (((int8_t)(src)) == 0); | |
184 | SET_NFLG (((int8_t)(src)) < 0); | |
185 | m68k_write_memory_8(dsta,src); | |
186 | }}}}m68k_incpc(6); | |
187 | return 20; | |
188 | } | |
189 | unsigned long CPUFUNC(op_39_4)(uint32_t opcode) /* OR */ | |
190 | { | |
191 | OpcodeFamily = 1; CurrentInstrCycles = 24; | |
192 | {{ int8_t src = get_ibyte(2); | |
193 | { uint32_t dsta = get_ilong(4); | |
194 | { int8_t dst = m68k_read_memory_8(dsta); | |
195 | src |= dst; | |
196 | CLEAR_CZNV; | |
197 | SET_ZFLG (((int8_t)(src)) == 0); | |
198 | SET_NFLG (((int8_t)(src)) < 0); | |
199 | m68k_write_memory_8(dsta,src); | |
200 | }}}}m68k_incpc(8); | |
201 | return 24; | |
202 | } | |
203 | unsigned long CPUFUNC(op_3c_4)(uint32_t opcode) /* ORSR */ | |
204 | { | |
205 | OpcodeFamily = 4; CurrentInstrCycles = 20; | |
206 | { MakeSR(); | |
207 | { int16_t src = get_iword(2); | |
208 | src &= 0xFF; | |
209 | regs.sr |= src; | |
210 | MakeFromSR(); | |
211 | }}m68k_incpc(4); | |
212 | return 20; | |
213 | } | |
214 | unsigned long CPUFUNC(op_40_4)(uint32_t opcode) /* OR */ | |
215 | { | |
216 | uint32_t dstreg = opcode & 7; | |
217 | OpcodeFamily = 1; CurrentInstrCycles = 8; | |
218 | {{ int16_t src = get_iword(2); | |
219 | { int16_t dst = m68k_dreg(regs, dstreg); | |
220 | src |= dst; | |
221 | CLEAR_CZNV; | |
222 | SET_ZFLG (((int16_t)(src)) == 0); | |
223 | SET_NFLG (((int16_t)(src)) < 0); | |
224 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
225 | }}}m68k_incpc(4); | |
226 | return 8; | |
227 | } | |
228 | unsigned long CPUFUNC(op_50_4)(uint32_t opcode) /* OR */ | |
229 | { | |
230 | uint32_t dstreg = opcode & 7; | |
231 | OpcodeFamily = 1; CurrentInstrCycles = 16; | |
232 | {{ int16_t src = get_iword(2); | |
233 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
234 | { int16_t dst = m68k_read_memory_16(dsta); | |
235 | src |= dst; | |
236 | CLEAR_CZNV; | |
237 | SET_ZFLG (((int16_t)(src)) == 0); | |
238 | SET_NFLG (((int16_t)(src)) < 0); | |
239 | m68k_write_memory_16(dsta,src); | |
240 | }}}}m68k_incpc(4); | |
241 | return 16; | |
242 | } | |
243 | unsigned long CPUFUNC(op_58_4)(uint32_t opcode) /* OR */ | |
244 | { | |
245 | uint32_t dstreg = opcode & 7; | |
246 | OpcodeFamily = 1; CurrentInstrCycles = 16; | |
247 | {{ int16_t src = get_iword(2); | |
248 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
249 | { int16_t dst = m68k_read_memory_16(dsta); | |
250 | m68k_areg(regs, dstreg) += 2; | |
251 | src |= dst; | |
252 | CLEAR_CZNV; | |
253 | SET_ZFLG (((int16_t)(src)) == 0); | |
254 | SET_NFLG (((int16_t)(src)) < 0); | |
255 | m68k_write_memory_16(dsta,src); | |
256 | }}}}m68k_incpc(4); | |
257 | return 16; | |
258 | } | |
259 | unsigned long CPUFUNC(op_60_4)(uint32_t opcode) /* OR */ | |
260 | { | |
261 | uint32_t dstreg = opcode & 7; | |
262 | OpcodeFamily = 1; CurrentInstrCycles = 18; | |
263 | {{ int16_t src = get_iword(2); | |
264 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
265 | { int16_t dst = m68k_read_memory_16(dsta); | |
266 | m68k_areg (regs, dstreg) = dsta; | |
267 | src |= dst; | |
268 | CLEAR_CZNV; | |
269 | SET_ZFLG (((int16_t)(src)) == 0); | |
270 | SET_NFLG (((int16_t)(src)) < 0); | |
271 | m68k_write_memory_16(dsta,src); | |
272 | }}}}m68k_incpc(4); | |
273 | return 18; | |
274 | } | |
275 | unsigned long CPUFUNC(op_68_4)(uint32_t opcode) /* OR */ | |
276 | { | |
277 | uint32_t dstreg = opcode & 7; | |
278 | OpcodeFamily = 1; CurrentInstrCycles = 20; | |
279 | {{ int16_t src = get_iword(2); | |
280 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); | |
281 | { int16_t dst = m68k_read_memory_16(dsta); | |
282 | src |= dst; | |
283 | CLEAR_CZNV; | |
284 | SET_ZFLG (((int16_t)(src)) == 0); | |
285 | SET_NFLG (((int16_t)(src)) < 0); | |
286 | m68k_write_memory_16(dsta,src); | |
287 | }}}}m68k_incpc(6); | |
288 | return 20; | |
289 | } | |
290 | unsigned long CPUFUNC(op_70_4)(uint32_t opcode) /* OR */ | |
291 | { | |
292 | uint32_t dstreg = opcode & 7; | |
293 | OpcodeFamily = 1; CurrentInstrCycles = 22; | |
294 | {{ int16_t src = get_iword(2); | |
295 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); | |
296 | BusCyclePenalty += 2; | |
297 | { int16_t dst = m68k_read_memory_16(dsta); | |
298 | src |= dst; | |
299 | CLEAR_CZNV; | |
300 | SET_ZFLG (((int16_t)(src)) == 0); | |
301 | SET_NFLG (((int16_t)(src)) < 0); | |
302 | m68k_write_memory_16(dsta,src); | |
303 | }}}}m68k_incpc(6); | |
304 | return 22; | |
305 | } | |
306 | unsigned long CPUFUNC(op_78_4)(uint32_t opcode) /* OR */ | |
307 | { | |
308 | OpcodeFamily = 1; CurrentInstrCycles = 20; | |
309 | {{ int16_t src = get_iword(2); | |
310 | { uint32_t dsta = (int32_t)(int16_t)get_iword(4); | |
311 | { int16_t dst = m68k_read_memory_16(dsta); | |
312 | src |= dst; | |
313 | CLEAR_CZNV; | |
314 | SET_ZFLG (((int16_t)(src)) == 0); | |
315 | SET_NFLG (((int16_t)(src)) < 0); | |
316 | m68k_write_memory_16(dsta,src); | |
317 | }}}}m68k_incpc(6); | |
318 | return 20; | |
319 | } | |
320 | unsigned long CPUFUNC(op_79_4)(uint32_t opcode) /* OR */ | |
321 | { | |
322 | OpcodeFamily = 1; CurrentInstrCycles = 24; | |
323 | {{ int16_t src = get_iword(2); | |
324 | { uint32_t dsta = get_ilong(4); | |
325 | { int16_t dst = m68k_read_memory_16(dsta); | |
326 | src |= dst; | |
327 | CLEAR_CZNV; | |
328 | SET_ZFLG (((int16_t)(src)) == 0); | |
329 | SET_NFLG (((int16_t)(src)) < 0); | |
330 | m68k_write_memory_16(dsta,src); | |
331 | }}}}m68k_incpc(8); | |
332 | return 24; | |
333 | } | |
334 | unsigned long CPUFUNC(op_7c_4)(uint32_t opcode) /* ORSR */ | |
335 | { | |
336 | OpcodeFamily = 4; CurrentInstrCycles = 20; | |
337 | {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel18; } | |
338 | { MakeSR(); | |
339 | { int16_t src = get_iword(2); | |
340 | regs.sr |= src; | |
341 | MakeFromSR(); | |
342 | }}}m68k_incpc(4); | |
343 | endlabel18: ; | |
344 | return 20; | |
345 | } | |
346 | unsigned long CPUFUNC(op_80_4)(uint32_t opcode) /* OR */ | |
347 | { | |
348 | uint32_t dstreg = opcode & 7; | |
349 | OpcodeFamily = 1; CurrentInstrCycles = 16; | |
350 | {{ int32_t src = get_ilong(2); | |
351 | { int32_t dst = m68k_dreg(regs, dstreg); | |
352 | src |= dst; | |
353 | CLEAR_CZNV; | |
354 | SET_ZFLG (((int32_t)(src)) == 0); | |
355 | SET_NFLG (((int32_t)(src)) < 0); | |
356 | m68k_dreg(regs, dstreg) = (src); | |
357 | }}}m68k_incpc(6); | |
358 | return 16; | |
359 | } | |
360 | unsigned long CPUFUNC(op_90_4)(uint32_t opcode) /* OR */ | |
361 | { | |
362 | uint32_t dstreg = opcode & 7; | |
363 | OpcodeFamily = 1; CurrentInstrCycles = 28; | |
364 | {{ int32_t src = get_ilong(2); | |
365 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
366 | { int32_t dst = m68k_read_memory_32(dsta); | |
367 | src |= dst; | |
368 | CLEAR_CZNV; | |
369 | SET_ZFLG (((int32_t)(src)) == 0); | |
370 | SET_NFLG (((int32_t)(src)) < 0); | |
371 | m68k_write_memory_32(dsta,src); | |
372 | }}}}m68k_incpc(6); | |
373 | return 28; | |
374 | } | |
375 | unsigned long CPUFUNC(op_98_4)(uint32_t opcode) /* OR */ | |
376 | { | |
377 | uint32_t dstreg = opcode & 7; | |
378 | OpcodeFamily = 1; CurrentInstrCycles = 28; | |
379 | {{ int32_t src = get_ilong(2); | |
380 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
381 | { int32_t dst = m68k_read_memory_32(dsta); | |
382 | m68k_areg(regs, dstreg) += 4; | |
383 | src |= dst; | |
384 | CLEAR_CZNV; | |
385 | SET_ZFLG (((int32_t)(src)) == 0); | |
386 | SET_NFLG (((int32_t)(src)) < 0); | |
387 | m68k_write_memory_32(dsta,src); | |
388 | }}}}m68k_incpc(6); | |
389 | return 28; | |
390 | } | |
391 | unsigned long CPUFUNC(op_a0_4)(uint32_t opcode) /* OR */ | |
392 | { | |
393 | uint32_t dstreg = opcode & 7; | |
394 | OpcodeFamily = 1; CurrentInstrCycles = 30; | |
395 | {{ int32_t src = get_ilong(2); | |
396 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
397 | { int32_t dst = m68k_read_memory_32(dsta); | |
398 | m68k_areg (regs, dstreg) = dsta; | |
399 | src |= dst; | |
400 | CLEAR_CZNV; | |
401 | SET_ZFLG (((int32_t)(src)) == 0); | |
402 | SET_NFLG (((int32_t)(src)) < 0); | |
403 | m68k_write_memory_32(dsta,src); | |
404 | }}}}m68k_incpc(6); | |
405 | return 30; | |
406 | } | |
407 | unsigned long CPUFUNC(op_a8_4)(uint32_t opcode) /* OR */ | |
408 | { | |
409 | uint32_t dstreg = opcode & 7; | |
410 | OpcodeFamily = 1; CurrentInstrCycles = 32; | |
411 | {{ int32_t src = get_ilong(2); | |
412 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(6); | |
413 | { int32_t dst = m68k_read_memory_32(dsta); | |
414 | src |= dst; | |
415 | CLEAR_CZNV; | |
416 | SET_ZFLG (((int32_t)(src)) == 0); | |
417 | SET_NFLG (((int32_t)(src)) < 0); | |
418 | m68k_write_memory_32(dsta,src); | |
419 | }}}}m68k_incpc(8); | |
420 | return 32; | |
421 | } | |
422 | unsigned long CPUFUNC(op_b0_4)(uint32_t opcode) /* OR */ | |
423 | { | |
424 | uint32_t dstreg = opcode & 7; | |
425 | OpcodeFamily = 1; CurrentInstrCycles = 34; | |
426 | {{ int32_t src = get_ilong(2); | |
427 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(6)); | |
428 | BusCyclePenalty += 2; | |
429 | { int32_t dst = m68k_read_memory_32(dsta); | |
430 | src |= dst; | |
431 | CLEAR_CZNV; | |
432 | SET_ZFLG (((int32_t)(src)) == 0); | |
433 | SET_NFLG (((int32_t)(src)) < 0); | |
434 | m68k_write_memory_32(dsta,src); | |
435 | }}}}m68k_incpc(8); | |
436 | return 34; | |
437 | } | |
438 | unsigned long CPUFUNC(op_b8_4)(uint32_t opcode) /* OR */ | |
439 | { | |
440 | OpcodeFamily = 1; CurrentInstrCycles = 32; | |
441 | {{ int32_t src = get_ilong(2); | |
442 | { uint32_t dsta = (int32_t)(int16_t)get_iword(6); | |
443 | { int32_t dst = m68k_read_memory_32(dsta); | |
444 | src |= dst; | |
445 | CLEAR_CZNV; | |
446 | SET_ZFLG (((int32_t)(src)) == 0); | |
447 | SET_NFLG (((int32_t)(src)) < 0); | |
448 | m68k_write_memory_32(dsta,src); | |
449 | }}}}m68k_incpc(8); | |
450 | return 32; | |
451 | } | |
452 | unsigned long CPUFUNC(op_b9_4)(uint32_t opcode) /* OR */ | |
453 | { | |
454 | OpcodeFamily = 1; CurrentInstrCycles = 36; | |
455 | {{ int32_t src = get_ilong(2); | |
456 | { uint32_t dsta = get_ilong(6); | |
457 | { int32_t dst = m68k_read_memory_32(dsta); | |
458 | src |= dst; | |
459 | CLEAR_CZNV; | |
460 | SET_ZFLG (((int32_t)(src)) == 0); | |
461 | SET_NFLG (((int32_t)(src)) < 0); | |
462 | m68k_write_memory_32(dsta,src); | |
463 | }}}}m68k_incpc(10); | |
464 | return 36; | |
465 | } | |
466 | unsigned long CPUFUNC(op_100_4)(uint32_t opcode) /* BTST */ | |
467 | { | |
468 | uint32_t srcreg = ((opcode >> 9) & 7); | |
469 | uint32_t dstreg = opcode & 7; | |
470 | OpcodeFamily = 21; CurrentInstrCycles = 6; | |
471 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
472 | { int32_t dst = m68k_dreg(regs, dstreg); | |
473 | src &= 31; | |
474 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
475 | }}}m68k_incpc(2); | |
476 | return 6; | |
477 | } | |
478 | unsigned long CPUFUNC(op_108_4)(uint32_t opcode) /* MVPMR */ | |
479 | { | |
480 | uint32_t srcreg = (opcode & 7); | |
481 | uint32_t dstreg = (opcode >> 9) & 7; | |
482 | OpcodeFamily = 29; CurrentInstrCycles = 16; | |
483 | { uint32_t memp = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
484 | { uint16_t val = (m68k_read_memory_8(memp) << 8) + m68k_read_memory_8(memp + 2); | |
485 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); | |
486 | }}m68k_incpc(4); | |
487 | return 16; | |
488 | } | |
489 | unsigned long CPUFUNC(op_110_4)(uint32_t opcode) /* BTST */ | |
490 | { | |
491 | uint32_t srcreg = ((opcode >> 9) & 7); | |
492 | uint32_t dstreg = opcode & 7; | |
493 | OpcodeFamily = 21; CurrentInstrCycles = 8; | |
494 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
495 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
496 | { int8_t dst = m68k_read_memory_8(dsta); | |
497 | src &= 7; | |
498 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
499 | }}}}m68k_incpc(2); | |
500 | return 8; | |
501 | } | |
502 | unsigned long CPUFUNC(op_118_4)(uint32_t opcode) /* BTST */ | |
503 | { | |
504 | uint32_t srcreg = ((opcode >> 9) & 7); | |
505 | uint32_t dstreg = opcode & 7; | |
506 | OpcodeFamily = 21; CurrentInstrCycles = 8; | |
507 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
508 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
509 | { int8_t dst = m68k_read_memory_8(dsta); | |
510 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
511 | src &= 7; | |
512 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
513 | }}}}m68k_incpc(2); | |
514 | return 8; | |
515 | } | |
516 | unsigned long CPUFUNC(op_120_4)(uint32_t opcode) /* BTST */ | |
517 | { | |
518 | uint32_t srcreg = ((opcode >> 9) & 7); | |
519 | uint32_t dstreg = opcode & 7; | |
520 | OpcodeFamily = 21; CurrentInstrCycles = 10; | |
521 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
522 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
523 | { int8_t dst = m68k_read_memory_8(dsta); | |
524 | m68k_areg (regs, dstreg) = dsta; | |
525 | src &= 7; | |
526 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
527 | }}}}m68k_incpc(2); | |
528 | return 10; | |
529 | } | |
530 | unsigned long CPUFUNC(op_128_4)(uint32_t opcode) /* BTST */ | |
531 | { | |
532 | uint32_t srcreg = ((opcode >> 9) & 7); | |
533 | uint32_t dstreg = opcode & 7; | |
534 | OpcodeFamily = 21; CurrentInstrCycles = 12; | |
535 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
536 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); | |
537 | { int8_t dst = m68k_read_memory_8(dsta); | |
538 | src &= 7; | |
539 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
540 | }}}}m68k_incpc(4); | |
541 | return 12; | |
542 | } | |
543 | unsigned long CPUFUNC(op_130_4)(uint32_t opcode) /* BTST */ | |
544 | { | |
545 | uint32_t srcreg = ((opcode >> 9) & 7); | |
546 | uint32_t dstreg = opcode & 7; | |
547 | OpcodeFamily = 21; CurrentInstrCycles = 14; | |
548 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
549 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); | |
550 | BusCyclePenalty += 2; | |
551 | { int8_t dst = m68k_read_memory_8(dsta); | |
552 | src &= 7; | |
553 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
554 | }}}}m68k_incpc(4); | |
555 | return 14; | |
556 | } | |
557 | unsigned long CPUFUNC(op_138_4)(uint32_t opcode) /* BTST */ | |
558 | { | |
559 | uint32_t srcreg = ((opcode >> 9) & 7); | |
560 | OpcodeFamily = 21; CurrentInstrCycles = 12; | |
561 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
562 | { uint32_t dsta = (int32_t)(int16_t)get_iword(2); | |
563 | { int8_t dst = m68k_read_memory_8(dsta); | |
564 | src &= 7; | |
565 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
566 | }}}}m68k_incpc(4); | |
567 | return 12; | |
568 | } | |
569 | unsigned long CPUFUNC(op_139_4)(uint32_t opcode) /* BTST */ | |
570 | { | |
571 | uint32_t srcreg = ((opcode >> 9) & 7); | |
572 | OpcodeFamily = 21; CurrentInstrCycles = 16; | |
573 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
574 | { uint32_t dsta = get_ilong(2); | |
575 | { int8_t dst = m68k_read_memory_8(dsta); | |
576 | src &= 7; | |
577 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
578 | }}}}m68k_incpc(6); | |
579 | return 16; | |
580 | } | |
581 | unsigned long CPUFUNC(op_13a_4)(uint32_t opcode) /* BTST */ | |
582 | { | |
583 | uint32_t srcreg = ((opcode >> 9) & 7); | |
584 | uint32_t dstreg = 2; | |
585 | OpcodeFamily = 21; CurrentInstrCycles = 12; | |
586 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
587 | { uint32_t dsta = m68k_getpc () + 2; | |
588 | dsta += (int32_t)(int16_t)get_iword(2); | |
589 | { int8_t dst = m68k_read_memory_8(dsta); | |
590 | src &= 7; | |
591 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
592 | }}}}m68k_incpc(4); | |
593 | return 12; | |
594 | } | |
595 | unsigned long CPUFUNC(op_13b_4)(uint32_t opcode) /* BTST */ | |
596 | { | |
597 | uint32_t srcreg = ((opcode >> 9) & 7); | |
598 | uint32_t dstreg = 3; | |
599 | OpcodeFamily = 21; CurrentInstrCycles = 14; | |
600 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
601 | { uint32_t tmppc = m68k_getpc() + 2; | |
602 | uint32_t dsta = get_disp_ea_000(tmppc, get_iword(2)); | |
603 | BusCyclePenalty += 2; | |
604 | { int8_t dst = m68k_read_memory_8(dsta); | |
605 | src &= 7; | |
606 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
607 | }}}}m68k_incpc(4); | |
608 | return 14; | |
609 | } | |
610 | unsigned long CPUFUNC(op_13c_4)(uint32_t opcode) /* BTST */ | |
611 | { | |
612 | uint32_t srcreg = ((opcode >> 9) & 7); | |
613 | OpcodeFamily = 21; CurrentInstrCycles = 8; | |
614 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
615 | { int8_t dst = get_ibyte(2); | |
616 | src &= 7; | |
617 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
618 | }}}m68k_incpc(4); | |
619 | return 8; | |
620 | } | |
621 | unsigned long CPUFUNC(op_140_4)(uint32_t opcode) /* BCHG */ | |
622 | { | |
623 | uint32_t srcreg = ((opcode >> 9) & 7); | |
624 | uint32_t dstreg = opcode & 7; | |
625 | OpcodeFamily = 22; CurrentInstrCycles = 8; | |
626 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
627 | { int32_t dst = m68k_dreg(regs, dstreg); | |
628 | src &= 31; | |
629 | dst ^= (1 << src); | |
630 | SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); | |
631 | m68k_dreg(regs, dstreg) = (dst); | |
632 | }}}m68k_incpc(2); | |
633 | return 8; | |
634 | } | |
635 | unsigned long CPUFUNC(op_148_4)(uint32_t opcode) /* MVPMR */ | |
636 | { | |
637 | uint32_t srcreg = (opcode & 7); | |
638 | uint32_t dstreg = (opcode >> 9) & 7; | |
639 | OpcodeFamily = 29; CurrentInstrCycles = 24; | |
640 | { uint32_t memp = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
641 | { uint32_t val = (m68k_read_memory_8(memp) << 24) + (m68k_read_memory_8(memp + 2) << 16) | |
642 | + (m68k_read_memory_8(memp + 4) << 8) + m68k_read_memory_8(memp + 6); | |
643 | m68k_dreg(regs, dstreg) = (val); | |
644 | }}m68k_incpc(4); | |
645 | return 24; | |
646 | } | |
647 | unsigned long CPUFUNC(op_150_4)(uint32_t opcode) /* BCHG */ | |
648 | { | |
649 | uint32_t srcreg = ((opcode >> 9) & 7); | |
650 | uint32_t dstreg = opcode & 7; | |
651 | OpcodeFamily = 22; CurrentInstrCycles = 12; | |
652 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
653 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
654 | { int8_t dst = m68k_read_memory_8(dsta); | |
655 | src &= 7; | |
656 | dst ^= (1 << src); | |
657 | SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); | |
658 | m68k_write_memory_8(dsta,dst); | |
659 | }}}}m68k_incpc(2); | |
660 | return 12; | |
661 | } | |
662 | unsigned long CPUFUNC(op_158_4)(uint32_t opcode) /* BCHG */ | |
663 | { | |
664 | uint32_t srcreg = ((opcode >> 9) & 7); | |
665 | uint32_t dstreg = opcode & 7; | |
666 | OpcodeFamily = 22; CurrentInstrCycles = 12; | |
667 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
668 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
669 | { int8_t dst = m68k_read_memory_8(dsta); | |
670 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
671 | src &= 7; | |
672 | dst ^= (1 << src); | |
673 | SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); | |
674 | m68k_write_memory_8(dsta,dst); | |
675 | }}}}m68k_incpc(2); | |
676 | return 12; | |
677 | } | |
678 | unsigned long CPUFUNC(op_160_4)(uint32_t opcode) /* BCHG */ | |
679 | { | |
680 | uint32_t srcreg = ((opcode >> 9) & 7); | |
681 | uint32_t dstreg = opcode & 7; | |
682 | OpcodeFamily = 22; CurrentInstrCycles = 14; | |
683 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
684 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
685 | { int8_t dst = m68k_read_memory_8(dsta); | |
686 | m68k_areg (regs, dstreg) = dsta; | |
687 | src &= 7; | |
688 | dst ^= (1 << src); | |
689 | SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); | |
690 | m68k_write_memory_8(dsta,dst); | |
691 | }}}}m68k_incpc(2); | |
692 | return 14; | |
693 | } | |
694 | unsigned long CPUFUNC(op_168_4)(uint32_t opcode) /* BCHG */ | |
695 | { | |
696 | uint32_t srcreg = ((opcode >> 9) & 7); | |
697 | uint32_t dstreg = opcode & 7; | |
698 | OpcodeFamily = 22; CurrentInstrCycles = 16; | |
699 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
700 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); | |
701 | { int8_t dst = m68k_read_memory_8(dsta); | |
702 | src &= 7; | |
703 | dst ^= (1 << src); | |
704 | SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); | |
705 | m68k_write_memory_8(dsta,dst); | |
706 | }}}}m68k_incpc(4); | |
707 | return 16; | |
708 | } | |
709 | unsigned long CPUFUNC(op_170_4)(uint32_t opcode) /* BCHG */ | |
710 | { | |
711 | uint32_t srcreg = ((opcode >> 9) & 7); | |
712 | uint32_t dstreg = opcode & 7; | |
713 | OpcodeFamily = 22; CurrentInstrCycles = 18; | |
714 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
715 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); | |
716 | BusCyclePenalty += 2; | |
717 | { int8_t dst = m68k_read_memory_8(dsta); | |
718 | src &= 7; | |
719 | dst ^= (1 << src); | |
720 | SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); | |
721 | m68k_write_memory_8(dsta,dst); | |
722 | }}}}m68k_incpc(4); | |
723 | return 18; | |
724 | } | |
725 | unsigned long CPUFUNC(op_178_4)(uint32_t opcode) /* BCHG */ | |
726 | { | |
727 | uint32_t srcreg = ((opcode >> 9) & 7); | |
728 | OpcodeFamily = 22; CurrentInstrCycles = 16; | |
729 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
730 | { uint32_t dsta = (int32_t)(int16_t)get_iword(2); | |
731 | { int8_t dst = m68k_read_memory_8(dsta); | |
732 | src &= 7; | |
733 | dst ^= (1 << src); | |
734 | SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); | |
735 | m68k_write_memory_8(dsta,dst); | |
736 | }}}}m68k_incpc(4); | |
737 | return 16; | |
738 | } | |
739 | unsigned long CPUFUNC(op_179_4)(uint32_t opcode) /* BCHG */ | |
740 | { | |
741 | uint32_t srcreg = ((opcode >> 9) & 7); | |
742 | OpcodeFamily = 22; CurrentInstrCycles = 20; | |
743 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
744 | { uint32_t dsta = get_ilong(2); | |
745 | { int8_t dst = m68k_read_memory_8(dsta); | |
746 | src &= 7; | |
747 | dst ^= (1 << src); | |
748 | SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); | |
749 | m68k_write_memory_8(dsta,dst); | |
750 | }}}}m68k_incpc(6); | |
751 | return 20; | |
752 | } | |
753 | unsigned long CPUFUNC(op_17a_4)(uint32_t opcode) /* BCHG */ | |
754 | { | |
755 | uint32_t srcreg = ((opcode >> 9) & 7); | |
756 | uint32_t dstreg = 2; | |
757 | OpcodeFamily = 22; CurrentInstrCycles = 16; | |
758 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
759 | { uint32_t dsta = m68k_getpc () + 2; | |
760 | dsta += (int32_t)(int16_t)get_iword(2); | |
761 | { int8_t dst = m68k_read_memory_8(dsta); | |
762 | src &= 7; | |
763 | dst ^= (1 << src); | |
764 | SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); | |
765 | m68k_write_memory_8(dsta,dst); | |
766 | }}}}m68k_incpc(4); | |
767 | return 16; | |
768 | } | |
769 | unsigned long CPUFUNC(op_17b_4)(uint32_t opcode) /* BCHG */ | |
770 | { | |
771 | uint32_t srcreg = ((opcode >> 9) & 7); | |
772 | uint32_t dstreg = 3; | |
773 | OpcodeFamily = 22; CurrentInstrCycles = 18; | |
774 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
775 | { uint32_t tmppc = m68k_getpc() + 2; | |
776 | uint32_t dsta = get_disp_ea_000(tmppc, get_iword(2)); | |
777 | BusCyclePenalty += 2; | |
778 | { int8_t dst = m68k_read_memory_8(dsta); | |
779 | src &= 7; | |
780 | dst ^= (1 << src); | |
781 | SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); | |
782 | m68k_write_memory_8(dsta,dst); | |
783 | }}}}m68k_incpc(4); | |
784 | return 18; | |
785 | } | |
786 | unsigned long CPUFUNC(op_180_4)(uint32_t opcode) /* BCLR */ | |
787 | { | |
788 | uint32_t srcreg = ((opcode >> 9) & 7); | |
789 | uint32_t dstreg = opcode & 7; | |
790 | OpcodeFamily = 23; CurrentInstrCycles = 10; | |
791 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
792 | { int32_t dst = m68k_dreg(regs, dstreg); | |
793 | src &= 31; | |
794 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
795 | dst &= ~(1 << src); | |
796 | m68k_dreg(regs, dstreg) = (dst); | |
797 | if ( src < 16 ) { m68k_incpc(2); return 8; } | |
798 | }}}m68k_incpc(2); | |
799 | return 10; | |
800 | } | |
801 | unsigned long CPUFUNC(op_188_4)(uint32_t opcode) /* MVPRM */ | |
802 | { | |
803 | uint32_t srcreg = ((opcode >> 9) & 7); | |
804 | uint32_t dstreg = opcode & 7; | |
805 | OpcodeFamily = 28; CurrentInstrCycles = 16; | |
806 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
807 | uint32_t memp = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); | |
808 | m68k_write_memory_8(memp, src >> 8); m68k_write_memory_8(memp + 2, src); | |
809 | }}m68k_incpc(4); | |
810 | return 16; | |
811 | } | |
812 | unsigned long CPUFUNC(op_190_4)(uint32_t opcode) /* BCLR */ | |
813 | { | |
814 | uint32_t srcreg = ((opcode >> 9) & 7); | |
815 | uint32_t dstreg = opcode & 7; | |
816 | OpcodeFamily = 23; CurrentInstrCycles = 12; | |
817 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
818 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
819 | { int8_t dst = m68k_read_memory_8(dsta); | |
820 | src &= 7; | |
821 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
822 | dst &= ~(1 << src); | |
823 | m68k_write_memory_8(dsta,dst); | |
824 | }}}}m68k_incpc(2); | |
825 | return 12; | |
826 | } | |
827 | unsigned long CPUFUNC(op_198_4)(uint32_t opcode) /* BCLR */ | |
828 | { | |
829 | uint32_t srcreg = ((opcode >> 9) & 7); | |
830 | uint32_t dstreg = opcode & 7; | |
831 | OpcodeFamily = 23; CurrentInstrCycles = 12; | |
832 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
833 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
834 | { int8_t dst = m68k_read_memory_8(dsta); | |
835 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
836 | src &= 7; | |
837 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
838 | dst &= ~(1 << src); | |
839 | m68k_write_memory_8(dsta,dst); | |
840 | }}}}m68k_incpc(2); | |
841 | return 12; | |
842 | } | |
843 | unsigned long CPUFUNC(op_1a0_4)(uint32_t opcode) /* BCLR */ | |
844 | { | |
845 | uint32_t srcreg = ((opcode >> 9) & 7); | |
846 | uint32_t dstreg = opcode & 7; | |
847 | OpcodeFamily = 23; CurrentInstrCycles = 14; | |
848 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
849 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
850 | { int8_t dst = m68k_read_memory_8(dsta); | |
851 | m68k_areg (regs, dstreg) = dsta; | |
852 | src &= 7; | |
853 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
854 | dst &= ~(1 << src); | |
855 | m68k_write_memory_8(dsta,dst); | |
856 | }}}}m68k_incpc(2); | |
857 | return 14; | |
858 | } | |
859 | unsigned long CPUFUNC(op_1a8_4)(uint32_t opcode) /* BCLR */ | |
860 | { | |
861 | uint32_t srcreg = ((opcode >> 9) & 7); | |
862 | uint32_t dstreg = opcode & 7; | |
863 | OpcodeFamily = 23; CurrentInstrCycles = 16; | |
864 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
865 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); | |
866 | { int8_t dst = m68k_read_memory_8(dsta); | |
867 | src &= 7; | |
868 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
869 | dst &= ~(1 << src); | |
870 | m68k_write_memory_8(dsta,dst); | |
871 | }}}}m68k_incpc(4); | |
872 | return 16; | |
873 | } | |
874 | unsigned long CPUFUNC(op_1b0_4)(uint32_t opcode) /* BCLR */ | |
875 | { | |
876 | uint32_t srcreg = ((opcode >> 9) & 7); | |
877 | uint32_t dstreg = opcode & 7; | |
878 | OpcodeFamily = 23; CurrentInstrCycles = 18; | |
879 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
880 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); | |
881 | BusCyclePenalty += 2; | |
882 | { int8_t dst = m68k_read_memory_8(dsta); | |
883 | src &= 7; | |
884 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
885 | dst &= ~(1 << src); | |
886 | m68k_write_memory_8(dsta,dst); | |
887 | }}}}m68k_incpc(4); | |
888 | return 18; | |
889 | } | |
890 | unsigned long CPUFUNC(op_1b8_4)(uint32_t opcode) /* BCLR */ | |
891 | { | |
892 | uint32_t srcreg = ((opcode >> 9) & 7); | |
893 | OpcodeFamily = 23; CurrentInstrCycles = 16; | |
894 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
895 | { uint32_t dsta = (int32_t)(int16_t)get_iword(2); | |
896 | { int8_t dst = m68k_read_memory_8(dsta); | |
897 | src &= 7; | |
898 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
899 | dst &= ~(1 << src); | |
900 | m68k_write_memory_8(dsta,dst); | |
901 | }}}}m68k_incpc(4); | |
902 | return 16; | |
903 | } | |
904 | unsigned long CPUFUNC(op_1b9_4)(uint32_t opcode) /* BCLR */ | |
905 | { | |
906 | uint32_t srcreg = ((opcode >> 9) & 7); | |
907 | OpcodeFamily = 23; CurrentInstrCycles = 20; | |
908 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
909 | { uint32_t dsta = get_ilong(2); | |
910 | { int8_t dst = m68k_read_memory_8(dsta); | |
911 | src &= 7; | |
912 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
913 | dst &= ~(1 << src); | |
914 | m68k_write_memory_8(dsta,dst); | |
915 | }}}}m68k_incpc(6); | |
916 | return 20; | |
917 | } | |
918 | unsigned long CPUFUNC(op_1ba_4)(uint32_t opcode) /* BCLR */ | |
919 | { | |
920 | uint32_t srcreg = ((opcode >> 9) & 7); | |
921 | uint32_t dstreg = 2; | |
922 | OpcodeFamily = 23; CurrentInstrCycles = 16; | |
923 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
924 | { uint32_t dsta = m68k_getpc () + 2; | |
925 | dsta += (int32_t)(int16_t)get_iword(2); | |
926 | { int8_t dst = m68k_read_memory_8(dsta); | |
927 | src &= 7; | |
928 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
929 | dst &= ~(1 << src); | |
930 | m68k_write_memory_8(dsta,dst); | |
931 | }}}}m68k_incpc(4); | |
932 | return 16; | |
933 | } | |
934 | unsigned long CPUFUNC(op_1bb_4)(uint32_t opcode) /* BCLR */ | |
935 | { | |
936 | uint32_t srcreg = ((opcode >> 9) & 7); | |
937 | uint32_t dstreg = 3; | |
938 | OpcodeFamily = 23; CurrentInstrCycles = 18; | |
939 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
940 | { uint32_t tmppc = m68k_getpc() + 2; | |
941 | uint32_t dsta = get_disp_ea_000(tmppc, get_iword(2)); | |
942 | BusCyclePenalty += 2; | |
943 | { int8_t dst = m68k_read_memory_8(dsta); | |
944 | src &= 7; | |
945 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
946 | dst &= ~(1 << src); | |
947 | m68k_write_memory_8(dsta,dst); | |
948 | }}}}m68k_incpc(4); | |
949 | return 18; | |
950 | } | |
951 | unsigned long CPUFUNC(op_1c0_4)(uint32_t opcode) /* BSET */ | |
952 | { | |
953 | uint32_t srcreg = ((opcode >> 9) & 7); | |
954 | uint32_t dstreg = opcode & 7; | |
955 | OpcodeFamily = 24; CurrentInstrCycles = 8; | |
956 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
957 | { int32_t dst = m68k_dreg(regs, dstreg); | |
958 | src &= 31; | |
959 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
960 | dst |= (1 << src); | |
961 | m68k_dreg(regs, dstreg) = (dst); | |
962 | }}}m68k_incpc(2); | |
963 | return 8; | |
964 | } | |
965 | unsigned long CPUFUNC(op_1c8_4)(uint32_t opcode) /* MVPRM */ | |
966 | { | |
967 | uint32_t srcreg = ((opcode >> 9) & 7); | |
968 | uint32_t dstreg = opcode & 7; | |
969 | OpcodeFamily = 28; CurrentInstrCycles = 24; | |
970 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
971 | uint32_t memp = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); | |
972 | m68k_write_memory_8(memp, src >> 24); m68k_write_memory_8(memp + 2, src >> 16); | |
973 | m68k_write_memory_8(memp + 4, src >> 8); m68k_write_memory_8(memp + 6, src); | |
974 | }}m68k_incpc(4); | |
975 | return 24; | |
976 | } | |
977 | unsigned long CPUFUNC(op_1d0_4)(uint32_t opcode) /* BSET */ | |
978 | { | |
979 | uint32_t srcreg = ((opcode >> 9) & 7); | |
980 | uint32_t dstreg = opcode & 7; | |
981 | OpcodeFamily = 24; CurrentInstrCycles = 12; | |
982 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
983 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
984 | { int8_t dst = m68k_read_memory_8(dsta); | |
985 | src &= 7; | |
986 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
987 | dst |= (1 << src); | |
988 | m68k_write_memory_8(dsta,dst); | |
989 | }}}}m68k_incpc(2); | |
990 | return 12; | |
991 | } | |
992 | unsigned long CPUFUNC(op_1d8_4)(uint32_t opcode) /* BSET */ | |
993 | { | |
994 | uint32_t srcreg = ((opcode >> 9) & 7); | |
995 | uint32_t dstreg = opcode & 7; | |
996 | OpcodeFamily = 24; CurrentInstrCycles = 12; | |
997 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
998 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
999 | { int8_t dst = m68k_read_memory_8(dsta); | |
1000 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
1001 | src &= 7; | |
1002 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
1003 | dst |= (1 << src); | |
1004 | m68k_write_memory_8(dsta,dst); | |
1005 | }}}}m68k_incpc(2); | |
1006 | return 12; | |
1007 | } | |
1008 | unsigned long CPUFUNC(op_1e0_4)(uint32_t opcode) /* BSET */ | |
1009 | { | |
1010 | uint32_t srcreg = ((opcode >> 9) & 7); | |
1011 | uint32_t dstreg = opcode & 7; | |
1012 | OpcodeFamily = 24; CurrentInstrCycles = 14; | |
1013 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
1014 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
1015 | { int8_t dst = m68k_read_memory_8(dsta); | |
1016 | m68k_areg (regs, dstreg) = dsta; | |
1017 | src &= 7; | |
1018 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
1019 | dst |= (1 << src); | |
1020 | m68k_write_memory_8(dsta,dst); | |
1021 | }}}}m68k_incpc(2); | |
1022 | return 14; | |
1023 | } | |
1024 | unsigned long CPUFUNC(op_1e8_4)(uint32_t opcode) /* BSET */ | |
1025 | { | |
1026 | uint32_t srcreg = ((opcode >> 9) & 7); | |
1027 | uint32_t dstreg = opcode & 7; | |
1028 | OpcodeFamily = 24; CurrentInstrCycles = 16; | |
1029 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
1030 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); | |
1031 | { int8_t dst = m68k_read_memory_8(dsta); | |
1032 | src &= 7; | |
1033 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
1034 | dst |= (1 << src); | |
1035 | m68k_write_memory_8(dsta,dst); | |
1036 | }}}}m68k_incpc(4); | |
1037 | return 16; | |
1038 | } | |
1039 | unsigned long CPUFUNC(op_1f0_4)(uint32_t opcode) /* BSET */ | |
1040 | { | |
1041 | uint32_t srcreg = ((opcode >> 9) & 7); | |
1042 | uint32_t dstreg = opcode & 7; | |
1043 | OpcodeFamily = 24; CurrentInstrCycles = 18; | |
1044 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
1045 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); | |
1046 | BusCyclePenalty += 2; | |
1047 | { int8_t dst = m68k_read_memory_8(dsta); | |
1048 | src &= 7; | |
1049 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
1050 | dst |= (1 << src); | |
1051 | m68k_write_memory_8(dsta,dst); | |
1052 | }}}}m68k_incpc(4); | |
1053 | return 18; | |
1054 | } | |
1055 | unsigned long CPUFUNC(op_1f8_4)(uint32_t opcode) /* BSET */ | |
1056 | { | |
1057 | uint32_t srcreg = ((opcode >> 9) & 7); | |
1058 | OpcodeFamily = 24; CurrentInstrCycles = 16; | |
1059 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
1060 | { uint32_t dsta = (int32_t)(int16_t)get_iword(2); | |
1061 | { int8_t dst = m68k_read_memory_8(dsta); | |
1062 | src &= 7; | |
1063 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
1064 | dst |= (1 << src); | |
1065 | m68k_write_memory_8(dsta,dst); | |
1066 | }}}}m68k_incpc(4); | |
1067 | return 16; | |
1068 | } | |
1069 | unsigned long CPUFUNC(op_1f9_4)(uint32_t opcode) /* BSET */ | |
1070 | { | |
1071 | uint32_t srcreg = ((opcode >> 9) & 7); | |
1072 | OpcodeFamily = 24; CurrentInstrCycles = 20; | |
1073 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
1074 | { uint32_t dsta = get_ilong(2); | |
1075 | { int8_t dst = m68k_read_memory_8(dsta); | |
1076 | src &= 7; | |
1077 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
1078 | dst |= (1 << src); | |
1079 | m68k_write_memory_8(dsta,dst); | |
1080 | }}}}m68k_incpc(6); | |
1081 | return 20; | |
1082 | } | |
1083 | unsigned long CPUFUNC(op_1fa_4)(uint32_t opcode) /* BSET */ | |
1084 | { | |
1085 | uint32_t srcreg = ((opcode >> 9) & 7); | |
1086 | uint32_t dstreg = 2; | |
1087 | OpcodeFamily = 24; CurrentInstrCycles = 16; | |
1088 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
1089 | { uint32_t dsta = m68k_getpc () + 2; | |
1090 | dsta += (int32_t)(int16_t)get_iword(2); | |
1091 | { int8_t dst = m68k_read_memory_8(dsta); | |
1092 | src &= 7; | |
1093 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
1094 | dst |= (1 << src); | |
1095 | m68k_write_memory_8(dsta,dst); | |
1096 | }}}}m68k_incpc(4); | |
1097 | return 16; | |
1098 | } | |
1099 | unsigned long CPUFUNC(op_1fb_4)(uint32_t opcode) /* BSET */ | |
1100 | { | |
1101 | uint32_t srcreg = ((opcode >> 9) & 7); | |
1102 | uint32_t dstreg = 3; | |
1103 | OpcodeFamily = 24; CurrentInstrCycles = 18; | |
1104 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
1105 | { uint32_t tmppc = m68k_getpc() + 2; | |
1106 | uint32_t dsta = get_disp_ea_000(tmppc, get_iword(2)); | |
1107 | BusCyclePenalty += 2; | |
1108 | { int8_t dst = m68k_read_memory_8(dsta); | |
1109 | src &= 7; | |
1110 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
1111 | dst |= (1 << src); | |
1112 | m68k_write_memory_8(dsta,dst); | |
1113 | }}}}m68k_incpc(4); | |
1114 | return 18; | |
1115 | } | |
1116 | unsigned long CPUFUNC(op_200_4)(uint32_t opcode) /* AND */ | |
1117 | { | |
1118 | uint32_t dstreg = opcode & 7; | |
1119 | OpcodeFamily = 2; CurrentInstrCycles = 8; | |
1120 | {{ int8_t src = get_ibyte(2); | |
1121 | { int8_t dst = m68k_dreg(regs, dstreg); | |
1122 | src &= dst; | |
1123 | CLEAR_CZNV; | |
1124 | SET_ZFLG (((int8_t)(src)) == 0); | |
1125 | SET_NFLG (((int8_t)(src)) < 0); | |
1126 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
1127 | }}}m68k_incpc(4); | |
1128 | return 8; | |
1129 | } | |
1130 | unsigned long CPUFUNC(op_210_4)(uint32_t opcode) /* AND */ | |
1131 | { | |
1132 | uint32_t dstreg = opcode & 7; | |
1133 | OpcodeFamily = 2; CurrentInstrCycles = 16; | |
1134 | {{ int8_t src = get_ibyte(2); | |
1135 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
1136 | { int8_t dst = m68k_read_memory_8(dsta); | |
1137 | src &= dst; | |
1138 | CLEAR_CZNV; | |
1139 | SET_ZFLG (((int8_t)(src)) == 0); | |
1140 | SET_NFLG (((int8_t)(src)) < 0); | |
1141 | m68k_write_memory_8(dsta,src); | |
1142 | }}}}m68k_incpc(4); | |
1143 | return 16; | |
1144 | } | |
1145 | unsigned long CPUFUNC(op_218_4)(uint32_t opcode) /* AND */ | |
1146 | { | |
1147 | uint32_t dstreg = opcode & 7; | |
1148 | OpcodeFamily = 2; CurrentInstrCycles = 16; | |
1149 | {{ int8_t src = get_ibyte(2); | |
1150 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
1151 | { int8_t dst = m68k_read_memory_8(dsta); | |
1152 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
1153 | src &= dst; | |
1154 | CLEAR_CZNV; | |
1155 | SET_ZFLG (((int8_t)(src)) == 0); | |
1156 | SET_NFLG (((int8_t)(src)) < 0); | |
1157 | m68k_write_memory_8(dsta,src); | |
1158 | }}}}m68k_incpc(4); | |
1159 | return 16; | |
1160 | } | |
1161 | unsigned long CPUFUNC(op_220_4)(uint32_t opcode) /* AND */ | |
1162 | { | |
1163 | uint32_t dstreg = opcode & 7; | |
1164 | OpcodeFamily = 2; CurrentInstrCycles = 18; | |
1165 | {{ int8_t src = get_ibyte(2); | |
1166 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
1167 | { int8_t dst = m68k_read_memory_8(dsta); | |
1168 | m68k_areg (regs, dstreg) = dsta; | |
1169 | src &= dst; | |
1170 | CLEAR_CZNV; | |
1171 | SET_ZFLG (((int8_t)(src)) == 0); | |
1172 | SET_NFLG (((int8_t)(src)) < 0); | |
1173 | m68k_write_memory_8(dsta,src); | |
1174 | }}}}m68k_incpc(4); | |
1175 | return 18; | |
1176 | } | |
1177 | unsigned long CPUFUNC(op_228_4)(uint32_t opcode) /* AND */ | |
1178 | { | |
1179 | uint32_t dstreg = opcode & 7; | |
1180 | OpcodeFamily = 2; CurrentInstrCycles = 20; | |
1181 | {{ int8_t src = get_ibyte(2); | |
1182 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); | |
1183 | { int8_t dst = m68k_read_memory_8(dsta); | |
1184 | src &= dst; | |
1185 | CLEAR_CZNV; | |
1186 | SET_ZFLG (((int8_t)(src)) == 0); | |
1187 | SET_NFLG (((int8_t)(src)) < 0); | |
1188 | m68k_write_memory_8(dsta,src); | |
1189 | }}}}m68k_incpc(6); | |
1190 | return 20; | |
1191 | } | |
1192 | unsigned long CPUFUNC(op_230_4)(uint32_t opcode) /* AND */ | |
1193 | { | |
1194 | uint32_t dstreg = opcode & 7; | |
1195 | OpcodeFamily = 2; CurrentInstrCycles = 22; | |
1196 | {{ int8_t src = get_ibyte(2); | |
1197 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); | |
1198 | BusCyclePenalty += 2; | |
1199 | { int8_t dst = m68k_read_memory_8(dsta); | |
1200 | src &= dst; | |
1201 | CLEAR_CZNV; | |
1202 | SET_ZFLG (((int8_t)(src)) == 0); | |
1203 | SET_NFLG (((int8_t)(src)) < 0); | |
1204 | m68k_write_memory_8(dsta,src); | |
1205 | }}}}m68k_incpc(6); | |
1206 | return 22; | |
1207 | } | |
1208 | unsigned long CPUFUNC(op_238_4)(uint32_t opcode) /* AND */ | |
1209 | { | |
1210 | OpcodeFamily = 2; CurrentInstrCycles = 20; | |
1211 | {{ int8_t src = get_ibyte(2); | |
1212 | { uint32_t dsta = (int32_t)(int16_t)get_iword(4); | |
1213 | { int8_t dst = m68k_read_memory_8(dsta); | |
1214 | src &= dst; | |
1215 | CLEAR_CZNV; | |
1216 | SET_ZFLG (((int8_t)(src)) == 0); | |
1217 | SET_NFLG (((int8_t)(src)) < 0); | |
1218 | m68k_write_memory_8(dsta,src); | |
1219 | }}}}m68k_incpc(6); | |
1220 | return 20; | |
1221 | } | |
1222 | unsigned long CPUFUNC(op_239_4)(uint32_t opcode) /* AND */ | |
1223 | { | |
1224 | OpcodeFamily = 2; CurrentInstrCycles = 24; | |
1225 | {{ int8_t src = get_ibyte(2); | |
1226 | { uint32_t dsta = get_ilong(4); | |
1227 | { int8_t dst = m68k_read_memory_8(dsta); | |
1228 | src &= dst; | |
1229 | CLEAR_CZNV; | |
1230 | SET_ZFLG (((int8_t)(src)) == 0); | |
1231 | SET_NFLG (((int8_t)(src)) < 0); | |
1232 | m68k_write_memory_8(dsta,src); | |
1233 | }}}}m68k_incpc(8); | |
1234 | return 24; | |
1235 | } | |
1236 | unsigned long CPUFUNC(op_23c_4)(uint32_t opcode) /* ANDSR */ | |
1237 | { | |
1238 | OpcodeFamily = 5; CurrentInstrCycles = 20; | |
1239 | { MakeSR(); | |
1240 | { int16_t src = get_iword(2); | |
1241 | src |= 0xFF00; | |
1242 | regs.sr &= src; | |
1243 | MakeFromSR(); | |
1244 | }}m68k_incpc(4); | |
1245 | return 20; | |
1246 | } | |
1247 | unsigned long CPUFUNC(op_240_4)(uint32_t opcode) /* AND */ | |
1248 | { | |
1249 | uint32_t dstreg = opcode & 7; | |
1250 | OpcodeFamily = 2; CurrentInstrCycles = 8; | |
1251 | {{ int16_t src = get_iword(2); | |
1252 | { int16_t dst = m68k_dreg(regs, dstreg); | |
1253 | src &= dst; | |
1254 | CLEAR_CZNV; | |
1255 | SET_ZFLG (((int16_t)(src)) == 0); | |
1256 | SET_NFLG (((int16_t)(src)) < 0); | |
1257 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
1258 | }}}m68k_incpc(4); | |
1259 | return 8; | |
1260 | } | |
1261 | unsigned long CPUFUNC(op_250_4)(uint32_t opcode) /* AND */ | |
1262 | { | |
1263 | uint32_t dstreg = opcode & 7; | |
1264 | OpcodeFamily = 2; CurrentInstrCycles = 16; | |
1265 | {{ int16_t src = get_iword(2); | |
1266 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
1267 | { int16_t dst = m68k_read_memory_16(dsta); | |
1268 | src &= dst; | |
1269 | CLEAR_CZNV; | |
1270 | SET_ZFLG (((int16_t)(src)) == 0); | |
1271 | SET_NFLG (((int16_t)(src)) < 0); | |
1272 | m68k_write_memory_16(dsta,src); | |
1273 | }}}}m68k_incpc(4); | |
1274 | return 16; | |
1275 | } | |
1276 | unsigned long CPUFUNC(op_258_4)(uint32_t opcode) /* AND */ | |
1277 | { | |
1278 | uint32_t dstreg = opcode & 7; | |
1279 | OpcodeFamily = 2; CurrentInstrCycles = 16; | |
1280 | {{ int16_t src = get_iword(2); | |
1281 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
1282 | { int16_t dst = m68k_read_memory_16(dsta); | |
1283 | m68k_areg(regs, dstreg) += 2; | |
1284 | src &= dst; | |
1285 | CLEAR_CZNV; | |
1286 | SET_ZFLG (((int16_t)(src)) == 0); | |
1287 | SET_NFLG (((int16_t)(src)) < 0); | |
1288 | m68k_write_memory_16(dsta,src); | |
1289 | }}}}m68k_incpc(4); | |
1290 | return 16; | |
1291 | } | |
1292 | unsigned long CPUFUNC(op_260_4)(uint32_t opcode) /* AND */ | |
1293 | { | |
1294 | uint32_t dstreg = opcode & 7; | |
1295 | OpcodeFamily = 2; CurrentInstrCycles = 18; | |
1296 | {{ int16_t src = get_iword(2); | |
1297 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
1298 | { int16_t dst = m68k_read_memory_16(dsta); | |
1299 | m68k_areg (regs, dstreg) = dsta; | |
1300 | src &= dst; | |
1301 | CLEAR_CZNV; | |
1302 | SET_ZFLG (((int16_t)(src)) == 0); | |
1303 | SET_NFLG (((int16_t)(src)) < 0); | |
1304 | m68k_write_memory_16(dsta,src); | |
1305 | }}}}m68k_incpc(4); | |
1306 | return 18; | |
1307 | } | |
1308 | unsigned long CPUFUNC(op_268_4)(uint32_t opcode) /* AND */ | |
1309 | { | |
1310 | uint32_t dstreg = opcode & 7; | |
1311 | OpcodeFamily = 2; CurrentInstrCycles = 20; | |
1312 | {{ int16_t src = get_iword(2); | |
1313 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); | |
1314 | { int16_t dst = m68k_read_memory_16(dsta); | |
1315 | src &= dst; | |
1316 | CLEAR_CZNV; | |
1317 | SET_ZFLG (((int16_t)(src)) == 0); | |
1318 | SET_NFLG (((int16_t)(src)) < 0); | |
1319 | m68k_write_memory_16(dsta,src); | |
1320 | }}}}m68k_incpc(6); | |
1321 | return 20; | |
1322 | } | |
1323 | unsigned long CPUFUNC(op_270_4)(uint32_t opcode) /* AND */ | |
1324 | { | |
1325 | uint32_t dstreg = opcode & 7; | |
1326 | OpcodeFamily = 2; CurrentInstrCycles = 22; | |
1327 | {{ int16_t src = get_iword(2); | |
1328 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); | |
1329 | BusCyclePenalty += 2; | |
1330 | { int16_t dst = m68k_read_memory_16(dsta); | |
1331 | src &= dst; | |
1332 | CLEAR_CZNV; | |
1333 | SET_ZFLG (((int16_t)(src)) == 0); | |
1334 | SET_NFLG (((int16_t)(src)) < 0); | |
1335 | m68k_write_memory_16(dsta,src); | |
1336 | }}}}m68k_incpc(6); | |
1337 | return 22; | |
1338 | } | |
1339 | unsigned long CPUFUNC(op_278_4)(uint32_t opcode) /* AND */ | |
1340 | { | |
1341 | OpcodeFamily = 2; CurrentInstrCycles = 20; | |
1342 | {{ int16_t src = get_iword(2); | |
1343 | { uint32_t dsta = (int32_t)(int16_t)get_iword(4); | |
1344 | { int16_t dst = m68k_read_memory_16(dsta); | |
1345 | src &= dst; | |
1346 | CLEAR_CZNV; | |
1347 | SET_ZFLG (((int16_t)(src)) == 0); | |
1348 | SET_NFLG (((int16_t)(src)) < 0); | |
1349 | m68k_write_memory_16(dsta,src); | |
1350 | }}}}m68k_incpc(6); | |
1351 | return 20; | |
1352 | } | |
1353 | unsigned long CPUFUNC(op_279_4)(uint32_t opcode) /* AND */ | |
1354 | { | |
1355 | OpcodeFamily = 2; CurrentInstrCycles = 24; | |
1356 | {{ int16_t src = get_iword(2); | |
1357 | { uint32_t dsta = get_ilong(4); | |
1358 | { int16_t dst = m68k_read_memory_16(dsta); | |
1359 | src &= dst; | |
1360 | CLEAR_CZNV; | |
1361 | SET_ZFLG (((int16_t)(src)) == 0); | |
1362 | SET_NFLG (((int16_t)(src)) < 0); | |
1363 | m68k_write_memory_16(dsta,src); | |
1364 | }}}}m68k_incpc(8); | |
1365 | return 24; | |
1366 | } | |
1367 | unsigned long CPUFUNC(op_27c_4)(uint32_t opcode) /* ANDSR */ | |
1368 | { | |
1369 | OpcodeFamily = 5; CurrentInstrCycles = 20; | |
1370 | {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel89; } | |
1371 | { MakeSR(); | |
1372 | { int16_t src = get_iword(2); | |
1373 | regs.sr &= src; | |
1374 | MakeFromSR(); | |
1375 | }}}m68k_incpc(4); | |
1376 | endlabel89: ; | |
1377 | return 20; | |
1378 | } | |
1379 | unsigned long CPUFUNC(op_280_4)(uint32_t opcode) /* AND */ | |
1380 | { | |
1381 | uint32_t dstreg = opcode & 7; | |
1382 | OpcodeFamily = 2; CurrentInstrCycles = 16; | |
1383 | {{ int32_t src = get_ilong(2); | |
1384 | { int32_t dst = m68k_dreg(regs, dstreg); | |
1385 | src &= dst; | |
1386 | CLEAR_CZNV; | |
1387 | SET_ZFLG (((int32_t)(src)) == 0); | |
1388 | SET_NFLG (((int32_t)(src)) < 0); | |
1389 | m68k_dreg(regs, dstreg) = (src); | |
1390 | }}}m68k_incpc(6); | |
1391 | return 16; | |
1392 | } | |
1393 | unsigned long CPUFUNC(op_290_4)(uint32_t opcode) /* AND */ | |
1394 | { | |
1395 | uint32_t dstreg = opcode & 7; | |
1396 | OpcodeFamily = 2; CurrentInstrCycles = 28; | |
1397 | {{ int32_t src = get_ilong(2); | |
1398 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
1399 | { int32_t dst = m68k_read_memory_32(dsta); | |
1400 | src &= dst; | |
1401 | CLEAR_CZNV; | |
1402 | SET_ZFLG (((int32_t)(src)) == 0); | |
1403 | SET_NFLG (((int32_t)(src)) < 0); | |
1404 | m68k_write_memory_32(dsta,src); | |
1405 | }}}}m68k_incpc(6); | |
1406 | return 28; | |
1407 | } | |
1408 | unsigned long CPUFUNC(op_298_4)(uint32_t opcode) /* AND */ | |
1409 | { | |
1410 | uint32_t dstreg = opcode & 7; | |
1411 | OpcodeFamily = 2; CurrentInstrCycles = 28; | |
1412 | {{ int32_t src = get_ilong(2); | |
1413 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
1414 | { int32_t dst = m68k_read_memory_32(dsta); | |
1415 | m68k_areg(regs, dstreg) += 4; | |
1416 | src &= dst; | |
1417 | CLEAR_CZNV; | |
1418 | SET_ZFLG (((int32_t)(src)) == 0); | |
1419 | SET_NFLG (((int32_t)(src)) < 0); | |
1420 | m68k_write_memory_32(dsta,src); | |
1421 | }}}}m68k_incpc(6); | |
1422 | return 28; | |
1423 | } | |
1424 | unsigned long CPUFUNC(op_2a0_4)(uint32_t opcode) /* AND */ | |
1425 | { | |
1426 | uint32_t dstreg = opcode & 7; | |
1427 | OpcodeFamily = 2; CurrentInstrCycles = 30; | |
1428 | {{ int32_t src = get_ilong(2); | |
1429 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
1430 | { int32_t dst = m68k_read_memory_32(dsta); | |
1431 | m68k_areg (regs, dstreg) = dsta; | |
1432 | src &= dst; | |
1433 | CLEAR_CZNV; | |
1434 | SET_ZFLG (((int32_t)(src)) == 0); | |
1435 | SET_NFLG (((int32_t)(src)) < 0); | |
1436 | m68k_write_memory_32(dsta,src); | |
1437 | }}}}m68k_incpc(6); | |
1438 | return 30; | |
1439 | } | |
1440 | unsigned long CPUFUNC(op_2a8_4)(uint32_t opcode) /* AND */ | |
1441 | { | |
1442 | uint32_t dstreg = opcode & 7; | |
1443 | OpcodeFamily = 2; CurrentInstrCycles = 32; | |
1444 | {{ int32_t src = get_ilong(2); | |
1445 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(6); | |
1446 | { int32_t dst = m68k_read_memory_32(dsta); | |
1447 | src &= dst; | |
1448 | CLEAR_CZNV; | |
1449 | SET_ZFLG (((int32_t)(src)) == 0); | |
1450 | SET_NFLG (((int32_t)(src)) < 0); | |
1451 | m68k_write_memory_32(dsta,src); | |
1452 | }}}}m68k_incpc(8); | |
1453 | return 32; | |
1454 | } | |
1455 | unsigned long CPUFUNC(op_2b0_4)(uint32_t opcode) /* AND */ | |
1456 | { | |
1457 | uint32_t dstreg = opcode & 7; | |
1458 | OpcodeFamily = 2; CurrentInstrCycles = 34; | |
1459 | {{ int32_t src = get_ilong(2); | |
1460 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(6)); | |
1461 | BusCyclePenalty += 2; | |
1462 | { int32_t dst = m68k_read_memory_32(dsta); | |
1463 | src &= dst; | |
1464 | CLEAR_CZNV; | |
1465 | SET_ZFLG (((int32_t)(src)) == 0); | |
1466 | SET_NFLG (((int32_t)(src)) < 0); | |
1467 | m68k_write_memory_32(dsta,src); | |
1468 | }}}}m68k_incpc(8); | |
1469 | return 34; | |
1470 | } | |
1471 | unsigned long CPUFUNC(op_2b8_4)(uint32_t opcode) /* AND */ | |
1472 | { | |
1473 | OpcodeFamily = 2; CurrentInstrCycles = 32; | |
1474 | {{ int32_t src = get_ilong(2); | |
1475 | { uint32_t dsta = (int32_t)(int16_t)get_iword(6); | |
1476 | { int32_t dst = m68k_read_memory_32(dsta); | |
1477 | src &= dst; | |
1478 | CLEAR_CZNV; | |
1479 | SET_ZFLG (((int32_t)(src)) == 0); | |
1480 | SET_NFLG (((int32_t)(src)) < 0); | |
1481 | m68k_write_memory_32(dsta,src); | |
1482 | }}}}m68k_incpc(8); | |
1483 | return 32; | |
1484 | } | |
1485 | unsigned long CPUFUNC(op_2b9_4)(uint32_t opcode) /* AND */ | |
1486 | { | |
1487 | OpcodeFamily = 2; CurrentInstrCycles = 36; | |
1488 | {{ int32_t src = get_ilong(2); | |
1489 | { uint32_t dsta = get_ilong(6); | |
1490 | { int32_t dst = m68k_read_memory_32(dsta); | |
1491 | src &= dst; | |
1492 | CLEAR_CZNV; | |
1493 | SET_ZFLG (((int32_t)(src)) == 0); | |
1494 | SET_NFLG (((int32_t)(src)) < 0); | |
1495 | m68k_write_memory_32(dsta,src); | |
1496 | }}}}m68k_incpc(10); | |
1497 | return 36; | |
1498 | } | |
1499 | unsigned long CPUFUNC(op_400_4)(uint32_t opcode) /* SUB */ | |
1500 | { | |
1501 | uint32_t dstreg = opcode & 7; | |
1502 | OpcodeFamily = 7; CurrentInstrCycles = 8; | |
1503 | {{ int8_t src = get_ibyte(2); | |
1504 | { int8_t dst = m68k_dreg(regs, dstreg); | |
1505 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
1506 | { int flgs = ((int8_t)(src)) < 0; | |
1507 | int flgo = ((int8_t)(dst)) < 0; | |
1508 | int flgn = ((int8_t)(newv)) < 0; | |
1509 | SET_ZFLG (((int8_t)(newv)) == 0); | |
1510 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
1511 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
1512 | COPY_CARRY; | |
1513 | SET_NFLG (flgn != 0); | |
1514 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
1515 | }}}}}}m68k_incpc(4); | |
1516 | return 8; | |
1517 | } | |
1518 | unsigned long CPUFUNC(op_410_4)(uint32_t opcode) /* SUB */ | |
1519 | { | |
1520 | uint32_t dstreg = opcode & 7; | |
1521 | OpcodeFamily = 7; CurrentInstrCycles = 16; | |
1522 | {{ int8_t src = get_ibyte(2); | |
1523 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
1524 | { int8_t dst = m68k_read_memory_8(dsta); | |
1525 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
1526 | { int flgs = ((int8_t)(src)) < 0; | |
1527 | int flgo = ((int8_t)(dst)) < 0; | |
1528 | int flgn = ((int8_t)(newv)) < 0; | |
1529 | SET_ZFLG (((int8_t)(newv)) == 0); | |
1530 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
1531 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
1532 | COPY_CARRY; | |
1533 | SET_NFLG (flgn != 0); | |
1534 | m68k_write_memory_8(dsta,newv); | |
1535 | }}}}}}}m68k_incpc(4); | |
1536 | return 16; | |
1537 | } | |
1538 | unsigned long CPUFUNC(op_418_4)(uint32_t opcode) /* SUB */ | |
1539 | { | |
1540 | uint32_t dstreg = opcode & 7; | |
1541 | OpcodeFamily = 7; CurrentInstrCycles = 16; | |
1542 | {{ int8_t src = get_ibyte(2); | |
1543 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
1544 | { int8_t dst = m68k_read_memory_8(dsta); | |
1545 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
1546 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
1547 | { int flgs = ((int8_t)(src)) < 0; | |
1548 | int flgo = ((int8_t)(dst)) < 0; | |
1549 | int flgn = ((int8_t)(newv)) < 0; | |
1550 | SET_ZFLG (((int8_t)(newv)) == 0); | |
1551 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
1552 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
1553 | COPY_CARRY; | |
1554 | SET_NFLG (flgn != 0); | |
1555 | m68k_write_memory_8(dsta,newv); | |
1556 | }}}}}}}m68k_incpc(4); | |
1557 | return 16; | |
1558 | } | |
1559 | unsigned long CPUFUNC(op_420_4)(uint32_t opcode) /* SUB */ | |
1560 | { | |
1561 | uint32_t dstreg = opcode & 7; | |
1562 | OpcodeFamily = 7; CurrentInstrCycles = 18; | |
1563 | {{ int8_t src = get_ibyte(2); | |
1564 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
1565 | { int8_t dst = m68k_read_memory_8(dsta); | |
1566 | m68k_areg (regs, dstreg) = dsta; | |
1567 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
1568 | { int flgs = ((int8_t)(src)) < 0; | |
1569 | int flgo = ((int8_t)(dst)) < 0; | |
1570 | int flgn = ((int8_t)(newv)) < 0; | |
1571 | SET_ZFLG (((int8_t)(newv)) == 0); | |
1572 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
1573 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
1574 | COPY_CARRY; | |
1575 | SET_NFLG (flgn != 0); | |
1576 | m68k_write_memory_8(dsta,newv); | |
1577 | }}}}}}}m68k_incpc(4); | |
1578 | return 18; | |
1579 | } | |
1580 | unsigned long CPUFUNC(op_428_4)(uint32_t opcode) /* SUB */ | |
1581 | { | |
1582 | uint32_t dstreg = opcode & 7; | |
1583 | OpcodeFamily = 7; CurrentInstrCycles = 20; | |
1584 | {{ int8_t src = get_ibyte(2); | |
1585 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); | |
1586 | { int8_t dst = m68k_read_memory_8(dsta); | |
1587 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
1588 | { int flgs = ((int8_t)(src)) < 0; | |
1589 | int flgo = ((int8_t)(dst)) < 0; | |
1590 | int flgn = ((int8_t)(newv)) < 0; | |
1591 | SET_ZFLG (((int8_t)(newv)) == 0); | |
1592 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
1593 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
1594 | COPY_CARRY; | |
1595 | SET_NFLG (flgn != 0); | |
1596 | m68k_write_memory_8(dsta,newv); | |
1597 | }}}}}}}m68k_incpc(6); | |
1598 | return 20; | |
1599 | } | |
1600 | unsigned long CPUFUNC(op_430_4)(uint32_t opcode) /* SUB */ | |
1601 | { | |
1602 | uint32_t dstreg = opcode & 7; | |
1603 | OpcodeFamily = 7; CurrentInstrCycles = 22; | |
1604 | {{ int8_t src = get_ibyte(2); | |
1605 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); | |
1606 | BusCyclePenalty += 2; | |
1607 | { int8_t dst = m68k_read_memory_8(dsta); | |
1608 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
1609 | { int flgs = ((int8_t)(src)) < 0; | |
1610 | int flgo = ((int8_t)(dst)) < 0; | |
1611 | int flgn = ((int8_t)(newv)) < 0; | |
1612 | SET_ZFLG (((int8_t)(newv)) == 0); | |
1613 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
1614 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
1615 | COPY_CARRY; | |
1616 | SET_NFLG (flgn != 0); | |
1617 | m68k_write_memory_8(dsta,newv); | |
1618 | }}}}}}}m68k_incpc(6); | |
1619 | return 22; | |
1620 | } | |
1621 | unsigned long CPUFUNC(op_438_4)(uint32_t opcode) /* SUB */ | |
1622 | { | |
1623 | OpcodeFamily = 7; CurrentInstrCycles = 20; | |
1624 | {{ int8_t src = get_ibyte(2); | |
1625 | { uint32_t dsta = (int32_t)(int16_t)get_iword(4); | |
1626 | { int8_t dst = m68k_read_memory_8(dsta); | |
1627 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
1628 | { int flgs = ((int8_t)(src)) < 0; | |
1629 | int flgo = ((int8_t)(dst)) < 0; | |
1630 | int flgn = ((int8_t)(newv)) < 0; | |
1631 | SET_ZFLG (((int8_t)(newv)) == 0); | |
1632 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
1633 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
1634 | COPY_CARRY; | |
1635 | SET_NFLG (flgn != 0); | |
1636 | m68k_write_memory_8(dsta,newv); | |
1637 | }}}}}}}m68k_incpc(6); | |
1638 | return 20; | |
1639 | } | |
1640 | unsigned long CPUFUNC(op_439_4)(uint32_t opcode) /* SUB */ | |
1641 | { | |
1642 | OpcodeFamily = 7; CurrentInstrCycles = 24; | |
1643 | {{ int8_t src = get_ibyte(2); | |
1644 | { uint32_t dsta = get_ilong(4); | |
1645 | { int8_t dst = m68k_read_memory_8(dsta); | |
1646 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
1647 | { int flgs = ((int8_t)(src)) < 0; | |
1648 | int flgo = ((int8_t)(dst)) < 0; | |
1649 | int flgn = ((int8_t)(newv)) < 0; | |
1650 | SET_ZFLG (((int8_t)(newv)) == 0); | |
1651 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
1652 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
1653 | COPY_CARRY; | |
1654 | SET_NFLG (flgn != 0); | |
1655 | m68k_write_memory_8(dsta,newv); | |
1656 | }}}}}}}m68k_incpc(8); | |
1657 | return 24; | |
1658 | } | |
1659 | unsigned long CPUFUNC(op_440_4)(uint32_t opcode) /* SUB */ | |
1660 | { | |
1661 | uint32_t dstreg = opcode & 7; | |
1662 | OpcodeFamily = 7; CurrentInstrCycles = 8; | |
1663 | {{ int16_t src = get_iword(2); | |
1664 | { int16_t dst = m68k_dreg(regs, dstreg); | |
1665 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
1666 | { int flgs = ((int16_t)(src)) < 0; | |
1667 | int flgo = ((int16_t)(dst)) < 0; | |
1668 | int flgn = ((int16_t)(newv)) < 0; | |
1669 | SET_ZFLG (((int16_t)(newv)) == 0); | |
1670 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
1671 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
1672 | COPY_CARRY; | |
1673 | SET_NFLG (flgn != 0); | |
1674 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
1675 | }}}}}}m68k_incpc(4); | |
1676 | return 8; | |
1677 | } | |
1678 | unsigned long CPUFUNC(op_450_4)(uint32_t opcode) /* SUB */ | |
1679 | { | |
1680 | uint32_t dstreg = opcode & 7; | |
1681 | OpcodeFamily = 7; CurrentInstrCycles = 16; | |
1682 | {{ int16_t src = get_iword(2); | |
1683 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
1684 | { int16_t dst = m68k_read_memory_16(dsta); | |
1685 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
1686 | { int flgs = ((int16_t)(src)) < 0; | |
1687 | int flgo = ((int16_t)(dst)) < 0; | |
1688 | int flgn = ((int16_t)(newv)) < 0; | |
1689 | SET_ZFLG (((int16_t)(newv)) == 0); | |
1690 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
1691 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
1692 | COPY_CARRY; | |
1693 | SET_NFLG (flgn != 0); | |
1694 | m68k_write_memory_16(dsta,newv); | |
1695 | }}}}}}}m68k_incpc(4); | |
1696 | return 16; | |
1697 | } | |
1698 | unsigned long CPUFUNC(op_458_4)(uint32_t opcode) /* SUB */ | |
1699 | { | |
1700 | uint32_t dstreg = opcode & 7; | |
1701 | OpcodeFamily = 7; CurrentInstrCycles = 16; | |
1702 | {{ int16_t src = get_iword(2); | |
1703 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
1704 | { int16_t dst = m68k_read_memory_16(dsta); | |
1705 | m68k_areg(regs, dstreg) += 2; | |
1706 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
1707 | { int flgs = ((int16_t)(src)) < 0; | |
1708 | int flgo = ((int16_t)(dst)) < 0; | |
1709 | int flgn = ((int16_t)(newv)) < 0; | |
1710 | SET_ZFLG (((int16_t)(newv)) == 0); | |
1711 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
1712 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
1713 | COPY_CARRY; | |
1714 | SET_NFLG (flgn != 0); | |
1715 | m68k_write_memory_16(dsta,newv); | |
1716 | }}}}}}}m68k_incpc(4); | |
1717 | return 16; | |
1718 | } | |
1719 | unsigned long CPUFUNC(op_460_4)(uint32_t opcode) /* SUB */ | |
1720 | { | |
1721 | uint32_t dstreg = opcode & 7; | |
1722 | OpcodeFamily = 7; CurrentInstrCycles = 18; | |
1723 | {{ int16_t src = get_iword(2); | |
1724 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
1725 | { int16_t dst = m68k_read_memory_16(dsta); | |
1726 | m68k_areg (regs, dstreg) = dsta; | |
1727 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
1728 | { int flgs = ((int16_t)(src)) < 0; | |
1729 | int flgo = ((int16_t)(dst)) < 0; | |
1730 | int flgn = ((int16_t)(newv)) < 0; | |
1731 | SET_ZFLG (((int16_t)(newv)) == 0); | |
1732 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
1733 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
1734 | COPY_CARRY; | |
1735 | SET_NFLG (flgn != 0); | |
1736 | m68k_write_memory_16(dsta,newv); | |
1737 | }}}}}}}m68k_incpc(4); | |
1738 | return 18; | |
1739 | } | |
1740 | unsigned long CPUFUNC(op_468_4)(uint32_t opcode) /* SUB */ | |
1741 | { | |
1742 | uint32_t dstreg = opcode & 7; | |
1743 | OpcodeFamily = 7; CurrentInstrCycles = 20; | |
1744 | {{ int16_t src = get_iword(2); | |
1745 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); | |
1746 | { int16_t dst = m68k_read_memory_16(dsta); | |
1747 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
1748 | { int flgs = ((int16_t)(src)) < 0; | |
1749 | int flgo = ((int16_t)(dst)) < 0; | |
1750 | int flgn = ((int16_t)(newv)) < 0; | |
1751 | SET_ZFLG (((int16_t)(newv)) == 0); | |
1752 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
1753 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
1754 | COPY_CARRY; | |
1755 | SET_NFLG (flgn != 0); | |
1756 | m68k_write_memory_16(dsta,newv); | |
1757 | }}}}}}}m68k_incpc(6); | |
1758 | return 20; | |
1759 | } | |
1760 | unsigned long CPUFUNC(op_470_4)(uint32_t opcode) /* SUB */ | |
1761 | { | |
1762 | uint32_t dstreg = opcode & 7; | |
1763 | OpcodeFamily = 7; CurrentInstrCycles = 22; | |
1764 | {{ int16_t src = get_iword(2); | |
1765 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); | |
1766 | BusCyclePenalty += 2; | |
1767 | { int16_t dst = m68k_read_memory_16(dsta); | |
1768 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
1769 | { int flgs = ((int16_t)(src)) < 0; | |
1770 | int flgo = ((int16_t)(dst)) < 0; | |
1771 | int flgn = ((int16_t)(newv)) < 0; | |
1772 | SET_ZFLG (((int16_t)(newv)) == 0); | |
1773 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
1774 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
1775 | COPY_CARRY; | |
1776 | SET_NFLG (flgn != 0); | |
1777 | m68k_write_memory_16(dsta,newv); | |
1778 | }}}}}}}m68k_incpc(6); | |
1779 | return 22; | |
1780 | } | |
1781 | unsigned long CPUFUNC(op_478_4)(uint32_t opcode) /* SUB */ | |
1782 | { | |
1783 | OpcodeFamily = 7; CurrentInstrCycles = 20; | |
1784 | {{ int16_t src = get_iword(2); | |
1785 | { uint32_t dsta = (int32_t)(int16_t)get_iword(4); | |
1786 | { int16_t dst = m68k_read_memory_16(dsta); | |
1787 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
1788 | { int flgs = ((int16_t)(src)) < 0; | |
1789 | int flgo = ((int16_t)(dst)) < 0; | |
1790 | int flgn = ((int16_t)(newv)) < 0; | |
1791 | SET_ZFLG (((int16_t)(newv)) == 0); | |
1792 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
1793 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
1794 | COPY_CARRY; | |
1795 | SET_NFLG (flgn != 0); | |
1796 | m68k_write_memory_16(dsta,newv); | |
1797 | }}}}}}}m68k_incpc(6); | |
1798 | return 20; | |
1799 | } | |
1800 | unsigned long CPUFUNC(op_479_4)(uint32_t opcode) /* SUB */ | |
1801 | { | |
1802 | OpcodeFamily = 7; CurrentInstrCycles = 24; | |
1803 | {{ int16_t src = get_iword(2); | |
1804 | { uint32_t dsta = get_ilong(4); | |
1805 | { int16_t dst = m68k_read_memory_16(dsta); | |
1806 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
1807 | { int flgs = ((int16_t)(src)) < 0; | |
1808 | int flgo = ((int16_t)(dst)) < 0; | |
1809 | int flgn = ((int16_t)(newv)) < 0; | |
1810 | SET_ZFLG (((int16_t)(newv)) == 0); | |
1811 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
1812 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
1813 | COPY_CARRY; | |
1814 | SET_NFLG (flgn != 0); | |
1815 | m68k_write_memory_16(dsta,newv); | |
1816 | }}}}}}}m68k_incpc(8); | |
1817 | return 24; | |
1818 | } | |
1819 | unsigned long CPUFUNC(op_480_4)(uint32_t opcode) /* SUB */ | |
1820 | { | |
1821 | uint32_t dstreg = opcode & 7; | |
1822 | OpcodeFamily = 7; CurrentInstrCycles = 16; | |
1823 | {{ int32_t src = get_ilong(2); | |
1824 | { int32_t dst = m68k_dreg(regs, dstreg); | |
1825 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
1826 | { int flgs = ((int32_t)(src)) < 0; | |
1827 | int flgo = ((int32_t)(dst)) < 0; | |
1828 | int flgn = ((int32_t)(newv)) < 0; | |
1829 | SET_ZFLG (((int32_t)(newv)) == 0); | |
1830 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
1831 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
1832 | COPY_CARRY; | |
1833 | SET_NFLG (flgn != 0); | |
1834 | m68k_dreg(regs, dstreg) = (newv); | |
1835 | }}}}}}m68k_incpc(6); | |
1836 | return 16; | |
1837 | } | |
1838 | unsigned long CPUFUNC(op_490_4)(uint32_t opcode) /* SUB */ | |
1839 | { | |
1840 | uint32_t dstreg = opcode & 7; | |
1841 | OpcodeFamily = 7; CurrentInstrCycles = 28; | |
1842 | {{ int32_t src = get_ilong(2); | |
1843 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
1844 | { int32_t dst = m68k_read_memory_32(dsta); | |
1845 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
1846 | { int flgs = ((int32_t)(src)) < 0; | |
1847 | int flgo = ((int32_t)(dst)) < 0; | |
1848 | int flgn = ((int32_t)(newv)) < 0; | |
1849 | SET_ZFLG (((int32_t)(newv)) == 0); | |
1850 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
1851 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
1852 | COPY_CARRY; | |
1853 | SET_NFLG (flgn != 0); | |
1854 | m68k_write_memory_32(dsta,newv); | |
1855 | }}}}}}}m68k_incpc(6); | |
1856 | return 28; | |
1857 | } | |
1858 | unsigned long CPUFUNC(op_498_4)(uint32_t opcode) /* SUB */ | |
1859 | { | |
1860 | uint32_t dstreg = opcode & 7; | |
1861 | OpcodeFamily = 7; CurrentInstrCycles = 28; | |
1862 | {{ int32_t src = get_ilong(2); | |
1863 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
1864 | { int32_t dst = m68k_read_memory_32(dsta); | |
1865 | m68k_areg(regs, dstreg) += 4; | |
1866 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
1867 | { int flgs = ((int32_t)(src)) < 0; | |
1868 | int flgo = ((int32_t)(dst)) < 0; | |
1869 | int flgn = ((int32_t)(newv)) < 0; | |
1870 | SET_ZFLG (((int32_t)(newv)) == 0); | |
1871 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
1872 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
1873 | COPY_CARRY; | |
1874 | SET_NFLG (flgn != 0); | |
1875 | m68k_write_memory_32(dsta,newv); | |
1876 | }}}}}}}m68k_incpc(6); | |
1877 | return 28; | |
1878 | } | |
1879 | unsigned long CPUFUNC(op_4a0_4)(uint32_t opcode) /* SUB */ | |
1880 | { | |
1881 | uint32_t dstreg = opcode & 7; | |
1882 | OpcodeFamily = 7; CurrentInstrCycles = 30; | |
1883 | {{ int32_t src = get_ilong(2); | |
1884 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
1885 | { int32_t dst = m68k_read_memory_32(dsta); | |
1886 | m68k_areg (regs, dstreg) = dsta; | |
1887 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
1888 | { int flgs = ((int32_t)(src)) < 0; | |
1889 | int flgo = ((int32_t)(dst)) < 0; | |
1890 | int flgn = ((int32_t)(newv)) < 0; | |
1891 | SET_ZFLG (((int32_t)(newv)) == 0); | |
1892 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
1893 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
1894 | COPY_CARRY; | |
1895 | SET_NFLG (flgn != 0); | |
1896 | m68k_write_memory_32(dsta,newv); | |
1897 | }}}}}}}m68k_incpc(6); | |
1898 | return 30; | |
1899 | } | |
1900 | unsigned long CPUFUNC(op_4a8_4)(uint32_t opcode) /* SUB */ | |
1901 | { | |
1902 | uint32_t dstreg = opcode & 7; | |
1903 | OpcodeFamily = 7; CurrentInstrCycles = 32; | |
1904 | {{ int32_t src = get_ilong(2); | |
1905 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(6); | |
1906 | { int32_t dst = m68k_read_memory_32(dsta); | |
1907 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
1908 | { int flgs = ((int32_t)(src)) < 0; | |
1909 | int flgo = ((int32_t)(dst)) < 0; | |
1910 | int flgn = ((int32_t)(newv)) < 0; | |
1911 | SET_ZFLG (((int32_t)(newv)) == 0); | |
1912 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
1913 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
1914 | COPY_CARRY; | |
1915 | SET_NFLG (flgn != 0); | |
1916 | m68k_write_memory_32(dsta,newv); | |
1917 | }}}}}}}m68k_incpc(8); | |
1918 | return 32; | |
1919 | } | |
1920 | unsigned long CPUFUNC(op_4b0_4)(uint32_t opcode) /* SUB */ | |
1921 | { | |
1922 | uint32_t dstreg = opcode & 7; | |
1923 | OpcodeFamily = 7; CurrentInstrCycles = 34; | |
1924 | {{ int32_t src = get_ilong(2); | |
1925 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(6)); | |
1926 | BusCyclePenalty += 2; | |
1927 | { int32_t dst = m68k_read_memory_32(dsta); | |
1928 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
1929 | { int flgs = ((int32_t)(src)) < 0; | |
1930 | int flgo = ((int32_t)(dst)) < 0; | |
1931 | int flgn = ((int32_t)(newv)) < 0; | |
1932 | SET_ZFLG (((int32_t)(newv)) == 0); | |
1933 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
1934 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
1935 | COPY_CARRY; | |
1936 | SET_NFLG (flgn != 0); | |
1937 | m68k_write_memory_32(dsta,newv); | |
1938 | }}}}}}}m68k_incpc(8); | |
1939 | return 34; | |
1940 | } | |
1941 | unsigned long CPUFUNC(op_4b8_4)(uint32_t opcode) /* SUB */ | |
1942 | { | |
1943 | OpcodeFamily = 7; CurrentInstrCycles = 32; | |
1944 | {{ int32_t src = get_ilong(2); | |
1945 | { uint32_t dsta = (int32_t)(int16_t)get_iword(6); | |
1946 | { int32_t dst = m68k_read_memory_32(dsta); | |
1947 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
1948 | { int flgs = ((int32_t)(src)) < 0; | |
1949 | int flgo = ((int32_t)(dst)) < 0; | |
1950 | int flgn = ((int32_t)(newv)) < 0; | |
1951 | SET_ZFLG (((int32_t)(newv)) == 0); | |
1952 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
1953 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
1954 | COPY_CARRY; | |
1955 | SET_NFLG (flgn != 0); | |
1956 | m68k_write_memory_32(dsta,newv); | |
1957 | }}}}}}}m68k_incpc(8); | |
1958 | return 32; | |
1959 | } | |
1960 | unsigned long CPUFUNC(op_4b9_4)(uint32_t opcode) /* SUB */ | |
1961 | { | |
1962 | OpcodeFamily = 7; CurrentInstrCycles = 36; | |
1963 | {{ int32_t src = get_ilong(2); | |
1964 | { uint32_t dsta = get_ilong(6); | |
1965 | { int32_t dst = m68k_read_memory_32(dsta); | |
1966 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
1967 | { int flgs = ((int32_t)(src)) < 0; | |
1968 | int flgo = ((int32_t)(dst)) < 0; | |
1969 | int flgn = ((int32_t)(newv)) < 0; | |
1970 | SET_ZFLG (((int32_t)(newv)) == 0); | |
1971 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
1972 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
1973 | COPY_CARRY; | |
1974 | SET_NFLG (flgn != 0); | |
1975 | m68k_write_memory_32(dsta,newv); | |
1976 | }}}}}}}m68k_incpc(10); | |
1977 | return 36; | |
1978 | } | |
1979 | unsigned long CPUFUNC(op_600_4)(uint32_t opcode) /* ADD */ | |
1980 | { | |
1981 | uint32_t dstreg = opcode & 7; | |
1982 | OpcodeFamily = 11; CurrentInstrCycles = 8; | |
1983 | {{ int8_t src = get_ibyte(2); | |
1984 | { int8_t dst = m68k_dreg(regs, dstreg); | |
1985 | { refill_prefetch (m68k_getpc(), 2); | |
1986 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
1987 | { int flgs = ((int8_t)(src)) < 0; | |
1988 | int flgo = ((int8_t)(dst)) < 0; | |
1989 | int flgn = ((int8_t)(newv)) < 0; | |
1990 | SET_ZFLG (((int8_t)(newv)) == 0); | |
1991 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
1992 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
1993 | COPY_CARRY; | |
1994 | SET_NFLG (flgn != 0); | |
1995 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
1996 | }}}}}}m68k_incpc(4); | |
1997 | return 8; | |
1998 | } | |
1999 | unsigned long CPUFUNC(op_610_4)(uint32_t opcode) /* ADD */ | |
2000 | { | |
2001 | uint32_t dstreg = opcode & 7; | |
2002 | OpcodeFamily = 11; CurrentInstrCycles = 16; | |
2003 | {{ int8_t src = get_ibyte(2); | |
2004 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
2005 | { int8_t dst = m68k_read_memory_8(dsta); | |
2006 | { refill_prefetch (m68k_getpc(), 2); | |
2007 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
2008 | { int flgs = ((int8_t)(src)) < 0; | |
2009 | int flgo = ((int8_t)(dst)) < 0; | |
2010 | int flgn = ((int8_t)(newv)) < 0; | |
2011 | SET_ZFLG (((int8_t)(newv)) == 0); | |
2012 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
2013 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
2014 | COPY_CARRY; | |
2015 | SET_NFLG (flgn != 0); | |
2016 | m68k_write_memory_8(dsta,newv); | |
2017 | }}}}}}}m68k_incpc(4); | |
2018 | return 16; | |
2019 | } | |
2020 | unsigned long CPUFUNC(op_618_4)(uint32_t opcode) /* ADD */ | |
2021 | { | |
2022 | uint32_t dstreg = opcode & 7; | |
2023 | OpcodeFamily = 11; CurrentInstrCycles = 16; | |
2024 | {{ int8_t src = get_ibyte(2); | |
2025 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
2026 | { int8_t dst = m68k_read_memory_8(dsta); | |
2027 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
2028 | { refill_prefetch (m68k_getpc(), 2); | |
2029 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
2030 | { int flgs = ((int8_t)(src)) < 0; | |
2031 | int flgo = ((int8_t)(dst)) < 0; | |
2032 | int flgn = ((int8_t)(newv)) < 0; | |
2033 | SET_ZFLG (((int8_t)(newv)) == 0); | |
2034 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
2035 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
2036 | COPY_CARRY; | |
2037 | SET_NFLG (flgn != 0); | |
2038 | m68k_write_memory_8(dsta,newv); | |
2039 | }}}}}}}m68k_incpc(4); | |
2040 | return 16; | |
2041 | } | |
2042 | unsigned long CPUFUNC(op_620_4)(uint32_t opcode) /* ADD */ | |
2043 | { | |
2044 | uint32_t dstreg = opcode & 7; | |
2045 | OpcodeFamily = 11; CurrentInstrCycles = 18; | |
2046 | {{ int8_t src = get_ibyte(2); | |
2047 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
2048 | { int8_t dst = m68k_read_memory_8(dsta); | |
2049 | m68k_areg (regs, dstreg) = dsta; | |
2050 | { refill_prefetch (m68k_getpc(), 2); | |
2051 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
2052 | { int flgs = ((int8_t)(src)) < 0; | |
2053 | int flgo = ((int8_t)(dst)) < 0; | |
2054 | int flgn = ((int8_t)(newv)) < 0; | |
2055 | SET_ZFLG (((int8_t)(newv)) == 0); | |
2056 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
2057 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
2058 | COPY_CARRY; | |
2059 | SET_NFLG (flgn != 0); | |
2060 | m68k_write_memory_8(dsta,newv); | |
2061 | }}}}}}}m68k_incpc(4); | |
2062 | return 18; | |
2063 | } | |
2064 | unsigned long CPUFUNC(op_628_4)(uint32_t opcode) /* ADD */ | |
2065 | { | |
2066 | uint32_t dstreg = opcode & 7; | |
2067 | OpcodeFamily = 11; CurrentInstrCycles = 20; | |
2068 | {{ int8_t src = get_ibyte(2); | |
2069 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); | |
2070 | { int8_t dst = m68k_read_memory_8(dsta); | |
2071 | { refill_prefetch (m68k_getpc(), 2); | |
2072 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
2073 | { int flgs = ((int8_t)(src)) < 0; | |
2074 | int flgo = ((int8_t)(dst)) < 0; | |
2075 | int flgn = ((int8_t)(newv)) < 0; | |
2076 | SET_ZFLG (((int8_t)(newv)) == 0); | |
2077 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
2078 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
2079 | COPY_CARRY; | |
2080 | SET_NFLG (flgn != 0); | |
2081 | m68k_write_memory_8(dsta,newv); | |
2082 | }}}}}}}m68k_incpc(6); | |
2083 | return 20; | |
2084 | } | |
2085 | unsigned long CPUFUNC(op_630_4)(uint32_t opcode) /* ADD */ | |
2086 | { | |
2087 | uint32_t dstreg = opcode & 7; | |
2088 | OpcodeFamily = 11; CurrentInstrCycles = 22; | |
2089 | {{ int8_t src = get_ibyte(2); | |
2090 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); | |
2091 | BusCyclePenalty += 2; | |
2092 | { int8_t dst = m68k_read_memory_8(dsta); | |
2093 | { refill_prefetch (m68k_getpc(), 2); | |
2094 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
2095 | { int flgs = ((int8_t)(src)) < 0; | |
2096 | int flgo = ((int8_t)(dst)) < 0; | |
2097 | int flgn = ((int8_t)(newv)) < 0; | |
2098 | SET_ZFLG (((int8_t)(newv)) == 0); | |
2099 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
2100 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
2101 | COPY_CARRY; | |
2102 | SET_NFLG (flgn != 0); | |
2103 | m68k_write_memory_8(dsta,newv); | |
2104 | }}}}}}}m68k_incpc(6); | |
2105 | return 22; | |
2106 | } | |
2107 | unsigned long CPUFUNC(op_638_4)(uint32_t opcode) /* ADD */ | |
2108 | { | |
2109 | OpcodeFamily = 11; CurrentInstrCycles = 20; | |
2110 | {{ int8_t src = get_ibyte(2); | |
2111 | { uint32_t dsta = (int32_t)(int16_t)get_iword(4); | |
2112 | { int8_t dst = m68k_read_memory_8(dsta); | |
2113 | { refill_prefetch (m68k_getpc(), 2); | |
2114 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
2115 | { int flgs = ((int8_t)(src)) < 0; | |
2116 | int flgo = ((int8_t)(dst)) < 0; | |
2117 | int flgn = ((int8_t)(newv)) < 0; | |
2118 | SET_ZFLG (((int8_t)(newv)) == 0); | |
2119 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
2120 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
2121 | COPY_CARRY; | |
2122 | SET_NFLG (flgn != 0); | |
2123 | m68k_write_memory_8(dsta,newv); | |
2124 | }}}}}}}m68k_incpc(6); | |
2125 | return 20; | |
2126 | } | |
2127 | unsigned long CPUFUNC(op_639_4)(uint32_t opcode) /* ADD */ | |
2128 | { | |
2129 | OpcodeFamily = 11; CurrentInstrCycles = 24; | |
2130 | {{ int8_t src = get_ibyte(2); | |
2131 | { uint32_t dsta = get_ilong(4); | |
2132 | { int8_t dst = m68k_read_memory_8(dsta); | |
2133 | { refill_prefetch (m68k_getpc(), 2); | |
2134 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
2135 | { int flgs = ((int8_t)(src)) < 0; | |
2136 | int flgo = ((int8_t)(dst)) < 0; | |
2137 | int flgn = ((int8_t)(newv)) < 0; | |
2138 | SET_ZFLG (((int8_t)(newv)) == 0); | |
2139 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
2140 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
2141 | COPY_CARRY; | |
2142 | SET_NFLG (flgn != 0); | |
2143 | m68k_write_memory_8(dsta,newv); | |
2144 | }}}}}}}m68k_incpc(8); | |
2145 | return 24; | |
2146 | } | |
2147 | unsigned long CPUFUNC(op_640_4)(uint32_t opcode) /* ADD */ | |
2148 | { | |
2149 | uint32_t dstreg = opcode & 7; | |
2150 | OpcodeFamily = 11; CurrentInstrCycles = 8; | |
2151 | {{ int16_t src = get_iword(2); | |
2152 | { int16_t dst = m68k_dreg(regs, dstreg); | |
2153 | { refill_prefetch (m68k_getpc(), 2); | |
2154 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
2155 | { int flgs = ((int16_t)(src)) < 0; | |
2156 | int flgo = ((int16_t)(dst)) < 0; | |
2157 | int flgn = ((int16_t)(newv)) < 0; | |
2158 | SET_ZFLG (((int16_t)(newv)) == 0); | |
2159 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
2160 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
2161 | COPY_CARRY; | |
2162 | SET_NFLG (flgn != 0); | |
2163 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
2164 | }}}}}}m68k_incpc(4); | |
2165 | return 8; | |
2166 | } | |
2167 | unsigned long CPUFUNC(op_650_4)(uint32_t opcode) /* ADD */ | |
2168 | { | |
2169 | uint32_t dstreg = opcode & 7; | |
2170 | OpcodeFamily = 11; CurrentInstrCycles = 16; | |
2171 | {{ int16_t src = get_iword(2); | |
2172 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
2173 | { int16_t dst = m68k_read_memory_16(dsta); | |
2174 | { refill_prefetch (m68k_getpc(), 2); | |
2175 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
2176 | { int flgs = ((int16_t)(src)) < 0; | |
2177 | int flgo = ((int16_t)(dst)) < 0; | |
2178 | int flgn = ((int16_t)(newv)) < 0; | |
2179 | SET_ZFLG (((int16_t)(newv)) == 0); | |
2180 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
2181 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
2182 | COPY_CARRY; | |
2183 | SET_NFLG (flgn != 0); | |
2184 | m68k_write_memory_16(dsta,newv); | |
2185 | }}}}}}}m68k_incpc(4); | |
2186 | return 16; | |
2187 | } | |
2188 | unsigned long CPUFUNC(op_658_4)(uint32_t opcode) /* ADD */ | |
2189 | { | |
2190 | uint32_t dstreg = opcode & 7; | |
2191 | OpcodeFamily = 11; CurrentInstrCycles = 16; | |
2192 | {{ int16_t src = get_iword(2); | |
2193 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
2194 | { int16_t dst = m68k_read_memory_16(dsta); | |
2195 | m68k_areg(regs, dstreg) += 2; | |
2196 | { refill_prefetch (m68k_getpc(), 2); | |
2197 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
2198 | { int flgs = ((int16_t)(src)) < 0; | |
2199 | int flgo = ((int16_t)(dst)) < 0; | |
2200 | int flgn = ((int16_t)(newv)) < 0; | |
2201 | SET_ZFLG (((int16_t)(newv)) == 0); | |
2202 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
2203 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
2204 | COPY_CARRY; | |
2205 | SET_NFLG (flgn != 0); | |
2206 | m68k_write_memory_16(dsta,newv); | |
2207 | }}}}}}}m68k_incpc(4); | |
2208 | return 16; | |
2209 | } | |
2210 | unsigned long CPUFUNC(op_660_4)(uint32_t opcode) /* ADD */ | |
2211 | { | |
2212 | uint32_t dstreg = opcode & 7; | |
2213 | OpcodeFamily = 11; CurrentInstrCycles = 18; | |
2214 | {{ int16_t src = get_iword(2); | |
2215 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
2216 | { int16_t dst = m68k_read_memory_16(dsta); | |
2217 | m68k_areg (regs, dstreg) = dsta; | |
2218 | { refill_prefetch (m68k_getpc(), 2); | |
2219 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
2220 | { int flgs = ((int16_t)(src)) < 0; | |
2221 | int flgo = ((int16_t)(dst)) < 0; | |
2222 | int flgn = ((int16_t)(newv)) < 0; | |
2223 | SET_ZFLG (((int16_t)(newv)) == 0); | |
2224 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
2225 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
2226 | COPY_CARRY; | |
2227 | SET_NFLG (flgn != 0); | |
2228 | m68k_write_memory_16(dsta,newv); | |
2229 | }}}}}}}m68k_incpc(4); | |
2230 | return 18; | |
2231 | } | |
2232 | unsigned long CPUFUNC(op_668_4)(uint32_t opcode) /* ADD */ | |
2233 | { | |
2234 | uint32_t dstreg = opcode & 7; | |
2235 | OpcodeFamily = 11; CurrentInstrCycles = 20; | |
2236 | {{ int16_t src = get_iword(2); | |
2237 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); | |
2238 | { int16_t dst = m68k_read_memory_16(dsta); | |
2239 | { refill_prefetch (m68k_getpc(), 2); | |
2240 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
2241 | { int flgs = ((int16_t)(src)) < 0; | |
2242 | int flgo = ((int16_t)(dst)) < 0; | |
2243 | int flgn = ((int16_t)(newv)) < 0; | |
2244 | SET_ZFLG (((int16_t)(newv)) == 0); | |
2245 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
2246 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
2247 | COPY_CARRY; | |
2248 | SET_NFLG (flgn != 0); | |
2249 | m68k_write_memory_16(dsta,newv); | |
2250 | }}}}}}}m68k_incpc(6); | |
2251 | return 20; | |
2252 | } | |
2253 | unsigned long CPUFUNC(op_670_4)(uint32_t opcode) /* ADD */ | |
2254 | { | |
2255 | uint32_t dstreg = opcode & 7; | |
2256 | OpcodeFamily = 11; CurrentInstrCycles = 22; | |
2257 | {{ int16_t src = get_iword(2); | |
2258 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); | |
2259 | BusCyclePenalty += 2; | |
2260 | { int16_t dst = m68k_read_memory_16(dsta); | |
2261 | { refill_prefetch (m68k_getpc(), 2); | |
2262 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
2263 | { int flgs = ((int16_t)(src)) < 0; | |
2264 | int flgo = ((int16_t)(dst)) < 0; | |
2265 | int flgn = ((int16_t)(newv)) < 0; | |
2266 | SET_ZFLG (((int16_t)(newv)) == 0); | |
2267 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
2268 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
2269 | COPY_CARRY; | |
2270 | SET_NFLG (flgn != 0); | |
2271 | m68k_write_memory_16(dsta,newv); | |
2272 | }}}}}}}m68k_incpc(6); | |
2273 | return 22; | |
2274 | } | |
2275 | unsigned long CPUFUNC(op_678_4)(uint32_t opcode) /* ADD */ | |
2276 | { | |
2277 | OpcodeFamily = 11; CurrentInstrCycles = 20; | |
2278 | {{ int16_t src = get_iword(2); | |
2279 | { uint32_t dsta = (int32_t)(int16_t)get_iword(4); | |
2280 | { int16_t dst = m68k_read_memory_16(dsta); | |
2281 | { refill_prefetch (m68k_getpc(), 2); | |
2282 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
2283 | { int flgs = ((int16_t)(src)) < 0; | |
2284 | int flgo = ((int16_t)(dst)) < 0; | |
2285 | int flgn = ((int16_t)(newv)) < 0; | |
2286 | SET_ZFLG (((int16_t)(newv)) == 0); | |
2287 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
2288 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
2289 | COPY_CARRY; | |
2290 | SET_NFLG (flgn != 0); | |
2291 | m68k_write_memory_16(dsta,newv); | |
2292 | }}}}}}}m68k_incpc(6); | |
2293 | return 20; | |
2294 | } | |
2295 | unsigned long CPUFUNC(op_679_4)(uint32_t opcode) /* ADD */ | |
2296 | { | |
2297 | OpcodeFamily = 11; CurrentInstrCycles = 24; | |
2298 | {{ int16_t src = get_iword(2); | |
2299 | { uint32_t dsta = get_ilong(4); | |
2300 | { int16_t dst = m68k_read_memory_16(dsta); | |
2301 | { refill_prefetch (m68k_getpc(), 2); | |
2302 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
2303 | { int flgs = ((int16_t)(src)) < 0; | |
2304 | int flgo = ((int16_t)(dst)) < 0; | |
2305 | int flgn = ((int16_t)(newv)) < 0; | |
2306 | SET_ZFLG (((int16_t)(newv)) == 0); | |
2307 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
2308 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
2309 | COPY_CARRY; | |
2310 | SET_NFLG (flgn != 0); | |
2311 | m68k_write_memory_16(dsta,newv); | |
2312 | }}}}}}}m68k_incpc(8); | |
2313 | return 24; | |
2314 | } | |
2315 | unsigned long CPUFUNC(op_680_4)(uint32_t opcode) /* ADD */ | |
2316 | { | |
2317 | uint32_t dstreg = opcode & 7; | |
2318 | OpcodeFamily = 11; CurrentInstrCycles = 16; | |
2319 | {{ int32_t src = get_ilong(2); | |
2320 | { int32_t dst = m68k_dreg(regs, dstreg); | |
2321 | { refill_prefetch (m68k_getpc(), 2); | |
2322 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
2323 | { int flgs = ((int32_t)(src)) < 0; | |
2324 | int flgo = ((int32_t)(dst)) < 0; | |
2325 | int flgn = ((int32_t)(newv)) < 0; | |
2326 | SET_ZFLG (((int32_t)(newv)) == 0); | |
2327 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
2328 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
2329 | COPY_CARRY; | |
2330 | SET_NFLG (flgn != 0); | |
2331 | m68k_dreg(regs, dstreg) = (newv); | |
2332 | }}}}}}m68k_incpc(6); | |
2333 | return 16; | |
2334 | } | |
2335 | unsigned long CPUFUNC(op_690_4)(uint32_t opcode) /* ADD */ | |
2336 | { | |
2337 | uint32_t dstreg = opcode & 7; | |
2338 | OpcodeFamily = 11; CurrentInstrCycles = 28; | |
2339 | {{ int32_t src = get_ilong(2); | |
2340 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
2341 | { int32_t dst = m68k_read_memory_32(dsta); | |
2342 | { refill_prefetch (m68k_getpc(), 2); | |
2343 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
2344 | { int flgs = ((int32_t)(src)) < 0; | |
2345 | int flgo = ((int32_t)(dst)) < 0; | |
2346 | int flgn = ((int32_t)(newv)) < 0; | |
2347 | SET_ZFLG (((int32_t)(newv)) == 0); | |
2348 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
2349 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
2350 | COPY_CARRY; | |
2351 | SET_NFLG (flgn != 0); | |
2352 | m68k_write_memory_32(dsta,newv); | |
2353 | }}}}}}}m68k_incpc(6); | |
2354 | return 28; | |
2355 | } | |
2356 | unsigned long CPUFUNC(op_698_4)(uint32_t opcode) /* ADD */ | |
2357 | { | |
2358 | uint32_t dstreg = opcode & 7; | |
2359 | OpcodeFamily = 11; CurrentInstrCycles = 28; | |
2360 | {{ int32_t src = get_ilong(2); | |
2361 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
2362 | { int32_t dst = m68k_read_memory_32(dsta); | |
2363 | m68k_areg(regs, dstreg) += 4; | |
2364 | { refill_prefetch (m68k_getpc(), 2); | |
2365 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
2366 | { int flgs = ((int32_t)(src)) < 0; | |
2367 | int flgo = ((int32_t)(dst)) < 0; | |
2368 | int flgn = ((int32_t)(newv)) < 0; | |
2369 | SET_ZFLG (((int32_t)(newv)) == 0); | |
2370 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
2371 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
2372 | COPY_CARRY; | |
2373 | SET_NFLG (flgn != 0); | |
2374 | m68k_write_memory_32(dsta,newv); | |
2375 | }}}}}}}m68k_incpc(6); | |
2376 | return 28; | |
2377 | } | |
2378 | unsigned long CPUFUNC(op_6a0_4)(uint32_t opcode) /* ADD */ | |
2379 | { | |
2380 | uint32_t dstreg = opcode & 7; | |
2381 | OpcodeFamily = 11; CurrentInstrCycles = 30; | |
2382 | {{ int32_t src = get_ilong(2); | |
2383 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
2384 | { int32_t dst = m68k_read_memory_32(dsta); | |
2385 | m68k_areg (regs, dstreg) = dsta; | |
2386 | { refill_prefetch (m68k_getpc(), 2); | |
2387 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
2388 | { int flgs = ((int32_t)(src)) < 0; | |
2389 | int flgo = ((int32_t)(dst)) < 0; | |
2390 | int flgn = ((int32_t)(newv)) < 0; | |
2391 | SET_ZFLG (((int32_t)(newv)) == 0); | |
2392 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
2393 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
2394 | COPY_CARRY; | |
2395 | SET_NFLG (flgn != 0); | |
2396 | m68k_write_memory_32(dsta,newv); | |
2397 | }}}}}}}m68k_incpc(6); | |
2398 | return 30; | |
2399 | } | |
2400 | unsigned long CPUFUNC(op_6a8_4)(uint32_t opcode) /* ADD */ | |
2401 | { | |
2402 | uint32_t dstreg = opcode & 7; | |
2403 | OpcodeFamily = 11; CurrentInstrCycles = 32; | |
2404 | {{ int32_t src = get_ilong(2); | |
2405 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(6); | |
2406 | { int32_t dst = m68k_read_memory_32(dsta); | |
2407 | { refill_prefetch (m68k_getpc(), 2); | |
2408 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
2409 | { int flgs = ((int32_t)(src)) < 0; | |
2410 | int flgo = ((int32_t)(dst)) < 0; | |
2411 | int flgn = ((int32_t)(newv)) < 0; | |
2412 | SET_ZFLG (((int32_t)(newv)) == 0); | |
2413 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
2414 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
2415 | COPY_CARRY; | |
2416 | SET_NFLG (flgn != 0); | |
2417 | m68k_write_memory_32(dsta,newv); | |
2418 | }}}}}}}m68k_incpc(8); | |
2419 | return 32; | |
2420 | } | |
2421 | unsigned long CPUFUNC(op_6b0_4)(uint32_t opcode) /* ADD */ | |
2422 | { | |
2423 | uint32_t dstreg = opcode & 7; | |
2424 | OpcodeFamily = 11; CurrentInstrCycles = 34; | |
2425 | {{ int32_t src = get_ilong(2); | |
2426 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(6)); | |
2427 | BusCyclePenalty += 2; | |
2428 | { int32_t dst = m68k_read_memory_32(dsta); | |
2429 | { refill_prefetch (m68k_getpc(), 2); | |
2430 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
2431 | { int flgs = ((int32_t)(src)) < 0; | |
2432 | int flgo = ((int32_t)(dst)) < 0; | |
2433 | int flgn = ((int32_t)(newv)) < 0; | |
2434 | SET_ZFLG (((int32_t)(newv)) == 0); | |
2435 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
2436 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
2437 | COPY_CARRY; | |
2438 | SET_NFLG (flgn != 0); | |
2439 | m68k_write_memory_32(dsta,newv); | |
2440 | }}}}}}}m68k_incpc(8); | |
2441 | return 34; | |
2442 | } | |
2443 | unsigned long CPUFUNC(op_6b8_4)(uint32_t opcode) /* ADD */ | |
2444 | { | |
2445 | OpcodeFamily = 11; CurrentInstrCycles = 32; | |
2446 | {{ int32_t src = get_ilong(2); | |
2447 | { uint32_t dsta = (int32_t)(int16_t)get_iword(6); | |
2448 | { int32_t dst = m68k_read_memory_32(dsta); | |
2449 | { refill_prefetch (m68k_getpc(), 2); | |
2450 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
2451 | { int flgs = ((int32_t)(src)) < 0; | |
2452 | int flgo = ((int32_t)(dst)) < 0; | |
2453 | int flgn = ((int32_t)(newv)) < 0; | |
2454 | SET_ZFLG (((int32_t)(newv)) == 0); | |
2455 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
2456 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
2457 | COPY_CARRY; | |
2458 | SET_NFLG (flgn != 0); | |
2459 | m68k_write_memory_32(dsta,newv); | |
2460 | }}}}}}}m68k_incpc(8); | |
2461 | return 32; | |
2462 | } | |
2463 | unsigned long CPUFUNC(op_6b9_4)(uint32_t opcode) /* ADD */ | |
2464 | { | |
2465 | OpcodeFamily = 11; CurrentInstrCycles = 36; | |
2466 | {{ int32_t src = get_ilong(2); | |
2467 | { uint32_t dsta = get_ilong(6); | |
2468 | { int32_t dst = m68k_read_memory_32(dsta); | |
2469 | { refill_prefetch (m68k_getpc(), 2); | |
2470 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
2471 | { int flgs = ((int32_t)(src)) < 0; | |
2472 | int flgo = ((int32_t)(dst)) < 0; | |
2473 | int flgn = ((int32_t)(newv)) < 0; | |
2474 | SET_ZFLG (((int32_t)(newv)) == 0); | |
2475 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
2476 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
2477 | COPY_CARRY; | |
2478 | SET_NFLG (flgn != 0); | |
2479 | m68k_write_memory_32(dsta,newv); | |
2480 | }}}}}}}m68k_incpc(10); | |
2481 | return 36; | |
2482 | } | |
2483 | unsigned long CPUFUNC(op_800_4)(uint32_t opcode) /* BTST */ | |
2484 | { | |
2485 | uint32_t dstreg = opcode & 7; | |
2486 | OpcodeFamily = 21; CurrentInstrCycles = 10; | |
2487 | {{ int16_t src = get_iword(2); | |
2488 | { int32_t dst = m68k_dreg(regs, dstreg); | |
2489 | src &= 31; | |
2490 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
2491 | }}}m68k_incpc(4); | |
2492 | return 10; | |
2493 | } | |
2494 | unsigned long CPUFUNC(op_810_4)(uint32_t opcode) /* BTST */ | |
2495 | { | |
2496 | uint32_t dstreg = opcode & 7; | |
2497 | OpcodeFamily = 21; CurrentInstrCycles = 12; | |
2498 | {{ int16_t src = get_iword(2); | |
2499 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
2500 | { int8_t dst = m68k_read_memory_8(dsta); | |
2501 | src &= 7; | |
2502 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
2503 | }}}}m68k_incpc(4); | |
2504 | return 12; | |
2505 | } | |
2506 | unsigned long CPUFUNC(op_818_4)(uint32_t opcode) /* BTST */ | |
2507 | { | |
2508 | uint32_t dstreg = opcode & 7; | |
2509 | OpcodeFamily = 21; CurrentInstrCycles = 12; | |
2510 | {{ int16_t src = get_iword(2); | |
2511 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
2512 | { int8_t dst = m68k_read_memory_8(dsta); | |
2513 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
2514 | src &= 7; | |
2515 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
2516 | }}}}m68k_incpc(4); | |
2517 | return 12; | |
2518 | } | |
2519 | unsigned long CPUFUNC(op_820_4)(uint32_t opcode) /* BTST */ | |
2520 | { | |
2521 | uint32_t dstreg = opcode & 7; | |
2522 | OpcodeFamily = 21; CurrentInstrCycles = 14; | |
2523 | {{ int16_t src = get_iword(2); | |
2524 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
2525 | { int8_t dst = m68k_read_memory_8(dsta); | |
2526 | m68k_areg (regs, dstreg) = dsta; | |
2527 | src &= 7; | |
2528 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
2529 | }}}}m68k_incpc(4); | |
2530 | return 14; | |
2531 | } | |
2532 | unsigned long CPUFUNC(op_828_4)(uint32_t opcode) /* BTST */ | |
2533 | { | |
2534 | uint32_t dstreg = opcode & 7; | |
2535 | OpcodeFamily = 21; CurrentInstrCycles = 16; | |
2536 | {{ int16_t src = get_iword(2); | |
2537 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); | |
2538 | { int8_t dst = m68k_read_memory_8(dsta); | |
2539 | src &= 7; | |
2540 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
2541 | }}}}m68k_incpc(6); | |
2542 | return 16; | |
2543 | } | |
2544 | unsigned long CPUFUNC(op_830_4)(uint32_t opcode) /* BTST */ | |
2545 | { | |
2546 | uint32_t dstreg = opcode & 7; | |
2547 | OpcodeFamily = 21; CurrentInstrCycles = 18; | |
2548 | {{ int16_t src = get_iword(2); | |
2549 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); | |
2550 | BusCyclePenalty += 2; | |
2551 | { int8_t dst = m68k_read_memory_8(dsta); | |
2552 | src &= 7; | |
2553 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
2554 | }}}}m68k_incpc(6); | |
2555 | return 18; | |
2556 | } | |
2557 | unsigned long CPUFUNC(op_838_4)(uint32_t opcode) /* BTST */ | |
2558 | { | |
2559 | OpcodeFamily = 21; CurrentInstrCycles = 16; | |
2560 | {{ int16_t src = get_iword(2); | |
2561 | { uint32_t dsta = (int32_t)(int16_t)get_iword(4); | |
2562 | { int8_t dst = m68k_read_memory_8(dsta); | |
2563 | src &= 7; | |
2564 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
2565 | }}}}m68k_incpc(6); | |
2566 | return 16; | |
2567 | } | |
2568 | unsigned long CPUFUNC(op_839_4)(uint32_t opcode) /* BTST */ | |
2569 | { | |
2570 | OpcodeFamily = 21; CurrentInstrCycles = 20; | |
2571 | {{ int16_t src = get_iword(2); | |
2572 | { uint32_t dsta = get_ilong(4); | |
2573 | { int8_t dst = m68k_read_memory_8(dsta); | |
2574 | src &= 7; | |
2575 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
2576 | }}}}m68k_incpc(8); | |
2577 | return 20; | |
2578 | } | |
2579 | unsigned long CPUFUNC(op_83a_4)(uint32_t opcode) /* BTST */ | |
2580 | { | |
2581 | uint32_t dstreg = 2; | |
2582 | OpcodeFamily = 21; CurrentInstrCycles = 16; | |
2583 | {{ int16_t src = get_iword(2); | |
2584 | { uint32_t dsta = m68k_getpc () + 4; | |
2585 | dsta += (int32_t)(int16_t)get_iword(4); | |
2586 | { int8_t dst = m68k_read_memory_8(dsta); | |
2587 | src &= 7; | |
2588 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
2589 | }}}}m68k_incpc(6); | |
2590 | return 16; | |
2591 | } | |
2592 | unsigned long CPUFUNC(op_83b_4)(uint32_t opcode) /* BTST */ | |
2593 | { | |
2594 | uint32_t dstreg = 3; | |
2595 | OpcodeFamily = 21; CurrentInstrCycles = 18; | |
2596 | {{ int16_t src = get_iword(2); | |
2597 | { uint32_t tmppc = m68k_getpc() + 4; | |
2598 | uint32_t dsta = get_disp_ea_000(tmppc, get_iword(4)); | |
2599 | BusCyclePenalty += 2; | |
2600 | { int8_t dst = m68k_read_memory_8(dsta); | |
2601 | src &= 7; | |
2602 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
2603 | }}}}m68k_incpc(6); | |
2604 | return 18; | |
2605 | } | |
2606 | unsigned long CPUFUNC(op_83c_4)(uint32_t opcode) /* BTST */ | |
2607 | { | |
2608 | OpcodeFamily = 21; CurrentInstrCycles = 12; | |
2609 | {{ int16_t src = get_iword(2); | |
2610 | { int8_t dst = get_ibyte(4); | |
2611 | src &= 7; | |
2612 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
2613 | }}}m68k_incpc(6); | |
2614 | return 12; | |
2615 | } | |
2616 | unsigned long CPUFUNC(op_840_4)(uint32_t opcode) /* BCHG */ | |
2617 | { | |
2618 | uint32_t dstreg = opcode & 7; | |
2619 | OpcodeFamily = 22; CurrentInstrCycles = 12; | |
2620 | {{ int16_t src = get_iword(2); | |
2621 | { int32_t dst = m68k_dreg(regs, dstreg); | |
2622 | src &= 31; | |
2623 | dst ^= (1 << src); | |
2624 | SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); | |
2625 | m68k_dreg(regs, dstreg) = (dst); | |
2626 | }}}m68k_incpc(4); | |
2627 | return 12; | |
2628 | } | |
2629 | unsigned long CPUFUNC(op_850_4)(uint32_t opcode) /* BCHG */ | |
2630 | { | |
2631 | uint32_t dstreg = opcode & 7; | |
2632 | OpcodeFamily = 22; CurrentInstrCycles = 16; | |
2633 | {{ int16_t src = get_iword(2); | |
2634 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
2635 | { int8_t dst = m68k_read_memory_8(dsta); | |
2636 | src &= 7; | |
2637 | dst ^= (1 << src); | |
2638 | SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); | |
2639 | m68k_write_memory_8(dsta,dst); | |
2640 | }}}}m68k_incpc(4); | |
2641 | return 16; | |
2642 | } | |
2643 | unsigned long CPUFUNC(op_858_4)(uint32_t opcode) /* BCHG */ | |
2644 | { | |
2645 | uint32_t dstreg = opcode & 7; | |
2646 | OpcodeFamily = 22; CurrentInstrCycles = 16; | |
2647 | {{ int16_t src = get_iword(2); | |
2648 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
2649 | { int8_t dst = m68k_read_memory_8(dsta); | |
2650 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
2651 | src &= 7; | |
2652 | dst ^= (1 << src); | |
2653 | SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); | |
2654 | m68k_write_memory_8(dsta,dst); | |
2655 | }}}}m68k_incpc(4); | |
2656 | return 16; | |
2657 | } | |
2658 | unsigned long CPUFUNC(op_860_4)(uint32_t opcode) /* BCHG */ | |
2659 | { | |
2660 | uint32_t dstreg = opcode & 7; | |
2661 | OpcodeFamily = 22; CurrentInstrCycles = 18; | |
2662 | {{ int16_t src = get_iword(2); | |
2663 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
2664 | { int8_t dst = m68k_read_memory_8(dsta); | |
2665 | m68k_areg (regs, dstreg) = dsta; | |
2666 | src &= 7; | |
2667 | dst ^= (1 << src); | |
2668 | SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); | |
2669 | m68k_write_memory_8(dsta,dst); | |
2670 | }}}}m68k_incpc(4); | |
2671 | return 18; | |
2672 | } | |
2673 | unsigned long CPUFUNC(op_868_4)(uint32_t opcode) /* BCHG */ | |
2674 | { | |
2675 | uint32_t dstreg = opcode & 7; | |
2676 | OpcodeFamily = 22; CurrentInstrCycles = 20; | |
2677 | {{ int16_t src = get_iword(2); | |
2678 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); | |
2679 | { int8_t dst = m68k_read_memory_8(dsta); | |
2680 | src &= 7; | |
2681 | dst ^= (1 << src); | |
2682 | SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); | |
2683 | m68k_write_memory_8(dsta,dst); | |
2684 | }}}}m68k_incpc(6); | |
2685 | return 20; | |
2686 | } | |
2687 | unsigned long CPUFUNC(op_870_4)(uint32_t opcode) /* BCHG */ | |
2688 | { | |
2689 | uint32_t dstreg = opcode & 7; | |
2690 | OpcodeFamily = 22; CurrentInstrCycles = 22; | |
2691 | {{ int16_t src = get_iword(2); | |
2692 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); | |
2693 | BusCyclePenalty += 2; | |
2694 | { int8_t dst = m68k_read_memory_8(dsta); | |
2695 | src &= 7; | |
2696 | dst ^= (1 << src); | |
2697 | SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); | |
2698 | m68k_write_memory_8(dsta,dst); | |
2699 | }}}}m68k_incpc(6); | |
2700 | return 22; | |
2701 | } | |
2702 | unsigned long CPUFUNC(op_878_4)(uint32_t opcode) /* BCHG */ | |
2703 | { | |
2704 | OpcodeFamily = 22; CurrentInstrCycles = 20; | |
2705 | {{ int16_t src = get_iword(2); | |
2706 | { uint32_t dsta = (int32_t)(int16_t)get_iword(4); | |
2707 | { int8_t dst = m68k_read_memory_8(dsta); | |
2708 | src &= 7; | |
2709 | dst ^= (1 << src); | |
2710 | SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); | |
2711 | m68k_write_memory_8(dsta,dst); | |
2712 | }}}}m68k_incpc(6); | |
2713 | return 20; | |
2714 | } | |
2715 | unsigned long CPUFUNC(op_879_4)(uint32_t opcode) /* BCHG */ | |
2716 | { | |
2717 | OpcodeFamily = 22; CurrentInstrCycles = 24; | |
2718 | {{ int16_t src = get_iword(2); | |
2719 | { uint32_t dsta = get_ilong(4); | |
2720 | { int8_t dst = m68k_read_memory_8(dsta); | |
2721 | src &= 7; | |
2722 | dst ^= (1 << src); | |
2723 | SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); | |
2724 | m68k_write_memory_8(dsta,dst); | |
2725 | }}}}m68k_incpc(8); | |
2726 | return 24; | |
2727 | } | |
2728 | unsigned long CPUFUNC(op_87a_4)(uint32_t opcode) /* BCHG */ | |
2729 | { | |
2730 | uint32_t dstreg = 2; | |
2731 | OpcodeFamily = 22; CurrentInstrCycles = 20; | |
2732 | {{ int16_t src = get_iword(2); | |
2733 | { uint32_t dsta = m68k_getpc () + 4; | |
2734 | dsta += (int32_t)(int16_t)get_iword(4); | |
2735 | { int8_t dst = m68k_read_memory_8(dsta); | |
2736 | src &= 7; | |
2737 | dst ^= (1 << src); | |
2738 | SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); | |
2739 | m68k_write_memory_8(dsta,dst); | |
2740 | }}}}m68k_incpc(6); | |
2741 | return 20; | |
2742 | } | |
2743 | unsigned long CPUFUNC(op_87b_4)(uint32_t opcode) /* BCHG */ | |
2744 | { | |
2745 | uint32_t dstreg = 3; | |
2746 | OpcodeFamily = 22; CurrentInstrCycles = 22; | |
2747 | {{ int16_t src = get_iword(2); | |
2748 | { uint32_t tmppc = m68k_getpc() + 4; | |
2749 | uint32_t dsta = get_disp_ea_000(tmppc, get_iword(4)); | |
2750 | BusCyclePenalty += 2; | |
2751 | { int8_t dst = m68k_read_memory_8(dsta); | |
2752 | src &= 7; | |
2753 | dst ^= (1 << src); | |
2754 | SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); | |
2755 | m68k_write_memory_8(dsta,dst); | |
2756 | }}}}m68k_incpc(6); | |
2757 | return 22; | |
2758 | } | |
2759 | unsigned long CPUFUNC(op_880_4)(uint32_t opcode) /* BCLR */ | |
2760 | { | |
2761 | uint32_t dstreg = opcode & 7; | |
2762 | OpcodeFamily = 23; CurrentInstrCycles = 14; | |
2763 | {{ int16_t src = get_iword(2); | |
2764 | { int32_t dst = m68k_dreg(regs, dstreg); | |
2765 | src &= 31; | |
2766 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
2767 | dst &= ~(1 << src); | |
2768 | m68k_dreg(regs, dstreg) = (dst); | |
2769 | if ( src < 16 ) { m68k_incpc(4); return 12; } | |
2770 | }}}m68k_incpc(4); | |
2771 | return 14; | |
2772 | } | |
2773 | unsigned long CPUFUNC(op_890_4)(uint32_t opcode) /* BCLR */ | |
2774 | { | |
2775 | uint32_t dstreg = opcode & 7; | |
2776 | OpcodeFamily = 23; CurrentInstrCycles = 16; | |
2777 | {{ int16_t src = get_iword(2); | |
2778 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
2779 | { int8_t dst = m68k_read_memory_8(dsta); | |
2780 | src &= 7; | |
2781 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
2782 | dst &= ~(1 << src); | |
2783 | m68k_write_memory_8(dsta,dst); | |
2784 | }}}}m68k_incpc(4); | |
2785 | return 16; | |
2786 | } | |
2787 | unsigned long CPUFUNC(op_898_4)(uint32_t opcode) /* BCLR */ | |
2788 | { | |
2789 | uint32_t dstreg = opcode & 7; | |
2790 | OpcodeFamily = 23; CurrentInstrCycles = 16; | |
2791 | {{ int16_t src = get_iword(2); | |
2792 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
2793 | { int8_t dst = m68k_read_memory_8(dsta); | |
2794 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
2795 | src &= 7; | |
2796 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
2797 | dst &= ~(1 << src); | |
2798 | m68k_write_memory_8(dsta,dst); | |
2799 | }}}}m68k_incpc(4); | |
2800 | return 16; | |
2801 | } | |
2802 | unsigned long CPUFUNC(op_8a0_4)(uint32_t opcode) /* BCLR */ | |
2803 | { | |
2804 | uint32_t dstreg = opcode & 7; | |
2805 | OpcodeFamily = 23; CurrentInstrCycles = 18; | |
2806 | {{ int16_t src = get_iword(2); | |
2807 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
2808 | { int8_t dst = m68k_read_memory_8(dsta); | |
2809 | m68k_areg (regs, dstreg) = dsta; | |
2810 | src &= 7; | |
2811 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
2812 | dst &= ~(1 << src); | |
2813 | m68k_write_memory_8(dsta,dst); | |
2814 | }}}}m68k_incpc(4); | |
2815 | return 18; | |
2816 | } | |
2817 | unsigned long CPUFUNC(op_8a8_4)(uint32_t opcode) /* BCLR */ | |
2818 | { | |
2819 | uint32_t dstreg = opcode & 7; | |
2820 | OpcodeFamily = 23; CurrentInstrCycles = 20; | |
2821 | {{ int16_t src = get_iword(2); | |
2822 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); | |
2823 | { int8_t dst = m68k_read_memory_8(dsta); | |
2824 | src &= 7; | |
2825 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
2826 | dst &= ~(1 << src); | |
2827 | m68k_write_memory_8(dsta,dst); | |
2828 | }}}}m68k_incpc(6); | |
2829 | return 20; | |
2830 | } | |
2831 | unsigned long CPUFUNC(op_8b0_4)(uint32_t opcode) /* BCLR */ | |
2832 | { | |
2833 | uint32_t dstreg = opcode & 7; | |
2834 | OpcodeFamily = 23; CurrentInstrCycles = 22; | |
2835 | {{ int16_t src = get_iword(2); | |
2836 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); | |
2837 | BusCyclePenalty += 2; | |
2838 | { int8_t dst = m68k_read_memory_8(dsta); | |
2839 | src &= 7; | |
2840 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
2841 | dst &= ~(1 << src); | |
2842 | m68k_write_memory_8(dsta,dst); | |
2843 | }}}}m68k_incpc(6); | |
2844 | return 22; | |
2845 | } | |
2846 | unsigned long CPUFUNC(op_8b8_4)(uint32_t opcode) /* BCLR */ | |
2847 | { | |
2848 | OpcodeFamily = 23; CurrentInstrCycles = 20; | |
2849 | {{ int16_t src = get_iword(2); | |
2850 | { uint32_t dsta = (int32_t)(int16_t)get_iword(4); | |
2851 | { int8_t dst = m68k_read_memory_8(dsta); | |
2852 | src &= 7; | |
2853 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
2854 | dst &= ~(1 << src); | |
2855 | m68k_write_memory_8(dsta,dst); | |
2856 | }}}}m68k_incpc(6); | |
2857 | return 20; | |
2858 | } | |
2859 | unsigned long CPUFUNC(op_8b9_4)(uint32_t opcode) /* BCLR */ | |
2860 | { | |
2861 | OpcodeFamily = 23; CurrentInstrCycles = 24; | |
2862 | {{ int16_t src = get_iword(2); | |
2863 | { uint32_t dsta = get_ilong(4); | |
2864 | { int8_t dst = m68k_read_memory_8(dsta); | |
2865 | src &= 7; | |
2866 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
2867 | dst &= ~(1 << src); | |
2868 | m68k_write_memory_8(dsta,dst); | |
2869 | }}}}m68k_incpc(8); | |
2870 | return 24; | |
2871 | } | |
2872 | unsigned long CPUFUNC(op_8ba_4)(uint32_t opcode) /* BCLR */ | |
2873 | { | |
2874 | uint32_t dstreg = 2; | |
2875 | OpcodeFamily = 23; CurrentInstrCycles = 20; | |
2876 | {{ int16_t src = get_iword(2); | |
2877 | { uint32_t dsta = m68k_getpc () + 4; | |
2878 | dsta += (int32_t)(int16_t)get_iword(4); | |
2879 | { int8_t dst = m68k_read_memory_8(dsta); | |
2880 | src &= 7; | |
2881 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
2882 | dst &= ~(1 << src); | |
2883 | m68k_write_memory_8(dsta,dst); | |
2884 | }}}}m68k_incpc(6); | |
2885 | return 20; | |
2886 | } | |
2887 | unsigned long CPUFUNC(op_8bb_4)(uint32_t opcode) /* BCLR */ | |
2888 | { | |
2889 | uint32_t dstreg = 3; | |
2890 | OpcodeFamily = 23; CurrentInstrCycles = 22; | |
2891 | {{ int16_t src = get_iword(2); | |
2892 | { uint32_t tmppc = m68k_getpc() + 4; | |
2893 | uint32_t dsta = get_disp_ea_000(tmppc, get_iword(4)); | |
2894 | BusCyclePenalty += 2; | |
2895 | { int8_t dst = m68k_read_memory_8(dsta); | |
2896 | src &= 7; | |
2897 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
2898 | dst &= ~(1 << src); | |
2899 | m68k_write_memory_8(dsta,dst); | |
2900 | }}}}m68k_incpc(6); | |
2901 | return 22; | |
2902 | } | |
2903 | unsigned long CPUFUNC(op_8c0_4)(uint32_t opcode) /* BSET */ | |
2904 | { | |
2905 | uint32_t dstreg = opcode & 7; | |
2906 | OpcodeFamily = 24; CurrentInstrCycles = 12; | |
2907 | {{ int16_t src = get_iword(2); | |
2908 | { int32_t dst = m68k_dreg(regs, dstreg); | |
2909 | src &= 31; | |
2910 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
2911 | dst |= (1 << src); | |
2912 | m68k_dreg(regs, dstreg) = (dst); | |
2913 | }}}m68k_incpc(4); | |
2914 | return 12; | |
2915 | } | |
2916 | unsigned long CPUFUNC(op_8d0_4)(uint32_t opcode) /* BSET */ | |
2917 | { | |
2918 | uint32_t dstreg = opcode & 7; | |
2919 | OpcodeFamily = 24; CurrentInstrCycles = 16; | |
2920 | {{ int16_t src = get_iword(2); | |
2921 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
2922 | { int8_t dst = m68k_read_memory_8(dsta); | |
2923 | src &= 7; | |
2924 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
2925 | dst |= (1 << src); | |
2926 | m68k_write_memory_8(dsta,dst); | |
2927 | }}}}m68k_incpc(4); | |
2928 | return 16; | |
2929 | } | |
2930 | unsigned long CPUFUNC(op_8d8_4)(uint32_t opcode) /* BSET */ | |
2931 | { | |
2932 | uint32_t dstreg = opcode & 7; | |
2933 | OpcodeFamily = 24; CurrentInstrCycles = 16; | |
2934 | {{ int16_t src = get_iword(2); | |
2935 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
2936 | { int8_t dst = m68k_read_memory_8(dsta); | |
2937 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
2938 | src &= 7; | |
2939 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
2940 | dst |= (1 << src); | |
2941 | m68k_write_memory_8(dsta,dst); | |
2942 | }}}}m68k_incpc(4); | |
2943 | return 16; | |
2944 | } | |
2945 | unsigned long CPUFUNC(op_8e0_4)(uint32_t opcode) /* BSET */ | |
2946 | { | |
2947 | uint32_t dstreg = opcode & 7; | |
2948 | OpcodeFamily = 24; CurrentInstrCycles = 18; | |
2949 | {{ int16_t src = get_iword(2); | |
2950 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
2951 | { int8_t dst = m68k_read_memory_8(dsta); | |
2952 | m68k_areg (regs, dstreg) = dsta; | |
2953 | src &= 7; | |
2954 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
2955 | dst |= (1 << src); | |
2956 | m68k_write_memory_8(dsta,dst); | |
2957 | }}}}m68k_incpc(4); | |
2958 | return 18; | |
2959 | } | |
2960 | unsigned long CPUFUNC(op_8e8_4)(uint32_t opcode) /* BSET */ | |
2961 | { | |
2962 | uint32_t dstreg = opcode & 7; | |
2963 | OpcodeFamily = 24; CurrentInstrCycles = 20; | |
2964 | {{ int16_t src = get_iword(2); | |
2965 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); | |
2966 | { int8_t dst = m68k_read_memory_8(dsta); | |
2967 | src &= 7; | |
2968 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
2969 | dst |= (1 << src); | |
2970 | m68k_write_memory_8(dsta,dst); | |
2971 | }}}}m68k_incpc(6); | |
2972 | return 20; | |
2973 | } | |
2974 | unsigned long CPUFUNC(op_8f0_4)(uint32_t opcode) /* BSET */ | |
2975 | { | |
2976 | uint32_t dstreg = opcode & 7; | |
2977 | OpcodeFamily = 24; CurrentInstrCycles = 22; | |
2978 | {{ int16_t src = get_iword(2); | |
2979 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); | |
2980 | BusCyclePenalty += 2; | |
2981 | { int8_t dst = m68k_read_memory_8(dsta); | |
2982 | src &= 7; | |
2983 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
2984 | dst |= (1 << src); | |
2985 | m68k_write_memory_8(dsta,dst); | |
2986 | }}}}m68k_incpc(6); | |
2987 | return 22; | |
2988 | } | |
2989 | unsigned long CPUFUNC(op_8f8_4)(uint32_t opcode) /* BSET */ | |
2990 | { | |
2991 | OpcodeFamily = 24; CurrentInstrCycles = 20; | |
2992 | {{ int16_t src = get_iword(2); | |
2993 | { uint32_t dsta = (int32_t)(int16_t)get_iword(4); | |
2994 | { int8_t dst = m68k_read_memory_8(dsta); | |
2995 | src &= 7; | |
2996 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
2997 | dst |= (1 << src); | |
2998 | m68k_write_memory_8(dsta,dst); | |
2999 | }}}}m68k_incpc(6); | |
3000 | return 20; | |
3001 | } | |
3002 | unsigned long CPUFUNC(op_8f9_4)(uint32_t opcode) /* BSET */ | |
3003 | { | |
3004 | OpcodeFamily = 24; CurrentInstrCycles = 24; | |
3005 | {{ int16_t src = get_iword(2); | |
3006 | { uint32_t dsta = get_ilong(4); | |
3007 | { int8_t dst = m68k_read_memory_8(dsta); | |
3008 | src &= 7; | |
3009 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
3010 | dst |= (1 << src); | |
3011 | m68k_write_memory_8(dsta,dst); | |
3012 | }}}}m68k_incpc(8); | |
3013 | return 24; | |
3014 | } | |
3015 | unsigned long CPUFUNC(op_8fa_4)(uint32_t opcode) /* BSET */ | |
3016 | { | |
3017 | uint32_t dstreg = 2; | |
3018 | OpcodeFamily = 24; CurrentInstrCycles = 20; | |
3019 | {{ int16_t src = get_iword(2); | |
3020 | { uint32_t dsta = m68k_getpc () + 4; | |
3021 | dsta += (int32_t)(int16_t)get_iword(4); | |
3022 | { int8_t dst = m68k_read_memory_8(dsta); | |
3023 | src &= 7; | |
3024 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
3025 | dst |= (1 << src); | |
3026 | m68k_write_memory_8(dsta,dst); | |
3027 | }}}}m68k_incpc(6); | |
3028 | return 20; | |
3029 | } | |
3030 | unsigned long CPUFUNC(op_8fb_4)(uint32_t opcode) /* BSET */ | |
3031 | { | |
3032 | uint32_t dstreg = 3; | |
3033 | OpcodeFamily = 24; CurrentInstrCycles = 22; | |
3034 | {{ int16_t src = get_iword(2); | |
3035 | { uint32_t tmppc = m68k_getpc() + 4; | |
3036 | uint32_t dsta = get_disp_ea_000(tmppc, get_iword(4)); | |
3037 | BusCyclePenalty += 2; | |
3038 | { int8_t dst = m68k_read_memory_8(dsta); | |
3039 | src &= 7; | |
3040 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
3041 | dst |= (1 << src); | |
3042 | m68k_write_memory_8(dsta,dst); | |
3043 | }}}}m68k_incpc(6); | |
3044 | return 22; | |
3045 | } | |
3046 | unsigned long CPUFUNC(op_a00_4)(uint32_t opcode) /* EOR */ | |
3047 | { | |
3048 | uint32_t dstreg = opcode & 7; | |
3049 | OpcodeFamily = 3; CurrentInstrCycles = 8; | |
3050 | {{ int8_t src = get_ibyte(2); | |
3051 | { int8_t dst = m68k_dreg(regs, dstreg); | |
3052 | src ^= dst; | |
3053 | CLEAR_CZNV; | |
3054 | SET_ZFLG (((int8_t)(src)) == 0); | |
3055 | SET_NFLG (((int8_t)(src)) < 0); | |
3056 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
3057 | }}}m68k_incpc(4); | |
3058 | return 8; | |
3059 | } | |
3060 | unsigned long CPUFUNC(op_a10_4)(uint32_t opcode) /* EOR */ | |
3061 | { | |
3062 | uint32_t dstreg = opcode & 7; | |
3063 | OpcodeFamily = 3; CurrentInstrCycles = 16; | |
3064 | {{ int8_t src = get_ibyte(2); | |
3065 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
3066 | { int8_t dst = m68k_read_memory_8(dsta); | |
3067 | src ^= dst; | |
3068 | CLEAR_CZNV; | |
3069 | SET_ZFLG (((int8_t)(src)) == 0); | |
3070 | SET_NFLG (((int8_t)(src)) < 0); | |
3071 | m68k_write_memory_8(dsta,src); | |
3072 | }}}}m68k_incpc(4); | |
3073 | return 16; | |
3074 | } | |
3075 | unsigned long CPUFUNC(op_a18_4)(uint32_t opcode) /* EOR */ | |
3076 | { | |
3077 | uint32_t dstreg = opcode & 7; | |
3078 | OpcodeFamily = 3; CurrentInstrCycles = 16; | |
3079 | {{ int8_t src = get_ibyte(2); | |
3080 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
3081 | { int8_t dst = m68k_read_memory_8(dsta); | |
3082 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
3083 | src ^= dst; | |
3084 | CLEAR_CZNV; | |
3085 | SET_ZFLG (((int8_t)(src)) == 0); | |
3086 | SET_NFLG (((int8_t)(src)) < 0); | |
3087 | m68k_write_memory_8(dsta,src); | |
3088 | }}}}m68k_incpc(4); | |
3089 | return 16; | |
3090 | } | |
3091 | unsigned long CPUFUNC(op_a20_4)(uint32_t opcode) /* EOR */ | |
3092 | { | |
3093 | uint32_t dstreg = opcode & 7; | |
3094 | OpcodeFamily = 3; CurrentInstrCycles = 18; | |
3095 | {{ int8_t src = get_ibyte(2); | |
3096 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
3097 | { int8_t dst = m68k_read_memory_8(dsta); | |
3098 | m68k_areg (regs, dstreg) = dsta; | |
3099 | src ^= dst; | |
3100 | CLEAR_CZNV; | |
3101 | SET_ZFLG (((int8_t)(src)) == 0); | |
3102 | SET_NFLG (((int8_t)(src)) < 0); | |
3103 | m68k_write_memory_8(dsta,src); | |
3104 | }}}}m68k_incpc(4); | |
3105 | return 18; | |
3106 | } | |
3107 | unsigned long CPUFUNC(op_a28_4)(uint32_t opcode) /* EOR */ | |
3108 | { | |
3109 | uint32_t dstreg = opcode & 7; | |
3110 | OpcodeFamily = 3; CurrentInstrCycles = 20; | |
3111 | {{ int8_t src = get_ibyte(2); | |
3112 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); | |
3113 | { int8_t dst = m68k_read_memory_8(dsta); | |
3114 | src ^= dst; | |
3115 | CLEAR_CZNV; | |
3116 | SET_ZFLG (((int8_t)(src)) == 0); | |
3117 | SET_NFLG (((int8_t)(src)) < 0); | |
3118 | m68k_write_memory_8(dsta,src); | |
3119 | }}}}m68k_incpc(6); | |
3120 | return 20; | |
3121 | } | |
3122 | unsigned long CPUFUNC(op_a30_4)(uint32_t opcode) /* EOR */ | |
3123 | { | |
3124 | uint32_t dstreg = opcode & 7; | |
3125 | OpcodeFamily = 3; CurrentInstrCycles = 22; | |
3126 | {{ int8_t src = get_ibyte(2); | |
3127 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); | |
3128 | BusCyclePenalty += 2; | |
3129 | { int8_t dst = m68k_read_memory_8(dsta); | |
3130 | src ^= dst; | |
3131 | CLEAR_CZNV; | |
3132 | SET_ZFLG (((int8_t)(src)) == 0); | |
3133 | SET_NFLG (((int8_t)(src)) < 0); | |
3134 | m68k_write_memory_8(dsta,src); | |
3135 | }}}}m68k_incpc(6); | |
3136 | return 22; | |
3137 | } | |
3138 | unsigned long CPUFUNC(op_a38_4)(uint32_t opcode) /* EOR */ | |
3139 | { | |
3140 | OpcodeFamily = 3; CurrentInstrCycles = 20; | |
3141 | {{ int8_t src = get_ibyte(2); | |
3142 | { uint32_t dsta = (int32_t)(int16_t)get_iword(4); | |
3143 | { int8_t dst = m68k_read_memory_8(dsta); | |
3144 | src ^= dst; | |
3145 | CLEAR_CZNV; | |
3146 | SET_ZFLG (((int8_t)(src)) == 0); | |
3147 | SET_NFLG (((int8_t)(src)) < 0); | |
3148 | m68k_write_memory_8(dsta,src); | |
3149 | }}}}m68k_incpc(6); | |
3150 | return 20; | |
3151 | } | |
3152 | unsigned long CPUFUNC(op_a39_4)(uint32_t opcode) /* EOR */ | |
3153 | { | |
3154 | OpcodeFamily = 3; CurrentInstrCycles = 24; | |
3155 | {{ int8_t src = get_ibyte(2); | |
3156 | { uint32_t dsta = get_ilong(4); | |
3157 | { int8_t dst = m68k_read_memory_8(dsta); | |
3158 | src ^= dst; | |
3159 | CLEAR_CZNV; | |
3160 | SET_ZFLG (((int8_t)(src)) == 0); | |
3161 | SET_NFLG (((int8_t)(src)) < 0); | |
3162 | m68k_write_memory_8(dsta,src); | |
3163 | }}}}m68k_incpc(8); | |
3164 | return 24; | |
3165 | } | |
3166 | unsigned long CPUFUNC(op_a3c_4)(uint32_t opcode) /* EORSR */ | |
3167 | { | |
3168 | OpcodeFamily = 6; CurrentInstrCycles = 20; | |
3169 | { MakeSR(); | |
3170 | { int16_t src = get_iword(2); | |
3171 | src &= 0xFF; | |
3172 | regs.sr ^= src; | |
3173 | MakeFromSR(); | |
3174 | }}m68k_incpc(4); | |
3175 | return 20; | |
3176 | } | |
3177 | unsigned long CPUFUNC(op_a40_4)(uint32_t opcode) /* EOR */ | |
3178 | { | |
3179 | uint32_t dstreg = opcode & 7; | |
3180 | OpcodeFamily = 3; CurrentInstrCycles = 8; | |
3181 | {{ int16_t src = get_iword(2); | |
3182 | { int16_t dst = m68k_dreg(regs, dstreg); | |
3183 | src ^= dst; | |
3184 | CLEAR_CZNV; | |
3185 | SET_ZFLG (((int16_t)(src)) == 0); | |
3186 | SET_NFLG (((int16_t)(src)) < 0); | |
3187 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
3188 | }}}m68k_incpc(4); | |
3189 | return 8; | |
3190 | } | |
3191 | unsigned long CPUFUNC(op_a50_4)(uint32_t opcode) /* EOR */ | |
3192 | { | |
3193 | uint32_t dstreg = opcode & 7; | |
3194 | OpcodeFamily = 3; CurrentInstrCycles = 16; | |
3195 | {{ int16_t src = get_iword(2); | |
3196 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
3197 | { int16_t dst = m68k_read_memory_16(dsta); | |
3198 | src ^= dst; | |
3199 | CLEAR_CZNV; | |
3200 | SET_ZFLG (((int16_t)(src)) == 0); | |
3201 | SET_NFLG (((int16_t)(src)) < 0); | |
3202 | m68k_write_memory_16(dsta,src); | |
3203 | }}}}m68k_incpc(4); | |
3204 | return 16; | |
3205 | } | |
3206 | unsigned long CPUFUNC(op_a58_4)(uint32_t opcode) /* EOR */ | |
3207 | { | |
3208 | uint32_t dstreg = opcode & 7; | |
3209 | OpcodeFamily = 3; CurrentInstrCycles = 16; | |
3210 | {{ int16_t src = get_iword(2); | |
3211 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
3212 | { int16_t dst = m68k_read_memory_16(dsta); | |
3213 | m68k_areg(regs, dstreg) += 2; | |
3214 | src ^= dst; | |
3215 | CLEAR_CZNV; | |
3216 | SET_ZFLG (((int16_t)(src)) == 0); | |
3217 | SET_NFLG (((int16_t)(src)) < 0); | |
3218 | m68k_write_memory_16(dsta,src); | |
3219 | }}}}m68k_incpc(4); | |
3220 | return 16; | |
3221 | } | |
3222 | unsigned long CPUFUNC(op_a60_4)(uint32_t opcode) /* EOR */ | |
3223 | { | |
3224 | uint32_t dstreg = opcode & 7; | |
3225 | OpcodeFamily = 3; CurrentInstrCycles = 18; | |
3226 | {{ int16_t src = get_iword(2); | |
3227 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
3228 | { int16_t dst = m68k_read_memory_16(dsta); | |
3229 | m68k_areg (regs, dstreg) = dsta; | |
3230 | src ^= dst; | |
3231 | CLEAR_CZNV; | |
3232 | SET_ZFLG (((int16_t)(src)) == 0); | |
3233 | SET_NFLG (((int16_t)(src)) < 0); | |
3234 | m68k_write_memory_16(dsta,src); | |
3235 | }}}}m68k_incpc(4); | |
3236 | return 18; | |
3237 | } | |
3238 | unsigned long CPUFUNC(op_a68_4)(uint32_t opcode) /* EOR */ | |
3239 | { | |
3240 | uint32_t dstreg = opcode & 7; | |
3241 | OpcodeFamily = 3; CurrentInstrCycles = 20; | |
3242 | {{ int16_t src = get_iword(2); | |
3243 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); | |
3244 | { int16_t dst = m68k_read_memory_16(dsta); | |
3245 | src ^= dst; | |
3246 | CLEAR_CZNV; | |
3247 | SET_ZFLG (((int16_t)(src)) == 0); | |
3248 | SET_NFLG (((int16_t)(src)) < 0); | |
3249 | m68k_write_memory_16(dsta,src); | |
3250 | }}}}m68k_incpc(6); | |
3251 | return 20; | |
3252 | } | |
3253 | unsigned long CPUFUNC(op_a70_4)(uint32_t opcode) /* EOR */ | |
3254 | { | |
3255 | uint32_t dstreg = opcode & 7; | |
3256 | OpcodeFamily = 3; CurrentInstrCycles = 22; | |
3257 | {{ int16_t src = get_iword(2); | |
3258 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); | |
3259 | BusCyclePenalty += 2; | |
3260 | { int16_t dst = m68k_read_memory_16(dsta); | |
3261 | src ^= dst; | |
3262 | CLEAR_CZNV; | |
3263 | SET_ZFLG (((int16_t)(src)) == 0); | |
3264 | SET_NFLG (((int16_t)(src)) < 0); | |
3265 | m68k_write_memory_16(dsta,src); | |
3266 | }}}}m68k_incpc(6); | |
3267 | return 22; | |
3268 | } | |
3269 | unsigned long CPUFUNC(op_a78_4)(uint32_t opcode) /* EOR */ | |
3270 | { | |
3271 | OpcodeFamily = 3; CurrentInstrCycles = 20; | |
3272 | {{ int16_t src = get_iword(2); | |
3273 | { uint32_t dsta = (int32_t)(int16_t)get_iword(4); | |
3274 | { int16_t dst = m68k_read_memory_16(dsta); | |
3275 | src ^= dst; | |
3276 | CLEAR_CZNV; | |
3277 | SET_ZFLG (((int16_t)(src)) == 0); | |
3278 | SET_NFLG (((int16_t)(src)) < 0); | |
3279 | m68k_write_memory_16(dsta,src); | |
3280 | }}}}m68k_incpc(6); | |
3281 | return 20; | |
3282 | } | |
3283 | unsigned long CPUFUNC(op_a79_4)(uint32_t opcode) /* EOR */ | |
3284 | { | |
3285 | OpcodeFamily = 3; CurrentInstrCycles = 24; | |
3286 | {{ int16_t src = get_iword(2); | |
3287 | { uint32_t dsta = get_ilong(4); | |
3288 | { int16_t dst = m68k_read_memory_16(dsta); | |
3289 | src ^= dst; | |
3290 | CLEAR_CZNV; | |
3291 | SET_ZFLG (((int16_t)(src)) == 0); | |
3292 | SET_NFLG (((int16_t)(src)) < 0); | |
3293 | m68k_write_memory_16(dsta,src); | |
3294 | }}}}m68k_incpc(8); | |
3295 | return 24; | |
3296 | } | |
3297 | unsigned long CPUFUNC(op_a7c_4)(uint32_t opcode) /* EORSR */ | |
3298 | { | |
3299 | OpcodeFamily = 6; CurrentInstrCycles = 20; | |
3300 | {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel204; } | |
3301 | { MakeSR(); | |
3302 | { int16_t src = get_iword(2); | |
3303 | regs.sr ^= src; | |
3304 | MakeFromSR(); | |
3305 | }}}m68k_incpc(4); | |
3306 | endlabel204: ; | |
3307 | return 20; | |
3308 | } | |
3309 | #endif | |
3310 | ||
3311 | #ifdef PART_2 | |
3312 | unsigned long CPUFUNC(op_a80_4)(uint32_t opcode) /* EOR */ | |
3313 | { | |
3314 | uint32_t dstreg = opcode & 7; | |
3315 | OpcodeFamily = 3; CurrentInstrCycles = 16; | |
3316 | {{ int32_t src = get_ilong(2); | |
3317 | { int32_t dst = m68k_dreg(regs, dstreg); | |
3318 | src ^= dst; | |
3319 | CLEAR_CZNV; | |
3320 | SET_ZFLG (((int32_t)(src)) == 0); | |
3321 | SET_NFLG (((int32_t)(src)) < 0); | |
3322 | m68k_dreg(regs, dstreg) = (src); | |
3323 | }}}m68k_incpc(6); | |
3324 | return 16; | |
3325 | } | |
3326 | unsigned long CPUFUNC(op_a90_4)(uint32_t opcode) /* EOR */ | |
3327 | { | |
3328 | uint32_t dstreg = opcode & 7; | |
3329 | OpcodeFamily = 3; CurrentInstrCycles = 28; | |
3330 | {{ int32_t src = get_ilong(2); | |
3331 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
3332 | { int32_t dst = m68k_read_memory_32(dsta); | |
3333 | src ^= dst; | |
3334 | CLEAR_CZNV; | |
3335 | SET_ZFLG (((int32_t)(src)) == 0); | |
3336 | SET_NFLG (((int32_t)(src)) < 0); | |
3337 | m68k_write_memory_32(dsta,src); | |
3338 | }}}}m68k_incpc(6); | |
3339 | return 28; | |
3340 | } | |
3341 | unsigned long CPUFUNC(op_a98_4)(uint32_t opcode) /* EOR */ | |
3342 | { | |
3343 | uint32_t dstreg = opcode & 7; | |
3344 | OpcodeFamily = 3; CurrentInstrCycles = 28; | |
3345 | {{ int32_t src = get_ilong(2); | |
3346 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
3347 | { int32_t dst = m68k_read_memory_32(dsta); | |
3348 | m68k_areg(regs, dstreg) += 4; | |
3349 | src ^= dst; | |
3350 | CLEAR_CZNV; | |
3351 | SET_ZFLG (((int32_t)(src)) == 0); | |
3352 | SET_NFLG (((int32_t)(src)) < 0); | |
3353 | m68k_write_memory_32(dsta,src); | |
3354 | }}}}m68k_incpc(6); | |
3355 | return 28; | |
3356 | } | |
3357 | unsigned long CPUFUNC(op_aa0_4)(uint32_t opcode) /* EOR */ | |
3358 | { | |
3359 | uint32_t dstreg = opcode & 7; | |
3360 | OpcodeFamily = 3; CurrentInstrCycles = 30; | |
3361 | {{ int32_t src = get_ilong(2); | |
3362 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
3363 | { int32_t dst = m68k_read_memory_32(dsta); | |
3364 | m68k_areg (regs, dstreg) = dsta; | |
3365 | src ^= dst; | |
3366 | CLEAR_CZNV; | |
3367 | SET_ZFLG (((int32_t)(src)) == 0); | |
3368 | SET_NFLG (((int32_t)(src)) < 0); | |
3369 | m68k_write_memory_32(dsta,src); | |
3370 | }}}}m68k_incpc(6); | |
3371 | return 30; | |
3372 | } | |
3373 | unsigned long CPUFUNC(op_aa8_4)(uint32_t opcode) /* EOR */ | |
3374 | { | |
3375 | uint32_t dstreg = opcode & 7; | |
3376 | OpcodeFamily = 3; CurrentInstrCycles = 32; | |
3377 | {{ int32_t src = get_ilong(2); | |
3378 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(6); | |
3379 | { int32_t dst = m68k_read_memory_32(dsta); | |
3380 | src ^= dst; | |
3381 | CLEAR_CZNV; | |
3382 | SET_ZFLG (((int32_t)(src)) == 0); | |
3383 | SET_NFLG (((int32_t)(src)) < 0); | |
3384 | m68k_write_memory_32(dsta,src); | |
3385 | }}}}m68k_incpc(8); | |
3386 | return 32; | |
3387 | } | |
3388 | unsigned long CPUFUNC(op_ab0_4)(uint32_t opcode) /* EOR */ | |
3389 | { | |
3390 | uint32_t dstreg = opcode & 7; | |
3391 | OpcodeFamily = 3; CurrentInstrCycles = 34; | |
3392 | {{ int32_t src = get_ilong(2); | |
3393 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(6)); | |
3394 | BusCyclePenalty += 2; | |
3395 | { int32_t dst = m68k_read_memory_32(dsta); | |
3396 | src ^= dst; | |
3397 | CLEAR_CZNV; | |
3398 | SET_ZFLG (((int32_t)(src)) == 0); | |
3399 | SET_NFLG (((int32_t)(src)) < 0); | |
3400 | m68k_write_memory_32(dsta,src); | |
3401 | }}}}m68k_incpc(8); | |
3402 | return 34; | |
3403 | } | |
3404 | unsigned long CPUFUNC(op_ab8_4)(uint32_t opcode) /* EOR */ | |
3405 | { | |
3406 | OpcodeFamily = 3; CurrentInstrCycles = 32; | |
3407 | {{ int32_t src = get_ilong(2); | |
3408 | { uint32_t dsta = (int32_t)(int16_t)get_iword(6); | |
3409 | { int32_t dst = m68k_read_memory_32(dsta); | |
3410 | src ^= dst; | |
3411 | CLEAR_CZNV; | |
3412 | SET_ZFLG (((int32_t)(src)) == 0); | |
3413 | SET_NFLG (((int32_t)(src)) < 0); | |
3414 | m68k_write_memory_32(dsta,src); | |
3415 | }}}}m68k_incpc(8); | |
3416 | return 32; | |
3417 | } | |
3418 | unsigned long CPUFUNC(op_ab9_4)(uint32_t opcode) /* EOR */ | |
3419 | { | |
3420 | OpcodeFamily = 3; CurrentInstrCycles = 36; | |
3421 | {{ int32_t src = get_ilong(2); | |
3422 | { uint32_t dsta = get_ilong(6); | |
3423 | { int32_t dst = m68k_read_memory_32(dsta); | |
3424 | src ^= dst; | |
3425 | CLEAR_CZNV; | |
3426 | SET_ZFLG (((int32_t)(src)) == 0); | |
3427 | SET_NFLG (((int32_t)(src)) < 0); | |
3428 | m68k_write_memory_32(dsta,src); | |
3429 | }}}}m68k_incpc(10); | |
3430 | return 36; | |
3431 | } | |
3432 | unsigned long CPUFUNC(op_c00_4)(uint32_t opcode) /* CMP */ | |
3433 | { | |
3434 | uint32_t dstreg = opcode & 7; | |
3435 | OpcodeFamily = 25; CurrentInstrCycles = 8; | |
3436 | {{ int8_t src = get_ibyte(2); | |
3437 | { int8_t dst = m68k_dreg(regs, dstreg); | |
3438 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
3439 | { int flgs = ((int8_t)(src)) < 0; | |
3440 | int flgo = ((int8_t)(dst)) < 0; | |
3441 | int flgn = ((int8_t)(newv)) < 0; | |
3442 | SET_ZFLG (((int8_t)(newv)) == 0); | |
3443 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
3444 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
3445 | SET_NFLG (flgn != 0); | |
3446 | }}}}}}m68k_incpc(4); | |
3447 | return 8; | |
3448 | } | |
3449 | unsigned long CPUFUNC(op_c10_4)(uint32_t opcode) /* CMP */ | |
3450 | { | |
3451 | uint32_t dstreg = opcode & 7; | |
3452 | OpcodeFamily = 25; CurrentInstrCycles = 12; | |
3453 | {{ int8_t src = get_ibyte(2); | |
3454 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
3455 | { int8_t dst = m68k_read_memory_8(dsta); | |
3456 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
3457 | { int flgs = ((int8_t)(src)) < 0; | |
3458 | int flgo = ((int8_t)(dst)) < 0; | |
3459 | int flgn = ((int8_t)(newv)) < 0; | |
3460 | SET_ZFLG (((int8_t)(newv)) == 0); | |
3461 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
3462 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
3463 | SET_NFLG (flgn != 0); | |
3464 | }}}}}}}m68k_incpc(4); | |
3465 | return 12; | |
3466 | } | |
3467 | unsigned long CPUFUNC(op_c18_4)(uint32_t opcode) /* CMP */ | |
3468 | { | |
3469 | uint32_t dstreg = opcode & 7; | |
3470 | OpcodeFamily = 25; CurrentInstrCycles = 12; | |
3471 | {{ int8_t src = get_ibyte(2); | |
3472 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
3473 | { int8_t dst = m68k_read_memory_8(dsta); | |
3474 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
3475 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
3476 | { int flgs = ((int8_t)(src)) < 0; | |
3477 | int flgo = ((int8_t)(dst)) < 0; | |
3478 | int flgn = ((int8_t)(newv)) < 0; | |
3479 | SET_ZFLG (((int8_t)(newv)) == 0); | |
3480 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
3481 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
3482 | SET_NFLG (flgn != 0); | |
3483 | }}}}}}}m68k_incpc(4); | |
3484 | return 12; | |
3485 | } | |
3486 | unsigned long CPUFUNC(op_c20_4)(uint32_t opcode) /* CMP */ | |
3487 | { | |
3488 | uint32_t dstreg = opcode & 7; | |
3489 | OpcodeFamily = 25; CurrentInstrCycles = 14; | |
3490 | {{ int8_t src = get_ibyte(2); | |
3491 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
3492 | { int8_t dst = m68k_read_memory_8(dsta); | |
3493 | m68k_areg (regs, dstreg) = dsta; | |
3494 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
3495 | { int flgs = ((int8_t)(src)) < 0; | |
3496 | int flgo = ((int8_t)(dst)) < 0; | |
3497 | int flgn = ((int8_t)(newv)) < 0; | |
3498 | SET_ZFLG (((int8_t)(newv)) == 0); | |
3499 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
3500 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
3501 | SET_NFLG (flgn != 0); | |
3502 | }}}}}}}m68k_incpc(4); | |
3503 | return 14; | |
3504 | } | |
3505 | unsigned long CPUFUNC(op_c28_4)(uint32_t opcode) /* CMP */ | |
3506 | { | |
3507 | uint32_t dstreg = opcode & 7; | |
3508 | OpcodeFamily = 25; CurrentInstrCycles = 16; | |
3509 | {{ int8_t src = get_ibyte(2); | |
3510 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); | |
3511 | { int8_t dst = m68k_read_memory_8(dsta); | |
3512 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
3513 | { int flgs = ((int8_t)(src)) < 0; | |
3514 | int flgo = ((int8_t)(dst)) < 0; | |
3515 | int flgn = ((int8_t)(newv)) < 0; | |
3516 | SET_ZFLG (((int8_t)(newv)) == 0); | |
3517 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
3518 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
3519 | SET_NFLG (flgn != 0); | |
3520 | }}}}}}}m68k_incpc(6); | |
3521 | return 16; | |
3522 | } | |
3523 | unsigned long CPUFUNC(op_c30_4)(uint32_t opcode) /* CMP */ | |
3524 | { | |
3525 | uint32_t dstreg = opcode & 7; | |
3526 | OpcodeFamily = 25; CurrentInstrCycles = 18; | |
3527 | {{ int8_t src = get_ibyte(2); | |
3528 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); | |
3529 | BusCyclePenalty += 2; | |
3530 | { int8_t dst = m68k_read_memory_8(dsta); | |
3531 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
3532 | { int flgs = ((int8_t)(src)) < 0; | |
3533 | int flgo = ((int8_t)(dst)) < 0; | |
3534 | int flgn = ((int8_t)(newv)) < 0; | |
3535 | SET_ZFLG (((int8_t)(newv)) == 0); | |
3536 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
3537 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
3538 | SET_NFLG (flgn != 0); | |
3539 | }}}}}}}m68k_incpc(6); | |
3540 | return 18; | |
3541 | } | |
3542 | unsigned long CPUFUNC(op_c38_4)(uint32_t opcode) /* CMP */ | |
3543 | { | |
3544 | OpcodeFamily = 25; CurrentInstrCycles = 16; | |
3545 | {{ int8_t src = get_ibyte(2); | |
3546 | { uint32_t dsta = (int32_t)(int16_t)get_iword(4); | |
3547 | { int8_t dst = m68k_read_memory_8(dsta); | |
3548 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
3549 | { int flgs = ((int8_t)(src)) < 0; | |
3550 | int flgo = ((int8_t)(dst)) < 0; | |
3551 | int flgn = ((int8_t)(newv)) < 0; | |
3552 | SET_ZFLG (((int8_t)(newv)) == 0); | |
3553 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
3554 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
3555 | SET_NFLG (flgn != 0); | |
3556 | }}}}}}}m68k_incpc(6); | |
3557 | return 16; | |
3558 | } | |
3559 | unsigned long CPUFUNC(op_c39_4)(uint32_t opcode) /* CMP */ | |
3560 | { | |
3561 | OpcodeFamily = 25; CurrentInstrCycles = 20; | |
3562 | {{ int8_t src = get_ibyte(2); | |
3563 | { uint32_t dsta = get_ilong(4); | |
3564 | { int8_t dst = m68k_read_memory_8(dsta); | |
3565 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
3566 | { int flgs = ((int8_t)(src)) < 0; | |
3567 | int flgo = ((int8_t)(dst)) < 0; | |
3568 | int flgn = ((int8_t)(newv)) < 0; | |
3569 | SET_ZFLG (((int8_t)(newv)) == 0); | |
3570 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
3571 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
3572 | SET_NFLG (flgn != 0); | |
3573 | }}}}}}}m68k_incpc(8); | |
3574 | return 20; | |
3575 | } | |
3576 | unsigned long CPUFUNC(op_c3a_4)(uint32_t opcode) /* CMP */ | |
3577 | { | |
3578 | uint32_t dstreg = 2; | |
3579 | OpcodeFamily = 25; CurrentInstrCycles = 16; | |
3580 | {{ int8_t src = get_ibyte(2); | |
3581 | { uint32_t dsta = m68k_getpc () + 4; | |
3582 | dsta += (int32_t)(int16_t)get_iword(4); | |
3583 | { int8_t dst = m68k_read_memory_8(dsta); | |
3584 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
3585 | { int flgs = ((int8_t)(src)) < 0; | |
3586 | int flgo = ((int8_t)(dst)) < 0; | |
3587 | int flgn = ((int8_t)(newv)) < 0; | |
3588 | SET_ZFLG (((int8_t)(newv)) == 0); | |
3589 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
3590 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
3591 | SET_NFLG (flgn != 0); | |
3592 | }}}}}}}m68k_incpc(6); | |
3593 | return 16; | |
3594 | } | |
3595 | unsigned long CPUFUNC(op_c3b_4)(uint32_t opcode) /* CMP */ | |
3596 | { | |
3597 | uint32_t dstreg = 3; | |
3598 | OpcodeFamily = 25; CurrentInstrCycles = 18; | |
3599 | {{ int8_t src = get_ibyte(2); | |
3600 | { uint32_t tmppc = m68k_getpc() + 4; | |
3601 | uint32_t dsta = get_disp_ea_000(tmppc, get_iword(4)); | |
3602 | BusCyclePenalty += 2; | |
3603 | { int8_t dst = m68k_read_memory_8(dsta); | |
3604 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
3605 | { int flgs = ((int8_t)(src)) < 0; | |
3606 | int flgo = ((int8_t)(dst)) < 0; | |
3607 | int flgn = ((int8_t)(newv)) < 0; | |
3608 | SET_ZFLG (((int8_t)(newv)) == 0); | |
3609 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
3610 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
3611 | SET_NFLG (flgn != 0); | |
3612 | }}}}}}}m68k_incpc(6); | |
3613 | return 18; | |
3614 | } | |
3615 | unsigned long CPUFUNC(op_c40_4)(uint32_t opcode) /* CMP */ | |
3616 | { | |
3617 | uint32_t dstreg = opcode & 7; | |
3618 | OpcodeFamily = 25; CurrentInstrCycles = 8; | |
3619 | {{ int16_t src = get_iword(2); | |
3620 | { int16_t dst = m68k_dreg(regs, dstreg); | |
3621 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
3622 | { int flgs = ((int16_t)(src)) < 0; | |
3623 | int flgo = ((int16_t)(dst)) < 0; | |
3624 | int flgn = ((int16_t)(newv)) < 0; | |
3625 | SET_ZFLG (((int16_t)(newv)) == 0); | |
3626 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
3627 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
3628 | SET_NFLG (flgn != 0); | |
3629 | }}}}}}m68k_incpc(4); | |
3630 | return 8; | |
3631 | } | |
3632 | unsigned long CPUFUNC(op_c50_4)(uint32_t opcode) /* CMP */ | |
3633 | { | |
3634 | uint32_t dstreg = opcode & 7; | |
3635 | OpcodeFamily = 25; CurrentInstrCycles = 12; | |
3636 | {{ int16_t src = get_iword(2); | |
3637 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
3638 | { int16_t dst = m68k_read_memory_16(dsta); | |
3639 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
3640 | { int flgs = ((int16_t)(src)) < 0; | |
3641 | int flgo = ((int16_t)(dst)) < 0; | |
3642 | int flgn = ((int16_t)(newv)) < 0; | |
3643 | SET_ZFLG (((int16_t)(newv)) == 0); | |
3644 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
3645 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
3646 | SET_NFLG (flgn != 0); | |
3647 | }}}}}}}m68k_incpc(4); | |
3648 | return 12; | |
3649 | } | |
3650 | unsigned long CPUFUNC(op_c58_4)(uint32_t opcode) /* CMP */ | |
3651 | { | |
3652 | uint32_t dstreg = opcode & 7; | |
3653 | OpcodeFamily = 25; CurrentInstrCycles = 12; | |
3654 | {{ int16_t src = get_iword(2); | |
3655 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
3656 | { int16_t dst = m68k_read_memory_16(dsta); | |
3657 | m68k_areg(regs, dstreg) += 2; | |
3658 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
3659 | { int flgs = ((int16_t)(src)) < 0; | |
3660 | int flgo = ((int16_t)(dst)) < 0; | |
3661 | int flgn = ((int16_t)(newv)) < 0; | |
3662 | SET_ZFLG (((int16_t)(newv)) == 0); | |
3663 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
3664 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
3665 | SET_NFLG (flgn != 0); | |
3666 | }}}}}}}m68k_incpc(4); | |
3667 | return 12; | |
3668 | } | |
3669 | unsigned long CPUFUNC(op_c60_4)(uint32_t opcode) /* CMP */ | |
3670 | { | |
3671 | uint32_t dstreg = opcode & 7; | |
3672 | OpcodeFamily = 25; CurrentInstrCycles = 14; | |
3673 | {{ int16_t src = get_iword(2); | |
3674 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
3675 | { int16_t dst = m68k_read_memory_16(dsta); | |
3676 | m68k_areg (regs, dstreg) = dsta; | |
3677 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
3678 | { int flgs = ((int16_t)(src)) < 0; | |
3679 | int flgo = ((int16_t)(dst)) < 0; | |
3680 | int flgn = ((int16_t)(newv)) < 0; | |
3681 | SET_ZFLG (((int16_t)(newv)) == 0); | |
3682 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
3683 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
3684 | SET_NFLG (flgn != 0); | |
3685 | }}}}}}}m68k_incpc(4); | |
3686 | return 14; | |
3687 | } | |
3688 | unsigned long CPUFUNC(op_c68_4)(uint32_t opcode) /* CMP */ | |
3689 | { | |
3690 | uint32_t dstreg = opcode & 7; | |
3691 | OpcodeFamily = 25; CurrentInstrCycles = 16; | |
3692 | {{ int16_t src = get_iword(2); | |
3693 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); | |
3694 | { int16_t dst = m68k_read_memory_16(dsta); | |
3695 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
3696 | { int flgs = ((int16_t)(src)) < 0; | |
3697 | int flgo = ((int16_t)(dst)) < 0; | |
3698 | int flgn = ((int16_t)(newv)) < 0; | |
3699 | SET_ZFLG (((int16_t)(newv)) == 0); | |
3700 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
3701 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
3702 | SET_NFLG (flgn != 0); | |
3703 | }}}}}}}m68k_incpc(6); | |
3704 | return 16; | |
3705 | } | |
3706 | unsigned long CPUFUNC(op_c70_4)(uint32_t opcode) /* CMP */ | |
3707 | { | |
3708 | uint32_t dstreg = opcode & 7; | |
3709 | OpcodeFamily = 25; CurrentInstrCycles = 18; | |
3710 | {{ int16_t src = get_iword(2); | |
3711 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); | |
3712 | BusCyclePenalty += 2; | |
3713 | { int16_t dst = m68k_read_memory_16(dsta); | |
3714 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
3715 | { int flgs = ((int16_t)(src)) < 0; | |
3716 | int flgo = ((int16_t)(dst)) < 0; | |
3717 | int flgn = ((int16_t)(newv)) < 0; | |
3718 | SET_ZFLG (((int16_t)(newv)) == 0); | |
3719 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
3720 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
3721 | SET_NFLG (flgn != 0); | |
3722 | }}}}}}}m68k_incpc(6); | |
3723 | return 18; | |
3724 | } | |
3725 | unsigned long CPUFUNC(op_c78_4)(uint32_t opcode) /* CMP */ | |
3726 | { | |
3727 | OpcodeFamily = 25; CurrentInstrCycles = 16; | |
3728 | {{ int16_t src = get_iword(2); | |
3729 | { uint32_t dsta = (int32_t)(int16_t)get_iword(4); | |
3730 | { int16_t dst = m68k_read_memory_16(dsta); | |
3731 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
3732 | { int flgs = ((int16_t)(src)) < 0; | |
3733 | int flgo = ((int16_t)(dst)) < 0; | |
3734 | int flgn = ((int16_t)(newv)) < 0; | |
3735 | SET_ZFLG (((int16_t)(newv)) == 0); | |
3736 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
3737 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
3738 | SET_NFLG (flgn != 0); | |
3739 | }}}}}}}m68k_incpc(6); | |
3740 | return 16; | |
3741 | } | |
3742 | unsigned long CPUFUNC(op_c79_4)(uint32_t opcode) /* CMP */ | |
3743 | { | |
3744 | OpcodeFamily = 25; CurrentInstrCycles = 20; | |
3745 | {{ int16_t src = get_iword(2); | |
3746 | { uint32_t dsta = get_ilong(4); | |
3747 | { int16_t dst = m68k_read_memory_16(dsta); | |
3748 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
3749 | { int flgs = ((int16_t)(src)) < 0; | |
3750 | int flgo = ((int16_t)(dst)) < 0; | |
3751 | int flgn = ((int16_t)(newv)) < 0; | |
3752 | SET_ZFLG (((int16_t)(newv)) == 0); | |
3753 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
3754 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
3755 | SET_NFLG (flgn != 0); | |
3756 | }}}}}}}m68k_incpc(8); | |
3757 | return 20; | |
3758 | } | |
3759 | unsigned long CPUFUNC(op_c7a_4)(uint32_t opcode) /* CMP */ | |
3760 | { | |
3761 | uint32_t dstreg = 2; | |
3762 | OpcodeFamily = 25; CurrentInstrCycles = 16; | |
3763 | {{ int16_t src = get_iword(2); | |
3764 | { uint32_t dsta = m68k_getpc () + 4; | |
3765 | dsta += (int32_t)(int16_t)get_iword(4); | |
3766 | { int16_t dst = m68k_read_memory_16(dsta); | |
3767 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
3768 | { int flgs = ((int16_t)(src)) < 0; | |
3769 | int flgo = ((int16_t)(dst)) < 0; | |
3770 | int flgn = ((int16_t)(newv)) < 0; | |
3771 | SET_ZFLG (((int16_t)(newv)) == 0); | |
3772 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
3773 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
3774 | SET_NFLG (flgn != 0); | |
3775 | }}}}}}}m68k_incpc(6); | |
3776 | return 16; | |
3777 | } | |
3778 | unsigned long CPUFUNC(op_c7b_4)(uint32_t opcode) /* CMP */ | |
3779 | { | |
3780 | uint32_t dstreg = 3; | |
3781 | OpcodeFamily = 25; CurrentInstrCycles = 18; | |
3782 | {{ int16_t src = get_iword(2); | |
3783 | { uint32_t tmppc = m68k_getpc() + 4; | |
3784 | uint32_t dsta = get_disp_ea_000(tmppc, get_iword(4)); | |
3785 | BusCyclePenalty += 2; | |
3786 | { int16_t dst = m68k_read_memory_16(dsta); | |
3787 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
3788 | { int flgs = ((int16_t)(src)) < 0; | |
3789 | int flgo = ((int16_t)(dst)) < 0; | |
3790 | int flgn = ((int16_t)(newv)) < 0; | |
3791 | SET_ZFLG (((int16_t)(newv)) == 0); | |
3792 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
3793 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
3794 | SET_NFLG (flgn != 0); | |
3795 | }}}}}}}m68k_incpc(6); | |
3796 | return 18; | |
3797 | } | |
3798 | unsigned long CPUFUNC(op_c80_4)(uint32_t opcode) /* CMP */ | |
3799 | { | |
3800 | uint32_t dstreg = opcode & 7; | |
3801 | OpcodeFamily = 25; CurrentInstrCycles = 14; | |
3802 | {{ int32_t src = get_ilong(2); | |
3803 | { int32_t dst = m68k_dreg(regs, dstreg); | |
3804 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
3805 | { int flgs = ((int32_t)(src)) < 0; | |
3806 | int flgo = ((int32_t)(dst)) < 0; | |
3807 | int flgn = ((int32_t)(newv)) < 0; | |
3808 | SET_ZFLG (((int32_t)(newv)) == 0); | |
3809 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
3810 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
3811 | SET_NFLG (flgn != 0); | |
3812 | }}}}}}m68k_incpc(6); | |
3813 | return 14; | |
3814 | } | |
3815 | unsigned long CPUFUNC(op_c90_4)(uint32_t opcode) /* CMP */ | |
3816 | { | |
3817 | uint32_t dstreg = opcode & 7; | |
3818 | OpcodeFamily = 25; CurrentInstrCycles = 20; | |
3819 | {{ int32_t src = get_ilong(2); | |
3820 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
3821 | { int32_t dst = m68k_read_memory_32(dsta); | |
3822 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
3823 | { int flgs = ((int32_t)(src)) < 0; | |
3824 | int flgo = ((int32_t)(dst)) < 0; | |
3825 | int flgn = ((int32_t)(newv)) < 0; | |
3826 | SET_ZFLG (((int32_t)(newv)) == 0); | |
3827 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
3828 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
3829 | SET_NFLG (flgn != 0); | |
3830 | }}}}}}}m68k_incpc(6); | |
3831 | return 20; | |
3832 | } | |
3833 | unsigned long CPUFUNC(op_c98_4)(uint32_t opcode) /* CMP */ | |
3834 | { | |
3835 | uint32_t dstreg = opcode & 7; | |
3836 | OpcodeFamily = 25; CurrentInstrCycles = 20; | |
3837 | {{ int32_t src = get_ilong(2); | |
3838 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
3839 | { int32_t dst = m68k_read_memory_32(dsta); | |
3840 | m68k_areg(regs, dstreg) += 4; | |
3841 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
3842 | { int flgs = ((int32_t)(src)) < 0; | |
3843 | int flgo = ((int32_t)(dst)) < 0; | |
3844 | int flgn = ((int32_t)(newv)) < 0; | |
3845 | SET_ZFLG (((int32_t)(newv)) == 0); | |
3846 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
3847 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
3848 | SET_NFLG (flgn != 0); | |
3849 | }}}}}}}m68k_incpc(6); | |
3850 | return 20; | |
3851 | } | |
3852 | unsigned long CPUFUNC(op_ca0_4)(uint32_t opcode) /* CMP */ | |
3853 | { | |
3854 | uint32_t dstreg = opcode & 7; | |
3855 | OpcodeFamily = 25; CurrentInstrCycles = 22; | |
3856 | {{ int32_t src = get_ilong(2); | |
3857 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
3858 | { int32_t dst = m68k_read_memory_32(dsta); | |
3859 | m68k_areg (regs, dstreg) = dsta; | |
3860 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
3861 | { int flgs = ((int32_t)(src)) < 0; | |
3862 | int flgo = ((int32_t)(dst)) < 0; | |
3863 | int flgn = ((int32_t)(newv)) < 0; | |
3864 | SET_ZFLG (((int32_t)(newv)) == 0); | |
3865 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
3866 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
3867 | SET_NFLG (flgn != 0); | |
3868 | }}}}}}}m68k_incpc(6); | |
3869 | return 22; | |
3870 | } | |
3871 | unsigned long CPUFUNC(op_ca8_4)(uint32_t opcode) /* CMP */ | |
3872 | { | |
3873 | uint32_t dstreg = opcode & 7; | |
3874 | OpcodeFamily = 25; CurrentInstrCycles = 24; | |
3875 | {{ int32_t src = get_ilong(2); | |
3876 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(6); | |
3877 | { int32_t dst = m68k_read_memory_32(dsta); | |
3878 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
3879 | { int flgs = ((int32_t)(src)) < 0; | |
3880 | int flgo = ((int32_t)(dst)) < 0; | |
3881 | int flgn = ((int32_t)(newv)) < 0; | |
3882 | SET_ZFLG (((int32_t)(newv)) == 0); | |
3883 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
3884 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
3885 | SET_NFLG (flgn != 0); | |
3886 | }}}}}}}m68k_incpc(8); | |
3887 | return 24; | |
3888 | } | |
3889 | unsigned long CPUFUNC(op_cb0_4)(uint32_t opcode) /* CMP */ | |
3890 | { | |
3891 | uint32_t dstreg = opcode & 7; | |
3892 | OpcodeFamily = 25; CurrentInstrCycles = 26; | |
3893 | {{ int32_t src = get_ilong(2); | |
3894 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(6)); | |
3895 | BusCyclePenalty += 2; | |
3896 | { int32_t dst = m68k_read_memory_32(dsta); | |
3897 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
3898 | { int flgs = ((int32_t)(src)) < 0; | |
3899 | int flgo = ((int32_t)(dst)) < 0; | |
3900 | int flgn = ((int32_t)(newv)) < 0; | |
3901 | SET_ZFLG (((int32_t)(newv)) == 0); | |
3902 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
3903 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
3904 | SET_NFLG (flgn != 0); | |
3905 | }}}}}}}m68k_incpc(8); | |
3906 | return 26; | |
3907 | } | |
3908 | unsigned long CPUFUNC(op_cb8_4)(uint32_t opcode) /* CMP */ | |
3909 | { | |
3910 | OpcodeFamily = 25; CurrentInstrCycles = 24; | |
3911 | {{ int32_t src = get_ilong(2); | |
3912 | { uint32_t dsta = (int32_t)(int16_t)get_iword(6); | |
3913 | { int32_t dst = m68k_read_memory_32(dsta); | |
3914 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
3915 | { int flgs = ((int32_t)(src)) < 0; | |
3916 | int flgo = ((int32_t)(dst)) < 0; | |
3917 | int flgn = ((int32_t)(newv)) < 0; | |
3918 | SET_ZFLG (((int32_t)(newv)) == 0); | |
3919 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
3920 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
3921 | SET_NFLG (flgn != 0); | |
3922 | }}}}}}}m68k_incpc(8); | |
3923 | return 24; | |
3924 | } | |
3925 | unsigned long CPUFUNC(op_cb9_4)(uint32_t opcode) /* CMP */ | |
3926 | { | |
3927 | OpcodeFamily = 25; CurrentInstrCycles = 28; | |
3928 | {{ int32_t src = get_ilong(2); | |
3929 | { uint32_t dsta = get_ilong(6); | |
3930 | { int32_t dst = m68k_read_memory_32(dsta); | |
3931 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
3932 | { int flgs = ((int32_t)(src)) < 0; | |
3933 | int flgo = ((int32_t)(dst)) < 0; | |
3934 | int flgn = ((int32_t)(newv)) < 0; | |
3935 | SET_ZFLG (((int32_t)(newv)) == 0); | |
3936 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
3937 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
3938 | SET_NFLG (flgn != 0); | |
3939 | }}}}}}}m68k_incpc(10); | |
3940 | return 28; | |
3941 | } | |
3942 | unsigned long CPUFUNC(op_cba_4)(uint32_t opcode) /* CMP */ | |
3943 | { | |
3944 | uint32_t dstreg = 2; | |
3945 | OpcodeFamily = 25; CurrentInstrCycles = 24; | |
3946 | {{ int32_t src = get_ilong(2); | |
3947 | { uint32_t dsta = m68k_getpc () + 6; | |
3948 | dsta += (int32_t)(int16_t)get_iword(6); | |
3949 | { int32_t dst = m68k_read_memory_32(dsta); | |
3950 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
3951 | { int flgs = ((int32_t)(src)) < 0; | |
3952 | int flgo = ((int32_t)(dst)) < 0; | |
3953 | int flgn = ((int32_t)(newv)) < 0; | |
3954 | SET_ZFLG (((int32_t)(newv)) == 0); | |
3955 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
3956 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
3957 | SET_NFLG (flgn != 0); | |
3958 | }}}}}}}m68k_incpc(8); | |
3959 | return 24; | |
3960 | } | |
3961 | unsigned long CPUFUNC(op_cbb_4)(uint32_t opcode) /* CMP */ | |
3962 | { | |
3963 | uint32_t dstreg = 3; | |
3964 | OpcodeFamily = 25; CurrentInstrCycles = 26; | |
3965 | {{ int32_t src = get_ilong(2); | |
3966 | { uint32_t tmppc = m68k_getpc() + 6; | |
3967 | uint32_t dsta = get_disp_ea_000(tmppc, get_iword(6)); | |
3968 | BusCyclePenalty += 2; | |
3969 | { int32_t dst = m68k_read_memory_32(dsta); | |
3970 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
3971 | { int flgs = ((int32_t)(src)) < 0; | |
3972 | int flgo = ((int32_t)(dst)) < 0; | |
3973 | int flgn = ((int32_t)(newv)) < 0; | |
3974 | SET_ZFLG (((int32_t)(newv)) == 0); | |
3975 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
3976 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
3977 | SET_NFLG (flgn != 0); | |
3978 | }}}}}}}m68k_incpc(8); | |
3979 | return 26; | |
3980 | } | |
3981 | unsigned long CPUFUNC(op_1000_4)(uint32_t opcode) /* MOVE */ | |
3982 | { | |
3983 | uint32_t srcreg = (opcode & 7); | |
3984 | uint32_t dstreg = (opcode >> 9) & 7; | |
3985 | OpcodeFamily = 30; CurrentInstrCycles = 4; | |
3986 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
3987 | { CLEAR_CZNV; | |
3988 | SET_ZFLG (((int8_t)(src)) == 0); | |
3989 | SET_NFLG (((int8_t)(src)) < 0); | |
3990 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
3991 | }}}m68k_incpc(2); | |
3992 | return 4; | |
3993 | } | |
3994 | unsigned long CPUFUNC(op_1008_4)(uint32_t opcode) /* MOVE */ | |
3995 | { | |
3996 | uint32_t srcreg = (opcode & 7); | |
3997 | uint32_t dstreg = (opcode >> 9) & 7; | |
3998 | OpcodeFamily = 30; CurrentInstrCycles = 4; | |
3999 | {{ int8_t src = m68k_areg(regs, srcreg); | |
4000 | { CLEAR_CZNV; | |
4001 | SET_ZFLG (((int8_t)(src)) == 0); | |
4002 | SET_NFLG (((int8_t)(src)) < 0); | |
4003 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
4004 | }}}m68k_incpc(2); | |
4005 | return 4; | |
4006 | } | |
4007 | unsigned long CPUFUNC(op_1010_4)(uint32_t opcode) /* MOVE */ | |
4008 | { | |
4009 | uint32_t srcreg = (opcode & 7); | |
4010 | uint32_t dstreg = (opcode >> 9) & 7; | |
4011 | OpcodeFamily = 30; CurrentInstrCycles = 8; | |
4012 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
4013 | { int8_t src = m68k_read_memory_8(srca); | |
4014 | { CLEAR_CZNV; | |
4015 | SET_ZFLG (((int8_t)(src)) == 0); | |
4016 | SET_NFLG (((int8_t)(src)) < 0); | |
4017 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
4018 | }}}}m68k_incpc(2); | |
4019 | return 8; | |
4020 | } | |
4021 | unsigned long CPUFUNC(op_1018_4)(uint32_t opcode) /* MOVE */ | |
4022 | { | |
4023 | uint32_t srcreg = (opcode & 7); | |
4024 | uint32_t dstreg = (opcode >> 9) & 7; | |
4025 | OpcodeFamily = 30; CurrentInstrCycles = 8; | |
4026 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
4027 | { int8_t src = m68k_read_memory_8(srca); | |
4028 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
4029 | { CLEAR_CZNV; | |
4030 | SET_ZFLG (((int8_t)(src)) == 0); | |
4031 | SET_NFLG (((int8_t)(src)) < 0); | |
4032 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
4033 | }}}}m68k_incpc(2); | |
4034 | return 8; | |
4035 | } | |
4036 | unsigned long CPUFUNC(op_1020_4)(uint32_t opcode) /* MOVE */ | |
4037 | { | |
4038 | uint32_t srcreg = (opcode & 7); | |
4039 | uint32_t dstreg = (opcode >> 9) & 7; | |
4040 | OpcodeFamily = 30; CurrentInstrCycles = 10; | |
4041 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
4042 | { int8_t src = m68k_read_memory_8(srca); | |
4043 | m68k_areg (regs, srcreg) = srca; | |
4044 | { CLEAR_CZNV; | |
4045 | SET_ZFLG (((int8_t)(src)) == 0); | |
4046 | SET_NFLG (((int8_t)(src)) < 0); | |
4047 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
4048 | }}}}m68k_incpc(2); | |
4049 | return 10; | |
4050 | } | |
4051 | unsigned long CPUFUNC(op_1028_4)(uint32_t opcode) /* MOVE */ | |
4052 | { | |
4053 | uint32_t srcreg = (opcode & 7); | |
4054 | uint32_t dstreg = (opcode >> 9) & 7; | |
4055 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
4056 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
4057 | { int8_t src = m68k_read_memory_8(srca); | |
4058 | { CLEAR_CZNV; | |
4059 | SET_ZFLG (((int8_t)(src)) == 0); | |
4060 | SET_NFLG (((int8_t)(src)) < 0); | |
4061 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
4062 | }}}}m68k_incpc(4); | |
4063 | return 12; | |
4064 | } | |
4065 | unsigned long CPUFUNC(op_1030_4)(uint32_t opcode) /* MOVE */ | |
4066 | { | |
4067 | uint32_t srcreg = (opcode & 7); | |
4068 | uint32_t dstreg = (opcode >> 9) & 7; | |
4069 | OpcodeFamily = 30; CurrentInstrCycles = 14; | |
4070 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
4071 | BusCyclePenalty += 2; | |
4072 | { int8_t src = m68k_read_memory_8(srca); | |
4073 | { CLEAR_CZNV; | |
4074 | SET_ZFLG (((int8_t)(src)) == 0); | |
4075 | SET_NFLG (((int8_t)(src)) < 0); | |
4076 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
4077 | }}}}m68k_incpc(4); | |
4078 | return 14; | |
4079 | } | |
4080 | unsigned long CPUFUNC(op_1038_4)(uint32_t opcode) /* MOVE */ | |
4081 | { | |
4082 | uint32_t dstreg = (opcode >> 9) & 7; | |
4083 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
4084 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
4085 | { int8_t src = m68k_read_memory_8(srca); | |
4086 | { CLEAR_CZNV; | |
4087 | SET_ZFLG (((int8_t)(src)) == 0); | |
4088 | SET_NFLG (((int8_t)(src)) < 0); | |
4089 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
4090 | }}}}m68k_incpc(4); | |
4091 | return 12; | |
4092 | } | |
4093 | unsigned long CPUFUNC(op_1039_4)(uint32_t opcode) /* MOVE */ | |
4094 | { | |
4095 | uint32_t dstreg = (opcode >> 9) & 7; | |
4096 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
4097 | {{ uint32_t srca = get_ilong(2); | |
4098 | { int8_t src = m68k_read_memory_8(srca); | |
4099 | { CLEAR_CZNV; | |
4100 | SET_ZFLG (((int8_t)(src)) == 0); | |
4101 | SET_NFLG (((int8_t)(src)) < 0); | |
4102 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
4103 | }}}}m68k_incpc(6); | |
4104 | return 16; | |
4105 | } | |
4106 | unsigned long CPUFUNC(op_103a_4)(uint32_t opcode) /* MOVE */ | |
4107 | { | |
4108 | uint32_t dstreg = (opcode >> 9) & 7; | |
4109 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
4110 | {{ uint32_t srca = m68k_getpc () + 2; | |
4111 | srca += (int32_t)(int16_t)get_iword(2); | |
4112 | { int8_t src = m68k_read_memory_8(srca); | |
4113 | { CLEAR_CZNV; | |
4114 | SET_ZFLG (((int8_t)(src)) == 0); | |
4115 | SET_NFLG (((int8_t)(src)) < 0); | |
4116 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
4117 | }}}}m68k_incpc(4); | |
4118 | return 12; | |
4119 | } | |
4120 | unsigned long CPUFUNC(op_103b_4)(uint32_t opcode) /* MOVE */ | |
4121 | { | |
4122 | uint32_t dstreg = (opcode >> 9) & 7; | |
4123 | OpcodeFamily = 30; CurrentInstrCycles = 14; | |
4124 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
4125 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
4126 | BusCyclePenalty += 2; | |
4127 | { int8_t src = m68k_read_memory_8(srca); | |
4128 | { CLEAR_CZNV; | |
4129 | SET_ZFLG (((int8_t)(src)) == 0); | |
4130 | SET_NFLG (((int8_t)(src)) < 0); | |
4131 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
4132 | }}}}m68k_incpc(4); | |
4133 | return 14; | |
4134 | } | |
4135 | unsigned long CPUFUNC(op_103c_4)(uint32_t opcode) /* MOVE */ | |
4136 | { | |
4137 | uint32_t dstreg = (opcode >> 9) & 7; | |
4138 | OpcodeFamily = 30; CurrentInstrCycles = 8; | |
4139 | {{ int8_t src = get_ibyte(2); | |
4140 | { CLEAR_CZNV; | |
4141 | SET_ZFLG (((int8_t)(src)) == 0); | |
4142 | SET_NFLG (((int8_t)(src)) < 0); | |
4143 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
4144 | }}}m68k_incpc(4); | |
4145 | return 8; | |
4146 | } | |
4147 | unsigned long CPUFUNC(op_1080_4)(uint32_t opcode) /* MOVE */ | |
4148 | { | |
4149 | uint32_t srcreg = (opcode & 7); | |
4150 | uint32_t dstreg = (opcode >> 9) & 7; | |
4151 | OpcodeFamily = 30; CurrentInstrCycles = 8; | |
4152 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
4153 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
4154 | CLEAR_CZNV; | |
4155 | SET_ZFLG (((int8_t)(src)) == 0); | |
4156 | SET_NFLG (((int8_t)(src)) < 0); | |
4157 | m68k_write_memory_8(dsta,src); | |
4158 | }}}m68k_incpc(2); | |
4159 | return 8; | |
4160 | } | |
4161 | unsigned long CPUFUNC(op_1088_4)(uint32_t opcode) /* MOVE */ | |
4162 | { | |
4163 | uint32_t srcreg = (opcode & 7); | |
4164 | uint32_t dstreg = (opcode >> 9) & 7; | |
4165 | OpcodeFamily = 30; CurrentInstrCycles = 8; | |
4166 | {{ int8_t src = m68k_areg(regs, srcreg); | |
4167 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
4168 | CLEAR_CZNV; | |
4169 | SET_ZFLG (((int8_t)(src)) == 0); | |
4170 | SET_NFLG (((int8_t)(src)) < 0); | |
4171 | m68k_write_memory_8(dsta,src); | |
4172 | }}}m68k_incpc(2); | |
4173 | return 8; | |
4174 | } | |
4175 | unsigned long CPUFUNC(op_1090_4)(uint32_t opcode) /* MOVE */ | |
4176 | { | |
4177 | uint32_t srcreg = (opcode & 7); | |
4178 | uint32_t dstreg = (opcode >> 9) & 7; | |
4179 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
4180 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
4181 | { int8_t src = m68k_read_memory_8(srca); | |
4182 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
4183 | CLEAR_CZNV; | |
4184 | SET_ZFLG (((int8_t)(src)) == 0); | |
4185 | SET_NFLG (((int8_t)(src)) < 0); | |
4186 | m68k_write_memory_8(dsta,src); | |
4187 | }}}}m68k_incpc(2); | |
4188 | return 12; | |
4189 | } | |
4190 | unsigned long CPUFUNC(op_1098_4)(uint32_t opcode) /* MOVE */ | |
4191 | { | |
4192 | uint32_t srcreg = (opcode & 7); | |
4193 | uint32_t dstreg = (opcode >> 9) & 7; | |
4194 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
4195 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
4196 | { int8_t src = m68k_read_memory_8(srca); | |
4197 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
4198 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
4199 | CLEAR_CZNV; | |
4200 | SET_ZFLG (((int8_t)(src)) == 0); | |
4201 | SET_NFLG (((int8_t)(src)) < 0); | |
4202 | m68k_write_memory_8(dsta,src); | |
4203 | }}}}m68k_incpc(2); | |
4204 | return 12; | |
4205 | } | |
4206 | unsigned long CPUFUNC(op_10a0_4)(uint32_t opcode) /* MOVE */ | |
4207 | { | |
4208 | uint32_t srcreg = (opcode & 7); | |
4209 | uint32_t dstreg = (opcode >> 9) & 7; | |
4210 | OpcodeFamily = 30; CurrentInstrCycles = 14; | |
4211 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
4212 | { int8_t src = m68k_read_memory_8(srca); | |
4213 | m68k_areg (regs, srcreg) = srca; | |
4214 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
4215 | CLEAR_CZNV; | |
4216 | SET_ZFLG (((int8_t)(src)) == 0); | |
4217 | SET_NFLG (((int8_t)(src)) < 0); | |
4218 | m68k_write_memory_8(dsta,src); | |
4219 | }}}}m68k_incpc(2); | |
4220 | return 14; | |
4221 | } | |
4222 | unsigned long CPUFUNC(op_10a8_4)(uint32_t opcode) /* MOVE */ | |
4223 | { | |
4224 | uint32_t srcreg = (opcode & 7); | |
4225 | uint32_t dstreg = (opcode >> 9) & 7; | |
4226 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
4227 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
4228 | { int8_t src = m68k_read_memory_8(srca); | |
4229 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
4230 | CLEAR_CZNV; | |
4231 | SET_ZFLG (((int8_t)(src)) == 0); | |
4232 | SET_NFLG (((int8_t)(src)) < 0); | |
4233 | m68k_write_memory_8(dsta,src); | |
4234 | }}}}m68k_incpc(4); | |
4235 | return 16; | |
4236 | } | |
4237 | unsigned long CPUFUNC(op_10b0_4)(uint32_t opcode) /* MOVE */ | |
4238 | { | |
4239 | uint32_t srcreg = (opcode & 7); | |
4240 | uint32_t dstreg = (opcode >> 9) & 7; | |
4241 | OpcodeFamily = 30; CurrentInstrCycles = 18; | |
4242 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
4243 | BusCyclePenalty += 2; | |
4244 | { int8_t src = m68k_read_memory_8(srca); | |
4245 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
4246 | CLEAR_CZNV; | |
4247 | SET_ZFLG (((int8_t)(src)) == 0); | |
4248 | SET_NFLG (((int8_t)(src)) < 0); | |
4249 | m68k_write_memory_8(dsta,src); | |
4250 | }}}}m68k_incpc(4); | |
4251 | return 18; | |
4252 | } | |
4253 | unsigned long CPUFUNC(op_10b8_4)(uint32_t opcode) /* MOVE */ | |
4254 | { | |
4255 | uint32_t dstreg = (opcode >> 9) & 7; | |
4256 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
4257 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
4258 | { int8_t src = m68k_read_memory_8(srca); | |
4259 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
4260 | CLEAR_CZNV; | |
4261 | SET_ZFLG (((int8_t)(src)) == 0); | |
4262 | SET_NFLG (((int8_t)(src)) < 0); | |
4263 | m68k_write_memory_8(dsta,src); | |
4264 | }}}}m68k_incpc(4); | |
4265 | return 16; | |
4266 | } | |
4267 | unsigned long CPUFUNC(op_10b9_4)(uint32_t opcode) /* MOVE */ | |
4268 | { | |
4269 | uint32_t dstreg = (opcode >> 9) & 7; | |
4270 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
4271 | {{ uint32_t srca = get_ilong(2); | |
4272 | { int8_t src = m68k_read_memory_8(srca); | |
4273 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
4274 | CLEAR_CZNV; | |
4275 | SET_ZFLG (((int8_t)(src)) == 0); | |
4276 | SET_NFLG (((int8_t)(src)) < 0); | |
4277 | m68k_write_memory_8(dsta,src); | |
4278 | }}}}m68k_incpc(6); | |
4279 | return 20; | |
4280 | } | |
4281 | unsigned long CPUFUNC(op_10ba_4)(uint32_t opcode) /* MOVE */ | |
4282 | { | |
4283 | uint32_t dstreg = (opcode >> 9) & 7; | |
4284 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
4285 | {{ uint32_t srca = m68k_getpc () + 2; | |
4286 | srca += (int32_t)(int16_t)get_iword(2); | |
4287 | { int8_t src = m68k_read_memory_8(srca); | |
4288 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
4289 | CLEAR_CZNV; | |
4290 | SET_ZFLG (((int8_t)(src)) == 0); | |
4291 | SET_NFLG (((int8_t)(src)) < 0); | |
4292 | m68k_write_memory_8(dsta,src); | |
4293 | }}}}m68k_incpc(4); | |
4294 | return 16; | |
4295 | } | |
4296 | unsigned long CPUFUNC(op_10bb_4)(uint32_t opcode) /* MOVE */ | |
4297 | { | |
4298 | uint32_t dstreg = (opcode >> 9) & 7; | |
4299 | OpcodeFamily = 30; CurrentInstrCycles = 18; | |
4300 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
4301 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
4302 | BusCyclePenalty += 2; | |
4303 | { int8_t src = m68k_read_memory_8(srca); | |
4304 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
4305 | CLEAR_CZNV; | |
4306 | SET_ZFLG (((int8_t)(src)) == 0); | |
4307 | SET_NFLG (((int8_t)(src)) < 0); | |
4308 | m68k_write_memory_8(dsta,src); | |
4309 | }}}}m68k_incpc(4); | |
4310 | return 18; | |
4311 | } | |
4312 | unsigned long CPUFUNC(op_10bc_4)(uint32_t opcode) /* MOVE */ | |
4313 | { | |
4314 | uint32_t dstreg = (opcode >> 9) & 7; | |
4315 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
4316 | {{ int8_t src = get_ibyte(2); | |
4317 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
4318 | CLEAR_CZNV; | |
4319 | SET_ZFLG (((int8_t)(src)) == 0); | |
4320 | SET_NFLG (((int8_t)(src)) < 0); | |
4321 | m68k_write_memory_8(dsta,src); | |
4322 | }}}m68k_incpc(4); | |
4323 | return 12; | |
4324 | } | |
4325 | unsigned long CPUFUNC(op_10c0_4)(uint32_t opcode) /* MOVE */ | |
4326 | { | |
4327 | uint32_t srcreg = (opcode & 7); | |
4328 | uint32_t dstreg = (opcode >> 9) & 7; | |
4329 | OpcodeFamily = 30; CurrentInstrCycles = 8; | |
4330 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
4331 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
4332 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
4333 | CLEAR_CZNV; | |
4334 | SET_ZFLG (((int8_t)(src)) == 0); | |
4335 | SET_NFLG (((int8_t)(src)) < 0); | |
4336 | m68k_write_memory_8(dsta,src); | |
4337 | }}}m68k_incpc(2); | |
4338 | return 8; | |
4339 | } | |
4340 | unsigned long CPUFUNC(op_10c8_4)(uint32_t opcode) /* MOVE */ | |
4341 | { | |
4342 | uint32_t srcreg = (opcode & 7); | |
4343 | uint32_t dstreg = (opcode >> 9) & 7; | |
4344 | OpcodeFamily = 30; CurrentInstrCycles = 8; | |
4345 | {{ int8_t src = m68k_areg(regs, srcreg); | |
4346 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
4347 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
4348 | CLEAR_CZNV; | |
4349 | SET_ZFLG (((int8_t)(src)) == 0); | |
4350 | SET_NFLG (((int8_t)(src)) < 0); | |
4351 | m68k_write_memory_8(dsta,src); | |
4352 | }}}m68k_incpc(2); | |
4353 | return 8; | |
4354 | } | |
4355 | unsigned long CPUFUNC(op_10d0_4)(uint32_t opcode) /* MOVE */ | |
4356 | { | |
4357 | uint32_t srcreg = (opcode & 7); | |
4358 | uint32_t dstreg = (opcode >> 9) & 7; | |
4359 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
4360 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
4361 | { int8_t src = m68k_read_memory_8(srca); | |
4362 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
4363 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
4364 | CLEAR_CZNV; | |
4365 | SET_ZFLG (((int8_t)(src)) == 0); | |
4366 | SET_NFLG (((int8_t)(src)) < 0); | |
4367 | m68k_write_memory_8(dsta,src); | |
4368 | }}}}m68k_incpc(2); | |
4369 | return 12; | |
4370 | } | |
4371 | unsigned long CPUFUNC(op_10d8_4)(uint32_t opcode) /* MOVE */ | |
4372 | { | |
4373 | uint32_t srcreg = (opcode & 7); | |
4374 | uint32_t dstreg = (opcode >> 9) & 7; | |
4375 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
4376 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
4377 | { int8_t src = m68k_read_memory_8(srca); | |
4378 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
4379 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
4380 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
4381 | CLEAR_CZNV; | |
4382 | SET_ZFLG (((int8_t)(src)) == 0); | |
4383 | SET_NFLG (((int8_t)(src)) < 0); | |
4384 | m68k_write_memory_8(dsta,src); | |
4385 | }}}}m68k_incpc(2); | |
4386 | return 12; | |
4387 | } | |
4388 | unsigned long CPUFUNC(op_10e0_4)(uint32_t opcode) /* MOVE */ | |
4389 | { | |
4390 | uint32_t srcreg = (opcode & 7); | |
4391 | uint32_t dstreg = (opcode >> 9) & 7; | |
4392 | OpcodeFamily = 30; CurrentInstrCycles = 14; | |
4393 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
4394 | { int8_t src = m68k_read_memory_8(srca); | |
4395 | m68k_areg (regs, srcreg) = srca; | |
4396 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
4397 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
4398 | CLEAR_CZNV; | |
4399 | SET_ZFLG (((int8_t)(src)) == 0); | |
4400 | SET_NFLG (((int8_t)(src)) < 0); | |
4401 | m68k_write_memory_8(dsta,src); | |
4402 | }}}}m68k_incpc(2); | |
4403 | return 14; | |
4404 | } | |
4405 | unsigned long CPUFUNC(op_10e8_4)(uint32_t opcode) /* MOVE */ | |
4406 | { | |
4407 | uint32_t srcreg = (opcode & 7); | |
4408 | uint32_t dstreg = (opcode >> 9) & 7; | |
4409 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
4410 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
4411 | { int8_t src = m68k_read_memory_8(srca); | |
4412 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
4413 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
4414 | CLEAR_CZNV; | |
4415 | SET_ZFLG (((int8_t)(src)) == 0); | |
4416 | SET_NFLG (((int8_t)(src)) < 0); | |
4417 | m68k_write_memory_8(dsta,src); | |
4418 | }}}}m68k_incpc(4); | |
4419 | return 16; | |
4420 | } | |
4421 | unsigned long CPUFUNC(op_10f0_4)(uint32_t opcode) /* MOVE */ | |
4422 | { | |
4423 | uint32_t srcreg = (opcode & 7); | |
4424 | uint32_t dstreg = (opcode >> 9) & 7; | |
4425 | OpcodeFamily = 30; CurrentInstrCycles = 18; | |
4426 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
4427 | BusCyclePenalty += 2; | |
4428 | { int8_t src = m68k_read_memory_8(srca); | |
4429 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
4430 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
4431 | CLEAR_CZNV; | |
4432 | SET_ZFLG (((int8_t)(src)) == 0); | |
4433 | SET_NFLG (((int8_t)(src)) < 0); | |
4434 | m68k_write_memory_8(dsta,src); | |
4435 | }}}}m68k_incpc(4); | |
4436 | return 18; | |
4437 | } | |
4438 | unsigned long CPUFUNC(op_10f8_4)(uint32_t opcode) /* MOVE */ | |
4439 | { | |
4440 | uint32_t dstreg = (opcode >> 9) & 7; | |
4441 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
4442 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
4443 | { int8_t src = m68k_read_memory_8(srca); | |
4444 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
4445 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
4446 | CLEAR_CZNV; | |
4447 | SET_ZFLG (((int8_t)(src)) == 0); | |
4448 | SET_NFLG (((int8_t)(src)) < 0); | |
4449 | m68k_write_memory_8(dsta,src); | |
4450 | }}}}m68k_incpc(4); | |
4451 | return 16; | |
4452 | } | |
4453 | unsigned long CPUFUNC(op_10f9_4)(uint32_t opcode) /* MOVE */ | |
4454 | { | |
4455 | uint32_t dstreg = (opcode >> 9) & 7; | |
4456 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
4457 | {{ uint32_t srca = get_ilong(2); | |
4458 | { int8_t src = m68k_read_memory_8(srca); | |
4459 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
4460 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
4461 | CLEAR_CZNV; | |
4462 | SET_ZFLG (((int8_t)(src)) == 0); | |
4463 | SET_NFLG (((int8_t)(src)) < 0); | |
4464 | m68k_write_memory_8(dsta,src); | |
4465 | }}}}m68k_incpc(6); | |
4466 | return 20; | |
4467 | } | |
4468 | unsigned long CPUFUNC(op_10fa_4)(uint32_t opcode) /* MOVE */ | |
4469 | { | |
4470 | uint32_t dstreg = (opcode >> 9) & 7; | |
4471 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
4472 | {{ uint32_t srca = m68k_getpc () + 2; | |
4473 | srca += (int32_t)(int16_t)get_iword(2); | |
4474 | { int8_t src = m68k_read_memory_8(srca); | |
4475 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
4476 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
4477 | CLEAR_CZNV; | |
4478 | SET_ZFLG (((int8_t)(src)) == 0); | |
4479 | SET_NFLG (((int8_t)(src)) < 0); | |
4480 | m68k_write_memory_8(dsta,src); | |
4481 | }}}}m68k_incpc(4); | |
4482 | return 16; | |
4483 | } | |
4484 | unsigned long CPUFUNC(op_10fb_4)(uint32_t opcode) /* MOVE */ | |
4485 | { | |
4486 | uint32_t dstreg = (opcode >> 9) & 7; | |
4487 | OpcodeFamily = 30; CurrentInstrCycles = 18; | |
4488 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
4489 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
4490 | BusCyclePenalty += 2; | |
4491 | { int8_t src = m68k_read_memory_8(srca); | |
4492 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
4493 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
4494 | CLEAR_CZNV; | |
4495 | SET_ZFLG (((int8_t)(src)) == 0); | |
4496 | SET_NFLG (((int8_t)(src)) < 0); | |
4497 | m68k_write_memory_8(dsta,src); | |
4498 | }}}}m68k_incpc(4); | |
4499 | return 18; | |
4500 | } | |
4501 | unsigned long CPUFUNC(op_10fc_4)(uint32_t opcode) /* MOVE */ | |
4502 | { | |
4503 | uint32_t dstreg = (opcode >> 9) & 7; | |
4504 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
4505 | {{ int8_t src = get_ibyte(2); | |
4506 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
4507 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
4508 | CLEAR_CZNV; | |
4509 | SET_ZFLG (((int8_t)(src)) == 0); | |
4510 | SET_NFLG (((int8_t)(src)) < 0); | |
4511 | m68k_write_memory_8(dsta,src); | |
4512 | }}}m68k_incpc(4); | |
4513 | return 12; | |
4514 | } | |
4515 | unsigned long CPUFUNC(op_1100_4)(uint32_t opcode) /* MOVE */ | |
4516 | { | |
4517 | uint32_t srcreg = (opcode & 7); | |
4518 | uint32_t dstreg = (opcode >> 9) & 7; | |
4519 | OpcodeFamily = 30; CurrentInstrCycles = 8; | |
4520 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
4521 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
4522 | m68k_areg (regs, dstreg) = dsta; | |
4523 | CLEAR_CZNV; | |
4524 | SET_ZFLG (((int8_t)(src)) == 0); | |
4525 | SET_NFLG (((int8_t)(src)) < 0); | |
4526 | m68k_write_memory_8(dsta,src); | |
4527 | }}}m68k_incpc(2); | |
4528 | return 8; | |
4529 | } | |
4530 | unsigned long CPUFUNC(op_1108_4)(uint32_t opcode) /* MOVE */ | |
4531 | { | |
4532 | uint32_t srcreg = (opcode & 7); | |
4533 | uint32_t dstreg = (opcode >> 9) & 7; | |
4534 | OpcodeFamily = 30; CurrentInstrCycles = 8; | |
4535 | {{ int8_t src = m68k_areg(regs, srcreg); | |
4536 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
4537 | m68k_areg (regs, dstreg) = dsta; | |
4538 | CLEAR_CZNV; | |
4539 | SET_ZFLG (((int8_t)(src)) == 0); | |
4540 | SET_NFLG (((int8_t)(src)) < 0); | |
4541 | m68k_write_memory_8(dsta,src); | |
4542 | }}}m68k_incpc(2); | |
4543 | return 8; | |
4544 | } | |
4545 | unsigned long CPUFUNC(op_1110_4)(uint32_t opcode) /* MOVE */ | |
4546 | { | |
4547 | uint32_t srcreg = (opcode & 7); | |
4548 | uint32_t dstreg = (opcode >> 9) & 7; | |
4549 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
4550 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
4551 | { int8_t src = m68k_read_memory_8(srca); | |
4552 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
4553 | m68k_areg (regs, dstreg) = dsta; | |
4554 | CLEAR_CZNV; | |
4555 | SET_ZFLG (((int8_t)(src)) == 0); | |
4556 | SET_NFLG (((int8_t)(src)) < 0); | |
4557 | m68k_write_memory_8(dsta,src); | |
4558 | }}}}m68k_incpc(2); | |
4559 | return 12; | |
4560 | } | |
4561 | unsigned long CPUFUNC(op_1118_4)(uint32_t opcode) /* MOVE */ | |
4562 | { | |
4563 | uint32_t srcreg = (opcode & 7); | |
4564 | uint32_t dstreg = (opcode >> 9) & 7; | |
4565 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
4566 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
4567 | { int8_t src = m68k_read_memory_8(srca); | |
4568 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
4569 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
4570 | m68k_areg (regs, dstreg) = dsta; | |
4571 | CLEAR_CZNV; | |
4572 | SET_ZFLG (((int8_t)(src)) == 0); | |
4573 | SET_NFLG (((int8_t)(src)) < 0); | |
4574 | m68k_write_memory_8(dsta,src); | |
4575 | }}}}m68k_incpc(2); | |
4576 | return 12; | |
4577 | } | |
4578 | unsigned long CPUFUNC(op_1120_4)(uint32_t opcode) /* MOVE */ | |
4579 | { | |
4580 | uint32_t srcreg = (opcode & 7); | |
4581 | uint32_t dstreg = (opcode >> 9) & 7; | |
4582 | OpcodeFamily = 30; CurrentInstrCycles = 14; | |
4583 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
4584 | { int8_t src = m68k_read_memory_8(srca); | |
4585 | m68k_areg (regs, srcreg) = srca; | |
4586 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
4587 | m68k_areg (regs, dstreg) = dsta; | |
4588 | CLEAR_CZNV; | |
4589 | SET_ZFLG (((int8_t)(src)) == 0); | |
4590 | SET_NFLG (((int8_t)(src)) < 0); | |
4591 | m68k_write_memory_8(dsta,src); | |
4592 | }}}}m68k_incpc(2); | |
4593 | return 14; | |
4594 | } | |
4595 | unsigned long CPUFUNC(op_1128_4)(uint32_t opcode) /* MOVE */ | |
4596 | { | |
4597 | uint32_t srcreg = (opcode & 7); | |
4598 | uint32_t dstreg = (opcode >> 9) & 7; | |
4599 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
4600 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
4601 | { int8_t src = m68k_read_memory_8(srca); | |
4602 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
4603 | m68k_areg (regs, dstreg) = dsta; | |
4604 | CLEAR_CZNV; | |
4605 | SET_ZFLG (((int8_t)(src)) == 0); | |
4606 | SET_NFLG (((int8_t)(src)) < 0); | |
4607 | m68k_write_memory_8(dsta,src); | |
4608 | }}}}m68k_incpc(4); | |
4609 | return 16; | |
4610 | } | |
4611 | unsigned long CPUFUNC(op_1130_4)(uint32_t opcode) /* MOVE */ | |
4612 | { | |
4613 | uint32_t srcreg = (opcode & 7); | |
4614 | uint32_t dstreg = (opcode >> 9) & 7; | |
4615 | OpcodeFamily = 30; CurrentInstrCycles = 18; | |
4616 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
4617 | BusCyclePenalty += 2; | |
4618 | { int8_t src = m68k_read_memory_8(srca); | |
4619 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
4620 | m68k_areg (regs, dstreg) = dsta; | |
4621 | CLEAR_CZNV; | |
4622 | SET_ZFLG (((int8_t)(src)) == 0); | |
4623 | SET_NFLG (((int8_t)(src)) < 0); | |
4624 | m68k_write_memory_8(dsta,src); | |
4625 | }}}}m68k_incpc(4); | |
4626 | return 18; | |
4627 | } | |
4628 | unsigned long CPUFUNC(op_1138_4)(uint32_t opcode) /* MOVE */ | |
4629 | { | |
4630 | uint32_t dstreg = (opcode >> 9) & 7; | |
4631 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
4632 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
4633 | { int8_t src = m68k_read_memory_8(srca); | |
4634 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
4635 | m68k_areg (regs, dstreg) = dsta; | |
4636 | CLEAR_CZNV; | |
4637 | SET_ZFLG (((int8_t)(src)) == 0); | |
4638 | SET_NFLG (((int8_t)(src)) < 0); | |
4639 | m68k_write_memory_8(dsta,src); | |
4640 | }}}}m68k_incpc(4); | |
4641 | return 16; | |
4642 | } | |
4643 | unsigned long CPUFUNC(op_1139_4)(uint32_t opcode) /* MOVE */ | |
4644 | { | |
4645 | uint32_t dstreg = (opcode >> 9) & 7; | |
4646 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
4647 | {{ uint32_t srca = get_ilong(2); | |
4648 | { int8_t src = m68k_read_memory_8(srca); | |
4649 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
4650 | m68k_areg (regs, dstreg) = dsta; | |
4651 | CLEAR_CZNV; | |
4652 | SET_ZFLG (((int8_t)(src)) == 0); | |
4653 | SET_NFLG (((int8_t)(src)) < 0); | |
4654 | m68k_write_memory_8(dsta,src); | |
4655 | }}}}m68k_incpc(6); | |
4656 | return 20; | |
4657 | } | |
4658 | unsigned long CPUFUNC(op_113a_4)(uint32_t opcode) /* MOVE */ | |
4659 | { | |
4660 | uint32_t dstreg = (opcode >> 9) & 7; | |
4661 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
4662 | {{ uint32_t srca = m68k_getpc () + 2; | |
4663 | srca += (int32_t)(int16_t)get_iword(2); | |
4664 | { int8_t src = m68k_read_memory_8(srca); | |
4665 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
4666 | m68k_areg (regs, dstreg) = dsta; | |
4667 | CLEAR_CZNV; | |
4668 | SET_ZFLG (((int8_t)(src)) == 0); | |
4669 | SET_NFLG (((int8_t)(src)) < 0); | |
4670 | m68k_write_memory_8(dsta,src); | |
4671 | }}}}m68k_incpc(4); | |
4672 | return 16; | |
4673 | } | |
4674 | unsigned long CPUFUNC(op_113b_4)(uint32_t opcode) /* MOVE */ | |
4675 | { | |
4676 | uint32_t dstreg = (opcode >> 9) & 7; | |
4677 | OpcodeFamily = 30; CurrentInstrCycles = 18; | |
4678 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
4679 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
4680 | BusCyclePenalty += 2; | |
4681 | { int8_t src = m68k_read_memory_8(srca); | |
4682 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
4683 | m68k_areg (regs, dstreg) = dsta; | |
4684 | CLEAR_CZNV; | |
4685 | SET_ZFLG (((int8_t)(src)) == 0); | |
4686 | SET_NFLG (((int8_t)(src)) < 0); | |
4687 | m68k_write_memory_8(dsta,src); | |
4688 | }}}}m68k_incpc(4); | |
4689 | return 18; | |
4690 | } | |
4691 | unsigned long CPUFUNC(op_113c_4)(uint32_t opcode) /* MOVE */ | |
4692 | { | |
4693 | uint32_t dstreg = (opcode >> 9) & 7; | |
4694 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
4695 | {{ int8_t src = get_ibyte(2); | |
4696 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
4697 | m68k_areg (regs, dstreg) = dsta; | |
4698 | CLEAR_CZNV; | |
4699 | SET_ZFLG (((int8_t)(src)) == 0); | |
4700 | SET_NFLG (((int8_t)(src)) < 0); | |
4701 | m68k_write_memory_8(dsta,src); | |
4702 | }}}m68k_incpc(4); | |
4703 | return 12; | |
4704 | } | |
4705 | unsigned long CPUFUNC(op_1140_4)(uint32_t opcode) /* MOVE */ | |
4706 | { | |
4707 | uint32_t srcreg = (opcode & 7); | |
4708 | uint32_t dstreg = (opcode >> 9) & 7; | |
4709 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
4710 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
4711 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); | |
4712 | CLEAR_CZNV; | |
4713 | SET_ZFLG (((int8_t)(src)) == 0); | |
4714 | SET_NFLG (((int8_t)(src)) < 0); | |
4715 | m68k_write_memory_8(dsta,src); | |
4716 | }}}m68k_incpc(4); | |
4717 | return 12; | |
4718 | } | |
4719 | unsigned long CPUFUNC(op_1148_4)(uint32_t opcode) /* MOVE */ | |
4720 | { | |
4721 | uint32_t srcreg = (opcode & 7); | |
4722 | uint32_t dstreg = (opcode >> 9) & 7; | |
4723 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
4724 | {{ int8_t src = m68k_areg(regs, srcreg); | |
4725 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); | |
4726 | CLEAR_CZNV; | |
4727 | SET_ZFLG (((int8_t)(src)) == 0); | |
4728 | SET_NFLG (((int8_t)(src)) < 0); | |
4729 | m68k_write_memory_8(dsta,src); | |
4730 | }}}m68k_incpc(4); | |
4731 | return 12; | |
4732 | } | |
4733 | unsigned long CPUFUNC(op_1150_4)(uint32_t opcode) /* MOVE */ | |
4734 | { | |
4735 | uint32_t srcreg = (opcode & 7); | |
4736 | uint32_t dstreg = (opcode >> 9) & 7; | |
4737 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
4738 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
4739 | { int8_t src = m68k_read_memory_8(srca); | |
4740 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); | |
4741 | CLEAR_CZNV; | |
4742 | SET_ZFLG (((int8_t)(src)) == 0); | |
4743 | SET_NFLG (((int8_t)(src)) < 0); | |
4744 | m68k_write_memory_8(dsta,src); | |
4745 | }}}}m68k_incpc(4); | |
4746 | return 16; | |
4747 | } | |
4748 | unsigned long CPUFUNC(op_1158_4)(uint32_t opcode) /* MOVE */ | |
4749 | { | |
4750 | uint32_t srcreg = (opcode & 7); | |
4751 | uint32_t dstreg = (opcode >> 9) & 7; | |
4752 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
4753 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
4754 | { int8_t src = m68k_read_memory_8(srca); | |
4755 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
4756 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); | |
4757 | CLEAR_CZNV; | |
4758 | SET_ZFLG (((int8_t)(src)) == 0); | |
4759 | SET_NFLG (((int8_t)(src)) < 0); | |
4760 | m68k_write_memory_8(dsta,src); | |
4761 | }}}}m68k_incpc(4); | |
4762 | return 16; | |
4763 | } | |
4764 | unsigned long CPUFUNC(op_1160_4)(uint32_t opcode) /* MOVE */ | |
4765 | { | |
4766 | uint32_t srcreg = (opcode & 7); | |
4767 | uint32_t dstreg = (opcode >> 9) & 7; | |
4768 | OpcodeFamily = 30; CurrentInstrCycles = 18; | |
4769 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
4770 | { int8_t src = m68k_read_memory_8(srca); | |
4771 | m68k_areg (regs, srcreg) = srca; | |
4772 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); | |
4773 | CLEAR_CZNV; | |
4774 | SET_ZFLG (((int8_t)(src)) == 0); | |
4775 | SET_NFLG (((int8_t)(src)) < 0); | |
4776 | m68k_write_memory_8(dsta,src); | |
4777 | }}}}m68k_incpc(4); | |
4778 | return 18; | |
4779 | } | |
4780 | unsigned long CPUFUNC(op_1168_4)(uint32_t opcode) /* MOVE */ | |
4781 | { | |
4782 | uint32_t srcreg = (opcode & 7); | |
4783 | uint32_t dstreg = (opcode >> 9) & 7; | |
4784 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
4785 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
4786 | { int8_t src = m68k_read_memory_8(srca); | |
4787 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); | |
4788 | CLEAR_CZNV; | |
4789 | SET_ZFLG (((int8_t)(src)) == 0); | |
4790 | SET_NFLG (((int8_t)(src)) < 0); | |
4791 | m68k_write_memory_8(dsta,src); | |
4792 | }}}}m68k_incpc(6); | |
4793 | return 20; | |
4794 | } | |
4795 | unsigned long CPUFUNC(op_1170_4)(uint32_t opcode) /* MOVE */ | |
4796 | { | |
4797 | uint32_t srcreg = (opcode & 7); | |
4798 | uint32_t dstreg = (opcode >> 9) & 7; | |
4799 | OpcodeFamily = 30; CurrentInstrCycles = 22; | |
4800 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
4801 | BusCyclePenalty += 2; | |
4802 | { int8_t src = m68k_read_memory_8(srca); | |
4803 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); | |
4804 | CLEAR_CZNV; | |
4805 | SET_ZFLG (((int8_t)(src)) == 0); | |
4806 | SET_NFLG (((int8_t)(src)) < 0); | |
4807 | m68k_write_memory_8(dsta,src); | |
4808 | }}}}m68k_incpc(6); | |
4809 | return 22; | |
4810 | } | |
4811 | unsigned long CPUFUNC(op_1178_4)(uint32_t opcode) /* MOVE */ | |
4812 | { | |
4813 | uint32_t dstreg = (opcode >> 9) & 7; | |
4814 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
4815 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
4816 | { int8_t src = m68k_read_memory_8(srca); | |
4817 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); | |
4818 | CLEAR_CZNV; | |
4819 | SET_ZFLG (((int8_t)(src)) == 0); | |
4820 | SET_NFLG (((int8_t)(src)) < 0); | |
4821 | m68k_write_memory_8(dsta,src); | |
4822 | }}}}m68k_incpc(6); | |
4823 | return 20; | |
4824 | } | |
4825 | unsigned long CPUFUNC(op_1179_4)(uint32_t opcode) /* MOVE */ | |
4826 | { | |
4827 | uint32_t dstreg = (opcode >> 9) & 7; | |
4828 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
4829 | {{ uint32_t srca = get_ilong(2); | |
4830 | { int8_t src = m68k_read_memory_8(srca); | |
4831 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(6); | |
4832 | CLEAR_CZNV; | |
4833 | SET_ZFLG (((int8_t)(src)) == 0); | |
4834 | SET_NFLG (((int8_t)(src)) < 0); | |
4835 | m68k_write_memory_8(dsta,src); | |
4836 | }}}}m68k_incpc(8); | |
4837 | return 24; | |
4838 | } | |
4839 | unsigned long CPUFUNC(op_117a_4)(uint32_t opcode) /* MOVE */ | |
4840 | { | |
4841 | uint32_t dstreg = (opcode >> 9) & 7; | |
4842 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
4843 | {{ uint32_t srca = m68k_getpc () + 2; | |
4844 | srca += (int32_t)(int16_t)get_iword(2); | |
4845 | { int8_t src = m68k_read_memory_8(srca); | |
4846 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); | |
4847 | CLEAR_CZNV; | |
4848 | SET_ZFLG (((int8_t)(src)) == 0); | |
4849 | SET_NFLG (((int8_t)(src)) < 0); | |
4850 | m68k_write_memory_8(dsta,src); | |
4851 | }}}}m68k_incpc(6); | |
4852 | return 20; | |
4853 | } | |
4854 | unsigned long CPUFUNC(op_117b_4)(uint32_t opcode) /* MOVE */ | |
4855 | { | |
4856 | uint32_t dstreg = (opcode >> 9) & 7; | |
4857 | OpcodeFamily = 30; CurrentInstrCycles = 22; | |
4858 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
4859 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
4860 | BusCyclePenalty += 2; | |
4861 | { int8_t src = m68k_read_memory_8(srca); | |
4862 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); | |
4863 | CLEAR_CZNV; | |
4864 | SET_ZFLG (((int8_t)(src)) == 0); | |
4865 | SET_NFLG (((int8_t)(src)) < 0); | |
4866 | m68k_write_memory_8(dsta,src); | |
4867 | }}}}m68k_incpc(6); | |
4868 | return 22; | |
4869 | } | |
4870 | unsigned long CPUFUNC(op_117c_4)(uint32_t opcode) /* MOVE */ | |
4871 | { | |
4872 | uint32_t dstreg = (opcode >> 9) & 7; | |
4873 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
4874 | {{ int8_t src = get_ibyte(2); | |
4875 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); | |
4876 | CLEAR_CZNV; | |
4877 | SET_ZFLG (((int8_t)(src)) == 0); | |
4878 | SET_NFLG (((int8_t)(src)) < 0); | |
4879 | m68k_write_memory_8(dsta,src); | |
4880 | }}}m68k_incpc(6); | |
4881 | return 16; | |
4882 | } | |
4883 | unsigned long CPUFUNC(op_1180_4)(uint32_t opcode) /* MOVE */ | |
4884 | { | |
4885 | uint32_t srcreg = (opcode & 7); | |
4886 | uint32_t dstreg = (opcode >> 9) & 7; | |
4887 | OpcodeFamily = 30; CurrentInstrCycles = 14; | |
4888 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
4889 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); | |
4890 | BusCyclePenalty += 2; | |
4891 | CLEAR_CZNV; | |
4892 | SET_ZFLG (((int8_t)(src)) == 0); | |
4893 | SET_NFLG (((int8_t)(src)) < 0); | |
4894 | m68k_write_memory_8(dsta,src); | |
4895 | }}}m68k_incpc(4); | |
4896 | return 14; | |
4897 | } | |
4898 | unsigned long CPUFUNC(op_1188_4)(uint32_t opcode) /* MOVE */ | |
4899 | { | |
4900 | uint32_t srcreg = (opcode & 7); | |
4901 | uint32_t dstreg = (opcode >> 9) & 7; | |
4902 | OpcodeFamily = 30; CurrentInstrCycles = 14; | |
4903 | {{ int8_t src = m68k_areg(regs, srcreg); | |
4904 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); | |
4905 | BusCyclePenalty += 2; | |
4906 | CLEAR_CZNV; | |
4907 | SET_ZFLG (((int8_t)(src)) == 0); | |
4908 | SET_NFLG (((int8_t)(src)) < 0); | |
4909 | m68k_write_memory_8(dsta,src); | |
4910 | }}}m68k_incpc(4); | |
4911 | return 14; | |
4912 | } | |
4913 | unsigned long CPUFUNC(op_1190_4)(uint32_t opcode) /* MOVE */ | |
4914 | { | |
4915 | uint32_t srcreg = (opcode & 7); | |
4916 | uint32_t dstreg = (opcode >> 9) & 7; | |
4917 | OpcodeFamily = 30; CurrentInstrCycles = 18; | |
4918 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
4919 | { int8_t src = m68k_read_memory_8(srca); | |
4920 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); | |
4921 | BusCyclePenalty += 2; | |
4922 | CLEAR_CZNV; | |
4923 | SET_ZFLG (((int8_t)(src)) == 0); | |
4924 | SET_NFLG (((int8_t)(src)) < 0); | |
4925 | m68k_write_memory_8(dsta,src); | |
4926 | }}}}m68k_incpc(4); | |
4927 | return 18; | |
4928 | } | |
4929 | unsigned long CPUFUNC(op_1198_4)(uint32_t opcode) /* MOVE */ | |
4930 | { | |
4931 | uint32_t srcreg = (opcode & 7); | |
4932 | uint32_t dstreg = (opcode >> 9) & 7; | |
4933 | OpcodeFamily = 30; CurrentInstrCycles = 18; | |
4934 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
4935 | { int8_t src = m68k_read_memory_8(srca); | |
4936 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
4937 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); | |
4938 | BusCyclePenalty += 2; | |
4939 | CLEAR_CZNV; | |
4940 | SET_ZFLG (((int8_t)(src)) == 0); | |
4941 | SET_NFLG (((int8_t)(src)) < 0); | |
4942 | m68k_write_memory_8(dsta,src); | |
4943 | }}}}m68k_incpc(4); | |
4944 | return 18; | |
4945 | } | |
4946 | unsigned long CPUFUNC(op_11a0_4)(uint32_t opcode) /* MOVE */ | |
4947 | { | |
4948 | uint32_t srcreg = (opcode & 7); | |
4949 | uint32_t dstreg = (opcode >> 9) & 7; | |
4950 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
4951 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
4952 | { int8_t src = m68k_read_memory_8(srca); | |
4953 | m68k_areg (regs, srcreg) = srca; | |
4954 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); | |
4955 | BusCyclePenalty += 2; | |
4956 | CLEAR_CZNV; | |
4957 | SET_ZFLG (((int8_t)(src)) == 0); | |
4958 | SET_NFLG (((int8_t)(src)) < 0); | |
4959 | m68k_write_memory_8(dsta,src); | |
4960 | }}}}m68k_incpc(4); | |
4961 | return 20; | |
4962 | } | |
4963 | unsigned long CPUFUNC(op_11a8_4)(uint32_t opcode) /* MOVE */ | |
4964 | { | |
4965 | uint32_t srcreg = (opcode & 7); | |
4966 | uint32_t dstreg = (opcode >> 9) & 7; | |
4967 | OpcodeFamily = 30; CurrentInstrCycles = 22; | |
4968 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
4969 | { int8_t src = m68k_read_memory_8(srca); | |
4970 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); | |
4971 | BusCyclePenalty += 2; | |
4972 | CLEAR_CZNV; | |
4973 | SET_ZFLG (((int8_t)(src)) == 0); | |
4974 | SET_NFLG (((int8_t)(src)) < 0); | |
4975 | m68k_write_memory_8(dsta,src); | |
4976 | }}}}m68k_incpc(6); | |
4977 | return 22; | |
4978 | } | |
4979 | unsigned long CPUFUNC(op_11b0_4)(uint32_t opcode) /* MOVE */ | |
4980 | { | |
4981 | uint32_t srcreg = (opcode & 7); | |
4982 | uint32_t dstreg = (opcode >> 9) & 7; | |
4983 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
4984 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
4985 | BusCyclePenalty += 2; | |
4986 | { int8_t src = m68k_read_memory_8(srca); | |
4987 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); | |
4988 | BusCyclePenalty += 2; | |
4989 | CLEAR_CZNV; | |
4990 | SET_ZFLG (((int8_t)(src)) == 0); | |
4991 | SET_NFLG (((int8_t)(src)) < 0); | |
4992 | m68k_write_memory_8(dsta,src); | |
4993 | }}}}m68k_incpc(6); | |
4994 | return 24; | |
4995 | } | |
4996 | unsigned long CPUFUNC(op_11b8_4)(uint32_t opcode) /* MOVE */ | |
4997 | { | |
4998 | uint32_t dstreg = (opcode >> 9) & 7; | |
4999 | OpcodeFamily = 30; CurrentInstrCycles = 22; | |
5000 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
5001 | { int8_t src = m68k_read_memory_8(srca); | |
5002 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); | |
5003 | BusCyclePenalty += 2; | |
5004 | CLEAR_CZNV; | |
5005 | SET_ZFLG (((int8_t)(src)) == 0); | |
5006 | SET_NFLG (((int8_t)(src)) < 0); | |
5007 | m68k_write_memory_8(dsta,src); | |
5008 | }}}}m68k_incpc(6); | |
5009 | return 22; | |
5010 | } | |
5011 | unsigned long CPUFUNC(op_11b9_4)(uint32_t opcode) /* MOVE */ | |
5012 | { | |
5013 | uint32_t dstreg = (opcode >> 9) & 7; | |
5014 | OpcodeFamily = 30; CurrentInstrCycles = 26; | |
5015 | {{ uint32_t srca = get_ilong(2); | |
5016 | { int8_t src = m68k_read_memory_8(srca); | |
5017 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(6)); | |
5018 | BusCyclePenalty += 2; | |
5019 | CLEAR_CZNV; | |
5020 | SET_ZFLG (((int8_t)(src)) == 0); | |
5021 | SET_NFLG (((int8_t)(src)) < 0); | |
5022 | m68k_write_memory_8(dsta,src); | |
5023 | }}}}m68k_incpc(8); | |
5024 | return 26; | |
5025 | } | |
5026 | unsigned long CPUFUNC(op_11ba_4)(uint32_t opcode) /* MOVE */ | |
5027 | { | |
5028 | uint32_t dstreg = (opcode >> 9) & 7; | |
5029 | OpcodeFamily = 30; CurrentInstrCycles = 22; | |
5030 | {{ uint32_t srca = m68k_getpc () + 2; | |
5031 | srca += (int32_t)(int16_t)get_iword(2); | |
5032 | { int8_t src = m68k_read_memory_8(srca); | |
5033 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); | |
5034 | BusCyclePenalty += 2; | |
5035 | CLEAR_CZNV; | |
5036 | SET_ZFLG (((int8_t)(src)) == 0); | |
5037 | SET_NFLG (((int8_t)(src)) < 0); | |
5038 | m68k_write_memory_8(dsta,src); | |
5039 | }}}}m68k_incpc(6); | |
5040 | return 22; | |
5041 | } | |
5042 | unsigned long CPUFUNC(op_11bb_4)(uint32_t opcode) /* MOVE */ | |
5043 | { | |
5044 | uint32_t dstreg = (opcode >> 9) & 7; | |
5045 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
5046 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
5047 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
5048 | BusCyclePenalty += 2; | |
5049 | { int8_t src = m68k_read_memory_8(srca); | |
5050 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); | |
5051 | BusCyclePenalty += 2; | |
5052 | CLEAR_CZNV; | |
5053 | SET_ZFLG (((int8_t)(src)) == 0); | |
5054 | SET_NFLG (((int8_t)(src)) < 0); | |
5055 | m68k_write_memory_8(dsta,src); | |
5056 | }}}}m68k_incpc(6); | |
5057 | return 24; | |
5058 | } | |
5059 | unsigned long CPUFUNC(op_11bc_4)(uint32_t opcode) /* MOVE */ | |
5060 | { | |
5061 | uint32_t dstreg = (opcode >> 9) & 7; | |
5062 | OpcodeFamily = 30; CurrentInstrCycles = 18; | |
5063 | {{ int8_t src = get_ibyte(2); | |
5064 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); | |
5065 | BusCyclePenalty += 2; | |
5066 | CLEAR_CZNV; | |
5067 | SET_ZFLG (((int8_t)(src)) == 0); | |
5068 | SET_NFLG (((int8_t)(src)) < 0); | |
5069 | m68k_write_memory_8(dsta,src); | |
5070 | }}}m68k_incpc(6); | |
5071 | return 18; | |
5072 | } | |
5073 | unsigned long CPUFUNC(op_11c0_4)(uint32_t opcode) /* MOVE */ | |
5074 | { | |
5075 | uint32_t srcreg = (opcode & 7); | |
5076 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
5077 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
5078 | { uint32_t dsta = (int32_t)(int16_t)get_iword(2); | |
5079 | CLEAR_CZNV; | |
5080 | SET_ZFLG (((int8_t)(src)) == 0); | |
5081 | SET_NFLG (((int8_t)(src)) < 0); | |
5082 | m68k_write_memory_8(dsta,src); | |
5083 | }}}m68k_incpc(4); | |
5084 | return 12; | |
5085 | } | |
5086 | unsigned long CPUFUNC(op_11c8_4)(uint32_t opcode) /* MOVE */ | |
5087 | { | |
5088 | uint32_t srcreg = (opcode & 7); | |
5089 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
5090 | {{ int8_t src = m68k_areg(regs, srcreg); | |
5091 | { uint32_t dsta = (int32_t)(int16_t)get_iword(2); | |
5092 | CLEAR_CZNV; | |
5093 | SET_ZFLG (((int8_t)(src)) == 0); | |
5094 | SET_NFLG (((int8_t)(src)) < 0); | |
5095 | m68k_write_memory_8(dsta,src); | |
5096 | }}}m68k_incpc(4); | |
5097 | return 12; | |
5098 | } | |
5099 | unsigned long CPUFUNC(op_11d0_4)(uint32_t opcode) /* MOVE */ | |
5100 | { | |
5101 | uint32_t srcreg = (opcode & 7); | |
5102 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
5103 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
5104 | { int8_t src = m68k_read_memory_8(srca); | |
5105 | { uint32_t dsta = (int32_t)(int16_t)get_iword(2); | |
5106 | CLEAR_CZNV; | |
5107 | SET_ZFLG (((int8_t)(src)) == 0); | |
5108 | SET_NFLG (((int8_t)(src)) < 0); | |
5109 | m68k_write_memory_8(dsta,src); | |
5110 | }}}}m68k_incpc(4); | |
5111 | return 16; | |
5112 | } | |
5113 | unsigned long CPUFUNC(op_11d8_4)(uint32_t opcode) /* MOVE */ | |
5114 | { | |
5115 | uint32_t srcreg = (opcode & 7); | |
5116 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
5117 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
5118 | { int8_t src = m68k_read_memory_8(srca); | |
5119 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
5120 | { uint32_t dsta = (int32_t)(int16_t)get_iword(2); | |
5121 | CLEAR_CZNV; | |
5122 | SET_ZFLG (((int8_t)(src)) == 0); | |
5123 | SET_NFLG (((int8_t)(src)) < 0); | |
5124 | m68k_write_memory_8(dsta,src); | |
5125 | }}}}m68k_incpc(4); | |
5126 | return 16; | |
5127 | } | |
5128 | unsigned long CPUFUNC(op_11e0_4)(uint32_t opcode) /* MOVE */ | |
5129 | { | |
5130 | uint32_t srcreg = (opcode & 7); | |
5131 | OpcodeFamily = 30; CurrentInstrCycles = 18; | |
5132 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
5133 | { int8_t src = m68k_read_memory_8(srca); | |
5134 | m68k_areg (regs, srcreg) = srca; | |
5135 | { uint32_t dsta = (int32_t)(int16_t)get_iword(2); | |
5136 | CLEAR_CZNV; | |
5137 | SET_ZFLG (((int8_t)(src)) == 0); | |
5138 | SET_NFLG (((int8_t)(src)) < 0); | |
5139 | m68k_write_memory_8(dsta,src); | |
5140 | }}}}m68k_incpc(4); | |
5141 | return 18; | |
5142 | } | |
5143 | unsigned long CPUFUNC(op_11e8_4)(uint32_t opcode) /* MOVE */ | |
5144 | { | |
5145 | uint32_t srcreg = (opcode & 7); | |
5146 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
5147 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
5148 | { int8_t src = m68k_read_memory_8(srca); | |
5149 | { uint32_t dsta = (int32_t)(int16_t)get_iword(4); | |
5150 | CLEAR_CZNV; | |
5151 | SET_ZFLG (((int8_t)(src)) == 0); | |
5152 | SET_NFLG (((int8_t)(src)) < 0); | |
5153 | m68k_write_memory_8(dsta,src); | |
5154 | }}}}m68k_incpc(6); | |
5155 | return 20; | |
5156 | } | |
5157 | unsigned long CPUFUNC(op_11f0_4)(uint32_t opcode) /* MOVE */ | |
5158 | { | |
5159 | uint32_t srcreg = (opcode & 7); | |
5160 | OpcodeFamily = 30; CurrentInstrCycles = 22; | |
5161 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
5162 | BusCyclePenalty += 2; | |
5163 | { int8_t src = m68k_read_memory_8(srca); | |
5164 | { uint32_t dsta = (int32_t)(int16_t)get_iword(4); | |
5165 | CLEAR_CZNV; | |
5166 | SET_ZFLG (((int8_t)(src)) == 0); | |
5167 | SET_NFLG (((int8_t)(src)) < 0); | |
5168 | m68k_write_memory_8(dsta,src); | |
5169 | }}}}m68k_incpc(6); | |
5170 | return 22; | |
5171 | } | |
5172 | unsigned long CPUFUNC(op_11f8_4)(uint32_t opcode) /* MOVE */ | |
5173 | { | |
5174 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
5175 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
5176 | { int8_t src = m68k_read_memory_8(srca); | |
5177 | { uint32_t dsta = (int32_t)(int16_t)get_iword(4); | |
5178 | CLEAR_CZNV; | |
5179 | SET_ZFLG (((int8_t)(src)) == 0); | |
5180 | SET_NFLG (((int8_t)(src)) < 0); | |
5181 | m68k_write_memory_8(dsta,src); | |
5182 | }}}}m68k_incpc(6); | |
5183 | return 20; | |
5184 | } | |
5185 | unsigned long CPUFUNC(op_11f9_4)(uint32_t opcode) /* MOVE */ | |
5186 | { | |
5187 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
5188 | {{ uint32_t srca = get_ilong(2); | |
5189 | { int8_t src = m68k_read_memory_8(srca); | |
5190 | { uint32_t dsta = (int32_t)(int16_t)get_iword(6); | |
5191 | CLEAR_CZNV; | |
5192 | SET_ZFLG (((int8_t)(src)) == 0); | |
5193 | SET_NFLG (((int8_t)(src)) < 0); | |
5194 | m68k_write_memory_8(dsta,src); | |
5195 | }}}}m68k_incpc(8); | |
5196 | return 24; | |
5197 | } | |
5198 | unsigned long CPUFUNC(op_11fa_4)(uint32_t opcode) /* MOVE */ | |
5199 | { | |
5200 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
5201 | {{ uint32_t srca = m68k_getpc () + 2; | |
5202 | srca += (int32_t)(int16_t)get_iword(2); | |
5203 | { int8_t src = m68k_read_memory_8(srca); | |
5204 | { uint32_t dsta = (int32_t)(int16_t)get_iword(4); | |
5205 | CLEAR_CZNV; | |
5206 | SET_ZFLG (((int8_t)(src)) == 0); | |
5207 | SET_NFLG (((int8_t)(src)) < 0); | |
5208 | m68k_write_memory_8(dsta,src); | |
5209 | }}}}m68k_incpc(6); | |
5210 | return 20; | |
5211 | } | |
5212 | unsigned long CPUFUNC(op_11fb_4)(uint32_t opcode) /* MOVE */ | |
5213 | { | |
5214 | OpcodeFamily = 30; CurrentInstrCycles = 22; | |
5215 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
5216 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
5217 | BusCyclePenalty += 2; | |
5218 | { int8_t src = m68k_read_memory_8(srca); | |
5219 | { uint32_t dsta = (int32_t)(int16_t)get_iword(4); | |
5220 | CLEAR_CZNV; | |
5221 | SET_ZFLG (((int8_t)(src)) == 0); | |
5222 | SET_NFLG (((int8_t)(src)) < 0); | |
5223 | m68k_write_memory_8(dsta,src); | |
5224 | }}}}m68k_incpc(6); | |
5225 | return 22; | |
5226 | } | |
5227 | unsigned long CPUFUNC(op_11fc_4)(uint32_t opcode) /* MOVE */ | |
5228 | { | |
5229 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
5230 | {{ int8_t src = get_ibyte(2); | |
5231 | { uint32_t dsta = (int32_t)(int16_t)get_iword(4); | |
5232 | CLEAR_CZNV; | |
5233 | SET_ZFLG (((int8_t)(src)) == 0); | |
5234 | SET_NFLG (((int8_t)(src)) < 0); | |
5235 | m68k_write_memory_8(dsta,src); | |
5236 | }}}m68k_incpc(6); | |
5237 | return 16; | |
5238 | } | |
5239 | unsigned long CPUFUNC(op_13c0_4)(uint32_t opcode) /* MOVE */ | |
5240 | { | |
5241 | uint32_t srcreg = (opcode & 7); | |
5242 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
5243 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
5244 | { uint32_t dsta = get_ilong(2); | |
5245 | CLEAR_CZNV; | |
5246 | SET_ZFLG (((int8_t)(src)) == 0); | |
5247 | SET_NFLG (((int8_t)(src)) < 0); | |
5248 | m68k_write_memory_8(dsta,src); | |
5249 | }}}m68k_incpc(6); | |
5250 | return 16; | |
5251 | } | |
5252 | unsigned long CPUFUNC(op_13c8_4)(uint32_t opcode) /* MOVE */ | |
5253 | { | |
5254 | uint32_t srcreg = (opcode & 7); | |
5255 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
5256 | {{ int8_t src = m68k_areg(regs, srcreg); | |
5257 | { uint32_t dsta = get_ilong(2); | |
5258 | CLEAR_CZNV; | |
5259 | SET_ZFLG (((int8_t)(src)) == 0); | |
5260 | SET_NFLG (((int8_t)(src)) < 0); | |
5261 | m68k_write_memory_8(dsta,src); | |
5262 | }}}m68k_incpc(6); | |
5263 | return 16; | |
5264 | } | |
5265 | unsigned long CPUFUNC(op_13d0_4)(uint32_t opcode) /* MOVE */ | |
5266 | { | |
5267 | uint32_t srcreg = (opcode & 7); | |
5268 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
5269 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
5270 | { int8_t src = m68k_read_memory_8(srca); | |
5271 | { uint32_t dsta = get_ilong(2); | |
5272 | CLEAR_CZNV; | |
5273 | SET_ZFLG (((int8_t)(src)) == 0); | |
5274 | SET_NFLG (((int8_t)(src)) < 0); | |
5275 | m68k_write_memory_8(dsta,src); | |
5276 | }}}}m68k_incpc(6); | |
5277 | return 20; | |
5278 | } | |
5279 | unsigned long CPUFUNC(op_13d8_4)(uint32_t opcode) /* MOVE */ | |
5280 | { | |
5281 | uint32_t srcreg = (opcode & 7); | |
5282 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
5283 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
5284 | { int8_t src = m68k_read_memory_8(srca); | |
5285 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
5286 | { uint32_t dsta = get_ilong(2); | |
5287 | CLEAR_CZNV; | |
5288 | SET_ZFLG (((int8_t)(src)) == 0); | |
5289 | SET_NFLG (((int8_t)(src)) < 0); | |
5290 | m68k_write_memory_8(dsta,src); | |
5291 | }}}}m68k_incpc(6); | |
5292 | return 20; | |
5293 | } | |
5294 | unsigned long CPUFUNC(op_13e0_4)(uint32_t opcode) /* MOVE */ | |
5295 | { | |
5296 | uint32_t srcreg = (opcode & 7); | |
5297 | OpcodeFamily = 30; CurrentInstrCycles = 22; | |
5298 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
5299 | { int8_t src = m68k_read_memory_8(srca); | |
5300 | m68k_areg (regs, srcreg) = srca; | |
5301 | { uint32_t dsta = get_ilong(2); | |
5302 | CLEAR_CZNV; | |
5303 | SET_ZFLG (((int8_t)(src)) == 0); | |
5304 | SET_NFLG (((int8_t)(src)) < 0); | |
5305 | m68k_write_memory_8(dsta,src); | |
5306 | }}}}m68k_incpc(6); | |
5307 | return 22; | |
5308 | } | |
5309 | unsigned long CPUFUNC(op_13e8_4)(uint32_t opcode) /* MOVE */ | |
5310 | { | |
5311 | uint32_t srcreg = (opcode & 7); | |
5312 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
5313 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
5314 | { int8_t src = m68k_read_memory_8(srca); | |
5315 | { uint32_t dsta = get_ilong(4); | |
5316 | CLEAR_CZNV; | |
5317 | SET_ZFLG (((int8_t)(src)) == 0); | |
5318 | SET_NFLG (((int8_t)(src)) < 0); | |
5319 | m68k_write_memory_8(dsta,src); | |
5320 | }}}}m68k_incpc(8); | |
5321 | return 24; | |
5322 | } | |
5323 | unsigned long CPUFUNC(op_13f0_4)(uint32_t opcode) /* MOVE */ | |
5324 | { | |
5325 | uint32_t srcreg = (opcode & 7); | |
5326 | OpcodeFamily = 30; CurrentInstrCycles = 26; | |
5327 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
5328 | BusCyclePenalty += 2; | |
5329 | { int8_t src = m68k_read_memory_8(srca); | |
5330 | { uint32_t dsta = get_ilong(4); | |
5331 | CLEAR_CZNV; | |
5332 | SET_ZFLG (((int8_t)(src)) == 0); | |
5333 | SET_NFLG (((int8_t)(src)) < 0); | |
5334 | m68k_write_memory_8(dsta,src); | |
5335 | }}}}m68k_incpc(8); | |
5336 | return 26; | |
5337 | } | |
5338 | unsigned long CPUFUNC(op_13f8_4)(uint32_t opcode) /* MOVE */ | |
5339 | { | |
5340 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
5341 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
5342 | { int8_t src = m68k_read_memory_8(srca); | |
5343 | { uint32_t dsta = get_ilong(4); | |
5344 | CLEAR_CZNV; | |
5345 | SET_ZFLG (((int8_t)(src)) == 0); | |
5346 | SET_NFLG (((int8_t)(src)) < 0); | |
5347 | m68k_write_memory_8(dsta,src); | |
5348 | }}}}m68k_incpc(8); | |
5349 | return 24; | |
5350 | } | |
5351 | unsigned long CPUFUNC(op_13f9_4)(uint32_t opcode) /* MOVE */ | |
5352 | { | |
5353 | OpcodeFamily = 30; CurrentInstrCycles = 28; | |
5354 | {{ uint32_t srca = get_ilong(2); | |
5355 | { int8_t src = m68k_read_memory_8(srca); | |
5356 | { uint32_t dsta = get_ilong(6); | |
5357 | CLEAR_CZNV; | |
5358 | SET_ZFLG (((int8_t)(src)) == 0); | |
5359 | SET_NFLG (((int8_t)(src)) < 0); | |
5360 | m68k_write_memory_8(dsta,src); | |
5361 | }}}}m68k_incpc(10); | |
5362 | return 28; | |
5363 | } | |
5364 | unsigned long CPUFUNC(op_13fa_4)(uint32_t opcode) /* MOVE */ | |
5365 | { | |
5366 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
5367 | {{ uint32_t srca = m68k_getpc () + 2; | |
5368 | srca += (int32_t)(int16_t)get_iword(2); | |
5369 | { int8_t src = m68k_read_memory_8(srca); | |
5370 | { uint32_t dsta = get_ilong(4); | |
5371 | CLEAR_CZNV; | |
5372 | SET_ZFLG (((int8_t)(src)) == 0); | |
5373 | SET_NFLG (((int8_t)(src)) < 0); | |
5374 | m68k_write_memory_8(dsta,src); | |
5375 | }}}}m68k_incpc(8); | |
5376 | return 24; | |
5377 | } | |
5378 | unsigned long CPUFUNC(op_13fb_4)(uint32_t opcode) /* MOVE */ | |
5379 | { | |
5380 | OpcodeFamily = 30; CurrentInstrCycles = 26; | |
5381 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
5382 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
5383 | BusCyclePenalty += 2; | |
5384 | { int8_t src = m68k_read_memory_8(srca); | |
5385 | { uint32_t dsta = get_ilong(4); | |
5386 | CLEAR_CZNV; | |
5387 | SET_ZFLG (((int8_t)(src)) == 0); | |
5388 | SET_NFLG (((int8_t)(src)) < 0); | |
5389 | m68k_write_memory_8(dsta,src); | |
5390 | }}}}m68k_incpc(8); | |
5391 | return 26; | |
5392 | } | |
5393 | unsigned long CPUFUNC(op_13fc_4)(uint32_t opcode) /* MOVE */ | |
5394 | { | |
5395 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
5396 | {{ int8_t src = get_ibyte(2); | |
5397 | { uint32_t dsta = get_ilong(4); | |
5398 | CLEAR_CZNV; | |
5399 | SET_ZFLG (((int8_t)(src)) == 0); | |
5400 | SET_NFLG (((int8_t)(src)) < 0); | |
5401 | m68k_write_memory_8(dsta,src); | |
5402 | }}}m68k_incpc(8); | |
5403 | return 20; | |
5404 | } | |
5405 | unsigned long CPUFUNC(op_2000_4)(uint32_t opcode) /* MOVE */ | |
5406 | { | |
5407 | uint32_t srcreg = (opcode & 7); | |
5408 | uint32_t dstreg = (opcode >> 9) & 7; | |
5409 | OpcodeFamily = 30; CurrentInstrCycles = 4; | |
5410 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
5411 | { CLEAR_CZNV; | |
5412 | SET_ZFLG (((int32_t)(src)) == 0); | |
5413 | SET_NFLG (((int32_t)(src)) < 0); | |
5414 | m68k_dreg(regs, dstreg) = (src); | |
5415 | }}}m68k_incpc(2); | |
5416 | return 4; | |
5417 | } | |
5418 | unsigned long CPUFUNC(op_2008_4)(uint32_t opcode) /* MOVE */ | |
5419 | { | |
5420 | uint32_t srcreg = (opcode & 7); | |
5421 | uint32_t dstreg = (opcode >> 9) & 7; | |
5422 | OpcodeFamily = 30; CurrentInstrCycles = 4; | |
5423 | {{ int32_t src = m68k_areg(regs, srcreg); | |
5424 | { CLEAR_CZNV; | |
5425 | SET_ZFLG (((int32_t)(src)) == 0); | |
5426 | SET_NFLG (((int32_t)(src)) < 0); | |
5427 | m68k_dreg(regs, dstreg) = (src); | |
5428 | }}}m68k_incpc(2); | |
5429 | return 4; | |
5430 | } | |
5431 | unsigned long CPUFUNC(op_2010_4)(uint32_t opcode) /* MOVE */ | |
5432 | { | |
5433 | uint32_t srcreg = (opcode & 7); | |
5434 | uint32_t dstreg = (opcode >> 9) & 7; | |
5435 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
5436 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
5437 | { int32_t src = m68k_read_memory_32(srca); | |
5438 | { CLEAR_CZNV; | |
5439 | SET_ZFLG (((int32_t)(src)) == 0); | |
5440 | SET_NFLG (((int32_t)(src)) < 0); | |
5441 | m68k_dreg(regs, dstreg) = (src); | |
5442 | }}}}m68k_incpc(2); | |
5443 | return 12; | |
5444 | } | |
5445 | unsigned long CPUFUNC(op_2018_4)(uint32_t opcode) /* MOVE */ | |
5446 | { | |
5447 | uint32_t srcreg = (opcode & 7); | |
5448 | uint32_t dstreg = (opcode >> 9) & 7; | |
5449 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
5450 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
5451 | { int32_t src = m68k_read_memory_32(srca); | |
5452 | m68k_areg(regs, srcreg) += 4; | |
5453 | { CLEAR_CZNV; | |
5454 | SET_ZFLG (((int32_t)(src)) == 0); | |
5455 | SET_NFLG (((int32_t)(src)) < 0); | |
5456 | m68k_dreg(regs, dstreg) = (src); | |
5457 | }}}}m68k_incpc(2); | |
5458 | return 12; | |
5459 | } | |
5460 | unsigned long CPUFUNC(op_2020_4)(uint32_t opcode) /* MOVE */ | |
5461 | { | |
5462 | uint32_t srcreg = (opcode & 7); | |
5463 | uint32_t dstreg = (opcode >> 9) & 7; | |
5464 | OpcodeFamily = 30; CurrentInstrCycles = 14; | |
5465 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 4; | |
5466 | { int32_t src = m68k_read_memory_32(srca); | |
5467 | m68k_areg (regs, srcreg) = srca; | |
5468 | { CLEAR_CZNV; | |
5469 | SET_ZFLG (((int32_t)(src)) == 0); | |
5470 | SET_NFLG (((int32_t)(src)) < 0); | |
5471 | m68k_dreg(regs, dstreg) = (src); | |
5472 | }}}}m68k_incpc(2); | |
5473 | return 14; | |
5474 | } | |
5475 | unsigned long CPUFUNC(op_2028_4)(uint32_t opcode) /* MOVE */ | |
5476 | { | |
5477 | uint32_t srcreg = (opcode & 7); | |
5478 | uint32_t dstreg = (opcode >> 9) & 7; | |
5479 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
5480 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
5481 | { int32_t src = m68k_read_memory_32(srca); | |
5482 | { CLEAR_CZNV; | |
5483 | SET_ZFLG (((int32_t)(src)) == 0); | |
5484 | SET_NFLG (((int32_t)(src)) < 0); | |
5485 | m68k_dreg(regs, dstreg) = (src); | |
5486 | }}}}m68k_incpc(4); | |
5487 | return 16; | |
5488 | } | |
5489 | unsigned long CPUFUNC(op_2030_4)(uint32_t opcode) /* MOVE */ | |
5490 | { | |
5491 | uint32_t srcreg = (opcode & 7); | |
5492 | uint32_t dstreg = (opcode >> 9) & 7; | |
5493 | OpcodeFamily = 30; CurrentInstrCycles = 18; | |
5494 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
5495 | BusCyclePenalty += 2; | |
5496 | { int32_t src = m68k_read_memory_32(srca); | |
5497 | { CLEAR_CZNV; | |
5498 | SET_ZFLG (((int32_t)(src)) == 0); | |
5499 | SET_NFLG (((int32_t)(src)) < 0); | |
5500 | m68k_dreg(regs, dstreg) = (src); | |
5501 | }}}}m68k_incpc(4); | |
5502 | return 18; | |
5503 | } | |
5504 | unsigned long CPUFUNC(op_2038_4)(uint32_t opcode) /* MOVE */ | |
5505 | { | |
5506 | uint32_t dstreg = (opcode >> 9) & 7; | |
5507 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
5508 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
5509 | { int32_t src = m68k_read_memory_32(srca); | |
5510 | { CLEAR_CZNV; | |
5511 | SET_ZFLG (((int32_t)(src)) == 0); | |
5512 | SET_NFLG (((int32_t)(src)) < 0); | |
5513 | m68k_dreg(regs, dstreg) = (src); | |
5514 | }}}}m68k_incpc(4); | |
5515 | return 16; | |
5516 | } | |
5517 | unsigned long CPUFUNC(op_2039_4)(uint32_t opcode) /* MOVE */ | |
5518 | { | |
5519 | uint32_t dstreg = (opcode >> 9) & 7; | |
5520 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
5521 | {{ uint32_t srca = get_ilong(2); | |
5522 | { int32_t src = m68k_read_memory_32(srca); | |
5523 | { CLEAR_CZNV; | |
5524 | SET_ZFLG (((int32_t)(src)) == 0); | |
5525 | SET_NFLG (((int32_t)(src)) < 0); | |
5526 | m68k_dreg(regs, dstreg) = (src); | |
5527 | }}}}m68k_incpc(6); | |
5528 | return 20; | |
5529 | } | |
5530 | unsigned long CPUFUNC(op_203a_4)(uint32_t opcode) /* MOVE */ | |
5531 | { | |
5532 | uint32_t dstreg = (opcode >> 9) & 7; | |
5533 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
5534 | {{ uint32_t srca = m68k_getpc () + 2; | |
5535 | srca += (int32_t)(int16_t)get_iword(2); | |
5536 | { int32_t src = m68k_read_memory_32(srca); | |
5537 | { CLEAR_CZNV; | |
5538 | SET_ZFLG (((int32_t)(src)) == 0); | |
5539 | SET_NFLG (((int32_t)(src)) < 0); | |
5540 | m68k_dreg(regs, dstreg) = (src); | |
5541 | }}}}m68k_incpc(4); | |
5542 | return 16; | |
5543 | } | |
5544 | unsigned long CPUFUNC(op_203b_4)(uint32_t opcode) /* MOVE */ | |
5545 | { | |
5546 | uint32_t dstreg = (opcode >> 9) & 7; | |
5547 | OpcodeFamily = 30; CurrentInstrCycles = 18; | |
5548 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
5549 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
5550 | BusCyclePenalty += 2; | |
5551 | { int32_t src = m68k_read_memory_32(srca); | |
5552 | { CLEAR_CZNV; | |
5553 | SET_ZFLG (((int32_t)(src)) == 0); | |
5554 | SET_NFLG (((int32_t)(src)) < 0); | |
5555 | m68k_dreg(regs, dstreg) = (src); | |
5556 | }}}}m68k_incpc(4); | |
5557 | return 18; | |
5558 | } | |
5559 | unsigned long CPUFUNC(op_203c_4)(uint32_t opcode) /* MOVE */ | |
5560 | { | |
5561 | uint32_t dstreg = (opcode >> 9) & 7; | |
5562 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
5563 | {{ int32_t src = get_ilong(2); | |
5564 | { CLEAR_CZNV; | |
5565 | SET_ZFLG (((int32_t)(src)) == 0); | |
5566 | SET_NFLG (((int32_t)(src)) < 0); | |
5567 | m68k_dreg(regs, dstreg) = (src); | |
5568 | }}}m68k_incpc(6); | |
5569 | return 12; | |
5570 | } | |
5571 | unsigned long CPUFUNC(op_2040_4)(uint32_t opcode) /* MOVEA */ | |
5572 | { | |
5573 | uint32_t srcreg = (opcode & 7); | |
5574 | uint32_t dstreg = (opcode >> 9) & 7; | |
5575 | OpcodeFamily = 31; CurrentInstrCycles = 4; | |
5576 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
5577 | { uint32_t val = src; | |
5578 | m68k_areg(regs, dstreg) = (val); | |
5579 | }}}m68k_incpc(2); | |
5580 | return 4; | |
5581 | } | |
5582 | unsigned long CPUFUNC(op_2048_4)(uint32_t opcode) /* MOVEA */ | |
5583 | { | |
5584 | uint32_t srcreg = (opcode & 7); | |
5585 | uint32_t dstreg = (opcode >> 9) & 7; | |
5586 | OpcodeFamily = 31; CurrentInstrCycles = 4; | |
5587 | {{ int32_t src = m68k_areg(regs, srcreg); | |
5588 | { uint32_t val = src; | |
5589 | m68k_areg(regs, dstreg) = (val); | |
5590 | }}}m68k_incpc(2); | |
5591 | return 4; | |
5592 | } | |
5593 | unsigned long CPUFUNC(op_2050_4)(uint32_t opcode) /* MOVEA */ | |
5594 | { | |
5595 | uint32_t srcreg = (opcode & 7); | |
5596 | uint32_t dstreg = (opcode >> 9) & 7; | |
5597 | OpcodeFamily = 31; CurrentInstrCycles = 12; | |
5598 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
5599 | { int32_t src = m68k_read_memory_32(srca); | |
5600 | { uint32_t val = src; | |
5601 | m68k_areg(regs, dstreg) = (val); | |
5602 | }}}}m68k_incpc(2); | |
5603 | return 12; | |
5604 | } | |
5605 | unsigned long CPUFUNC(op_2058_4)(uint32_t opcode) /* MOVEA */ | |
5606 | { | |
5607 | uint32_t srcreg = (opcode & 7); | |
5608 | uint32_t dstreg = (opcode >> 9) & 7; | |
5609 | OpcodeFamily = 31; CurrentInstrCycles = 12; | |
5610 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
5611 | { int32_t src = m68k_read_memory_32(srca); | |
5612 | m68k_areg(regs, srcreg) += 4; | |
5613 | { uint32_t val = src; | |
5614 | m68k_areg(regs, dstreg) = (val); | |
5615 | }}}}m68k_incpc(2); | |
5616 | return 12; | |
5617 | } | |
5618 | unsigned long CPUFUNC(op_2060_4)(uint32_t opcode) /* MOVEA */ | |
5619 | { | |
5620 | uint32_t srcreg = (opcode & 7); | |
5621 | uint32_t dstreg = (opcode >> 9) & 7; | |
5622 | OpcodeFamily = 31; CurrentInstrCycles = 14; | |
5623 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 4; | |
5624 | { int32_t src = m68k_read_memory_32(srca); | |
5625 | m68k_areg (regs, srcreg) = srca; | |
5626 | { uint32_t val = src; | |
5627 | m68k_areg(regs, dstreg) = (val); | |
5628 | }}}}m68k_incpc(2); | |
5629 | return 14; | |
5630 | } | |
5631 | unsigned long CPUFUNC(op_2068_4)(uint32_t opcode) /* MOVEA */ | |
5632 | { | |
5633 | uint32_t srcreg = (opcode & 7); | |
5634 | uint32_t dstreg = (opcode >> 9) & 7; | |
5635 | OpcodeFamily = 31; CurrentInstrCycles = 16; | |
5636 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
5637 | { int32_t src = m68k_read_memory_32(srca); | |
5638 | { uint32_t val = src; | |
5639 | m68k_areg(regs, dstreg) = (val); | |
5640 | }}}}m68k_incpc(4); | |
5641 | return 16; | |
5642 | } | |
5643 | unsigned long CPUFUNC(op_2070_4)(uint32_t opcode) /* MOVEA */ | |
5644 | { | |
5645 | uint32_t srcreg = (opcode & 7); | |
5646 | uint32_t dstreg = (opcode >> 9) & 7; | |
5647 | OpcodeFamily = 31; CurrentInstrCycles = 18; | |
5648 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
5649 | BusCyclePenalty += 2; | |
5650 | { int32_t src = m68k_read_memory_32(srca); | |
5651 | { uint32_t val = src; | |
5652 | m68k_areg(regs, dstreg) = (val); | |
5653 | }}}}m68k_incpc(4); | |
5654 | return 18; | |
5655 | } | |
5656 | unsigned long CPUFUNC(op_2078_4)(uint32_t opcode) /* MOVEA */ | |
5657 | { | |
5658 | uint32_t dstreg = (opcode >> 9) & 7; | |
5659 | OpcodeFamily = 31; CurrentInstrCycles = 16; | |
5660 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
5661 | { int32_t src = m68k_read_memory_32(srca); | |
5662 | { uint32_t val = src; | |
5663 | m68k_areg(regs, dstreg) = (val); | |
5664 | }}}}m68k_incpc(4); | |
5665 | return 16; | |
5666 | } | |
5667 | unsigned long CPUFUNC(op_2079_4)(uint32_t opcode) /* MOVEA */ | |
5668 | { | |
5669 | uint32_t dstreg = (opcode >> 9) & 7; | |
5670 | OpcodeFamily = 31; CurrentInstrCycles = 20; | |
5671 | {{ uint32_t srca = get_ilong(2); | |
5672 | { int32_t src = m68k_read_memory_32(srca); | |
5673 | { uint32_t val = src; | |
5674 | m68k_areg(regs, dstreg) = (val); | |
5675 | }}}}m68k_incpc(6); | |
5676 | return 20; | |
5677 | } | |
5678 | unsigned long CPUFUNC(op_207a_4)(uint32_t opcode) /* MOVEA */ | |
5679 | { | |
5680 | uint32_t dstreg = (opcode >> 9) & 7; | |
5681 | OpcodeFamily = 31; CurrentInstrCycles = 16; | |
5682 | {{ uint32_t srca = m68k_getpc () + 2; | |
5683 | srca += (int32_t)(int16_t)get_iword(2); | |
5684 | { int32_t src = m68k_read_memory_32(srca); | |
5685 | { uint32_t val = src; | |
5686 | m68k_areg(regs, dstreg) = (val); | |
5687 | }}}}m68k_incpc(4); | |
5688 | return 16; | |
5689 | } | |
5690 | unsigned long CPUFUNC(op_207b_4)(uint32_t opcode) /* MOVEA */ | |
5691 | { | |
5692 | uint32_t dstreg = (opcode >> 9) & 7; | |
5693 | OpcodeFamily = 31; CurrentInstrCycles = 18; | |
5694 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
5695 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
5696 | BusCyclePenalty += 2; | |
5697 | { int32_t src = m68k_read_memory_32(srca); | |
5698 | { uint32_t val = src; | |
5699 | m68k_areg(regs, dstreg) = (val); | |
5700 | }}}}m68k_incpc(4); | |
5701 | return 18; | |
5702 | } | |
5703 | unsigned long CPUFUNC(op_207c_4)(uint32_t opcode) /* MOVEA */ | |
5704 | { | |
5705 | uint32_t dstreg = (opcode >> 9) & 7; | |
5706 | OpcodeFamily = 31; CurrentInstrCycles = 12; | |
5707 | {{ int32_t src = get_ilong(2); | |
5708 | { uint32_t val = src; | |
5709 | m68k_areg(regs, dstreg) = (val); | |
5710 | }}}m68k_incpc(6); | |
5711 | return 12; | |
5712 | } | |
5713 | unsigned long CPUFUNC(op_2080_4)(uint32_t opcode) /* MOVE */ | |
5714 | { | |
5715 | uint32_t srcreg = (opcode & 7); | |
5716 | uint32_t dstreg = (opcode >> 9) & 7; | |
5717 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
5718 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
5719 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
5720 | CLEAR_CZNV; | |
5721 | SET_ZFLG (((int32_t)(src)) == 0); | |
5722 | SET_NFLG (((int32_t)(src)) < 0); | |
5723 | m68k_write_memory_32(dsta,src); | |
5724 | }}}m68k_incpc(2); | |
5725 | return 12; | |
5726 | } | |
5727 | unsigned long CPUFUNC(op_2088_4)(uint32_t opcode) /* MOVE */ | |
5728 | { | |
5729 | uint32_t srcreg = (opcode & 7); | |
5730 | uint32_t dstreg = (opcode >> 9) & 7; | |
5731 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
5732 | {{ int32_t src = m68k_areg(regs, srcreg); | |
5733 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
5734 | CLEAR_CZNV; | |
5735 | SET_ZFLG (((int32_t)(src)) == 0); | |
5736 | SET_NFLG (((int32_t)(src)) < 0); | |
5737 | m68k_write_memory_32(dsta,src); | |
5738 | }}}m68k_incpc(2); | |
5739 | return 12; | |
5740 | } | |
5741 | unsigned long CPUFUNC(op_2090_4)(uint32_t opcode) /* MOVE */ | |
5742 | { | |
5743 | uint32_t srcreg = (opcode & 7); | |
5744 | uint32_t dstreg = (opcode >> 9) & 7; | |
5745 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
5746 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
5747 | { int32_t src = m68k_read_memory_32(srca); | |
5748 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
5749 | CLEAR_CZNV; | |
5750 | SET_ZFLG (((int32_t)(src)) == 0); | |
5751 | SET_NFLG (((int32_t)(src)) < 0); | |
5752 | m68k_write_memory_32(dsta,src); | |
5753 | }}}}m68k_incpc(2); | |
5754 | return 20; | |
5755 | } | |
5756 | unsigned long CPUFUNC(op_2098_4)(uint32_t opcode) /* MOVE */ | |
5757 | { | |
5758 | uint32_t srcreg = (opcode & 7); | |
5759 | uint32_t dstreg = (opcode >> 9) & 7; | |
5760 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
5761 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
5762 | { int32_t src = m68k_read_memory_32(srca); | |
5763 | m68k_areg(regs, srcreg) += 4; | |
5764 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
5765 | CLEAR_CZNV; | |
5766 | SET_ZFLG (((int32_t)(src)) == 0); | |
5767 | SET_NFLG (((int32_t)(src)) < 0); | |
5768 | m68k_write_memory_32(dsta,src); | |
5769 | }}}}m68k_incpc(2); | |
5770 | return 20; | |
5771 | } | |
5772 | unsigned long CPUFUNC(op_20a0_4)(uint32_t opcode) /* MOVE */ | |
5773 | { | |
5774 | uint32_t srcreg = (opcode & 7); | |
5775 | uint32_t dstreg = (opcode >> 9) & 7; | |
5776 | OpcodeFamily = 30; CurrentInstrCycles = 22; | |
5777 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 4; | |
5778 | { int32_t src = m68k_read_memory_32(srca); | |
5779 | m68k_areg (regs, srcreg) = srca; | |
5780 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
5781 | CLEAR_CZNV; | |
5782 | SET_ZFLG (((int32_t)(src)) == 0); | |
5783 | SET_NFLG (((int32_t)(src)) < 0); | |
5784 | m68k_write_memory_32(dsta,src); | |
5785 | }}}}m68k_incpc(2); | |
5786 | return 22; | |
5787 | } | |
5788 | unsigned long CPUFUNC(op_20a8_4)(uint32_t opcode) /* MOVE */ | |
5789 | { | |
5790 | uint32_t srcreg = (opcode & 7); | |
5791 | uint32_t dstreg = (opcode >> 9) & 7; | |
5792 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
5793 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
5794 | { int32_t src = m68k_read_memory_32(srca); | |
5795 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
5796 | CLEAR_CZNV; | |
5797 | SET_ZFLG (((int32_t)(src)) == 0); | |
5798 | SET_NFLG (((int32_t)(src)) < 0); | |
5799 | m68k_write_memory_32(dsta,src); | |
5800 | }}}}m68k_incpc(4); | |
5801 | return 24; | |
5802 | } | |
5803 | unsigned long CPUFUNC(op_20b0_4)(uint32_t opcode) /* MOVE */ | |
5804 | { | |
5805 | uint32_t srcreg = (opcode & 7); | |
5806 | uint32_t dstreg = (opcode >> 9) & 7; | |
5807 | OpcodeFamily = 30; CurrentInstrCycles = 26; | |
5808 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
5809 | BusCyclePenalty += 2; | |
5810 | { int32_t src = m68k_read_memory_32(srca); | |
5811 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
5812 | CLEAR_CZNV; | |
5813 | SET_ZFLG (((int32_t)(src)) == 0); | |
5814 | SET_NFLG (((int32_t)(src)) < 0); | |
5815 | m68k_write_memory_32(dsta,src); | |
5816 | }}}}m68k_incpc(4); | |
5817 | return 26; | |
5818 | } | |
5819 | unsigned long CPUFUNC(op_20b8_4)(uint32_t opcode) /* MOVE */ | |
5820 | { | |
5821 | uint32_t dstreg = (opcode >> 9) & 7; | |
5822 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
5823 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
5824 | { int32_t src = m68k_read_memory_32(srca); | |
5825 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
5826 | CLEAR_CZNV; | |
5827 | SET_ZFLG (((int32_t)(src)) == 0); | |
5828 | SET_NFLG (((int32_t)(src)) < 0); | |
5829 | m68k_write_memory_32(dsta,src); | |
5830 | }}}}m68k_incpc(4); | |
5831 | return 24; | |
5832 | } | |
5833 | unsigned long CPUFUNC(op_20b9_4)(uint32_t opcode) /* MOVE */ | |
5834 | { | |
5835 | uint32_t dstreg = (opcode >> 9) & 7; | |
5836 | OpcodeFamily = 30; CurrentInstrCycles = 28; | |
5837 | {{ uint32_t srca = get_ilong(2); | |
5838 | { int32_t src = m68k_read_memory_32(srca); | |
5839 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
5840 | CLEAR_CZNV; | |
5841 | SET_ZFLG (((int32_t)(src)) == 0); | |
5842 | SET_NFLG (((int32_t)(src)) < 0); | |
5843 | m68k_write_memory_32(dsta,src); | |
5844 | }}}}m68k_incpc(6); | |
5845 | return 28; | |
5846 | } | |
5847 | unsigned long CPUFUNC(op_20ba_4)(uint32_t opcode) /* MOVE */ | |
5848 | { | |
5849 | uint32_t dstreg = (opcode >> 9) & 7; | |
5850 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
5851 | {{ uint32_t srca = m68k_getpc () + 2; | |
5852 | srca += (int32_t)(int16_t)get_iword(2); | |
5853 | { int32_t src = m68k_read_memory_32(srca); | |
5854 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
5855 | CLEAR_CZNV; | |
5856 | SET_ZFLG (((int32_t)(src)) == 0); | |
5857 | SET_NFLG (((int32_t)(src)) < 0); | |
5858 | m68k_write_memory_32(dsta,src); | |
5859 | }}}}m68k_incpc(4); | |
5860 | return 24; | |
5861 | } | |
5862 | unsigned long CPUFUNC(op_20bb_4)(uint32_t opcode) /* MOVE */ | |
5863 | { | |
5864 | uint32_t dstreg = (opcode >> 9) & 7; | |
5865 | OpcodeFamily = 30; CurrentInstrCycles = 26; | |
5866 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
5867 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
5868 | BusCyclePenalty += 2; | |
5869 | { int32_t src = m68k_read_memory_32(srca); | |
5870 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
5871 | CLEAR_CZNV; | |
5872 | SET_ZFLG (((int32_t)(src)) == 0); | |
5873 | SET_NFLG (((int32_t)(src)) < 0); | |
5874 | m68k_write_memory_32(dsta,src); | |
5875 | }}}}m68k_incpc(4); | |
5876 | return 26; | |
5877 | } | |
5878 | unsigned long CPUFUNC(op_20bc_4)(uint32_t opcode) /* MOVE */ | |
5879 | { | |
5880 | uint32_t dstreg = (opcode >> 9) & 7; | |
5881 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
5882 | {{ int32_t src = get_ilong(2); | |
5883 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
5884 | CLEAR_CZNV; | |
5885 | SET_ZFLG (((int32_t)(src)) == 0); | |
5886 | SET_NFLG (((int32_t)(src)) < 0); | |
5887 | m68k_write_memory_32(dsta,src); | |
5888 | }}}m68k_incpc(6); | |
5889 | return 20; | |
5890 | } | |
5891 | unsigned long CPUFUNC(op_20c0_4)(uint32_t opcode) /* MOVE */ | |
5892 | { | |
5893 | uint32_t srcreg = (opcode & 7); | |
5894 | uint32_t dstreg = (opcode >> 9) & 7; | |
5895 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
5896 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
5897 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
5898 | m68k_areg(regs, dstreg) += 4; | |
5899 | CLEAR_CZNV; | |
5900 | SET_ZFLG (((int32_t)(src)) == 0); | |
5901 | SET_NFLG (((int32_t)(src)) < 0); | |
5902 | m68k_write_memory_32(dsta,src); | |
5903 | }}}m68k_incpc(2); | |
5904 | return 12; | |
5905 | } | |
5906 | unsigned long CPUFUNC(op_20c8_4)(uint32_t opcode) /* MOVE */ | |
5907 | { | |
5908 | uint32_t srcreg = (opcode & 7); | |
5909 | uint32_t dstreg = (opcode >> 9) & 7; | |
5910 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
5911 | {{ int32_t src = m68k_areg(regs, srcreg); | |
5912 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
5913 | m68k_areg(regs, dstreg) += 4; | |
5914 | CLEAR_CZNV; | |
5915 | SET_ZFLG (((int32_t)(src)) == 0); | |
5916 | SET_NFLG (((int32_t)(src)) < 0); | |
5917 | m68k_write_memory_32(dsta,src); | |
5918 | }}}m68k_incpc(2); | |
5919 | return 12; | |
5920 | } | |
5921 | unsigned long CPUFUNC(op_20d0_4)(uint32_t opcode) /* MOVE */ | |
5922 | { | |
5923 | uint32_t srcreg = (opcode & 7); | |
5924 | uint32_t dstreg = (opcode >> 9) & 7; | |
5925 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
5926 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
5927 | { int32_t src = m68k_read_memory_32(srca); | |
5928 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
5929 | m68k_areg(regs, dstreg) += 4; | |
5930 | CLEAR_CZNV; | |
5931 | SET_ZFLG (((int32_t)(src)) == 0); | |
5932 | SET_NFLG (((int32_t)(src)) < 0); | |
5933 | m68k_write_memory_32(dsta,src); | |
5934 | }}}}m68k_incpc(2); | |
5935 | return 20; | |
5936 | } | |
5937 | unsigned long CPUFUNC(op_20d8_4)(uint32_t opcode) /* MOVE */ | |
5938 | { | |
5939 | uint32_t srcreg = (opcode & 7); | |
5940 | uint32_t dstreg = (opcode >> 9) & 7; | |
5941 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
5942 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
5943 | { int32_t src = m68k_read_memory_32(srca); | |
5944 | m68k_areg(regs, srcreg) += 4; | |
5945 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
5946 | m68k_areg(regs, dstreg) += 4; | |
5947 | CLEAR_CZNV; | |
5948 | SET_ZFLG (((int32_t)(src)) == 0); | |
5949 | SET_NFLG (((int32_t)(src)) < 0); | |
5950 | m68k_write_memory_32(dsta,src); | |
5951 | }}}}m68k_incpc(2); | |
5952 | return 20; | |
5953 | } | |
5954 | unsigned long CPUFUNC(op_20e0_4)(uint32_t opcode) /* MOVE */ | |
5955 | { | |
5956 | uint32_t srcreg = (opcode & 7); | |
5957 | uint32_t dstreg = (opcode >> 9) & 7; | |
5958 | OpcodeFamily = 30; CurrentInstrCycles = 22; | |
5959 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 4; | |
5960 | { int32_t src = m68k_read_memory_32(srca); | |
5961 | m68k_areg (regs, srcreg) = srca; | |
5962 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
5963 | m68k_areg(regs, dstreg) += 4; | |
5964 | CLEAR_CZNV; | |
5965 | SET_ZFLG (((int32_t)(src)) == 0); | |
5966 | SET_NFLG (((int32_t)(src)) < 0); | |
5967 | m68k_write_memory_32(dsta,src); | |
5968 | }}}}m68k_incpc(2); | |
5969 | return 22; | |
5970 | } | |
5971 | unsigned long CPUFUNC(op_20e8_4)(uint32_t opcode) /* MOVE */ | |
5972 | { | |
5973 | uint32_t srcreg = (opcode & 7); | |
5974 | uint32_t dstreg = (opcode >> 9) & 7; | |
5975 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
5976 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
5977 | { int32_t src = m68k_read_memory_32(srca); | |
5978 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
5979 | m68k_areg(regs, dstreg) += 4; | |
5980 | CLEAR_CZNV; | |
5981 | SET_ZFLG (((int32_t)(src)) == 0); | |
5982 | SET_NFLG (((int32_t)(src)) < 0); | |
5983 | m68k_write_memory_32(dsta,src); | |
5984 | }}}}m68k_incpc(4); | |
5985 | return 24; | |
5986 | } | |
5987 | unsigned long CPUFUNC(op_20f0_4)(uint32_t opcode) /* MOVE */ | |
5988 | { | |
5989 | uint32_t srcreg = (opcode & 7); | |
5990 | uint32_t dstreg = (opcode >> 9) & 7; | |
5991 | OpcodeFamily = 30; CurrentInstrCycles = 26; | |
5992 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
5993 | BusCyclePenalty += 2; | |
5994 | { int32_t src = m68k_read_memory_32(srca); | |
5995 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
5996 | m68k_areg(regs, dstreg) += 4; | |
5997 | CLEAR_CZNV; | |
5998 | SET_ZFLG (((int32_t)(src)) == 0); | |
5999 | SET_NFLG (((int32_t)(src)) < 0); | |
6000 | m68k_write_memory_32(dsta,src); | |
6001 | }}}}m68k_incpc(4); | |
6002 | return 26; | |
6003 | } | |
6004 | unsigned long CPUFUNC(op_20f8_4)(uint32_t opcode) /* MOVE */ | |
6005 | { | |
6006 | uint32_t dstreg = (opcode >> 9) & 7; | |
6007 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
6008 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
6009 | { int32_t src = m68k_read_memory_32(srca); | |
6010 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
6011 | m68k_areg(regs, dstreg) += 4; | |
6012 | CLEAR_CZNV; | |
6013 | SET_ZFLG (((int32_t)(src)) == 0); | |
6014 | SET_NFLG (((int32_t)(src)) < 0); | |
6015 | m68k_write_memory_32(dsta,src); | |
6016 | }}}}m68k_incpc(4); | |
6017 | return 24; | |
6018 | } | |
6019 | unsigned long CPUFUNC(op_20f9_4)(uint32_t opcode) /* MOVE */ | |
6020 | { | |
6021 | uint32_t dstreg = (opcode >> 9) & 7; | |
6022 | OpcodeFamily = 30; CurrentInstrCycles = 28; | |
6023 | {{ uint32_t srca = get_ilong(2); | |
6024 | { int32_t src = m68k_read_memory_32(srca); | |
6025 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
6026 | m68k_areg(regs, dstreg) += 4; | |
6027 | CLEAR_CZNV; | |
6028 | SET_ZFLG (((int32_t)(src)) == 0); | |
6029 | SET_NFLG (((int32_t)(src)) < 0); | |
6030 | m68k_write_memory_32(dsta,src); | |
6031 | }}}}m68k_incpc(6); | |
6032 | return 28; | |
6033 | } | |
6034 | unsigned long CPUFUNC(op_20fa_4)(uint32_t opcode) /* MOVE */ | |
6035 | { | |
6036 | uint32_t dstreg = (opcode >> 9) & 7; | |
6037 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
6038 | {{ uint32_t srca = m68k_getpc () + 2; | |
6039 | srca += (int32_t)(int16_t)get_iword(2); | |
6040 | { int32_t src = m68k_read_memory_32(srca); | |
6041 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
6042 | m68k_areg(regs, dstreg) += 4; | |
6043 | CLEAR_CZNV; | |
6044 | SET_ZFLG (((int32_t)(src)) == 0); | |
6045 | SET_NFLG (((int32_t)(src)) < 0); | |
6046 | m68k_write_memory_32(dsta,src); | |
6047 | }}}}m68k_incpc(4); | |
6048 | return 24; | |
6049 | } | |
6050 | unsigned long CPUFUNC(op_20fb_4)(uint32_t opcode) /* MOVE */ | |
6051 | { | |
6052 | uint32_t dstreg = (opcode >> 9) & 7; | |
6053 | OpcodeFamily = 30; CurrentInstrCycles = 26; | |
6054 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
6055 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
6056 | BusCyclePenalty += 2; | |
6057 | { int32_t src = m68k_read_memory_32(srca); | |
6058 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
6059 | m68k_areg(regs, dstreg) += 4; | |
6060 | CLEAR_CZNV; | |
6061 | SET_ZFLG (((int32_t)(src)) == 0); | |
6062 | SET_NFLG (((int32_t)(src)) < 0); | |
6063 | m68k_write_memory_32(dsta,src); | |
6064 | }}}}m68k_incpc(4); | |
6065 | return 26; | |
6066 | } | |
6067 | unsigned long CPUFUNC(op_20fc_4)(uint32_t opcode) /* MOVE */ | |
6068 | { | |
6069 | uint32_t dstreg = (opcode >> 9) & 7; | |
6070 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
6071 | {{ int32_t src = get_ilong(2); | |
6072 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
6073 | m68k_areg(regs, dstreg) += 4; | |
6074 | CLEAR_CZNV; | |
6075 | SET_ZFLG (((int32_t)(src)) == 0); | |
6076 | SET_NFLG (((int32_t)(src)) < 0); | |
6077 | m68k_write_memory_32(dsta,src); | |
6078 | }}}m68k_incpc(6); | |
6079 | return 20; | |
6080 | } | |
6081 | unsigned long CPUFUNC(op_2100_4)(uint32_t opcode) /* MOVE */ | |
6082 | { | |
6083 | uint32_t srcreg = (opcode & 7); | |
6084 | uint32_t dstreg = (opcode >> 9) & 7; | |
6085 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
6086 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
6087 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
6088 | m68k_areg (regs, dstreg) = dsta; | |
6089 | CLEAR_CZNV; | |
6090 | SET_ZFLG (((int32_t)(src)) == 0); | |
6091 | SET_NFLG (((int32_t)(src)) < 0); | |
6092 | m68k_write_memory_32(dsta,src); | |
6093 | }}}m68k_incpc(2); | |
6094 | return 12; | |
6095 | } | |
6096 | unsigned long CPUFUNC(op_2108_4)(uint32_t opcode) /* MOVE */ | |
6097 | { | |
6098 | uint32_t srcreg = (opcode & 7); | |
6099 | uint32_t dstreg = (opcode >> 9) & 7; | |
6100 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
6101 | {{ int32_t src = m68k_areg(regs, srcreg); | |
6102 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
6103 | m68k_areg (regs, dstreg) = dsta; | |
6104 | CLEAR_CZNV; | |
6105 | SET_ZFLG (((int32_t)(src)) == 0); | |
6106 | SET_NFLG (((int32_t)(src)) < 0); | |
6107 | m68k_write_memory_32(dsta,src); | |
6108 | }}}m68k_incpc(2); | |
6109 | return 12; | |
6110 | } | |
6111 | unsigned long CPUFUNC(op_2110_4)(uint32_t opcode) /* MOVE */ | |
6112 | { | |
6113 | uint32_t srcreg = (opcode & 7); | |
6114 | uint32_t dstreg = (opcode >> 9) & 7; | |
6115 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
6116 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
6117 | { int32_t src = m68k_read_memory_32(srca); | |
6118 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
6119 | m68k_areg (regs, dstreg) = dsta; | |
6120 | CLEAR_CZNV; | |
6121 | SET_ZFLG (((int32_t)(src)) == 0); | |
6122 | SET_NFLG (((int32_t)(src)) < 0); | |
6123 | m68k_write_memory_32(dsta,src); | |
6124 | }}}}m68k_incpc(2); | |
6125 | return 20; | |
6126 | } | |
6127 | unsigned long CPUFUNC(op_2118_4)(uint32_t opcode) /* MOVE */ | |
6128 | { | |
6129 | uint32_t srcreg = (opcode & 7); | |
6130 | uint32_t dstreg = (opcode >> 9) & 7; | |
6131 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
6132 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
6133 | { int32_t src = m68k_read_memory_32(srca); | |
6134 | m68k_areg(regs, srcreg) += 4; | |
6135 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
6136 | m68k_areg (regs, dstreg) = dsta; | |
6137 | CLEAR_CZNV; | |
6138 | SET_ZFLG (((int32_t)(src)) == 0); | |
6139 | SET_NFLG (((int32_t)(src)) < 0); | |
6140 | m68k_write_memory_32(dsta,src); | |
6141 | }}}}m68k_incpc(2); | |
6142 | return 20; | |
6143 | } | |
6144 | unsigned long CPUFUNC(op_2120_4)(uint32_t opcode) /* MOVE */ | |
6145 | { | |
6146 | uint32_t srcreg = (opcode & 7); | |
6147 | uint32_t dstreg = (opcode >> 9) & 7; | |
6148 | OpcodeFamily = 30; CurrentInstrCycles = 22; | |
6149 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 4; | |
6150 | { int32_t src = m68k_read_memory_32(srca); | |
6151 | m68k_areg (regs, srcreg) = srca; | |
6152 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
6153 | m68k_areg (regs, dstreg) = dsta; | |
6154 | CLEAR_CZNV; | |
6155 | SET_ZFLG (((int32_t)(src)) == 0); | |
6156 | SET_NFLG (((int32_t)(src)) < 0); | |
6157 | m68k_write_memory_32(dsta,src); | |
6158 | }}}}m68k_incpc(2); | |
6159 | return 22; | |
6160 | } | |
6161 | unsigned long CPUFUNC(op_2128_4)(uint32_t opcode) /* MOVE */ | |
6162 | { | |
6163 | uint32_t srcreg = (opcode & 7); | |
6164 | uint32_t dstreg = (opcode >> 9) & 7; | |
6165 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
6166 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
6167 | { int32_t src = m68k_read_memory_32(srca); | |
6168 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
6169 | m68k_areg (regs, dstreg) = dsta; | |
6170 | CLEAR_CZNV; | |
6171 | SET_ZFLG (((int32_t)(src)) == 0); | |
6172 | SET_NFLG (((int32_t)(src)) < 0); | |
6173 | m68k_write_memory_32(dsta,src); | |
6174 | }}}}m68k_incpc(4); | |
6175 | return 24; | |
6176 | } | |
6177 | unsigned long CPUFUNC(op_2130_4)(uint32_t opcode) /* MOVE */ | |
6178 | { | |
6179 | uint32_t srcreg = (opcode & 7); | |
6180 | uint32_t dstreg = (opcode >> 9) & 7; | |
6181 | OpcodeFamily = 30; CurrentInstrCycles = 26; | |
6182 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
6183 | BusCyclePenalty += 2; | |
6184 | { int32_t src = m68k_read_memory_32(srca); | |
6185 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
6186 | m68k_areg (regs, dstreg) = dsta; | |
6187 | CLEAR_CZNV; | |
6188 | SET_ZFLG (((int32_t)(src)) == 0); | |
6189 | SET_NFLG (((int32_t)(src)) < 0); | |
6190 | m68k_write_memory_32(dsta,src); | |
6191 | }}}}m68k_incpc(4); | |
6192 | return 26; | |
6193 | } | |
6194 | unsigned long CPUFUNC(op_2138_4)(uint32_t opcode) /* MOVE */ | |
6195 | { | |
6196 | uint32_t dstreg = (opcode >> 9) & 7; | |
6197 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
6198 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
6199 | { int32_t src = m68k_read_memory_32(srca); | |
6200 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
6201 | m68k_areg (regs, dstreg) = dsta; | |
6202 | CLEAR_CZNV; | |
6203 | SET_ZFLG (((int32_t)(src)) == 0); | |
6204 | SET_NFLG (((int32_t)(src)) < 0); | |
6205 | m68k_write_memory_32(dsta,src); | |
6206 | }}}}m68k_incpc(4); | |
6207 | return 24; | |
6208 | } | |
6209 | #endif | |
6210 | ||
6211 | #ifdef PART_3 | |
6212 | unsigned long CPUFUNC(op_2139_4)(uint32_t opcode) /* MOVE */ | |
6213 | { | |
6214 | uint32_t dstreg = (opcode >> 9) & 7; | |
6215 | OpcodeFamily = 30; CurrentInstrCycles = 28; | |
6216 | {{ uint32_t srca = get_ilong(2); | |
6217 | { int32_t src = m68k_read_memory_32(srca); | |
6218 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
6219 | m68k_areg (regs, dstreg) = dsta; | |
6220 | CLEAR_CZNV; | |
6221 | SET_ZFLG (((int32_t)(src)) == 0); | |
6222 | SET_NFLG (((int32_t)(src)) < 0); | |
6223 | m68k_write_memory_32(dsta,src); | |
6224 | }}}}m68k_incpc(6); | |
6225 | return 28; | |
6226 | } | |
6227 | unsigned long CPUFUNC(op_213a_4)(uint32_t opcode) /* MOVE */ | |
6228 | { | |
6229 | uint32_t dstreg = (opcode >> 9) & 7; | |
6230 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
6231 | {{ uint32_t srca = m68k_getpc () + 2; | |
6232 | srca += (int32_t)(int16_t)get_iword(2); | |
6233 | { int32_t src = m68k_read_memory_32(srca); | |
6234 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
6235 | m68k_areg (regs, dstreg) = dsta; | |
6236 | CLEAR_CZNV; | |
6237 | SET_ZFLG (((int32_t)(src)) == 0); | |
6238 | SET_NFLG (((int32_t)(src)) < 0); | |
6239 | m68k_write_memory_32(dsta,src); | |
6240 | }}}}m68k_incpc(4); | |
6241 | return 24; | |
6242 | } | |
6243 | unsigned long CPUFUNC(op_213b_4)(uint32_t opcode) /* MOVE */ | |
6244 | { | |
6245 | uint32_t dstreg = (opcode >> 9) & 7; | |
6246 | OpcodeFamily = 30; CurrentInstrCycles = 26; | |
6247 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
6248 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
6249 | BusCyclePenalty += 2; | |
6250 | { int32_t src = m68k_read_memory_32(srca); | |
6251 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
6252 | m68k_areg (regs, dstreg) = dsta; | |
6253 | CLEAR_CZNV; | |
6254 | SET_ZFLG (((int32_t)(src)) == 0); | |
6255 | SET_NFLG (((int32_t)(src)) < 0); | |
6256 | m68k_write_memory_32(dsta,src); | |
6257 | }}}}m68k_incpc(4); | |
6258 | return 26; | |
6259 | } | |
6260 | unsigned long CPUFUNC(op_213c_4)(uint32_t opcode) /* MOVE */ | |
6261 | { | |
6262 | uint32_t dstreg = (opcode >> 9) & 7; | |
6263 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
6264 | {{ int32_t src = get_ilong(2); | |
6265 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
6266 | m68k_areg (regs, dstreg) = dsta; | |
6267 | CLEAR_CZNV; | |
6268 | SET_ZFLG (((int32_t)(src)) == 0); | |
6269 | SET_NFLG (((int32_t)(src)) < 0); | |
6270 | m68k_write_memory_32(dsta,src); | |
6271 | }}}m68k_incpc(6); | |
6272 | return 20; | |
6273 | } | |
6274 | unsigned long CPUFUNC(op_2140_4)(uint32_t opcode) /* MOVE */ | |
6275 | { | |
6276 | uint32_t srcreg = (opcode & 7); | |
6277 | uint32_t dstreg = (opcode >> 9) & 7; | |
6278 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
6279 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
6280 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); | |
6281 | CLEAR_CZNV; | |
6282 | SET_ZFLG (((int32_t)(src)) == 0); | |
6283 | SET_NFLG (((int32_t)(src)) < 0); | |
6284 | m68k_write_memory_32(dsta,src); | |
6285 | }}}m68k_incpc(4); | |
6286 | return 16; | |
6287 | } | |
6288 | unsigned long CPUFUNC(op_2148_4)(uint32_t opcode) /* MOVE */ | |
6289 | { | |
6290 | uint32_t srcreg = (opcode & 7); | |
6291 | uint32_t dstreg = (opcode >> 9) & 7; | |
6292 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
6293 | {{ int32_t src = m68k_areg(regs, srcreg); | |
6294 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); | |
6295 | CLEAR_CZNV; | |
6296 | SET_ZFLG (((int32_t)(src)) == 0); | |
6297 | SET_NFLG (((int32_t)(src)) < 0); | |
6298 | m68k_write_memory_32(dsta,src); | |
6299 | }}}m68k_incpc(4); | |
6300 | return 16; | |
6301 | } | |
6302 | unsigned long CPUFUNC(op_2150_4)(uint32_t opcode) /* MOVE */ | |
6303 | { | |
6304 | uint32_t srcreg = (opcode & 7); | |
6305 | uint32_t dstreg = (opcode >> 9) & 7; | |
6306 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
6307 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
6308 | { int32_t src = m68k_read_memory_32(srca); | |
6309 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); | |
6310 | CLEAR_CZNV; | |
6311 | SET_ZFLG (((int32_t)(src)) == 0); | |
6312 | SET_NFLG (((int32_t)(src)) < 0); | |
6313 | m68k_write_memory_32(dsta,src); | |
6314 | }}}}m68k_incpc(4); | |
6315 | return 24; | |
6316 | } | |
6317 | unsigned long CPUFUNC(op_2158_4)(uint32_t opcode) /* MOVE */ | |
6318 | { | |
6319 | uint32_t srcreg = (opcode & 7); | |
6320 | uint32_t dstreg = (opcode >> 9) & 7; | |
6321 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
6322 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
6323 | { int32_t src = m68k_read_memory_32(srca); | |
6324 | m68k_areg(regs, srcreg) += 4; | |
6325 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); | |
6326 | CLEAR_CZNV; | |
6327 | SET_ZFLG (((int32_t)(src)) == 0); | |
6328 | SET_NFLG (((int32_t)(src)) < 0); | |
6329 | m68k_write_memory_32(dsta,src); | |
6330 | }}}}m68k_incpc(4); | |
6331 | return 24; | |
6332 | } | |
6333 | unsigned long CPUFUNC(op_2160_4)(uint32_t opcode) /* MOVE */ | |
6334 | { | |
6335 | uint32_t srcreg = (opcode & 7); | |
6336 | uint32_t dstreg = (opcode >> 9) & 7; | |
6337 | OpcodeFamily = 30; CurrentInstrCycles = 26; | |
6338 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 4; | |
6339 | { int32_t src = m68k_read_memory_32(srca); | |
6340 | m68k_areg (regs, srcreg) = srca; | |
6341 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); | |
6342 | CLEAR_CZNV; | |
6343 | SET_ZFLG (((int32_t)(src)) == 0); | |
6344 | SET_NFLG (((int32_t)(src)) < 0); | |
6345 | m68k_write_memory_32(dsta,src); | |
6346 | }}}}m68k_incpc(4); | |
6347 | return 26; | |
6348 | } | |
6349 | unsigned long CPUFUNC(op_2168_4)(uint32_t opcode) /* MOVE */ | |
6350 | { | |
6351 | uint32_t srcreg = (opcode & 7); | |
6352 | uint32_t dstreg = (opcode >> 9) & 7; | |
6353 | OpcodeFamily = 30; CurrentInstrCycles = 28; | |
6354 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
6355 | { int32_t src = m68k_read_memory_32(srca); | |
6356 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); | |
6357 | CLEAR_CZNV; | |
6358 | SET_ZFLG (((int32_t)(src)) == 0); | |
6359 | SET_NFLG (((int32_t)(src)) < 0); | |
6360 | m68k_write_memory_32(dsta,src); | |
6361 | }}}}m68k_incpc(6); | |
6362 | return 28; | |
6363 | } | |
6364 | unsigned long CPUFUNC(op_2170_4)(uint32_t opcode) /* MOVE */ | |
6365 | { | |
6366 | uint32_t srcreg = (opcode & 7); | |
6367 | uint32_t dstreg = (opcode >> 9) & 7; | |
6368 | OpcodeFamily = 30; CurrentInstrCycles = 30; | |
6369 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
6370 | BusCyclePenalty += 2; | |
6371 | { int32_t src = m68k_read_memory_32(srca); | |
6372 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); | |
6373 | CLEAR_CZNV; | |
6374 | SET_ZFLG (((int32_t)(src)) == 0); | |
6375 | SET_NFLG (((int32_t)(src)) < 0); | |
6376 | m68k_write_memory_32(dsta,src); | |
6377 | }}}}m68k_incpc(6); | |
6378 | return 30; | |
6379 | } | |
6380 | unsigned long CPUFUNC(op_2178_4)(uint32_t opcode) /* MOVE */ | |
6381 | { | |
6382 | uint32_t dstreg = (opcode >> 9) & 7; | |
6383 | OpcodeFamily = 30; CurrentInstrCycles = 28; | |
6384 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
6385 | { int32_t src = m68k_read_memory_32(srca); | |
6386 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); | |
6387 | CLEAR_CZNV; | |
6388 | SET_ZFLG (((int32_t)(src)) == 0); | |
6389 | SET_NFLG (((int32_t)(src)) < 0); | |
6390 | m68k_write_memory_32(dsta,src); | |
6391 | }}}}m68k_incpc(6); | |
6392 | return 28; | |
6393 | } | |
6394 | unsigned long CPUFUNC(op_2179_4)(uint32_t opcode) /* MOVE */ | |
6395 | { | |
6396 | uint32_t dstreg = (opcode >> 9) & 7; | |
6397 | OpcodeFamily = 30; CurrentInstrCycles = 32; | |
6398 | {{ uint32_t srca = get_ilong(2); | |
6399 | { int32_t src = m68k_read_memory_32(srca); | |
6400 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(6); | |
6401 | CLEAR_CZNV; | |
6402 | SET_ZFLG (((int32_t)(src)) == 0); | |
6403 | SET_NFLG (((int32_t)(src)) < 0); | |
6404 | m68k_write_memory_32(dsta,src); | |
6405 | }}}}m68k_incpc(8); | |
6406 | return 32; | |
6407 | } | |
6408 | unsigned long CPUFUNC(op_217a_4)(uint32_t opcode) /* MOVE */ | |
6409 | { | |
6410 | uint32_t dstreg = (opcode >> 9) & 7; | |
6411 | OpcodeFamily = 30; CurrentInstrCycles = 28; | |
6412 | {{ uint32_t srca = m68k_getpc () + 2; | |
6413 | srca += (int32_t)(int16_t)get_iword(2); | |
6414 | { int32_t src = m68k_read_memory_32(srca); | |
6415 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); | |
6416 | CLEAR_CZNV; | |
6417 | SET_ZFLG (((int32_t)(src)) == 0); | |
6418 | SET_NFLG (((int32_t)(src)) < 0); | |
6419 | m68k_write_memory_32(dsta,src); | |
6420 | }}}}m68k_incpc(6); | |
6421 | return 28; | |
6422 | } | |
6423 | unsigned long CPUFUNC(op_217b_4)(uint32_t opcode) /* MOVE */ | |
6424 | { | |
6425 | uint32_t dstreg = (opcode >> 9) & 7; | |
6426 | OpcodeFamily = 30; CurrentInstrCycles = 30; | |
6427 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
6428 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
6429 | BusCyclePenalty += 2; | |
6430 | { int32_t src = m68k_read_memory_32(srca); | |
6431 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); | |
6432 | CLEAR_CZNV; | |
6433 | SET_ZFLG (((int32_t)(src)) == 0); | |
6434 | SET_NFLG (((int32_t)(src)) < 0); | |
6435 | m68k_write_memory_32(dsta,src); | |
6436 | }}}}m68k_incpc(6); | |
6437 | return 30; | |
6438 | } | |
6439 | unsigned long CPUFUNC(op_217c_4)(uint32_t opcode) /* MOVE */ | |
6440 | { | |
6441 | uint32_t dstreg = (opcode >> 9) & 7; | |
6442 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
6443 | {{ int32_t src = get_ilong(2); | |
6444 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(6); | |
6445 | CLEAR_CZNV; | |
6446 | SET_ZFLG (((int32_t)(src)) == 0); | |
6447 | SET_NFLG (((int32_t)(src)) < 0); | |
6448 | m68k_write_memory_32(dsta,src); | |
6449 | }}}m68k_incpc(8); | |
6450 | return 24; | |
6451 | } | |
6452 | unsigned long CPUFUNC(op_2180_4)(uint32_t opcode) /* MOVE */ | |
6453 | { | |
6454 | uint32_t srcreg = (opcode & 7); | |
6455 | uint32_t dstreg = (opcode >> 9) & 7; | |
6456 | OpcodeFamily = 30; CurrentInstrCycles = 18; | |
6457 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
6458 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); | |
6459 | BusCyclePenalty += 2; | |
6460 | CLEAR_CZNV; | |
6461 | SET_ZFLG (((int32_t)(src)) == 0); | |
6462 | SET_NFLG (((int32_t)(src)) < 0); | |
6463 | m68k_write_memory_32(dsta,src); | |
6464 | }}}m68k_incpc(4); | |
6465 | return 18; | |
6466 | } | |
6467 | unsigned long CPUFUNC(op_2188_4)(uint32_t opcode) /* MOVE */ | |
6468 | { | |
6469 | uint32_t srcreg = (opcode & 7); | |
6470 | uint32_t dstreg = (opcode >> 9) & 7; | |
6471 | OpcodeFamily = 30; CurrentInstrCycles = 18; | |
6472 | {{ int32_t src = m68k_areg(regs, srcreg); | |
6473 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); | |
6474 | BusCyclePenalty += 2; | |
6475 | CLEAR_CZNV; | |
6476 | SET_ZFLG (((int32_t)(src)) == 0); | |
6477 | SET_NFLG (((int32_t)(src)) < 0); | |
6478 | m68k_write_memory_32(dsta,src); | |
6479 | }}}m68k_incpc(4); | |
6480 | return 18; | |
6481 | } | |
6482 | unsigned long CPUFUNC(op_2190_4)(uint32_t opcode) /* MOVE */ | |
6483 | { | |
6484 | uint32_t srcreg = (opcode & 7); | |
6485 | uint32_t dstreg = (opcode >> 9) & 7; | |
6486 | OpcodeFamily = 30; CurrentInstrCycles = 26; | |
6487 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
6488 | { int32_t src = m68k_read_memory_32(srca); | |
6489 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); | |
6490 | BusCyclePenalty += 2; | |
6491 | CLEAR_CZNV; | |
6492 | SET_ZFLG (((int32_t)(src)) == 0); | |
6493 | SET_NFLG (((int32_t)(src)) < 0); | |
6494 | m68k_write_memory_32(dsta,src); | |
6495 | }}}}m68k_incpc(4); | |
6496 | return 26; | |
6497 | } | |
6498 | unsigned long CPUFUNC(op_2198_4)(uint32_t opcode) /* MOVE */ | |
6499 | { | |
6500 | uint32_t srcreg = (opcode & 7); | |
6501 | uint32_t dstreg = (opcode >> 9) & 7; | |
6502 | OpcodeFamily = 30; CurrentInstrCycles = 26; | |
6503 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
6504 | { int32_t src = m68k_read_memory_32(srca); | |
6505 | m68k_areg(regs, srcreg) += 4; | |
6506 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); | |
6507 | BusCyclePenalty += 2; | |
6508 | CLEAR_CZNV; | |
6509 | SET_ZFLG (((int32_t)(src)) == 0); | |
6510 | SET_NFLG (((int32_t)(src)) < 0); | |
6511 | m68k_write_memory_32(dsta,src); | |
6512 | }}}}m68k_incpc(4); | |
6513 | return 26; | |
6514 | } | |
6515 | unsigned long CPUFUNC(op_21a0_4)(uint32_t opcode) /* MOVE */ | |
6516 | { | |
6517 | uint32_t srcreg = (opcode & 7); | |
6518 | uint32_t dstreg = (opcode >> 9) & 7; | |
6519 | OpcodeFamily = 30; CurrentInstrCycles = 28; | |
6520 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 4; | |
6521 | { int32_t src = m68k_read_memory_32(srca); | |
6522 | m68k_areg (regs, srcreg) = srca; | |
6523 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); | |
6524 | BusCyclePenalty += 2; | |
6525 | CLEAR_CZNV; | |
6526 | SET_ZFLG (((int32_t)(src)) == 0); | |
6527 | SET_NFLG (((int32_t)(src)) < 0); | |
6528 | m68k_write_memory_32(dsta,src); | |
6529 | }}}}m68k_incpc(4); | |
6530 | return 28; | |
6531 | } | |
6532 | unsigned long CPUFUNC(op_21a8_4)(uint32_t opcode) /* MOVE */ | |
6533 | { | |
6534 | uint32_t srcreg = (opcode & 7); | |
6535 | uint32_t dstreg = (opcode >> 9) & 7; | |
6536 | OpcodeFamily = 30; CurrentInstrCycles = 30; | |
6537 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
6538 | { int32_t src = m68k_read_memory_32(srca); | |
6539 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); | |
6540 | BusCyclePenalty += 2; | |
6541 | CLEAR_CZNV; | |
6542 | SET_ZFLG (((int32_t)(src)) == 0); | |
6543 | SET_NFLG (((int32_t)(src)) < 0); | |
6544 | m68k_write_memory_32(dsta,src); | |
6545 | }}}}m68k_incpc(6); | |
6546 | return 30; | |
6547 | } | |
6548 | unsigned long CPUFUNC(op_21b0_4)(uint32_t opcode) /* MOVE */ | |
6549 | { | |
6550 | uint32_t srcreg = (opcode & 7); | |
6551 | uint32_t dstreg = (opcode >> 9) & 7; | |
6552 | OpcodeFamily = 30; CurrentInstrCycles = 32; | |
6553 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
6554 | BusCyclePenalty += 2; | |
6555 | { int32_t src = m68k_read_memory_32(srca); | |
6556 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); | |
6557 | BusCyclePenalty += 2; | |
6558 | CLEAR_CZNV; | |
6559 | SET_ZFLG (((int32_t)(src)) == 0); | |
6560 | SET_NFLG (((int32_t)(src)) < 0); | |
6561 | m68k_write_memory_32(dsta,src); | |
6562 | }}}}m68k_incpc(6); | |
6563 | return 32; | |
6564 | } | |
6565 | unsigned long CPUFUNC(op_21b8_4)(uint32_t opcode) /* MOVE */ | |
6566 | { | |
6567 | uint32_t dstreg = (opcode >> 9) & 7; | |
6568 | OpcodeFamily = 30; CurrentInstrCycles = 30; | |
6569 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
6570 | { int32_t src = m68k_read_memory_32(srca); | |
6571 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); | |
6572 | BusCyclePenalty += 2; | |
6573 | CLEAR_CZNV; | |
6574 | SET_ZFLG (((int32_t)(src)) == 0); | |
6575 | SET_NFLG (((int32_t)(src)) < 0); | |
6576 | m68k_write_memory_32(dsta,src); | |
6577 | }}}}m68k_incpc(6); | |
6578 | return 30; | |
6579 | } | |
6580 | unsigned long CPUFUNC(op_21b9_4)(uint32_t opcode) /* MOVE */ | |
6581 | { | |
6582 | uint32_t dstreg = (opcode >> 9) & 7; | |
6583 | OpcodeFamily = 30; CurrentInstrCycles = 34; | |
6584 | {{ uint32_t srca = get_ilong(2); | |
6585 | { int32_t src = m68k_read_memory_32(srca); | |
6586 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(6)); | |
6587 | BusCyclePenalty += 2; | |
6588 | CLEAR_CZNV; | |
6589 | SET_ZFLG (((int32_t)(src)) == 0); | |
6590 | SET_NFLG (((int32_t)(src)) < 0); | |
6591 | m68k_write_memory_32(dsta,src); | |
6592 | }}}}m68k_incpc(8); | |
6593 | return 34; | |
6594 | } | |
6595 | unsigned long CPUFUNC(op_21ba_4)(uint32_t opcode) /* MOVE */ | |
6596 | { | |
6597 | uint32_t dstreg = (opcode >> 9) & 7; | |
6598 | OpcodeFamily = 30; CurrentInstrCycles = 30; | |
6599 | {{ uint32_t srca = m68k_getpc () + 2; | |
6600 | srca += (int32_t)(int16_t)get_iword(2); | |
6601 | { int32_t src = m68k_read_memory_32(srca); | |
6602 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); | |
6603 | BusCyclePenalty += 2; | |
6604 | CLEAR_CZNV; | |
6605 | SET_ZFLG (((int32_t)(src)) == 0); | |
6606 | SET_NFLG (((int32_t)(src)) < 0); | |
6607 | m68k_write_memory_32(dsta,src); | |
6608 | }}}}m68k_incpc(6); | |
6609 | return 30; | |
6610 | } | |
6611 | unsigned long CPUFUNC(op_21bb_4)(uint32_t opcode) /* MOVE */ | |
6612 | { | |
6613 | uint32_t dstreg = (opcode >> 9) & 7; | |
6614 | OpcodeFamily = 30; CurrentInstrCycles = 32; | |
6615 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
6616 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
6617 | BusCyclePenalty += 2; | |
6618 | { int32_t src = m68k_read_memory_32(srca); | |
6619 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); | |
6620 | BusCyclePenalty += 2; | |
6621 | CLEAR_CZNV; | |
6622 | SET_ZFLG (((int32_t)(src)) == 0); | |
6623 | SET_NFLG (((int32_t)(src)) < 0); | |
6624 | m68k_write_memory_32(dsta,src); | |
6625 | }}}}m68k_incpc(6); | |
6626 | return 32; | |
6627 | } | |
6628 | unsigned long CPUFUNC(op_21bc_4)(uint32_t opcode) /* MOVE */ | |
6629 | { | |
6630 | uint32_t dstreg = (opcode >> 9) & 7; | |
6631 | OpcodeFamily = 30; CurrentInstrCycles = 26; | |
6632 | {{ int32_t src = get_ilong(2); | |
6633 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(6)); | |
6634 | BusCyclePenalty += 2; | |
6635 | CLEAR_CZNV; | |
6636 | SET_ZFLG (((int32_t)(src)) == 0); | |
6637 | SET_NFLG (((int32_t)(src)) < 0); | |
6638 | m68k_write_memory_32(dsta,src); | |
6639 | }}}m68k_incpc(8); | |
6640 | return 26; | |
6641 | } | |
6642 | unsigned long CPUFUNC(op_21c0_4)(uint32_t opcode) /* MOVE */ | |
6643 | { | |
6644 | uint32_t srcreg = (opcode & 7); | |
6645 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
6646 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
6647 | { uint32_t dsta = (int32_t)(int16_t)get_iword(2); | |
6648 | CLEAR_CZNV; | |
6649 | SET_ZFLG (((int32_t)(src)) == 0); | |
6650 | SET_NFLG (((int32_t)(src)) < 0); | |
6651 | m68k_write_memory_32(dsta,src); | |
6652 | }}}m68k_incpc(4); | |
6653 | return 16; | |
6654 | } | |
6655 | unsigned long CPUFUNC(op_21c8_4)(uint32_t opcode) /* MOVE */ | |
6656 | { | |
6657 | uint32_t srcreg = (opcode & 7); | |
6658 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
6659 | {{ int32_t src = m68k_areg(regs, srcreg); | |
6660 | { uint32_t dsta = (int32_t)(int16_t)get_iword(2); | |
6661 | CLEAR_CZNV; | |
6662 | SET_ZFLG (((int32_t)(src)) == 0); | |
6663 | SET_NFLG (((int32_t)(src)) < 0); | |
6664 | m68k_write_memory_32(dsta,src); | |
6665 | }}}m68k_incpc(4); | |
6666 | return 16; | |
6667 | } | |
6668 | unsigned long CPUFUNC(op_21d0_4)(uint32_t opcode) /* MOVE */ | |
6669 | { | |
6670 | uint32_t srcreg = (opcode & 7); | |
6671 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
6672 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
6673 | { int32_t src = m68k_read_memory_32(srca); | |
6674 | { uint32_t dsta = (int32_t)(int16_t)get_iword(2); | |
6675 | CLEAR_CZNV; | |
6676 | SET_ZFLG (((int32_t)(src)) == 0); | |
6677 | SET_NFLG (((int32_t)(src)) < 0); | |
6678 | m68k_write_memory_32(dsta,src); | |
6679 | }}}}m68k_incpc(4); | |
6680 | return 24; | |
6681 | } | |
6682 | unsigned long CPUFUNC(op_21d8_4)(uint32_t opcode) /* MOVE */ | |
6683 | { | |
6684 | uint32_t srcreg = (opcode & 7); | |
6685 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
6686 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
6687 | { int32_t src = m68k_read_memory_32(srca); | |
6688 | m68k_areg(regs, srcreg) += 4; | |
6689 | { uint32_t dsta = (int32_t)(int16_t)get_iword(2); | |
6690 | CLEAR_CZNV; | |
6691 | SET_ZFLG (((int32_t)(src)) == 0); | |
6692 | SET_NFLG (((int32_t)(src)) < 0); | |
6693 | m68k_write_memory_32(dsta,src); | |
6694 | }}}}m68k_incpc(4); | |
6695 | return 24; | |
6696 | } | |
6697 | unsigned long CPUFUNC(op_21e0_4)(uint32_t opcode) /* MOVE */ | |
6698 | { | |
6699 | uint32_t srcreg = (opcode & 7); | |
6700 | OpcodeFamily = 30; CurrentInstrCycles = 26; | |
6701 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 4; | |
6702 | { int32_t src = m68k_read_memory_32(srca); | |
6703 | m68k_areg (regs, srcreg) = srca; | |
6704 | { uint32_t dsta = (int32_t)(int16_t)get_iword(2); | |
6705 | CLEAR_CZNV; | |
6706 | SET_ZFLG (((int32_t)(src)) == 0); | |
6707 | SET_NFLG (((int32_t)(src)) < 0); | |
6708 | m68k_write_memory_32(dsta,src); | |
6709 | }}}}m68k_incpc(4); | |
6710 | return 26; | |
6711 | } | |
6712 | unsigned long CPUFUNC(op_21e8_4)(uint32_t opcode) /* MOVE */ | |
6713 | { | |
6714 | uint32_t srcreg = (opcode & 7); | |
6715 | OpcodeFamily = 30; CurrentInstrCycles = 28; | |
6716 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
6717 | { int32_t src = m68k_read_memory_32(srca); | |
6718 | { uint32_t dsta = (int32_t)(int16_t)get_iword(4); | |
6719 | CLEAR_CZNV; | |
6720 | SET_ZFLG (((int32_t)(src)) == 0); | |
6721 | SET_NFLG (((int32_t)(src)) < 0); | |
6722 | m68k_write_memory_32(dsta,src); | |
6723 | }}}}m68k_incpc(6); | |
6724 | return 28; | |
6725 | } | |
6726 | unsigned long CPUFUNC(op_21f0_4)(uint32_t opcode) /* MOVE */ | |
6727 | { | |
6728 | uint32_t srcreg = (opcode & 7); | |
6729 | OpcodeFamily = 30; CurrentInstrCycles = 30; | |
6730 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
6731 | BusCyclePenalty += 2; | |
6732 | { int32_t src = m68k_read_memory_32(srca); | |
6733 | { uint32_t dsta = (int32_t)(int16_t)get_iword(4); | |
6734 | CLEAR_CZNV; | |
6735 | SET_ZFLG (((int32_t)(src)) == 0); | |
6736 | SET_NFLG (((int32_t)(src)) < 0); | |
6737 | m68k_write_memory_32(dsta,src); | |
6738 | }}}}m68k_incpc(6); | |
6739 | return 30; | |
6740 | } | |
6741 | unsigned long CPUFUNC(op_21f8_4)(uint32_t opcode) /* MOVE */ | |
6742 | { | |
6743 | OpcodeFamily = 30; CurrentInstrCycles = 28; | |
6744 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
6745 | { int32_t src = m68k_read_memory_32(srca); | |
6746 | { uint32_t dsta = (int32_t)(int16_t)get_iword(4); | |
6747 | CLEAR_CZNV; | |
6748 | SET_ZFLG (((int32_t)(src)) == 0); | |
6749 | SET_NFLG (((int32_t)(src)) < 0); | |
6750 | m68k_write_memory_32(dsta,src); | |
6751 | }}}}m68k_incpc(6); | |
6752 | return 28; | |
6753 | } | |
6754 | unsigned long CPUFUNC(op_21f9_4)(uint32_t opcode) /* MOVE */ | |
6755 | { | |
6756 | OpcodeFamily = 30; CurrentInstrCycles = 32; | |
6757 | {{ uint32_t srca = get_ilong(2); | |
6758 | { int32_t src = m68k_read_memory_32(srca); | |
6759 | { uint32_t dsta = (int32_t)(int16_t)get_iword(6); | |
6760 | CLEAR_CZNV; | |
6761 | SET_ZFLG (((int32_t)(src)) == 0); | |
6762 | SET_NFLG (((int32_t)(src)) < 0); | |
6763 | m68k_write_memory_32(dsta,src); | |
6764 | }}}}m68k_incpc(8); | |
6765 | return 32; | |
6766 | } | |
6767 | unsigned long CPUFUNC(op_21fa_4)(uint32_t opcode) /* MOVE */ | |
6768 | { | |
6769 | OpcodeFamily = 30; CurrentInstrCycles = 28; | |
6770 | {{ uint32_t srca = m68k_getpc () + 2; | |
6771 | srca += (int32_t)(int16_t)get_iword(2); | |
6772 | { int32_t src = m68k_read_memory_32(srca); | |
6773 | { uint32_t dsta = (int32_t)(int16_t)get_iword(4); | |
6774 | CLEAR_CZNV; | |
6775 | SET_ZFLG (((int32_t)(src)) == 0); | |
6776 | SET_NFLG (((int32_t)(src)) < 0); | |
6777 | m68k_write_memory_32(dsta,src); | |
6778 | }}}}m68k_incpc(6); | |
6779 | return 28; | |
6780 | } | |
6781 | unsigned long CPUFUNC(op_21fb_4)(uint32_t opcode) /* MOVE */ | |
6782 | { | |
6783 | OpcodeFamily = 30; CurrentInstrCycles = 30; | |
6784 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
6785 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
6786 | BusCyclePenalty += 2; | |
6787 | { int32_t src = m68k_read_memory_32(srca); | |
6788 | { uint32_t dsta = (int32_t)(int16_t)get_iword(4); | |
6789 | CLEAR_CZNV; | |
6790 | SET_ZFLG (((int32_t)(src)) == 0); | |
6791 | SET_NFLG (((int32_t)(src)) < 0); | |
6792 | m68k_write_memory_32(dsta,src); | |
6793 | }}}}m68k_incpc(6); | |
6794 | return 30; | |
6795 | } | |
6796 | unsigned long CPUFUNC(op_21fc_4)(uint32_t opcode) /* MOVE */ | |
6797 | { | |
6798 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
6799 | {{ int32_t src = get_ilong(2); | |
6800 | { uint32_t dsta = (int32_t)(int16_t)get_iword(6); | |
6801 | CLEAR_CZNV; | |
6802 | SET_ZFLG (((int32_t)(src)) == 0); | |
6803 | SET_NFLG (((int32_t)(src)) < 0); | |
6804 | m68k_write_memory_32(dsta,src); | |
6805 | }}}m68k_incpc(8); | |
6806 | return 24; | |
6807 | } | |
6808 | unsigned long CPUFUNC(op_23c0_4)(uint32_t opcode) /* MOVE */ | |
6809 | { | |
6810 | uint32_t srcreg = (opcode & 7); | |
6811 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
6812 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
6813 | { uint32_t dsta = get_ilong(2); | |
6814 | CLEAR_CZNV; | |
6815 | SET_ZFLG (((int32_t)(src)) == 0); | |
6816 | SET_NFLG (((int32_t)(src)) < 0); | |
6817 | m68k_write_memory_32(dsta,src); | |
6818 | }}}m68k_incpc(6); | |
6819 | return 20; | |
6820 | } | |
6821 | unsigned long CPUFUNC(op_23c8_4)(uint32_t opcode) /* MOVE */ | |
6822 | { | |
6823 | uint32_t srcreg = (opcode & 7); | |
6824 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
6825 | {{ int32_t src = m68k_areg(regs, srcreg); | |
6826 | { uint32_t dsta = get_ilong(2); | |
6827 | CLEAR_CZNV; | |
6828 | SET_ZFLG (((int32_t)(src)) == 0); | |
6829 | SET_NFLG (((int32_t)(src)) < 0); | |
6830 | m68k_write_memory_32(dsta,src); | |
6831 | }}}m68k_incpc(6); | |
6832 | return 20; | |
6833 | } | |
6834 | unsigned long CPUFUNC(op_23d0_4)(uint32_t opcode) /* MOVE */ | |
6835 | { | |
6836 | uint32_t srcreg = (opcode & 7); | |
6837 | OpcodeFamily = 30; CurrentInstrCycles = 28; | |
6838 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
6839 | { int32_t src = m68k_read_memory_32(srca); | |
6840 | { uint32_t dsta = get_ilong(2); | |
6841 | CLEAR_CZNV; | |
6842 | SET_ZFLG (((int32_t)(src)) == 0); | |
6843 | SET_NFLG (((int32_t)(src)) < 0); | |
6844 | m68k_write_memory_32(dsta,src); | |
6845 | }}}}m68k_incpc(6); | |
6846 | return 28; | |
6847 | } | |
6848 | unsigned long CPUFUNC(op_23d8_4)(uint32_t opcode) /* MOVE */ | |
6849 | { | |
6850 | uint32_t srcreg = (opcode & 7); | |
6851 | OpcodeFamily = 30; CurrentInstrCycles = 28; | |
6852 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
6853 | { int32_t src = m68k_read_memory_32(srca); | |
6854 | m68k_areg(regs, srcreg) += 4; | |
6855 | { uint32_t dsta = get_ilong(2); | |
6856 | CLEAR_CZNV; | |
6857 | SET_ZFLG (((int32_t)(src)) == 0); | |
6858 | SET_NFLG (((int32_t)(src)) < 0); | |
6859 | m68k_write_memory_32(dsta,src); | |
6860 | }}}}m68k_incpc(6); | |
6861 | return 28; | |
6862 | } | |
6863 | unsigned long CPUFUNC(op_23e0_4)(uint32_t opcode) /* MOVE */ | |
6864 | { | |
6865 | uint32_t srcreg = (opcode & 7); | |
6866 | OpcodeFamily = 30; CurrentInstrCycles = 30; | |
6867 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 4; | |
6868 | { int32_t src = m68k_read_memory_32(srca); | |
6869 | m68k_areg (regs, srcreg) = srca; | |
6870 | { uint32_t dsta = get_ilong(2); | |
6871 | CLEAR_CZNV; | |
6872 | SET_ZFLG (((int32_t)(src)) == 0); | |
6873 | SET_NFLG (((int32_t)(src)) < 0); | |
6874 | m68k_write_memory_32(dsta,src); | |
6875 | }}}}m68k_incpc(6); | |
6876 | return 30; | |
6877 | } | |
6878 | unsigned long CPUFUNC(op_23e8_4)(uint32_t opcode) /* MOVE */ | |
6879 | { | |
6880 | uint32_t srcreg = (opcode & 7); | |
6881 | OpcodeFamily = 30; CurrentInstrCycles = 32; | |
6882 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
6883 | { int32_t src = m68k_read_memory_32(srca); | |
6884 | { uint32_t dsta = get_ilong(4); | |
6885 | CLEAR_CZNV; | |
6886 | SET_ZFLG (((int32_t)(src)) == 0); | |
6887 | SET_NFLG (((int32_t)(src)) < 0); | |
6888 | m68k_write_memory_32(dsta,src); | |
6889 | }}}}m68k_incpc(8); | |
6890 | return 32; | |
6891 | } | |
6892 | unsigned long CPUFUNC(op_23f0_4)(uint32_t opcode) /* MOVE */ | |
6893 | { | |
6894 | uint32_t srcreg = (opcode & 7); | |
6895 | OpcodeFamily = 30; CurrentInstrCycles = 34; | |
6896 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
6897 | BusCyclePenalty += 2; | |
6898 | { int32_t src = m68k_read_memory_32(srca); | |
6899 | { uint32_t dsta = get_ilong(4); | |
6900 | CLEAR_CZNV; | |
6901 | SET_ZFLG (((int32_t)(src)) == 0); | |
6902 | SET_NFLG (((int32_t)(src)) < 0); | |
6903 | m68k_write_memory_32(dsta,src); | |
6904 | }}}}m68k_incpc(8); | |
6905 | return 34; | |
6906 | } | |
6907 | unsigned long CPUFUNC(op_23f8_4)(uint32_t opcode) /* MOVE */ | |
6908 | { | |
6909 | OpcodeFamily = 30; CurrentInstrCycles = 32; | |
6910 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
6911 | { int32_t src = m68k_read_memory_32(srca); | |
6912 | { uint32_t dsta = get_ilong(4); | |
6913 | CLEAR_CZNV; | |
6914 | SET_ZFLG (((int32_t)(src)) == 0); | |
6915 | SET_NFLG (((int32_t)(src)) < 0); | |
6916 | m68k_write_memory_32(dsta,src); | |
6917 | }}}}m68k_incpc(8); | |
6918 | return 32; | |
6919 | } | |
6920 | unsigned long CPUFUNC(op_23f9_4)(uint32_t opcode) /* MOVE */ | |
6921 | { | |
6922 | OpcodeFamily = 30; CurrentInstrCycles = 36; | |
6923 | {{ uint32_t srca = get_ilong(2); | |
6924 | { int32_t src = m68k_read_memory_32(srca); | |
6925 | { uint32_t dsta = get_ilong(6); | |
6926 | CLEAR_CZNV; | |
6927 | SET_ZFLG (((int32_t)(src)) == 0); | |
6928 | SET_NFLG (((int32_t)(src)) < 0); | |
6929 | m68k_write_memory_32(dsta,src); | |
6930 | }}}}m68k_incpc(10); | |
6931 | return 36; | |
6932 | } | |
6933 | unsigned long CPUFUNC(op_23fa_4)(uint32_t opcode) /* MOVE */ | |
6934 | { | |
6935 | OpcodeFamily = 30; CurrentInstrCycles = 32; | |
6936 | {{ uint32_t srca = m68k_getpc () + 2; | |
6937 | srca += (int32_t)(int16_t)get_iword(2); | |
6938 | { int32_t src = m68k_read_memory_32(srca); | |
6939 | { uint32_t dsta = get_ilong(4); | |
6940 | CLEAR_CZNV; | |
6941 | SET_ZFLG (((int32_t)(src)) == 0); | |
6942 | SET_NFLG (((int32_t)(src)) < 0); | |
6943 | m68k_write_memory_32(dsta,src); | |
6944 | }}}}m68k_incpc(8); | |
6945 | return 32; | |
6946 | } | |
6947 | unsigned long CPUFUNC(op_23fb_4)(uint32_t opcode) /* MOVE */ | |
6948 | { | |
6949 | OpcodeFamily = 30; CurrentInstrCycles = 34; | |
6950 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
6951 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
6952 | BusCyclePenalty += 2; | |
6953 | { int32_t src = m68k_read_memory_32(srca); | |
6954 | { uint32_t dsta = get_ilong(4); | |
6955 | CLEAR_CZNV; | |
6956 | SET_ZFLG (((int32_t)(src)) == 0); | |
6957 | SET_NFLG (((int32_t)(src)) < 0); | |
6958 | m68k_write_memory_32(dsta,src); | |
6959 | }}}}m68k_incpc(8); | |
6960 | return 34; | |
6961 | } | |
6962 | unsigned long CPUFUNC(op_23fc_4)(uint32_t opcode) /* MOVE */ | |
6963 | { | |
6964 | OpcodeFamily = 30; CurrentInstrCycles = 28; | |
6965 | {{ int32_t src = get_ilong(2); | |
6966 | { uint32_t dsta = get_ilong(6); | |
6967 | CLEAR_CZNV; | |
6968 | SET_ZFLG (((int32_t)(src)) == 0); | |
6969 | SET_NFLG (((int32_t)(src)) < 0); | |
6970 | m68k_write_memory_32(dsta,src); | |
6971 | }}}m68k_incpc(10); | |
6972 | return 28; | |
6973 | } | |
6974 | unsigned long CPUFUNC(op_3000_4)(uint32_t opcode) /* MOVE */ | |
6975 | { | |
6976 | uint32_t srcreg = (opcode & 7); | |
6977 | uint32_t dstreg = (opcode >> 9) & 7; | |
6978 | OpcodeFamily = 30; CurrentInstrCycles = 4; | |
6979 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
6980 | { CLEAR_CZNV; | |
6981 | SET_ZFLG (((int16_t)(src)) == 0); | |
6982 | SET_NFLG (((int16_t)(src)) < 0); | |
6983 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
6984 | }}}m68k_incpc(2); | |
6985 | return 4; | |
6986 | } | |
6987 | unsigned long CPUFUNC(op_3008_4)(uint32_t opcode) /* MOVE */ | |
6988 | { | |
6989 | uint32_t srcreg = (opcode & 7); | |
6990 | uint32_t dstreg = (opcode >> 9) & 7; | |
6991 | OpcodeFamily = 30; CurrentInstrCycles = 4; | |
6992 | {{ int16_t src = m68k_areg(regs, srcreg); | |
6993 | { CLEAR_CZNV; | |
6994 | SET_ZFLG (((int16_t)(src)) == 0); | |
6995 | SET_NFLG (((int16_t)(src)) < 0); | |
6996 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
6997 | }}}m68k_incpc(2); | |
6998 | return 4; | |
6999 | } | |
7000 | unsigned long CPUFUNC(op_3010_4)(uint32_t opcode) /* MOVE */ | |
7001 | { | |
7002 | uint32_t srcreg = (opcode & 7); | |
7003 | uint32_t dstreg = (opcode >> 9) & 7; | |
7004 | OpcodeFamily = 30; CurrentInstrCycles = 8; | |
7005 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
7006 | { int16_t src = m68k_read_memory_16(srca); | |
7007 | { CLEAR_CZNV; | |
7008 | SET_ZFLG (((int16_t)(src)) == 0); | |
7009 | SET_NFLG (((int16_t)(src)) < 0); | |
7010 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
7011 | }}}}m68k_incpc(2); | |
7012 | return 8; | |
7013 | } | |
7014 | unsigned long CPUFUNC(op_3018_4)(uint32_t opcode) /* MOVE */ | |
7015 | { | |
7016 | uint32_t srcreg = (opcode & 7); | |
7017 | uint32_t dstreg = (opcode >> 9) & 7; | |
7018 | OpcodeFamily = 30; CurrentInstrCycles = 8; | |
7019 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
7020 | { int16_t src = m68k_read_memory_16(srca); | |
7021 | m68k_areg(regs, srcreg) += 2; | |
7022 | { CLEAR_CZNV; | |
7023 | SET_ZFLG (((int16_t)(src)) == 0); | |
7024 | SET_NFLG (((int16_t)(src)) < 0); | |
7025 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
7026 | }}}}m68k_incpc(2); | |
7027 | return 8; | |
7028 | } | |
7029 | unsigned long CPUFUNC(op_3020_4)(uint32_t opcode) /* MOVE */ | |
7030 | { | |
7031 | uint32_t srcreg = (opcode & 7); | |
7032 | uint32_t dstreg = (opcode >> 9) & 7; | |
7033 | OpcodeFamily = 30; CurrentInstrCycles = 10; | |
7034 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
7035 | { int16_t src = m68k_read_memory_16(srca); | |
7036 | m68k_areg (regs, srcreg) = srca; | |
7037 | { CLEAR_CZNV; | |
7038 | SET_ZFLG (((int16_t)(src)) == 0); | |
7039 | SET_NFLG (((int16_t)(src)) < 0); | |
7040 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
7041 | }}}}m68k_incpc(2); | |
7042 | return 10; | |
7043 | } | |
7044 | unsigned long CPUFUNC(op_3028_4)(uint32_t opcode) /* MOVE */ | |
7045 | { | |
7046 | uint32_t srcreg = (opcode & 7); | |
7047 | uint32_t dstreg = (opcode >> 9) & 7; | |
7048 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
7049 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
7050 | { int16_t src = m68k_read_memory_16(srca); | |
7051 | { CLEAR_CZNV; | |
7052 | SET_ZFLG (((int16_t)(src)) == 0); | |
7053 | SET_NFLG (((int16_t)(src)) < 0); | |
7054 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
7055 | }}}}m68k_incpc(4); | |
7056 | return 12; | |
7057 | } | |
7058 | unsigned long CPUFUNC(op_3030_4)(uint32_t opcode) /* MOVE */ | |
7059 | { | |
7060 | uint32_t srcreg = (opcode & 7); | |
7061 | uint32_t dstreg = (opcode >> 9) & 7; | |
7062 | OpcodeFamily = 30; CurrentInstrCycles = 14; | |
7063 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
7064 | BusCyclePenalty += 2; | |
7065 | { int16_t src = m68k_read_memory_16(srca); | |
7066 | { CLEAR_CZNV; | |
7067 | SET_ZFLG (((int16_t)(src)) == 0); | |
7068 | SET_NFLG (((int16_t)(src)) < 0); | |
7069 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
7070 | }}}}m68k_incpc(4); | |
7071 | return 14; | |
7072 | } | |
7073 | unsigned long CPUFUNC(op_3038_4)(uint32_t opcode) /* MOVE */ | |
7074 | { | |
7075 | uint32_t dstreg = (opcode >> 9) & 7; | |
7076 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
7077 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
7078 | { int16_t src = m68k_read_memory_16(srca); | |
7079 | { CLEAR_CZNV; | |
7080 | SET_ZFLG (((int16_t)(src)) == 0); | |
7081 | SET_NFLG (((int16_t)(src)) < 0); | |
7082 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
7083 | }}}}m68k_incpc(4); | |
7084 | return 12; | |
7085 | } | |
7086 | unsigned long CPUFUNC(op_3039_4)(uint32_t opcode) /* MOVE */ | |
7087 | { | |
7088 | uint32_t dstreg = (opcode >> 9) & 7; | |
7089 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
7090 | {{ uint32_t srca = get_ilong(2); | |
7091 | { int16_t src = m68k_read_memory_16(srca); | |
7092 | { CLEAR_CZNV; | |
7093 | SET_ZFLG (((int16_t)(src)) == 0); | |
7094 | SET_NFLG (((int16_t)(src)) < 0); | |
7095 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
7096 | }}}}m68k_incpc(6); | |
7097 | return 16; | |
7098 | } | |
7099 | unsigned long CPUFUNC(op_303a_4)(uint32_t opcode) /* MOVE */ | |
7100 | { | |
7101 | uint32_t dstreg = (opcode >> 9) & 7; | |
7102 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
7103 | {{ uint32_t srca = m68k_getpc () + 2; | |
7104 | srca += (int32_t)(int16_t)get_iword(2); | |
7105 | { int16_t src = m68k_read_memory_16(srca); | |
7106 | { CLEAR_CZNV; | |
7107 | SET_ZFLG (((int16_t)(src)) == 0); | |
7108 | SET_NFLG (((int16_t)(src)) < 0); | |
7109 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
7110 | }}}}m68k_incpc(4); | |
7111 | return 12; | |
7112 | } | |
7113 | unsigned long CPUFUNC(op_303b_4)(uint32_t opcode) /* MOVE */ | |
7114 | { | |
7115 | uint32_t dstreg = (opcode >> 9) & 7; | |
7116 | OpcodeFamily = 30; CurrentInstrCycles = 14; | |
7117 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
7118 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
7119 | BusCyclePenalty += 2; | |
7120 | { int16_t src = m68k_read_memory_16(srca); | |
7121 | { CLEAR_CZNV; | |
7122 | SET_ZFLG (((int16_t)(src)) == 0); | |
7123 | SET_NFLG (((int16_t)(src)) < 0); | |
7124 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
7125 | }}}}m68k_incpc(4); | |
7126 | return 14; | |
7127 | } | |
7128 | unsigned long CPUFUNC(op_303c_4)(uint32_t opcode) /* MOVE */ | |
7129 | { | |
7130 | uint32_t dstreg = (opcode >> 9) & 7; | |
7131 | OpcodeFamily = 30; CurrentInstrCycles = 8; | |
7132 | {{ int16_t src = get_iword(2); | |
7133 | { CLEAR_CZNV; | |
7134 | SET_ZFLG (((int16_t)(src)) == 0); | |
7135 | SET_NFLG (((int16_t)(src)) < 0); | |
7136 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
7137 | }}}m68k_incpc(4); | |
7138 | return 8; | |
7139 | } | |
7140 | unsigned long CPUFUNC(op_3040_4)(uint32_t opcode) /* MOVEA */ | |
7141 | { | |
7142 | uint32_t srcreg = (opcode & 7); | |
7143 | uint32_t dstreg = (opcode >> 9) & 7; | |
7144 | OpcodeFamily = 31; CurrentInstrCycles = 4; | |
7145 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
7146 | { uint32_t val = (int32_t)(int16_t)src; | |
7147 | m68k_areg(regs, dstreg) = (val); | |
7148 | }}}m68k_incpc(2); | |
7149 | return 4; | |
7150 | } | |
7151 | unsigned long CPUFUNC(op_3048_4)(uint32_t opcode) /* MOVEA */ | |
7152 | { | |
7153 | uint32_t srcreg = (opcode & 7); | |
7154 | uint32_t dstreg = (opcode >> 9) & 7; | |
7155 | OpcodeFamily = 31; CurrentInstrCycles = 4; | |
7156 | {{ int16_t src = m68k_areg(regs, srcreg); | |
7157 | { uint32_t val = (int32_t)(int16_t)src; | |
7158 | m68k_areg(regs, dstreg) = (val); | |
7159 | }}}m68k_incpc(2); | |
7160 | return 4; | |
7161 | } | |
7162 | unsigned long CPUFUNC(op_3050_4)(uint32_t opcode) /* MOVEA */ | |
7163 | { | |
7164 | uint32_t srcreg = (opcode & 7); | |
7165 | uint32_t dstreg = (opcode >> 9) & 7; | |
7166 | OpcodeFamily = 31; CurrentInstrCycles = 8; | |
7167 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
7168 | { int16_t src = m68k_read_memory_16(srca); | |
7169 | { uint32_t val = (int32_t)(int16_t)src; | |
7170 | m68k_areg(regs, dstreg) = (val); | |
7171 | }}}}m68k_incpc(2); | |
7172 | return 8; | |
7173 | } | |
7174 | unsigned long CPUFUNC(op_3058_4)(uint32_t opcode) /* MOVEA */ | |
7175 | { | |
7176 | uint32_t srcreg = (opcode & 7); | |
7177 | uint32_t dstreg = (opcode >> 9) & 7; | |
7178 | OpcodeFamily = 31; CurrentInstrCycles = 8; | |
7179 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
7180 | { int16_t src = m68k_read_memory_16(srca); | |
7181 | m68k_areg(regs, srcreg) += 2; | |
7182 | { uint32_t val = (int32_t)(int16_t)src; | |
7183 | m68k_areg(regs, dstreg) = (val); | |
7184 | }}}}m68k_incpc(2); | |
7185 | return 8; | |
7186 | } | |
7187 | unsigned long CPUFUNC(op_3060_4)(uint32_t opcode) /* MOVEA */ | |
7188 | { | |
7189 | uint32_t srcreg = (opcode & 7); | |
7190 | uint32_t dstreg = (opcode >> 9) & 7; | |
7191 | OpcodeFamily = 31; CurrentInstrCycles = 10; | |
7192 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
7193 | { int16_t src = m68k_read_memory_16(srca); | |
7194 | m68k_areg (regs, srcreg) = srca; | |
7195 | { uint32_t val = (int32_t)(int16_t)src; | |
7196 | m68k_areg(regs, dstreg) = (val); | |
7197 | }}}}m68k_incpc(2); | |
7198 | return 10; | |
7199 | } | |
7200 | unsigned long CPUFUNC(op_3068_4)(uint32_t opcode) /* MOVEA */ | |
7201 | { | |
7202 | uint32_t srcreg = (opcode & 7); | |
7203 | uint32_t dstreg = (opcode >> 9) & 7; | |
7204 | OpcodeFamily = 31; CurrentInstrCycles = 12; | |
7205 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
7206 | { int16_t src = m68k_read_memory_16(srca); | |
7207 | { uint32_t val = (int32_t)(int16_t)src; | |
7208 | m68k_areg(regs, dstreg) = (val); | |
7209 | }}}}m68k_incpc(4); | |
7210 | return 12; | |
7211 | } | |
7212 | unsigned long CPUFUNC(op_3070_4)(uint32_t opcode) /* MOVEA */ | |
7213 | { | |
7214 | uint32_t srcreg = (opcode & 7); | |
7215 | uint32_t dstreg = (opcode >> 9) & 7; | |
7216 | OpcodeFamily = 31; CurrentInstrCycles = 14; | |
7217 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
7218 | BusCyclePenalty += 2; | |
7219 | { int16_t src = m68k_read_memory_16(srca); | |
7220 | { uint32_t val = (int32_t)(int16_t)src; | |
7221 | m68k_areg(regs, dstreg) = (val); | |
7222 | }}}}m68k_incpc(4); | |
7223 | return 14; | |
7224 | } | |
7225 | unsigned long CPUFUNC(op_3078_4)(uint32_t opcode) /* MOVEA */ | |
7226 | { | |
7227 | uint32_t dstreg = (opcode >> 9) & 7; | |
7228 | OpcodeFamily = 31; CurrentInstrCycles = 12; | |
7229 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
7230 | { int16_t src = m68k_read_memory_16(srca); | |
7231 | { uint32_t val = (int32_t)(int16_t)src; | |
7232 | m68k_areg(regs, dstreg) = (val); | |
7233 | }}}}m68k_incpc(4); | |
7234 | return 12; | |
7235 | } | |
7236 | unsigned long CPUFUNC(op_3079_4)(uint32_t opcode) /* MOVEA */ | |
7237 | { | |
7238 | uint32_t dstreg = (opcode >> 9) & 7; | |
7239 | OpcodeFamily = 31; CurrentInstrCycles = 16; | |
7240 | {{ uint32_t srca = get_ilong(2); | |
7241 | { int16_t src = m68k_read_memory_16(srca); | |
7242 | { uint32_t val = (int32_t)(int16_t)src; | |
7243 | m68k_areg(regs, dstreg) = (val); | |
7244 | }}}}m68k_incpc(6); | |
7245 | return 16; | |
7246 | } | |
7247 | unsigned long CPUFUNC(op_307a_4)(uint32_t opcode) /* MOVEA */ | |
7248 | { | |
7249 | uint32_t dstreg = (opcode >> 9) & 7; | |
7250 | OpcodeFamily = 31; CurrentInstrCycles = 12; | |
7251 | {{ uint32_t srca = m68k_getpc () + 2; | |
7252 | srca += (int32_t)(int16_t)get_iword(2); | |
7253 | { int16_t src = m68k_read_memory_16(srca); | |
7254 | { uint32_t val = (int32_t)(int16_t)src; | |
7255 | m68k_areg(regs, dstreg) = (val); | |
7256 | }}}}m68k_incpc(4); | |
7257 | return 12; | |
7258 | } | |
7259 | unsigned long CPUFUNC(op_307b_4)(uint32_t opcode) /* MOVEA */ | |
7260 | { | |
7261 | uint32_t dstreg = (opcode >> 9) & 7; | |
7262 | OpcodeFamily = 31; CurrentInstrCycles = 14; | |
7263 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
7264 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
7265 | BusCyclePenalty += 2; | |
7266 | { int16_t src = m68k_read_memory_16(srca); | |
7267 | { uint32_t val = (int32_t)(int16_t)src; | |
7268 | m68k_areg(regs, dstreg) = (val); | |
7269 | }}}}m68k_incpc(4); | |
7270 | return 14; | |
7271 | } | |
7272 | unsigned long CPUFUNC(op_307c_4)(uint32_t opcode) /* MOVEA */ | |
7273 | { | |
7274 | uint32_t dstreg = (opcode >> 9) & 7; | |
7275 | OpcodeFamily = 31; CurrentInstrCycles = 8; | |
7276 | {{ int16_t src = get_iword(2); | |
7277 | { uint32_t val = (int32_t)(int16_t)src; | |
7278 | m68k_areg(regs, dstreg) = (val); | |
7279 | }}}m68k_incpc(4); | |
7280 | return 8; | |
7281 | } | |
7282 | unsigned long CPUFUNC(op_3080_4)(uint32_t opcode) /* MOVE */ | |
7283 | { | |
7284 | uint32_t srcreg = (opcode & 7); | |
7285 | uint32_t dstreg = (opcode >> 9) & 7; | |
7286 | OpcodeFamily = 30; CurrentInstrCycles = 8; | |
7287 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
7288 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
7289 | CLEAR_CZNV; | |
7290 | SET_ZFLG (((int16_t)(src)) == 0); | |
7291 | SET_NFLG (((int16_t)(src)) < 0); | |
7292 | m68k_write_memory_16(dsta,src); | |
7293 | }}}m68k_incpc(2); | |
7294 | return 8; | |
7295 | } | |
7296 | unsigned long CPUFUNC(op_3088_4)(uint32_t opcode) /* MOVE */ | |
7297 | { | |
7298 | uint32_t srcreg = (opcode & 7); | |
7299 | uint32_t dstreg = (opcode >> 9) & 7; | |
7300 | OpcodeFamily = 30; CurrentInstrCycles = 8; | |
7301 | {{ int16_t src = m68k_areg(regs, srcreg); | |
7302 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
7303 | CLEAR_CZNV; | |
7304 | SET_ZFLG (((int16_t)(src)) == 0); | |
7305 | SET_NFLG (((int16_t)(src)) < 0); | |
7306 | m68k_write_memory_16(dsta,src); | |
7307 | }}}m68k_incpc(2); | |
7308 | return 8; | |
7309 | } | |
7310 | unsigned long CPUFUNC(op_3090_4)(uint32_t opcode) /* MOVE */ | |
7311 | { | |
7312 | uint32_t srcreg = (opcode & 7); | |
7313 | uint32_t dstreg = (opcode >> 9) & 7; | |
7314 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
7315 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
7316 | { int16_t src = m68k_read_memory_16(srca); | |
7317 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
7318 | CLEAR_CZNV; | |
7319 | SET_ZFLG (((int16_t)(src)) == 0); | |
7320 | SET_NFLG (((int16_t)(src)) < 0); | |
7321 | m68k_write_memory_16(dsta,src); | |
7322 | }}}}m68k_incpc(2); | |
7323 | return 12; | |
7324 | } | |
7325 | unsigned long CPUFUNC(op_3098_4)(uint32_t opcode) /* MOVE */ | |
7326 | { | |
7327 | uint32_t srcreg = (opcode & 7); | |
7328 | uint32_t dstreg = (opcode >> 9) & 7; | |
7329 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
7330 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
7331 | { int16_t src = m68k_read_memory_16(srca); | |
7332 | m68k_areg(regs, srcreg) += 2; | |
7333 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
7334 | CLEAR_CZNV; | |
7335 | SET_ZFLG (((int16_t)(src)) == 0); | |
7336 | SET_NFLG (((int16_t)(src)) < 0); | |
7337 | m68k_write_memory_16(dsta,src); | |
7338 | }}}}m68k_incpc(2); | |
7339 | return 12; | |
7340 | } | |
7341 | unsigned long CPUFUNC(op_30a0_4)(uint32_t opcode) /* MOVE */ | |
7342 | { | |
7343 | uint32_t srcreg = (opcode & 7); | |
7344 | uint32_t dstreg = (opcode >> 9) & 7; | |
7345 | OpcodeFamily = 30; CurrentInstrCycles = 14; | |
7346 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
7347 | { int16_t src = m68k_read_memory_16(srca); | |
7348 | m68k_areg (regs, srcreg) = srca; | |
7349 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
7350 | CLEAR_CZNV; | |
7351 | SET_ZFLG (((int16_t)(src)) == 0); | |
7352 | SET_NFLG (((int16_t)(src)) < 0); | |
7353 | m68k_write_memory_16(dsta,src); | |
7354 | }}}}m68k_incpc(2); | |
7355 | return 14; | |
7356 | } | |
7357 | unsigned long CPUFUNC(op_30a8_4)(uint32_t opcode) /* MOVE */ | |
7358 | { | |
7359 | uint32_t srcreg = (opcode & 7); | |
7360 | uint32_t dstreg = (opcode >> 9) & 7; | |
7361 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
7362 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
7363 | { int16_t src = m68k_read_memory_16(srca); | |
7364 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
7365 | CLEAR_CZNV; | |
7366 | SET_ZFLG (((int16_t)(src)) == 0); | |
7367 | SET_NFLG (((int16_t)(src)) < 0); | |
7368 | m68k_write_memory_16(dsta,src); | |
7369 | }}}}m68k_incpc(4); | |
7370 | return 16; | |
7371 | } | |
7372 | unsigned long CPUFUNC(op_30b0_4)(uint32_t opcode) /* MOVE */ | |
7373 | { | |
7374 | uint32_t srcreg = (opcode & 7); | |
7375 | uint32_t dstreg = (opcode >> 9) & 7; | |
7376 | OpcodeFamily = 30; CurrentInstrCycles = 18; | |
7377 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
7378 | BusCyclePenalty += 2; | |
7379 | { int16_t src = m68k_read_memory_16(srca); | |
7380 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
7381 | CLEAR_CZNV; | |
7382 | SET_ZFLG (((int16_t)(src)) == 0); | |
7383 | SET_NFLG (((int16_t)(src)) < 0); | |
7384 | m68k_write_memory_16(dsta,src); | |
7385 | }}}}m68k_incpc(4); | |
7386 | return 18; | |
7387 | } | |
7388 | unsigned long CPUFUNC(op_30b8_4)(uint32_t opcode) /* MOVE */ | |
7389 | { | |
7390 | uint32_t dstreg = (opcode >> 9) & 7; | |
7391 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
7392 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
7393 | { int16_t src = m68k_read_memory_16(srca); | |
7394 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
7395 | CLEAR_CZNV; | |
7396 | SET_ZFLG (((int16_t)(src)) == 0); | |
7397 | SET_NFLG (((int16_t)(src)) < 0); | |
7398 | m68k_write_memory_16(dsta,src); | |
7399 | }}}}m68k_incpc(4); | |
7400 | return 16; | |
7401 | } | |
7402 | unsigned long CPUFUNC(op_30b9_4)(uint32_t opcode) /* MOVE */ | |
7403 | { | |
7404 | uint32_t dstreg = (opcode >> 9) & 7; | |
7405 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
7406 | {{ uint32_t srca = get_ilong(2); | |
7407 | { int16_t src = m68k_read_memory_16(srca); | |
7408 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
7409 | CLEAR_CZNV; | |
7410 | SET_ZFLG (((int16_t)(src)) == 0); | |
7411 | SET_NFLG (((int16_t)(src)) < 0); | |
7412 | m68k_write_memory_16(dsta,src); | |
7413 | }}}}m68k_incpc(6); | |
7414 | return 20; | |
7415 | } | |
7416 | unsigned long CPUFUNC(op_30ba_4)(uint32_t opcode) /* MOVE */ | |
7417 | { | |
7418 | uint32_t dstreg = (opcode >> 9) & 7; | |
7419 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
7420 | {{ uint32_t srca = m68k_getpc () + 2; | |
7421 | srca += (int32_t)(int16_t)get_iword(2); | |
7422 | { int16_t src = m68k_read_memory_16(srca); | |
7423 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
7424 | CLEAR_CZNV; | |
7425 | SET_ZFLG (((int16_t)(src)) == 0); | |
7426 | SET_NFLG (((int16_t)(src)) < 0); | |
7427 | m68k_write_memory_16(dsta,src); | |
7428 | }}}}m68k_incpc(4); | |
7429 | return 16; | |
7430 | } | |
7431 | unsigned long CPUFUNC(op_30bb_4)(uint32_t opcode) /* MOVE */ | |
7432 | { | |
7433 | uint32_t dstreg = (opcode >> 9) & 7; | |
7434 | OpcodeFamily = 30; CurrentInstrCycles = 18; | |
7435 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
7436 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
7437 | BusCyclePenalty += 2; | |
7438 | { int16_t src = m68k_read_memory_16(srca); | |
7439 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
7440 | CLEAR_CZNV; | |
7441 | SET_ZFLG (((int16_t)(src)) == 0); | |
7442 | SET_NFLG (((int16_t)(src)) < 0); | |
7443 | m68k_write_memory_16(dsta,src); | |
7444 | }}}}m68k_incpc(4); | |
7445 | return 18; | |
7446 | } | |
7447 | unsigned long CPUFUNC(op_30bc_4)(uint32_t opcode) /* MOVE */ | |
7448 | { | |
7449 | uint32_t dstreg = (opcode >> 9) & 7; | |
7450 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
7451 | {{ int16_t src = get_iword(2); | |
7452 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
7453 | CLEAR_CZNV; | |
7454 | SET_ZFLG (((int16_t)(src)) == 0); | |
7455 | SET_NFLG (((int16_t)(src)) < 0); | |
7456 | m68k_write_memory_16(dsta,src); | |
7457 | }}}m68k_incpc(4); | |
7458 | return 12; | |
7459 | } | |
7460 | unsigned long CPUFUNC(op_30c0_4)(uint32_t opcode) /* MOVE */ | |
7461 | { | |
7462 | uint32_t srcreg = (opcode & 7); | |
7463 | uint32_t dstreg = (opcode >> 9) & 7; | |
7464 | OpcodeFamily = 30; CurrentInstrCycles = 8; | |
7465 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
7466 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
7467 | m68k_areg(regs, dstreg) += 2; | |
7468 | CLEAR_CZNV; | |
7469 | SET_ZFLG (((int16_t)(src)) == 0); | |
7470 | SET_NFLG (((int16_t)(src)) < 0); | |
7471 | m68k_write_memory_16(dsta,src); | |
7472 | }}}m68k_incpc(2); | |
7473 | return 8; | |
7474 | } | |
7475 | unsigned long CPUFUNC(op_30c8_4)(uint32_t opcode) /* MOVE */ | |
7476 | { | |
7477 | uint32_t srcreg = (opcode & 7); | |
7478 | uint32_t dstreg = (opcode >> 9) & 7; | |
7479 | OpcodeFamily = 30; CurrentInstrCycles = 8; | |
7480 | {{ int16_t src = m68k_areg(regs, srcreg); | |
7481 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
7482 | m68k_areg(regs, dstreg) += 2; | |
7483 | CLEAR_CZNV; | |
7484 | SET_ZFLG (((int16_t)(src)) == 0); | |
7485 | SET_NFLG (((int16_t)(src)) < 0); | |
7486 | m68k_write_memory_16(dsta,src); | |
7487 | }}}m68k_incpc(2); | |
7488 | return 8; | |
7489 | } | |
7490 | unsigned long CPUFUNC(op_30d0_4)(uint32_t opcode) /* MOVE */ | |
7491 | { | |
7492 | uint32_t srcreg = (opcode & 7); | |
7493 | uint32_t dstreg = (opcode >> 9) & 7; | |
7494 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
7495 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
7496 | { int16_t src = m68k_read_memory_16(srca); | |
7497 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
7498 | m68k_areg(regs, dstreg) += 2; | |
7499 | CLEAR_CZNV; | |
7500 | SET_ZFLG (((int16_t)(src)) == 0); | |
7501 | SET_NFLG (((int16_t)(src)) < 0); | |
7502 | m68k_write_memory_16(dsta,src); | |
7503 | }}}}m68k_incpc(2); | |
7504 | return 12; | |
7505 | } | |
7506 | unsigned long CPUFUNC(op_30d8_4)(uint32_t opcode) /* MOVE */ | |
7507 | { | |
7508 | uint32_t srcreg = (opcode & 7); | |
7509 | uint32_t dstreg = (opcode >> 9) & 7; | |
7510 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
7511 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
7512 | { int16_t src = m68k_read_memory_16(srca); | |
7513 | m68k_areg(regs, srcreg) += 2; | |
7514 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
7515 | m68k_areg(regs, dstreg) += 2; | |
7516 | CLEAR_CZNV; | |
7517 | SET_ZFLG (((int16_t)(src)) == 0); | |
7518 | SET_NFLG (((int16_t)(src)) < 0); | |
7519 | m68k_write_memory_16(dsta,src); | |
7520 | }}}}m68k_incpc(2); | |
7521 | return 12; | |
7522 | } | |
7523 | unsigned long CPUFUNC(op_30e0_4)(uint32_t opcode) /* MOVE */ | |
7524 | { | |
7525 | uint32_t srcreg = (opcode & 7); | |
7526 | uint32_t dstreg = (opcode >> 9) & 7; | |
7527 | OpcodeFamily = 30; CurrentInstrCycles = 14; | |
7528 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
7529 | { int16_t src = m68k_read_memory_16(srca); | |
7530 | m68k_areg (regs, srcreg) = srca; | |
7531 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
7532 | m68k_areg(regs, dstreg) += 2; | |
7533 | CLEAR_CZNV; | |
7534 | SET_ZFLG (((int16_t)(src)) == 0); | |
7535 | SET_NFLG (((int16_t)(src)) < 0); | |
7536 | m68k_write_memory_16(dsta,src); | |
7537 | }}}}m68k_incpc(2); | |
7538 | return 14; | |
7539 | } | |
7540 | unsigned long CPUFUNC(op_30e8_4)(uint32_t opcode) /* MOVE */ | |
7541 | { | |
7542 | uint32_t srcreg = (opcode & 7); | |
7543 | uint32_t dstreg = (opcode >> 9) & 7; | |
7544 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
7545 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
7546 | { int16_t src = m68k_read_memory_16(srca); | |
7547 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
7548 | m68k_areg(regs, dstreg) += 2; | |
7549 | CLEAR_CZNV; | |
7550 | SET_ZFLG (((int16_t)(src)) == 0); | |
7551 | SET_NFLG (((int16_t)(src)) < 0); | |
7552 | m68k_write_memory_16(dsta,src); | |
7553 | }}}}m68k_incpc(4); | |
7554 | return 16; | |
7555 | } | |
7556 | unsigned long CPUFUNC(op_30f0_4)(uint32_t opcode) /* MOVE */ | |
7557 | { | |
7558 | uint32_t srcreg = (opcode & 7); | |
7559 | uint32_t dstreg = (opcode >> 9) & 7; | |
7560 | OpcodeFamily = 30; CurrentInstrCycles = 18; | |
7561 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
7562 | BusCyclePenalty += 2; | |
7563 | { int16_t src = m68k_read_memory_16(srca); | |
7564 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
7565 | m68k_areg(regs, dstreg) += 2; | |
7566 | CLEAR_CZNV; | |
7567 | SET_ZFLG (((int16_t)(src)) == 0); | |
7568 | SET_NFLG (((int16_t)(src)) < 0); | |
7569 | m68k_write_memory_16(dsta,src); | |
7570 | }}}}m68k_incpc(4); | |
7571 | return 18; | |
7572 | } | |
7573 | unsigned long CPUFUNC(op_30f8_4)(uint32_t opcode) /* MOVE */ | |
7574 | { | |
7575 | uint32_t dstreg = (opcode >> 9) & 7; | |
7576 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
7577 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
7578 | { int16_t src = m68k_read_memory_16(srca); | |
7579 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
7580 | m68k_areg(regs, dstreg) += 2; | |
7581 | CLEAR_CZNV; | |
7582 | SET_ZFLG (((int16_t)(src)) == 0); | |
7583 | SET_NFLG (((int16_t)(src)) < 0); | |
7584 | m68k_write_memory_16(dsta,src); | |
7585 | }}}}m68k_incpc(4); | |
7586 | return 16; | |
7587 | } | |
7588 | unsigned long CPUFUNC(op_30f9_4)(uint32_t opcode) /* MOVE */ | |
7589 | { | |
7590 | uint32_t dstreg = (opcode >> 9) & 7; | |
7591 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
7592 | {{ uint32_t srca = get_ilong(2); | |
7593 | { int16_t src = m68k_read_memory_16(srca); | |
7594 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
7595 | m68k_areg(regs, dstreg) += 2; | |
7596 | CLEAR_CZNV; | |
7597 | SET_ZFLG (((int16_t)(src)) == 0); | |
7598 | SET_NFLG (((int16_t)(src)) < 0); | |
7599 | m68k_write_memory_16(dsta,src); | |
7600 | }}}}m68k_incpc(6); | |
7601 | return 20; | |
7602 | } | |
7603 | unsigned long CPUFUNC(op_30fa_4)(uint32_t opcode) /* MOVE */ | |
7604 | { | |
7605 | uint32_t dstreg = (opcode >> 9) & 7; | |
7606 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
7607 | {{ uint32_t srca = m68k_getpc () + 2; | |
7608 | srca += (int32_t)(int16_t)get_iword(2); | |
7609 | { int16_t src = m68k_read_memory_16(srca); | |
7610 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
7611 | m68k_areg(regs, dstreg) += 2; | |
7612 | CLEAR_CZNV; | |
7613 | SET_ZFLG (((int16_t)(src)) == 0); | |
7614 | SET_NFLG (((int16_t)(src)) < 0); | |
7615 | m68k_write_memory_16(dsta,src); | |
7616 | }}}}m68k_incpc(4); | |
7617 | return 16; | |
7618 | } | |
7619 | unsigned long CPUFUNC(op_30fb_4)(uint32_t opcode) /* MOVE */ | |
7620 | { | |
7621 | uint32_t dstreg = (opcode >> 9) & 7; | |
7622 | OpcodeFamily = 30; CurrentInstrCycles = 18; | |
7623 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
7624 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
7625 | BusCyclePenalty += 2; | |
7626 | { int16_t src = m68k_read_memory_16(srca); | |
7627 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
7628 | m68k_areg(regs, dstreg) += 2; | |
7629 | CLEAR_CZNV; | |
7630 | SET_ZFLG (((int16_t)(src)) == 0); | |
7631 | SET_NFLG (((int16_t)(src)) < 0); | |
7632 | m68k_write_memory_16(dsta,src); | |
7633 | }}}}m68k_incpc(4); | |
7634 | return 18; | |
7635 | } | |
7636 | unsigned long CPUFUNC(op_30fc_4)(uint32_t opcode) /* MOVE */ | |
7637 | { | |
7638 | uint32_t dstreg = (opcode >> 9) & 7; | |
7639 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
7640 | {{ int16_t src = get_iword(2); | |
7641 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
7642 | m68k_areg(regs, dstreg) += 2; | |
7643 | CLEAR_CZNV; | |
7644 | SET_ZFLG (((int16_t)(src)) == 0); | |
7645 | SET_NFLG (((int16_t)(src)) < 0); | |
7646 | m68k_write_memory_16(dsta,src); | |
7647 | }}}m68k_incpc(4); | |
7648 | return 12; | |
7649 | } | |
7650 | unsigned long CPUFUNC(op_3100_4)(uint32_t opcode) /* MOVE */ | |
7651 | { | |
7652 | uint32_t srcreg = (opcode & 7); | |
7653 | uint32_t dstreg = (opcode >> 9) & 7; | |
7654 | OpcodeFamily = 30; CurrentInstrCycles = 8; | |
7655 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
7656 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
7657 | m68k_areg (regs, dstreg) = dsta; | |
7658 | CLEAR_CZNV; | |
7659 | SET_ZFLG (((int16_t)(src)) == 0); | |
7660 | SET_NFLG (((int16_t)(src)) < 0); | |
7661 | m68k_write_memory_16(dsta,src); | |
7662 | }}}m68k_incpc(2); | |
7663 | return 8; | |
7664 | } | |
7665 | unsigned long CPUFUNC(op_3108_4)(uint32_t opcode) /* MOVE */ | |
7666 | { | |
7667 | uint32_t srcreg = (opcode & 7); | |
7668 | uint32_t dstreg = (opcode >> 9) & 7; | |
7669 | OpcodeFamily = 30; CurrentInstrCycles = 8; | |
7670 | {{ int16_t src = m68k_areg(regs, srcreg); | |
7671 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
7672 | m68k_areg (regs, dstreg) = dsta; | |
7673 | CLEAR_CZNV; | |
7674 | SET_ZFLG (((int16_t)(src)) == 0); | |
7675 | SET_NFLG (((int16_t)(src)) < 0); | |
7676 | m68k_write_memory_16(dsta,src); | |
7677 | }}}m68k_incpc(2); | |
7678 | return 8; | |
7679 | } | |
7680 | unsigned long CPUFUNC(op_3110_4)(uint32_t opcode) /* MOVE */ | |
7681 | { | |
7682 | uint32_t srcreg = (opcode & 7); | |
7683 | uint32_t dstreg = (opcode >> 9) & 7; | |
7684 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
7685 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
7686 | { int16_t src = m68k_read_memory_16(srca); | |
7687 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
7688 | m68k_areg (regs, dstreg) = dsta; | |
7689 | CLEAR_CZNV; | |
7690 | SET_ZFLG (((int16_t)(src)) == 0); | |
7691 | SET_NFLG (((int16_t)(src)) < 0); | |
7692 | m68k_write_memory_16(dsta,src); | |
7693 | }}}}m68k_incpc(2); | |
7694 | return 12; | |
7695 | } | |
7696 | unsigned long CPUFUNC(op_3118_4)(uint32_t opcode) /* MOVE */ | |
7697 | { | |
7698 | uint32_t srcreg = (opcode & 7); | |
7699 | uint32_t dstreg = (opcode >> 9) & 7; | |
7700 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
7701 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
7702 | { int16_t src = m68k_read_memory_16(srca); | |
7703 | m68k_areg(regs, srcreg) += 2; | |
7704 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
7705 | m68k_areg (regs, dstreg) = dsta; | |
7706 | CLEAR_CZNV; | |
7707 | SET_ZFLG (((int16_t)(src)) == 0); | |
7708 | SET_NFLG (((int16_t)(src)) < 0); | |
7709 | m68k_write_memory_16(dsta,src); | |
7710 | }}}}m68k_incpc(2); | |
7711 | return 12; | |
7712 | } | |
7713 | unsigned long CPUFUNC(op_3120_4)(uint32_t opcode) /* MOVE */ | |
7714 | { | |
7715 | uint32_t srcreg = (opcode & 7); | |
7716 | uint32_t dstreg = (opcode >> 9) & 7; | |
7717 | OpcodeFamily = 30; CurrentInstrCycles = 14; | |
7718 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
7719 | { int16_t src = m68k_read_memory_16(srca); | |
7720 | m68k_areg (regs, srcreg) = srca; | |
7721 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
7722 | m68k_areg (regs, dstreg) = dsta; | |
7723 | CLEAR_CZNV; | |
7724 | SET_ZFLG (((int16_t)(src)) == 0); | |
7725 | SET_NFLG (((int16_t)(src)) < 0); | |
7726 | m68k_write_memory_16(dsta,src); | |
7727 | }}}}m68k_incpc(2); | |
7728 | return 14; | |
7729 | } | |
7730 | unsigned long CPUFUNC(op_3128_4)(uint32_t opcode) /* MOVE */ | |
7731 | { | |
7732 | uint32_t srcreg = (opcode & 7); | |
7733 | uint32_t dstreg = (opcode >> 9) & 7; | |
7734 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
7735 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
7736 | { int16_t src = m68k_read_memory_16(srca); | |
7737 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
7738 | m68k_areg (regs, dstreg) = dsta; | |
7739 | CLEAR_CZNV; | |
7740 | SET_ZFLG (((int16_t)(src)) == 0); | |
7741 | SET_NFLG (((int16_t)(src)) < 0); | |
7742 | m68k_write_memory_16(dsta,src); | |
7743 | }}}}m68k_incpc(4); | |
7744 | return 16; | |
7745 | } | |
7746 | unsigned long CPUFUNC(op_3130_4)(uint32_t opcode) /* MOVE */ | |
7747 | { | |
7748 | uint32_t srcreg = (opcode & 7); | |
7749 | uint32_t dstreg = (opcode >> 9) & 7; | |
7750 | OpcodeFamily = 30; CurrentInstrCycles = 18; | |
7751 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
7752 | BusCyclePenalty += 2; | |
7753 | { int16_t src = m68k_read_memory_16(srca); | |
7754 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
7755 | m68k_areg (regs, dstreg) = dsta; | |
7756 | CLEAR_CZNV; | |
7757 | SET_ZFLG (((int16_t)(src)) == 0); | |
7758 | SET_NFLG (((int16_t)(src)) < 0); | |
7759 | m68k_write_memory_16(dsta,src); | |
7760 | }}}}m68k_incpc(4); | |
7761 | return 18; | |
7762 | } | |
7763 | unsigned long CPUFUNC(op_3138_4)(uint32_t opcode) /* MOVE */ | |
7764 | { | |
7765 | uint32_t dstreg = (opcode >> 9) & 7; | |
7766 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
7767 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
7768 | { int16_t src = m68k_read_memory_16(srca); | |
7769 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
7770 | m68k_areg (regs, dstreg) = dsta; | |
7771 | CLEAR_CZNV; | |
7772 | SET_ZFLG (((int16_t)(src)) == 0); | |
7773 | SET_NFLG (((int16_t)(src)) < 0); | |
7774 | m68k_write_memory_16(dsta,src); | |
7775 | }}}}m68k_incpc(4); | |
7776 | return 16; | |
7777 | } | |
7778 | unsigned long CPUFUNC(op_3139_4)(uint32_t opcode) /* MOVE */ | |
7779 | { | |
7780 | uint32_t dstreg = (opcode >> 9) & 7; | |
7781 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
7782 | {{ uint32_t srca = get_ilong(2); | |
7783 | { int16_t src = m68k_read_memory_16(srca); | |
7784 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
7785 | m68k_areg (regs, dstreg) = dsta; | |
7786 | CLEAR_CZNV; | |
7787 | SET_ZFLG (((int16_t)(src)) == 0); | |
7788 | SET_NFLG (((int16_t)(src)) < 0); | |
7789 | m68k_write_memory_16(dsta,src); | |
7790 | }}}}m68k_incpc(6); | |
7791 | return 20; | |
7792 | } | |
7793 | unsigned long CPUFUNC(op_313a_4)(uint32_t opcode) /* MOVE */ | |
7794 | { | |
7795 | uint32_t dstreg = (opcode >> 9) & 7; | |
7796 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
7797 | {{ uint32_t srca = m68k_getpc () + 2; | |
7798 | srca += (int32_t)(int16_t)get_iword(2); | |
7799 | { int16_t src = m68k_read_memory_16(srca); | |
7800 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
7801 | m68k_areg (regs, dstreg) = dsta; | |
7802 | CLEAR_CZNV; | |
7803 | SET_ZFLG (((int16_t)(src)) == 0); | |
7804 | SET_NFLG (((int16_t)(src)) < 0); | |
7805 | m68k_write_memory_16(dsta,src); | |
7806 | }}}}m68k_incpc(4); | |
7807 | return 16; | |
7808 | } | |
7809 | unsigned long CPUFUNC(op_313b_4)(uint32_t opcode) /* MOVE */ | |
7810 | { | |
7811 | uint32_t dstreg = (opcode >> 9) & 7; | |
7812 | OpcodeFamily = 30; CurrentInstrCycles = 18; | |
7813 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
7814 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
7815 | BusCyclePenalty += 2; | |
7816 | { int16_t src = m68k_read_memory_16(srca); | |
7817 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
7818 | m68k_areg (regs, dstreg) = dsta; | |
7819 | CLEAR_CZNV; | |
7820 | SET_ZFLG (((int16_t)(src)) == 0); | |
7821 | SET_NFLG (((int16_t)(src)) < 0); | |
7822 | m68k_write_memory_16(dsta,src); | |
7823 | }}}}m68k_incpc(4); | |
7824 | return 18; | |
7825 | } | |
7826 | unsigned long CPUFUNC(op_313c_4)(uint32_t opcode) /* MOVE */ | |
7827 | { | |
7828 | uint32_t dstreg = (opcode >> 9) & 7; | |
7829 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
7830 | {{ int16_t src = get_iword(2); | |
7831 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
7832 | m68k_areg (regs, dstreg) = dsta; | |
7833 | CLEAR_CZNV; | |
7834 | SET_ZFLG (((int16_t)(src)) == 0); | |
7835 | SET_NFLG (((int16_t)(src)) < 0); | |
7836 | m68k_write_memory_16(dsta,src); | |
7837 | }}}m68k_incpc(4); | |
7838 | return 12; | |
7839 | } | |
7840 | unsigned long CPUFUNC(op_3140_4)(uint32_t opcode) /* MOVE */ | |
7841 | { | |
7842 | uint32_t srcreg = (opcode & 7); | |
7843 | uint32_t dstreg = (opcode >> 9) & 7; | |
7844 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
7845 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
7846 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); | |
7847 | CLEAR_CZNV; | |
7848 | SET_ZFLG (((int16_t)(src)) == 0); | |
7849 | SET_NFLG (((int16_t)(src)) < 0); | |
7850 | m68k_write_memory_16(dsta,src); | |
7851 | }}}m68k_incpc(4); | |
7852 | return 12; | |
7853 | } | |
7854 | unsigned long CPUFUNC(op_3148_4)(uint32_t opcode) /* MOVE */ | |
7855 | { | |
7856 | uint32_t srcreg = (opcode & 7); | |
7857 | uint32_t dstreg = (opcode >> 9) & 7; | |
7858 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
7859 | {{ int16_t src = m68k_areg(regs, srcreg); | |
7860 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); | |
7861 | CLEAR_CZNV; | |
7862 | SET_ZFLG (((int16_t)(src)) == 0); | |
7863 | SET_NFLG (((int16_t)(src)) < 0); | |
7864 | m68k_write_memory_16(dsta,src); | |
7865 | }}}m68k_incpc(4); | |
7866 | return 12; | |
7867 | } | |
7868 | unsigned long CPUFUNC(op_3150_4)(uint32_t opcode) /* MOVE */ | |
7869 | { | |
7870 | uint32_t srcreg = (opcode & 7); | |
7871 | uint32_t dstreg = (opcode >> 9) & 7; | |
7872 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
7873 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
7874 | { int16_t src = m68k_read_memory_16(srca); | |
7875 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); | |
7876 | CLEAR_CZNV; | |
7877 | SET_ZFLG (((int16_t)(src)) == 0); | |
7878 | SET_NFLG (((int16_t)(src)) < 0); | |
7879 | m68k_write_memory_16(dsta,src); | |
7880 | }}}}m68k_incpc(4); | |
7881 | return 16; | |
7882 | } | |
7883 | unsigned long CPUFUNC(op_3158_4)(uint32_t opcode) /* MOVE */ | |
7884 | { | |
7885 | uint32_t srcreg = (opcode & 7); | |
7886 | uint32_t dstreg = (opcode >> 9) & 7; | |
7887 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
7888 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
7889 | { int16_t src = m68k_read_memory_16(srca); | |
7890 | m68k_areg(regs, srcreg) += 2; | |
7891 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); | |
7892 | CLEAR_CZNV; | |
7893 | SET_ZFLG (((int16_t)(src)) == 0); | |
7894 | SET_NFLG (((int16_t)(src)) < 0); | |
7895 | m68k_write_memory_16(dsta,src); | |
7896 | }}}}m68k_incpc(4); | |
7897 | return 16; | |
7898 | } | |
7899 | unsigned long CPUFUNC(op_3160_4)(uint32_t opcode) /* MOVE */ | |
7900 | { | |
7901 | uint32_t srcreg = (opcode & 7); | |
7902 | uint32_t dstreg = (opcode >> 9) & 7; | |
7903 | OpcodeFamily = 30; CurrentInstrCycles = 18; | |
7904 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
7905 | { int16_t src = m68k_read_memory_16(srca); | |
7906 | m68k_areg (regs, srcreg) = srca; | |
7907 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); | |
7908 | CLEAR_CZNV; | |
7909 | SET_ZFLG (((int16_t)(src)) == 0); | |
7910 | SET_NFLG (((int16_t)(src)) < 0); | |
7911 | m68k_write_memory_16(dsta,src); | |
7912 | }}}}m68k_incpc(4); | |
7913 | return 18; | |
7914 | } | |
7915 | unsigned long CPUFUNC(op_3168_4)(uint32_t opcode) /* MOVE */ | |
7916 | { | |
7917 | uint32_t srcreg = (opcode & 7); | |
7918 | uint32_t dstreg = (opcode >> 9) & 7; | |
7919 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
7920 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
7921 | { int16_t src = m68k_read_memory_16(srca); | |
7922 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); | |
7923 | CLEAR_CZNV; | |
7924 | SET_ZFLG (((int16_t)(src)) == 0); | |
7925 | SET_NFLG (((int16_t)(src)) < 0); | |
7926 | m68k_write_memory_16(dsta,src); | |
7927 | }}}}m68k_incpc(6); | |
7928 | return 20; | |
7929 | } | |
7930 | unsigned long CPUFUNC(op_3170_4)(uint32_t opcode) /* MOVE */ | |
7931 | { | |
7932 | uint32_t srcreg = (opcode & 7); | |
7933 | uint32_t dstreg = (opcode >> 9) & 7; | |
7934 | OpcodeFamily = 30; CurrentInstrCycles = 22; | |
7935 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
7936 | BusCyclePenalty += 2; | |
7937 | { int16_t src = m68k_read_memory_16(srca); | |
7938 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); | |
7939 | CLEAR_CZNV; | |
7940 | SET_ZFLG (((int16_t)(src)) == 0); | |
7941 | SET_NFLG (((int16_t)(src)) < 0); | |
7942 | m68k_write_memory_16(dsta,src); | |
7943 | }}}}m68k_incpc(6); | |
7944 | return 22; | |
7945 | } | |
7946 | unsigned long CPUFUNC(op_3178_4)(uint32_t opcode) /* MOVE */ | |
7947 | { | |
7948 | uint32_t dstreg = (opcode >> 9) & 7; | |
7949 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
7950 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
7951 | { int16_t src = m68k_read_memory_16(srca); | |
7952 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); | |
7953 | CLEAR_CZNV; | |
7954 | SET_ZFLG (((int16_t)(src)) == 0); | |
7955 | SET_NFLG (((int16_t)(src)) < 0); | |
7956 | m68k_write_memory_16(dsta,src); | |
7957 | }}}}m68k_incpc(6); | |
7958 | return 20; | |
7959 | } | |
7960 | unsigned long CPUFUNC(op_3179_4)(uint32_t opcode) /* MOVE */ | |
7961 | { | |
7962 | uint32_t dstreg = (opcode >> 9) & 7; | |
7963 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
7964 | {{ uint32_t srca = get_ilong(2); | |
7965 | { int16_t src = m68k_read_memory_16(srca); | |
7966 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(6); | |
7967 | CLEAR_CZNV; | |
7968 | SET_ZFLG (((int16_t)(src)) == 0); | |
7969 | SET_NFLG (((int16_t)(src)) < 0); | |
7970 | m68k_write_memory_16(dsta,src); | |
7971 | }}}}m68k_incpc(8); | |
7972 | return 24; | |
7973 | } | |
7974 | unsigned long CPUFUNC(op_317a_4)(uint32_t opcode) /* MOVE */ | |
7975 | { | |
7976 | uint32_t dstreg = (opcode >> 9) & 7; | |
7977 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
7978 | {{ uint32_t srca = m68k_getpc () + 2; | |
7979 | srca += (int32_t)(int16_t)get_iword(2); | |
7980 | { int16_t src = m68k_read_memory_16(srca); | |
7981 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); | |
7982 | CLEAR_CZNV; | |
7983 | SET_ZFLG (((int16_t)(src)) == 0); | |
7984 | SET_NFLG (((int16_t)(src)) < 0); | |
7985 | m68k_write_memory_16(dsta,src); | |
7986 | }}}}m68k_incpc(6); | |
7987 | return 20; | |
7988 | } | |
7989 | unsigned long CPUFUNC(op_317b_4)(uint32_t opcode) /* MOVE */ | |
7990 | { | |
7991 | uint32_t dstreg = (opcode >> 9) & 7; | |
7992 | OpcodeFamily = 30; CurrentInstrCycles = 22; | |
7993 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
7994 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
7995 | BusCyclePenalty += 2; | |
7996 | { int16_t src = m68k_read_memory_16(srca); | |
7997 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); | |
7998 | CLEAR_CZNV; | |
7999 | SET_ZFLG (((int16_t)(src)) == 0); | |
8000 | SET_NFLG (((int16_t)(src)) < 0); | |
8001 | m68k_write_memory_16(dsta,src); | |
8002 | }}}}m68k_incpc(6); | |
8003 | return 22; | |
8004 | } | |
8005 | unsigned long CPUFUNC(op_317c_4)(uint32_t opcode) /* MOVE */ | |
8006 | { | |
8007 | uint32_t dstreg = (opcode >> 9) & 7; | |
8008 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
8009 | {{ int16_t src = get_iword(2); | |
8010 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); | |
8011 | CLEAR_CZNV; | |
8012 | SET_ZFLG (((int16_t)(src)) == 0); | |
8013 | SET_NFLG (((int16_t)(src)) < 0); | |
8014 | m68k_write_memory_16(dsta,src); | |
8015 | }}}m68k_incpc(6); | |
8016 | return 16; | |
8017 | } | |
8018 | unsigned long CPUFUNC(op_3180_4)(uint32_t opcode) /* MOVE */ | |
8019 | { | |
8020 | uint32_t srcreg = (opcode & 7); | |
8021 | uint32_t dstreg = (opcode >> 9) & 7; | |
8022 | OpcodeFamily = 30; CurrentInstrCycles = 14; | |
8023 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
8024 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); | |
8025 | BusCyclePenalty += 2; | |
8026 | CLEAR_CZNV; | |
8027 | SET_ZFLG (((int16_t)(src)) == 0); | |
8028 | SET_NFLG (((int16_t)(src)) < 0); | |
8029 | m68k_write_memory_16(dsta,src); | |
8030 | }}}m68k_incpc(4); | |
8031 | return 14; | |
8032 | } | |
8033 | unsigned long CPUFUNC(op_3188_4)(uint32_t opcode) /* MOVE */ | |
8034 | { | |
8035 | uint32_t srcreg = (opcode & 7); | |
8036 | uint32_t dstreg = (opcode >> 9) & 7; | |
8037 | OpcodeFamily = 30; CurrentInstrCycles = 14; | |
8038 | {{ int16_t src = m68k_areg(regs, srcreg); | |
8039 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); | |
8040 | BusCyclePenalty += 2; | |
8041 | CLEAR_CZNV; | |
8042 | SET_ZFLG (((int16_t)(src)) == 0); | |
8043 | SET_NFLG (((int16_t)(src)) < 0); | |
8044 | m68k_write_memory_16(dsta,src); | |
8045 | }}}m68k_incpc(4); | |
8046 | return 14; | |
8047 | } | |
8048 | unsigned long CPUFUNC(op_3190_4)(uint32_t opcode) /* MOVE */ | |
8049 | { | |
8050 | uint32_t srcreg = (opcode & 7); | |
8051 | uint32_t dstreg = (opcode >> 9) & 7; | |
8052 | OpcodeFamily = 30; CurrentInstrCycles = 18; | |
8053 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
8054 | { int16_t src = m68k_read_memory_16(srca); | |
8055 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); | |
8056 | BusCyclePenalty += 2; | |
8057 | CLEAR_CZNV; | |
8058 | SET_ZFLG (((int16_t)(src)) == 0); | |
8059 | SET_NFLG (((int16_t)(src)) < 0); | |
8060 | m68k_write_memory_16(dsta,src); | |
8061 | }}}}m68k_incpc(4); | |
8062 | return 18; | |
8063 | } | |
8064 | unsigned long CPUFUNC(op_3198_4)(uint32_t opcode) /* MOVE */ | |
8065 | { | |
8066 | uint32_t srcreg = (opcode & 7); | |
8067 | uint32_t dstreg = (opcode >> 9) & 7; | |
8068 | OpcodeFamily = 30; CurrentInstrCycles = 18; | |
8069 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
8070 | { int16_t src = m68k_read_memory_16(srca); | |
8071 | m68k_areg(regs, srcreg) += 2; | |
8072 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); | |
8073 | BusCyclePenalty += 2; | |
8074 | CLEAR_CZNV; | |
8075 | SET_ZFLG (((int16_t)(src)) == 0); | |
8076 | SET_NFLG (((int16_t)(src)) < 0); | |
8077 | m68k_write_memory_16(dsta,src); | |
8078 | }}}}m68k_incpc(4); | |
8079 | return 18; | |
8080 | } | |
8081 | unsigned long CPUFUNC(op_31a0_4)(uint32_t opcode) /* MOVE */ | |
8082 | { | |
8083 | uint32_t srcreg = (opcode & 7); | |
8084 | uint32_t dstreg = (opcode >> 9) & 7; | |
8085 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
8086 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
8087 | { int16_t src = m68k_read_memory_16(srca); | |
8088 | m68k_areg (regs, srcreg) = srca; | |
8089 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); | |
8090 | BusCyclePenalty += 2; | |
8091 | CLEAR_CZNV; | |
8092 | SET_ZFLG (((int16_t)(src)) == 0); | |
8093 | SET_NFLG (((int16_t)(src)) < 0); | |
8094 | m68k_write_memory_16(dsta,src); | |
8095 | }}}}m68k_incpc(4); | |
8096 | return 20; | |
8097 | } | |
8098 | unsigned long CPUFUNC(op_31a8_4)(uint32_t opcode) /* MOVE */ | |
8099 | { | |
8100 | uint32_t srcreg = (opcode & 7); | |
8101 | uint32_t dstreg = (opcode >> 9) & 7; | |
8102 | OpcodeFamily = 30; CurrentInstrCycles = 22; | |
8103 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
8104 | { int16_t src = m68k_read_memory_16(srca); | |
8105 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); | |
8106 | BusCyclePenalty += 2; | |
8107 | CLEAR_CZNV; | |
8108 | SET_ZFLG (((int16_t)(src)) == 0); | |
8109 | SET_NFLG (((int16_t)(src)) < 0); | |
8110 | m68k_write_memory_16(dsta,src); | |
8111 | }}}}m68k_incpc(6); | |
8112 | return 22; | |
8113 | } | |
8114 | unsigned long CPUFUNC(op_31b0_4)(uint32_t opcode) /* MOVE */ | |
8115 | { | |
8116 | uint32_t srcreg = (opcode & 7); | |
8117 | uint32_t dstreg = (opcode >> 9) & 7; | |
8118 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
8119 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
8120 | BusCyclePenalty += 2; | |
8121 | { int16_t src = m68k_read_memory_16(srca); | |
8122 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); | |
8123 | BusCyclePenalty += 2; | |
8124 | CLEAR_CZNV; | |
8125 | SET_ZFLG (((int16_t)(src)) == 0); | |
8126 | SET_NFLG (((int16_t)(src)) < 0); | |
8127 | m68k_write_memory_16(dsta,src); | |
8128 | }}}}m68k_incpc(6); | |
8129 | return 24; | |
8130 | } | |
8131 | unsigned long CPUFUNC(op_31b8_4)(uint32_t opcode) /* MOVE */ | |
8132 | { | |
8133 | uint32_t dstreg = (opcode >> 9) & 7; | |
8134 | OpcodeFamily = 30; CurrentInstrCycles = 22; | |
8135 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
8136 | { int16_t src = m68k_read_memory_16(srca); | |
8137 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); | |
8138 | BusCyclePenalty += 2; | |
8139 | CLEAR_CZNV; | |
8140 | SET_ZFLG (((int16_t)(src)) == 0); | |
8141 | SET_NFLG (((int16_t)(src)) < 0); | |
8142 | m68k_write_memory_16(dsta,src); | |
8143 | }}}}m68k_incpc(6); | |
8144 | return 22; | |
8145 | } | |
8146 | unsigned long CPUFUNC(op_31b9_4)(uint32_t opcode) /* MOVE */ | |
8147 | { | |
8148 | uint32_t dstreg = (opcode >> 9) & 7; | |
8149 | OpcodeFamily = 30; CurrentInstrCycles = 26; | |
8150 | {{ uint32_t srca = get_ilong(2); | |
8151 | { int16_t src = m68k_read_memory_16(srca); | |
8152 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(6)); | |
8153 | BusCyclePenalty += 2; | |
8154 | CLEAR_CZNV; | |
8155 | SET_ZFLG (((int16_t)(src)) == 0); | |
8156 | SET_NFLG (((int16_t)(src)) < 0); | |
8157 | m68k_write_memory_16(dsta,src); | |
8158 | }}}}m68k_incpc(8); | |
8159 | return 26; | |
8160 | } | |
8161 | unsigned long CPUFUNC(op_31ba_4)(uint32_t opcode) /* MOVE */ | |
8162 | { | |
8163 | uint32_t dstreg = (opcode >> 9) & 7; | |
8164 | OpcodeFamily = 30; CurrentInstrCycles = 22; | |
8165 | {{ uint32_t srca = m68k_getpc () + 2; | |
8166 | srca += (int32_t)(int16_t)get_iword(2); | |
8167 | { int16_t src = m68k_read_memory_16(srca); | |
8168 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); | |
8169 | BusCyclePenalty += 2; | |
8170 | CLEAR_CZNV; | |
8171 | SET_ZFLG (((int16_t)(src)) == 0); | |
8172 | SET_NFLG (((int16_t)(src)) < 0); | |
8173 | m68k_write_memory_16(dsta,src); | |
8174 | }}}}m68k_incpc(6); | |
8175 | return 22; | |
8176 | } | |
8177 | unsigned long CPUFUNC(op_31bb_4)(uint32_t opcode) /* MOVE */ | |
8178 | { | |
8179 | uint32_t dstreg = (opcode >> 9) & 7; | |
8180 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
8181 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
8182 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
8183 | BusCyclePenalty += 2; | |
8184 | { int16_t src = m68k_read_memory_16(srca); | |
8185 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); | |
8186 | BusCyclePenalty += 2; | |
8187 | CLEAR_CZNV; | |
8188 | SET_ZFLG (((int16_t)(src)) == 0); | |
8189 | SET_NFLG (((int16_t)(src)) < 0); | |
8190 | m68k_write_memory_16(dsta,src); | |
8191 | }}}}m68k_incpc(6); | |
8192 | return 24; | |
8193 | } | |
8194 | unsigned long CPUFUNC(op_31bc_4)(uint32_t opcode) /* MOVE */ | |
8195 | { | |
8196 | uint32_t dstreg = (opcode >> 9) & 7; | |
8197 | OpcodeFamily = 30; CurrentInstrCycles = 18; | |
8198 | {{ int16_t src = get_iword(2); | |
8199 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); | |
8200 | BusCyclePenalty += 2; | |
8201 | CLEAR_CZNV; | |
8202 | SET_ZFLG (((int16_t)(src)) == 0); | |
8203 | SET_NFLG (((int16_t)(src)) < 0); | |
8204 | m68k_write_memory_16(dsta,src); | |
8205 | }}}m68k_incpc(6); | |
8206 | return 18; | |
8207 | } | |
8208 | unsigned long CPUFUNC(op_31c0_4)(uint32_t opcode) /* MOVE */ | |
8209 | { | |
8210 | uint32_t srcreg = (opcode & 7); | |
8211 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
8212 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
8213 | { uint32_t dsta = (int32_t)(int16_t)get_iword(2); | |
8214 | CLEAR_CZNV; | |
8215 | SET_ZFLG (((int16_t)(src)) == 0); | |
8216 | SET_NFLG (((int16_t)(src)) < 0); | |
8217 | m68k_write_memory_16(dsta,src); | |
8218 | }}}m68k_incpc(4); | |
8219 | return 12; | |
8220 | } | |
8221 | unsigned long CPUFUNC(op_31c8_4)(uint32_t opcode) /* MOVE */ | |
8222 | { | |
8223 | uint32_t srcreg = (opcode & 7); | |
8224 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
8225 | {{ int16_t src = m68k_areg(regs, srcreg); | |
8226 | { uint32_t dsta = (int32_t)(int16_t)get_iword(2); | |
8227 | CLEAR_CZNV; | |
8228 | SET_ZFLG (((int16_t)(src)) == 0); | |
8229 | SET_NFLG (((int16_t)(src)) < 0); | |
8230 | m68k_write_memory_16(dsta,src); | |
8231 | }}}m68k_incpc(4); | |
8232 | return 12; | |
8233 | } | |
8234 | unsigned long CPUFUNC(op_31d0_4)(uint32_t opcode) /* MOVE */ | |
8235 | { | |
8236 | uint32_t srcreg = (opcode & 7); | |
8237 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
8238 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
8239 | { int16_t src = m68k_read_memory_16(srca); | |
8240 | { uint32_t dsta = (int32_t)(int16_t)get_iword(2); | |
8241 | CLEAR_CZNV; | |
8242 | SET_ZFLG (((int16_t)(src)) == 0); | |
8243 | SET_NFLG (((int16_t)(src)) < 0); | |
8244 | m68k_write_memory_16(dsta,src); | |
8245 | }}}}m68k_incpc(4); | |
8246 | return 16; | |
8247 | } | |
8248 | unsigned long CPUFUNC(op_31d8_4)(uint32_t opcode) /* MOVE */ | |
8249 | { | |
8250 | uint32_t srcreg = (opcode & 7); | |
8251 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
8252 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
8253 | { int16_t src = m68k_read_memory_16(srca); | |
8254 | m68k_areg(regs, srcreg) += 2; | |
8255 | { uint32_t dsta = (int32_t)(int16_t)get_iword(2); | |
8256 | CLEAR_CZNV; | |
8257 | SET_ZFLG (((int16_t)(src)) == 0); | |
8258 | SET_NFLG (((int16_t)(src)) < 0); | |
8259 | m68k_write_memory_16(dsta,src); | |
8260 | }}}}m68k_incpc(4); | |
8261 | return 16; | |
8262 | } | |
8263 | unsigned long CPUFUNC(op_31e0_4)(uint32_t opcode) /* MOVE */ | |
8264 | { | |
8265 | uint32_t srcreg = (opcode & 7); | |
8266 | OpcodeFamily = 30; CurrentInstrCycles = 18; | |
8267 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
8268 | { int16_t src = m68k_read_memory_16(srca); | |
8269 | m68k_areg (regs, srcreg) = srca; | |
8270 | { uint32_t dsta = (int32_t)(int16_t)get_iword(2); | |
8271 | CLEAR_CZNV; | |
8272 | SET_ZFLG (((int16_t)(src)) == 0); | |
8273 | SET_NFLG (((int16_t)(src)) < 0); | |
8274 | m68k_write_memory_16(dsta,src); | |
8275 | }}}}m68k_incpc(4); | |
8276 | return 18; | |
8277 | } | |
8278 | unsigned long CPUFUNC(op_31e8_4)(uint32_t opcode) /* MOVE */ | |
8279 | { | |
8280 | uint32_t srcreg = (opcode & 7); | |
8281 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
8282 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
8283 | { int16_t src = m68k_read_memory_16(srca); | |
8284 | { uint32_t dsta = (int32_t)(int16_t)get_iword(4); | |
8285 | CLEAR_CZNV; | |
8286 | SET_ZFLG (((int16_t)(src)) == 0); | |
8287 | SET_NFLG (((int16_t)(src)) < 0); | |
8288 | m68k_write_memory_16(dsta,src); | |
8289 | }}}}m68k_incpc(6); | |
8290 | return 20; | |
8291 | } | |
8292 | unsigned long CPUFUNC(op_31f0_4)(uint32_t opcode) /* MOVE */ | |
8293 | { | |
8294 | uint32_t srcreg = (opcode & 7); | |
8295 | OpcodeFamily = 30; CurrentInstrCycles = 22; | |
8296 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
8297 | BusCyclePenalty += 2; | |
8298 | { int16_t src = m68k_read_memory_16(srca); | |
8299 | { uint32_t dsta = (int32_t)(int16_t)get_iword(4); | |
8300 | CLEAR_CZNV; | |
8301 | SET_ZFLG (((int16_t)(src)) == 0); | |
8302 | SET_NFLG (((int16_t)(src)) < 0); | |
8303 | m68k_write_memory_16(dsta,src); | |
8304 | }}}}m68k_incpc(6); | |
8305 | return 22; | |
8306 | } | |
8307 | unsigned long CPUFUNC(op_31f8_4)(uint32_t opcode) /* MOVE */ | |
8308 | { | |
8309 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
8310 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
8311 | { int16_t src = m68k_read_memory_16(srca); | |
8312 | { uint32_t dsta = (int32_t)(int16_t)get_iword(4); | |
8313 | CLEAR_CZNV; | |
8314 | SET_ZFLG (((int16_t)(src)) == 0); | |
8315 | SET_NFLG (((int16_t)(src)) < 0); | |
8316 | m68k_write_memory_16(dsta,src); | |
8317 | }}}}m68k_incpc(6); | |
8318 | return 20; | |
8319 | } | |
8320 | unsigned long CPUFUNC(op_31f9_4)(uint32_t opcode) /* MOVE */ | |
8321 | { | |
8322 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
8323 | {{ uint32_t srca = get_ilong(2); | |
8324 | { int16_t src = m68k_read_memory_16(srca); | |
8325 | { uint32_t dsta = (int32_t)(int16_t)get_iword(6); | |
8326 | CLEAR_CZNV; | |
8327 | SET_ZFLG (((int16_t)(src)) == 0); | |
8328 | SET_NFLG (((int16_t)(src)) < 0); | |
8329 | m68k_write_memory_16(dsta,src); | |
8330 | }}}}m68k_incpc(8); | |
8331 | return 24; | |
8332 | } | |
8333 | unsigned long CPUFUNC(op_31fa_4)(uint32_t opcode) /* MOVE */ | |
8334 | { | |
8335 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
8336 | {{ uint32_t srca = m68k_getpc () + 2; | |
8337 | srca += (int32_t)(int16_t)get_iword(2); | |
8338 | { int16_t src = m68k_read_memory_16(srca); | |
8339 | { uint32_t dsta = (int32_t)(int16_t)get_iword(4); | |
8340 | CLEAR_CZNV; | |
8341 | SET_ZFLG (((int16_t)(src)) == 0); | |
8342 | SET_NFLG (((int16_t)(src)) < 0); | |
8343 | m68k_write_memory_16(dsta,src); | |
8344 | }}}}m68k_incpc(6); | |
8345 | return 20; | |
8346 | } | |
8347 | unsigned long CPUFUNC(op_31fb_4)(uint32_t opcode) /* MOVE */ | |
8348 | { | |
8349 | OpcodeFamily = 30; CurrentInstrCycles = 22; | |
8350 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
8351 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
8352 | BusCyclePenalty += 2; | |
8353 | { int16_t src = m68k_read_memory_16(srca); | |
8354 | { uint32_t dsta = (int32_t)(int16_t)get_iword(4); | |
8355 | CLEAR_CZNV; | |
8356 | SET_ZFLG (((int16_t)(src)) == 0); | |
8357 | SET_NFLG (((int16_t)(src)) < 0); | |
8358 | m68k_write_memory_16(dsta,src); | |
8359 | }}}}m68k_incpc(6); | |
8360 | return 22; | |
8361 | } | |
8362 | unsigned long CPUFUNC(op_31fc_4)(uint32_t opcode) /* MOVE */ | |
8363 | { | |
8364 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
8365 | {{ int16_t src = get_iword(2); | |
8366 | { uint32_t dsta = (int32_t)(int16_t)get_iword(4); | |
8367 | CLEAR_CZNV; | |
8368 | SET_ZFLG (((int16_t)(src)) == 0); | |
8369 | SET_NFLG (((int16_t)(src)) < 0); | |
8370 | m68k_write_memory_16(dsta,src); | |
8371 | }}}m68k_incpc(6); | |
8372 | return 16; | |
8373 | } | |
8374 | unsigned long CPUFUNC(op_33c0_4)(uint32_t opcode) /* MOVE */ | |
8375 | { | |
8376 | uint32_t srcreg = (opcode & 7); | |
8377 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
8378 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
8379 | { uint32_t dsta = get_ilong(2); | |
8380 | CLEAR_CZNV; | |
8381 | SET_ZFLG (((int16_t)(src)) == 0); | |
8382 | SET_NFLG (((int16_t)(src)) < 0); | |
8383 | m68k_write_memory_16(dsta,src); | |
8384 | }}}m68k_incpc(6); | |
8385 | return 16; | |
8386 | } | |
8387 | unsigned long CPUFUNC(op_33c8_4)(uint32_t opcode) /* MOVE */ | |
8388 | { | |
8389 | uint32_t srcreg = (opcode & 7); | |
8390 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
8391 | {{ int16_t src = m68k_areg(regs, srcreg); | |
8392 | { uint32_t dsta = get_ilong(2); | |
8393 | CLEAR_CZNV; | |
8394 | SET_ZFLG (((int16_t)(src)) == 0); | |
8395 | SET_NFLG (((int16_t)(src)) < 0); | |
8396 | m68k_write_memory_16(dsta,src); | |
8397 | }}}m68k_incpc(6); | |
8398 | return 16; | |
8399 | } | |
8400 | unsigned long CPUFUNC(op_33d0_4)(uint32_t opcode) /* MOVE */ | |
8401 | { | |
8402 | uint32_t srcreg = (opcode & 7); | |
8403 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
8404 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
8405 | { int16_t src = m68k_read_memory_16(srca); | |
8406 | { uint32_t dsta = get_ilong(2); | |
8407 | CLEAR_CZNV; | |
8408 | SET_ZFLG (((int16_t)(src)) == 0); | |
8409 | SET_NFLG (((int16_t)(src)) < 0); | |
8410 | m68k_write_memory_16(dsta,src); | |
8411 | }}}}m68k_incpc(6); | |
8412 | return 20; | |
8413 | } | |
8414 | unsigned long CPUFUNC(op_33d8_4)(uint32_t opcode) /* MOVE */ | |
8415 | { | |
8416 | uint32_t srcreg = (opcode & 7); | |
8417 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
8418 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
8419 | { int16_t src = m68k_read_memory_16(srca); | |
8420 | m68k_areg(regs, srcreg) += 2; | |
8421 | { uint32_t dsta = get_ilong(2); | |
8422 | CLEAR_CZNV; | |
8423 | SET_ZFLG (((int16_t)(src)) == 0); | |
8424 | SET_NFLG (((int16_t)(src)) < 0); | |
8425 | m68k_write_memory_16(dsta,src); | |
8426 | }}}}m68k_incpc(6); | |
8427 | return 20; | |
8428 | } | |
8429 | unsigned long CPUFUNC(op_33e0_4)(uint32_t opcode) /* MOVE */ | |
8430 | { | |
8431 | uint32_t srcreg = (opcode & 7); | |
8432 | OpcodeFamily = 30; CurrentInstrCycles = 22; | |
8433 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
8434 | { int16_t src = m68k_read_memory_16(srca); | |
8435 | m68k_areg (regs, srcreg) = srca; | |
8436 | { uint32_t dsta = get_ilong(2); | |
8437 | CLEAR_CZNV; | |
8438 | SET_ZFLG (((int16_t)(src)) == 0); | |
8439 | SET_NFLG (((int16_t)(src)) < 0); | |
8440 | m68k_write_memory_16(dsta,src); | |
8441 | }}}}m68k_incpc(6); | |
8442 | return 22; | |
8443 | } | |
8444 | unsigned long CPUFUNC(op_33e8_4)(uint32_t opcode) /* MOVE */ | |
8445 | { | |
8446 | uint32_t srcreg = (opcode & 7); | |
8447 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
8448 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
8449 | { int16_t src = m68k_read_memory_16(srca); | |
8450 | { uint32_t dsta = get_ilong(4); | |
8451 | CLEAR_CZNV; | |
8452 | SET_ZFLG (((int16_t)(src)) == 0); | |
8453 | SET_NFLG (((int16_t)(src)) < 0); | |
8454 | m68k_write_memory_16(dsta,src); | |
8455 | }}}}m68k_incpc(8); | |
8456 | return 24; | |
8457 | } | |
8458 | unsigned long CPUFUNC(op_33f0_4)(uint32_t opcode) /* MOVE */ | |
8459 | { | |
8460 | uint32_t srcreg = (opcode & 7); | |
8461 | OpcodeFamily = 30; CurrentInstrCycles = 26; | |
8462 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
8463 | BusCyclePenalty += 2; | |
8464 | { int16_t src = m68k_read_memory_16(srca); | |
8465 | { uint32_t dsta = get_ilong(4); | |
8466 | CLEAR_CZNV; | |
8467 | SET_ZFLG (((int16_t)(src)) == 0); | |
8468 | SET_NFLG (((int16_t)(src)) < 0); | |
8469 | m68k_write_memory_16(dsta,src); | |
8470 | }}}}m68k_incpc(8); | |
8471 | return 26; | |
8472 | } | |
8473 | unsigned long CPUFUNC(op_33f8_4)(uint32_t opcode) /* MOVE */ | |
8474 | { | |
8475 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
8476 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
8477 | { int16_t src = m68k_read_memory_16(srca); | |
8478 | { uint32_t dsta = get_ilong(4); | |
8479 | CLEAR_CZNV; | |
8480 | SET_ZFLG (((int16_t)(src)) == 0); | |
8481 | SET_NFLG (((int16_t)(src)) < 0); | |
8482 | m68k_write_memory_16(dsta,src); | |
8483 | }}}}m68k_incpc(8); | |
8484 | return 24; | |
8485 | } | |
8486 | unsigned long CPUFUNC(op_33f9_4)(uint32_t opcode) /* MOVE */ | |
8487 | { | |
8488 | OpcodeFamily = 30; CurrentInstrCycles = 28; | |
8489 | {{ uint32_t srca = get_ilong(2); | |
8490 | { int16_t src = m68k_read_memory_16(srca); | |
8491 | { uint32_t dsta = get_ilong(6); | |
8492 | CLEAR_CZNV; | |
8493 | SET_ZFLG (((int16_t)(src)) == 0); | |
8494 | SET_NFLG (((int16_t)(src)) < 0); | |
8495 | m68k_write_memory_16(dsta,src); | |
8496 | }}}}m68k_incpc(10); | |
8497 | return 28; | |
8498 | } | |
8499 | unsigned long CPUFUNC(op_33fa_4)(uint32_t opcode) /* MOVE */ | |
8500 | { | |
8501 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
8502 | {{ uint32_t srca = m68k_getpc () + 2; | |
8503 | srca += (int32_t)(int16_t)get_iword(2); | |
8504 | { int16_t src = m68k_read_memory_16(srca); | |
8505 | { uint32_t dsta = get_ilong(4); | |
8506 | CLEAR_CZNV; | |
8507 | SET_ZFLG (((int16_t)(src)) == 0); | |
8508 | SET_NFLG (((int16_t)(src)) < 0); | |
8509 | m68k_write_memory_16(dsta,src); | |
8510 | }}}}m68k_incpc(8); | |
8511 | return 24; | |
8512 | } | |
8513 | unsigned long CPUFUNC(op_33fb_4)(uint32_t opcode) /* MOVE */ | |
8514 | { | |
8515 | OpcodeFamily = 30; CurrentInstrCycles = 26; | |
8516 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
8517 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
8518 | BusCyclePenalty += 2; | |
8519 | { int16_t src = m68k_read_memory_16(srca); | |
8520 | { uint32_t dsta = get_ilong(4); | |
8521 | CLEAR_CZNV; | |
8522 | SET_ZFLG (((int16_t)(src)) == 0); | |
8523 | SET_NFLG (((int16_t)(src)) < 0); | |
8524 | m68k_write_memory_16(dsta,src); | |
8525 | }}}}m68k_incpc(8); | |
8526 | return 26; | |
8527 | } | |
8528 | unsigned long CPUFUNC(op_33fc_4)(uint32_t opcode) /* MOVE */ | |
8529 | { | |
8530 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
8531 | {{ int16_t src = get_iword(2); | |
8532 | { uint32_t dsta = get_ilong(4); | |
8533 | CLEAR_CZNV; | |
8534 | SET_ZFLG (((int16_t)(src)) == 0); | |
8535 | SET_NFLG (((int16_t)(src)) < 0); | |
8536 | m68k_write_memory_16(dsta,src); | |
8537 | }}}m68k_incpc(8); | |
8538 | return 20; | |
8539 | } | |
8540 | unsigned long CPUFUNC(op_4000_4)(uint32_t opcode) /* NEGX */ | |
8541 | { | |
8542 | uint32_t srcreg = (opcode & 7); | |
8543 | OpcodeFamily = 16; CurrentInstrCycles = 4; | |
8544 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
8545 | { uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); | |
8546 | { int flgs = ((int8_t)(src)) < 0; | |
8547 | int flgo = ((int8_t)(0)) < 0; | |
8548 | int flgn = ((int8_t)(newv)) < 0; | |
8549 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
8550 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
8551 | COPY_CARRY; | |
8552 | SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); | |
8553 | SET_NFLG (((int8_t)(newv)) < 0); | |
8554 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((newv) & 0xff); | |
8555 | }}}}m68k_incpc(2); | |
8556 | return 4; | |
8557 | } | |
8558 | unsigned long CPUFUNC(op_4010_4)(uint32_t opcode) /* NEGX */ | |
8559 | { | |
8560 | uint32_t srcreg = (opcode & 7); | |
8561 | OpcodeFamily = 16; CurrentInstrCycles = 12; | |
8562 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
8563 | { int8_t src = m68k_read_memory_8(srca); | |
8564 | { uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); | |
8565 | { int flgs = ((int8_t)(src)) < 0; | |
8566 | int flgo = ((int8_t)(0)) < 0; | |
8567 | int flgn = ((int8_t)(newv)) < 0; | |
8568 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
8569 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
8570 | COPY_CARRY; | |
8571 | SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); | |
8572 | SET_NFLG (((int8_t)(newv)) < 0); | |
8573 | m68k_write_memory_8(srca,newv); | |
8574 | }}}}}m68k_incpc(2); | |
8575 | return 12; | |
8576 | } | |
8577 | unsigned long CPUFUNC(op_4018_4)(uint32_t opcode) /* NEGX */ | |
8578 | { | |
8579 | uint32_t srcreg = (opcode & 7); | |
8580 | OpcodeFamily = 16; CurrentInstrCycles = 12; | |
8581 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
8582 | { int8_t src = m68k_read_memory_8(srca); | |
8583 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
8584 | { uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); | |
8585 | { int flgs = ((int8_t)(src)) < 0; | |
8586 | int flgo = ((int8_t)(0)) < 0; | |
8587 | int flgn = ((int8_t)(newv)) < 0; | |
8588 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
8589 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
8590 | COPY_CARRY; | |
8591 | SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); | |
8592 | SET_NFLG (((int8_t)(newv)) < 0); | |
8593 | m68k_write_memory_8(srca,newv); | |
8594 | }}}}}m68k_incpc(2); | |
8595 | return 12; | |
8596 | } | |
8597 | unsigned long CPUFUNC(op_4020_4)(uint32_t opcode) /* NEGX */ | |
8598 | { | |
8599 | uint32_t srcreg = (opcode & 7); | |
8600 | OpcodeFamily = 16; CurrentInstrCycles = 14; | |
8601 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
8602 | { int8_t src = m68k_read_memory_8(srca); | |
8603 | m68k_areg (regs, srcreg) = srca; | |
8604 | { uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); | |
8605 | { int flgs = ((int8_t)(src)) < 0; | |
8606 | int flgo = ((int8_t)(0)) < 0; | |
8607 | int flgn = ((int8_t)(newv)) < 0; | |
8608 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
8609 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
8610 | COPY_CARRY; | |
8611 | SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); | |
8612 | SET_NFLG (((int8_t)(newv)) < 0); | |
8613 | m68k_write_memory_8(srca,newv); | |
8614 | }}}}}m68k_incpc(2); | |
8615 | return 14; | |
8616 | } | |
8617 | unsigned long CPUFUNC(op_4028_4)(uint32_t opcode) /* NEGX */ | |
8618 | { | |
8619 | uint32_t srcreg = (opcode & 7); | |
8620 | OpcodeFamily = 16; CurrentInstrCycles = 16; | |
8621 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
8622 | { int8_t src = m68k_read_memory_8(srca); | |
8623 | { uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); | |
8624 | { int flgs = ((int8_t)(src)) < 0; | |
8625 | int flgo = ((int8_t)(0)) < 0; | |
8626 | int flgn = ((int8_t)(newv)) < 0; | |
8627 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
8628 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
8629 | COPY_CARRY; | |
8630 | SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); | |
8631 | SET_NFLG (((int8_t)(newv)) < 0); | |
8632 | m68k_write_memory_8(srca,newv); | |
8633 | }}}}}m68k_incpc(4); | |
8634 | return 16; | |
8635 | } | |
8636 | unsigned long CPUFUNC(op_4030_4)(uint32_t opcode) /* NEGX */ | |
8637 | { | |
8638 | uint32_t srcreg = (opcode & 7); | |
8639 | OpcodeFamily = 16; CurrentInstrCycles = 18; | |
8640 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
8641 | BusCyclePenalty += 2; | |
8642 | { int8_t src = m68k_read_memory_8(srca); | |
8643 | { uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); | |
8644 | { int flgs = ((int8_t)(src)) < 0; | |
8645 | int flgo = ((int8_t)(0)) < 0; | |
8646 | int flgn = ((int8_t)(newv)) < 0; | |
8647 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
8648 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
8649 | COPY_CARRY; | |
8650 | SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); | |
8651 | SET_NFLG (((int8_t)(newv)) < 0); | |
8652 | m68k_write_memory_8(srca,newv); | |
8653 | }}}}}m68k_incpc(4); | |
8654 | return 18; | |
8655 | } | |
8656 | unsigned long CPUFUNC(op_4038_4)(uint32_t opcode) /* NEGX */ | |
8657 | { | |
8658 | OpcodeFamily = 16; CurrentInstrCycles = 16; | |
8659 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
8660 | { int8_t src = m68k_read_memory_8(srca); | |
8661 | { uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); | |
8662 | { int flgs = ((int8_t)(src)) < 0; | |
8663 | int flgo = ((int8_t)(0)) < 0; | |
8664 | int flgn = ((int8_t)(newv)) < 0; | |
8665 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
8666 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
8667 | COPY_CARRY; | |
8668 | SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); | |
8669 | SET_NFLG (((int8_t)(newv)) < 0); | |
8670 | m68k_write_memory_8(srca,newv); | |
8671 | }}}}}m68k_incpc(4); | |
8672 | return 16; | |
8673 | } | |
8674 | unsigned long CPUFUNC(op_4039_4)(uint32_t opcode) /* NEGX */ | |
8675 | { | |
8676 | OpcodeFamily = 16; CurrentInstrCycles = 20; | |
8677 | {{ uint32_t srca = get_ilong(2); | |
8678 | { int8_t src = m68k_read_memory_8(srca); | |
8679 | { uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); | |
8680 | { int flgs = ((int8_t)(src)) < 0; | |
8681 | int flgo = ((int8_t)(0)) < 0; | |
8682 | int flgn = ((int8_t)(newv)) < 0; | |
8683 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
8684 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
8685 | COPY_CARRY; | |
8686 | SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); | |
8687 | SET_NFLG (((int8_t)(newv)) < 0); | |
8688 | m68k_write_memory_8(srca,newv); | |
8689 | }}}}}m68k_incpc(6); | |
8690 | return 20; | |
8691 | } | |
8692 | unsigned long CPUFUNC(op_4040_4)(uint32_t opcode) /* NEGX */ | |
8693 | { | |
8694 | uint32_t srcreg = (opcode & 7); | |
8695 | OpcodeFamily = 16; CurrentInstrCycles = 4; | |
8696 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
8697 | { uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); | |
8698 | { int flgs = ((int16_t)(src)) < 0; | |
8699 | int flgo = ((int16_t)(0)) < 0; | |
8700 | int flgn = ((int16_t)(newv)) < 0; | |
8701 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
8702 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
8703 | COPY_CARRY; | |
8704 | SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0)); | |
8705 | SET_NFLG (((int16_t)(newv)) < 0); | |
8706 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((newv) & 0xffff); | |
8707 | }}}}m68k_incpc(2); | |
8708 | return 4; | |
8709 | } | |
8710 | unsigned long CPUFUNC(op_4050_4)(uint32_t opcode) /* NEGX */ | |
8711 | { | |
8712 | uint32_t srcreg = (opcode & 7); | |
8713 | OpcodeFamily = 16; CurrentInstrCycles = 12; | |
8714 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
8715 | { int16_t src = m68k_read_memory_16(srca); | |
8716 | { uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); | |
8717 | { int flgs = ((int16_t)(src)) < 0; | |
8718 | int flgo = ((int16_t)(0)) < 0; | |
8719 | int flgn = ((int16_t)(newv)) < 0; | |
8720 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
8721 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
8722 | COPY_CARRY; | |
8723 | SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0)); | |
8724 | SET_NFLG (((int16_t)(newv)) < 0); | |
8725 | m68k_write_memory_16(srca,newv); | |
8726 | }}}}}m68k_incpc(2); | |
8727 | return 12; | |
8728 | } | |
8729 | unsigned long CPUFUNC(op_4058_4)(uint32_t opcode) /* NEGX */ | |
8730 | { | |
8731 | uint32_t srcreg = (opcode & 7); | |
8732 | OpcodeFamily = 16; CurrentInstrCycles = 12; | |
8733 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
8734 | { int16_t src = m68k_read_memory_16(srca); | |
8735 | m68k_areg(regs, srcreg) += 2; | |
8736 | { uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); | |
8737 | { int flgs = ((int16_t)(src)) < 0; | |
8738 | int flgo = ((int16_t)(0)) < 0; | |
8739 | int flgn = ((int16_t)(newv)) < 0; | |
8740 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
8741 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
8742 | COPY_CARRY; | |
8743 | SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0)); | |
8744 | SET_NFLG (((int16_t)(newv)) < 0); | |
8745 | m68k_write_memory_16(srca,newv); | |
8746 | }}}}}m68k_incpc(2); | |
8747 | return 12; | |
8748 | } | |
8749 | unsigned long CPUFUNC(op_4060_4)(uint32_t opcode) /* NEGX */ | |
8750 | { | |
8751 | uint32_t srcreg = (opcode & 7); | |
8752 | OpcodeFamily = 16; CurrentInstrCycles = 14; | |
8753 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
8754 | { int16_t src = m68k_read_memory_16(srca); | |
8755 | m68k_areg (regs, srcreg) = srca; | |
8756 | { uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); | |
8757 | { int flgs = ((int16_t)(src)) < 0; | |
8758 | int flgo = ((int16_t)(0)) < 0; | |
8759 | int flgn = ((int16_t)(newv)) < 0; | |
8760 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
8761 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
8762 | COPY_CARRY; | |
8763 | SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0)); | |
8764 | SET_NFLG (((int16_t)(newv)) < 0); | |
8765 | m68k_write_memory_16(srca,newv); | |
8766 | }}}}}m68k_incpc(2); | |
8767 | return 14; | |
8768 | } | |
8769 | unsigned long CPUFUNC(op_4068_4)(uint32_t opcode) /* NEGX */ | |
8770 | { | |
8771 | uint32_t srcreg = (opcode & 7); | |
8772 | OpcodeFamily = 16; CurrentInstrCycles = 16; | |
8773 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
8774 | { int16_t src = m68k_read_memory_16(srca); | |
8775 | { uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); | |
8776 | { int flgs = ((int16_t)(src)) < 0; | |
8777 | int flgo = ((int16_t)(0)) < 0; | |
8778 | int flgn = ((int16_t)(newv)) < 0; | |
8779 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
8780 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
8781 | COPY_CARRY; | |
8782 | SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0)); | |
8783 | SET_NFLG (((int16_t)(newv)) < 0); | |
8784 | m68k_write_memory_16(srca,newv); | |
8785 | }}}}}m68k_incpc(4); | |
8786 | return 16; | |
8787 | } | |
8788 | unsigned long CPUFUNC(op_4070_4)(uint32_t opcode) /* NEGX */ | |
8789 | { | |
8790 | uint32_t srcreg = (opcode & 7); | |
8791 | OpcodeFamily = 16; CurrentInstrCycles = 18; | |
8792 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
8793 | BusCyclePenalty += 2; | |
8794 | { int16_t src = m68k_read_memory_16(srca); | |
8795 | { uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); | |
8796 | { int flgs = ((int16_t)(src)) < 0; | |
8797 | int flgo = ((int16_t)(0)) < 0; | |
8798 | int flgn = ((int16_t)(newv)) < 0; | |
8799 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
8800 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
8801 | COPY_CARRY; | |
8802 | SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0)); | |
8803 | SET_NFLG (((int16_t)(newv)) < 0); | |
8804 | m68k_write_memory_16(srca,newv); | |
8805 | }}}}}m68k_incpc(4); | |
8806 | return 18; | |
8807 | } | |
8808 | unsigned long CPUFUNC(op_4078_4)(uint32_t opcode) /* NEGX */ | |
8809 | { | |
8810 | OpcodeFamily = 16; CurrentInstrCycles = 16; | |
8811 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
8812 | { int16_t src = m68k_read_memory_16(srca); | |
8813 | { uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); | |
8814 | { int flgs = ((int16_t)(src)) < 0; | |
8815 | int flgo = ((int16_t)(0)) < 0; | |
8816 | int flgn = ((int16_t)(newv)) < 0; | |
8817 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
8818 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
8819 | COPY_CARRY; | |
8820 | SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0)); | |
8821 | SET_NFLG (((int16_t)(newv)) < 0); | |
8822 | m68k_write_memory_16(srca,newv); | |
8823 | }}}}}m68k_incpc(4); | |
8824 | return 16; | |
8825 | } | |
8826 | unsigned long CPUFUNC(op_4079_4)(uint32_t opcode) /* NEGX */ | |
8827 | { | |
8828 | OpcodeFamily = 16; CurrentInstrCycles = 20; | |
8829 | {{ uint32_t srca = get_ilong(2); | |
8830 | { int16_t src = m68k_read_memory_16(srca); | |
8831 | { uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); | |
8832 | { int flgs = ((int16_t)(src)) < 0; | |
8833 | int flgo = ((int16_t)(0)) < 0; | |
8834 | int flgn = ((int16_t)(newv)) < 0; | |
8835 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
8836 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
8837 | COPY_CARRY; | |
8838 | SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0)); | |
8839 | SET_NFLG (((int16_t)(newv)) < 0); | |
8840 | m68k_write_memory_16(srca,newv); | |
8841 | }}}}}m68k_incpc(6); | |
8842 | return 20; | |
8843 | } | |
8844 | unsigned long CPUFUNC(op_4080_4)(uint32_t opcode) /* NEGX */ | |
8845 | { | |
8846 | uint32_t srcreg = (opcode & 7); | |
8847 | OpcodeFamily = 16; CurrentInstrCycles = 6; | |
8848 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
8849 | { uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); | |
8850 | { int flgs = ((int32_t)(src)) < 0; | |
8851 | int flgo = ((int32_t)(0)) < 0; | |
8852 | int flgn = ((int32_t)(newv)) < 0; | |
8853 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
8854 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
8855 | COPY_CARRY; | |
8856 | SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0)); | |
8857 | SET_NFLG (((int32_t)(newv)) < 0); | |
8858 | m68k_dreg(regs, srcreg) = (newv); | |
8859 | }}}}m68k_incpc(2); | |
8860 | return 6; | |
8861 | } | |
8862 | unsigned long CPUFUNC(op_4090_4)(uint32_t opcode) /* NEGX */ | |
8863 | { | |
8864 | uint32_t srcreg = (opcode & 7); | |
8865 | OpcodeFamily = 16; CurrentInstrCycles = 20; | |
8866 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
8867 | { int32_t src = m68k_read_memory_32(srca); | |
8868 | { uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); | |
8869 | { int flgs = ((int32_t)(src)) < 0; | |
8870 | int flgo = ((int32_t)(0)) < 0; | |
8871 | int flgn = ((int32_t)(newv)) < 0; | |
8872 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
8873 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
8874 | COPY_CARRY; | |
8875 | SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0)); | |
8876 | SET_NFLG (((int32_t)(newv)) < 0); | |
8877 | m68k_write_memory_32(srca,newv); | |
8878 | }}}}}m68k_incpc(2); | |
8879 | return 20; | |
8880 | } | |
8881 | unsigned long CPUFUNC(op_4098_4)(uint32_t opcode) /* NEGX */ | |
8882 | { | |
8883 | uint32_t srcreg = (opcode & 7); | |
8884 | OpcodeFamily = 16; CurrentInstrCycles = 20; | |
8885 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
8886 | { int32_t src = m68k_read_memory_32(srca); | |
8887 | m68k_areg(regs, srcreg) += 4; | |
8888 | { uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); | |
8889 | { int flgs = ((int32_t)(src)) < 0; | |
8890 | int flgo = ((int32_t)(0)) < 0; | |
8891 | int flgn = ((int32_t)(newv)) < 0; | |
8892 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
8893 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
8894 | COPY_CARRY; | |
8895 | SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0)); | |
8896 | SET_NFLG (((int32_t)(newv)) < 0); | |
8897 | m68k_write_memory_32(srca,newv); | |
8898 | }}}}}m68k_incpc(2); | |
8899 | return 20; | |
8900 | } | |
8901 | unsigned long CPUFUNC(op_40a0_4)(uint32_t opcode) /* NEGX */ | |
8902 | { | |
8903 | uint32_t srcreg = (opcode & 7); | |
8904 | OpcodeFamily = 16; CurrentInstrCycles = 22; | |
8905 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 4; | |
8906 | { int32_t src = m68k_read_memory_32(srca); | |
8907 | m68k_areg (regs, srcreg) = srca; | |
8908 | { uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); | |
8909 | { int flgs = ((int32_t)(src)) < 0; | |
8910 | int flgo = ((int32_t)(0)) < 0; | |
8911 | int flgn = ((int32_t)(newv)) < 0; | |
8912 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
8913 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
8914 | COPY_CARRY; | |
8915 | SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0)); | |
8916 | SET_NFLG (((int32_t)(newv)) < 0); | |
8917 | m68k_write_memory_32(srca,newv); | |
8918 | }}}}}m68k_incpc(2); | |
8919 | return 22; | |
8920 | } | |
8921 | unsigned long CPUFUNC(op_40a8_4)(uint32_t opcode) /* NEGX */ | |
8922 | { | |
8923 | uint32_t srcreg = (opcode & 7); | |
8924 | OpcodeFamily = 16; CurrentInstrCycles = 24; | |
8925 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
8926 | { int32_t src = m68k_read_memory_32(srca); | |
8927 | { uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); | |
8928 | { int flgs = ((int32_t)(src)) < 0; | |
8929 | int flgo = ((int32_t)(0)) < 0; | |
8930 | int flgn = ((int32_t)(newv)) < 0; | |
8931 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
8932 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
8933 | COPY_CARRY; | |
8934 | SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0)); | |
8935 | SET_NFLG (((int32_t)(newv)) < 0); | |
8936 | m68k_write_memory_32(srca,newv); | |
8937 | }}}}}m68k_incpc(4); | |
8938 | return 24; | |
8939 | } | |
8940 | unsigned long CPUFUNC(op_40b0_4)(uint32_t opcode) /* NEGX */ | |
8941 | { | |
8942 | uint32_t srcreg = (opcode & 7); | |
8943 | OpcodeFamily = 16; CurrentInstrCycles = 26; | |
8944 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
8945 | BusCyclePenalty += 2; | |
8946 | { int32_t src = m68k_read_memory_32(srca); | |
8947 | { uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); | |
8948 | { int flgs = ((int32_t)(src)) < 0; | |
8949 | int flgo = ((int32_t)(0)) < 0; | |
8950 | int flgn = ((int32_t)(newv)) < 0; | |
8951 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
8952 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
8953 | COPY_CARRY; | |
8954 | SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0)); | |
8955 | SET_NFLG (((int32_t)(newv)) < 0); | |
8956 | m68k_write_memory_32(srca,newv); | |
8957 | }}}}}m68k_incpc(4); | |
8958 | return 26; | |
8959 | } | |
8960 | unsigned long CPUFUNC(op_40b8_4)(uint32_t opcode) /* NEGX */ | |
8961 | { | |
8962 | OpcodeFamily = 16; CurrentInstrCycles = 24; | |
8963 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
8964 | { int32_t src = m68k_read_memory_32(srca); | |
8965 | { uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); | |
8966 | { int flgs = ((int32_t)(src)) < 0; | |
8967 | int flgo = ((int32_t)(0)) < 0; | |
8968 | int flgn = ((int32_t)(newv)) < 0; | |
8969 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
8970 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
8971 | COPY_CARRY; | |
8972 | SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0)); | |
8973 | SET_NFLG (((int32_t)(newv)) < 0); | |
8974 | m68k_write_memory_32(srca,newv); | |
8975 | }}}}}m68k_incpc(4); | |
8976 | return 24; | |
8977 | } | |
8978 | unsigned long CPUFUNC(op_40b9_4)(uint32_t opcode) /* NEGX */ | |
8979 | { | |
8980 | OpcodeFamily = 16; CurrentInstrCycles = 28; | |
8981 | {{ uint32_t srca = get_ilong(2); | |
8982 | { int32_t src = m68k_read_memory_32(srca); | |
8983 | { uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); | |
8984 | { int flgs = ((int32_t)(src)) < 0; | |
8985 | int flgo = ((int32_t)(0)) < 0; | |
8986 | int flgn = ((int32_t)(newv)) < 0; | |
8987 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
8988 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
8989 | COPY_CARRY; | |
8990 | SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0)); | |
8991 | SET_NFLG (((int32_t)(newv)) < 0); | |
8992 | m68k_write_memory_32(srca,newv); | |
8993 | }}}}}m68k_incpc(6); | |
8994 | return 28; | |
8995 | } | |
8996 | unsigned long CPUFUNC(op_40c0_4)(uint32_t opcode) /* MVSR2 */ | |
8997 | { | |
8998 | uint32_t srcreg = (opcode & 7); | |
8999 | OpcodeFamily = 32; CurrentInstrCycles = 6; | |
9000 | {{ MakeSR(); | |
9001 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((regs.sr) & 0xffff); | |
9002 | }}m68k_incpc(2); | |
9003 | return 6; | |
9004 | } | |
9005 | unsigned long CPUFUNC(op_40d0_4)(uint32_t opcode) /* MVSR2 */ | |
9006 | { | |
9007 | uint32_t srcreg = (opcode & 7); | |
9008 | OpcodeFamily = 32; CurrentInstrCycles = 12; | |
9009 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
9010 | MakeSR(); | |
9011 | m68k_write_memory_16(srca,regs.sr); | |
9012 | }}m68k_incpc(2); | |
9013 | return 12; | |
9014 | } | |
9015 | unsigned long CPUFUNC(op_40d8_4)(uint32_t opcode) /* MVSR2 */ | |
9016 | { | |
9017 | uint32_t srcreg = (opcode & 7); | |
9018 | OpcodeFamily = 32; CurrentInstrCycles = 12; | |
9019 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
9020 | m68k_areg(regs, srcreg) += 2; | |
9021 | MakeSR(); | |
9022 | m68k_write_memory_16(srca,regs.sr); | |
9023 | }}m68k_incpc(2); | |
9024 | return 12; | |
9025 | } | |
9026 | unsigned long CPUFUNC(op_40e0_4)(uint32_t opcode) /* MVSR2 */ | |
9027 | { | |
9028 | uint32_t srcreg = (opcode & 7); | |
9029 | OpcodeFamily = 32; CurrentInstrCycles = 14; | |
9030 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
9031 | m68k_areg (regs, srcreg) = srca; | |
9032 | MakeSR(); | |
9033 | m68k_write_memory_16(srca,regs.sr); | |
9034 | }}m68k_incpc(2); | |
9035 | return 14; | |
9036 | } | |
9037 | unsigned long CPUFUNC(op_40e8_4)(uint32_t opcode) /* MVSR2 */ | |
9038 | { | |
9039 | uint32_t srcreg = (opcode & 7); | |
9040 | OpcodeFamily = 32; CurrentInstrCycles = 16; | |
9041 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
9042 | MakeSR(); | |
9043 | m68k_write_memory_16(srca,regs.sr); | |
9044 | }}m68k_incpc(4); | |
9045 | return 16; | |
9046 | } | |
9047 | unsigned long CPUFUNC(op_40f0_4)(uint32_t opcode) /* MVSR2 */ | |
9048 | { | |
9049 | uint32_t srcreg = (opcode & 7); | |
9050 | OpcodeFamily = 32; CurrentInstrCycles = 18; | |
9051 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
9052 | BusCyclePenalty += 2; | |
9053 | MakeSR(); | |
9054 | m68k_write_memory_16(srca,regs.sr); | |
9055 | }}m68k_incpc(4); | |
9056 | return 18; | |
9057 | } | |
9058 | unsigned long CPUFUNC(op_40f8_4)(uint32_t opcode) /* MVSR2 */ | |
9059 | { | |
9060 | OpcodeFamily = 32; CurrentInstrCycles = 16; | |
9061 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
9062 | MakeSR(); | |
9063 | m68k_write_memory_16(srca,regs.sr); | |
9064 | }}m68k_incpc(4); | |
9065 | return 16; | |
9066 | } | |
9067 | unsigned long CPUFUNC(op_40f9_4)(uint32_t opcode) /* MVSR2 */ | |
9068 | { | |
9069 | OpcodeFamily = 32; CurrentInstrCycles = 20; | |
9070 | {{ uint32_t srca = get_ilong(2); | |
9071 | MakeSR(); | |
9072 | m68k_write_memory_16(srca,regs.sr); | |
9073 | }}m68k_incpc(6); | |
9074 | return 20; | |
9075 | } | |
9076 | unsigned long CPUFUNC(op_4180_4)(uint32_t opcode) /* CHK */ | |
9077 | { | |
9078 | uint32_t srcreg = (opcode & 7); | |
9079 | uint32_t dstreg = (opcode >> 9) & 7; | |
9080 | OpcodeFamily = 80; CurrentInstrCycles = 10; | |
9081 | { uint32_t oldpc = m68k_getpc(); | |
9082 | { int16_t src = m68k_dreg(regs, srcreg); | |
9083 | { int16_t dst = m68k_dreg(regs, dstreg); | |
9084 | m68k_incpc(2); | |
9085 | if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel587; } | |
9086 | else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel587; } | |
9087 | }}}endlabel587: ; | |
9088 | return 10; | |
9089 | } | |
9090 | unsigned long CPUFUNC(op_4190_4)(uint32_t opcode) /* CHK */ | |
9091 | { | |
9092 | uint32_t srcreg = (opcode & 7); | |
9093 | uint32_t dstreg = (opcode >> 9) & 7; | |
9094 | OpcodeFamily = 80; CurrentInstrCycles = 14; | |
9095 | { uint32_t oldpc = m68k_getpc(); | |
9096 | { uint32_t srca = m68k_areg(regs, srcreg); | |
9097 | { int16_t src = m68k_read_memory_16(srca); | |
9098 | { int16_t dst = m68k_dreg(regs, dstreg); | |
9099 | m68k_incpc(2); | |
9100 | if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel588; } | |
9101 | else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel588; } | |
9102 | }}}}endlabel588: ; | |
9103 | return 14; | |
9104 | } | |
9105 | unsigned long CPUFUNC(op_4198_4)(uint32_t opcode) /* CHK */ | |
9106 | { | |
9107 | uint32_t srcreg = (opcode & 7); | |
9108 | uint32_t dstreg = (opcode >> 9) & 7; | |
9109 | OpcodeFamily = 80; CurrentInstrCycles = 14; | |
9110 | { uint32_t oldpc = m68k_getpc(); | |
9111 | { uint32_t srca = m68k_areg(regs, srcreg); | |
9112 | { int16_t src = m68k_read_memory_16(srca); | |
9113 | m68k_areg(regs, srcreg) += 2; | |
9114 | { int16_t dst = m68k_dreg(regs, dstreg); | |
9115 | m68k_incpc(2); | |
9116 | if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel589; } | |
9117 | else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel589; } | |
9118 | }}}}endlabel589: ; | |
9119 | return 14; | |
9120 | } | |
9121 | unsigned long CPUFUNC(op_41a0_4)(uint32_t opcode) /* CHK */ | |
9122 | { | |
9123 | uint32_t srcreg = (opcode & 7); | |
9124 | uint32_t dstreg = (opcode >> 9) & 7; | |
9125 | OpcodeFamily = 80; CurrentInstrCycles = 16; | |
9126 | { uint32_t oldpc = m68k_getpc(); | |
9127 | { uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
9128 | { int16_t src = m68k_read_memory_16(srca); | |
9129 | m68k_areg (regs, srcreg) = srca; | |
9130 | { int16_t dst = m68k_dreg(regs, dstreg); | |
9131 | m68k_incpc(2); | |
9132 | if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel590; } | |
9133 | else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel590; } | |
9134 | }}}}endlabel590: ; | |
9135 | return 16; | |
9136 | } | |
9137 | unsigned long CPUFUNC(op_41a8_4)(uint32_t opcode) /* CHK */ | |
9138 | { | |
9139 | uint32_t srcreg = (opcode & 7); | |
9140 | uint32_t dstreg = (opcode >> 9) & 7; | |
9141 | OpcodeFamily = 80; CurrentInstrCycles = 18; | |
9142 | { uint32_t oldpc = m68k_getpc(); | |
9143 | { uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
9144 | { int16_t src = m68k_read_memory_16(srca); | |
9145 | { int16_t dst = m68k_dreg(regs, dstreg); | |
9146 | m68k_incpc(4); | |
9147 | if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel591; } | |
9148 | else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel591; } | |
9149 | }}}}endlabel591: ; | |
9150 | return 18; | |
9151 | } | |
9152 | unsigned long CPUFUNC(op_41b0_4)(uint32_t opcode) /* CHK */ | |
9153 | { | |
9154 | uint32_t srcreg = (opcode & 7); | |
9155 | uint32_t dstreg = (opcode >> 9) & 7; | |
9156 | OpcodeFamily = 80; CurrentInstrCycles = 20; | |
9157 | { uint32_t oldpc = m68k_getpc(); | |
9158 | { uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
9159 | BusCyclePenalty += 2; | |
9160 | { int16_t src = m68k_read_memory_16(srca); | |
9161 | { int16_t dst = m68k_dreg(regs, dstreg); | |
9162 | m68k_incpc(4); | |
9163 | if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel592; } | |
9164 | else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel592; } | |
9165 | }}}}endlabel592: ; | |
9166 | return 20; | |
9167 | } | |
9168 | unsigned long CPUFUNC(op_41b8_4)(uint32_t opcode) /* CHK */ | |
9169 | { | |
9170 | uint32_t dstreg = (opcode >> 9) & 7; | |
9171 | OpcodeFamily = 80; CurrentInstrCycles = 18; | |
9172 | { uint32_t oldpc = m68k_getpc(); | |
9173 | { uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
9174 | { int16_t src = m68k_read_memory_16(srca); | |
9175 | { int16_t dst = m68k_dreg(regs, dstreg); | |
9176 | m68k_incpc(4); | |
9177 | if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel593; } | |
9178 | else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel593; } | |
9179 | }}}}endlabel593: ; | |
9180 | return 18; | |
9181 | } | |
9182 | unsigned long CPUFUNC(op_41b9_4)(uint32_t opcode) /* CHK */ | |
9183 | { | |
9184 | uint32_t dstreg = (opcode >> 9) & 7; | |
9185 | OpcodeFamily = 80; CurrentInstrCycles = 22; | |
9186 | { uint32_t oldpc = m68k_getpc(); | |
9187 | { uint32_t srca = get_ilong(2); | |
9188 | { int16_t src = m68k_read_memory_16(srca); | |
9189 | { int16_t dst = m68k_dreg(regs, dstreg); | |
9190 | m68k_incpc(6); | |
9191 | if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel594; } | |
9192 | else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel594; } | |
9193 | }}}}endlabel594: ; | |
9194 | return 22; | |
9195 | } | |
9196 | unsigned long CPUFUNC(op_41ba_4)(uint32_t opcode) /* CHK */ | |
9197 | { | |
9198 | uint32_t dstreg = (opcode >> 9) & 7; | |
9199 | OpcodeFamily = 80; CurrentInstrCycles = 18; | |
9200 | { uint32_t oldpc = m68k_getpc(); | |
9201 | { uint32_t srca = m68k_getpc () + 2; | |
9202 | srca += (int32_t)(int16_t)get_iword(2); | |
9203 | { int16_t src = m68k_read_memory_16(srca); | |
9204 | { int16_t dst = m68k_dreg(regs, dstreg); | |
9205 | m68k_incpc(4); | |
9206 | if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel595; } | |
9207 | else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel595; } | |
9208 | }}}}endlabel595: ; | |
9209 | return 18; | |
9210 | } | |
9211 | unsigned long CPUFUNC(op_41bb_4)(uint32_t opcode) /* CHK */ | |
9212 | { | |
9213 | uint32_t dstreg = (opcode >> 9) & 7; | |
9214 | OpcodeFamily = 80; CurrentInstrCycles = 20; | |
9215 | { uint32_t oldpc = m68k_getpc(); | |
9216 | { uint32_t tmppc = m68k_getpc() + 2; | |
9217 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
9218 | BusCyclePenalty += 2; | |
9219 | { int16_t src = m68k_read_memory_16(srca); | |
9220 | { int16_t dst = m68k_dreg(regs, dstreg); | |
9221 | m68k_incpc(4); | |
9222 | if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel596; } | |
9223 | else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel596; } | |
9224 | }}}}endlabel596: ; | |
9225 | return 20; | |
9226 | } | |
9227 | unsigned long CPUFUNC(op_41bc_4)(uint32_t opcode) /* CHK */ | |
9228 | { | |
9229 | uint32_t dstreg = (opcode >> 9) & 7; | |
9230 | OpcodeFamily = 80; CurrentInstrCycles = 14; | |
9231 | { uint32_t oldpc = m68k_getpc(); | |
9232 | { int16_t src = get_iword(2); | |
9233 | { int16_t dst = m68k_dreg(regs, dstreg); | |
9234 | m68k_incpc(4); | |
9235 | if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel597; } | |
9236 | else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel597; } | |
9237 | }}}endlabel597: ; | |
9238 | return 14; | |
9239 | } | |
9240 | unsigned long CPUFUNC(op_41d0_4)(uint32_t opcode) /* LEA */ | |
9241 | { | |
9242 | uint32_t srcreg = (opcode & 7); | |
9243 | uint32_t dstreg = (opcode >> 9) & 7; | |
9244 | OpcodeFamily = 56; CurrentInstrCycles = 4; | |
9245 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
9246 | { m68k_areg(regs, dstreg) = (srca); | |
9247 | }}}m68k_incpc(2); | |
9248 | return 4; | |
9249 | } | |
9250 | unsigned long CPUFUNC(op_41e8_4)(uint32_t opcode) /* LEA */ | |
9251 | { | |
9252 | uint32_t srcreg = (opcode & 7); | |
9253 | uint32_t dstreg = (opcode >> 9) & 7; | |
9254 | OpcodeFamily = 56; CurrentInstrCycles = 8; | |
9255 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
9256 | { m68k_areg(regs, dstreg) = (srca); | |
9257 | }}}m68k_incpc(4); | |
9258 | return 8; | |
9259 | } | |
9260 | unsigned long CPUFUNC(op_41f0_4)(uint32_t opcode) /* LEA */ | |
9261 | { | |
9262 | uint32_t srcreg = (opcode & 7); | |
9263 | uint32_t dstreg = (opcode >> 9) & 7; | |
9264 | OpcodeFamily = 56; CurrentInstrCycles = 14; | |
9265 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
9266 | BusCyclePenalty += 2; | |
9267 | { m68k_areg(regs, dstreg) = (srca); | |
9268 | }}}m68k_incpc(4); | |
9269 | return 14; | |
9270 | } | |
9271 | unsigned long CPUFUNC(op_41f8_4)(uint32_t opcode) /* LEA */ | |
9272 | { | |
9273 | uint32_t dstreg = (opcode >> 9) & 7; | |
9274 | OpcodeFamily = 56; CurrentInstrCycles = 8; | |
9275 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
9276 | { m68k_areg(regs, dstreg) = (srca); | |
9277 | }}}m68k_incpc(4); | |
9278 | return 8; | |
9279 | } | |
9280 | unsigned long CPUFUNC(op_41f9_4)(uint32_t opcode) /* LEA */ | |
9281 | { | |
9282 | uint32_t dstreg = (opcode >> 9) & 7; | |
9283 | OpcodeFamily = 56; CurrentInstrCycles = 12; | |
9284 | {{ uint32_t srca = get_ilong(2); | |
9285 | { m68k_areg(regs, dstreg) = (srca); | |
9286 | }}}m68k_incpc(6); | |
9287 | return 12; | |
9288 | } | |
9289 | unsigned long CPUFUNC(op_41fa_4)(uint32_t opcode) /* LEA */ | |
9290 | { | |
9291 | uint32_t dstreg = (opcode >> 9) & 7; | |
9292 | OpcodeFamily = 56; CurrentInstrCycles = 8; | |
9293 | {{ uint32_t srca = m68k_getpc () + 2; | |
9294 | srca += (int32_t)(int16_t)get_iword(2); | |
9295 | { m68k_areg(regs, dstreg) = (srca); | |
9296 | }}}m68k_incpc(4); | |
9297 | return 8; | |
9298 | } | |
9299 | unsigned long CPUFUNC(op_41fb_4)(uint32_t opcode) /* LEA */ | |
9300 | { | |
9301 | uint32_t dstreg = (opcode >> 9) & 7; | |
9302 | OpcodeFamily = 56; CurrentInstrCycles = 14; | |
9303 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
9304 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
9305 | BusCyclePenalty += 2; | |
9306 | { m68k_areg(regs, dstreg) = (srca); | |
9307 | }}}m68k_incpc(4); | |
9308 | return 14; | |
9309 | } | |
9310 | unsigned long CPUFUNC(op_4200_4)(uint32_t opcode) /* CLR */ | |
9311 | { | |
9312 | uint32_t srcreg = (opcode & 7); | |
9313 | OpcodeFamily = 18; CurrentInstrCycles = 4; | |
9314 | {{ CLEAR_CZNV; | |
9315 | SET_ZFLG (((int8_t)(0)) == 0); | |
9316 | SET_NFLG (((int8_t)(0)) < 0); | |
9317 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((0) & 0xff); | |
9318 | }}m68k_incpc(2); | |
9319 | return 4; | |
9320 | } | |
9321 | unsigned long CPUFUNC(op_4210_4)(uint32_t opcode) /* CLR */ | |
9322 | { | |
9323 | uint32_t srcreg = (opcode & 7); | |
9324 | OpcodeFamily = 18; CurrentInstrCycles = 12; | |
9325 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
9326 | int8_t src = m68k_read_memory_8(srca); | |
9327 | CLEAR_CZNV; | |
9328 | SET_ZFLG (((int8_t)(0)) == 0); | |
9329 | SET_NFLG (((int8_t)(0)) < 0); | |
9330 | m68k_write_memory_8(srca,0); | |
9331 | }}m68k_incpc(2); | |
9332 | return 12; | |
9333 | } | |
9334 | unsigned long CPUFUNC(op_4218_4)(uint32_t opcode) /* CLR */ | |
9335 | { | |
9336 | uint32_t srcreg = (opcode & 7); | |
9337 | OpcodeFamily = 18; CurrentInstrCycles = 12; | |
9338 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
9339 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
9340 | int8_t src = m68k_read_memory_8(srca); | |
9341 | CLEAR_CZNV; | |
9342 | SET_ZFLG (((int8_t)(0)) == 0); | |
9343 | SET_NFLG (((int8_t)(0)) < 0); | |
9344 | m68k_write_memory_8(srca,0); | |
9345 | }}m68k_incpc(2); | |
9346 | return 12; | |
9347 | } | |
9348 | unsigned long CPUFUNC(op_4220_4)(uint32_t opcode) /* CLR */ | |
9349 | { | |
9350 | uint32_t srcreg = (opcode & 7); | |
9351 | OpcodeFamily = 18; CurrentInstrCycles = 14; | |
9352 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
9353 | m68k_areg (regs, srcreg) = srca; | |
9354 | int8_t src = m68k_read_memory_8(srca); | |
9355 | CLEAR_CZNV; | |
9356 | SET_ZFLG (((int8_t)(0)) == 0); | |
9357 | SET_NFLG (((int8_t)(0)) < 0); | |
9358 | m68k_write_memory_8(srca,0); | |
9359 | }}m68k_incpc(2); | |
9360 | return 14; | |
9361 | } | |
9362 | unsigned long CPUFUNC(op_4228_4)(uint32_t opcode) /* CLR */ | |
9363 | { | |
9364 | uint32_t srcreg = (opcode & 7); | |
9365 | OpcodeFamily = 18; CurrentInstrCycles = 16; | |
9366 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
9367 | int8_t src = m68k_read_memory_8(srca); | |
9368 | CLEAR_CZNV; | |
9369 | SET_ZFLG (((int8_t)(0)) == 0); | |
9370 | SET_NFLG (((int8_t)(0)) < 0); | |
9371 | m68k_write_memory_8(srca,0); | |
9372 | }}m68k_incpc(4); | |
9373 | return 16; | |
9374 | } | |
9375 | unsigned long CPUFUNC(op_4230_4)(uint32_t opcode) /* CLR */ | |
9376 | { | |
9377 | uint32_t srcreg = (opcode & 7); | |
9378 | OpcodeFamily = 18; CurrentInstrCycles = 18; | |
9379 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
9380 | BusCyclePenalty += 2; | |
9381 | int8_t src = m68k_read_memory_8(srca); | |
9382 | CLEAR_CZNV; | |
9383 | SET_ZFLG (((int8_t)(0)) == 0); | |
9384 | SET_NFLG (((int8_t)(0)) < 0); | |
9385 | m68k_write_memory_8(srca,0); | |
9386 | }}m68k_incpc(4); | |
9387 | return 18; | |
9388 | } | |
9389 | unsigned long CPUFUNC(op_4238_4)(uint32_t opcode) /* CLR */ | |
9390 | { | |
9391 | OpcodeFamily = 18; CurrentInstrCycles = 16; | |
9392 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
9393 | int8_t src = m68k_read_memory_8(srca); | |
9394 | CLEAR_CZNV; | |
9395 | SET_ZFLG (((int8_t)(0)) == 0); | |
9396 | SET_NFLG (((int8_t)(0)) < 0); | |
9397 | m68k_write_memory_8(srca,0); | |
9398 | }}m68k_incpc(4); | |
9399 | return 16; | |
9400 | } | |
9401 | unsigned long CPUFUNC(op_4239_4)(uint32_t opcode) /* CLR */ | |
9402 | { | |
9403 | OpcodeFamily = 18; CurrentInstrCycles = 20; | |
9404 | {{ uint32_t srca = get_ilong(2); | |
9405 | int8_t src = m68k_read_memory_8(srca); | |
9406 | CLEAR_CZNV; | |
9407 | SET_ZFLG (((int8_t)(0)) == 0); | |
9408 | SET_NFLG (((int8_t)(0)) < 0); | |
9409 | m68k_write_memory_8(srca,0); | |
9410 | }}m68k_incpc(6); | |
9411 | return 20; | |
9412 | } | |
9413 | unsigned long CPUFUNC(op_4240_4)(uint32_t opcode) /* CLR */ | |
9414 | { | |
9415 | uint32_t srcreg = (opcode & 7); | |
9416 | OpcodeFamily = 18; CurrentInstrCycles = 4; | |
9417 | {{ CLEAR_CZNV; | |
9418 | SET_ZFLG (((int16_t)(0)) == 0); | |
9419 | SET_NFLG (((int16_t)(0)) < 0); | |
9420 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((0) & 0xffff); | |
9421 | }}m68k_incpc(2); | |
9422 | return 4; | |
9423 | } | |
9424 | unsigned long CPUFUNC(op_4250_4)(uint32_t opcode) /* CLR */ | |
9425 | { | |
9426 | uint32_t srcreg = (opcode & 7); | |
9427 | OpcodeFamily = 18; CurrentInstrCycles = 12; | |
9428 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
9429 | int16_t src = m68k_read_memory_16(srca); | |
9430 | CLEAR_CZNV; | |
9431 | SET_ZFLG (((int16_t)(0)) == 0); | |
9432 | SET_NFLG (((int16_t)(0)) < 0); | |
9433 | m68k_write_memory_16(srca,0); | |
9434 | }}m68k_incpc(2); | |
9435 | return 12; | |
9436 | } | |
9437 | unsigned long CPUFUNC(op_4258_4)(uint32_t opcode) /* CLR */ | |
9438 | { | |
9439 | uint32_t srcreg = (opcode & 7); | |
9440 | OpcodeFamily = 18; CurrentInstrCycles = 12; | |
9441 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
9442 | m68k_areg(regs, srcreg) += 2; | |
9443 | int16_t src = m68k_read_memory_16(srca); | |
9444 | CLEAR_CZNV; | |
9445 | SET_ZFLG (((int16_t)(0)) == 0); | |
9446 | SET_NFLG (((int16_t)(0)) < 0); | |
9447 | m68k_write_memory_16(srca,0); | |
9448 | }}m68k_incpc(2); | |
9449 | return 12; | |
9450 | } | |
9451 | unsigned long CPUFUNC(op_4260_4)(uint32_t opcode) /* CLR */ | |
9452 | { | |
9453 | uint32_t srcreg = (opcode & 7); | |
9454 | OpcodeFamily = 18; CurrentInstrCycles = 14; | |
9455 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
9456 | m68k_areg (regs, srcreg) = srca; | |
9457 | int16_t src = m68k_read_memory_16(srca); | |
9458 | CLEAR_CZNV; | |
9459 | SET_ZFLG (((int16_t)(0)) == 0); | |
9460 | SET_NFLG (((int16_t)(0)) < 0); | |
9461 | m68k_write_memory_16(srca,0); | |
9462 | }}m68k_incpc(2); | |
9463 | return 14; | |
9464 | } | |
9465 | unsigned long CPUFUNC(op_4268_4)(uint32_t opcode) /* CLR */ | |
9466 | { | |
9467 | uint32_t srcreg = (opcode & 7); | |
9468 | OpcodeFamily = 18; CurrentInstrCycles = 16; | |
9469 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
9470 | int16_t src = m68k_read_memory_16(srca); | |
9471 | CLEAR_CZNV; | |
9472 | SET_ZFLG (((int16_t)(0)) == 0); | |
9473 | SET_NFLG (((int16_t)(0)) < 0); | |
9474 | m68k_write_memory_16(srca,0); | |
9475 | }}m68k_incpc(4); | |
9476 | return 16; | |
9477 | } | |
9478 | #endif | |
9479 | ||
9480 | #ifdef PART_4 | |
9481 | unsigned long CPUFUNC(op_4270_4)(uint32_t opcode) /* CLR */ | |
9482 | { | |
9483 | uint32_t srcreg = (opcode & 7); | |
9484 | OpcodeFamily = 18; CurrentInstrCycles = 18; | |
9485 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
9486 | BusCyclePenalty += 2; | |
9487 | int16_t src = m68k_read_memory_16(srca); | |
9488 | CLEAR_CZNV; | |
9489 | SET_ZFLG (((int16_t)(0)) == 0); | |
9490 | SET_NFLG (((int16_t)(0)) < 0); | |
9491 | m68k_write_memory_16(srca,0); | |
9492 | }}m68k_incpc(4); | |
9493 | return 18; | |
9494 | } | |
9495 | unsigned long CPUFUNC(op_4278_4)(uint32_t opcode) /* CLR */ | |
9496 | { | |
9497 | OpcodeFamily = 18; CurrentInstrCycles = 16; | |
9498 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
9499 | int16_t src = m68k_read_memory_16(srca); | |
9500 | CLEAR_CZNV; | |
9501 | SET_ZFLG (((int16_t)(0)) == 0); | |
9502 | SET_NFLG (((int16_t)(0)) < 0); | |
9503 | m68k_write_memory_16(srca,0); | |
9504 | }}m68k_incpc(4); | |
9505 | return 16; | |
9506 | } | |
9507 | unsigned long CPUFUNC(op_4279_4)(uint32_t opcode) /* CLR */ | |
9508 | { | |
9509 | OpcodeFamily = 18; CurrentInstrCycles = 20; | |
9510 | {{ uint32_t srca = get_ilong(2); | |
9511 | int16_t src = m68k_read_memory_16(srca); | |
9512 | CLEAR_CZNV; | |
9513 | SET_ZFLG (((int16_t)(0)) == 0); | |
9514 | SET_NFLG (((int16_t)(0)) < 0); | |
9515 | m68k_write_memory_16(srca,0); | |
9516 | }}m68k_incpc(6); | |
9517 | return 20; | |
9518 | } | |
9519 | unsigned long CPUFUNC(op_4280_4)(uint32_t opcode) /* CLR */ | |
9520 | { | |
9521 | uint32_t srcreg = (opcode & 7); | |
9522 | OpcodeFamily = 18; CurrentInstrCycles = 6; | |
9523 | {{ CLEAR_CZNV; | |
9524 | SET_ZFLG (((int32_t)(0)) == 0); | |
9525 | SET_NFLG (((int32_t)(0)) < 0); | |
9526 | m68k_dreg(regs, srcreg) = (0); | |
9527 | }}m68k_incpc(2); | |
9528 | return 6; | |
9529 | } | |
9530 | unsigned long CPUFUNC(op_4290_4)(uint32_t opcode) /* CLR */ | |
9531 | { | |
9532 | uint32_t srcreg = (opcode & 7); | |
9533 | OpcodeFamily = 18; CurrentInstrCycles = 20; | |
9534 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
9535 | int32_t src = m68k_read_memory_32(srca); | |
9536 | CLEAR_CZNV; | |
9537 | SET_ZFLG (((int32_t)(0)) == 0); | |
9538 | SET_NFLG (((int32_t)(0)) < 0); | |
9539 | m68k_write_memory_32(srca,0); | |
9540 | }}m68k_incpc(2); | |
9541 | return 20; | |
9542 | } | |
9543 | unsigned long CPUFUNC(op_4298_4)(uint32_t opcode) /* CLR */ | |
9544 | { | |
9545 | uint32_t srcreg = (opcode & 7); | |
9546 | OpcodeFamily = 18; CurrentInstrCycles = 20; | |
9547 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
9548 | m68k_areg(regs, srcreg) += 4; | |
9549 | int32_t src = m68k_read_memory_32(srca); | |
9550 | CLEAR_CZNV; | |
9551 | SET_ZFLG (((int32_t)(0)) == 0); | |
9552 | SET_NFLG (((int32_t)(0)) < 0); | |
9553 | m68k_write_memory_32(srca,0); | |
9554 | }}m68k_incpc(2); | |
9555 | return 20; | |
9556 | } | |
9557 | unsigned long CPUFUNC(op_42a0_4)(uint32_t opcode) /* CLR */ | |
9558 | { | |
9559 | uint32_t srcreg = (opcode & 7); | |
9560 | OpcodeFamily = 18; CurrentInstrCycles = 22; | |
9561 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 4; | |
9562 | m68k_areg (regs, srcreg) = srca; | |
9563 | int32_t src = m68k_read_memory_32(srca); | |
9564 | CLEAR_CZNV; | |
9565 | SET_ZFLG (((int32_t)(0)) == 0); | |
9566 | SET_NFLG (((int32_t)(0)) < 0); | |
9567 | m68k_write_memory_32(srca,0); | |
9568 | }}m68k_incpc(2); | |
9569 | return 22; | |
9570 | } | |
9571 | unsigned long CPUFUNC(op_42a8_4)(uint32_t opcode) /* CLR */ | |
9572 | { | |
9573 | uint32_t srcreg = (opcode & 7); | |
9574 | OpcodeFamily = 18; CurrentInstrCycles = 24; | |
9575 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
9576 | int32_t src = m68k_read_memory_32(srca); | |
9577 | CLEAR_CZNV; | |
9578 | SET_ZFLG (((int32_t)(0)) == 0); | |
9579 | SET_NFLG (((int32_t)(0)) < 0); | |
9580 | m68k_write_memory_32(srca,0); | |
9581 | }}m68k_incpc(4); | |
9582 | return 24; | |
9583 | } | |
9584 | unsigned long CPUFUNC(op_42b0_4)(uint32_t opcode) /* CLR */ | |
9585 | { | |
9586 | uint32_t srcreg = (opcode & 7); | |
9587 | OpcodeFamily = 18; CurrentInstrCycles = 26; | |
9588 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
9589 | BusCyclePenalty += 2; | |
9590 | int32_t src = m68k_read_memory_32(srca); | |
9591 | CLEAR_CZNV; | |
9592 | SET_ZFLG (((int32_t)(0)) == 0); | |
9593 | SET_NFLG (((int32_t)(0)) < 0); | |
9594 | m68k_write_memory_32(srca,0); | |
9595 | }}m68k_incpc(4); | |
9596 | return 26; | |
9597 | } | |
9598 | unsigned long CPUFUNC(op_42b8_4)(uint32_t opcode) /* CLR */ | |
9599 | { | |
9600 | OpcodeFamily = 18; CurrentInstrCycles = 24; | |
9601 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
9602 | int32_t src = m68k_read_memory_32(srca); | |
9603 | CLEAR_CZNV; | |
9604 | SET_ZFLG (((int32_t)(0)) == 0); | |
9605 | SET_NFLG (((int32_t)(0)) < 0); | |
9606 | m68k_write_memory_32(srca,0); | |
9607 | }}m68k_incpc(4); | |
9608 | return 24; | |
9609 | } | |
9610 | unsigned long CPUFUNC(op_42b9_4)(uint32_t opcode) /* CLR */ | |
9611 | { | |
9612 | OpcodeFamily = 18; CurrentInstrCycles = 28; | |
9613 | {{ uint32_t srca = get_ilong(2); | |
9614 | int32_t src = m68k_read_memory_32(srca); | |
9615 | CLEAR_CZNV; | |
9616 | SET_ZFLG (((int32_t)(0)) == 0); | |
9617 | SET_NFLG (((int32_t)(0)) < 0); | |
9618 | m68k_write_memory_32(srca,0); | |
9619 | }}m68k_incpc(6); | |
9620 | return 28; | |
9621 | } | |
9622 | unsigned long CPUFUNC(op_4400_4)(uint32_t opcode) /* NEG */ | |
9623 | { | |
9624 | uint32_t srcreg = (opcode & 7); | |
9625 | OpcodeFamily = 15; CurrentInstrCycles = 4; | |
9626 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
9627 | {{uint32_t dst = ((int8_t)(0)) - ((int8_t)(src)); | |
9628 | { int flgs = ((int8_t)(src)) < 0; | |
9629 | int flgo = ((int8_t)(0)) < 0; | |
9630 | int flgn = ((int8_t)(dst)) < 0; | |
9631 | SET_ZFLG (((int8_t)(dst)) == 0); | |
9632 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
9633 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(0))); | |
9634 | COPY_CARRY; | |
9635 | SET_NFLG (flgn != 0); | |
9636 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((dst) & 0xff); | |
9637 | }}}}}m68k_incpc(2); | |
9638 | return 4; | |
9639 | } | |
9640 | unsigned long CPUFUNC(op_4410_4)(uint32_t opcode) /* NEG */ | |
9641 | { | |
9642 | uint32_t srcreg = (opcode & 7); | |
9643 | OpcodeFamily = 15; CurrentInstrCycles = 12; | |
9644 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
9645 | { int8_t src = m68k_read_memory_8(srca); | |
9646 | {{uint32_t dst = ((int8_t)(0)) - ((int8_t)(src)); | |
9647 | { int flgs = ((int8_t)(src)) < 0; | |
9648 | int flgo = ((int8_t)(0)) < 0; | |
9649 | int flgn = ((int8_t)(dst)) < 0; | |
9650 | SET_ZFLG (((int8_t)(dst)) == 0); | |
9651 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
9652 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(0))); | |
9653 | COPY_CARRY; | |
9654 | SET_NFLG (flgn != 0); | |
9655 | m68k_write_memory_8(srca,dst); | |
9656 | }}}}}}m68k_incpc(2); | |
9657 | return 12; | |
9658 | } | |
9659 | unsigned long CPUFUNC(op_4418_4)(uint32_t opcode) /* NEG */ | |
9660 | { | |
9661 | uint32_t srcreg = (opcode & 7); | |
9662 | OpcodeFamily = 15; CurrentInstrCycles = 12; | |
9663 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
9664 | { int8_t src = m68k_read_memory_8(srca); | |
9665 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
9666 | {{uint32_t dst = ((int8_t)(0)) - ((int8_t)(src)); | |
9667 | { int flgs = ((int8_t)(src)) < 0; | |
9668 | int flgo = ((int8_t)(0)) < 0; | |
9669 | int flgn = ((int8_t)(dst)) < 0; | |
9670 | SET_ZFLG (((int8_t)(dst)) == 0); | |
9671 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
9672 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(0))); | |
9673 | COPY_CARRY; | |
9674 | SET_NFLG (flgn != 0); | |
9675 | m68k_write_memory_8(srca,dst); | |
9676 | }}}}}}m68k_incpc(2); | |
9677 | return 12; | |
9678 | } | |
9679 | unsigned long CPUFUNC(op_4420_4)(uint32_t opcode) /* NEG */ | |
9680 | { | |
9681 | uint32_t srcreg = (opcode & 7); | |
9682 | OpcodeFamily = 15; CurrentInstrCycles = 14; | |
9683 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
9684 | { int8_t src = m68k_read_memory_8(srca); | |
9685 | m68k_areg (regs, srcreg) = srca; | |
9686 | {{uint32_t dst = ((int8_t)(0)) - ((int8_t)(src)); | |
9687 | { int flgs = ((int8_t)(src)) < 0; | |
9688 | int flgo = ((int8_t)(0)) < 0; | |
9689 | int flgn = ((int8_t)(dst)) < 0; | |
9690 | SET_ZFLG (((int8_t)(dst)) == 0); | |
9691 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
9692 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(0))); | |
9693 | COPY_CARRY; | |
9694 | SET_NFLG (flgn != 0); | |
9695 | m68k_write_memory_8(srca,dst); | |
9696 | }}}}}}m68k_incpc(2); | |
9697 | return 14; | |
9698 | } | |
9699 | unsigned long CPUFUNC(op_4428_4)(uint32_t opcode) /* NEG */ | |
9700 | { | |
9701 | uint32_t srcreg = (opcode & 7); | |
9702 | OpcodeFamily = 15; CurrentInstrCycles = 16; | |
9703 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
9704 | { int8_t src = m68k_read_memory_8(srca); | |
9705 | {{uint32_t dst = ((int8_t)(0)) - ((int8_t)(src)); | |
9706 | { int flgs = ((int8_t)(src)) < 0; | |
9707 | int flgo = ((int8_t)(0)) < 0; | |
9708 | int flgn = ((int8_t)(dst)) < 0; | |
9709 | SET_ZFLG (((int8_t)(dst)) == 0); | |
9710 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
9711 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(0))); | |
9712 | COPY_CARRY; | |
9713 | SET_NFLG (flgn != 0); | |
9714 | m68k_write_memory_8(srca,dst); | |
9715 | }}}}}}m68k_incpc(4); | |
9716 | return 16; | |
9717 | } | |
9718 | unsigned long CPUFUNC(op_4430_4)(uint32_t opcode) /* NEG */ | |
9719 | { | |
9720 | uint32_t srcreg = (opcode & 7); | |
9721 | OpcodeFamily = 15; CurrentInstrCycles = 18; | |
9722 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
9723 | BusCyclePenalty += 2; | |
9724 | { int8_t src = m68k_read_memory_8(srca); | |
9725 | {{uint32_t dst = ((int8_t)(0)) - ((int8_t)(src)); | |
9726 | { int flgs = ((int8_t)(src)) < 0; | |
9727 | int flgo = ((int8_t)(0)) < 0; | |
9728 | int flgn = ((int8_t)(dst)) < 0; | |
9729 | SET_ZFLG (((int8_t)(dst)) == 0); | |
9730 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
9731 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(0))); | |
9732 | COPY_CARRY; | |
9733 | SET_NFLG (flgn != 0); | |
9734 | m68k_write_memory_8(srca,dst); | |
9735 | }}}}}}m68k_incpc(4); | |
9736 | return 18; | |
9737 | } | |
9738 | unsigned long CPUFUNC(op_4438_4)(uint32_t opcode) /* NEG */ | |
9739 | { | |
9740 | OpcodeFamily = 15; CurrentInstrCycles = 16; | |
9741 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
9742 | { int8_t src = m68k_read_memory_8(srca); | |
9743 | {{uint32_t dst = ((int8_t)(0)) - ((int8_t)(src)); | |
9744 | { int flgs = ((int8_t)(src)) < 0; | |
9745 | int flgo = ((int8_t)(0)) < 0; | |
9746 | int flgn = ((int8_t)(dst)) < 0; | |
9747 | SET_ZFLG (((int8_t)(dst)) == 0); | |
9748 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
9749 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(0))); | |
9750 | COPY_CARRY; | |
9751 | SET_NFLG (flgn != 0); | |
9752 | m68k_write_memory_8(srca,dst); | |
9753 | }}}}}}m68k_incpc(4); | |
9754 | return 16; | |
9755 | } | |
9756 | unsigned long CPUFUNC(op_4439_4)(uint32_t opcode) /* NEG */ | |
9757 | { | |
9758 | OpcodeFamily = 15; CurrentInstrCycles = 20; | |
9759 | {{ uint32_t srca = get_ilong(2); | |
9760 | { int8_t src = m68k_read_memory_8(srca); | |
9761 | {{uint32_t dst = ((int8_t)(0)) - ((int8_t)(src)); | |
9762 | { int flgs = ((int8_t)(src)) < 0; | |
9763 | int flgo = ((int8_t)(0)) < 0; | |
9764 | int flgn = ((int8_t)(dst)) < 0; | |
9765 | SET_ZFLG (((int8_t)(dst)) == 0); | |
9766 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
9767 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(0))); | |
9768 | COPY_CARRY; | |
9769 | SET_NFLG (flgn != 0); | |
9770 | m68k_write_memory_8(srca,dst); | |
9771 | }}}}}}m68k_incpc(6); | |
9772 | return 20; | |
9773 | } | |
9774 | unsigned long CPUFUNC(op_4440_4)(uint32_t opcode) /* NEG */ | |
9775 | { | |
9776 | uint32_t srcreg = (opcode & 7); | |
9777 | OpcodeFamily = 15; CurrentInstrCycles = 4; | |
9778 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
9779 | {{uint32_t dst = ((int16_t)(0)) - ((int16_t)(src)); | |
9780 | { int flgs = ((int16_t)(src)) < 0; | |
9781 | int flgo = ((int16_t)(0)) < 0; | |
9782 | int flgn = ((int16_t)(dst)) < 0; | |
9783 | SET_ZFLG (((int16_t)(dst)) == 0); | |
9784 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
9785 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(0))); | |
9786 | COPY_CARRY; | |
9787 | SET_NFLG (flgn != 0); | |
9788 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((dst) & 0xffff); | |
9789 | }}}}}m68k_incpc(2); | |
9790 | return 4; | |
9791 | } | |
9792 | unsigned long CPUFUNC(op_4450_4)(uint32_t opcode) /* NEG */ | |
9793 | { | |
9794 | uint32_t srcreg = (opcode & 7); | |
9795 | OpcodeFamily = 15; CurrentInstrCycles = 12; | |
9796 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
9797 | { int16_t src = m68k_read_memory_16(srca); | |
9798 | {{uint32_t dst = ((int16_t)(0)) - ((int16_t)(src)); | |
9799 | { int flgs = ((int16_t)(src)) < 0; | |
9800 | int flgo = ((int16_t)(0)) < 0; | |
9801 | int flgn = ((int16_t)(dst)) < 0; | |
9802 | SET_ZFLG (((int16_t)(dst)) == 0); | |
9803 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
9804 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(0))); | |
9805 | COPY_CARRY; | |
9806 | SET_NFLG (flgn != 0); | |
9807 | m68k_write_memory_16(srca,dst); | |
9808 | }}}}}}m68k_incpc(2); | |
9809 | return 12; | |
9810 | } | |
9811 | unsigned long CPUFUNC(op_4458_4)(uint32_t opcode) /* NEG */ | |
9812 | { | |
9813 | uint32_t srcreg = (opcode & 7); | |
9814 | OpcodeFamily = 15; CurrentInstrCycles = 12; | |
9815 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
9816 | { int16_t src = m68k_read_memory_16(srca); | |
9817 | m68k_areg(regs, srcreg) += 2; | |
9818 | {{uint32_t dst = ((int16_t)(0)) - ((int16_t)(src)); | |
9819 | { int flgs = ((int16_t)(src)) < 0; | |
9820 | int flgo = ((int16_t)(0)) < 0; | |
9821 | int flgn = ((int16_t)(dst)) < 0; | |
9822 | SET_ZFLG (((int16_t)(dst)) == 0); | |
9823 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
9824 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(0))); | |
9825 | COPY_CARRY; | |
9826 | SET_NFLG (flgn != 0); | |
9827 | m68k_write_memory_16(srca,dst); | |
9828 | }}}}}}m68k_incpc(2); | |
9829 | return 12; | |
9830 | } | |
9831 | unsigned long CPUFUNC(op_4460_4)(uint32_t opcode) /* NEG */ | |
9832 | { | |
9833 | uint32_t srcreg = (opcode & 7); | |
9834 | OpcodeFamily = 15; CurrentInstrCycles = 14; | |
9835 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
9836 | { int16_t src = m68k_read_memory_16(srca); | |
9837 | m68k_areg (regs, srcreg) = srca; | |
9838 | {{uint32_t dst = ((int16_t)(0)) - ((int16_t)(src)); | |
9839 | { int flgs = ((int16_t)(src)) < 0; | |
9840 | int flgo = ((int16_t)(0)) < 0; | |
9841 | int flgn = ((int16_t)(dst)) < 0; | |
9842 | SET_ZFLG (((int16_t)(dst)) == 0); | |
9843 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
9844 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(0))); | |
9845 | COPY_CARRY; | |
9846 | SET_NFLG (flgn != 0); | |
9847 | m68k_write_memory_16(srca,dst); | |
9848 | }}}}}}m68k_incpc(2); | |
9849 | return 14; | |
9850 | } | |
9851 | unsigned long CPUFUNC(op_4468_4)(uint32_t opcode) /* NEG */ | |
9852 | { | |
9853 | uint32_t srcreg = (opcode & 7); | |
9854 | OpcodeFamily = 15; CurrentInstrCycles = 16; | |
9855 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
9856 | { int16_t src = m68k_read_memory_16(srca); | |
9857 | {{uint32_t dst = ((int16_t)(0)) - ((int16_t)(src)); | |
9858 | { int flgs = ((int16_t)(src)) < 0; | |
9859 | int flgo = ((int16_t)(0)) < 0; | |
9860 | int flgn = ((int16_t)(dst)) < 0; | |
9861 | SET_ZFLG (((int16_t)(dst)) == 0); | |
9862 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
9863 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(0))); | |
9864 | COPY_CARRY; | |
9865 | SET_NFLG (flgn != 0); | |
9866 | m68k_write_memory_16(srca,dst); | |
9867 | }}}}}}m68k_incpc(4); | |
9868 | return 16; | |
9869 | } | |
9870 | unsigned long CPUFUNC(op_4470_4)(uint32_t opcode) /* NEG */ | |
9871 | { | |
9872 | uint32_t srcreg = (opcode & 7); | |
9873 | OpcodeFamily = 15; CurrentInstrCycles = 18; | |
9874 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
9875 | BusCyclePenalty += 2; | |
9876 | { int16_t src = m68k_read_memory_16(srca); | |
9877 | {{uint32_t dst = ((int16_t)(0)) - ((int16_t)(src)); | |
9878 | { int flgs = ((int16_t)(src)) < 0; | |
9879 | int flgo = ((int16_t)(0)) < 0; | |
9880 | int flgn = ((int16_t)(dst)) < 0; | |
9881 | SET_ZFLG (((int16_t)(dst)) == 0); | |
9882 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
9883 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(0))); | |
9884 | COPY_CARRY; | |
9885 | SET_NFLG (flgn != 0); | |
9886 | m68k_write_memory_16(srca,dst); | |
9887 | }}}}}}m68k_incpc(4); | |
9888 | return 18; | |
9889 | } | |
9890 | unsigned long CPUFUNC(op_4478_4)(uint32_t opcode) /* NEG */ | |
9891 | { | |
9892 | OpcodeFamily = 15; CurrentInstrCycles = 16; | |
9893 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
9894 | { int16_t src = m68k_read_memory_16(srca); | |
9895 | {{uint32_t dst = ((int16_t)(0)) - ((int16_t)(src)); | |
9896 | { int flgs = ((int16_t)(src)) < 0; | |
9897 | int flgo = ((int16_t)(0)) < 0; | |
9898 | int flgn = ((int16_t)(dst)) < 0; | |
9899 | SET_ZFLG (((int16_t)(dst)) == 0); | |
9900 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
9901 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(0))); | |
9902 | COPY_CARRY; | |
9903 | SET_NFLG (flgn != 0); | |
9904 | m68k_write_memory_16(srca,dst); | |
9905 | }}}}}}m68k_incpc(4); | |
9906 | return 16; | |
9907 | } | |
9908 | unsigned long CPUFUNC(op_4479_4)(uint32_t opcode) /* NEG */ | |
9909 | { | |
9910 | OpcodeFamily = 15; CurrentInstrCycles = 20; | |
9911 | {{ uint32_t srca = get_ilong(2); | |
9912 | { int16_t src = m68k_read_memory_16(srca); | |
9913 | {{uint32_t dst = ((int16_t)(0)) - ((int16_t)(src)); | |
9914 | { int flgs = ((int16_t)(src)) < 0; | |
9915 | int flgo = ((int16_t)(0)) < 0; | |
9916 | int flgn = ((int16_t)(dst)) < 0; | |
9917 | SET_ZFLG (((int16_t)(dst)) == 0); | |
9918 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
9919 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(0))); | |
9920 | COPY_CARRY; | |
9921 | SET_NFLG (flgn != 0); | |
9922 | m68k_write_memory_16(srca,dst); | |
9923 | }}}}}}m68k_incpc(6); | |
9924 | return 20; | |
9925 | } | |
9926 | unsigned long CPUFUNC(op_4480_4)(uint32_t opcode) /* NEG */ | |
9927 | { | |
9928 | uint32_t srcreg = (opcode & 7); | |
9929 | OpcodeFamily = 15; CurrentInstrCycles = 6; | |
9930 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
9931 | {{uint32_t dst = ((int32_t)(0)) - ((int32_t)(src)); | |
9932 | { int flgs = ((int32_t)(src)) < 0; | |
9933 | int flgo = ((int32_t)(0)) < 0; | |
9934 | int flgn = ((int32_t)(dst)) < 0; | |
9935 | SET_ZFLG (((int32_t)(dst)) == 0); | |
9936 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
9937 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(0))); | |
9938 | COPY_CARRY; | |
9939 | SET_NFLG (flgn != 0); | |
9940 | m68k_dreg(regs, srcreg) = (dst); | |
9941 | }}}}}m68k_incpc(2); | |
9942 | return 6; | |
9943 | } | |
9944 | unsigned long CPUFUNC(op_4490_4)(uint32_t opcode) /* NEG */ | |
9945 | { | |
9946 | uint32_t srcreg = (opcode & 7); | |
9947 | OpcodeFamily = 15; CurrentInstrCycles = 20; | |
9948 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
9949 | { int32_t src = m68k_read_memory_32(srca); | |
9950 | {{uint32_t dst = ((int32_t)(0)) - ((int32_t)(src)); | |
9951 | { int flgs = ((int32_t)(src)) < 0; | |
9952 | int flgo = ((int32_t)(0)) < 0; | |
9953 | int flgn = ((int32_t)(dst)) < 0; | |
9954 | SET_ZFLG (((int32_t)(dst)) == 0); | |
9955 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
9956 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(0))); | |
9957 | COPY_CARRY; | |
9958 | SET_NFLG (flgn != 0); | |
9959 | m68k_write_memory_32(srca,dst); | |
9960 | }}}}}}m68k_incpc(2); | |
9961 | return 20; | |
9962 | } | |
9963 | unsigned long CPUFUNC(op_4498_4)(uint32_t opcode) /* NEG */ | |
9964 | { | |
9965 | uint32_t srcreg = (opcode & 7); | |
9966 | OpcodeFamily = 15; CurrentInstrCycles = 20; | |
9967 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
9968 | { int32_t src = m68k_read_memory_32(srca); | |
9969 | m68k_areg(regs, srcreg) += 4; | |
9970 | {{uint32_t dst = ((int32_t)(0)) - ((int32_t)(src)); | |
9971 | { int flgs = ((int32_t)(src)) < 0; | |
9972 | int flgo = ((int32_t)(0)) < 0; | |
9973 | int flgn = ((int32_t)(dst)) < 0; | |
9974 | SET_ZFLG (((int32_t)(dst)) == 0); | |
9975 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
9976 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(0))); | |
9977 | COPY_CARRY; | |
9978 | SET_NFLG (flgn != 0); | |
9979 | m68k_write_memory_32(srca,dst); | |
9980 | }}}}}}m68k_incpc(2); | |
9981 | return 20; | |
9982 | } | |
9983 | unsigned long CPUFUNC(op_44a0_4)(uint32_t opcode) /* NEG */ | |
9984 | { | |
9985 | uint32_t srcreg = (opcode & 7); | |
9986 | OpcodeFamily = 15; CurrentInstrCycles = 22; | |
9987 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 4; | |
9988 | { int32_t src = m68k_read_memory_32(srca); | |
9989 | m68k_areg (regs, srcreg) = srca; | |
9990 | {{uint32_t dst = ((int32_t)(0)) - ((int32_t)(src)); | |
9991 | { int flgs = ((int32_t)(src)) < 0; | |
9992 | int flgo = ((int32_t)(0)) < 0; | |
9993 | int flgn = ((int32_t)(dst)) < 0; | |
9994 | SET_ZFLG (((int32_t)(dst)) == 0); | |
9995 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
9996 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(0))); | |
9997 | COPY_CARRY; | |
9998 | SET_NFLG (flgn != 0); | |
9999 | m68k_write_memory_32(srca,dst); | |
10000 | }}}}}}m68k_incpc(2); | |
10001 | return 22; | |
10002 | } | |
10003 | unsigned long CPUFUNC(op_44a8_4)(uint32_t opcode) /* NEG */ | |
10004 | { | |
10005 | uint32_t srcreg = (opcode & 7); | |
10006 | OpcodeFamily = 15; CurrentInstrCycles = 24; | |
10007 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
10008 | { int32_t src = m68k_read_memory_32(srca); | |
10009 | {{uint32_t dst = ((int32_t)(0)) - ((int32_t)(src)); | |
10010 | { int flgs = ((int32_t)(src)) < 0; | |
10011 | int flgo = ((int32_t)(0)) < 0; | |
10012 | int flgn = ((int32_t)(dst)) < 0; | |
10013 | SET_ZFLG (((int32_t)(dst)) == 0); | |
10014 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
10015 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(0))); | |
10016 | COPY_CARRY; | |
10017 | SET_NFLG (flgn != 0); | |
10018 | m68k_write_memory_32(srca,dst); | |
10019 | }}}}}}m68k_incpc(4); | |
10020 | return 24; | |
10021 | } | |
10022 | unsigned long CPUFUNC(op_44b0_4)(uint32_t opcode) /* NEG */ | |
10023 | { | |
10024 | uint32_t srcreg = (opcode & 7); | |
10025 | OpcodeFamily = 15; CurrentInstrCycles = 26; | |
10026 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
10027 | BusCyclePenalty += 2; | |
10028 | { int32_t src = m68k_read_memory_32(srca); | |
10029 | {{uint32_t dst = ((int32_t)(0)) - ((int32_t)(src)); | |
10030 | { int flgs = ((int32_t)(src)) < 0; | |
10031 | int flgo = ((int32_t)(0)) < 0; | |
10032 | int flgn = ((int32_t)(dst)) < 0; | |
10033 | SET_ZFLG (((int32_t)(dst)) == 0); | |
10034 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
10035 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(0))); | |
10036 | COPY_CARRY; | |
10037 | SET_NFLG (flgn != 0); | |
10038 | m68k_write_memory_32(srca,dst); | |
10039 | }}}}}}m68k_incpc(4); | |
10040 | return 26; | |
10041 | } | |
10042 | unsigned long CPUFUNC(op_44b8_4)(uint32_t opcode) /* NEG */ | |
10043 | { | |
10044 | OpcodeFamily = 15; CurrentInstrCycles = 24; | |
10045 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
10046 | { int32_t src = m68k_read_memory_32(srca); | |
10047 | {{uint32_t dst = ((int32_t)(0)) - ((int32_t)(src)); | |
10048 | { int flgs = ((int32_t)(src)) < 0; | |
10049 | int flgo = ((int32_t)(0)) < 0; | |
10050 | int flgn = ((int32_t)(dst)) < 0; | |
10051 | SET_ZFLG (((int32_t)(dst)) == 0); | |
10052 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
10053 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(0))); | |
10054 | COPY_CARRY; | |
10055 | SET_NFLG (flgn != 0); | |
10056 | m68k_write_memory_32(srca,dst); | |
10057 | }}}}}}m68k_incpc(4); | |
10058 | return 24; | |
10059 | } | |
10060 | unsigned long CPUFUNC(op_44b9_4)(uint32_t opcode) /* NEG */ | |
10061 | { | |
10062 | OpcodeFamily = 15; CurrentInstrCycles = 28; | |
10063 | {{ uint32_t srca = get_ilong(2); | |
10064 | { int32_t src = m68k_read_memory_32(srca); | |
10065 | {{uint32_t dst = ((int32_t)(0)) - ((int32_t)(src)); | |
10066 | { int flgs = ((int32_t)(src)) < 0; | |
10067 | int flgo = ((int32_t)(0)) < 0; | |
10068 | int flgn = ((int32_t)(dst)) < 0; | |
10069 | SET_ZFLG (((int32_t)(dst)) == 0); | |
10070 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
10071 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(0))); | |
10072 | COPY_CARRY; | |
10073 | SET_NFLG (flgn != 0); | |
10074 | m68k_write_memory_32(srca,dst); | |
10075 | }}}}}}m68k_incpc(6); | |
10076 | return 28; | |
10077 | } | |
10078 | unsigned long CPUFUNC(op_44c0_4)(uint32_t opcode) /* MV2SR */ | |
10079 | { | |
10080 | uint32_t srcreg = (opcode & 7); | |
10081 | OpcodeFamily = 33; CurrentInstrCycles = 12; | |
10082 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
10083 | MakeSR(); | |
10084 | regs.sr &= 0xFF00; | |
10085 | regs.sr |= src & 0xFF; | |
10086 | MakeFromSR(); | |
10087 | }}m68k_incpc(2); | |
10088 | return 12; | |
10089 | } | |
10090 | unsigned long CPUFUNC(op_44d0_4)(uint32_t opcode) /* MV2SR */ | |
10091 | { | |
10092 | uint32_t srcreg = (opcode & 7); | |
10093 | OpcodeFamily = 33; CurrentInstrCycles = 16; | |
10094 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
10095 | { int16_t src = m68k_read_memory_16(srca); | |
10096 | MakeSR(); | |
10097 | regs.sr &= 0xFF00; | |
10098 | regs.sr |= src & 0xFF; | |
10099 | MakeFromSR(); | |
10100 | }}}m68k_incpc(2); | |
10101 | return 16; | |
10102 | } | |
10103 | unsigned long CPUFUNC(op_44d8_4)(uint32_t opcode) /* MV2SR */ | |
10104 | { | |
10105 | uint32_t srcreg = (opcode & 7); | |
10106 | OpcodeFamily = 33; CurrentInstrCycles = 16; | |
10107 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
10108 | { int16_t src = m68k_read_memory_16(srca); | |
10109 | m68k_areg(regs, srcreg) += 2; | |
10110 | MakeSR(); | |
10111 | regs.sr &= 0xFF00; | |
10112 | regs.sr |= src & 0xFF; | |
10113 | MakeFromSR(); | |
10114 | }}}m68k_incpc(2); | |
10115 | return 16; | |
10116 | } | |
10117 | unsigned long CPUFUNC(op_44e0_4)(uint32_t opcode) /* MV2SR */ | |
10118 | { | |
10119 | uint32_t srcreg = (opcode & 7); | |
10120 | OpcodeFamily = 33; CurrentInstrCycles = 18; | |
10121 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
10122 | { int16_t src = m68k_read_memory_16(srca); | |
10123 | m68k_areg (regs, srcreg) = srca; | |
10124 | MakeSR(); | |
10125 | regs.sr &= 0xFF00; | |
10126 | regs.sr |= src & 0xFF; | |
10127 | MakeFromSR(); | |
10128 | }}}m68k_incpc(2); | |
10129 | return 18; | |
10130 | } | |
10131 | unsigned long CPUFUNC(op_44e8_4)(uint32_t opcode) /* MV2SR */ | |
10132 | { | |
10133 | uint32_t srcreg = (opcode & 7); | |
10134 | OpcodeFamily = 33; CurrentInstrCycles = 20; | |
10135 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
10136 | { int16_t src = m68k_read_memory_16(srca); | |
10137 | MakeSR(); | |
10138 | regs.sr &= 0xFF00; | |
10139 | regs.sr |= src & 0xFF; | |
10140 | MakeFromSR(); | |
10141 | }}}m68k_incpc(4); | |
10142 | return 20; | |
10143 | } | |
10144 | unsigned long CPUFUNC(op_44f0_4)(uint32_t opcode) /* MV2SR */ | |
10145 | { | |
10146 | uint32_t srcreg = (opcode & 7); | |
10147 | OpcodeFamily = 33; CurrentInstrCycles = 22; | |
10148 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
10149 | BusCyclePenalty += 2; | |
10150 | { int16_t src = m68k_read_memory_16(srca); | |
10151 | MakeSR(); | |
10152 | regs.sr &= 0xFF00; | |
10153 | regs.sr |= src & 0xFF; | |
10154 | MakeFromSR(); | |
10155 | }}}m68k_incpc(4); | |
10156 | return 22; | |
10157 | } | |
10158 | unsigned long CPUFUNC(op_44f8_4)(uint32_t opcode) /* MV2SR */ | |
10159 | { | |
10160 | OpcodeFamily = 33; CurrentInstrCycles = 20; | |
10161 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
10162 | { int16_t src = m68k_read_memory_16(srca); | |
10163 | MakeSR(); | |
10164 | regs.sr &= 0xFF00; | |
10165 | regs.sr |= src & 0xFF; | |
10166 | MakeFromSR(); | |
10167 | }}}m68k_incpc(4); | |
10168 | return 20; | |
10169 | } | |
10170 | unsigned long CPUFUNC(op_44f9_4)(uint32_t opcode) /* MV2SR */ | |
10171 | { | |
10172 | OpcodeFamily = 33; CurrentInstrCycles = 24; | |
10173 | {{ uint32_t srca = get_ilong(2); | |
10174 | { int16_t src = m68k_read_memory_16(srca); | |
10175 | MakeSR(); | |
10176 | regs.sr &= 0xFF00; | |
10177 | regs.sr |= src & 0xFF; | |
10178 | MakeFromSR(); | |
10179 | }}}m68k_incpc(6); | |
10180 | return 24; | |
10181 | } | |
10182 | unsigned long CPUFUNC(op_44fa_4)(uint32_t opcode) /* MV2SR */ | |
10183 | { | |
10184 | OpcodeFamily = 33; CurrentInstrCycles = 20; | |
10185 | {{ uint32_t srca = m68k_getpc () + 2; | |
10186 | srca += (int32_t)(int16_t)get_iword(2); | |
10187 | { int16_t src = m68k_read_memory_16(srca); | |
10188 | MakeSR(); | |
10189 | regs.sr &= 0xFF00; | |
10190 | regs.sr |= src & 0xFF; | |
10191 | MakeFromSR(); | |
10192 | }}}m68k_incpc(4); | |
10193 | return 20; | |
10194 | } | |
10195 | unsigned long CPUFUNC(op_44fb_4)(uint32_t opcode) /* MV2SR */ | |
10196 | { | |
10197 | OpcodeFamily = 33; CurrentInstrCycles = 22; | |
10198 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
10199 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
10200 | BusCyclePenalty += 2; | |
10201 | { int16_t src = m68k_read_memory_16(srca); | |
10202 | MakeSR(); | |
10203 | regs.sr &= 0xFF00; | |
10204 | regs.sr |= src & 0xFF; | |
10205 | MakeFromSR(); | |
10206 | }}}m68k_incpc(4); | |
10207 | return 22; | |
10208 | } | |
10209 | unsigned long CPUFUNC(op_44fc_4)(uint32_t opcode) /* MV2SR */ | |
10210 | { | |
10211 | OpcodeFamily = 33; CurrentInstrCycles = 16; | |
10212 | {{ int16_t src = get_iword(2); | |
10213 | MakeSR(); | |
10214 | regs.sr &= 0xFF00; | |
10215 | regs.sr |= src & 0xFF; | |
10216 | MakeFromSR(); | |
10217 | }}m68k_incpc(4); | |
10218 | return 16; | |
10219 | } | |
10220 | unsigned long CPUFUNC(op_4600_4)(uint32_t opcode) /* NOT */ | |
10221 | { | |
10222 | uint32_t srcreg = (opcode & 7); | |
10223 | OpcodeFamily = 19; CurrentInstrCycles = 4; | |
10224 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
10225 | { uint32_t dst = ~src; | |
10226 | CLEAR_CZNV; | |
10227 | SET_ZFLG (((int8_t)(dst)) == 0); | |
10228 | SET_NFLG (((int8_t)(dst)) < 0); | |
10229 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((dst) & 0xff); | |
10230 | }}}m68k_incpc(2); | |
10231 | return 4; | |
10232 | } | |
10233 | unsigned long CPUFUNC(op_4610_4)(uint32_t opcode) /* NOT */ | |
10234 | { | |
10235 | uint32_t srcreg = (opcode & 7); | |
10236 | OpcodeFamily = 19; CurrentInstrCycles = 12; | |
10237 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
10238 | { int8_t src = m68k_read_memory_8(srca); | |
10239 | { uint32_t dst = ~src; | |
10240 | CLEAR_CZNV; | |
10241 | SET_ZFLG (((int8_t)(dst)) == 0); | |
10242 | SET_NFLG (((int8_t)(dst)) < 0); | |
10243 | m68k_write_memory_8(srca,dst); | |
10244 | }}}}m68k_incpc(2); | |
10245 | return 12; | |
10246 | } | |
10247 | unsigned long CPUFUNC(op_4618_4)(uint32_t opcode) /* NOT */ | |
10248 | { | |
10249 | uint32_t srcreg = (opcode & 7); | |
10250 | OpcodeFamily = 19; CurrentInstrCycles = 12; | |
10251 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
10252 | { int8_t src = m68k_read_memory_8(srca); | |
10253 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
10254 | { uint32_t dst = ~src; | |
10255 | CLEAR_CZNV; | |
10256 | SET_ZFLG (((int8_t)(dst)) == 0); | |
10257 | SET_NFLG (((int8_t)(dst)) < 0); | |
10258 | m68k_write_memory_8(srca,dst); | |
10259 | }}}}m68k_incpc(2); | |
10260 | return 12; | |
10261 | } | |
10262 | unsigned long CPUFUNC(op_4620_4)(uint32_t opcode) /* NOT */ | |
10263 | { | |
10264 | uint32_t srcreg = (opcode & 7); | |
10265 | OpcodeFamily = 19; CurrentInstrCycles = 14; | |
10266 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
10267 | { int8_t src = m68k_read_memory_8(srca); | |
10268 | m68k_areg (regs, srcreg) = srca; | |
10269 | { uint32_t dst = ~src; | |
10270 | CLEAR_CZNV; | |
10271 | SET_ZFLG (((int8_t)(dst)) == 0); | |
10272 | SET_NFLG (((int8_t)(dst)) < 0); | |
10273 | m68k_write_memory_8(srca,dst); | |
10274 | }}}}m68k_incpc(2); | |
10275 | return 14; | |
10276 | } | |
10277 | unsigned long CPUFUNC(op_4628_4)(uint32_t opcode) /* NOT */ | |
10278 | { | |
10279 | uint32_t srcreg = (opcode & 7); | |
10280 | OpcodeFamily = 19; CurrentInstrCycles = 16; | |
10281 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
10282 | { int8_t src = m68k_read_memory_8(srca); | |
10283 | { uint32_t dst = ~src; | |
10284 | CLEAR_CZNV; | |
10285 | SET_ZFLG (((int8_t)(dst)) == 0); | |
10286 | SET_NFLG (((int8_t)(dst)) < 0); | |
10287 | m68k_write_memory_8(srca,dst); | |
10288 | }}}}m68k_incpc(4); | |
10289 | return 16; | |
10290 | } | |
10291 | unsigned long CPUFUNC(op_4630_4)(uint32_t opcode) /* NOT */ | |
10292 | { | |
10293 | uint32_t srcreg = (opcode & 7); | |
10294 | OpcodeFamily = 19; CurrentInstrCycles = 18; | |
10295 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
10296 | BusCyclePenalty += 2; | |
10297 | { int8_t src = m68k_read_memory_8(srca); | |
10298 | { uint32_t dst = ~src; | |
10299 | CLEAR_CZNV; | |
10300 | SET_ZFLG (((int8_t)(dst)) == 0); | |
10301 | SET_NFLG (((int8_t)(dst)) < 0); | |
10302 | m68k_write_memory_8(srca,dst); | |
10303 | }}}}m68k_incpc(4); | |
10304 | return 18; | |
10305 | } | |
10306 | unsigned long CPUFUNC(op_4638_4)(uint32_t opcode) /* NOT */ | |
10307 | { | |
10308 | OpcodeFamily = 19; CurrentInstrCycles = 16; | |
10309 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
10310 | { int8_t src = m68k_read_memory_8(srca); | |
10311 | { uint32_t dst = ~src; | |
10312 | CLEAR_CZNV; | |
10313 | SET_ZFLG (((int8_t)(dst)) == 0); | |
10314 | SET_NFLG (((int8_t)(dst)) < 0); | |
10315 | m68k_write_memory_8(srca,dst); | |
10316 | }}}}m68k_incpc(4); | |
10317 | return 16; | |
10318 | } | |
10319 | unsigned long CPUFUNC(op_4639_4)(uint32_t opcode) /* NOT */ | |
10320 | { | |
10321 | OpcodeFamily = 19; CurrentInstrCycles = 20; | |
10322 | {{ uint32_t srca = get_ilong(2); | |
10323 | { int8_t src = m68k_read_memory_8(srca); | |
10324 | { uint32_t dst = ~src; | |
10325 | CLEAR_CZNV; | |
10326 | SET_ZFLG (((int8_t)(dst)) == 0); | |
10327 | SET_NFLG (((int8_t)(dst)) < 0); | |
10328 | m68k_write_memory_8(srca,dst); | |
10329 | }}}}m68k_incpc(6); | |
10330 | return 20; | |
10331 | } | |
10332 | unsigned long CPUFUNC(op_4640_4)(uint32_t opcode) /* NOT */ | |
10333 | { | |
10334 | uint32_t srcreg = (opcode & 7); | |
10335 | OpcodeFamily = 19; CurrentInstrCycles = 4; | |
10336 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
10337 | { uint32_t dst = ~src; | |
10338 | CLEAR_CZNV; | |
10339 | SET_ZFLG (((int16_t)(dst)) == 0); | |
10340 | SET_NFLG (((int16_t)(dst)) < 0); | |
10341 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((dst) & 0xffff); | |
10342 | }}}m68k_incpc(2); | |
10343 | return 4; | |
10344 | } | |
10345 | unsigned long CPUFUNC(op_4650_4)(uint32_t opcode) /* NOT */ | |
10346 | { | |
10347 | uint32_t srcreg = (opcode & 7); | |
10348 | OpcodeFamily = 19; CurrentInstrCycles = 12; | |
10349 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
10350 | { int16_t src = m68k_read_memory_16(srca); | |
10351 | { uint32_t dst = ~src; | |
10352 | CLEAR_CZNV; | |
10353 | SET_ZFLG (((int16_t)(dst)) == 0); | |
10354 | SET_NFLG (((int16_t)(dst)) < 0); | |
10355 | m68k_write_memory_16(srca,dst); | |
10356 | }}}}m68k_incpc(2); | |
10357 | return 12; | |
10358 | } | |
10359 | unsigned long CPUFUNC(op_4658_4)(uint32_t opcode) /* NOT */ | |
10360 | { | |
10361 | uint32_t srcreg = (opcode & 7); | |
10362 | OpcodeFamily = 19; CurrentInstrCycles = 12; | |
10363 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
10364 | { int16_t src = m68k_read_memory_16(srca); | |
10365 | m68k_areg(regs, srcreg) += 2; | |
10366 | { uint32_t dst = ~src; | |
10367 | CLEAR_CZNV; | |
10368 | SET_ZFLG (((int16_t)(dst)) == 0); | |
10369 | SET_NFLG (((int16_t)(dst)) < 0); | |
10370 | m68k_write_memory_16(srca,dst); | |
10371 | }}}}m68k_incpc(2); | |
10372 | return 12; | |
10373 | } | |
10374 | unsigned long CPUFUNC(op_4660_4)(uint32_t opcode) /* NOT */ | |
10375 | { | |
10376 | uint32_t srcreg = (opcode & 7); | |
10377 | OpcodeFamily = 19; CurrentInstrCycles = 14; | |
10378 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
10379 | { int16_t src = m68k_read_memory_16(srca); | |
10380 | m68k_areg (regs, srcreg) = srca; | |
10381 | { uint32_t dst = ~src; | |
10382 | CLEAR_CZNV; | |
10383 | SET_ZFLG (((int16_t)(dst)) == 0); | |
10384 | SET_NFLG (((int16_t)(dst)) < 0); | |
10385 | m68k_write_memory_16(srca,dst); | |
10386 | }}}}m68k_incpc(2); | |
10387 | return 14; | |
10388 | } | |
10389 | unsigned long CPUFUNC(op_4668_4)(uint32_t opcode) /* NOT */ | |
10390 | { | |
10391 | uint32_t srcreg = (opcode & 7); | |
10392 | OpcodeFamily = 19; CurrentInstrCycles = 16; | |
10393 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
10394 | { int16_t src = m68k_read_memory_16(srca); | |
10395 | { uint32_t dst = ~src; | |
10396 | CLEAR_CZNV; | |
10397 | SET_ZFLG (((int16_t)(dst)) == 0); | |
10398 | SET_NFLG (((int16_t)(dst)) < 0); | |
10399 | m68k_write_memory_16(srca,dst); | |
10400 | }}}}m68k_incpc(4); | |
10401 | return 16; | |
10402 | } | |
10403 | unsigned long CPUFUNC(op_4670_4)(uint32_t opcode) /* NOT */ | |
10404 | { | |
10405 | uint32_t srcreg = (opcode & 7); | |
10406 | OpcodeFamily = 19; CurrentInstrCycles = 18; | |
10407 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
10408 | BusCyclePenalty += 2; | |
10409 | { int16_t src = m68k_read_memory_16(srca); | |
10410 | { uint32_t dst = ~src; | |
10411 | CLEAR_CZNV; | |
10412 | SET_ZFLG (((int16_t)(dst)) == 0); | |
10413 | SET_NFLG (((int16_t)(dst)) < 0); | |
10414 | m68k_write_memory_16(srca,dst); | |
10415 | }}}}m68k_incpc(4); | |
10416 | return 18; | |
10417 | } | |
10418 | unsigned long CPUFUNC(op_4678_4)(uint32_t opcode) /* NOT */ | |
10419 | { | |
10420 | OpcodeFamily = 19; CurrentInstrCycles = 16; | |
10421 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
10422 | { int16_t src = m68k_read_memory_16(srca); | |
10423 | { uint32_t dst = ~src; | |
10424 | CLEAR_CZNV; | |
10425 | SET_ZFLG (((int16_t)(dst)) == 0); | |
10426 | SET_NFLG (((int16_t)(dst)) < 0); | |
10427 | m68k_write_memory_16(srca,dst); | |
10428 | }}}}m68k_incpc(4); | |
10429 | return 16; | |
10430 | } | |
10431 | unsigned long CPUFUNC(op_4679_4)(uint32_t opcode) /* NOT */ | |
10432 | { | |
10433 | OpcodeFamily = 19; CurrentInstrCycles = 20; | |
10434 | {{ uint32_t srca = get_ilong(2); | |
10435 | { int16_t src = m68k_read_memory_16(srca); | |
10436 | { uint32_t dst = ~src; | |
10437 | CLEAR_CZNV; | |
10438 | SET_ZFLG (((int16_t)(dst)) == 0); | |
10439 | SET_NFLG (((int16_t)(dst)) < 0); | |
10440 | m68k_write_memory_16(srca,dst); | |
10441 | }}}}m68k_incpc(6); | |
10442 | return 20; | |
10443 | } | |
10444 | unsigned long CPUFUNC(op_4680_4)(uint32_t opcode) /* NOT */ | |
10445 | { | |
10446 | uint32_t srcreg = (opcode & 7); | |
10447 | OpcodeFamily = 19; CurrentInstrCycles = 6; | |
10448 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
10449 | { uint32_t dst = ~src; | |
10450 | CLEAR_CZNV; | |
10451 | SET_ZFLG (((int32_t)(dst)) == 0); | |
10452 | SET_NFLG (((int32_t)(dst)) < 0); | |
10453 | m68k_dreg(regs, srcreg) = (dst); | |
10454 | }}}m68k_incpc(2); | |
10455 | return 6; | |
10456 | } | |
10457 | unsigned long CPUFUNC(op_4690_4)(uint32_t opcode) /* NOT */ | |
10458 | { | |
10459 | uint32_t srcreg = (opcode & 7); | |
10460 | OpcodeFamily = 19; CurrentInstrCycles = 20; | |
10461 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
10462 | { int32_t src = m68k_read_memory_32(srca); | |
10463 | { uint32_t dst = ~src; | |
10464 | CLEAR_CZNV; | |
10465 | SET_ZFLG (((int32_t)(dst)) == 0); | |
10466 | SET_NFLG (((int32_t)(dst)) < 0); | |
10467 | m68k_write_memory_32(srca,dst); | |
10468 | }}}}m68k_incpc(2); | |
10469 | return 20; | |
10470 | } | |
10471 | unsigned long CPUFUNC(op_4698_4)(uint32_t opcode) /* NOT */ | |
10472 | { | |
10473 | uint32_t srcreg = (opcode & 7); | |
10474 | OpcodeFamily = 19; CurrentInstrCycles = 20; | |
10475 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
10476 | { int32_t src = m68k_read_memory_32(srca); | |
10477 | m68k_areg(regs, srcreg) += 4; | |
10478 | { uint32_t dst = ~src; | |
10479 | CLEAR_CZNV; | |
10480 | SET_ZFLG (((int32_t)(dst)) == 0); | |
10481 | SET_NFLG (((int32_t)(dst)) < 0); | |
10482 | m68k_write_memory_32(srca,dst); | |
10483 | }}}}m68k_incpc(2); | |
10484 | return 20; | |
10485 | } | |
10486 | unsigned long CPUFUNC(op_46a0_4)(uint32_t opcode) /* NOT */ | |
10487 | { | |
10488 | uint32_t srcreg = (opcode & 7); | |
10489 | OpcodeFamily = 19; CurrentInstrCycles = 22; | |
10490 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 4; | |
10491 | { int32_t src = m68k_read_memory_32(srca); | |
10492 | m68k_areg (regs, srcreg) = srca; | |
10493 | { uint32_t dst = ~src; | |
10494 | CLEAR_CZNV; | |
10495 | SET_ZFLG (((int32_t)(dst)) == 0); | |
10496 | SET_NFLG (((int32_t)(dst)) < 0); | |
10497 | m68k_write_memory_32(srca,dst); | |
10498 | }}}}m68k_incpc(2); | |
10499 | return 22; | |
10500 | } | |
10501 | unsigned long CPUFUNC(op_46a8_4)(uint32_t opcode) /* NOT */ | |
10502 | { | |
10503 | uint32_t srcreg = (opcode & 7); | |
10504 | OpcodeFamily = 19; CurrentInstrCycles = 24; | |
10505 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
10506 | { int32_t src = m68k_read_memory_32(srca); | |
10507 | { uint32_t dst = ~src; | |
10508 | CLEAR_CZNV; | |
10509 | SET_ZFLG (((int32_t)(dst)) == 0); | |
10510 | SET_NFLG (((int32_t)(dst)) < 0); | |
10511 | m68k_write_memory_32(srca,dst); | |
10512 | }}}}m68k_incpc(4); | |
10513 | return 24; | |
10514 | } | |
10515 | unsigned long CPUFUNC(op_46b0_4)(uint32_t opcode) /* NOT */ | |
10516 | { | |
10517 | uint32_t srcreg = (opcode & 7); | |
10518 | OpcodeFamily = 19; CurrentInstrCycles = 26; | |
10519 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
10520 | BusCyclePenalty += 2; | |
10521 | { int32_t src = m68k_read_memory_32(srca); | |
10522 | { uint32_t dst = ~src; | |
10523 | CLEAR_CZNV; | |
10524 | SET_ZFLG (((int32_t)(dst)) == 0); | |
10525 | SET_NFLG (((int32_t)(dst)) < 0); | |
10526 | m68k_write_memory_32(srca,dst); | |
10527 | }}}}m68k_incpc(4); | |
10528 | return 26; | |
10529 | } | |
10530 | unsigned long CPUFUNC(op_46b8_4)(uint32_t opcode) /* NOT */ | |
10531 | { | |
10532 | OpcodeFamily = 19; CurrentInstrCycles = 24; | |
10533 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
10534 | { int32_t src = m68k_read_memory_32(srca); | |
10535 | { uint32_t dst = ~src; | |
10536 | CLEAR_CZNV; | |
10537 | SET_ZFLG (((int32_t)(dst)) == 0); | |
10538 | SET_NFLG (((int32_t)(dst)) < 0); | |
10539 | m68k_write_memory_32(srca,dst); | |
10540 | }}}}m68k_incpc(4); | |
10541 | return 24; | |
10542 | } | |
10543 | unsigned long CPUFUNC(op_46b9_4)(uint32_t opcode) /* NOT */ | |
10544 | { | |
10545 | OpcodeFamily = 19; CurrentInstrCycles = 28; | |
10546 | {{ uint32_t srca = get_ilong(2); | |
10547 | { int32_t src = m68k_read_memory_32(srca); | |
10548 | { uint32_t dst = ~src; | |
10549 | CLEAR_CZNV; | |
10550 | SET_ZFLG (((int32_t)(dst)) == 0); | |
10551 | SET_NFLG (((int32_t)(dst)) < 0); | |
10552 | m68k_write_memory_32(srca,dst); | |
10553 | }}}}m68k_incpc(6); | |
10554 | return 28; | |
10555 | } | |
10556 | unsigned long CPUFUNC(op_46c0_4)(uint32_t opcode) /* MV2SR */ | |
10557 | { | |
10558 | uint32_t srcreg = (opcode & 7); | |
10559 | OpcodeFamily = 33; CurrentInstrCycles = 12; | |
10560 | {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel688; } | |
10561 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
10562 | regs.sr = src; | |
10563 | MakeFromSR(); | |
10564 | }}}m68k_incpc(2); | |
10565 | endlabel688: ; | |
10566 | return 12; | |
10567 | } | |
10568 | unsigned long CPUFUNC(op_46d0_4)(uint32_t opcode) /* MV2SR */ | |
10569 | { | |
10570 | uint32_t srcreg = (opcode & 7); | |
10571 | OpcodeFamily = 33; CurrentInstrCycles = 16; | |
10572 | {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel689; } | |
10573 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
10574 | { int16_t src = m68k_read_memory_16(srca); | |
10575 | regs.sr = src; | |
10576 | MakeFromSR(); | |
10577 | }}}}m68k_incpc(2); | |
10578 | endlabel689: ; | |
10579 | return 16; | |
10580 | } | |
10581 | unsigned long CPUFUNC(op_46d8_4)(uint32_t opcode) /* MV2SR */ | |
10582 | { | |
10583 | uint32_t srcreg = (opcode & 7); | |
10584 | OpcodeFamily = 33; CurrentInstrCycles = 16; | |
10585 | {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel690; } | |
10586 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
10587 | { int16_t src = m68k_read_memory_16(srca); | |
10588 | m68k_areg(regs, srcreg) += 2; | |
10589 | regs.sr = src; | |
10590 | MakeFromSR(); | |
10591 | }}}}m68k_incpc(2); | |
10592 | endlabel690: ; | |
10593 | return 16; | |
10594 | } | |
10595 | unsigned long CPUFUNC(op_46e0_4)(uint32_t opcode) /* MV2SR */ | |
10596 | { | |
10597 | uint32_t srcreg = (opcode & 7); | |
10598 | OpcodeFamily = 33; CurrentInstrCycles = 18; | |
10599 | {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel691; } | |
10600 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
10601 | { int16_t src = m68k_read_memory_16(srca); | |
10602 | m68k_areg (regs, srcreg) = srca; | |
10603 | regs.sr = src; | |
10604 | MakeFromSR(); | |
10605 | }}}}m68k_incpc(2); | |
10606 | endlabel691: ; | |
10607 | return 18; | |
10608 | } | |
10609 | unsigned long CPUFUNC(op_46e8_4)(uint32_t opcode) /* MV2SR */ | |
10610 | { | |
10611 | uint32_t srcreg = (opcode & 7); | |
10612 | OpcodeFamily = 33; CurrentInstrCycles = 20; | |
10613 | {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel692; } | |
10614 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
10615 | { int16_t src = m68k_read_memory_16(srca); | |
10616 | regs.sr = src; | |
10617 | MakeFromSR(); | |
10618 | }}}}m68k_incpc(4); | |
10619 | endlabel692: ; | |
10620 | return 20; | |
10621 | } | |
10622 | unsigned long CPUFUNC(op_46f0_4)(uint32_t opcode) /* MV2SR */ | |
10623 | { | |
10624 | uint32_t srcreg = (opcode & 7); | |
10625 | OpcodeFamily = 33; CurrentInstrCycles = 22; | |
10626 | {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel693; } | |
10627 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
10628 | BusCyclePenalty += 2; | |
10629 | { int16_t src = m68k_read_memory_16(srca); | |
10630 | regs.sr = src; | |
10631 | MakeFromSR(); | |
10632 | }}}}m68k_incpc(4); | |
10633 | endlabel693: ; | |
10634 | return 22; | |
10635 | } | |
10636 | unsigned long CPUFUNC(op_46f8_4)(uint32_t opcode) /* MV2SR */ | |
10637 | { | |
10638 | OpcodeFamily = 33; CurrentInstrCycles = 20; | |
10639 | {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel694; } | |
10640 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
10641 | { int16_t src = m68k_read_memory_16(srca); | |
10642 | regs.sr = src; | |
10643 | MakeFromSR(); | |
10644 | }}}}m68k_incpc(4); | |
10645 | endlabel694: ; | |
10646 | return 20; | |
10647 | } | |
10648 | unsigned long CPUFUNC(op_46f9_4)(uint32_t opcode) /* MV2SR */ | |
10649 | { | |
10650 | OpcodeFamily = 33; CurrentInstrCycles = 24; | |
10651 | {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel695; } | |
10652 | {{ uint32_t srca = get_ilong(2); | |
10653 | { int16_t src = m68k_read_memory_16(srca); | |
10654 | regs.sr = src; | |
10655 | MakeFromSR(); | |
10656 | }}}}m68k_incpc(6); | |
10657 | endlabel695: ; | |
10658 | return 24; | |
10659 | } | |
10660 | unsigned long CPUFUNC(op_46fa_4)(uint32_t opcode) /* MV2SR */ | |
10661 | { | |
10662 | OpcodeFamily = 33; CurrentInstrCycles = 20; | |
10663 | {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel696; } | |
10664 | {{ uint32_t srca = m68k_getpc () + 2; | |
10665 | srca += (int32_t)(int16_t)get_iword(2); | |
10666 | { int16_t src = m68k_read_memory_16(srca); | |
10667 | regs.sr = src; | |
10668 | MakeFromSR(); | |
10669 | }}}}m68k_incpc(4); | |
10670 | endlabel696: ; | |
10671 | return 20; | |
10672 | } | |
10673 | unsigned long CPUFUNC(op_46fb_4)(uint32_t opcode) /* MV2SR */ | |
10674 | { | |
10675 | OpcodeFamily = 33; CurrentInstrCycles = 22; | |
10676 | {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel697; } | |
10677 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
10678 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
10679 | BusCyclePenalty += 2; | |
10680 | { int16_t src = m68k_read_memory_16(srca); | |
10681 | regs.sr = src; | |
10682 | MakeFromSR(); | |
10683 | }}}}m68k_incpc(4); | |
10684 | endlabel697: ; | |
10685 | return 22; | |
10686 | } | |
10687 | unsigned long CPUFUNC(op_46fc_4)(uint32_t opcode) /* MV2SR */ | |
10688 | { | |
10689 | OpcodeFamily = 33; CurrentInstrCycles = 16; | |
10690 | {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel698; } | |
10691 | {{ int16_t src = get_iword(2); | |
10692 | regs.sr = src; | |
10693 | MakeFromSR(); | |
10694 | }}}m68k_incpc(4); | |
10695 | endlabel698: ; | |
10696 | return 16; | |
10697 | } | |
10698 | unsigned long CPUFUNC(op_4800_4)(uint32_t opcode) /* NBCD */ | |
10699 | { | |
10700 | uint32_t srcreg = (opcode & 7); | |
10701 | OpcodeFamily = 17; CurrentInstrCycles = 6; | |
10702 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
10703 | { uint16_t newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0); | |
10704 | uint16_t newv_hi = - (src & 0xF0); | |
10705 | uint16_t newv; | |
10706 | int cflg; | |
10707 | if (newv_lo > 9) { newv_lo -= 6; } | |
10708 | newv = newv_hi + newv_lo; cflg = (newv & 0x1F0) > 0x90; | |
10709 | if (cflg) newv -= 0x60; | |
10710 | SET_CFLG (cflg); | |
10711 | COPY_CARRY; | |
10712 | SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); | |
10713 | SET_NFLG (((int8_t)(newv)) < 0); | |
10714 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((newv) & 0xff); | |
10715 | }}}m68k_incpc(2); | |
10716 | return 6; | |
10717 | } | |
10718 | unsigned long CPUFUNC(op_4810_4)(uint32_t opcode) /* NBCD */ | |
10719 | { | |
10720 | uint32_t srcreg = (opcode & 7); | |
10721 | OpcodeFamily = 17; CurrentInstrCycles = 12; | |
10722 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
10723 | { int8_t src = m68k_read_memory_8(srca); | |
10724 | { uint16_t newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0); | |
10725 | uint16_t newv_hi = - (src & 0xF0); | |
10726 | uint16_t newv; | |
10727 | int cflg; | |
10728 | if (newv_lo > 9) { newv_lo -= 6; } | |
10729 | newv = newv_hi + newv_lo; cflg = (newv & 0x1F0) > 0x90; | |
10730 | if (cflg) newv -= 0x60; | |
10731 | SET_CFLG (cflg); | |
10732 | COPY_CARRY; | |
10733 | SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); | |
10734 | SET_NFLG (((int8_t)(newv)) < 0); | |
10735 | m68k_write_memory_8(srca,newv); | |
10736 | }}}}m68k_incpc(2); | |
10737 | return 12; | |
10738 | } | |
10739 | unsigned long CPUFUNC(op_4818_4)(uint32_t opcode) /* NBCD */ | |
10740 | { | |
10741 | uint32_t srcreg = (opcode & 7); | |
10742 | OpcodeFamily = 17; CurrentInstrCycles = 12; | |
10743 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
10744 | { int8_t src = m68k_read_memory_8(srca); | |
10745 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
10746 | { uint16_t newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0); | |
10747 | uint16_t newv_hi = - (src & 0xF0); | |
10748 | uint16_t newv; | |
10749 | int cflg; | |
10750 | if (newv_lo > 9) { newv_lo -= 6; } | |
10751 | newv = newv_hi + newv_lo; cflg = (newv & 0x1F0) > 0x90; | |
10752 | if (cflg) newv -= 0x60; | |
10753 | SET_CFLG (cflg); | |
10754 | COPY_CARRY; | |
10755 | SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); | |
10756 | SET_NFLG (((int8_t)(newv)) < 0); | |
10757 | m68k_write_memory_8(srca,newv); | |
10758 | }}}}m68k_incpc(2); | |
10759 | return 12; | |
10760 | } | |
10761 | unsigned long CPUFUNC(op_4820_4)(uint32_t opcode) /* NBCD */ | |
10762 | { | |
10763 | uint32_t srcreg = (opcode & 7); | |
10764 | OpcodeFamily = 17; CurrentInstrCycles = 14; | |
10765 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
10766 | { int8_t src = m68k_read_memory_8(srca); | |
10767 | m68k_areg (regs, srcreg) = srca; | |
10768 | { uint16_t newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0); | |
10769 | uint16_t newv_hi = - (src & 0xF0); | |
10770 | uint16_t newv; | |
10771 | int cflg; | |
10772 | if (newv_lo > 9) { newv_lo -= 6; } | |
10773 | newv = newv_hi + newv_lo; cflg = (newv & 0x1F0) > 0x90; | |
10774 | if (cflg) newv -= 0x60; | |
10775 | SET_CFLG (cflg); | |
10776 | COPY_CARRY; | |
10777 | SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); | |
10778 | SET_NFLG (((int8_t)(newv)) < 0); | |
10779 | m68k_write_memory_8(srca,newv); | |
10780 | }}}}m68k_incpc(2); | |
10781 | return 14; | |
10782 | } | |
10783 | unsigned long CPUFUNC(op_4828_4)(uint32_t opcode) /* NBCD */ | |
10784 | { | |
10785 | uint32_t srcreg = (opcode & 7); | |
10786 | OpcodeFamily = 17; CurrentInstrCycles = 16; | |
10787 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
10788 | { int8_t src = m68k_read_memory_8(srca); | |
10789 | { uint16_t newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0); | |
10790 | uint16_t newv_hi = - (src & 0xF0); | |
10791 | uint16_t newv; | |
10792 | int cflg; | |
10793 | if (newv_lo > 9) { newv_lo -= 6; } | |
10794 | newv = newv_hi + newv_lo; cflg = (newv & 0x1F0) > 0x90; | |
10795 | if (cflg) newv -= 0x60; | |
10796 | SET_CFLG (cflg); | |
10797 | COPY_CARRY; | |
10798 | SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); | |
10799 | SET_NFLG (((int8_t)(newv)) < 0); | |
10800 | m68k_write_memory_8(srca,newv); | |
10801 | }}}}m68k_incpc(4); | |
10802 | return 16; | |
10803 | } | |
10804 | unsigned long CPUFUNC(op_4830_4)(uint32_t opcode) /* NBCD */ | |
10805 | { | |
10806 | uint32_t srcreg = (opcode & 7); | |
10807 | OpcodeFamily = 17; CurrentInstrCycles = 18; | |
10808 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
10809 | BusCyclePenalty += 2; | |
10810 | { int8_t src = m68k_read_memory_8(srca); | |
10811 | { uint16_t newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0); | |
10812 | uint16_t newv_hi = - (src & 0xF0); | |
10813 | uint16_t newv; | |
10814 | int cflg; | |
10815 | if (newv_lo > 9) { newv_lo -= 6; } | |
10816 | newv = newv_hi + newv_lo; cflg = (newv & 0x1F0) > 0x90; | |
10817 | if (cflg) newv -= 0x60; | |
10818 | SET_CFLG (cflg); | |
10819 | COPY_CARRY; | |
10820 | SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); | |
10821 | SET_NFLG (((int8_t)(newv)) < 0); | |
10822 | m68k_write_memory_8(srca,newv); | |
10823 | }}}}m68k_incpc(4); | |
10824 | return 18; | |
10825 | } | |
10826 | unsigned long CPUFUNC(op_4838_4)(uint32_t opcode) /* NBCD */ | |
10827 | { | |
10828 | OpcodeFamily = 17; CurrentInstrCycles = 16; | |
10829 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
10830 | { int8_t src = m68k_read_memory_8(srca); | |
10831 | { uint16_t newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0); | |
10832 | uint16_t newv_hi = - (src & 0xF0); | |
10833 | uint16_t newv; | |
10834 | int cflg; | |
10835 | if (newv_lo > 9) { newv_lo -= 6; } | |
10836 | newv = newv_hi + newv_lo; cflg = (newv & 0x1F0) > 0x90; | |
10837 | if (cflg) newv -= 0x60; | |
10838 | SET_CFLG (cflg); | |
10839 | COPY_CARRY; | |
10840 | SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); | |
10841 | SET_NFLG (((int8_t)(newv)) < 0); | |
10842 | m68k_write_memory_8(srca,newv); | |
10843 | }}}}m68k_incpc(4); | |
10844 | return 16; | |
10845 | } | |
10846 | unsigned long CPUFUNC(op_4839_4)(uint32_t opcode) /* NBCD */ | |
10847 | { | |
10848 | OpcodeFamily = 17; CurrentInstrCycles = 20; | |
10849 | {{ uint32_t srca = get_ilong(2); | |
10850 | { int8_t src = m68k_read_memory_8(srca); | |
10851 | { uint16_t newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0); | |
10852 | uint16_t newv_hi = - (src & 0xF0); | |
10853 | uint16_t newv; | |
10854 | int cflg; | |
10855 | if (newv_lo > 9) { newv_lo -= 6; } | |
10856 | newv = newv_hi + newv_lo; cflg = (newv & 0x1F0) > 0x90; | |
10857 | if (cflg) newv -= 0x60; | |
10858 | SET_CFLG (cflg); | |
10859 | COPY_CARRY; | |
10860 | SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); | |
10861 | SET_NFLG (((int8_t)(newv)) < 0); | |
10862 | m68k_write_memory_8(srca,newv); | |
10863 | }}}}m68k_incpc(6); | |
10864 | return 20; | |
10865 | } | |
10866 | unsigned long CPUFUNC(op_4840_4)(uint32_t opcode) /* SWAP */ | |
10867 | { | |
10868 | uint32_t srcreg = (opcode & 7); | |
10869 | OpcodeFamily = 34; CurrentInstrCycles = 4; | |
10870 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
10871 | { uint32_t dst = ((src >> 16)&0xFFFF) | ((src&0xFFFF)<<16); | |
10872 | CLEAR_CZNV; | |
10873 | SET_ZFLG (((int32_t)(dst)) == 0); | |
10874 | SET_NFLG (((int32_t)(dst)) < 0); | |
10875 | m68k_dreg(regs, srcreg) = (dst); | |
10876 | }}}m68k_incpc(2); | |
10877 | return 4; | |
10878 | } | |
10879 | unsigned long CPUFUNC(op_4850_4)(uint32_t opcode) /* PEA */ | |
10880 | { | |
10881 | uint32_t srcreg = (opcode & 7); | |
10882 | OpcodeFamily = 57; CurrentInstrCycles = 12; | |
10883 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
10884 | { uint32_t dsta = m68k_areg(regs, 7) - 4; | |
10885 | m68k_areg (regs, 7) = dsta; | |
10886 | m68k_write_memory_32(dsta,srca); | |
10887 | }}}m68k_incpc(2); | |
10888 | return 12; | |
10889 | } | |
10890 | unsigned long CPUFUNC(op_4868_4)(uint32_t opcode) /* PEA */ | |
10891 | { | |
10892 | uint32_t srcreg = (opcode & 7); | |
10893 | OpcodeFamily = 57; CurrentInstrCycles = 16; | |
10894 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
10895 | { uint32_t dsta = m68k_areg(regs, 7) - 4; | |
10896 | m68k_areg (regs, 7) = dsta; | |
10897 | m68k_write_memory_32(dsta,srca); | |
10898 | }}}m68k_incpc(4); | |
10899 | return 16; | |
10900 | } | |
10901 | unsigned long CPUFUNC(op_4870_4)(uint32_t opcode) /* PEA */ | |
10902 | { | |
10903 | uint32_t srcreg = (opcode & 7); | |
10904 | OpcodeFamily = 57; CurrentInstrCycles = 22; | |
10905 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
10906 | BusCyclePenalty += 2; | |
10907 | { uint32_t dsta = m68k_areg(regs, 7) - 4; | |
10908 | m68k_areg (regs, 7) = dsta; | |
10909 | m68k_write_memory_32(dsta,srca); | |
10910 | }}}m68k_incpc(4); | |
10911 | return 22; | |
10912 | } | |
10913 | unsigned long CPUFUNC(op_4878_4)(uint32_t opcode) /* PEA */ | |
10914 | { | |
10915 | OpcodeFamily = 57; CurrentInstrCycles = 16; | |
10916 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
10917 | { uint32_t dsta = m68k_areg(regs, 7) - 4; | |
10918 | m68k_areg (regs, 7) = dsta; | |
10919 | m68k_write_memory_32(dsta,srca); | |
10920 | }}}m68k_incpc(4); | |
10921 | return 16; | |
10922 | } | |
10923 | unsigned long CPUFUNC(op_4879_4)(uint32_t opcode) /* PEA */ | |
10924 | { | |
10925 | OpcodeFamily = 57; CurrentInstrCycles = 20; | |
10926 | {{ uint32_t srca = get_ilong(2); | |
10927 | { uint32_t dsta = m68k_areg(regs, 7) - 4; | |
10928 | m68k_areg (regs, 7) = dsta; | |
10929 | m68k_write_memory_32(dsta,srca); | |
10930 | }}}m68k_incpc(6); | |
10931 | return 20; | |
10932 | } | |
10933 | unsigned long CPUFUNC(op_487a_4)(uint32_t opcode) /* PEA */ | |
10934 | { | |
10935 | OpcodeFamily = 57; CurrentInstrCycles = 16; | |
10936 | {{ uint32_t srca = m68k_getpc () + 2; | |
10937 | srca += (int32_t)(int16_t)get_iword(2); | |
10938 | { uint32_t dsta = m68k_areg(regs, 7) - 4; | |
10939 | m68k_areg (regs, 7) = dsta; | |
10940 | m68k_write_memory_32(dsta,srca); | |
10941 | }}}m68k_incpc(4); | |
10942 | return 16; | |
10943 | } | |
10944 | unsigned long CPUFUNC(op_487b_4)(uint32_t opcode) /* PEA */ | |
10945 | { | |
10946 | OpcodeFamily = 57; CurrentInstrCycles = 22; | |
10947 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
10948 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
10949 | BusCyclePenalty += 2; | |
10950 | { uint32_t dsta = m68k_areg(regs, 7) - 4; | |
10951 | m68k_areg (regs, 7) = dsta; | |
10952 | m68k_write_memory_32(dsta,srca); | |
10953 | }}}m68k_incpc(4); | |
10954 | return 22; | |
10955 | } | |
10956 | unsigned long CPUFUNC(op_4880_4)(uint32_t opcode) /* EXT */ | |
10957 | { | |
10958 | uint32_t srcreg = (opcode & 7); | |
10959 | OpcodeFamily = 36; CurrentInstrCycles = 4; | |
10960 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
10961 | { uint16_t dst = (int16_t)(int8_t)src; | |
10962 | CLEAR_CZNV; | |
10963 | SET_ZFLG (((int16_t)(dst)) == 0); | |
10964 | SET_NFLG (((int16_t)(dst)) < 0); | |
10965 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((dst) & 0xffff); | |
10966 | }}}m68k_incpc(2); | |
10967 | return 4; | |
10968 | } | |
10969 | unsigned long CPUFUNC(op_4890_4)(uint32_t opcode) /* MVMLE */ | |
10970 | { | |
10971 | uint32_t dstreg = opcode & 7; | |
10972 | unsigned int retcycles = 0; | |
10973 | OpcodeFamily = 38; CurrentInstrCycles = 8; | |
10974 | { uint16_t mask = get_iword(2); | |
10975 | retcycles = 0; | |
10976 | { uint32_t srca = m68k_areg(regs, dstreg); | |
10977 | { uint16_t dmask = mask & 0xff, amask = (mask >> 8) & 0xff; | |
10978 | while (dmask) { m68k_write_memory_16(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; retcycles+=4; } | |
10979 | while (amask) { m68k_write_memory_16(srca, m68k_areg(regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; retcycles+=4; } | |
10980 | }}}m68k_incpc(4); | |
10981 | return (8+retcycles); | |
10982 | } | |
10983 | unsigned long CPUFUNC(op_48a0_4)(uint32_t opcode) /* MVMLE */ | |
10984 | { | |
10985 | uint32_t dstreg = opcode & 7; | |
10986 | unsigned int retcycles = 0; | |
10987 | OpcodeFamily = 38; CurrentInstrCycles = 8; | |
10988 | { uint16_t mask = get_iword(2); | |
10989 | retcycles = 0; | |
10990 | { uint32_t srca = m68k_areg(regs, dstreg) - 0; | |
10991 | { uint16_t amask = mask & 0xff, dmask = (mask >> 8) & 0xff; | |
10992 | while (amask) { srca -= 2; m68k_write_memory_16(srca, m68k_areg(regs, movem_index2[amask])); amask = movem_next[amask]; retcycles+=4; } | |
10993 | while (dmask) { srca -= 2; m68k_write_memory_16(srca, m68k_dreg(regs, movem_index2[dmask])); dmask = movem_next[dmask]; retcycles+=4; } | |
10994 | m68k_areg(regs, dstreg) = srca; | |
10995 | }}}m68k_incpc(4); | |
10996 | return (8+retcycles); | |
10997 | } | |
10998 | unsigned long CPUFUNC(op_48a8_4)(uint32_t opcode) /* MVMLE */ | |
10999 | { | |
11000 | uint32_t dstreg = opcode & 7; | |
11001 | unsigned int retcycles = 0; | |
11002 | OpcodeFamily = 38; CurrentInstrCycles = 12; | |
11003 | { uint16_t mask = get_iword(2); | |
11004 | retcycles = 0; | |
11005 | { uint32_t srca = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); | |
11006 | { uint16_t dmask = mask & 0xff, amask = (mask >> 8) & 0xff; | |
11007 | while (dmask) { m68k_write_memory_16(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; retcycles+=4; } | |
11008 | while (amask) { m68k_write_memory_16(srca, m68k_areg(regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; retcycles+=4; } | |
11009 | }}}m68k_incpc(6); | |
11010 | return (12+retcycles); | |
11011 | } | |
11012 | unsigned long CPUFUNC(op_48b0_4)(uint32_t opcode) /* MVMLE */ | |
11013 | { | |
11014 | uint32_t dstreg = opcode & 7; | |
11015 | unsigned int retcycles = 0; | |
11016 | OpcodeFamily = 38; CurrentInstrCycles = 14; | |
11017 | { uint16_t mask = get_iword(2); | |
11018 | retcycles = 0; | |
11019 | { uint32_t srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); | |
11020 | BusCyclePenalty += 2; | |
11021 | { uint16_t dmask = mask & 0xff, amask = (mask >> 8) & 0xff; | |
11022 | while (dmask) { m68k_write_memory_16(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; retcycles+=4; } | |
11023 | while (amask) { m68k_write_memory_16(srca, m68k_areg(regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; retcycles+=4; } | |
11024 | }}}m68k_incpc(6); | |
11025 | return (14+retcycles); | |
11026 | } | |
11027 | unsigned long CPUFUNC(op_48b8_4)(uint32_t opcode) /* MVMLE */ | |
11028 | { | |
11029 | unsigned int retcycles = 0; | |
11030 | OpcodeFamily = 38; CurrentInstrCycles = 12; | |
11031 | { uint16_t mask = get_iword(2); | |
11032 | retcycles = 0; | |
11033 | { uint32_t srca = (int32_t)(int16_t)get_iword(4); | |
11034 | { uint16_t dmask = mask & 0xff, amask = (mask >> 8) & 0xff; | |
11035 | while (dmask) { m68k_write_memory_16(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; retcycles+=4; } | |
11036 | while (amask) { m68k_write_memory_16(srca, m68k_areg(regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; retcycles+=4; } | |
11037 | }}}m68k_incpc(6); | |
11038 | return (12+retcycles); | |
11039 | } | |
11040 | unsigned long CPUFUNC(op_48b9_4)(uint32_t opcode) /* MVMLE */ | |
11041 | { | |
11042 | unsigned int retcycles = 0; | |
11043 | OpcodeFamily = 38; CurrentInstrCycles = 16; | |
11044 | { uint16_t mask = get_iword(2); | |
11045 | retcycles = 0; | |
11046 | { uint32_t srca = get_ilong(4); | |
11047 | { uint16_t dmask = mask & 0xff, amask = (mask >> 8) & 0xff; | |
11048 | while (dmask) { m68k_write_memory_16(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; retcycles+=4; } | |
11049 | while (amask) { m68k_write_memory_16(srca, m68k_areg(regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; retcycles+=4; } | |
11050 | }}}m68k_incpc(8); | |
11051 | return (16+retcycles); | |
11052 | } | |
11053 | unsigned long CPUFUNC(op_48c0_4)(uint32_t opcode) /* EXT */ | |
11054 | { | |
11055 | uint32_t srcreg = (opcode & 7); | |
11056 | OpcodeFamily = 36; CurrentInstrCycles = 4; | |
11057 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
11058 | { uint32_t dst = (int32_t)(int16_t)src; | |
11059 | CLEAR_CZNV; | |
11060 | SET_ZFLG (((int32_t)(dst)) == 0); | |
11061 | SET_NFLG (((int32_t)(dst)) < 0); | |
11062 | m68k_dreg(regs, srcreg) = (dst); | |
11063 | }}}m68k_incpc(2); | |
11064 | return 4; | |
11065 | } | |
11066 | unsigned long CPUFUNC(op_48d0_4)(uint32_t opcode) /* MVMLE */ | |
11067 | { | |
11068 | uint32_t dstreg = opcode & 7; | |
11069 | unsigned int retcycles = 0; | |
11070 | OpcodeFamily = 38; CurrentInstrCycles = 8; | |
11071 | { uint16_t mask = get_iword(2); | |
11072 | retcycles = 0; | |
11073 | { uint32_t srca = m68k_areg(regs, dstreg); | |
11074 | { uint16_t dmask = mask & 0xff, amask = (mask >> 8) & 0xff; | |
11075 | while (dmask) { m68k_write_memory_32(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; retcycles+=8; } | |
11076 | while (amask) { m68k_write_memory_32(srca, m68k_areg(regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; retcycles+=8; } | |
11077 | }}}m68k_incpc(4); | |
11078 | return (8+retcycles); | |
11079 | } | |
11080 | unsigned long CPUFUNC(op_48e0_4)(uint32_t opcode) /* MVMLE */ | |
11081 | { | |
11082 | uint32_t dstreg = opcode & 7; | |
11083 | unsigned int retcycles = 0; | |
11084 | OpcodeFamily = 38; CurrentInstrCycles = 8; | |
11085 | { uint16_t mask = get_iword(2); | |
11086 | retcycles = 0; | |
11087 | { uint32_t srca = m68k_areg(regs, dstreg) - 0; | |
11088 | { uint16_t amask = mask & 0xff, dmask = (mask >> 8) & 0xff; | |
11089 | while (amask) { srca -= 4; m68k_write_memory_32(srca, m68k_areg(regs, movem_index2[amask])); amask = movem_next[amask]; retcycles+=8; } | |
11090 | while (dmask) { srca -= 4; m68k_write_memory_32(srca, m68k_dreg(regs, movem_index2[dmask])); dmask = movem_next[dmask]; retcycles+=8; } | |
11091 | m68k_areg(regs, dstreg) = srca; | |
11092 | }}}m68k_incpc(4); | |
11093 | return (8+retcycles); | |
11094 | } | |
11095 | unsigned long CPUFUNC(op_48e8_4)(uint32_t opcode) /* MVMLE */ | |
11096 | { | |
11097 | uint32_t dstreg = opcode & 7; | |
11098 | unsigned int retcycles = 0; | |
11099 | OpcodeFamily = 38; CurrentInstrCycles = 12; | |
11100 | { uint16_t mask = get_iword(2); | |
11101 | retcycles = 0; | |
11102 | { uint32_t srca = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); | |
11103 | { uint16_t dmask = mask & 0xff, amask = (mask >> 8) & 0xff; | |
11104 | while (dmask) { m68k_write_memory_32(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; retcycles+=8; } | |
11105 | while (amask) { m68k_write_memory_32(srca, m68k_areg(regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; retcycles+=8; } | |
11106 | }}}m68k_incpc(6); | |
11107 | return (12+retcycles); | |
11108 | } | |
11109 | unsigned long CPUFUNC(op_48f0_4)(uint32_t opcode) /* MVMLE */ | |
11110 | { | |
11111 | uint32_t dstreg = opcode & 7; | |
11112 | unsigned int retcycles = 0; | |
11113 | OpcodeFamily = 38; CurrentInstrCycles = 14; | |
11114 | { uint16_t mask = get_iword(2); | |
11115 | retcycles = 0; | |
11116 | { uint32_t srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); | |
11117 | BusCyclePenalty += 2; | |
11118 | { uint16_t dmask = mask & 0xff, amask = (mask >> 8) & 0xff; | |
11119 | while (dmask) { m68k_write_memory_32(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; retcycles+=8; } | |
11120 | while (amask) { m68k_write_memory_32(srca, m68k_areg(regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; retcycles+=8; } | |
11121 | }}}m68k_incpc(6); | |
11122 | return (14+retcycles); | |
11123 | } | |
11124 | unsigned long CPUFUNC(op_48f8_4)(uint32_t opcode) /* MVMLE */ | |
11125 | { | |
11126 | unsigned int retcycles = 0; | |
11127 | OpcodeFamily = 38; CurrentInstrCycles = 12; | |
11128 | { uint16_t mask = get_iword(2); | |
11129 | retcycles = 0; | |
11130 | { uint32_t srca = (int32_t)(int16_t)get_iword(4); | |
11131 | { uint16_t dmask = mask & 0xff, amask = (mask >> 8) & 0xff; | |
11132 | while (dmask) { m68k_write_memory_32(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; retcycles+=8; } | |
11133 | while (amask) { m68k_write_memory_32(srca, m68k_areg(regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; retcycles+=8; } | |
11134 | }}}m68k_incpc(6); | |
11135 | return (12+retcycles); | |
11136 | } | |
11137 | unsigned long CPUFUNC(op_48f9_4)(uint32_t opcode) /* MVMLE */ | |
11138 | { | |
11139 | unsigned int retcycles = 0; | |
11140 | OpcodeFamily = 38; CurrentInstrCycles = 16; | |
11141 | { uint16_t mask = get_iword(2); | |
11142 | retcycles = 0; | |
11143 | { uint32_t srca = get_ilong(4); | |
11144 | { uint16_t dmask = mask & 0xff, amask = (mask >> 8) & 0xff; | |
11145 | while (dmask) { m68k_write_memory_32(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; retcycles+=8; } | |
11146 | while (amask) { m68k_write_memory_32(srca, m68k_areg(regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; retcycles+=8; } | |
11147 | }}}m68k_incpc(8); | |
11148 | return (16+retcycles); | |
11149 | } | |
11150 | unsigned long CPUFUNC(op_4a00_4)(uint32_t opcode) /* TST */ | |
11151 | { | |
11152 | uint32_t srcreg = (opcode & 7); | |
11153 | OpcodeFamily = 20; CurrentInstrCycles = 4; | |
11154 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
11155 | CLEAR_CZNV; | |
11156 | SET_ZFLG (((int8_t)(src)) == 0); | |
11157 | SET_NFLG (((int8_t)(src)) < 0); | |
11158 | }}m68k_incpc(2); | |
11159 | return 4; | |
11160 | } | |
11161 | unsigned long CPUFUNC(op_4a10_4)(uint32_t opcode) /* TST */ | |
11162 | { | |
11163 | uint32_t srcreg = (opcode & 7); | |
11164 | OpcodeFamily = 20; CurrentInstrCycles = 8; | |
11165 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
11166 | { int8_t src = m68k_read_memory_8(srca); | |
11167 | CLEAR_CZNV; | |
11168 | SET_ZFLG (((int8_t)(src)) == 0); | |
11169 | SET_NFLG (((int8_t)(src)) < 0); | |
11170 | }}}m68k_incpc(2); | |
11171 | return 8; | |
11172 | } | |
11173 | unsigned long CPUFUNC(op_4a18_4)(uint32_t opcode) /* TST */ | |
11174 | { | |
11175 | uint32_t srcreg = (opcode & 7); | |
11176 | OpcodeFamily = 20; CurrentInstrCycles = 8; | |
11177 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
11178 | { int8_t src = m68k_read_memory_8(srca); | |
11179 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
11180 | CLEAR_CZNV; | |
11181 | SET_ZFLG (((int8_t)(src)) == 0); | |
11182 | SET_NFLG (((int8_t)(src)) < 0); | |
11183 | }}}m68k_incpc(2); | |
11184 | return 8; | |
11185 | } | |
11186 | unsigned long CPUFUNC(op_4a20_4)(uint32_t opcode) /* TST */ | |
11187 | { | |
11188 | uint32_t srcreg = (opcode & 7); | |
11189 | OpcodeFamily = 20; CurrentInstrCycles = 10; | |
11190 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
11191 | { int8_t src = m68k_read_memory_8(srca); | |
11192 | m68k_areg (regs, srcreg) = srca; | |
11193 | CLEAR_CZNV; | |
11194 | SET_ZFLG (((int8_t)(src)) == 0); | |
11195 | SET_NFLG (((int8_t)(src)) < 0); | |
11196 | }}}m68k_incpc(2); | |
11197 | return 10; | |
11198 | } | |
11199 | unsigned long CPUFUNC(op_4a28_4)(uint32_t opcode) /* TST */ | |
11200 | { | |
11201 | uint32_t srcreg = (opcode & 7); | |
11202 | OpcodeFamily = 20; CurrentInstrCycles = 12; | |
11203 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
11204 | { int8_t src = m68k_read_memory_8(srca); | |
11205 | CLEAR_CZNV; | |
11206 | SET_ZFLG (((int8_t)(src)) == 0); | |
11207 | SET_NFLG (((int8_t)(src)) < 0); | |
11208 | }}}m68k_incpc(4); | |
11209 | return 12; | |
11210 | } | |
11211 | unsigned long CPUFUNC(op_4a30_4)(uint32_t opcode) /* TST */ | |
11212 | { | |
11213 | uint32_t srcreg = (opcode & 7); | |
11214 | OpcodeFamily = 20; CurrentInstrCycles = 14; | |
11215 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
11216 | BusCyclePenalty += 2; | |
11217 | { int8_t src = m68k_read_memory_8(srca); | |
11218 | CLEAR_CZNV; | |
11219 | SET_ZFLG (((int8_t)(src)) == 0); | |
11220 | SET_NFLG (((int8_t)(src)) < 0); | |
11221 | }}}m68k_incpc(4); | |
11222 | return 14; | |
11223 | } | |
11224 | unsigned long CPUFUNC(op_4a38_4)(uint32_t opcode) /* TST */ | |
11225 | { | |
11226 | OpcodeFamily = 20; CurrentInstrCycles = 12; | |
11227 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
11228 | { int8_t src = m68k_read_memory_8(srca); | |
11229 | CLEAR_CZNV; | |
11230 | SET_ZFLG (((int8_t)(src)) == 0); | |
11231 | SET_NFLG (((int8_t)(src)) < 0); | |
11232 | }}}m68k_incpc(4); | |
11233 | return 12; | |
11234 | } | |
11235 | unsigned long CPUFUNC(op_4a39_4)(uint32_t opcode) /* TST */ | |
11236 | { | |
11237 | OpcodeFamily = 20; CurrentInstrCycles = 16; | |
11238 | {{ uint32_t srca = get_ilong(2); | |
11239 | { int8_t src = m68k_read_memory_8(srca); | |
11240 | CLEAR_CZNV; | |
11241 | SET_ZFLG (((int8_t)(src)) == 0); | |
11242 | SET_NFLG (((int8_t)(src)) < 0); | |
11243 | }}}m68k_incpc(6); | |
11244 | return 16; | |
11245 | } | |
11246 | unsigned long CPUFUNC(op_4a3a_4)(uint32_t opcode) /* TST */ | |
11247 | { | |
11248 | OpcodeFamily = 20; CurrentInstrCycles = 12; | |
11249 | {{ uint32_t srca = m68k_getpc () + 2; | |
11250 | srca += (int32_t)(int16_t)get_iword(2); | |
11251 | { int8_t src = m68k_read_memory_8(srca); | |
11252 | CLEAR_CZNV; | |
11253 | SET_ZFLG (((int8_t)(src)) == 0); | |
11254 | SET_NFLG (((int8_t)(src)) < 0); | |
11255 | }}}m68k_incpc(4); | |
11256 | return 12; | |
11257 | } | |
11258 | unsigned long CPUFUNC(op_4a3b_4)(uint32_t opcode) /* TST */ | |
11259 | { | |
11260 | OpcodeFamily = 20; CurrentInstrCycles = 14; | |
11261 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
11262 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
11263 | BusCyclePenalty += 2; | |
11264 | { int8_t src = m68k_read_memory_8(srca); | |
11265 | CLEAR_CZNV; | |
11266 | SET_ZFLG (((int8_t)(src)) == 0); | |
11267 | SET_NFLG (((int8_t)(src)) < 0); | |
11268 | }}}m68k_incpc(4); | |
11269 | return 14; | |
11270 | } | |
11271 | unsigned long CPUFUNC(op_4a3c_4)(uint32_t opcode) /* TST */ | |
11272 | { | |
11273 | OpcodeFamily = 20; CurrentInstrCycles = 8; | |
11274 | {{ int8_t src = get_ibyte(2); | |
11275 | CLEAR_CZNV; | |
11276 | SET_ZFLG (((int8_t)(src)) == 0); | |
11277 | SET_NFLG (((int8_t)(src)) < 0); | |
11278 | }}m68k_incpc(4); | |
11279 | return 8; | |
11280 | } | |
11281 | unsigned long CPUFUNC(op_4a40_4)(uint32_t opcode) /* TST */ | |
11282 | { | |
11283 | uint32_t srcreg = (opcode & 7); | |
11284 | OpcodeFamily = 20; CurrentInstrCycles = 4; | |
11285 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
11286 | CLEAR_CZNV; | |
11287 | SET_ZFLG (((int16_t)(src)) == 0); | |
11288 | SET_NFLG (((int16_t)(src)) < 0); | |
11289 | }}m68k_incpc(2); | |
11290 | return 4; | |
11291 | } | |
11292 | unsigned long CPUFUNC(op_4a48_4)(uint32_t opcode) /* TST */ | |
11293 | { | |
11294 | uint32_t srcreg = (opcode & 7); | |
11295 | OpcodeFamily = 20; CurrentInstrCycles = 4; | |
11296 | {{ int16_t src = m68k_areg(regs, srcreg); | |
11297 | CLEAR_CZNV; | |
11298 | SET_ZFLG (((int16_t)(src)) == 0); | |
11299 | SET_NFLG (((int16_t)(src)) < 0); | |
11300 | }}m68k_incpc(2); | |
11301 | return 4; | |
11302 | } | |
11303 | unsigned long CPUFUNC(op_4a50_4)(uint32_t opcode) /* TST */ | |
11304 | { | |
11305 | uint32_t srcreg = (opcode & 7); | |
11306 | OpcodeFamily = 20; CurrentInstrCycles = 8; | |
11307 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
11308 | { int16_t src = m68k_read_memory_16(srca); | |
11309 | CLEAR_CZNV; | |
11310 | SET_ZFLG (((int16_t)(src)) == 0); | |
11311 | SET_NFLG (((int16_t)(src)) < 0); | |
11312 | }}}m68k_incpc(2); | |
11313 | return 8; | |
11314 | } | |
11315 | unsigned long CPUFUNC(op_4a58_4)(uint32_t opcode) /* TST */ | |
11316 | { | |
11317 | uint32_t srcreg = (opcode & 7); | |
11318 | OpcodeFamily = 20; CurrentInstrCycles = 8; | |
11319 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
11320 | { int16_t src = m68k_read_memory_16(srca); | |
11321 | m68k_areg(regs, srcreg) += 2; | |
11322 | CLEAR_CZNV; | |
11323 | SET_ZFLG (((int16_t)(src)) == 0); | |
11324 | SET_NFLG (((int16_t)(src)) < 0); | |
11325 | }}}m68k_incpc(2); | |
11326 | return 8; | |
11327 | } | |
11328 | unsigned long CPUFUNC(op_4a60_4)(uint32_t opcode) /* TST */ | |
11329 | { | |
11330 | uint32_t srcreg = (opcode & 7); | |
11331 | OpcodeFamily = 20; CurrentInstrCycles = 10; | |
11332 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
11333 | { int16_t src = m68k_read_memory_16(srca); | |
11334 | m68k_areg (regs, srcreg) = srca; | |
11335 | CLEAR_CZNV; | |
11336 | SET_ZFLG (((int16_t)(src)) == 0); | |
11337 | SET_NFLG (((int16_t)(src)) < 0); | |
11338 | }}}m68k_incpc(2); | |
11339 | return 10; | |
11340 | } | |
11341 | unsigned long CPUFUNC(op_4a68_4)(uint32_t opcode) /* TST */ | |
11342 | { | |
11343 | uint32_t srcreg = (opcode & 7); | |
11344 | OpcodeFamily = 20; CurrentInstrCycles = 12; | |
11345 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
11346 | { int16_t src = m68k_read_memory_16(srca); | |
11347 | CLEAR_CZNV; | |
11348 | SET_ZFLG (((int16_t)(src)) == 0); | |
11349 | SET_NFLG (((int16_t)(src)) < 0); | |
11350 | }}}m68k_incpc(4); | |
11351 | return 12; | |
11352 | } | |
11353 | unsigned long CPUFUNC(op_4a70_4)(uint32_t opcode) /* TST */ | |
11354 | { | |
11355 | uint32_t srcreg = (opcode & 7); | |
11356 | OpcodeFamily = 20; CurrentInstrCycles = 14; | |
11357 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
11358 | BusCyclePenalty += 2; | |
11359 | { int16_t src = m68k_read_memory_16(srca); | |
11360 | CLEAR_CZNV; | |
11361 | SET_ZFLG (((int16_t)(src)) == 0); | |
11362 | SET_NFLG (((int16_t)(src)) < 0); | |
11363 | }}}m68k_incpc(4); | |
11364 | return 14; | |
11365 | } | |
11366 | unsigned long CPUFUNC(op_4a78_4)(uint32_t opcode) /* TST */ | |
11367 | { | |
11368 | OpcodeFamily = 20; CurrentInstrCycles = 12; | |
11369 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
11370 | { int16_t src = m68k_read_memory_16(srca); | |
11371 | CLEAR_CZNV; | |
11372 | SET_ZFLG (((int16_t)(src)) == 0); | |
11373 | SET_NFLG (((int16_t)(src)) < 0); | |
11374 | }}}m68k_incpc(4); | |
11375 | return 12; | |
11376 | } | |
11377 | unsigned long CPUFUNC(op_4a79_4)(uint32_t opcode) /* TST */ | |
11378 | { | |
11379 | OpcodeFamily = 20; CurrentInstrCycles = 16; | |
11380 | {{ uint32_t srca = get_ilong(2); | |
11381 | { int16_t src = m68k_read_memory_16(srca); | |
11382 | CLEAR_CZNV; | |
11383 | SET_ZFLG (((int16_t)(src)) == 0); | |
11384 | SET_NFLG (((int16_t)(src)) < 0); | |
11385 | }}}m68k_incpc(6); | |
11386 | return 16; | |
11387 | } | |
11388 | unsigned long CPUFUNC(op_4a7a_4)(uint32_t opcode) /* TST */ | |
11389 | { | |
11390 | OpcodeFamily = 20; CurrentInstrCycles = 12; | |
11391 | {{ uint32_t srca = m68k_getpc () + 2; | |
11392 | srca += (int32_t)(int16_t)get_iword(2); | |
11393 | { int16_t src = m68k_read_memory_16(srca); | |
11394 | CLEAR_CZNV; | |
11395 | SET_ZFLG (((int16_t)(src)) == 0); | |
11396 | SET_NFLG (((int16_t)(src)) < 0); | |
11397 | }}}m68k_incpc(4); | |
11398 | return 12; | |
11399 | } | |
11400 | unsigned long CPUFUNC(op_4a7b_4)(uint32_t opcode) /* TST */ | |
11401 | { | |
11402 | OpcodeFamily = 20; CurrentInstrCycles = 14; | |
11403 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
11404 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
11405 | BusCyclePenalty += 2; | |
11406 | { int16_t src = m68k_read_memory_16(srca); | |
11407 | CLEAR_CZNV; | |
11408 | SET_ZFLG (((int16_t)(src)) == 0); | |
11409 | SET_NFLG (((int16_t)(src)) < 0); | |
11410 | }}}m68k_incpc(4); | |
11411 | return 14; | |
11412 | } | |
11413 | unsigned long CPUFUNC(op_4a7c_4)(uint32_t opcode) /* TST */ | |
11414 | { | |
11415 | OpcodeFamily = 20; CurrentInstrCycles = 8; | |
11416 | {{ int16_t src = get_iword(2); | |
11417 | CLEAR_CZNV; | |
11418 | SET_ZFLG (((int16_t)(src)) == 0); | |
11419 | SET_NFLG (((int16_t)(src)) < 0); | |
11420 | }}m68k_incpc(4); | |
11421 | return 8; | |
11422 | } | |
11423 | unsigned long CPUFUNC(op_4a80_4)(uint32_t opcode) /* TST */ | |
11424 | { | |
11425 | uint32_t srcreg = (opcode & 7); | |
11426 | OpcodeFamily = 20; CurrentInstrCycles = 4; | |
11427 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
11428 | CLEAR_CZNV; | |
11429 | SET_ZFLG (((int32_t)(src)) == 0); | |
11430 | SET_NFLG (((int32_t)(src)) < 0); | |
11431 | }}m68k_incpc(2); | |
11432 | return 4; | |
11433 | } | |
11434 | unsigned long CPUFUNC(op_4a88_4)(uint32_t opcode) /* TST */ | |
11435 | { | |
11436 | uint32_t srcreg = (opcode & 7); | |
11437 | OpcodeFamily = 20; CurrentInstrCycles = 4; | |
11438 | {{ int32_t src = m68k_areg(regs, srcreg); | |
11439 | CLEAR_CZNV; | |
11440 | SET_ZFLG (((int32_t)(src)) == 0); | |
11441 | SET_NFLG (((int32_t)(src)) < 0); | |
11442 | }}m68k_incpc(2); | |
11443 | return 4; | |
11444 | } | |
11445 | unsigned long CPUFUNC(op_4a90_4)(uint32_t opcode) /* TST */ | |
11446 | { | |
11447 | uint32_t srcreg = (opcode & 7); | |
11448 | OpcodeFamily = 20; CurrentInstrCycles = 12; | |
11449 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
11450 | { int32_t src = m68k_read_memory_32(srca); | |
11451 | CLEAR_CZNV; | |
11452 | SET_ZFLG (((int32_t)(src)) == 0); | |
11453 | SET_NFLG (((int32_t)(src)) < 0); | |
11454 | }}}m68k_incpc(2); | |
11455 | return 12; | |
11456 | } | |
11457 | unsigned long CPUFUNC(op_4a98_4)(uint32_t opcode) /* TST */ | |
11458 | { | |
11459 | uint32_t srcreg = (opcode & 7); | |
11460 | OpcodeFamily = 20; CurrentInstrCycles = 12; | |
11461 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
11462 | { int32_t src = m68k_read_memory_32(srca); | |
11463 | m68k_areg(regs, srcreg) += 4; | |
11464 | CLEAR_CZNV; | |
11465 | SET_ZFLG (((int32_t)(src)) == 0); | |
11466 | SET_NFLG (((int32_t)(src)) < 0); | |
11467 | }}}m68k_incpc(2); | |
11468 | return 12; | |
11469 | } | |
11470 | unsigned long CPUFUNC(op_4aa0_4)(uint32_t opcode) /* TST */ | |
11471 | { | |
11472 | uint32_t srcreg = (opcode & 7); | |
11473 | OpcodeFamily = 20; CurrentInstrCycles = 14; | |
11474 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 4; | |
11475 | { int32_t src = m68k_read_memory_32(srca); | |
11476 | m68k_areg (regs, srcreg) = srca; | |
11477 | CLEAR_CZNV; | |
11478 | SET_ZFLG (((int32_t)(src)) == 0); | |
11479 | SET_NFLG (((int32_t)(src)) < 0); | |
11480 | }}}m68k_incpc(2); | |
11481 | return 14; | |
11482 | } | |
11483 | unsigned long CPUFUNC(op_4aa8_4)(uint32_t opcode) /* TST */ | |
11484 | { | |
11485 | uint32_t srcreg = (opcode & 7); | |
11486 | OpcodeFamily = 20; CurrentInstrCycles = 16; | |
11487 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
11488 | { int32_t src = m68k_read_memory_32(srca); | |
11489 | CLEAR_CZNV; | |
11490 | SET_ZFLG (((int32_t)(src)) == 0); | |
11491 | SET_NFLG (((int32_t)(src)) < 0); | |
11492 | }}}m68k_incpc(4); | |
11493 | return 16; | |
11494 | } | |
11495 | unsigned long CPUFUNC(op_4ab0_4)(uint32_t opcode) /* TST */ | |
11496 | { | |
11497 | uint32_t srcreg = (opcode & 7); | |
11498 | OpcodeFamily = 20; CurrentInstrCycles = 18; | |
11499 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
11500 | BusCyclePenalty += 2; | |
11501 | { int32_t src = m68k_read_memory_32(srca); | |
11502 | CLEAR_CZNV; | |
11503 | SET_ZFLG (((int32_t)(src)) == 0); | |
11504 | SET_NFLG (((int32_t)(src)) < 0); | |
11505 | }}}m68k_incpc(4); | |
11506 | return 18; | |
11507 | } | |
11508 | unsigned long CPUFUNC(op_4ab8_4)(uint32_t opcode) /* TST */ | |
11509 | { | |
11510 | OpcodeFamily = 20; CurrentInstrCycles = 16; | |
11511 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
11512 | { int32_t src = m68k_read_memory_32(srca); | |
11513 | CLEAR_CZNV; | |
11514 | SET_ZFLG (((int32_t)(src)) == 0); | |
11515 | SET_NFLG (((int32_t)(src)) < 0); | |
11516 | }}}m68k_incpc(4); | |
11517 | return 16; | |
11518 | } | |
11519 | unsigned long CPUFUNC(op_4ab9_4)(uint32_t opcode) /* TST */ | |
11520 | { | |
11521 | OpcodeFamily = 20; CurrentInstrCycles = 20; | |
11522 | {{ uint32_t srca = get_ilong(2); | |
11523 | { int32_t src = m68k_read_memory_32(srca); | |
11524 | CLEAR_CZNV; | |
11525 | SET_ZFLG (((int32_t)(src)) == 0); | |
11526 | SET_NFLG (((int32_t)(src)) < 0); | |
11527 | }}}m68k_incpc(6); | |
11528 | return 20; | |
11529 | } | |
11530 | unsigned long CPUFUNC(op_4aba_4)(uint32_t opcode) /* TST */ | |
11531 | { | |
11532 | OpcodeFamily = 20; CurrentInstrCycles = 16; | |
11533 | {{ uint32_t srca = m68k_getpc () + 2; | |
11534 | srca += (int32_t)(int16_t)get_iword(2); | |
11535 | { int32_t src = m68k_read_memory_32(srca); | |
11536 | CLEAR_CZNV; | |
11537 | SET_ZFLG (((int32_t)(src)) == 0); | |
11538 | SET_NFLG (((int32_t)(src)) < 0); | |
11539 | }}}m68k_incpc(4); | |
11540 | return 16; | |
11541 | } | |
11542 | unsigned long CPUFUNC(op_4abb_4)(uint32_t opcode) /* TST */ | |
11543 | { | |
11544 | OpcodeFamily = 20; CurrentInstrCycles = 18; | |
11545 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
11546 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
11547 | BusCyclePenalty += 2; | |
11548 | { int32_t src = m68k_read_memory_32(srca); | |
11549 | CLEAR_CZNV; | |
11550 | SET_ZFLG (((int32_t)(src)) == 0); | |
11551 | SET_NFLG (((int32_t)(src)) < 0); | |
11552 | }}}m68k_incpc(4); | |
11553 | return 18; | |
11554 | } | |
11555 | unsigned long CPUFUNC(op_4abc_4)(uint32_t opcode) /* TST */ | |
11556 | { | |
11557 | OpcodeFamily = 20; CurrentInstrCycles = 12; | |
11558 | {{ int32_t src = get_ilong(2); | |
11559 | CLEAR_CZNV; | |
11560 | SET_ZFLG (((int32_t)(src)) == 0); | |
11561 | SET_NFLG (((int32_t)(src)) < 0); | |
11562 | }}m68k_incpc(6); | |
11563 | return 12; | |
11564 | } | |
11565 | unsigned long CPUFUNC(op_4ac0_4)(uint32_t opcode) /* TAS */ | |
11566 | { | |
11567 | uint32_t srcreg = (opcode & 7); | |
11568 | OpcodeFamily = 98; CurrentInstrCycles = 4; | |
11569 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
11570 | CLEAR_CZNV; | |
11571 | SET_ZFLG (((int8_t)(src)) == 0); | |
11572 | SET_NFLG (((int8_t)(src)) < 0); | |
11573 | src |= 0x80; | |
11574 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((src) & 0xff); | |
11575 | }}m68k_incpc(2); | |
11576 | return 4; | |
11577 | } | |
11578 | unsigned long CPUFUNC(op_4ad0_4)(uint32_t opcode) /* TAS */ | |
11579 | { | |
11580 | uint32_t srcreg = (opcode & 7); | |
11581 | OpcodeFamily = 98; CurrentInstrCycles = 14; | |
11582 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
11583 | { int8_t src = m68k_read_memory_8(srca); | |
11584 | CLEAR_CZNV; | |
11585 | SET_ZFLG (((int8_t)(src)) == 0); | |
11586 | SET_NFLG (((int8_t)(src)) < 0); | |
11587 | src |= 0x80; | |
11588 | m68k_write_memory_8(srca,src); | |
11589 | }}}m68k_incpc(2); | |
11590 | return 14; | |
11591 | } | |
11592 | unsigned long CPUFUNC(op_4ad8_4)(uint32_t opcode) /* TAS */ | |
11593 | { | |
11594 | uint32_t srcreg = (opcode & 7); | |
11595 | OpcodeFamily = 98; CurrentInstrCycles = 14; | |
11596 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
11597 | { int8_t src = m68k_read_memory_8(srca); | |
11598 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
11599 | CLEAR_CZNV; | |
11600 | SET_ZFLG (((int8_t)(src)) == 0); | |
11601 | SET_NFLG (((int8_t)(src)) < 0); | |
11602 | src |= 0x80; | |
11603 | m68k_write_memory_8(srca,src); | |
11604 | }}}m68k_incpc(2); | |
11605 | return 14; | |
11606 | } | |
11607 | unsigned long CPUFUNC(op_4ae0_4)(uint32_t opcode) /* TAS */ | |
11608 | { | |
11609 | uint32_t srcreg = (opcode & 7); | |
11610 | OpcodeFamily = 98; CurrentInstrCycles = 16; | |
11611 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
11612 | { int8_t src = m68k_read_memory_8(srca); | |
11613 | m68k_areg (regs, srcreg) = srca; | |
11614 | CLEAR_CZNV; | |
11615 | SET_ZFLG (((int8_t)(src)) == 0); | |
11616 | SET_NFLG (((int8_t)(src)) < 0); | |
11617 | src |= 0x80; | |
11618 | m68k_write_memory_8(srca,src); | |
11619 | }}}m68k_incpc(2); | |
11620 | return 16; | |
11621 | } | |
11622 | unsigned long CPUFUNC(op_4ae8_4)(uint32_t opcode) /* TAS */ | |
11623 | { | |
11624 | uint32_t srcreg = (opcode & 7); | |
11625 | OpcodeFamily = 98; CurrentInstrCycles = 18; | |
11626 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
11627 | { int8_t src = m68k_read_memory_8(srca); | |
11628 | CLEAR_CZNV; | |
11629 | SET_ZFLG (((int8_t)(src)) == 0); | |
11630 | SET_NFLG (((int8_t)(src)) < 0); | |
11631 | src |= 0x80; | |
11632 | m68k_write_memory_8(srca,src); | |
11633 | }}}m68k_incpc(4); | |
11634 | return 18; | |
11635 | } | |
11636 | unsigned long CPUFUNC(op_4af0_4)(uint32_t opcode) /* TAS */ | |
11637 | { | |
11638 | uint32_t srcreg = (opcode & 7); | |
11639 | OpcodeFamily = 98; CurrentInstrCycles = 20; | |
11640 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
11641 | BusCyclePenalty += 2; | |
11642 | { int8_t src = m68k_read_memory_8(srca); | |
11643 | CLEAR_CZNV; | |
11644 | SET_ZFLG (((int8_t)(src)) == 0); | |
11645 | SET_NFLG (((int8_t)(src)) < 0); | |
11646 | src |= 0x80; | |
11647 | m68k_write_memory_8(srca,src); | |
11648 | }}}m68k_incpc(4); | |
11649 | return 20; | |
11650 | } | |
11651 | unsigned long CPUFUNC(op_4af8_4)(uint32_t opcode) /* TAS */ | |
11652 | { | |
11653 | OpcodeFamily = 98; CurrentInstrCycles = 18; | |
11654 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
11655 | { int8_t src = m68k_read_memory_8(srca); | |
11656 | CLEAR_CZNV; | |
11657 | SET_ZFLG (((int8_t)(src)) == 0); | |
11658 | SET_NFLG (((int8_t)(src)) < 0); | |
11659 | src |= 0x80; | |
11660 | m68k_write_memory_8(srca,src); | |
11661 | }}}m68k_incpc(4); | |
11662 | return 18; | |
11663 | } | |
11664 | unsigned long CPUFUNC(op_4af9_4)(uint32_t opcode) /* TAS */ | |
11665 | { | |
11666 | OpcodeFamily = 98; CurrentInstrCycles = 22; | |
11667 | {{ uint32_t srca = get_ilong(2); | |
11668 | { int8_t src = m68k_read_memory_8(srca); | |
11669 | CLEAR_CZNV; | |
11670 | SET_ZFLG (((int8_t)(src)) == 0); | |
11671 | SET_NFLG (((int8_t)(src)) < 0); | |
11672 | src |= 0x80; | |
11673 | m68k_write_memory_8(srca,src); | |
11674 | }}}m68k_incpc(6); | |
11675 | return 22; | |
11676 | } | |
11677 | unsigned long CPUFUNC(op_4c90_4)(uint32_t opcode) /* MVMEL */ | |
11678 | { | |
11679 | uint32_t dstreg = opcode & 7; | |
11680 | unsigned int retcycles = 0; | |
11681 | OpcodeFamily = 37; CurrentInstrCycles = 12; | |
11682 | { uint16_t mask = get_iword(2); | |
11683 | unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; | |
11684 | retcycles = 0; | |
11685 | { uint32_t srca = m68k_areg(regs, dstreg); | |
11686 | { while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; } | |
11687 | while (amask) { m68k_areg(regs, movem_index1[amask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; } | |
11688 | }}}m68k_incpc(4); | |
11689 | return (12+retcycles); | |
11690 | } | |
11691 | unsigned long CPUFUNC(op_4c98_4)(uint32_t opcode) /* MVMEL */ | |
11692 | { | |
11693 | uint32_t dstreg = opcode & 7; | |
11694 | unsigned int retcycles = 0; | |
11695 | OpcodeFamily = 37; CurrentInstrCycles = 12; | |
11696 | { uint16_t mask = get_iword(2); | |
11697 | unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; | |
11698 | retcycles = 0; | |
11699 | { uint32_t srca = m68k_areg(regs, dstreg); | |
11700 | { while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; } | |
11701 | while (amask) { m68k_areg(regs, movem_index1[amask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; } | |
11702 | m68k_areg(regs, dstreg) = srca; | |
11703 | }}}m68k_incpc(4); | |
11704 | return (12+retcycles); | |
11705 | } | |
11706 | unsigned long CPUFUNC(op_4ca8_4)(uint32_t opcode) /* MVMEL */ | |
11707 | { | |
11708 | uint32_t dstreg = opcode & 7; | |
11709 | unsigned int retcycles = 0; | |
11710 | OpcodeFamily = 37; CurrentInstrCycles = 16; | |
11711 | { uint16_t mask = get_iword(2); | |
11712 | unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; | |
11713 | retcycles = 0; | |
11714 | { uint32_t srca = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); | |
11715 | { while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; } | |
11716 | while (amask) { m68k_areg(regs, movem_index1[amask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; } | |
11717 | }}}m68k_incpc(6); | |
11718 | return (16+retcycles); | |
11719 | } | |
11720 | unsigned long CPUFUNC(op_4cb0_4)(uint32_t opcode) /* MVMEL */ | |
11721 | { | |
11722 | uint32_t dstreg = opcode & 7; | |
11723 | unsigned int retcycles = 0; | |
11724 | OpcodeFamily = 37; CurrentInstrCycles = 18; | |
11725 | { uint16_t mask = get_iword(2); | |
11726 | unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; | |
11727 | retcycles = 0; | |
11728 | { uint32_t srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); | |
11729 | BusCyclePenalty += 2; | |
11730 | { while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; } | |
11731 | while (amask) { m68k_areg(regs, movem_index1[amask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; } | |
11732 | }}}m68k_incpc(6); | |
11733 | return (18+retcycles); | |
11734 | } | |
11735 | unsigned long CPUFUNC(op_4cb8_4)(uint32_t opcode) /* MVMEL */ | |
11736 | { | |
11737 | unsigned int retcycles = 0; | |
11738 | OpcodeFamily = 37; CurrentInstrCycles = 16; | |
11739 | { uint16_t mask = get_iword(2); | |
11740 | unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; | |
11741 | retcycles = 0; | |
11742 | { uint32_t srca = (int32_t)(int16_t)get_iword(4); | |
11743 | { while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; } | |
11744 | while (amask) { m68k_areg(regs, movem_index1[amask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; } | |
11745 | }}}m68k_incpc(6); | |
11746 | return (16+retcycles); | |
11747 | } | |
11748 | unsigned long CPUFUNC(op_4cb9_4)(uint32_t opcode) /* MVMEL */ | |
11749 | { | |
11750 | unsigned int retcycles = 0; | |
11751 | OpcodeFamily = 37; CurrentInstrCycles = 20; | |
11752 | { uint16_t mask = get_iword(2); | |
11753 | unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; | |
11754 | retcycles = 0; | |
11755 | { uint32_t srca = get_ilong(4); | |
11756 | { while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; } | |
11757 | while (amask) { m68k_areg(regs, movem_index1[amask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; } | |
11758 | }}}m68k_incpc(8); | |
11759 | return (20+retcycles); | |
11760 | } | |
11761 | unsigned long CPUFUNC(op_4cba_4)(uint32_t opcode) /* MVMEL */ | |
11762 | { | |
11763 | uint32_t dstreg = 2; | |
11764 | unsigned int retcycles = 0; | |
11765 | OpcodeFamily = 37; CurrentInstrCycles = 16; | |
11766 | { uint16_t mask = get_iword(2); | |
11767 | unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; | |
11768 | retcycles = 0; | |
11769 | { uint32_t srca = m68k_getpc () + 4; | |
11770 | srca += (int32_t)(int16_t)get_iword(4); | |
11771 | { while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; } | |
11772 | while (amask) { m68k_areg(regs, movem_index1[amask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; } | |
11773 | }}}m68k_incpc(6); | |
11774 | return (16+retcycles); | |
11775 | } | |
11776 | unsigned long CPUFUNC(op_4cbb_4)(uint32_t opcode) /* MVMEL */ | |
11777 | { | |
11778 | uint32_t dstreg = 3; | |
11779 | unsigned int retcycles = 0; | |
11780 | OpcodeFamily = 37; CurrentInstrCycles = 18; | |
11781 | { uint16_t mask = get_iword(2); | |
11782 | unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; | |
11783 | retcycles = 0; | |
11784 | { uint32_t tmppc = m68k_getpc() + 4; | |
11785 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(4)); | |
11786 | BusCyclePenalty += 2; | |
11787 | { while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; } | |
11788 | while (amask) { m68k_areg(regs, movem_index1[amask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; } | |
11789 | }}}m68k_incpc(6); | |
11790 | return (18+retcycles); | |
11791 | } | |
11792 | unsigned long CPUFUNC(op_4cd0_4)(uint32_t opcode) /* MVMEL */ | |
11793 | { | |
11794 | uint32_t dstreg = opcode & 7; | |
11795 | unsigned int retcycles = 0; | |
11796 | OpcodeFamily = 37; CurrentInstrCycles = 12; | |
11797 | { uint16_t mask = get_iword(2); | |
11798 | unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; | |
11799 | retcycles = 0; | |
11800 | { uint32_t srca = m68k_areg(regs, dstreg); | |
11801 | { while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = m68k_read_memory_32(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; } | |
11802 | while (amask) { m68k_areg(regs, movem_index1[amask]) = m68k_read_memory_32(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; } | |
11803 | }}}m68k_incpc(4); | |
11804 | return (12+retcycles); | |
11805 | } | |
11806 | unsigned long CPUFUNC(op_4cd8_4)(uint32_t opcode) /* MVMEL */ | |
11807 | { | |
11808 | uint32_t dstreg = opcode & 7; | |
11809 | unsigned int retcycles = 0; | |
11810 | OpcodeFamily = 37; CurrentInstrCycles = 12; | |
11811 | { uint16_t mask = get_iword(2); | |
11812 | unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; | |
11813 | retcycles = 0; | |
11814 | { uint32_t srca = m68k_areg(regs, dstreg); | |
11815 | { while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = m68k_read_memory_32(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; } | |
11816 | while (amask) { m68k_areg(regs, movem_index1[amask]) = m68k_read_memory_32(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; } | |
11817 | m68k_areg(regs, dstreg) = srca; | |
11818 | }}}m68k_incpc(4); | |
11819 | return (12+retcycles); | |
11820 | } | |
11821 | unsigned long CPUFUNC(op_4ce8_4)(uint32_t opcode) /* MVMEL */ | |
11822 | { | |
11823 | uint32_t dstreg = opcode & 7; | |
11824 | unsigned int retcycles = 0; | |
11825 | OpcodeFamily = 37; CurrentInstrCycles = 16; | |
11826 | { uint16_t mask = get_iword(2); | |
11827 | unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; | |
11828 | retcycles = 0; | |
11829 | { uint32_t srca = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(4); | |
11830 | { while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = m68k_read_memory_32(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; } | |
11831 | while (amask) { m68k_areg(regs, movem_index1[amask]) = m68k_read_memory_32(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; } | |
11832 | }}}m68k_incpc(6); | |
11833 | return (16+retcycles); | |
11834 | } | |
11835 | unsigned long CPUFUNC(op_4cf0_4)(uint32_t opcode) /* MVMEL */ | |
11836 | { | |
11837 | uint32_t dstreg = opcode & 7; | |
11838 | unsigned int retcycles = 0; | |
11839 | OpcodeFamily = 37; CurrentInstrCycles = 18; | |
11840 | { uint16_t mask = get_iword(2); | |
11841 | unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; | |
11842 | retcycles = 0; | |
11843 | { uint32_t srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(4)); | |
11844 | BusCyclePenalty += 2; | |
11845 | { while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = m68k_read_memory_32(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; } | |
11846 | while (amask) { m68k_areg(regs, movem_index1[amask]) = m68k_read_memory_32(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; } | |
11847 | }}}m68k_incpc(6); | |
11848 | return (18+retcycles); | |
11849 | } | |
11850 | unsigned long CPUFUNC(op_4cf8_4)(uint32_t opcode) /* MVMEL */ | |
11851 | { | |
11852 | unsigned int retcycles = 0; | |
11853 | OpcodeFamily = 37; CurrentInstrCycles = 16; | |
11854 | { uint16_t mask = get_iword(2); | |
11855 | unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; | |
11856 | retcycles = 0; | |
11857 | { uint32_t srca = (int32_t)(int16_t)get_iword(4); | |
11858 | { while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = m68k_read_memory_32(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; } | |
11859 | while (amask) { m68k_areg(regs, movem_index1[amask]) = m68k_read_memory_32(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; } | |
11860 | }}}m68k_incpc(6); | |
11861 | return (16+retcycles); | |
11862 | } | |
11863 | unsigned long CPUFUNC(op_4cf9_4)(uint32_t opcode) /* MVMEL */ | |
11864 | { | |
11865 | unsigned int retcycles = 0; | |
11866 | OpcodeFamily = 37; CurrentInstrCycles = 20; | |
11867 | { uint16_t mask = get_iword(2); | |
11868 | unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; | |
11869 | retcycles = 0; | |
11870 | { uint32_t srca = get_ilong(4); | |
11871 | { while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = m68k_read_memory_32(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; } | |
11872 | while (amask) { m68k_areg(regs, movem_index1[amask]) = m68k_read_memory_32(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; } | |
11873 | }}}m68k_incpc(8); | |
11874 | return (20+retcycles); | |
11875 | } | |
11876 | unsigned long CPUFUNC(op_4cfa_4)(uint32_t opcode) /* MVMEL */ | |
11877 | { | |
11878 | uint32_t dstreg = 2; | |
11879 | unsigned int retcycles = 0; | |
11880 | OpcodeFamily = 37; CurrentInstrCycles = 16; | |
11881 | { uint16_t mask = get_iword(2); | |
11882 | unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; | |
11883 | retcycles = 0; | |
11884 | { uint32_t srca = m68k_getpc () + 4; | |
11885 | srca += (int32_t)(int16_t)get_iword(4); | |
11886 | { while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = m68k_read_memory_32(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; } | |
11887 | while (amask) { m68k_areg(regs, movem_index1[amask]) = m68k_read_memory_32(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; } | |
11888 | }}}m68k_incpc(6); | |
11889 | return (16+retcycles); | |
11890 | } | |
11891 | unsigned long CPUFUNC(op_4cfb_4)(uint32_t opcode) /* MVMEL */ | |
11892 | { | |
11893 | uint32_t dstreg = 3; | |
11894 | unsigned int retcycles = 0; | |
11895 | OpcodeFamily = 37; CurrentInstrCycles = 18; | |
11896 | { uint16_t mask = get_iword(2); | |
11897 | unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; | |
11898 | retcycles = 0; | |
11899 | { uint32_t tmppc = m68k_getpc() + 4; | |
11900 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(4)); | |
11901 | BusCyclePenalty += 2; | |
11902 | { while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = m68k_read_memory_32(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; } | |
11903 | while (amask) { m68k_areg(regs, movem_index1[amask]) = m68k_read_memory_32(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; } | |
11904 | }}}m68k_incpc(6); | |
11905 | return (18+retcycles); | |
11906 | } | |
11907 | unsigned long CPUFUNC(op_4e40_4)(uint32_t opcode) /* TRAP */ | |
11908 | { | |
11909 | uint32_t srcreg = (opcode & 15); | |
11910 | OpcodeFamily = 39; CurrentInstrCycles = 4; | |
11911 | {{ uint32_t src = srcreg; | |
11912 | m68k_incpc(2); | |
11913 | Exception(src+32,0,M68000_EXC_SRC_CPU); | |
11914 | }}return 4; | |
11915 | } | |
11916 | unsigned long CPUFUNC(op_4e50_4)(uint32_t opcode) /* LINK */ | |
11917 | { | |
11918 | uint32_t srcreg = (opcode & 7); | |
11919 | OpcodeFamily = 47; CurrentInstrCycles = 18; | |
11920 | {{ uint32_t olda = m68k_areg(regs, 7) - 4; | |
11921 | m68k_areg (regs, 7) = olda; | |
11922 | { int32_t src = m68k_areg(regs, srcreg); | |
11923 | m68k_write_memory_32(olda,src); | |
11924 | m68k_areg(regs, srcreg) = (m68k_areg(regs, 7)); | |
11925 | { int16_t offs = get_iword(2); | |
11926 | m68k_areg(regs, 7) += offs; | |
11927 | }}}}m68k_incpc(4); | |
11928 | return 18; | |
11929 | } | |
11930 | unsigned long CPUFUNC(op_4e58_4)(uint32_t opcode) /* UNLK */ | |
11931 | { | |
11932 | uint32_t srcreg = (opcode & 7); | |
11933 | OpcodeFamily = 48; CurrentInstrCycles = 12; | |
11934 | {{ int32_t src = m68k_areg(regs, srcreg); | |
11935 | m68k_areg(regs, 7) = src; | |
11936 | { uint32_t olda = m68k_areg(regs, 7); | |
11937 | { int32_t old = m68k_read_memory_32(olda); | |
11938 | m68k_areg(regs, 7) += 4; | |
11939 | m68k_areg(regs, srcreg) = (old); | |
11940 | }}}}m68k_incpc(2); | |
11941 | return 12; | |
11942 | } | |
11943 | unsigned long CPUFUNC(op_4e60_4)(uint32_t opcode) /* MVR2USP */ | |
11944 | { | |
11945 | uint32_t srcreg = (opcode & 7); | |
11946 | OpcodeFamily = 40; CurrentInstrCycles = 4; | |
11947 | {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel791; } | |
11948 | {{ int32_t src = m68k_areg(regs, srcreg); | |
11949 | regs.usp = src; | |
11950 | }}}m68k_incpc(2); | |
11951 | endlabel791: ; | |
11952 | return 4; | |
11953 | } | |
11954 | unsigned long CPUFUNC(op_4e68_4)(uint32_t opcode) /* MVUSP2R */ | |
11955 | { | |
11956 | uint32_t srcreg = (opcode & 7); | |
11957 | OpcodeFamily = 41; CurrentInstrCycles = 4; | |
11958 | {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel792; } | |
11959 | {{ m68k_areg(regs, srcreg) = (regs.usp); | |
11960 | }}}m68k_incpc(2); | |
11961 | endlabel792: ; | |
11962 | return 4; | |
11963 | } | |
11964 | unsigned long CPUFUNC(op_4e70_4)(uint32_t opcode) /* RESET */ | |
11965 | { | |
11966 | OpcodeFamily = 42; CurrentInstrCycles = 132; | |
11967 | {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel793; } | |
11968 | {}}m68k_incpc(2); | |
11969 | endlabel793: ; | |
11970 | return 132; | |
11971 | } | |
11972 | unsigned long CPUFUNC(op_4e71_4)(uint32_t opcode) /* NOP */ | |
11973 | { | |
11974 | OpcodeFamily = 43; CurrentInstrCycles = 4; | |
11975 | {}m68k_incpc(2); | |
11976 | return 4; | |
11977 | } | |
11978 | unsigned long CPUFUNC(op_4e72_4)(uint32_t opcode) /* STOP */ | |
11979 | { | |
11980 | OpcodeFamily = 44; CurrentInstrCycles = 4; | |
11981 | {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel795; } | |
11982 | {{ int16_t src = get_iword(2); | |
11983 | regs.sr = src; | |
11984 | MakeFromSR(); | |
11985 | m68k_setstopped(1); | |
11986 | }}}m68k_incpc(4); | |
11987 | endlabel795: ; | |
11988 | return 4; | |
11989 | } | |
11990 | unsigned long CPUFUNC(op_4e73_4)(uint32_t opcode) /* RTE */ | |
11991 | { | |
11992 | OpcodeFamily = 45; CurrentInstrCycles = 20; | |
11993 | {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel796; } | |
11994 | {{ uint32_t sra = m68k_areg(regs, 7); | |
11995 | { int16_t sr = m68k_read_memory_16(sra); | |
11996 | m68k_areg(regs, 7) += 2; | |
11997 | { uint32_t pca = m68k_areg(regs, 7); | |
11998 | { int32_t pc = m68k_read_memory_32(pca); | |
11999 | m68k_areg(regs, 7) += 4; | |
12000 | regs.sr = sr; m68k_setpc_rte(pc); | |
12001 | MakeFromSR(); | |
12002 | }}}}}}endlabel796: ; | |
12003 | return 20; | |
12004 | } | |
12005 | unsigned long CPUFUNC(op_4e74_4)(uint32_t opcode) /* RTD */ | |
12006 | { | |
12007 | OpcodeFamily = 46; CurrentInstrCycles = 16; | |
12008 | {{ uint32_t pca = m68k_areg(regs, 7); | |
12009 | { int32_t pc = m68k_read_memory_32(pca); | |
12010 | m68k_areg(regs, 7) += 4; | |
12011 | { int16_t offs = get_iword(2); | |
12012 | m68k_areg(regs, 7) += offs; | |
12013 | m68k_setpc_rte(pc); | |
12014 | }}}}return 16; | |
12015 | } | |
12016 | unsigned long CPUFUNC(op_4e75_4)(uint32_t opcode) /* RTS */ | |
12017 | { | |
12018 | OpcodeFamily = 49; CurrentInstrCycles = 16; | |
12019 | { m68k_do_rts(); | |
12020 | }return 16; | |
12021 | } | |
12022 | unsigned long CPUFUNC(op_4e76_4)(uint32_t opcode) /* TRAPV */ | |
12023 | { | |
12024 | OpcodeFamily = 50; CurrentInstrCycles = 4; | |
12025 | {m68k_incpc(2); | |
12026 | if (GET_VFLG) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel799; } | |
12027 | }endlabel799: ; | |
12028 | return 4; | |
12029 | } | |
12030 | unsigned long CPUFUNC(op_4e77_4)(uint32_t opcode) /* RTR */ | |
12031 | { | |
12032 | OpcodeFamily = 51; CurrentInstrCycles = 20; | |
12033 | { MakeSR(); | |
12034 | { uint32_t sra = m68k_areg(regs, 7); | |
12035 | { int16_t sr = m68k_read_memory_16(sra); | |
12036 | m68k_areg(regs, 7) += 2; | |
12037 | { uint32_t pca = m68k_areg(regs, 7); | |
12038 | { int32_t pc = m68k_read_memory_32(pca); | |
12039 | m68k_areg(regs, 7) += 4; | |
12040 | regs.sr &= 0xFF00; sr &= 0xFF; | |
12041 | regs.sr |= sr; m68k_setpc(pc); | |
12042 | MakeFromSR(); | |
12043 | }}}}}return 20; | |
12044 | } | |
12045 | unsigned long CPUFUNC(op_4e90_4)(uint32_t opcode) /* JSR */ | |
12046 | { | |
12047 | uint32_t srcreg = (opcode & 7); | |
12048 | OpcodeFamily = 52; CurrentInstrCycles = 16; | |
12049 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
12050 | uint32_t oldpc = m68k_getpc () + 2; | |
12051 | m68k_do_jsr(m68k_getpc() + 2, srca); | |
12052 | }}return 16; | |
12053 | } | |
12054 | unsigned long CPUFUNC(op_4ea8_4)(uint32_t opcode) /* JSR */ | |
12055 | { | |
12056 | uint32_t srcreg = (opcode & 7); | |
12057 | OpcodeFamily = 52; CurrentInstrCycles = 18; | |
12058 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
12059 | uint32_t oldpc = m68k_getpc () + 4; | |
12060 | m68k_do_jsr(m68k_getpc() + 4, srca); | |
12061 | }}return 18; | |
12062 | } | |
12063 | unsigned long CPUFUNC(op_4eb0_4)(uint32_t opcode) /* JSR */ | |
12064 | { | |
12065 | uint32_t srcreg = (opcode & 7); | |
12066 | OpcodeFamily = 52; CurrentInstrCycles = 22; | |
12067 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
12068 | BusCyclePenalty += 2; | |
12069 | uint32_t oldpc = m68k_getpc () + 4; | |
12070 | m68k_do_jsr(m68k_getpc() + 4, srca); | |
12071 | }}return 22; | |
12072 | } | |
12073 | unsigned long CPUFUNC(op_4eb8_4)(uint32_t opcode) /* JSR */ | |
12074 | { | |
12075 | OpcodeFamily = 52; CurrentInstrCycles = 18; | |
12076 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
12077 | uint32_t oldpc = m68k_getpc () + 4; | |
12078 | m68k_do_jsr(m68k_getpc() + 4, srca); | |
12079 | }}return 18; | |
12080 | } | |
12081 | unsigned long CPUFUNC(op_4eb9_4)(uint32_t opcode) /* JSR */ | |
12082 | { | |
12083 | OpcodeFamily = 52; CurrentInstrCycles = 20; | |
12084 | {{ uint32_t srca = get_ilong(2); | |
12085 | uint32_t oldpc = m68k_getpc () + 6; | |
12086 | m68k_do_jsr(m68k_getpc() + 6, srca); | |
12087 | }}return 20; | |
12088 | } | |
12089 | unsigned long CPUFUNC(op_4eba_4)(uint32_t opcode) /* JSR */ | |
12090 | { | |
12091 | OpcodeFamily = 52; CurrentInstrCycles = 18; | |
12092 | {{ uint32_t srca = m68k_getpc () + 2; | |
12093 | srca += (int32_t)(int16_t)get_iword(2); | |
12094 | uint32_t oldpc = m68k_getpc () + 4; | |
12095 | m68k_do_jsr(m68k_getpc() + 4, srca); | |
12096 | }}return 18; | |
12097 | } | |
12098 | unsigned long CPUFUNC(op_4ebb_4)(uint32_t opcode) /* JSR */ | |
12099 | { | |
12100 | OpcodeFamily = 52; CurrentInstrCycles = 22; | |
12101 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
12102 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
12103 | BusCyclePenalty += 2; | |
12104 | uint32_t oldpc = m68k_getpc () + 4; | |
12105 | m68k_do_jsr(m68k_getpc() + 4, srca); | |
12106 | }}return 22; | |
12107 | } | |
12108 | unsigned long CPUFUNC(op_4ed0_4)(uint32_t opcode) /* JMP */ | |
12109 | { | |
12110 | uint32_t srcreg = (opcode & 7); | |
12111 | OpcodeFamily = 53; CurrentInstrCycles = 8; | |
12112 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
12113 | m68k_setpc(srca); | |
12114 | }}return 8; | |
12115 | } | |
12116 | unsigned long CPUFUNC(op_4ee8_4)(uint32_t opcode) /* JMP */ | |
12117 | { | |
12118 | uint32_t srcreg = (opcode & 7); | |
12119 | OpcodeFamily = 53; CurrentInstrCycles = 10; | |
12120 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
12121 | m68k_setpc(srca); | |
12122 | }}return 10; | |
12123 | } | |
12124 | unsigned long CPUFUNC(op_4ef0_4)(uint32_t opcode) /* JMP */ | |
12125 | { | |
12126 | uint32_t srcreg = (opcode & 7); | |
12127 | OpcodeFamily = 53; CurrentInstrCycles = 14; | |
12128 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
12129 | BusCyclePenalty += 2; | |
12130 | m68k_setpc(srca); | |
12131 | }}return 14; | |
12132 | } | |
12133 | unsigned long CPUFUNC(op_4ef8_4)(uint32_t opcode) /* JMP */ | |
12134 | { | |
12135 | OpcodeFamily = 53; CurrentInstrCycles = 10; | |
12136 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
12137 | m68k_setpc(srca); | |
12138 | }}return 10; | |
12139 | } | |
12140 | unsigned long CPUFUNC(op_4ef9_4)(uint32_t opcode) /* JMP */ | |
12141 | { | |
12142 | OpcodeFamily = 53; CurrentInstrCycles = 12; | |
12143 | {{ uint32_t srca = get_ilong(2); | |
12144 | m68k_setpc(srca); | |
12145 | }}return 12; | |
12146 | } | |
12147 | unsigned long CPUFUNC(op_4efa_4)(uint32_t opcode) /* JMP */ | |
12148 | { | |
12149 | OpcodeFamily = 53; CurrentInstrCycles = 10; | |
12150 | {{ uint32_t srca = m68k_getpc () + 2; | |
12151 | srca += (int32_t)(int16_t)get_iword(2); | |
12152 | m68k_setpc(srca); | |
12153 | }}return 10; | |
12154 | } | |
12155 | unsigned long CPUFUNC(op_4efb_4)(uint32_t opcode) /* JMP */ | |
12156 | { | |
12157 | OpcodeFamily = 53; CurrentInstrCycles = 14; | |
12158 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
12159 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
12160 | BusCyclePenalty += 2; | |
12161 | m68k_setpc(srca); | |
12162 | }}return 14; | |
12163 | } | |
12164 | unsigned long CPUFUNC(op_5000_4)(uint32_t opcode) /* ADD */ | |
12165 | { | |
12166 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
12167 | uint32_t dstreg = opcode & 7; | |
12168 | OpcodeFamily = 11; CurrentInstrCycles = 4; | |
12169 | {{ uint32_t src = srcreg; | |
12170 | { int8_t dst = m68k_dreg(regs, dstreg); | |
12171 | { refill_prefetch (m68k_getpc(), 2); | |
12172 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
12173 | { int flgs = ((int8_t)(src)) < 0; | |
12174 | int flgo = ((int8_t)(dst)) < 0; | |
12175 | int flgn = ((int8_t)(newv)) < 0; | |
12176 | SET_ZFLG (((int8_t)(newv)) == 0); | |
12177 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
12178 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
12179 | COPY_CARRY; | |
12180 | SET_NFLG (flgn != 0); | |
12181 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
12182 | }}}}}}m68k_incpc(2); | |
12183 | return 4; | |
12184 | } | |
12185 | unsigned long CPUFUNC(op_5010_4)(uint32_t opcode) /* ADD */ | |
12186 | { | |
12187 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
12188 | uint32_t dstreg = opcode & 7; | |
12189 | OpcodeFamily = 11; CurrentInstrCycles = 12; | |
12190 | {{ uint32_t src = srcreg; | |
12191 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
12192 | { int8_t dst = m68k_read_memory_8(dsta); | |
12193 | { refill_prefetch (m68k_getpc(), 2); | |
12194 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
12195 | { int flgs = ((int8_t)(src)) < 0; | |
12196 | int flgo = ((int8_t)(dst)) < 0; | |
12197 | int flgn = ((int8_t)(newv)) < 0; | |
12198 | SET_ZFLG (((int8_t)(newv)) == 0); | |
12199 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
12200 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
12201 | COPY_CARRY; | |
12202 | SET_NFLG (flgn != 0); | |
12203 | m68k_write_memory_8(dsta,newv); | |
12204 | }}}}}}}m68k_incpc(2); | |
12205 | return 12; | |
12206 | } | |
12207 | unsigned long CPUFUNC(op_5018_4)(uint32_t opcode) /* ADD */ | |
12208 | { | |
12209 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
12210 | uint32_t dstreg = opcode & 7; | |
12211 | OpcodeFamily = 11; CurrentInstrCycles = 12; | |
12212 | {{ uint32_t src = srcreg; | |
12213 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
12214 | { int8_t dst = m68k_read_memory_8(dsta); | |
12215 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
12216 | { refill_prefetch (m68k_getpc(), 2); | |
12217 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
12218 | { int flgs = ((int8_t)(src)) < 0; | |
12219 | int flgo = ((int8_t)(dst)) < 0; | |
12220 | int flgn = ((int8_t)(newv)) < 0; | |
12221 | SET_ZFLG (((int8_t)(newv)) == 0); | |
12222 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
12223 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
12224 | COPY_CARRY; | |
12225 | SET_NFLG (flgn != 0); | |
12226 | m68k_write_memory_8(dsta,newv); | |
12227 | }}}}}}}m68k_incpc(2); | |
12228 | return 12; | |
12229 | } | |
12230 | #endif | |
12231 | ||
12232 | #ifdef PART_5 | |
12233 | unsigned long CPUFUNC(op_5020_4)(uint32_t opcode) /* ADD */ | |
12234 | { | |
12235 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
12236 | uint32_t dstreg = opcode & 7; | |
12237 | OpcodeFamily = 11; CurrentInstrCycles = 14; | |
12238 | {{ uint32_t src = srcreg; | |
12239 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
12240 | { int8_t dst = m68k_read_memory_8(dsta); | |
12241 | m68k_areg (regs, dstreg) = dsta; | |
12242 | { refill_prefetch (m68k_getpc(), 2); | |
12243 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
12244 | { int flgs = ((int8_t)(src)) < 0; | |
12245 | int flgo = ((int8_t)(dst)) < 0; | |
12246 | int flgn = ((int8_t)(newv)) < 0; | |
12247 | SET_ZFLG (((int8_t)(newv)) == 0); | |
12248 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
12249 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
12250 | COPY_CARRY; | |
12251 | SET_NFLG (flgn != 0); | |
12252 | m68k_write_memory_8(dsta,newv); | |
12253 | }}}}}}}m68k_incpc(2); | |
12254 | return 14; | |
12255 | } | |
12256 | unsigned long CPUFUNC(op_5028_4)(uint32_t opcode) /* ADD */ | |
12257 | { | |
12258 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
12259 | uint32_t dstreg = opcode & 7; | |
12260 | OpcodeFamily = 11; CurrentInstrCycles = 16; | |
12261 | {{ uint32_t src = srcreg; | |
12262 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); | |
12263 | { int8_t dst = m68k_read_memory_8(dsta); | |
12264 | { refill_prefetch (m68k_getpc(), 2); | |
12265 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
12266 | { int flgs = ((int8_t)(src)) < 0; | |
12267 | int flgo = ((int8_t)(dst)) < 0; | |
12268 | int flgn = ((int8_t)(newv)) < 0; | |
12269 | SET_ZFLG (((int8_t)(newv)) == 0); | |
12270 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
12271 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
12272 | COPY_CARRY; | |
12273 | SET_NFLG (flgn != 0); | |
12274 | m68k_write_memory_8(dsta,newv); | |
12275 | }}}}}}}m68k_incpc(4); | |
12276 | return 16; | |
12277 | } | |
12278 | unsigned long CPUFUNC(op_5030_4)(uint32_t opcode) /* ADD */ | |
12279 | { | |
12280 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
12281 | uint32_t dstreg = opcode & 7; | |
12282 | OpcodeFamily = 11; CurrentInstrCycles = 18; | |
12283 | {{ uint32_t src = srcreg; | |
12284 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); | |
12285 | BusCyclePenalty += 2; | |
12286 | { int8_t dst = m68k_read_memory_8(dsta); | |
12287 | { refill_prefetch (m68k_getpc(), 2); | |
12288 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
12289 | { int flgs = ((int8_t)(src)) < 0; | |
12290 | int flgo = ((int8_t)(dst)) < 0; | |
12291 | int flgn = ((int8_t)(newv)) < 0; | |
12292 | SET_ZFLG (((int8_t)(newv)) == 0); | |
12293 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
12294 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
12295 | COPY_CARRY; | |
12296 | SET_NFLG (flgn != 0); | |
12297 | m68k_write_memory_8(dsta,newv); | |
12298 | }}}}}}}m68k_incpc(4); | |
12299 | return 18; | |
12300 | } | |
12301 | unsigned long CPUFUNC(op_5038_4)(uint32_t opcode) /* ADD */ | |
12302 | { | |
12303 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
12304 | OpcodeFamily = 11; CurrentInstrCycles = 16; | |
12305 | {{ uint32_t src = srcreg; | |
12306 | { uint32_t dsta = (int32_t)(int16_t)get_iword(2); | |
12307 | { int8_t dst = m68k_read_memory_8(dsta); | |
12308 | { refill_prefetch (m68k_getpc(), 2); | |
12309 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
12310 | { int flgs = ((int8_t)(src)) < 0; | |
12311 | int flgo = ((int8_t)(dst)) < 0; | |
12312 | int flgn = ((int8_t)(newv)) < 0; | |
12313 | SET_ZFLG (((int8_t)(newv)) == 0); | |
12314 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
12315 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
12316 | COPY_CARRY; | |
12317 | SET_NFLG (flgn != 0); | |
12318 | m68k_write_memory_8(dsta,newv); | |
12319 | }}}}}}}m68k_incpc(4); | |
12320 | return 16; | |
12321 | } | |
12322 | unsigned long CPUFUNC(op_5039_4)(uint32_t opcode) /* ADD */ | |
12323 | { | |
12324 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
12325 | OpcodeFamily = 11; CurrentInstrCycles = 20; | |
12326 | {{ uint32_t src = srcreg; | |
12327 | { uint32_t dsta = get_ilong(2); | |
12328 | { int8_t dst = m68k_read_memory_8(dsta); | |
12329 | { refill_prefetch (m68k_getpc(), 2); | |
12330 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
12331 | { int flgs = ((int8_t)(src)) < 0; | |
12332 | int flgo = ((int8_t)(dst)) < 0; | |
12333 | int flgn = ((int8_t)(newv)) < 0; | |
12334 | SET_ZFLG (((int8_t)(newv)) == 0); | |
12335 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
12336 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
12337 | COPY_CARRY; | |
12338 | SET_NFLG (flgn != 0); | |
12339 | m68k_write_memory_8(dsta,newv); | |
12340 | }}}}}}}m68k_incpc(6); | |
12341 | return 20; | |
12342 | } | |
12343 | unsigned long CPUFUNC(op_5040_4)(uint32_t opcode) /* ADD */ | |
12344 | { | |
12345 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
12346 | uint32_t dstreg = opcode & 7; | |
12347 | OpcodeFamily = 11; CurrentInstrCycles = 4; | |
12348 | {{ uint32_t src = srcreg; | |
12349 | { int16_t dst = m68k_dreg(regs, dstreg); | |
12350 | { refill_prefetch (m68k_getpc(), 2); | |
12351 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
12352 | { int flgs = ((int16_t)(src)) < 0; | |
12353 | int flgo = ((int16_t)(dst)) < 0; | |
12354 | int flgn = ((int16_t)(newv)) < 0; | |
12355 | SET_ZFLG (((int16_t)(newv)) == 0); | |
12356 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
12357 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
12358 | COPY_CARRY; | |
12359 | SET_NFLG (flgn != 0); | |
12360 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
12361 | }}}}}}m68k_incpc(2); | |
12362 | return 4; | |
12363 | } | |
12364 | unsigned long CPUFUNC(op_5048_4)(uint32_t opcode) /* ADDA */ | |
12365 | { | |
12366 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
12367 | uint32_t dstreg = opcode & 7; | |
12368 | OpcodeFamily = 12; CurrentInstrCycles = 8; | |
12369 | {{ uint32_t src = srcreg; | |
12370 | { int32_t dst = m68k_areg(regs, dstreg); | |
12371 | { uint32_t newv = dst + src; | |
12372 | m68k_areg(regs, dstreg) = (newv); | |
12373 | }}}}m68k_incpc(2); | |
12374 | return 8; | |
12375 | } | |
12376 | unsigned long CPUFUNC(op_5050_4)(uint32_t opcode) /* ADD */ | |
12377 | { | |
12378 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
12379 | uint32_t dstreg = opcode & 7; | |
12380 | OpcodeFamily = 11; CurrentInstrCycles = 12; | |
12381 | {{ uint32_t src = srcreg; | |
12382 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
12383 | { int16_t dst = m68k_read_memory_16(dsta); | |
12384 | { refill_prefetch (m68k_getpc(), 2); | |
12385 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
12386 | { int flgs = ((int16_t)(src)) < 0; | |
12387 | int flgo = ((int16_t)(dst)) < 0; | |
12388 | int flgn = ((int16_t)(newv)) < 0; | |
12389 | SET_ZFLG (((int16_t)(newv)) == 0); | |
12390 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
12391 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
12392 | COPY_CARRY; | |
12393 | SET_NFLG (flgn != 0); | |
12394 | m68k_write_memory_16(dsta,newv); | |
12395 | }}}}}}}m68k_incpc(2); | |
12396 | return 12; | |
12397 | } | |
12398 | unsigned long CPUFUNC(op_5058_4)(uint32_t opcode) /* ADD */ | |
12399 | { | |
12400 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
12401 | uint32_t dstreg = opcode & 7; | |
12402 | OpcodeFamily = 11; CurrentInstrCycles = 12; | |
12403 | {{ uint32_t src = srcreg; | |
12404 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
12405 | { int16_t dst = m68k_read_memory_16(dsta); | |
12406 | m68k_areg(regs, dstreg) += 2; | |
12407 | { refill_prefetch (m68k_getpc(), 2); | |
12408 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
12409 | { int flgs = ((int16_t)(src)) < 0; | |
12410 | int flgo = ((int16_t)(dst)) < 0; | |
12411 | int flgn = ((int16_t)(newv)) < 0; | |
12412 | SET_ZFLG (((int16_t)(newv)) == 0); | |
12413 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
12414 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
12415 | COPY_CARRY; | |
12416 | SET_NFLG (flgn != 0); | |
12417 | m68k_write_memory_16(dsta,newv); | |
12418 | }}}}}}}m68k_incpc(2); | |
12419 | return 12; | |
12420 | } | |
12421 | unsigned long CPUFUNC(op_5060_4)(uint32_t opcode) /* ADD */ | |
12422 | { | |
12423 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
12424 | uint32_t dstreg = opcode & 7; | |
12425 | OpcodeFamily = 11; CurrentInstrCycles = 14; | |
12426 | {{ uint32_t src = srcreg; | |
12427 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
12428 | { int16_t dst = m68k_read_memory_16(dsta); | |
12429 | m68k_areg (regs, dstreg) = dsta; | |
12430 | { refill_prefetch (m68k_getpc(), 2); | |
12431 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
12432 | { int flgs = ((int16_t)(src)) < 0; | |
12433 | int flgo = ((int16_t)(dst)) < 0; | |
12434 | int flgn = ((int16_t)(newv)) < 0; | |
12435 | SET_ZFLG (((int16_t)(newv)) == 0); | |
12436 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
12437 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
12438 | COPY_CARRY; | |
12439 | SET_NFLG (flgn != 0); | |
12440 | m68k_write_memory_16(dsta,newv); | |
12441 | }}}}}}}m68k_incpc(2); | |
12442 | return 14; | |
12443 | } | |
12444 | unsigned long CPUFUNC(op_5068_4)(uint32_t opcode) /* ADD */ | |
12445 | { | |
12446 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
12447 | uint32_t dstreg = opcode & 7; | |
12448 | OpcodeFamily = 11; CurrentInstrCycles = 16; | |
12449 | {{ uint32_t src = srcreg; | |
12450 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); | |
12451 | { int16_t dst = m68k_read_memory_16(dsta); | |
12452 | { refill_prefetch (m68k_getpc(), 2); | |
12453 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
12454 | { int flgs = ((int16_t)(src)) < 0; | |
12455 | int flgo = ((int16_t)(dst)) < 0; | |
12456 | int flgn = ((int16_t)(newv)) < 0; | |
12457 | SET_ZFLG (((int16_t)(newv)) == 0); | |
12458 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
12459 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
12460 | COPY_CARRY; | |
12461 | SET_NFLG (flgn != 0); | |
12462 | m68k_write_memory_16(dsta,newv); | |
12463 | }}}}}}}m68k_incpc(4); | |
12464 | return 16; | |
12465 | } | |
12466 | unsigned long CPUFUNC(op_5070_4)(uint32_t opcode) /* ADD */ | |
12467 | { | |
12468 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
12469 | uint32_t dstreg = opcode & 7; | |
12470 | OpcodeFamily = 11; CurrentInstrCycles = 18; | |
12471 | {{ uint32_t src = srcreg; | |
12472 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); | |
12473 | BusCyclePenalty += 2; | |
12474 | { int16_t dst = m68k_read_memory_16(dsta); | |
12475 | { refill_prefetch (m68k_getpc(), 2); | |
12476 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
12477 | { int flgs = ((int16_t)(src)) < 0; | |
12478 | int flgo = ((int16_t)(dst)) < 0; | |
12479 | int flgn = ((int16_t)(newv)) < 0; | |
12480 | SET_ZFLG (((int16_t)(newv)) == 0); | |
12481 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
12482 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
12483 | COPY_CARRY; | |
12484 | SET_NFLG (flgn != 0); | |
12485 | m68k_write_memory_16(dsta,newv); | |
12486 | }}}}}}}m68k_incpc(4); | |
12487 | return 18; | |
12488 | } | |
12489 | unsigned long CPUFUNC(op_5078_4)(uint32_t opcode) /* ADD */ | |
12490 | { | |
12491 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
12492 | OpcodeFamily = 11; CurrentInstrCycles = 16; | |
12493 | {{ uint32_t src = srcreg; | |
12494 | { uint32_t dsta = (int32_t)(int16_t)get_iword(2); | |
12495 | { int16_t dst = m68k_read_memory_16(dsta); | |
12496 | { refill_prefetch (m68k_getpc(), 2); | |
12497 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
12498 | { int flgs = ((int16_t)(src)) < 0; | |
12499 | int flgo = ((int16_t)(dst)) < 0; | |
12500 | int flgn = ((int16_t)(newv)) < 0; | |
12501 | SET_ZFLG (((int16_t)(newv)) == 0); | |
12502 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
12503 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
12504 | COPY_CARRY; | |
12505 | SET_NFLG (flgn != 0); | |
12506 | m68k_write_memory_16(dsta,newv); | |
12507 | }}}}}}}m68k_incpc(4); | |
12508 | return 16; | |
12509 | } | |
12510 | unsigned long CPUFUNC(op_5079_4)(uint32_t opcode) /* ADD */ | |
12511 | { | |
12512 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
12513 | OpcodeFamily = 11; CurrentInstrCycles = 20; | |
12514 | {{ uint32_t src = srcreg; | |
12515 | { uint32_t dsta = get_ilong(2); | |
12516 | { int16_t dst = m68k_read_memory_16(dsta); | |
12517 | { refill_prefetch (m68k_getpc(), 2); | |
12518 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
12519 | { int flgs = ((int16_t)(src)) < 0; | |
12520 | int flgo = ((int16_t)(dst)) < 0; | |
12521 | int flgn = ((int16_t)(newv)) < 0; | |
12522 | SET_ZFLG (((int16_t)(newv)) == 0); | |
12523 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
12524 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
12525 | COPY_CARRY; | |
12526 | SET_NFLG (flgn != 0); | |
12527 | m68k_write_memory_16(dsta,newv); | |
12528 | }}}}}}}m68k_incpc(6); | |
12529 | return 20; | |
12530 | } | |
12531 | unsigned long CPUFUNC(op_5080_4)(uint32_t opcode) /* ADD */ | |
12532 | { | |
12533 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
12534 | uint32_t dstreg = opcode & 7; | |
12535 | OpcodeFamily = 11; CurrentInstrCycles = 8; | |
12536 | {{ uint32_t src = srcreg; | |
12537 | { int32_t dst = m68k_dreg(regs, dstreg); | |
12538 | { refill_prefetch (m68k_getpc(), 2); | |
12539 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
12540 | { int flgs = ((int32_t)(src)) < 0; | |
12541 | int flgo = ((int32_t)(dst)) < 0; | |
12542 | int flgn = ((int32_t)(newv)) < 0; | |
12543 | SET_ZFLG (((int32_t)(newv)) == 0); | |
12544 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
12545 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
12546 | COPY_CARRY; | |
12547 | SET_NFLG (flgn != 0); | |
12548 | m68k_dreg(regs, dstreg) = (newv); | |
12549 | }}}}}}m68k_incpc(2); | |
12550 | return 8; | |
12551 | } | |
12552 | unsigned long CPUFUNC(op_5088_4)(uint32_t opcode) /* ADDA */ | |
12553 | { | |
12554 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
12555 | uint32_t dstreg = opcode & 7; | |
12556 | OpcodeFamily = 12; CurrentInstrCycles = 8; | |
12557 | {{ uint32_t src = srcreg; | |
12558 | { int32_t dst = m68k_areg(regs, dstreg); | |
12559 | { uint32_t newv = dst + src; | |
12560 | m68k_areg(regs, dstreg) = (newv); | |
12561 | }}}}m68k_incpc(2); | |
12562 | return 8; | |
12563 | } | |
12564 | unsigned long CPUFUNC(op_5090_4)(uint32_t opcode) /* ADD */ | |
12565 | { | |
12566 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
12567 | uint32_t dstreg = opcode & 7; | |
12568 | OpcodeFamily = 11; CurrentInstrCycles = 20; | |
12569 | {{ uint32_t src = srcreg; | |
12570 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
12571 | { int32_t dst = m68k_read_memory_32(dsta); | |
12572 | { refill_prefetch (m68k_getpc(), 2); | |
12573 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
12574 | { int flgs = ((int32_t)(src)) < 0; | |
12575 | int flgo = ((int32_t)(dst)) < 0; | |
12576 | int flgn = ((int32_t)(newv)) < 0; | |
12577 | SET_ZFLG (((int32_t)(newv)) == 0); | |
12578 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
12579 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
12580 | COPY_CARRY; | |
12581 | SET_NFLG (flgn != 0); | |
12582 | m68k_write_memory_32(dsta,newv); | |
12583 | }}}}}}}m68k_incpc(2); | |
12584 | return 20; | |
12585 | } | |
12586 | unsigned long CPUFUNC(op_5098_4)(uint32_t opcode) /* ADD */ | |
12587 | { | |
12588 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
12589 | uint32_t dstreg = opcode & 7; | |
12590 | OpcodeFamily = 11; CurrentInstrCycles = 20; | |
12591 | {{ uint32_t src = srcreg; | |
12592 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
12593 | { int32_t dst = m68k_read_memory_32(dsta); | |
12594 | m68k_areg(regs, dstreg) += 4; | |
12595 | { refill_prefetch (m68k_getpc(), 2); | |
12596 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
12597 | { int flgs = ((int32_t)(src)) < 0; | |
12598 | int flgo = ((int32_t)(dst)) < 0; | |
12599 | int flgn = ((int32_t)(newv)) < 0; | |
12600 | SET_ZFLG (((int32_t)(newv)) == 0); | |
12601 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
12602 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
12603 | COPY_CARRY; | |
12604 | SET_NFLG (flgn != 0); | |
12605 | m68k_write_memory_32(dsta,newv); | |
12606 | }}}}}}}m68k_incpc(2); | |
12607 | return 20; | |
12608 | } | |
12609 | unsigned long CPUFUNC(op_50a0_4)(uint32_t opcode) /* ADD */ | |
12610 | { | |
12611 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
12612 | uint32_t dstreg = opcode & 7; | |
12613 | OpcodeFamily = 11; CurrentInstrCycles = 22; | |
12614 | {{ uint32_t src = srcreg; | |
12615 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
12616 | { int32_t dst = m68k_read_memory_32(dsta); | |
12617 | m68k_areg (regs, dstreg) = dsta; | |
12618 | { refill_prefetch (m68k_getpc(), 2); | |
12619 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
12620 | { int flgs = ((int32_t)(src)) < 0; | |
12621 | int flgo = ((int32_t)(dst)) < 0; | |
12622 | int flgn = ((int32_t)(newv)) < 0; | |
12623 | SET_ZFLG (((int32_t)(newv)) == 0); | |
12624 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
12625 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
12626 | COPY_CARRY; | |
12627 | SET_NFLG (flgn != 0); | |
12628 | m68k_write_memory_32(dsta,newv); | |
12629 | }}}}}}}m68k_incpc(2); | |
12630 | return 22; | |
12631 | } | |
12632 | unsigned long CPUFUNC(op_50a8_4)(uint32_t opcode) /* ADD */ | |
12633 | { | |
12634 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
12635 | uint32_t dstreg = opcode & 7; | |
12636 | OpcodeFamily = 11; CurrentInstrCycles = 24; | |
12637 | {{ uint32_t src = srcreg; | |
12638 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); | |
12639 | { int32_t dst = m68k_read_memory_32(dsta); | |
12640 | { refill_prefetch (m68k_getpc(), 2); | |
12641 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
12642 | { int flgs = ((int32_t)(src)) < 0; | |
12643 | int flgo = ((int32_t)(dst)) < 0; | |
12644 | int flgn = ((int32_t)(newv)) < 0; | |
12645 | SET_ZFLG (((int32_t)(newv)) == 0); | |
12646 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
12647 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
12648 | COPY_CARRY; | |
12649 | SET_NFLG (flgn != 0); | |
12650 | m68k_write_memory_32(dsta,newv); | |
12651 | }}}}}}}m68k_incpc(4); | |
12652 | return 24; | |
12653 | } | |
12654 | unsigned long CPUFUNC(op_50b0_4)(uint32_t opcode) /* ADD */ | |
12655 | { | |
12656 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
12657 | uint32_t dstreg = opcode & 7; | |
12658 | OpcodeFamily = 11; CurrentInstrCycles = 26; | |
12659 | {{ uint32_t src = srcreg; | |
12660 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); | |
12661 | BusCyclePenalty += 2; | |
12662 | { int32_t dst = m68k_read_memory_32(dsta); | |
12663 | { refill_prefetch (m68k_getpc(), 2); | |
12664 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
12665 | { int flgs = ((int32_t)(src)) < 0; | |
12666 | int flgo = ((int32_t)(dst)) < 0; | |
12667 | int flgn = ((int32_t)(newv)) < 0; | |
12668 | SET_ZFLG (((int32_t)(newv)) == 0); | |
12669 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
12670 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
12671 | COPY_CARRY; | |
12672 | SET_NFLG (flgn != 0); | |
12673 | m68k_write_memory_32(dsta,newv); | |
12674 | }}}}}}}m68k_incpc(4); | |
12675 | return 26; | |
12676 | } | |
12677 | unsigned long CPUFUNC(op_50b8_4)(uint32_t opcode) /* ADD */ | |
12678 | { | |
12679 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
12680 | OpcodeFamily = 11; CurrentInstrCycles = 24; | |
12681 | {{ uint32_t src = srcreg; | |
12682 | { uint32_t dsta = (int32_t)(int16_t)get_iword(2); | |
12683 | { int32_t dst = m68k_read_memory_32(dsta); | |
12684 | { refill_prefetch (m68k_getpc(), 2); | |
12685 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
12686 | { int flgs = ((int32_t)(src)) < 0; | |
12687 | int flgo = ((int32_t)(dst)) < 0; | |
12688 | int flgn = ((int32_t)(newv)) < 0; | |
12689 | SET_ZFLG (((int32_t)(newv)) == 0); | |
12690 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
12691 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
12692 | COPY_CARRY; | |
12693 | SET_NFLG (flgn != 0); | |
12694 | m68k_write_memory_32(dsta,newv); | |
12695 | }}}}}}}m68k_incpc(4); | |
12696 | return 24; | |
12697 | } | |
12698 | unsigned long CPUFUNC(op_50b9_4)(uint32_t opcode) /* ADD */ | |
12699 | { | |
12700 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
12701 | OpcodeFamily = 11; CurrentInstrCycles = 28; | |
12702 | {{ uint32_t src = srcreg; | |
12703 | { uint32_t dsta = get_ilong(2); | |
12704 | { int32_t dst = m68k_read_memory_32(dsta); | |
12705 | { refill_prefetch (m68k_getpc(), 2); | |
12706 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
12707 | { int flgs = ((int32_t)(src)) < 0; | |
12708 | int flgo = ((int32_t)(dst)) < 0; | |
12709 | int flgn = ((int32_t)(newv)) < 0; | |
12710 | SET_ZFLG (((int32_t)(newv)) == 0); | |
12711 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
12712 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
12713 | COPY_CARRY; | |
12714 | SET_NFLG (flgn != 0); | |
12715 | m68k_write_memory_32(dsta,newv); | |
12716 | }}}}}}}m68k_incpc(6); | |
12717 | return 28; | |
12718 | } | |
12719 | unsigned long CPUFUNC(op_50c0_4)(uint32_t opcode) /* Scc */ | |
12720 | { | |
12721 | uint32_t srcreg = (opcode & 7); | |
12722 | OpcodeFamily = 59; CurrentInstrCycles = 4; | |
12723 | {{{ int val = cctrue(0) ? 0xff : 0; | |
12724 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); | |
12725 | if (val) { m68k_incpc(2) ; return 4+2; } | |
12726 | }}}m68k_incpc(2); | |
12727 | return 4; | |
12728 | } | |
12729 | unsigned long CPUFUNC(op_50c8_4)(uint32_t opcode) /* DBcc */ | |
12730 | { | |
12731 | uint32_t srcreg = (opcode & 7); | |
12732 | OpcodeFamily = 58; CurrentInstrCycles = 12; | |
12733 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
12734 | { int16_t offs = get_iword(2); | |
12735 | if (!cctrue(0)) { | |
12736 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); | |
12737 | if (src) { | |
12738 | m68k_incpc((int32_t)offs + 2); | |
12739 | return 10; | |
12740 | } else { | |
12741 | m68k_incpc(4); | |
12742 | return 14; | |
12743 | } | |
12744 | } | |
12745 | }}}m68k_incpc(4); | |
12746 | endlabel842: ; | |
12747 | return 12; | |
12748 | } | |
12749 | unsigned long CPUFUNC(op_50d0_4)(uint32_t opcode) /* Scc */ | |
12750 | { | |
12751 | uint32_t srcreg = (opcode & 7); | |
12752 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
12753 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
12754 | { int val = cctrue(0) ? 0xff : 0; | |
12755 | m68k_write_memory_8(srca,val); | |
12756 | }}}m68k_incpc(2); | |
12757 | return 12; | |
12758 | } | |
12759 | unsigned long CPUFUNC(op_50d8_4)(uint32_t opcode) /* Scc */ | |
12760 | { | |
12761 | uint32_t srcreg = (opcode & 7); | |
12762 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
12763 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
12764 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
12765 | { int val = cctrue(0) ? 0xff : 0; | |
12766 | m68k_write_memory_8(srca,val); | |
12767 | }}}m68k_incpc(2); | |
12768 | return 12; | |
12769 | } | |
12770 | unsigned long CPUFUNC(op_50e0_4)(uint32_t opcode) /* Scc */ | |
12771 | { | |
12772 | uint32_t srcreg = (opcode & 7); | |
12773 | OpcodeFamily = 59; CurrentInstrCycles = 14; | |
12774 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
12775 | m68k_areg (regs, srcreg) = srca; | |
12776 | { int val = cctrue(0) ? 0xff : 0; | |
12777 | m68k_write_memory_8(srca,val); | |
12778 | }}}m68k_incpc(2); | |
12779 | return 14; | |
12780 | } | |
12781 | unsigned long CPUFUNC(op_50e8_4)(uint32_t opcode) /* Scc */ | |
12782 | { | |
12783 | uint32_t srcreg = (opcode & 7); | |
12784 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
12785 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
12786 | { int val = cctrue(0) ? 0xff : 0; | |
12787 | m68k_write_memory_8(srca,val); | |
12788 | }}}m68k_incpc(4); | |
12789 | return 16; | |
12790 | } | |
12791 | unsigned long CPUFUNC(op_50f0_4)(uint32_t opcode) /* Scc */ | |
12792 | { | |
12793 | uint32_t srcreg = (opcode & 7); | |
12794 | OpcodeFamily = 59; CurrentInstrCycles = 18; | |
12795 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
12796 | BusCyclePenalty += 2; | |
12797 | { int val = cctrue(0) ? 0xff : 0; | |
12798 | m68k_write_memory_8(srca,val); | |
12799 | }}}m68k_incpc(4); | |
12800 | return 18; | |
12801 | } | |
12802 | unsigned long CPUFUNC(op_50f8_4)(uint32_t opcode) /* Scc */ | |
12803 | { | |
12804 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
12805 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
12806 | { int val = cctrue(0) ? 0xff : 0; | |
12807 | m68k_write_memory_8(srca,val); | |
12808 | }}}m68k_incpc(4); | |
12809 | return 16; | |
12810 | } | |
12811 | unsigned long CPUFUNC(op_50f9_4)(uint32_t opcode) /* Scc */ | |
12812 | { | |
12813 | OpcodeFamily = 59; CurrentInstrCycles = 20; | |
12814 | {{ uint32_t srca = get_ilong(2); | |
12815 | { int val = cctrue(0) ? 0xff : 0; | |
12816 | m68k_write_memory_8(srca,val); | |
12817 | }}}m68k_incpc(6); | |
12818 | return 20; | |
12819 | } | |
12820 | unsigned long CPUFUNC(op_5100_4)(uint32_t opcode) /* SUB */ | |
12821 | { | |
12822 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
12823 | uint32_t dstreg = opcode & 7; | |
12824 | OpcodeFamily = 7; CurrentInstrCycles = 4; | |
12825 | {{ uint32_t src = srcreg; | |
12826 | { int8_t dst = m68k_dreg(regs, dstreg); | |
12827 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
12828 | { int flgs = ((int8_t)(src)) < 0; | |
12829 | int flgo = ((int8_t)(dst)) < 0; | |
12830 | int flgn = ((int8_t)(newv)) < 0; | |
12831 | SET_ZFLG (((int8_t)(newv)) == 0); | |
12832 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
12833 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
12834 | COPY_CARRY; | |
12835 | SET_NFLG (flgn != 0); | |
12836 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
12837 | }}}}}}m68k_incpc(2); | |
12838 | return 4; | |
12839 | } | |
12840 | unsigned long CPUFUNC(op_5110_4)(uint32_t opcode) /* SUB */ | |
12841 | { | |
12842 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
12843 | uint32_t dstreg = opcode & 7; | |
12844 | OpcodeFamily = 7; CurrentInstrCycles = 12; | |
12845 | {{ uint32_t src = srcreg; | |
12846 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
12847 | { int8_t dst = m68k_read_memory_8(dsta); | |
12848 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
12849 | { int flgs = ((int8_t)(src)) < 0; | |
12850 | int flgo = ((int8_t)(dst)) < 0; | |
12851 | int flgn = ((int8_t)(newv)) < 0; | |
12852 | SET_ZFLG (((int8_t)(newv)) == 0); | |
12853 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
12854 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
12855 | COPY_CARRY; | |
12856 | SET_NFLG (flgn != 0); | |
12857 | m68k_write_memory_8(dsta,newv); | |
12858 | }}}}}}}m68k_incpc(2); | |
12859 | return 12; | |
12860 | } | |
12861 | unsigned long CPUFUNC(op_5118_4)(uint32_t opcode) /* SUB */ | |
12862 | { | |
12863 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
12864 | uint32_t dstreg = opcode & 7; | |
12865 | OpcodeFamily = 7; CurrentInstrCycles = 12; | |
12866 | {{ uint32_t src = srcreg; | |
12867 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
12868 | { int8_t dst = m68k_read_memory_8(dsta); | |
12869 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
12870 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
12871 | { int flgs = ((int8_t)(src)) < 0; | |
12872 | int flgo = ((int8_t)(dst)) < 0; | |
12873 | int flgn = ((int8_t)(newv)) < 0; | |
12874 | SET_ZFLG (((int8_t)(newv)) == 0); | |
12875 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
12876 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
12877 | COPY_CARRY; | |
12878 | SET_NFLG (flgn != 0); | |
12879 | m68k_write_memory_8(dsta,newv); | |
12880 | }}}}}}}m68k_incpc(2); | |
12881 | return 12; | |
12882 | } | |
12883 | unsigned long CPUFUNC(op_5120_4)(uint32_t opcode) /* SUB */ | |
12884 | { | |
12885 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
12886 | uint32_t dstreg = opcode & 7; | |
12887 | OpcodeFamily = 7; CurrentInstrCycles = 14; | |
12888 | {{ uint32_t src = srcreg; | |
12889 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
12890 | { int8_t dst = m68k_read_memory_8(dsta); | |
12891 | m68k_areg (regs, dstreg) = dsta; | |
12892 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
12893 | { int flgs = ((int8_t)(src)) < 0; | |
12894 | int flgo = ((int8_t)(dst)) < 0; | |
12895 | int flgn = ((int8_t)(newv)) < 0; | |
12896 | SET_ZFLG (((int8_t)(newv)) == 0); | |
12897 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
12898 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
12899 | COPY_CARRY; | |
12900 | SET_NFLG (flgn != 0); | |
12901 | m68k_write_memory_8(dsta,newv); | |
12902 | }}}}}}}m68k_incpc(2); | |
12903 | return 14; | |
12904 | } | |
12905 | unsigned long CPUFUNC(op_5128_4)(uint32_t opcode) /* SUB */ | |
12906 | { | |
12907 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
12908 | uint32_t dstreg = opcode & 7; | |
12909 | OpcodeFamily = 7; CurrentInstrCycles = 16; | |
12910 | {{ uint32_t src = srcreg; | |
12911 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); | |
12912 | { int8_t dst = m68k_read_memory_8(dsta); | |
12913 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
12914 | { int flgs = ((int8_t)(src)) < 0; | |
12915 | int flgo = ((int8_t)(dst)) < 0; | |
12916 | int flgn = ((int8_t)(newv)) < 0; | |
12917 | SET_ZFLG (((int8_t)(newv)) == 0); | |
12918 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
12919 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
12920 | COPY_CARRY; | |
12921 | SET_NFLG (flgn != 0); | |
12922 | m68k_write_memory_8(dsta,newv); | |
12923 | }}}}}}}m68k_incpc(4); | |
12924 | return 16; | |
12925 | } | |
12926 | unsigned long CPUFUNC(op_5130_4)(uint32_t opcode) /* SUB */ | |
12927 | { | |
12928 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
12929 | uint32_t dstreg = opcode & 7; | |
12930 | OpcodeFamily = 7; CurrentInstrCycles = 18; | |
12931 | {{ uint32_t src = srcreg; | |
12932 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); | |
12933 | BusCyclePenalty += 2; | |
12934 | { int8_t dst = m68k_read_memory_8(dsta); | |
12935 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
12936 | { int flgs = ((int8_t)(src)) < 0; | |
12937 | int flgo = ((int8_t)(dst)) < 0; | |
12938 | int flgn = ((int8_t)(newv)) < 0; | |
12939 | SET_ZFLG (((int8_t)(newv)) == 0); | |
12940 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
12941 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
12942 | COPY_CARRY; | |
12943 | SET_NFLG (flgn != 0); | |
12944 | m68k_write_memory_8(dsta,newv); | |
12945 | }}}}}}}m68k_incpc(4); | |
12946 | return 18; | |
12947 | } | |
12948 | unsigned long CPUFUNC(op_5138_4)(uint32_t opcode) /* SUB */ | |
12949 | { | |
12950 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
12951 | OpcodeFamily = 7; CurrentInstrCycles = 16; | |
12952 | {{ uint32_t src = srcreg; | |
12953 | { uint32_t dsta = (int32_t)(int16_t)get_iword(2); | |
12954 | { int8_t dst = m68k_read_memory_8(dsta); | |
12955 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
12956 | { int flgs = ((int8_t)(src)) < 0; | |
12957 | int flgo = ((int8_t)(dst)) < 0; | |
12958 | int flgn = ((int8_t)(newv)) < 0; | |
12959 | SET_ZFLG (((int8_t)(newv)) == 0); | |
12960 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
12961 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
12962 | COPY_CARRY; | |
12963 | SET_NFLG (flgn != 0); | |
12964 | m68k_write_memory_8(dsta,newv); | |
12965 | }}}}}}}m68k_incpc(4); | |
12966 | return 16; | |
12967 | } | |
12968 | unsigned long CPUFUNC(op_5139_4)(uint32_t opcode) /* SUB */ | |
12969 | { | |
12970 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
12971 | OpcodeFamily = 7; CurrentInstrCycles = 20; | |
12972 | {{ uint32_t src = srcreg; | |
12973 | { uint32_t dsta = get_ilong(2); | |
12974 | { int8_t dst = m68k_read_memory_8(dsta); | |
12975 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
12976 | { int flgs = ((int8_t)(src)) < 0; | |
12977 | int flgo = ((int8_t)(dst)) < 0; | |
12978 | int flgn = ((int8_t)(newv)) < 0; | |
12979 | SET_ZFLG (((int8_t)(newv)) == 0); | |
12980 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
12981 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
12982 | COPY_CARRY; | |
12983 | SET_NFLG (flgn != 0); | |
12984 | m68k_write_memory_8(dsta,newv); | |
12985 | }}}}}}}m68k_incpc(6); | |
12986 | return 20; | |
12987 | } | |
12988 | unsigned long CPUFUNC(op_5140_4)(uint32_t opcode) /* SUB */ | |
12989 | { | |
12990 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
12991 | uint32_t dstreg = opcode & 7; | |
12992 | OpcodeFamily = 7; CurrentInstrCycles = 4; | |
12993 | {{ uint32_t src = srcreg; | |
12994 | { int16_t dst = m68k_dreg(regs, dstreg); | |
12995 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
12996 | { int flgs = ((int16_t)(src)) < 0; | |
12997 | int flgo = ((int16_t)(dst)) < 0; | |
12998 | int flgn = ((int16_t)(newv)) < 0; | |
12999 | SET_ZFLG (((int16_t)(newv)) == 0); | |
13000 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
13001 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
13002 | COPY_CARRY; | |
13003 | SET_NFLG (flgn != 0); | |
13004 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
13005 | }}}}}}m68k_incpc(2); | |
13006 | return 4; | |
13007 | } | |
13008 | unsigned long CPUFUNC(op_5148_4)(uint32_t opcode) /* SUBA */ | |
13009 | { | |
13010 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
13011 | uint32_t dstreg = opcode & 7; | |
13012 | OpcodeFamily = 8; CurrentInstrCycles = 8; | |
13013 | {{ uint32_t src = srcreg; | |
13014 | { int32_t dst = m68k_areg(regs, dstreg); | |
13015 | { uint32_t newv = dst - src; | |
13016 | m68k_areg(regs, dstreg) = (newv); | |
13017 | }}}}m68k_incpc(2); | |
13018 | return 8; | |
13019 | } | |
13020 | unsigned long CPUFUNC(op_5150_4)(uint32_t opcode) /* SUB */ | |
13021 | { | |
13022 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
13023 | uint32_t dstreg = opcode & 7; | |
13024 | OpcodeFamily = 7; CurrentInstrCycles = 12; | |
13025 | {{ uint32_t src = srcreg; | |
13026 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
13027 | { int16_t dst = m68k_read_memory_16(dsta); | |
13028 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
13029 | { int flgs = ((int16_t)(src)) < 0; | |
13030 | int flgo = ((int16_t)(dst)) < 0; | |
13031 | int flgn = ((int16_t)(newv)) < 0; | |
13032 | SET_ZFLG (((int16_t)(newv)) == 0); | |
13033 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
13034 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
13035 | COPY_CARRY; | |
13036 | SET_NFLG (flgn != 0); | |
13037 | m68k_write_memory_16(dsta,newv); | |
13038 | }}}}}}}m68k_incpc(2); | |
13039 | return 12; | |
13040 | } | |
13041 | unsigned long CPUFUNC(op_5158_4)(uint32_t opcode) /* SUB */ | |
13042 | { | |
13043 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
13044 | uint32_t dstreg = opcode & 7; | |
13045 | OpcodeFamily = 7; CurrentInstrCycles = 12; | |
13046 | {{ uint32_t src = srcreg; | |
13047 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
13048 | { int16_t dst = m68k_read_memory_16(dsta); | |
13049 | m68k_areg(regs, dstreg) += 2; | |
13050 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
13051 | { int flgs = ((int16_t)(src)) < 0; | |
13052 | int flgo = ((int16_t)(dst)) < 0; | |
13053 | int flgn = ((int16_t)(newv)) < 0; | |
13054 | SET_ZFLG (((int16_t)(newv)) == 0); | |
13055 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
13056 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
13057 | COPY_CARRY; | |
13058 | SET_NFLG (flgn != 0); | |
13059 | m68k_write_memory_16(dsta,newv); | |
13060 | }}}}}}}m68k_incpc(2); | |
13061 | return 12; | |
13062 | } | |
13063 | unsigned long CPUFUNC(op_5160_4)(uint32_t opcode) /* SUB */ | |
13064 | { | |
13065 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
13066 | uint32_t dstreg = opcode & 7; | |
13067 | OpcodeFamily = 7; CurrentInstrCycles = 14; | |
13068 | {{ uint32_t src = srcreg; | |
13069 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
13070 | { int16_t dst = m68k_read_memory_16(dsta); | |
13071 | m68k_areg (regs, dstreg) = dsta; | |
13072 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
13073 | { int flgs = ((int16_t)(src)) < 0; | |
13074 | int flgo = ((int16_t)(dst)) < 0; | |
13075 | int flgn = ((int16_t)(newv)) < 0; | |
13076 | SET_ZFLG (((int16_t)(newv)) == 0); | |
13077 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
13078 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
13079 | COPY_CARRY; | |
13080 | SET_NFLG (flgn != 0); | |
13081 | m68k_write_memory_16(dsta,newv); | |
13082 | }}}}}}}m68k_incpc(2); | |
13083 | return 14; | |
13084 | } | |
13085 | unsigned long CPUFUNC(op_5168_4)(uint32_t opcode) /* SUB */ | |
13086 | { | |
13087 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
13088 | uint32_t dstreg = opcode & 7; | |
13089 | OpcodeFamily = 7; CurrentInstrCycles = 16; | |
13090 | {{ uint32_t src = srcreg; | |
13091 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); | |
13092 | { int16_t dst = m68k_read_memory_16(dsta); | |
13093 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
13094 | { int flgs = ((int16_t)(src)) < 0; | |
13095 | int flgo = ((int16_t)(dst)) < 0; | |
13096 | int flgn = ((int16_t)(newv)) < 0; | |
13097 | SET_ZFLG (((int16_t)(newv)) == 0); | |
13098 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
13099 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
13100 | COPY_CARRY; | |
13101 | SET_NFLG (flgn != 0); | |
13102 | m68k_write_memory_16(dsta,newv); | |
13103 | }}}}}}}m68k_incpc(4); | |
13104 | return 16; | |
13105 | } | |
13106 | unsigned long CPUFUNC(op_5170_4)(uint32_t opcode) /* SUB */ | |
13107 | { | |
13108 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
13109 | uint32_t dstreg = opcode & 7; | |
13110 | OpcodeFamily = 7; CurrentInstrCycles = 18; | |
13111 | {{ uint32_t src = srcreg; | |
13112 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); | |
13113 | BusCyclePenalty += 2; | |
13114 | { int16_t dst = m68k_read_memory_16(dsta); | |
13115 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
13116 | { int flgs = ((int16_t)(src)) < 0; | |
13117 | int flgo = ((int16_t)(dst)) < 0; | |
13118 | int flgn = ((int16_t)(newv)) < 0; | |
13119 | SET_ZFLG (((int16_t)(newv)) == 0); | |
13120 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
13121 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
13122 | COPY_CARRY; | |
13123 | SET_NFLG (flgn != 0); | |
13124 | m68k_write_memory_16(dsta,newv); | |
13125 | }}}}}}}m68k_incpc(4); | |
13126 | return 18; | |
13127 | } | |
13128 | unsigned long CPUFUNC(op_5178_4)(uint32_t opcode) /* SUB */ | |
13129 | { | |
13130 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
13131 | OpcodeFamily = 7; CurrentInstrCycles = 16; | |
13132 | {{ uint32_t src = srcreg; | |
13133 | { uint32_t dsta = (int32_t)(int16_t)get_iword(2); | |
13134 | { int16_t dst = m68k_read_memory_16(dsta); | |
13135 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
13136 | { int flgs = ((int16_t)(src)) < 0; | |
13137 | int flgo = ((int16_t)(dst)) < 0; | |
13138 | int flgn = ((int16_t)(newv)) < 0; | |
13139 | SET_ZFLG (((int16_t)(newv)) == 0); | |
13140 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
13141 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
13142 | COPY_CARRY; | |
13143 | SET_NFLG (flgn != 0); | |
13144 | m68k_write_memory_16(dsta,newv); | |
13145 | }}}}}}}m68k_incpc(4); | |
13146 | return 16; | |
13147 | } | |
13148 | unsigned long CPUFUNC(op_5179_4)(uint32_t opcode) /* SUB */ | |
13149 | { | |
13150 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
13151 | OpcodeFamily = 7; CurrentInstrCycles = 20; | |
13152 | {{ uint32_t src = srcreg; | |
13153 | { uint32_t dsta = get_ilong(2); | |
13154 | { int16_t dst = m68k_read_memory_16(dsta); | |
13155 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
13156 | { int flgs = ((int16_t)(src)) < 0; | |
13157 | int flgo = ((int16_t)(dst)) < 0; | |
13158 | int flgn = ((int16_t)(newv)) < 0; | |
13159 | SET_ZFLG (((int16_t)(newv)) == 0); | |
13160 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
13161 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
13162 | COPY_CARRY; | |
13163 | SET_NFLG (flgn != 0); | |
13164 | m68k_write_memory_16(dsta,newv); | |
13165 | }}}}}}}m68k_incpc(6); | |
13166 | return 20; | |
13167 | } | |
13168 | unsigned long CPUFUNC(op_5180_4)(uint32_t opcode) /* SUB */ | |
13169 | { | |
13170 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
13171 | uint32_t dstreg = opcode & 7; | |
13172 | OpcodeFamily = 7; CurrentInstrCycles = 8; | |
13173 | {{ uint32_t src = srcreg; | |
13174 | { int32_t dst = m68k_dreg(regs, dstreg); | |
13175 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
13176 | { int flgs = ((int32_t)(src)) < 0; | |
13177 | int flgo = ((int32_t)(dst)) < 0; | |
13178 | int flgn = ((int32_t)(newv)) < 0; | |
13179 | SET_ZFLG (((int32_t)(newv)) == 0); | |
13180 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
13181 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
13182 | COPY_CARRY; | |
13183 | SET_NFLG (flgn != 0); | |
13184 | m68k_dreg(regs, dstreg) = (newv); | |
13185 | }}}}}}m68k_incpc(2); | |
13186 | return 8; | |
13187 | } | |
13188 | unsigned long CPUFUNC(op_5188_4)(uint32_t opcode) /* SUBA */ | |
13189 | { | |
13190 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
13191 | uint32_t dstreg = opcode & 7; | |
13192 | OpcodeFamily = 8; CurrentInstrCycles = 8; | |
13193 | {{ uint32_t src = srcreg; | |
13194 | { int32_t dst = m68k_areg(regs, dstreg); | |
13195 | { uint32_t newv = dst - src; | |
13196 | m68k_areg(regs, dstreg) = (newv); | |
13197 | }}}}m68k_incpc(2); | |
13198 | return 8; | |
13199 | } | |
13200 | unsigned long CPUFUNC(op_5190_4)(uint32_t opcode) /* SUB */ | |
13201 | { | |
13202 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
13203 | uint32_t dstreg = opcode & 7; | |
13204 | OpcodeFamily = 7; CurrentInstrCycles = 20; | |
13205 | {{ uint32_t src = srcreg; | |
13206 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
13207 | { int32_t dst = m68k_read_memory_32(dsta); | |
13208 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
13209 | { int flgs = ((int32_t)(src)) < 0; | |
13210 | int flgo = ((int32_t)(dst)) < 0; | |
13211 | int flgn = ((int32_t)(newv)) < 0; | |
13212 | SET_ZFLG (((int32_t)(newv)) == 0); | |
13213 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
13214 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
13215 | COPY_CARRY; | |
13216 | SET_NFLG (flgn != 0); | |
13217 | m68k_write_memory_32(dsta,newv); | |
13218 | }}}}}}}m68k_incpc(2); | |
13219 | return 20; | |
13220 | } | |
13221 | unsigned long CPUFUNC(op_5198_4)(uint32_t opcode) /* SUB */ | |
13222 | { | |
13223 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
13224 | uint32_t dstreg = opcode & 7; | |
13225 | OpcodeFamily = 7; CurrentInstrCycles = 20; | |
13226 | {{ uint32_t src = srcreg; | |
13227 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
13228 | { int32_t dst = m68k_read_memory_32(dsta); | |
13229 | m68k_areg(regs, dstreg) += 4; | |
13230 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
13231 | { int flgs = ((int32_t)(src)) < 0; | |
13232 | int flgo = ((int32_t)(dst)) < 0; | |
13233 | int flgn = ((int32_t)(newv)) < 0; | |
13234 | SET_ZFLG (((int32_t)(newv)) == 0); | |
13235 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
13236 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
13237 | COPY_CARRY; | |
13238 | SET_NFLG (flgn != 0); | |
13239 | m68k_write_memory_32(dsta,newv); | |
13240 | }}}}}}}m68k_incpc(2); | |
13241 | return 20; | |
13242 | } | |
13243 | unsigned long CPUFUNC(op_51a0_4)(uint32_t opcode) /* SUB */ | |
13244 | { | |
13245 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
13246 | uint32_t dstreg = opcode & 7; | |
13247 | OpcodeFamily = 7; CurrentInstrCycles = 22; | |
13248 | {{ uint32_t src = srcreg; | |
13249 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
13250 | { int32_t dst = m68k_read_memory_32(dsta); | |
13251 | m68k_areg (regs, dstreg) = dsta; | |
13252 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
13253 | { int flgs = ((int32_t)(src)) < 0; | |
13254 | int flgo = ((int32_t)(dst)) < 0; | |
13255 | int flgn = ((int32_t)(newv)) < 0; | |
13256 | SET_ZFLG (((int32_t)(newv)) == 0); | |
13257 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
13258 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
13259 | COPY_CARRY; | |
13260 | SET_NFLG (flgn != 0); | |
13261 | m68k_write_memory_32(dsta,newv); | |
13262 | }}}}}}}m68k_incpc(2); | |
13263 | return 22; | |
13264 | } | |
13265 | unsigned long CPUFUNC(op_51a8_4)(uint32_t opcode) /* SUB */ | |
13266 | { | |
13267 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
13268 | uint32_t dstreg = opcode & 7; | |
13269 | OpcodeFamily = 7; CurrentInstrCycles = 24; | |
13270 | {{ uint32_t src = srcreg; | |
13271 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); | |
13272 | { int32_t dst = m68k_read_memory_32(dsta); | |
13273 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
13274 | { int flgs = ((int32_t)(src)) < 0; | |
13275 | int flgo = ((int32_t)(dst)) < 0; | |
13276 | int flgn = ((int32_t)(newv)) < 0; | |
13277 | SET_ZFLG (((int32_t)(newv)) == 0); | |
13278 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
13279 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
13280 | COPY_CARRY; | |
13281 | SET_NFLG (flgn != 0); | |
13282 | m68k_write_memory_32(dsta,newv); | |
13283 | }}}}}}}m68k_incpc(4); | |
13284 | return 24; | |
13285 | } | |
13286 | unsigned long CPUFUNC(op_51b0_4)(uint32_t opcode) /* SUB */ | |
13287 | { | |
13288 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
13289 | uint32_t dstreg = opcode & 7; | |
13290 | OpcodeFamily = 7; CurrentInstrCycles = 26; | |
13291 | {{ uint32_t src = srcreg; | |
13292 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); | |
13293 | BusCyclePenalty += 2; | |
13294 | { int32_t dst = m68k_read_memory_32(dsta); | |
13295 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
13296 | { int flgs = ((int32_t)(src)) < 0; | |
13297 | int flgo = ((int32_t)(dst)) < 0; | |
13298 | int flgn = ((int32_t)(newv)) < 0; | |
13299 | SET_ZFLG (((int32_t)(newv)) == 0); | |
13300 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
13301 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
13302 | COPY_CARRY; | |
13303 | SET_NFLG (flgn != 0); | |
13304 | m68k_write_memory_32(dsta,newv); | |
13305 | }}}}}}}m68k_incpc(4); | |
13306 | return 26; | |
13307 | } | |
13308 | unsigned long CPUFUNC(op_51b8_4)(uint32_t opcode) /* SUB */ | |
13309 | { | |
13310 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
13311 | OpcodeFamily = 7; CurrentInstrCycles = 24; | |
13312 | {{ uint32_t src = srcreg; | |
13313 | { uint32_t dsta = (int32_t)(int16_t)get_iword(2); | |
13314 | { int32_t dst = m68k_read_memory_32(dsta); | |
13315 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
13316 | { int flgs = ((int32_t)(src)) < 0; | |
13317 | int flgo = ((int32_t)(dst)) < 0; | |
13318 | int flgn = ((int32_t)(newv)) < 0; | |
13319 | SET_ZFLG (((int32_t)(newv)) == 0); | |
13320 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
13321 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
13322 | COPY_CARRY; | |
13323 | SET_NFLG (flgn != 0); | |
13324 | m68k_write_memory_32(dsta,newv); | |
13325 | }}}}}}}m68k_incpc(4); | |
13326 | return 24; | |
13327 | } | |
13328 | unsigned long CPUFUNC(op_51b9_4)(uint32_t opcode) /* SUB */ | |
13329 | { | |
13330 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
13331 | OpcodeFamily = 7; CurrentInstrCycles = 28; | |
13332 | {{ uint32_t src = srcreg; | |
13333 | { uint32_t dsta = get_ilong(2); | |
13334 | { int32_t dst = m68k_read_memory_32(dsta); | |
13335 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
13336 | { int flgs = ((int32_t)(src)) < 0; | |
13337 | int flgo = ((int32_t)(dst)) < 0; | |
13338 | int flgn = ((int32_t)(newv)) < 0; | |
13339 | SET_ZFLG (((int32_t)(newv)) == 0); | |
13340 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
13341 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
13342 | COPY_CARRY; | |
13343 | SET_NFLG (flgn != 0); | |
13344 | m68k_write_memory_32(dsta,newv); | |
13345 | }}}}}}}m68k_incpc(6); | |
13346 | return 28; | |
13347 | } | |
13348 | unsigned long CPUFUNC(op_51c0_4)(uint32_t opcode) /* Scc */ | |
13349 | { | |
13350 | uint32_t srcreg = (opcode & 7); | |
13351 | OpcodeFamily = 59; CurrentInstrCycles = 4; | |
13352 | {{{ int val = cctrue(1) ? 0xff : 0; | |
13353 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); | |
13354 | if (val) { m68k_incpc(2) ; return 4+2; } | |
13355 | }}}m68k_incpc(2); | |
13356 | return 4; | |
13357 | } | |
13358 | unsigned long CPUFUNC(op_51c8_4)(uint32_t opcode) /* DBcc */ | |
13359 | { | |
13360 | uint32_t srcreg = (opcode & 7); | |
13361 | OpcodeFamily = 58; CurrentInstrCycles = 12; | |
13362 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
13363 | { int16_t offs = get_iword(2); | |
13364 | if (!cctrue(1)) { | |
13365 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); | |
13366 | if (src) { | |
13367 | m68k_incpc((int32_t)offs + 2); | |
13368 | return 10; | |
13369 | } else { | |
13370 | m68k_incpc(4); | |
13371 | return 14; | |
13372 | } | |
13373 | } | |
13374 | }}}m68k_incpc(4); | |
13375 | endlabel877: ; | |
13376 | return 12; | |
13377 | } | |
13378 | unsigned long CPUFUNC(op_51d0_4)(uint32_t opcode) /* Scc */ | |
13379 | { | |
13380 | uint32_t srcreg = (opcode & 7); | |
13381 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
13382 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
13383 | { int val = cctrue(1) ? 0xff : 0; | |
13384 | m68k_write_memory_8(srca,val); | |
13385 | }}}m68k_incpc(2); | |
13386 | return 12; | |
13387 | } | |
13388 | unsigned long CPUFUNC(op_51d8_4)(uint32_t opcode) /* Scc */ | |
13389 | { | |
13390 | uint32_t srcreg = (opcode & 7); | |
13391 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
13392 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
13393 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
13394 | { int val = cctrue(1) ? 0xff : 0; | |
13395 | m68k_write_memory_8(srca,val); | |
13396 | }}}m68k_incpc(2); | |
13397 | return 12; | |
13398 | } | |
13399 | unsigned long CPUFUNC(op_51e0_4)(uint32_t opcode) /* Scc */ | |
13400 | { | |
13401 | uint32_t srcreg = (opcode & 7); | |
13402 | OpcodeFamily = 59; CurrentInstrCycles = 14; | |
13403 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
13404 | m68k_areg (regs, srcreg) = srca; | |
13405 | { int val = cctrue(1) ? 0xff : 0; | |
13406 | m68k_write_memory_8(srca,val); | |
13407 | }}}m68k_incpc(2); | |
13408 | return 14; | |
13409 | } | |
13410 | unsigned long CPUFUNC(op_51e8_4)(uint32_t opcode) /* Scc */ | |
13411 | { | |
13412 | uint32_t srcreg = (opcode & 7); | |
13413 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
13414 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
13415 | { int val = cctrue(1) ? 0xff : 0; | |
13416 | m68k_write_memory_8(srca,val); | |
13417 | }}}m68k_incpc(4); | |
13418 | return 16; | |
13419 | } | |
13420 | unsigned long CPUFUNC(op_51f0_4)(uint32_t opcode) /* Scc */ | |
13421 | { | |
13422 | uint32_t srcreg = (opcode & 7); | |
13423 | OpcodeFamily = 59; CurrentInstrCycles = 18; | |
13424 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
13425 | BusCyclePenalty += 2; | |
13426 | { int val = cctrue(1) ? 0xff : 0; | |
13427 | m68k_write_memory_8(srca,val); | |
13428 | }}}m68k_incpc(4); | |
13429 | return 18; | |
13430 | } | |
13431 | unsigned long CPUFUNC(op_51f8_4)(uint32_t opcode) /* Scc */ | |
13432 | { | |
13433 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
13434 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
13435 | { int val = cctrue(1) ? 0xff : 0; | |
13436 | m68k_write_memory_8(srca,val); | |
13437 | }}}m68k_incpc(4); | |
13438 | return 16; | |
13439 | } | |
13440 | unsigned long CPUFUNC(op_51f9_4)(uint32_t opcode) /* Scc */ | |
13441 | { | |
13442 | OpcodeFamily = 59; CurrentInstrCycles = 20; | |
13443 | {{ uint32_t srca = get_ilong(2); | |
13444 | { int val = cctrue(1) ? 0xff : 0; | |
13445 | m68k_write_memory_8(srca,val); | |
13446 | }}}m68k_incpc(6); | |
13447 | return 20; | |
13448 | } | |
13449 | unsigned long CPUFUNC(op_52c0_4)(uint32_t opcode) /* Scc */ | |
13450 | { | |
13451 | uint32_t srcreg = (opcode & 7); | |
13452 | OpcodeFamily = 59; CurrentInstrCycles = 4; | |
13453 | {{{ int val = cctrue(2) ? 0xff : 0; | |
13454 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); | |
13455 | if (val) { m68k_incpc(2) ; return 4+2; } | |
13456 | }}}m68k_incpc(2); | |
13457 | return 4; | |
13458 | } | |
13459 | unsigned long CPUFUNC(op_52c8_4)(uint32_t opcode) /* DBcc */ | |
13460 | { | |
13461 | uint32_t srcreg = (opcode & 7); | |
13462 | OpcodeFamily = 58; CurrentInstrCycles = 12; | |
13463 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
13464 | { int16_t offs = get_iword(2); | |
13465 | if (!cctrue(2)) { | |
13466 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); | |
13467 | if (src) { | |
13468 | m68k_incpc((int32_t)offs + 2); | |
13469 | return 10; | |
13470 | } else { | |
13471 | m68k_incpc(4); | |
13472 | return 14; | |
13473 | } | |
13474 | } | |
13475 | }}}m68k_incpc(4); | |
13476 | endlabel886: ; | |
13477 | return 12; | |
13478 | } | |
13479 | unsigned long CPUFUNC(op_52d0_4)(uint32_t opcode) /* Scc */ | |
13480 | { | |
13481 | uint32_t srcreg = (opcode & 7); | |
13482 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
13483 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
13484 | { int val = cctrue(2) ? 0xff : 0; | |
13485 | m68k_write_memory_8(srca,val); | |
13486 | }}}m68k_incpc(2); | |
13487 | return 12; | |
13488 | } | |
13489 | unsigned long CPUFUNC(op_52d8_4)(uint32_t opcode) /* Scc */ | |
13490 | { | |
13491 | uint32_t srcreg = (opcode & 7); | |
13492 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
13493 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
13494 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
13495 | { int val = cctrue(2) ? 0xff : 0; | |
13496 | m68k_write_memory_8(srca,val); | |
13497 | }}}m68k_incpc(2); | |
13498 | return 12; | |
13499 | } | |
13500 | unsigned long CPUFUNC(op_52e0_4)(uint32_t opcode) /* Scc */ | |
13501 | { | |
13502 | uint32_t srcreg = (opcode & 7); | |
13503 | OpcodeFamily = 59; CurrentInstrCycles = 14; | |
13504 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
13505 | m68k_areg (regs, srcreg) = srca; | |
13506 | { int val = cctrue(2) ? 0xff : 0; | |
13507 | m68k_write_memory_8(srca,val); | |
13508 | }}}m68k_incpc(2); | |
13509 | return 14; | |
13510 | } | |
13511 | unsigned long CPUFUNC(op_52e8_4)(uint32_t opcode) /* Scc */ | |
13512 | { | |
13513 | uint32_t srcreg = (opcode & 7); | |
13514 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
13515 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
13516 | { int val = cctrue(2) ? 0xff : 0; | |
13517 | m68k_write_memory_8(srca,val); | |
13518 | }}}m68k_incpc(4); | |
13519 | return 16; | |
13520 | } | |
13521 | unsigned long CPUFUNC(op_52f0_4)(uint32_t opcode) /* Scc */ | |
13522 | { | |
13523 | uint32_t srcreg = (opcode & 7); | |
13524 | OpcodeFamily = 59; CurrentInstrCycles = 18; | |
13525 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
13526 | BusCyclePenalty += 2; | |
13527 | { int val = cctrue(2) ? 0xff : 0; | |
13528 | m68k_write_memory_8(srca,val); | |
13529 | }}}m68k_incpc(4); | |
13530 | return 18; | |
13531 | } | |
13532 | unsigned long CPUFUNC(op_52f8_4)(uint32_t opcode) /* Scc */ | |
13533 | { | |
13534 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
13535 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
13536 | { int val = cctrue(2) ? 0xff : 0; | |
13537 | m68k_write_memory_8(srca,val); | |
13538 | }}}m68k_incpc(4); | |
13539 | return 16; | |
13540 | } | |
13541 | unsigned long CPUFUNC(op_52f9_4)(uint32_t opcode) /* Scc */ | |
13542 | { | |
13543 | OpcodeFamily = 59; CurrentInstrCycles = 20; | |
13544 | {{ uint32_t srca = get_ilong(2); | |
13545 | { int val = cctrue(2) ? 0xff : 0; | |
13546 | m68k_write_memory_8(srca,val); | |
13547 | }}}m68k_incpc(6); | |
13548 | return 20; | |
13549 | } | |
13550 | unsigned long CPUFUNC(op_53c0_4)(uint32_t opcode) /* Scc */ | |
13551 | { | |
13552 | uint32_t srcreg = (opcode & 7); | |
13553 | OpcodeFamily = 59; CurrentInstrCycles = 4; | |
13554 | {{{ int val = cctrue(3) ? 0xff : 0; | |
13555 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); | |
13556 | if (val) { m68k_incpc(2) ; return 4+2; } | |
13557 | }}}m68k_incpc(2); | |
13558 | return 4; | |
13559 | } | |
13560 | unsigned long CPUFUNC(op_53c8_4)(uint32_t opcode) /* DBcc */ | |
13561 | { | |
13562 | uint32_t srcreg = (opcode & 7); | |
13563 | OpcodeFamily = 58; CurrentInstrCycles = 12; | |
13564 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
13565 | { int16_t offs = get_iword(2); | |
13566 | if (!cctrue(3)) { | |
13567 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); | |
13568 | if (src) { | |
13569 | m68k_incpc((int32_t)offs + 2); | |
13570 | return 10; | |
13571 | } else { | |
13572 | m68k_incpc(4); | |
13573 | return 14; | |
13574 | } | |
13575 | } | |
13576 | }}}m68k_incpc(4); | |
13577 | endlabel895: ; | |
13578 | return 12; | |
13579 | } | |
13580 | unsigned long CPUFUNC(op_53d0_4)(uint32_t opcode) /* Scc */ | |
13581 | { | |
13582 | uint32_t srcreg = (opcode & 7); | |
13583 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
13584 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
13585 | { int val = cctrue(3) ? 0xff : 0; | |
13586 | m68k_write_memory_8(srca,val); | |
13587 | }}}m68k_incpc(2); | |
13588 | return 12; | |
13589 | } | |
13590 | unsigned long CPUFUNC(op_53d8_4)(uint32_t opcode) /* Scc */ | |
13591 | { | |
13592 | uint32_t srcreg = (opcode & 7); | |
13593 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
13594 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
13595 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
13596 | { int val = cctrue(3) ? 0xff : 0; | |
13597 | m68k_write_memory_8(srca,val); | |
13598 | }}}m68k_incpc(2); | |
13599 | return 12; | |
13600 | } | |
13601 | unsigned long CPUFUNC(op_53e0_4)(uint32_t opcode) /* Scc */ | |
13602 | { | |
13603 | uint32_t srcreg = (opcode & 7); | |
13604 | OpcodeFamily = 59; CurrentInstrCycles = 14; | |
13605 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
13606 | m68k_areg (regs, srcreg) = srca; | |
13607 | { int val = cctrue(3) ? 0xff : 0; | |
13608 | m68k_write_memory_8(srca,val); | |
13609 | }}}m68k_incpc(2); | |
13610 | return 14; | |
13611 | } | |
13612 | unsigned long CPUFUNC(op_53e8_4)(uint32_t opcode) /* Scc */ | |
13613 | { | |
13614 | uint32_t srcreg = (opcode & 7); | |
13615 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
13616 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
13617 | { int val = cctrue(3) ? 0xff : 0; | |
13618 | m68k_write_memory_8(srca,val); | |
13619 | }}}m68k_incpc(4); | |
13620 | return 16; | |
13621 | } | |
13622 | unsigned long CPUFUNC(op_53f0_4)(uint32_t opcode) /* Scc */ | |
13623 | { | |
13624 | uint32_t srcreg = (opcode & 7); | |
13625 | OpcodeFamily = 59; CurrentInstrCycles = 18; | |
13626 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
13627 | BusCyclePenalty += 2; | |
13628 | { int val = cctrue(3) ? 0xff : 0; | |
13629 | m68k_write_memory_8(srca,val); | |
13630 | }}}m68k_incpc(4); | |
13631 | return 18; | |
13632 | } | |
13633 | unsigned long CPUFUNC(op_53f8_4)(uint32_t opcode) /* Scc */ | |
13634 | { | |
13635 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
13636 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
13637 | { int val = cctrue(3) ? 0xff : 0; | |
13638 | m68k_write_memory_8(srca,val); | |
13639 | }}}m68k_incpc(4); | |
13640 | return 16; | |
13641 | } | |
13642 | unsigned long CPUFUNC(op_53f9_4)(uint32_t opcode) /* Scc */ | |
13643 | { | |
13644 | OpcodeFamily = 59; CurrentInstrCycles = 20; | |
13645 | {{ uint32_t srca = get_ilong(2); | |
13646 | { int val = cctrue(3) ? 0xff : 0; | |
13647 | m68k_write_memory_8(srca,val); | |
13648 | }}}m68k_incpc(6); | |
13649 | return 20; | |
13650 | } | |
13651 | unsigned long CPUFUNC(op_54c0_4)(uint32_t opcode) /* Scc */ | |
13652 | { | |
13653 | uint32_t srcreg = (opcode & 7); | |
13654 | OpcodeFamily = 59; CurrentInstrCycles = 4; | |
13655 | {{{ int val = cctrue(4) ? 0xff : 0; | |
13656 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); | |
13657 | if (val) { m68k_incpc(2) ; return 4+2; } | |
13658 | }}}m68k_incpc(2); | |
13659 | return 4; | |
13660 | } | |
13661 | unsigned long CPUFUNC(op_54c8_4)(uint32_t opcode) /* DBcc */ | |
13662 | { | |
13663 | uint32_t srcreg = (opcode & 7); | |
13664 | OpcodeFamily = 58; CurrentInstrCycles = 12; | |
13665 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
13666 | { int16_t offs = get_iword(2); | |
13667 | if (!cctrue(4)) { | |
13668 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); | |
13669 | if (src) { | |
13670 | m68k_incpc((int32_t)offs + 2); | |
13671 | return 10; | |
13672 | } else { | |
13673 | m68k_incpc(4); | |
13674 | return 14; | |
13675 | } | |
13676 | } | |
13677 | }}}m68k_incpc(4); | |
13678 | endlabel904: ; | |
13679 | return 12; | |
13680 | } | |
13681 | unsigned long CPUFUNC(op_54d0_4)(uint32_t opcode) /* Scc */ | |
13682 | { | |
13683 | uint32_t srcreg = (opcode & 7); | |
13684 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
13685 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
13686 | { int val = cctrue(4) ? 0xff : 0; | |
13687 | m68k_write_memory_8(srca,val); | |
13688 | }}}m68k_incpc(2); | |
13689 | return 12; | |
13690 | } | |
13691 | unsigned long CPUFUNC(op_54d8_4)(uint32_t opcode) /* Scc */ | |
13692 | { | |
13693 | uint32_t srcreg = (opcode & 7); | |
13694 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
13695 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
13696 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
13697 | { int val = cctrue(4) ? 0xff : 0; | |
13698 | m68k_write_memory_8(srca,val); | |
13699 | }}}m68k_incpc(2); | |
13700 | return 12; | |
13701 | } | |
13702 | unsigned long CPUFUNC(op_54e0_4)(uint32_t opcode) /* Scc */ | |
13703 | { | |
13704 | uint32_t srcreg = (opcode & 7); | |
13705 | OpcodeFamily = 59; CurrentInstrCycles = 14; | |
13706 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
13707 | m68k_areg (regs, srcreg) = srca; | |
13708 | { int val = cctrue(4) ? 0xff : 0; | |
13709 | m68k_write_memory_8(srca,val); | |
13710 | }}}m68k_incpc(2); | |
13711 | return 14; | |
13712 | } | |
13713 | unsigned long CPUFUNC(op_54e8_4)(uint32_t opcode) /* Scc */ | |
13714 | { | |
13715 | uint32_t srcreg = (opcode & 7); | |
13716 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
13717 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
13718 | { int val = cctrue(4) ? 0xff : 0; | |
13719 | m68k_write_memory_8(srca,val); | |
13720 | }}}m68k_incpc(4); | |
13721 | return 16; | |
13722 | } | |
13723 | unsigned long CPUFUNC(op_54f0_4)(uint32_t opcode) /* Scc */ | |
13724 | { | |
13725 | uint32_t srcreg = (opcode & 7); | |
13726 | OpcodeFamily = 59; CurrentInstrCycles = 18; | |
13727 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
13728 | BusCyclePenalty += 2; | |
13729 | { int val = cctrue(4) ? 0xff : 0; | |
13730 | m68k_write_memory_8(srca,val); | |
13731 | }}}m68k_incpc(4); | |
13732 | return 18; | |
13733 | } | |
13734 | unsigned long CPUFUNC(op_54f8_4)(uint32_t opcode) /* Scc */ | |
13735 | { | |
13736 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
13737 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
13738 | { int val = cctrue(4) ? 0xff : 0; | |
13739 | m68k_write_memory_8(srca,val); | |
13740 | }}}m68k_incpc(4); | |
13741 | return 16; | |
13742 | } | |
13743 | unsigned long CPUFUNC(op_54f9_4)(uint32_t opcode) /* Scc */ | |
13744 | { | |
13745 | OpcodeFamily = 59; CurrentInstrCycles = 20; | |
13746 | {{ uint32_t srca = get_ilong(2); | |
13747 | { int val = cctrue(4) ? 0xff : 0; | |
13748 | m68k_write_memory_8(srca,val); | |
13749 | }}}m68k_incpc(6); | |
13750 | return 20; | |
13751 | } | |
13752 | unsigned long CPUFUNC(op_55c0_4)(uint32_t opcode) /* Scc */ | |
13753 | { | |
13754 | uint32_t srcreg = (opcode & 7); | |
13755 | OpcodeFamily = 59; CurrentInstrCycles = 4; | |
13756 | {{{ int val = cctrue(5) ? 0xff : 0; | |
13757 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); | |
13758 | if (val) { m68k_incpc(2) ; return 4+2; } | |
13759 | }}}m68k_incpc(2); | |
13760 | return 4; | |
13761 | } | |
13762 | unsigned long CPUFUNC(op_55c8_4)(uint32_t opcode) /* DBcc */ | |
13763 | { | |
13764 | uint32_t srcreg = (opcode & 7); | |
13765 | OpcodeFamily = 58; CurrentInstrCycles = 12; | |
13766 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
13767 | { int16_t offs = get_iword(2); | |
13768 | if (!cctrue(5)) { | |
13769 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); | |
13770 | if (src) { | |
13771 | m68k_incpc((int32_t)offs + 2); | |
13772 | return 10; | |
13773 | } else { | |
13774 | m68k_incpc(4); | |
13775 | return 14; | |
13776 | } | |
13777 | } | |
13778 | }}}m68k_incpc(4); | |
13779 | endlabel913: ; | |
13780 | return 12; | |
13781 | } | |
13782 | unsigned long CPUFUNC(op_55d0_4)(uint32_t opcode) /* Scc */ | |
13783 | { | |
13784 | uint32_t srcreg = (opcode & 7); | |
13785 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
13786 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
13787 | { int val = cctrue(5) ? 0xff : 0; | |
13788 | m68k_write_memory_8(srca,val); | |
13789 | }}}m68k_incpc(2); | |
13790 | return 12; | |
13791 | } | |
13792 | unsigned long CPUFUNC(op_55d8_4)(uint32_t opcode) /* Scc */ | |
13793 | { | |
13794 | uint32_t srcreg = (opcode & 7); | |
13795 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
13796 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
13797 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
13798 | { int val = cctrue(5) ? 0xff : 0; | |
13799 | m68k_write_memory_8(srca,val); | |
13800 | }}}m68k_incpc(2); | |
13801 | return 12; | |
13802 | } | |
13803 | unsigned long CPUFUNC(op_55e0_4)(uint32_t opcode) /* Scc */ | |
13804 | { | |
13805 | uint32_t srcreg = (opcode & 7); | |
13806 | OpcodeFamily = 59; CurrentInstrCycles = 14; | |
13807 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
13808 | m68k_areg (regs, srcreg) = srca; | |
13809 | { int val = cctrue(5) ? 0xff : 0; | |
13810 | m68k_write_memory_8(srca,val); | |
13811 | }}}m68k_incpc(2); | |
13812 | return 14; | |
13813 | } | |
13814 | unsigned long CPUFUNC(op_55e8_4)(uint32_t opcode) /* Scc */ | |
13815 | { | |
13816 | uint32_t srcreg = (opcode & 7); | |
13817 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
13818 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
13819 | { int val = cctrue(5) ? 0xff : 0; | |
13820 | m68k_write_memory_8(srca,val); | |
13821 | }}}m68k_incpc(4); | |
13822 | return 16; | |
13823 | } | |
13824 | unsigned long CPUFUNC(op_55f0_4)(uint32_t opcode) /* Scc */ | |
13825 | { | |
13826 | uint32_t srcreg = (opcode & 7); | |
13827 | OpcodeFamily = 59; CurrentInstrCycles = 18; | |
13828 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
13829 | BusCyclePenalty += 2; | |
13830 | { int val = cctrue(5) ? 0xff : 0; | |
13831 | m68k_write_memory_8(srca,val); | |
13832 | }}}m68k_incpc(4); | |
13833 | return 18; | |
13834 | } | |
13835 | unsigned long CPUFUNC(op_55f8_4)(uint32_t opcode) /* Scc */ | |
13836 | { | |
13837 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
13838 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
13839 | { int val = cctrue(5) ? 0xff : 0; | |
13840 | m68k_write_memory_8(srca,val); | |
13841 | }}}m68k_incpc(4); | |
13842 | return 16; | |
13843 | } | |
13844 | unsigned long CPUFUNC(op_55f9_4)(uint32_t opcode) /* Scc */ | |
13845 | { | |
13846 | OpcodeFamily = 59; CurrentInstrCycles = 20; | |
13847 | {{ uint32_t srca = get_ilong(2); | |
13848 | { int val = cctrue(5) ? 0xff : 0; | |
13849 | m68k_write_memory_8(srca,val); | |
13850 | }}}m68k_incpc(6); | |
13851 | return 20; | |
13852 | } | |
13853 | unsigned long CPUFUNC(op_56c0_4)(uint32_t opcode) /* Scc */ | |
13854 | { | |
13855 | uint32_t srcreg = (opcode & 7); | |
13856 | OpcodeFamily = 59; CurrentInstrCycles = 4; | |
13857 | {{{ int val = cctrue(6) ? 0xff : 0; | |
13858 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); | |
13859 | if (val) { m68k_incpc(2) ; return 4+2; } | |
13860 | }}}m68k_incpc(2); | |
13861 | return 4; | |
13862 | } | |
13863 | unsigned long CPUFUNC(op_56c8_4)(uint32_t opcode) /* DBcc */ | |
13864 | { | |
13865 | uint32_t srcreg = (opcode & 7); | |
13866 | OpcodeFamily = 58; CurrentInstrCycles = 12; | |
13867 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
13868 | { int16_t offs = get_iword(2); | |
13869 | if (!cctrue(6)) { | |
13870 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); | |
13871 | if (src) { | |
13872 | m68k_incpc((int32_t)offs + 2); | |
13873 | return 10; | |
13874 | } else { | |
13875 | m68k_incpc(4); | |
13876 | return 14; | |
13877 | } | |
13878 | } | |
13879 | }}}m68k_incpc(4); | |
13880 | endlabel922: ; | |
13881 | return 12; | |
13882 | } | |
13883 | unsigned long CPUFUNC(op_56d0_4)(uint32_t opcode) /* Scc */ | |
13884 | { | |
13885 | uint32_t srcreg = (opcode & 7); | |
13886 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
13887 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
13888 | { int val = cctrue(6) ? 0xff : 0; | |
13889 | m68k_write_memory_8(srca,val); | |
13890 | }}}m68k_incpc(2); | |
13891 | return 12; | |
13892 | } | |
13893 | unsigned long CPUFUNC(op_56d8_4)(uint32_t opcode) /* Scc */ | |
13894 | { | |
13895 | uint32_t srcreg = (opcode & 7); | |
13896 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
13897 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
13898 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
13899 | { int val = cctrue(6) ? 0xff : 0; | |
13900 | m68k_write_memory_8(srca,val); | |
13901 | }}}m68k_incpc(2); | |
13902 | return 12; | |
13903 | } | |
13904 | unsigned long CPUFUNC(op_56e0_4)(uint32_t opcode) /* Scc */ | |
13905 | { | |
13906 | uint32_t srcreg = (opcode & 7); | |
13907 | OpcodeFamily = 59; CurrentInstrCycles = 14; | |
13908 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
13909 | m68k_areg (regs, srcreg) = srca; | |
13910 | { int val = cctrue(6) ? 0xff : 0; | |
13911 | m68k_write_memory_8(srca,val); | |
13912 | }}}m68k_incpc(2); | |
13913 | return 14; | |
13914 | } | |
13915 | unsigned long CPUFUNC(op_56e8_4)(uint32_t opcode) /* Scc */ | |
13916 | { | |
13917 | uint32_t srcreg = (opcode & 7); | |
13918 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
13919 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
13920 | { int val = cctrue(6) ? 0xff : 0; | |
13921 | m68k_write_memory_8(srca,val); | |
13922 | }}}m68k_incpc(4); | |
13923 | return 16; | |
13924 | } | |
13925 | unsigned long CPUFUNC(op_56f0_4)(uint32_t opcode) /* Scc */ | |
13926 | { | |
13927 | uint32_t srcreg = (opcode & 7); | |
13928 | OpcodeFamily = 59; CurrentInstrCycles = 18; | |
13929 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
13930 | BusCyclePenalty += 2; | |
13931 | { int val = cctrue(6) ? 0xff : 0; | |
13932 | m68k_write_memory_8(srca,val); | |
13933 | }}}m68k_incpc(4); | |
13934 | return 18; | |
13935 | } | |
13936 | unsigned long CPUFUNC(op_56f8_4)(uint32_t opcode) /* Scc */ | |
13937 | { | |
13938 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
13939 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
13940 | { int val = cctrue(6) ? 0xff : 0; | |
13941 | m68k_write_memory_8(srca,val); | |
13942 | }}}m68k_incpc(4); | |
13943 | return 16; | |
13944 | } | |
13945 | unsigned long CPUFUNC(op_56f9_4)(uint32_t opcode) /* Scc */ | |
13946 | { | |
13947 | OpcodeFamily = 59; CurrentInstrCycles = 20; | |
13948 | {{ uint32_t srca = get_ilong(2); | |
13949 | { int val = cctrue(6) ? 0xff : 0; | |
13950 | m68k_write_memory_8(srca,val); | |
13951 | }}}m68k_incpc(6); | |
13952 | return 20; | |
13953 | } | |
13954 | unsigned long CPUFUNC(op_57c0_4)(uint32_t opcode) /* Scc */ | |
13955 | { | |
13956 | uint32_t srcreg = (opcode & 7); | |
13957 | OpcodeFamily = 59; CurrentInstrCycles = 4; | |
13958 | {{{ int val = cctrue(7) ? 0xff : 0; | |
13959 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); | |
13960 | if (val) { m68k_incpc(2) ; return 4+2; } | |
13961 | }}}m68k_incpc(2); | |
13962 | return 4; | |
13963 | } | |
13964 | unsigned long CPUFUNC(op_57c8_4)(uint32_t opcode) /* DBcc */ | |
13965 | { | |
13966 | uint32_t srcreg = (opcode & 7); | |
13967 | OpcodeFamily = 58; CurrentInstrCycles = 12; | |
13968 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
13969 | { int16_t offs = get_iword(2); | |
13970 | if (!cctrue(7)) { | |
13971 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); | |
13972 | if (src) { | |
13973 | m68k_incpc((int32_t)offs + 2); | |
13974 | return 10; | |
13975 | } else { | |
13976 | m68k_incpc(4); | |
13977 | return 14; | |
13978 | } | |
13979 | } | |
13980 | }}}m68k_incpc(4); | |
13981 | endlabel931: ; | |
13982 | return 12; | |
13983 | } | |
13984 | unsigned long CPUFUNC(op_57d0_4)(uint32_t opcode) /* Scc */ | |
13985 | { | |
13986 | uint32_t srcreg = (opcode & 7); | |
13987 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
13988 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
13989 | { int val = cctrue(7) ? 0xff : 0; | |
13990 | m68k_write_memory_8(srca,val); | |
13991 | }}}m68k_incpc(2); | |
13992 | return 12; | |
13993 | } | |
13994 | unsigned long CPUFUNC(op_57d8_4)(uint32_t opcode) /* Scc */ | |
13995 | { | |
13996 | uint32_t srcreg = (opcode & 7); | |
13997 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
13998 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
13999 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
14000 | { int val = cctrue(7) ? 0xff : 0; | |
14001 | m68k_write_memory_8(srca,val); | |
14002 | }}}m68k_incpc(2); | |
14003 | return 12; | |
14004 | } | |
14005 | unsigned long CPUFUNC(op_57e0_4)(uint32_t opcode) /* Scc */ | |
14006 | { | |
14007 | uint32_t srcreg = (opcode & 7); | |
14008 | OpcodeFamily = 59; CurrentInstrCycles = 14; | |
14009 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
14010 | m68k_areg (regs, srcreg) = srca; | |
14011 | { int val = cctrue(7) ? 0xff : 0; | |
14012 | m68k_write_memory_8(srca,val); | |
14013 | }}}m68k_incpc(2); | |
14014 | return 14; | |
14015 | } | |
14016 | unsigned long CPUFUNC(op_57e8_4)(uint32_t opcode) /* Scc */ | |
14017 | { | |
14018 | uint32_t srcreg = (opcode & 7); | |
14019 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
14020 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
14021 | { int val = cctrue(7) ? 0xff : 0; | |
14022 | m68k_write_memory_8(srca,val); | |
14023 | }}}m68k_incpc(4); | |
14024 | return 16; | |
14025 | } | |
14026 | unsigned long CPUFUNC(op_57f0_4)(uint32_t opcode) /* Scc */ | |
14027 | { | |
14028 | uint32_t srcreg = (opcode & 7); | |
14029 | OpcodeFamily = 59; CurrentInstrCycles = 18; | |
14030 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
14031 | BusCyclePenalty += 2; | |
14032 | { int val = cctrue(7) ? 0xff : 0; | |
14033 | m68k_write_memory_8(srca,val); | |
14034 | }}}m68k_incpc(4); | |
14035 | return 18; | |
14036 | } | |
14037 | unsigned long CPUFUNC(op_57f8_4)(uint32_t opcode) /* Scc */ | |
14038 | { | |
14039 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
14040 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
14041 | { int val = cctrue(7) ? 0xff : 0; | |
14042 | m68k_write_memory_8(srca,val); | |
14043 | }}}m68k_incpc(4); | |
14044 | return 16; | |
14045 | } | |
14046 | unsigned long CPUFUNC(op_57f9_4)(uint32_t opcode) /* Scc */ | |
14047 | { | |
14048 | OpcodeFamily = 59; CurrentInstrCycles = 20; | |
14049 | {{ uint32_t srca = get_ilong(2); | |
14050 | { int val = cctrue(7) ? 0xff : 0; | |
14051 | m68k_write_memory_8(srca,val); | |
14052 | }}}m68k_incpc(6); | |
14053 | return 20; | |
14054 | } | |
14055 | unsigned long CPUFUNC(op_58c0_4)(uint32_t opcode) /* Scc */ | |
14056 | { | |
14057 | uint32_t srcreg = (opcode & 7); | |
14058 | OpcodeFamily = 59; CurrentInstrCycles = 4; | |
14059 | {{{ int val = cctrue(8) ? 0xff : 0; | |
14060 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); | |
14061 | if (val) { m68k_incpc(2) ; return 4+2; } | |
14062 | }}}m68k_incpc(2); | |
14063 | return 4; | |
14064 | } | |
14065 | unsigned long CPUFUNC(op_58c8_4)(uint32_t opcode) /* DBcc */ | |
14066 | { | |
14067 | uint32_t srcreg = (opcode & 7); | |
14068 | OpcodeFamily = 58; CurrentInstrCycles = 12; | |
14069 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
14070 | { int16_t offs = get_iword(2); | |
14071 | if (!cctrue(8)) { | |
14072 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); | |
14073 | if (src) { | |
14074 | m68k_incpc((int32_t)offs + 2); | |
14075 | return 10; | |
14076 | } else { | |
14077 | m68k_incpc(4); | |
14078 | return 14; | |
14079 | } | |
14080 | } | |
14081 | }}}m68k_incpc(4); | |
14082 | endlabel940: ; | |
14083 | return 12; | |
14084 | } | |
14085 | unsigned long CPUFUNC(op_58d0_4)(uint32_t opcode) /* Scc */ | |
14086 | { | |
14087 | uint32_t srcreg = (opcode & 7); | |
14088 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
14089 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
14090 | { int val = cctrue(8) ? 0xff : 0; | |
14091 | m68k_write_memory_8(srca,val); | |
14092 | }}}m68k_incpc(2); | |
14093 | return 12; | |
14094 | } | |
14095 | unsigned long CPUFUNC(op_58d8_4)(uint32_t opcode) /* Scc */ | |
14096 | { | |
14097 | uint32_t srcreg = (opcode & 7); | |
14098 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
14099 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
14100 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
14101 | { int val = cctrue(8) ? 0xff : 0; | |
14102 | m68k_write_memory_8(srca,val); | |
14103 | }}}m68k_incpc(2); | |
14104 | return 12; | |
14105 | } | |
14106 | unsigned long CPUFUNC(op_58e0_4)(uint32_t opcode) /* Scc */ | |
14107 | { | |
14108 | uint32_t srcreg = (opcode & 7); | |
14109 | OpcodeFamily = 59; CurrentInstrCycles = 14; | |
14110 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
14111 | m68k_areg (regs, srcreg) = srca; | |
14112 | { int val = cctrue(8) ? 0xff : 0; | |
14113 | m68k_write_memory_8(srca,val); | |
14114 | }}}m68k_incpc(2); | |
14115 | return 14; | |
14116 | } | |
14117 | unsigned long CPUFUNC(op_58e8_4)(uint32_t opcode) /* Scc */ | |
14118 | { | |
14119 | uint32_t srcreg = (opcode & 7); | |
14120 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
14121 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
14122 | { int val = cctrue(8) ? 0xff : 0; | |
14123 | m68k_write_memory_8(srca,val); | |
14124 | }}}m68k_incpc(4); | |
14125 | return 16; | |
14126 | } | |
14127 | unsigned long CPUFUNC(op_58f0_4)(uint32_t opcode) /* Scc */ | |
14128 | { | |
14129 | uint32_t srcreg = (opcode & 7); | |
14130 | OpcodeFamily = 59; CurrentInstrCycles = 18; | |
14131 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
14132 | BusCyclePenalty += 2; | |
14133 | { int val = cctrue(8) ? 0xff : 0; | |
14134 | m68k_write_memory_8(srca,val); | |
14135 | }}}m68k_incpc(4); | |
14136 | return 18; | |
14137 | } | |
14138 | unsigned long CPUFUNC(op_58f8_4)(uint32_t opcode) /* Scc */ | |
14139 | { | |
14140 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
14141 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
14142 | { int val = cctrue(8) ? 0xff : 0; | |
14143 | m68k_write_memory_8(srca,val); | |
14144 | }}}m68k_incpc(4); | |
14145 | return 16; | |
14146 | } | |
14147 | unsigned long CPUFUNC(op_58f9_4)(uint32_t opcode) /* Scc */ | |
14148 | { | |
14149 | OpcodeFamily = 59; CurrentInstrCycles = 20; | |
14150 | {{ uint32_t srca = get_ilong(2); | |
14151 | { int val = cctrue(8) ? 0xff : 0; | |
14152 | m68k_write_memory_8(srca,val); | |
14153 | }}}m68k_incpc(6); | |
14154 | return 20; | |
14155 | } | |
14156 | unsigned long CPUFUNC(op_59c0_4)(uint32_t opcode) /* Scc */ | |
14157 | { | |
14158 | uint32_t srcreg = (opcode & 7); | |
14159 | OpcodeFamily = 59; CurrentInstrCycles = 4; | |
14160 | {{{ int val = cctrue(9) ? 0xff : 0; | |
14161 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); | |
14162 | if (val) { m68k_incpc(2) ; return 4+2; } | |
14163 | }}}m68k_incpc(2); | |
14164 | return 4; | |
14165 | } | |
14166 | unsigned long CPUFUNC(op_59c8_4)(uint32_t opcode) /* DBcc */ | |
14167 | { | |
14168 | uint32_t srcreg = (opcode & 7); | |
14169 | OpcodeFamily = 58; CurrentInstrCycles = 12; | |
14170 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
14171 | { int16_t offs = get_iword(2); | |
14172 | if (!cctrue(9)) { | |
14173 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); | |
14174 | if (src) { | |
14175 | m68k_incpc((int32_t)offs + 2); | |
14176 | return 10; | |
14177 | } else { | |
14178 | m68k_incpc(4); | |
14179 | return 14; | |
14180 | } | |
14181 | } | |
14182 | }}}m68k_incpc(4); | |
14183 | endlabel949: ; | |
14184 | return 12; | |
14185 | } | |
14186 | unsigned long CPUFUNC(op_59d0_4)(uint32_t opcode) /* Scc */ | |
14187 | { | |
14188 | uint32_t srcreg = (opcode & 7); | |
14189 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
14190 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
14191 | { int val = cctrue(9) ? 0xff : 0; | |
14192 | m68k_write_memory_8(srca,val); | |
14193 | }}}m68k_incpc(2); | |
14194 | return 12; | |
14195 | } | |
14196 | unsigned long CPUFUNC(op_59d8_4)(uint32_t opcode) /* Scc */ | |
14197 | { | |
14198 | uint32_t srcreg = (opcode & 7); | |
14199 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
14200 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
14201 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
14202 | { int val = cctrue(9) ? 0xff : 0; | |
14203 | m68k_write_memory_8(srca,val); | |
14204 | }}}m68k_incpc(2); | |
14205 | return 12; | |
14206 | } | |
14207 | unsigned long CPUFUNC(op_59e0_4)(uint32_t opcode) /* Scc */ | |
14208 | { | |
14209 | uint32_t srcreg = (opcode & 7); | |
14210 | OpcodeFamily = 59; CurrentInstrCycles = 14; | |
14211 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
14212 | m68k_areg (regs, srcreg) = srca; | |
14213 | { int val = cctrue(9) ? 0xff : 0; | |
14214 | m68k_write_memory_8(srca,val); | |
14215 | }}}m68k_incpc(2); | |
14216 | return 14; | |
14217 | } | |
14218 | unsigned long CPUFUNC(op_59e8_4)(uint32_t opcode) /* Scc */ | |
14219 | { | |
14220 | uint32_t srcreg = (opcode & 7); | |
14221 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
14222 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
14223 | { int val = cctrue(9) ? 0xff : 0; | |
14224 | m68k_write_memory_8(srca,val); | |
14225 | }}}m68k_incpc(4); | |
14226 | return 16; | |
14227 | } | |
14228 | unsigned long CPUFUNC(op_59f0_4)(uint32_t opcode) /* Scc */ | |
14229 | { | |
14230 | uint32_t srcreg = (opcode & 7); | |
14231 | OpcodeFamily = 59; CurrentInstrCycles = 18; | |
14232 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
14233 | BusCyclePenalty += 2; | |
14234 | { int val = cctrue(9) ? 0xff : 0; | |
14235 | m68k_write_memory_8(srca,val); | |
14236 | }}}m68k_incpc(4); | |
14237 | return 18; | |
14238 | } | |
14239 | unsigned long CPUFUNC(op_59f8_4)(uint32_t opcode) /* Scc */ | |
14240 | { | |
14241 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
14242 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
14243 | { int val = cctrue(9) ? 0xff : 0; | |
14244 | m68k_write_memory_8(srca,val); | |
14245 | }}}m68k_incpc(4); | |
14246 | return 16; | |
14247 | } | |
14248 | unsigned long CPUFUNC(op_59f9_4)(uint32_t opcode) /* Scc */ | |
14249 | { | |
14250 | OpcodeFamily = 59; CurrentInstrCycles = 20; | |
14251 | {{ uint32_t srca = get_ilong(2); | |
14252 | { int val = cctrue(9) ? 0xff : 0; | |
14253 | m68k_write_memory_8(srca,val); | |
14254 | }}}m68k_incpc(6); | |
14255 | return 20; | |
14256 | } | |
14257 | unsigned long CPUFUNC(op_5ac0_4)(uint32_t opcode) /* Scc */ | |
14258 | { | |
14259 | uint32_t srcreg = (opcode & 7); | |
14260 | OpcodeFamily = 59; CurrentInstrCycles = 4; | |
14261 | {{{ int val = cctrue(10) ? 0xff : 0; | |
14262 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); | |
14263 | if (val) { m68k_incpc(2) ; return 4+2; } | |
14264 | }}}m68k_incpc(2); | |
14265 | return 4; | |
14266 | } | |
14267 | unsigned long CPUFUNC(op_5ac8_4)(uint32_t opcode) /* DBcc */ | |
14268 | { | |
14269 | uint32_t srcreg = (opcode & 7); | |
14270 | OpcodeFamily = 58; CurrentInstrCycles = 12; | |
14271 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
14272 | { int16_t offs = get_iword(2); | |
14273 | if (!cctrue(10)) { | |
14274 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); | |
14275 | if (src) { | |
14276 | m68k_incpc((int32_t)offs + 2); | |
14277 | return 10; | |
14278 | } else { | |
14279 | m68k_incpc(4); | |
14280 | return 14; | |
14281 | } | |
14282 | } | |
14283 | }}}m68k_incpc(4); | |
14284 | endlabel958: ; | |
14285 | return 12; | |
14286 | } | |
14287 | unsigned long CPUFUNC(op_5ad0_4)(uint32_t opcode) /* Scc */ | |
14288 | { | |
14289 | uint32_t srcreg = (opcode & 7); | |
14290 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
14291 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
14292 | { int val = cctrue(10) ? 0xff : 0; | |
14293 | m68k_write_memory_8(srca,val); | |
14294 | }}}m68k_incpc(2); | |
14295 | return 12; | |
14296 | } | |
14297 | unsigned long CPUFUNC(op_5ad8_4)(uint32_t opcode) /* Scc */ | |
14298 | { | |
14299 | uint32_t srcreg = (opcode & 7); | |
14300 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
14301 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
14302 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
14303 | { int val = cctrue(10) ? 0xff : 0; | |
14304 | m68k_write_memory_8(srca,val); | |
14305 | }}}m68k_incpc(2); | |
14306 | return 12; | |
14307 | } | |
14308 | unsigned long CPUFUNC(op_5ae0_4)(uint32_t opcode) /* Scc */ | |
14309 | { | |
14310 | uint32_t srcreg = (opcode & 7); | |
14311 | OpcodeFamily = 59; CurrentInstrCycles = 14; | |
14312 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
14313 | m68k_areg (regs, srcreg) = srca; | |
14314 | { int val = cctrue(10) ? 0xff : 0; | |
14315 | m68k_write_memory_8(srca,val); | |
14316 | }}}m68k_incpc(2); | |
14317 | return 14; | |
14318 | } | |
14319 | unsigned long CPUFUNC(op_5ae8_4)(uint32_t opcode) /* Scc */ | |
14320 | { | |
14321 | uint32_t srcreg = (opcode & 7); | |
14322 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
14323 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
14324 | { int val = cctrue(10) ? 0xff : 0; | |
14325 | m68k_write_memory_8(srca,val); | |
14326 | }}}m68k_incpc(4); | |
14327 | return 16; | |
14328 | } | |
14329 | unsigned long CPUFUNC(op_5af0_4)(uint32_t opcode) /* Scc */ | |
14330 | { | |
14331 | uint32_t srcreg = (opcode & 7); | |
14332 | OpcodeFamily = 59; CurrentInstrCycles = 18; | |
14333 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
14334 | BusCyclePenalty += 2; | |
14335 | { int val = cctrue(10) ? 0xff : 0; | |
14336 | m68k_write_memory_8(srca,val); | |
14337 | }}}m68k_incpc(4); | |
14338 | return 18; | |
14339 | } | |
14340 | unsigned long CPUFUNC(op_5af8_4)(uint32_t opcode) /* Scc */ | |
14341 | { | |
14342 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
14343 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
14344 | { int val = cctrue(10) ? 0xff : 0; | |
14345 | m68k_write_memory_8(srca,val); | |
14346 | }}}m68k_incpc(4); | |
14347 | return 16; | |
14348 | } | |
14349 | unsigned long CPUFUNC(op_5af9_4)(uint32_t opcode) /* Scc */ | |
14350 | { | |
14351 | OpcodeFamily = 59; CurrentInstrCycles = 20; | |
14352 | {{ uint32_t srca = get_ilong(2); | |
14353 | { int val = cctrue(10) ? 0xff : 0; | |
14354 | m68k_write_memory_8(srca,val); | |
14355 | }}}m68k_incpc(6); | |
14356 | return 20; | |
14357 | } | |
14358 | unsigned long CPUFUNC(op_5bc0_4)(uint32_t opcode) /* Scc */ | |
14359 | { | |
14360 | uint32_t srcreg = (opcode & 7); | |
14361 | OpcodeFamily = 59; CurrentInstrCycles = 4; | |
14362 | {{{ int val = cctrue(11) ? 0xff : 0; | |
14363 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); | |
14364 | if (val) { m68k_incpc(2) ; return 4+2; } | |
14365 | }}}m68k_incpc(2); | |
14366 | return 4; | |
14367 | } | |
14368 | unsigned long CPUFUNC(op_5bc8_4)(uint32_t opcode) /* DBcc */ | |
14369 | { | |
14370 | uint32_t srcreg = (opcode & 7); | |
14371 | OpcodeFamily = 58; CurrentInstrCycles = 12; | |
14372 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
14373 | { int16_t offs = get_iword(2); | |
14374 | if (!cctrue(11)) { | |
14375 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); | |
14376 | if (src) { | |
14377 | m68k_incpc((int32_t)offs + 2); | |
14378 | return 10; | |
14379 | } else { | |
14380 | m68k_incpc(4); | |
14381 | return 14; | |
14382 | } | |
14383 | } | |
14384 | }}}m68k_incpc(4); | |
14385 | endlabel967: ; | |
14386 | return 12; | |
14387 | } | |
14388 | unsigned long CPUFUNC(op_5bd0_4)(uint32_t opcode) /* Scc */ | |
14389 | { | |
14390 | uint32_t srcreg = (opcode & 7); | |
14391 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
14392 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
14393 | { int val = cctrue(11) ? 0xff : 0; | |
14394 | m68k_write_memory_8(srca,val); | |
14395 | }}}m68k_incpc(2); | |
14396 | return 12; | |
14397 | } | |
14398 | unsigned long CPUFUNC(op_5bd8_4)(uint32_t opcode) /* Scc */ | |
14399 | { | |
14400 | uint32_t srcreg = (opcode & 7); | |
14401 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
14402 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
14403 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
14404 | { int val = cctrue(11) ? 0xff : 0; | |
14405 | m68k_write_memory_8(srca,val); | |
14406 | }}}m68k_incpc(2); | |
14407 | return 12; | |
14408 | } | |
14409 | unsigned long CPUFUNC(op_5be0_4)(uint32_t opcode) /* Scc */ | |
14410 | { | |
14411 | uint32_t srcreg = (opcode & 7); | |
14412 | OpcodeFamily = 59; CurrentInstrCycles = 14; | |
14413 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
14414 | m68k_areg (regs, srcreg) = srca; | |
14415 | { int val = cctrue(11) ? 0xff : 0; | |
14416 | m68k_write_memory_8(srca,val); | |
14417 | }}}m68k_incpc(2); | |
14418 | return 14; | |
14419 | } | |
14420 | unsigned long CPUFUNC(op_5be8_4)(uint32_t opcode) /* Scc */ | |
14421 | { | |
14422 | uint32_t srcreg = (opcode & 7); | |
14423 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
14424 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
14425 | { int val = cctrue(11) ? 0xff : 0; | |
14426 | m68k_write_memory_8(srca,val); | |
14427 | }}}m68k_incpc(4); | |
14428 | return 16; | |
14429 | } | |
14430 | unsigned long CPUFUNC(op_5bf0_4)(uint32_t opcode) /* Scc */ | |
14431 | { | |
14432 | uint32_t srcreg = (opcode & 7); | |
14433 | OpcodeFamily = 59; CurrentInstrCycles = 18; | |
14434 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
14435 | BusCyclePenalty += 2; | |
14436 | { int val = cctrue(11) ? 0xff : 0; | |
14437 | m68k_write_memory_8(srca,val); | |
14438 | }}}m68k_incpc(4); | |
14439 | return 18; | |
14440 | } | |
14441 | unsigned long CPUFUNC(op_5bf8_4)(uint32_t opcode) /* Scc */ | |
14442 | { | |
14443 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
14444 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
14445 | { int val = cctrue(11) ? 0xff : 0; | |
14446 | m68k_write_memory_8(srca,val); | |
14447 | }}}m68k_incpc(4); | |
14448 | return 16; | |
14449 | } | |
14450 | unsigned long CPUFUNC(op_5bf9_4)(uint32_t opcode) /* Scc */ | |
14451 | { | |
14452 | OpcodeFamily = 59; CurrentInstrCycles = 20; | |
14453 | {{ uint32_t srca = get_ilong(2); | |
14454 | { int val = cctrue(11) ? 0xff : 0; | |
14455 | m68k_write_memory_8(srca,val); | |
14456 | }}}m68k_incpc(6); | |
14457 | return 20; | |
14458 | } | |
14459 | unsigned long CPUFUNC(op_5cc0_4)(uint32_t opcode) /* Scc */ | |
14460 | { | |
14461 | uint32_t srcreg = (opcode & 7); | |
14462 | OpcodeFamily = 59; CurrentInstrCycles = 4; | |
14463 | {{{ int val = cctrue(12) ? 0xff : 0; | |
14464 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); | |
14465 | if (val) { m68k_incpc(2) ; return 4+2; } | |
14466 | }}}m68k_incpc(2); | |
14467 | return 4; | |
14468 | } | |
14469 | unsigned long CPUFUNC(op_5cc8_4)(uint32_t opcode) /* DBcc */ | |
14470 | { | |
14471 | uint32_t srcreg = (opcode & 7); | |
14472 | OpcodeFamily = 58; CurrentInstrCycles = 12; | |
14473 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
14474 | { int16_t offs = get_iword(2); | |
14475 | if (!cctrue(12)) { | |
14476 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); | |
14477 | if (src) { | |
14478 | m68k_incpc((int32_t)offs + 2); | |
14479 | return 10; | |
14480 | } else { | |
14481 | m68k_incpc(4); | |
14482 | return 14; | |
14483 | } | |
14484 | } | |
14485 | }}}m68k_incpc(4); | |
14486 | endlabel976: ; | |
14487 | return 12; | |
14488 | } | |
14489 | unsigned long CPUFUNC(op_5cd0_4)(uint32_t opcode) /* Scc */ | |
14490 | { | |
14491 | uint32_t srcreg = (opcode & 7); | |
14492 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
14493 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
14494 | { int val = cctrue(12) ? 0xff : 0; | |
14495 | m68k_write_memory_8(srca,val); | |
14496 | }}}m68k_incpc(2); | |
14497 | return 12; | |
14498 | } | |
14499 | unsigned long CPUFUNC(op_5cd8_4)(uint32_t opcode) /* Scc */ | |
14500 | { | |
14501 | uint32_t srcreg = (opcode & 7); | |
14502 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
14503 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
14504 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
14505 | { int val = cctrue(12) ? 0xff : 0; | |
14506 | m68k_write_memory_8(srca,val); | |
14507 | }}}m68k_incpc(2); | |
14508 | return 12; | |
14509 | } | |
14510 | unsigned long CPUFUNC(op_5ce0_4)(uint32_t opcode) /* Scc */ | |
14511 | { | |
14512 | uint32_t srcreg = (opcode & 7); | |
14513 | OpcodeFamily = 59; CurrentInstrCycles = 14; | |
14514 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
14515 | m68k_areg (regs, srcreg) = srca; | |
14516 | { int val = cctrue(12) ? 0xff : 0; | |
14517 | m68k_write_memory_8(srca,val); | |
14518 | }}}m68k_incpc(2); | |
14519 | return 14; | |
14520 | } | |
14521 | unsigned long CPUFUNC(op_5ce8_4)(uint32_t opcode) /* Scc */ | |
14522 | { | |
14523 | uint32_t srcreg = (opcode & 7); | |
14524 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
14525 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
14526 | { int val = cctrue(12) ? 0xff : 0; | |
14527 | m68k_write_memory_8(srca,val); | |
14528 | }}}m68k_incpc(4); | |
14529 | return 16; | |
14530 | } | |
14531 | unsigned long CPUFUNC(op_5cf0_4)(uint32_t opcode) /* Scc */ | |
14532 | { | |
14533 | uint32_t srcreg = (opcode & 7); | |
14534 | OpcodeFamily = 59; CurrentInstrCycles = 18; | |
14535 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
14536 | BusCyclePenalty += 2; | |
14537 | { int val = cctrue(12) ? 0xff : 0; | |
14538 | m68k_write_memory_8(srca,val); | |
14539 | }}}m68k_incpc(4); | |
14540 | return 18; | |
14541 | } | |
14542 | unsigned long CPUFUNC(op_5cf8_4)(uint32_t opcode) /* Scc */ | |
14543 | { | |
14544 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
14545 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
14546 | { int val = cctrue(12) ? 0xff : 0; | |
14547 | m68k_write_memory_8(srca,val); | |
14548 | }}}m68k_incpc(4); | |
14549 | return 16; | |
14550 | } | |
14551 | unsigned long CPUFUNC(op_5cf9_4)(uint32_t opcode) /* Scc */ | |
14552 | { | |
14553 | OpcodeFamily = 59; CurrentInstrCycles = 20; | |
14554 | {{ uint32_t srca = get_ilong(2); | |
14555 | { int val = cctrue(12) ? 0xff : 0; | |
14556 | m68k_write_memory_8(srca,val); | |
14557 | }}}m68k_incpc(6); | |
14558 | return 20; | |
14559 | } | |
14560 | unsigned long CPUFUNC(op_5dc0_4)(uint32_t opcode) /* Scc */ | |
14561 | { | |
14562 | uint32_t srcreg = (opcode & 7); | |
14563 | OpcodeFamily = 59; CurrentInstrCycles = 4; | |
14564 | {{{ int val = cctrue(13) ? 0xff : 0; | |
14565 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); | |
14566 | if (val) { m68k_incpc(2) ; return 4+2; } | |
14567 | }}}m68k_incpc(2); | |
14568 | return 4; | |
14569 | } | |
14570 | unsigned long CPUFUNC(op_5dc8_4)(uint32_t opcode) /* DBcc */ | |
14571 | { | |
14572 | uint32_t srcreg = (opcode & 7); | |
14573 | OpcodeFamily = 58; CurrentInstrCycles = 12; | |
14574 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
14575 | { int16_t offs = get_iword(2); | |
14576 | if (!cctrue(13)) { | |
14577 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); | |
14578 | if (src) { | |
14579 | m68k_incpc((int32_t)offs + 2); | |
14580 | return 10; | |
14581 | } else { | |
14582 | m68k_incpc(4); | |
14583 | return 14; | |
14584 | } | |
14585 | } | |
14586 | }}}m68k_incpc(4); | |
14587 | endlabel985: ; | |
14588 | return 12; | |
14589 | } | |
14590 | unsigned long CPUFUNC(op_5dd0_4)(uint32_t opcode) /* Scc */ | |
14591 | { | |
14592 | uint32_t srcreg = (opcode & 7); | |
14593 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
14594 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
14595 | { int val = cctrue(13) ? 0xff : 0; | |
14596 | m68k_write_memory_8(srca,val); | |
14597 | }}}m68k_incpc(2); | |
14598 | return 12; | |
14599 | } | |
14600 | unsigned long CPUFUNC(op_5dd8_4)(uint32_t opcode) /* Scc */ | |
14601 | { | |
14602 | uint32_t srcreg = (opcode & 7); | |
14603 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
14604 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
14605 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
14606 | { int val = cctrue(13) ? 0xff : 0; | |
14607 | m68k_write_memory_8(srca,val); | |
14608 | }}}m68k_incpc(2); | |
14609 | return 12; | |
14610 | } | |
14611 | unsigned long CPUFUNC(op_5de0_4)(uint32_t opcode) /* Scc */ | |
14612 | { | |
14613 | uint32_t srcreg = (opcode & 7); | |
14614 | OpcodeFamily = 59; CurrentInstrCycles = 14; | |
14615 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
14616 | m68k_areg (regs, srcreg) = srca; | |
14617 | { int val = cctrue(13) ? 0xff : 0; | |
14618 | m68k_write_memory_8(srca,val); | |
14619 | }}}m68k_incpc(2); | |
14620 | return 14; | |
14621 | } | |
14622 | unsigned long CPUFUNC(op_5de8_4)(uint32_t opcode) /* Scc */ | |
14623 | { | |
14624 | uint32_t srcreg = (opcode & 7); | |
14625 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
14626 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
14627 | { int val = cctrue(13) ? 0xff : 0; | |
14628 | m68k_write_memory_8(srca,val); | |
14629 | }}}m68k_incpc(4); | |
14630 | return 16; | |
14631 | } | |
14632 | unsigned long CPUFUNC(op_5df0_4)(uint32_t opcode) /* Scc */ | |
14633 | { | |
14634 | uint32_t srcreg = (opcode & 7); | |
14635 | OpcodeFamily = 59; CurrentInstrCycles = 18; | |
14636 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
14637 | BusCyclePenalty += 2; | |
14638 | { int val = cctrue(13) ? 0xff : 0; | |
14639 | m68k_write_memory_8(srca,val); | |
14640 | }}}m68k_incpc(4); | |
14641 | return 18; | |
14642 | } | |
14643 | unsigned long CPUFUNC(op_5df8_4)(uint32_t opcode) /* Scc */ | |
14644 | { | |
14645 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
14646 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
14647 | { int val = cctrue(13) ? 0xff : 0; | |
14648 | m68k_write_memory_8(srca,val); | |
14649 | }}}m68k_incpc(4); | |
14650 | return 16; | |
14651 | } | |
14652 | unsigned long CPUFUNC(op_5df9_4)(uint32_t opcode) /* Scc */ | |
14653 | { | |
14654 | OpcodeFamily = 59; CurrentInstrCycles = 20; | |
14655 | {{ uint32_t srca = get_ilong(2); | |
14656 | { int val = cctrue(13) ? 0xff : 0; | |
14657 | m68k_write_memory_8(srca,val); | |
14658 | }}}m68k_incpc(6); | |
14659 | return 20; | |
14660 | } | |
14661 | unsigned long CPUFUNC(op_5ec0_4)(uint32_t opcode) /* Scc */ | |
14662 | { | |
14663 | uint32_t srcreg = (opcode & 7); | |
14664 | OpcodeFamily = 59; CurrentInstrCycles = 4; | |
14665 | {{{ int val = cctrue(14) ? 0xff : 0; | |
14666 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); | |
14667 | if (val) { m68k_incpc(2) ; return 4+2; } | |
14668 | }}}m68k_incpc(2); | |
14669 | return 4; | |
14670 | } | |
14671 | unsigned long CPUFUNC(op_5ec8_4)(uint32_t opcode) /* DBcc */ | |
14672 | { | |
14673 | uint32_t srcreg = (opcode & 7); | |
14674 | OpcodeFamily = 58; CurrentInstrCycles = 12; | |
14675 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
14676 | { int16_t offs = get_iword(2); | |
14677 | if (!cctrue(14)) { | |
14678 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); | |
14679 | if (src) { | |
14680 | m68k_incpc((int32_t)offs + 2); | |
14681 | return 10; | |
14682 | } else { | |
14683 | m68k_incpc(4); | |
14684 | return 14; | |
14685 | } | |
14686 | } | |
14687 | }}}m68k_incpc(4); | |
14688 | endlabel994: ; | |
14689 | return 12; | |
14690 | } | |
14691 | unsigned long CPUFUNC(op_5ed0_4)(uint32_t opcode) /* Scc */ | |
14692 | { | |
14693 | uint32_t srcreg = (opcode & 7); | |
14694 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
14695 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
14696 | { int val = cctrue(14) ? 0xff : 0; | |
14697 | m68k_write_memory_8(srca,val); | |
14698 | }}}m68k_incpc(2); | |
14699 | return 12; | |
14700 | } | |
14701 | unsigned long CPUFUNC(op_5ed8_4)(uint32_t opcode) /* Scc */ | |
14702 | { | |
14703 | uint32_t srcreg = (opcode & 7); | |
14704 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
14705 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
14706 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
14707 | { int val = cctrue(14) ? 0xff : 0; | |
14708 | m68k_write_memory_8(srca,val); | |
14709 | }}}m68k_incpc(2); | |
14710 | return 12; | |
14711 | } | |
14712 | unsigned long CPUFUNC(op_5ee0_4)(uint32_t opcode) /* Scc */ | |
14713 | { | |
14714 | uint32_t srcreg = (opcode & 7); | |
14715 | OpcodeFamily = 59; CurrentInstrCycles = 14; | |
14716 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
14717 | m68k_areg (regs, srcreg) = srca; | |
14718 | { int val = cctrue(14) ? 0xff : 0; | |
14719 | m68k_write_memory_8(srca,val); | |
14720 | }}}m68k_incpc(2); | |
14721 | return 14; | |
14722 | } | |
14723 | unsigned long CPUFUNC(op_5ee8_4)(uint32_t opcode) /* Scc */ | |
14724 | { | |
14725 | uint32_t srcreg = (opcode & 7); | |
14726 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
14727 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
14728 | { int val = cctrue(14) ? 0xff : 0; | |
14729 | m68k_write_memory_8(srca,val); | |
14730 | }}}m68k_incpc(4); | |
14731 | return 16; | |
14732 | } | |
14733 | unsigned long CPUFUNC(op_5ef0_4)(uint32_t opcode) /* Scc */ | |
14734 | { | |
14735 | uint32_t srcreg = (opcode & 7); | |
14736 | OpcodeFamily = 59; CurrentInstrCycles = 18; | |
14737 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
14738 | BusCyclePenalty += 2; | |
14739 | { int val = cctrue(14) ? 0xff : 0; | |
14740 | m68k_write_memory_8(srca,val); | |
14741 | }}}m68k_incpc(4); | |
14742 | return 18; | |
14743 | } | |
14744 | unsigned long CPUFUNC(op_5ef8_4)(uint32_t opcode) /* Scc */ | |
14745 | { | |
14746 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
14747 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
14748 | { int val = cctrue(14) ? 0xff : 0; | |
14749 | m68k_write_memory_8(srca,val); | |
14750 | }}}m68k_incpc(4); | |
14751 | return 16; | |
14752 | } | |
14753 | unsigned long CPUFUNC(op_5ef9_4)(uint32_t opcode) /* Scc */ | |
14754 | { | |
14755 | OpcodeFamily = 59; CurrentInstrCycles = 20; | |
14756 | {{ uint32_t srca = get_ilong(2); | |
14757 | { int val = cctrue(14) ? 0xff : 0; | |
14758 | m68k_write_memory_8(srca,val); | |
14759 | }}}m68k_incpc(6); | |
14760 | return 20; | |
14761 | } | |
14762 | unsigned long CPUFUNC(op_5fc0_4)(uint32_t opcode) /* Scc */ | |
14763 | { | |
14764 | uint32_t srcreg = (opcode & 7); | |
14765 | OpcodeFamily = 59; CurrentInstrCycles = 4; | |
14766 | {{{ int val = cctrue(15) ? 0xff : 0; | |
14767 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); | |
14768 | if (val) { m68k_incpc(2) ; return 4+2; } | |
14769 | }}}m68k_incpc(2); | |
14770 | return 4; | |
14771 | } | |
14772 | unsigned long CPUFUNC(op_5fc8_4)(uint32_t opcode) /* DBcc */ | |
14773 | { | |
14774 | uint32_t srcreg = (opcode & 7); | |
14775 | OpcodeFamily = 58; CurrentInstrCycles = 12; | |
14776 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
14777 | { int16_t offs = get_iword(2); | |
14778 | if (!cctrue(15)) { | |
14779 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); | |
14780 | if (src) { | |
14781 | m68k_incpc((int32_t)offs + 2); | |
14782 | return 10; | |
14783 | } else { | |
14784 | m68k_incpc(4); | |
14785 | return 14; | |
14786 | } | |
14787 | } | |
14788 | }}}m68k_incpc(4); | |
14789 | endlabel1003: ; | |
14790 | return 12; | |
14791 | } | |
14792 | unsigned long CPUFUNC(op_5fd0_4)(uint32_t opcode) /* Scc */ | |
14793 | { | |
14794 | uint32_t srcreg = (opcode & 7); | |
14795 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
14796 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
14797 | { int val = cctrue(15) ? 0xff : 0; | |
14798 | m68k_write_memory_8(srca,val); | |
14799 | }}}m68k_incpc(2); | |
14800 | return 12; | |
14801 | } | |
14802 | unsigned long CPUFUNC(op_5fd8_4)(uint32_t opcode) /* Scc */ | |
14803 | { | |
14804 | uint32_t srcreg = (opcode & 7); | |
14805 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
14806 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
14807 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
14808 | { int val = cctrue(15) ? 0xff : 0; | |
14809 | m68k_write_memory_8(srca,val); | |
14810 | }}}m68k_incpc(2); | |
14811 | return 12; | |
14812 | } | |
14813 | unsigned long CPUFUNC(op_5fe0_4)(uint32_t opcode) /* Scc */ | |
14814 | { | |
14815 | uint32_t srcreg = (opcode & 7); | |
14816 | OpcodeFamily = 59; CurrentInstrCycles = 14; | |
14817 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
14818 | m68k_areg (regs, srcreg) = srca; | |
14819 | { int val = cctrue(15) ? 0xff : 0; | |
14820 | m68k_write_memory_8(srca,val); | |
14821 | }}}m68k_incpc(2); | |
14822 | return 14; | |
14823 | } | |
14824 | #endif | |
14825 | ||
14826 | #ifdef PART_6 | |
14827 | unsigned long CPUFUNC(op_5fe8_4)(uint32_t opcode) /* Scc */ | |
14828 | { | |
14829 | uint32_t srcreg = (opcode & 7); | |
14830 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
14831 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
14832 | { int val = cctrue(15) ? 0xff : 0; | |
14833 | m68k_write_memory_8(srca,val); | |
14834 | }}}m68k_incpc(4); | |
14835 | return 16; | |
14836 | } | |
14837 | unsigned long CPUFUNC(op_5ff0_4)(uint32_t opcode) /* Scc */ | |
14838 | { | |
14839 | uint32_t srcreg = (opcode & 7); | |
14840 | OpcodeFamily = 59; CurrentInstrCycles = 18; | |
14841 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
14842 | BusCyclePenalty += 2; | |
14843 | { int val = cctrue(15) ? 0xff : 0; | |
14844 | m68k_write_memory_8(srca,val); | |
14845 | }}}m68k_incpc(4); | |
14846 | return 18; | |
14847 | } | |
14848 | unsigned long CPUFUNC(op_5ff8_4)(uint32_t opcode) /* Scc */ | |
14849 | { | |
14850 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
14851 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
14852 | { int val = cctrue(15) ? 0xff : 0; | |
14853 | m68k_write_memory_8(srca,val); | |
14854 | }}}m68k_incpc(4); | |
14855 | return 16; | |
14856 | } | |
14857 | unsigned long CPUFUNC(op_5ff9_4)(uint32_t opcode) /* Scc */ | |
14858 | { | |
14859 | OpcodeFamily = 59; CurrentInstrCycles = 20; | |
14860 | {{ uint32_t srca = get_ilong(2); | |
14861 | { int val = cctrue(15) ? 0xff : 0; | |
14862 | m68k_write_memory_8(srca,val); | |
14863 | }}}m68k_incpc(6); | |
14864 | return 20; | |
14865 | } | |
14866 | unsigned long CPUFUNC(op_6000_4)(uint32_t opcode) /* Bcc */ | |
14867 | { | |
14868 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
14869 | {{ int16_t src = get_iword(2); | |
14870 | if (!cctrue(0)) goto didnt_jump; | |
14871 | m68k_incpc ((int32_t)src + 2); | |
14872 | return 10; | |
14873 | didnt_jump:; | |
14874 | }}m68k_incpc(4); | |
14875 | endlabel1011: ; | |
14876 | return 12; | |
14877 | } | |
14878 | unsigned long CPUFUNC(op_6001_4)(uint32_t opcode) /* Bcc */ | |
14879 | { | |
14880 | uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); | |
14881 | OpcodeFamily = 55; CurrentInstrCycles = 8; | |
14882 | {{ uint32_t src = srcreg; | |
14883 | if (!cctrue(0)) goto didnt_jump; | |
14884 | m68k_incpc ((int32_t)src + 2); | |
14885 | return 10; | |
14886 | didnt_jump:; | |
14887 | }}m68k_incpc(2); | |
14888 | endlabel1012: ; | |
14889 | return 8; | |
14890 | } | |
14891 | unsigned long CPUFUNC(op_60ff_4)(uint32_t opcode) /* Bcc */ | |
14892 | { | |
14893 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
14894 | { m68k_incpc(2); | |
14895 | if (!cctrue(0)) goto endlabel1013; | |
14896 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
14897 | last_fault_for_exception_3 = m68k_getpc() + 1; | |
14898 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel1013; | |
14899 | { int32_t src = get_ilong(2); | |
14900 | if (!cctrue(0)) goto didnt_jump; | |
14901 | m68k_incpc ((int32_t)src + 2); | |
14902 | return 10; | |
14903 | didnt_jump:; | |
14904 | }}m68k_incpc(6); | |
14905 | endlabel1013: ; | |
14906 | return 12; | |
14907 | } | |
14908 | unsigned long CPUFUNC(op_6100_4)(uint32_t opcode) /* BSR */ | |
14909 | { | |
14910 | OpcodeFamily = 54; CurrentInstrCycles = 18; | |
14911 | {{ int16_t src = get_iword(2); | |
14912 | int32_t s = (int32_t)src + 2; | |
14913 | m68k_do_bsr(m68k_getpc() + 4, s); | |
14914 | }}return 18; | |
14915 | } | |
14916 | unsigned long CPUFUNC(op_6101_4)(uint32_t opcode) /* BSR */ | |
14917 | { | |
14918 | uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); | |
14919 | OpcodeFamily = 54; CurrentInstrCycles = 18; | |
14920 | {{ uint32_t src = srcreg; | |
14921 | int32_t s = (int32_t)src + 2; | |
14922 | m68k_do_bsr(m68k_getpc() + 2, s); | |
14923 | }}return 18; | |
14924 | } | |
14925 | unsigned long CPUFUNC(op_61ff_4)(uint32_t opcode) /* BSR */ | |
14926 | { | |
14927 | OpcodeFamily = 54; CurrentInstrCycles = 18; | |
14928 | {{ int32_t src = get_ilong(2); | |
14929 | int32_t s = (int32_t)src + 2; | |
14930 | m68k_do_bsr(m68k_getpc() + 6, s); | |
14931 | }}return 18; | |
14932 | } | |
14933 | unsigned long CPUFUNC(op_6200_4)(uint32_t opcode) /* Bcc */ | |
14934 | { | |
14935 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
14936 | {{ int16_t src = get_iword(2); | |
14937 | if (!cctrue(2)) goto didnt_jump; | |
14938 | m68k_incpc ((int32_t)src + 2); | |
14939 | return 10; | |
14940 | didnt_jump:; | |
14941 | }}m68k_incpc(4); | |
14942 | endlabel1017: ; | |
14943 | return 12; | |
14944 | } | |
14945 | unsigned long CPUFUNC(op_6201_4)(uint32_t opcode) /* Bcc */ | |
14946 | { | |
14947 | uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); | |
14948 | OpcodeFamily = 55; CurrentInstrCycles = 8; | |
14949 | {{ uint32_t src = srcreg; | |
14950 | if (!cctrue(2)) goto didnt_jump; | |
14951 | m68k_incpc ((int32_t)src + 2); | |
14952 | return 10; | |
14953 | didnt_jump:; | |
14954 | }}m68k_incpc(2); | |
14955 | endlabel1018: ; | |
14956 | return 8; | |
14957 | } | |
14958 | unsigned long CPUFUNC(op_62ff_4)(uint32_t opcode) /* Bcc */ | |
14959 | { | |
14960 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
14961 | { m68k_incpc(2); | |
14962 | if (!cctrue(2)) goto endlabel1019; | |
14963 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
14964 | last_fault_for_exception_3 = m68k_getpc() + 1; | |
14965 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel1019; | |
14966 | { int32_t src = get_ilong(2); | |
14967 | if (!cctrue(2)) goto didnt_jump; | |
14968 | m68k_incpc ((int32_t)src + 2); | |
14969 | return 10; | |
14970 | didnt_jump:; | |
14971 | }}m68k_incpc(6); | |
14972 | endlabel1019: ; | |
14973 | return 12; | |
14974 | } | |
14975 | unsigned long CPUFUNC(op_6300_4)(uint32_t opcode) /* Bcc */ | |
14976 | { | |
14977 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
14978 | {{ int16_t src = get_iword(2); | |
14979 | if (!cctrue(3)) goto didnt_jump; | |
14980 | m68k_incpc ((int32_t)src + 2); | |
14981 | return 10; | |
14982 | didnt_jump:; | |
14983 | }}m68k_incpc(4); | |
14984 | endlabel1020: ; | |
14985 | return 12; | |
14986 | } | |
14987 | unsigned long CPUFUNC(op_6301_4)(uint32_t opcode) /* Bcc */ | |
14988 | { | |
14989 | uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); | |
14990 | OpcodeFamily = 55; CurrentInstrCycles = 8; | |
14991 | {{ uint32_t src = srcreg; | |
14992 | if (!cctrue(3)) goto didnt_jump; | |
14993 | m68k_incpc ((int32_t)src + 2); | |
14994 | return 10; | |
14995 | didnt_jump:; | |
14996 | }}m68k_incpc(2); | |
14997 | endlabel1021: ; | |
14998 | return 8; | |
14999 | } | |
15000 | unsigned long CPUFUNC(op_63ff_4)(uint32_t opcode) /* Bcc */ | |
15001 | { | |
15002 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
15003 | { m68k_incpc(2); | |
15004 | if (!cctrue(3)) goto endlabel1022; | |
15005 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
15006 | last_fault_for_exception_3 = m68k_getpc() + 1; | |
15007 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel1022; | |
15008 | { int32_t src = get_ilong(2); | |
15009 | if (!cctrue(3)) goto didnt_jump; | |
15010 | m68k_incpc ((int32_t)src + 2); | |
15011 | return 10; | |
15012 | didnt_jump:; | |
15013 | }}m68k_incpc(6); | |
15014 | endlabel1022: ; | |
15015 | return 12; | |
15016 | } | |
15017 | unsigned long CPUFUNC(op_6400_4)(uint32_t opcode) /* Bcc */ | |
15018 | { | |
15019 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
15020 | {{ int16_t src = get_iword(2); | |
15021 | if (!cctrue(4)) goto didnt_jump; | |
15022 | m68k_incpc ((int32_t)src + 2); | |
15023 | return 10; | |
15024 | didnt_jump:; | |
15025 | }}m68k_incpc(4); | |
15026 | endlabel1023: ; | |
15027 | return 12; | |
15028 | } | |
15029 | unsigned long CPUFUNC(op_6401_4)(uint32_t opcode) /* Bcc */ | |
15030 | { | |
15031 | uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); | |
15032 | OpcodeFamily = 55; CurrentInstrCycles = 8; | |
15033 | {{ uint32_t src = srcreg; | |
15034 | if (!cctrue(4)) goto didnt_jump; | |
15035 | m68k_incpc ((int32_t)src + 2); | |
15036 | return 10; | |
15037 | didnt_jump:; | |
15038 | }}m68k_incpc(2); | |
15039 | endlabel1024: ; | |
15040 | return 8; | |
15041 | } | |
15042 | unsigned long CPUFUNC(op_64ff_4)(uint32_t opcode) /* Bcc */ | |
15043 | { | |
15044 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
15045 | { m68k_incpc(2); | |
15046 | if (!cctrue(4)) goto endlabel1025; | |
15047 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
15048 | last_fault_for_exception_3 = m68k_getpc() + 1; | |
15049 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel1025; | |
15050 | { int32_t src = get_ilong(2); | |
15051 | if (!cctrue(4)) goto didnt_jump; | |
15052 | m68k_incpc ((int32_t)src + 2); | |
15053 | return 10; | |
15054 | didnt_jump:; | |
15055 | }}m68k_incpc(6); | |
15056 | endlabel1025: ; | |
15057 | return 12; | |
15058 | } | |
15059 | unsigned long CPUFUNC(op_6500_4)(uint32_t opcode) /* Bcc */ | |
15060 | { | |
15061 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
15062 | {{ int16_t src = get_iword(2); | |
15063 | if (!cctrue(5)) goto didnt_jump; | |
15064 | m68k_incpc ((int32_t)src + 2); | |
15065 | return 10; | |
15066 | didnt_jump:; | |
15067 | }}m68k_incpc(4); | |
15068 | endlabel1026: ; | |
15069 | return 12; | |
15070 | } | |
15071 | unsigned long CPUFUNC(op_6501_4)(uint32_t opcode) /* Bcc */ | |
15072 | { | |
15073 | uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); | |
15074 | OpcodeFamily = 55; CurrentInstrCycles = 8; | |
15075 | {{ uint32_t src = srcreg; | |
15076 | if (!cctrue(5)) goto didnt_jump; | |
15077 | m68k_incpc ((int32_t)src + 2); | |
15078 | return 10; | |
15079 | didnt_jump:; | |
15080 | }}m68k_incpc(2); | |
15081 | endlabel1027: ; | |
15082 | return 8; | |
15083 | } | |
15084 | unsigned long CPUFUNC(op_65ff_4)(uint32_t opcode) /* Bcc */ | |
15085 | { | |
15086 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
15087 | { m68k_incpc(2); | |
15088 | if (!cctrue(5)) goto endlabel1028; | |
15089 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
15090 | last_fault_for_exception_3 = m68k_getpc() + 1; | |
15091 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel1028; | |
15092 | { int32_t src = get_ilong(2); | |
15093 | if (!cctrue(5)) goto didnt_jump; | |
15094 | m68k_incpc ((int32_t)src + 2); | |
15095 | return 10; | |
15096 | didnt_jump:; | |
15097 | }}m68k_incpc(6); | |
15098 | endlabel1028: ; | |
15099 | return 12; | |
15100 | } | |
15101 | unsigned long CPUFUNC(op_6600_4)(uint32_t opcode) /* Bcc */ | |
15102 | { | |
15103 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
15104 | {{ int16_t src = get_iword(2); | |
15105 | if (!cctrue(6)) goto didnt_jump; | |
15106 | m68k_incpc ((int32_t)src + 2); | |
15107 | return 10; | |
15108 | didnt_jump:; | |
15109 | }}m68k_incpc(4); | |
15110 | endlabel1029: ; | |
15111 | return 12; | |
15112 | } | |
15113 | unsigned long CPUFUNC(op_6601_4)(uint32_t opcode) /* Bcc */ | |
15114 | { | |
15115 | uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); | |
15116 | OpcodeFamily = 55; CurrentInstrCycles = 8; | |
15117 | {{ uint32_t src = srcreg; | |
15118 | if (!cctrue(6)) goto didnt_jump; | |
15119 | m68k_incpc ((int32_t)src + 2); | |
15120 | return 10; | |
15121 | didnt_jump:; | |
15122 | }}m68k_incpc(2); | |
15123 | endlabel1030: ; | |
15124 | return 8; | |
15125 | } | |
15126 | unsigned long CPUFUNC(op_66ff_4)(uint32_t opcode) /* Bcc */ | |
15127 | { | |
15128 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
15129 | { m68k_incpc(2); | |
15130 | if (!cctrue(6)) goto endlabel1031; | |
15131 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
15132 | last_fault_for_exception_3 = m68k_getpc() + 1; | |
15133 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel1031; | |
15134 | { int32_t src = get_ilong(2); | |
15135 | if (!cctrue(6)) goto didnt_jump; | |
15136 | m68k_incpc ((int32_t)src + 2); | |
15137 | return 10; | |
15138 | didnt_jump:; | |
15139 | }}m68k_incpc(6); | |
15140 | endlabel1031: ; | |
15141 | return 12; | |
15142 | } | |
15143 | unsigned long CPUFUNC(op_6700_4)(uint32_t opcode) /* Bcc */ | |
15144 | { | |
15145 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
15146 | {{ int16_t src = get_iword(2); | |
15147 | if (!cctrue(7)) goto didnt_jump; | |
15148 | m68k_incpc ((int32_t)src + 2); | |
15149 | return 10; | |
15150 | didnt_jump:; | |
15151 | }}m68k_incpc(4); | |
15152 | endlabel1032: ; | |
15153 | return 12; | |
15154 | } | |
15155 | unsigned long CPUFUNC(op_6701_4)(uint32_t opcode) /* Bcc */ | |
15156 | { | |
15157 | uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); | |
15158 | OpcodeFamily = 55; CurrentInstrCycles = 8; | |
15159 | {{ uint32_t src = srcreg; | |
15160 | if (!cctrue(7)) goto didnt_jump; | |
15161 | m68k_incpc ((int32_t)src + 2); | |
15162 | return 10; | |
15163 | didnt_jump:; | |
15164 | }}m68k_incpc(2); | |
15165 | endlabel1033: ; | |
15166 | return 8; | |
15167 | } | |
15168 | unsigned long CPUFUNC(op_67ff_4)(uint32_t opcode) /* Bcc */ | |
15169 | { | |
15170 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
15171 | { m68k_incpc(2); | |
15172 | if (!cctrue(7)) goto endlabel1034; | |
15173 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
15174 | last_fault_for_exception_3 = m68k_getpc() + 1; | |
15175 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel1034; | |
15176 | { int32_t src = get_ilong(2); | |
15177 | if (!cctrue(7)) goto didnt_jump; | |
15178 | m68k_incpc ((int32_t)src + 2); | |
15179 | return 10; | |
15180 | didnt_jump:; | |
15181 | }}m68k_incpc(6); | |
15182 | endlabel1034: ; | |
15183 | return 12; | |
15184 | } | |
15185 | unsigned long CPUFUNC(op_6800_4)(uint32_t opcode) /* Bcc */ | |
15186 | { | |
15187 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
15188 | {{ int16_t src = get_iword(2); | |
15189 | if (!cctrue(8)) goto didnt_jump; | |
15190 | m68k_incpc ((int32_t)src + 2); | |
15191 | return 10; | |
15192 | didnt_jump:; | |
15193 | }}m68k_incpc(4); | |
15194 | endlabel1035: ; | |
15195 | return 12; | |
15196 | } | |
15197 | unsigned long CPUFUNC(op_6801_4)(uint32_t opcode) /* Bcc */ | |
15198 | { | |
15199 | uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); | |
15200 | OpcodeFamily = 55; CurrentInstrCycles = 8; | |
15201 | {{ uint32_t src = srcreg; | |
15202 | if (!cctrue(8)) goto didnt_jump; | |
15203 | m68k_incpc ((int32_t)src + 2); | |
15204 | return 10; | |
15205 | didnt_jump:; | |
15206 | }}m68k_incpc(2); | |
15207 | endlabel1036: ; | |
15208 | return 8; | |
15209 | } | |
15210 | unsigned long CPUFUNC(op_68ff_4)(uint32_t opcode) /* Bcc */ | |
15211 | { | |
15212 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
15213 | { m68k_incpc(2); | |
15214 | if (!cctrue(8)) goto endlabel1037; | |
15215 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
15216 | last_fault_for_exception_3 = m68k_getpc() + 1; | |
15217 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel1037; | |
15218 | { int32_t src = get_ilong(2); | |
15219 | if (!cctrue(8)) goto didnt_jump; | |
15220 | m68k_incpc ((int32_t)src + 2); | |
15221 | return 10; | |
15222 | didnt_jump:; | |
15223 | }}m68k_incpc(6); | |
15224 | endlabel1037: ; | |
15225 | return 12; | |
15226 | } | |
15227 | unsigned long CPUFUNC(op_6900_4)(uint32_t opcode) /* Bcc */ | |
15228 | { | |
15229 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
15230 | {{ int16_t src = get_iword(2); | |
15231 | if (!cctrue(9)) goto didnt_jump; | |
15232 | m68k_incpc ((int32_t)src + 2); | |
15233 | return 10; | |
15234 | didnt_jump:; | |
15235 | }}m68k_incpc(4); | |
15236 | endlabel1038: ; | |
15237 | return 12; | |
15238 | } | |
15239 | unsigned long CPUFUNC(op_6901_4)(uint32_t opcode) /* Bcc */ | |
15240 | { | |
15241 | uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); | |
15242 | OpcodeFamily = 55; CurrentInstrCycles = 8; | |
15243 | {{ uint32_t src = srcreg; | |
15244 | if (!cctrue(9)) goto didnt_jump; | |
15245 | m68k_incpc ((int32_t)src + 2); | |
15246 | return 10; | |
15247 | didnt_jump:; | |
15248 | }}m68k_incpc(2); | |
15249 | endlabel1039: ; | |
15250 | return 8; | |
15251 | } | |
15252 | unsigned long CPUFUNC(op_69ff_4)(uint32_t opcode) /* Bcc */ | |
15253 | { | |
15254 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
15255 | { m68k_incpc(2); | |
15256 | if (!cctrue(9)) goto endlabel1040; | |
15257 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
15258 | last_fault_for_exception_3 = m68k_getpc() + 1; | |
15259 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel1040; | |
15260 | { int32_t src = get_ilong(2); | |
15261 | if (!cctrue(9)) goto didnt_jump; | |
15262 | m68k_incpc ((int32_t)src + 2); | |
15263 | return 10; | |
15264 | didnt_jump:; | |
15265 | }}m68k_incpc(6); | |
15266 | endlabel1040: ; | |
15267 | return 12; | |
15268 | } | |
15269 | unsigned long CPUFUNC(op_6a00_4)(uint32_t opcode) /* Bcc */ | |
15270 | { | |
15271 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
15272 | {{ int16_t src = get_iword(2); | |
15273 | if (!cctrue(10)) goto didnt_jump; | |
15274 | m68k_incpc ((int32_t)src + 2); | |
15275 | return 10; | |
15276 | didnt_jump:; | |
15277 | }}m68k_incpc(4); | |
15278 | endlabel1041: ; | |
15279 | return 12; | |
15280 | } | |
15281 | unsigned long CPUFUNC(op_6a01_4)(uint32_t opcode) /* Bcc */ | |
15282 | { | |
15283 | uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); | |
15284 | OpcodeFamily = 55; CurrentInstrCycles = 8; | |
15285 | {{ uint32_t src = srcreg; | |
15286 | if (!cctrue(10)) goto didnt_jump; | |
15287 | m68k_incpc ((int32_t)src + 2); | |
15288 | return 10; | |
15289 | didnt_jump:; | |
15290 | }}m68k_incpc(2); | |
15291 | endlabel1042: ; | |
15292 | return 8; | |
15293 | } | |
15294 | unsigned long CPUFUNC(op_6aff_4)(uint32_t opcode) /* Bcc */ | |
15295 | { | |
15296 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
15297 | { m68k_incpc(2); | |
15298 | if (!cctrue(10)) goto endlabel1043; | |
15299 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
15300 | last_fault_for_exception_3 = m68k_getpc() + 1; | |
15301 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel1043; | |
15302 | { int32_t src = get_ilong(2); | |
15303 | if (!cctrue(10)) goto didnt_jump; | |
15304 | m68k_incpc ((int32_t)src + 2); | |
15305 | return 10; | |
15306 | didnt_jump:; | |
15307 | }}m68k_incpc(6); | |
15308 | endlabel1043: ; | |
15309 | return 12; | |
15310 | } | |
15311 | unsigned long CPUFUNC(op_6b00_4)(uint32_t opcode) /* Bcc */ | |
15312 | { | |
15313 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
15314 | {{ int16_t src = get_iword(2); | |
15315 | if (!cctrue(11)) goto didnt_jump; | |
15316 | m68k_incpc ((int32_t)src + 2); | |
15317 | return 10; | |
15318 | didnt_jump:; | |
15319 | }}m68k_incpc(4); | |
15320 | endlabel1044: ; | |
15321 | return 12; | |
15322 | } | |
15323 | unsigned long CPUFUNC(op_6b01_4)(uint32_t opcode) /* Bcc */ | |
15324 | { | |
15325 | uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); | |
15326 | OpcodeFamily = 55; CurrentInstrCycles = 8; | |
15327 | {{ uint32_t src = srcreg; | |
15328 | if (!cctrue(11)) goto didnt_jump; | |
15329 | m68k_incpc ((int32_t)src + 2); | |
15330 | return 10; | |
15331 | didnt_jump:; | |
15332 | }}m68k_incpc(2); | |
15333 | endlabel1045: ; | |
15334 | return 8; | |
15335 | } | |
15336 | unsigned long CPUFUNC(op_6bff_4)(uint32_t opcode) /* Bcc */ | |
15337 | { | |
15338 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
15339 | { m68k_incpc(2); | |
15340 | if (!cctrue(11)) goto endlabel1046; | |
15341 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
15342 | last_fault_for_exception_3 = m68k_getpc() + 1; | |
15343 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel1046; | |
15344 | { int32_t src = get_ilong(2); | |
15345 | if (!cctrue(11)) goto didnt_jump; | |
15346 | m68k_incpc ((int32_t)src + 2); | |
15347 | return 10; | |
15348 | didnt_jump:; | |
15349 | }}m68k_incpc(6); | |
15350 | endlabel1046: ; | |
15351 | return 12; | |
15352 | } | |
15353 | unsigned long CPUFUNC(op_6c00_4)(uint32_t opcode) /* Bcc */ | |
15354 | { | |
15355 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
15356 | {{ int16_t src = get_iword(2); | |
15357 | if (!cctrue(12)) goto didnt_jump; | |
15358 | m68k_incpc ((int32_t)src + 2); | |
15359 | return 10; | |
15360 | didnt_jump:; | |
15361 | }}m68k_incpc(4); | |
15362 | endlabel1047: ; | |
15363 | return 12; | |
15364 | } | |
15365 | unsigned long CPUFUNC(op_6c01_4)(uint32_t opcode) /* Bcc */ | |
15366 | { | |
15367 | uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); | |
15368 | OpcodeFamily = 55; CurrentInstrCycles = 8; | |
15369 | {{ uint32_t src = srcreg; | |
15370 | if (!cctrue(12)) goto didnt_jump; | |
15371 | m68k_incpc ((int32_t)src + 2); | |
15372 | return 10; | |
15373 | didnt_jump:; | |
15374 | }}m68k_incpc(2); | |
15375 | endlabel1048: ; | |
15376 | return 8; | |
15377 | } | |
15378 | unsigned long CPUFUNC(op_6cff_4)(uint32_t opcode) /* Bcc */ | |
15379 | { | |
15380 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
15381 | { m68k_incpc(2); | |
15382 | if (!cctrue(12)) goto endlabel1049; | |
15383 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
15384 | last_fault_for_exception_3 = m68k_getpc() + 1; | |
15385 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel1049; | |
15386 | { int32_t src = get_ilong(2); | |
15387 | if (!cctrue(12)) goto didnt_jump; | |
15388 | m68k_incpc ((int32_t)src + 2); | |
15389 | return 10; | |
15390 | didnt_jump:; | |
15391 | }}m68k_incpc(6); | |
15392 | endlabel1049: ; | |
15393 | return 12; | |
15394 | } | |
15395 | unsigned long CPUFUNC(op_6d00_4)(uint32_t opcode) /* Bcc */ | |
15396 | { | |
15397 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
15398 | {{ int16_t src = get_iword(2); | |
15399 | if (!cctrue(13)) goto didnt_jump; | |
15400 | m68k_incpc ((int32_t)src + 2); | |
15401 | return 10; | |
15402 | didnt_jump:; | |
15403 | }}m68k_incpc(4); | |
15404 | endlabel1050: ; | |
15405 | return 12; | |
15406 | } | |
15407 | unsigned long CPUFUNC(op_6d01_4)(uint32_t opcode) /* Bcc */ | |
15408 | { | |
15409 | uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); | |
15410 | OpcodeFamily = 55; CurrentInstrCycles = 8; | |
15411 | {{ uint32_t src = srcreg; | |
15412 | if (!cctrue(13)) goto didnt_jump; | |
15413 | m68k_incpc ((int32_t)src + 2); | |
15414 | return 10; | |
15415 | didnt_jump:; | |
15416 | }}m68k_incpc(2); | |
15417 | endlabel1051: ; | |
15418 | return 8; | |
15419 | } | |
15420 | unsigned long CPUFUNC(op_6dff_4)(uint32_t opcode) /* Bcc */ | |
15421 | { | |
15422 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
15423 | { m68k_incpc(2); | |
15424 | if (!cctrue(13)) goto endlabel1052; | |
15425 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
15426 | last_fault_for_exception_3 = m68k_getpc() + 1; | |
15427 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel1052; | |
15428 | { int32_t src = get_ilong(2); | |
15429 | if (!cctrue(13)) goto didnt_jump; | |
15430 | m68k_incpc ((int32_t)src + 2); | |
15431 | return 10; | |
15432 | didnt_jump:; | |
15433 | }}m68k_incpc(6); | |
15434 | endlabel1052: ; | |
15435 | return 12; | |
15436 | } | |
15437 | unsigned long CPUFUNC(op_6e00_4)(uint32_t opcode) /* Bcc */ | |
15438 | { | |
15439 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
15440 | {{ int16_t src = get_iword(2); | |
15441 | if (!cctrue(14)) goto didnt_jump; | |
15442 | m68k_incpc ((int32_t)src + 2); | |
15443 | return 10; | |
15444 | didnt_jump:; | |
15445 | }}m68k_incpc(4); | |
15446 | endlabel1053: ; | |
15447 | return 12; | |
15448 | } | |
15449 | unsigned long CPUFUNC(op_6e01_4)(uint32_t opcode) /* Bcc */ | |
15450 | { | |
15451 | uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); | |
15452 | OpcodeFamily = 55; CurrentInstrCycles = 8; | |
15453 | {{ uint32_t src = srcreg; | |
15454 | if (!cctrue(14)) goto didnt_jump; | |
15455 | m68k_incpc ((int32_t)src + 2); | |
15456 | return 10; | |
15457 | didnt_jump:; | |
15458 | }}m68k_incpc(2); | |
15459 | endlabel1054: ; | |
15460 | return 8; | |
15461 | } | |
15462 | unsigned long CPUFUNC(op_6eff_4)(uint32_t opcode) /* Bcc */ | |
15463 | { | |
15464 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
15465 | { m68k_incpc(2); | |
15466 | if (!cctrue(14)) goto endlabel1055; | |
15467 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
15468 | last_fault_for_exception_3 = m68k_getpc() + 1; | |
15469 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel1055; | |
15470 | { int32_t src = get_ilong(2); | |
15471 | if (!cctrue(14)) goto didnt_jump; | |
15472 | m68k_incpc ((int32_t)src + 2); | |
15473 | return 10; | |
15474 | didnt_jump:; | |
15475 | }}m68k_incpc(6); | |
15476 | endlabel1055: ; | |
15477 | return 12; | |
15478 | } | |
15479 | unsigned long CPUFUNC(op_6f00_4)(uint32_t opcode) /* Bcc */ | |
15480 | { | |
15481 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
15482 | {{ int16_t src = get_iword(2); | |
15483 | if (!cctrue(15)) goto didnt_jump; | |
15484 | m68k_incpc ((int32_t)src + 2); | |
15485 | return 10; | |
15486 | didnt_jump:; | |
15487 | }}m68k_incpc(4); | |
15488 | endlabel1056: ; | |
15489 | return 12; | |
15490 | } | |
15491 | unsigned long CPUFUNC(op_6f01_4)(uint32_t opcode) /* Bcc */ | |
15492 | { | |
15493 | uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); | |
15494 | OpcodeFamily = 55; CurrentInstrCycles = 8; | |
15495 | {{ uint32_t src = srcreg; | |
15496 | if (!cctrue(15)) goto didnt_jump; | |
15497 | m68k_incpc ((int32_t)src + 2); | |
15498 | return 10; | |
15499 | didnt_jump:; | |
15500 | }}m68k_incpc(2); | |
15501 | endlabel1057: ; | |
15502 | return 8; | |
15503 | } | |
15504 | unsigned long CPUFUNC(op_6fff_4)(uint32_t opcode) /* Bcc */ | |
15505 | { | |
15506 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
15507 | { m68k_incpc(2); | |
15508 | if (!cctrue(15)) goto endlabel1058; | |
15509 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
15510 | last_fault_for_exception_3 = m68k_getpc() + 1; | |
15511 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel1058; | |
15512 | { int32_t src = get_ilong(2); | |
15513 | if (!cctrue(15)) goto didnt_jump; | |
15514 | m68k_incpc ((int32_t)src + 2); | |
15515 | return 10; | |
15516 | didnt_jump:; | |
15517 | }}m68k_incpc(6); | |
15518 | endlabel1058: ; | |
15519 | return 12; | |
15520 | } | |
15521 | unsigned long CPUFUNC(op_7000_4)(uint32_t opcode) /* MOVE */ | |
15522 | { | |
15523 | uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); | |
15524 | uint32_t dstreg = (opcode >> 9) & 7; | |
15525 | OpcodeFamily = 30; CurrentInstrCycles = 4; | |
15526 | {{ uint32_t src = srcreg; | |
15527 | { CLEAR_CZNV; | |
15528 | SET_ZFLG (((int32_t)(src)) == 0); | |
15529 | SET_NFLG (((int32_t)(src)) < 0); | |
15530 | m68k_dreg(regs, dstreg) = (src); | |
15531 | }}}m68k_incpc(2); | |
15532 | return 4; | |
15533 | } | |
15534 | unsigned long CPUFUNC(op_8000_4)(uint32_t opcode) /* OR */ | |
15535 | { | |
15536 | uint32_t srcreg = (opcode & 7); | |
15537 | uint32_t dstreg = (opcode >> 9) & 7; | |
15538 | OpcodeFamily = 1; CurrentInstrCycles = 4; | |
15539 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
15540 | { int8_t dst = m68k_dreg(regs, dstreg); | |
15541 | src |= dst; | |
15542 | CLEAR_CZNV; | |
15543 | SET_ZFLG (((int8_t)(src)) == 0); | |
15544 | SET_NFLG (((int8_t)(src)) < 0); | |
15545 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
15546 | }}}m68k_incpc(2); | |
15547 | return 4; | |
15548 | } | |
15549 | unsigned long CPUFUNC(op_8010_4)(uint32_t opcode) /* OR */ | |
15550 | { | |
15551 | uint32_t srcreg = (opcode & 7); | |
15552 | uint32_t dstreg = (opcode >> 9) & 7; | |
15553 | OpcodeFamily = 1; CurrentInstrCycles = 8; | |
15554 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
15555 | { int8_t src = m68k_read_memory_8(srca); | |
15556 | { int8_t dst = m68k_dreg(regs, dstreg); | |
15557 | src |= dst; | |
15558 | CLEAR_CZNV; | |
15559 | SET_ZFLG (((int8_t)(src)) == 0); | |
15560 | SET_NFLG (((int8_t)(src)) < 0); | |
15561 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
15562 | }}}}m68k_incpc(2); | |
15563 | return 8; | |
15564 | } | |
15565 | unsigned long CPUFUNC(op_8018_4)(uint32_t opcode) /* OR */ | |
15566 | { | |
15567 | uint32_t srcreg = (opcode & 7); | |
15568 | uint32_t dstreg = (opcode >> 9) & 7; | |
15569 | OpcodeFamily = 1; CurrentInstrCycles = 8; | |
15570 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
15571 | { int8_t src = m68k_read_memory_8(srca); | |
15572 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
15573 | { int8_t dst = m68k_dreg(regs, dstreg); | |
15574 | src |= dst; | |
15575 | CLEAR_CZNV; | |
15576 | SET_ZFLG (((int8_t)(src)) == 0); | |
15577 | SET_NFLG (((int8_t)(src)) < 0); | |
15578 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
15579 | }}}}m68k_incpc(2); | |
15580 | return 8; | |
15581 | } | |
15582 | unsigned long CPUFUNC(op_8020_4)(uint32_t opcode) /* OR */ | |
15583 | { | |
15584 | uint32_t srcreg = (opcode & 7); | |
15585 | uint32_t dstreg = (opcode >> 9) & 7; | |
15586 | OpcodeFamily = 1; CurrentInstrCycles = 10; | |
15587 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
15588 | { int8_t src = m68k_read_memory_8(srca); | |
15589 | m68k_areg (regs, srcreg) = srca; | |
15590 | { int8_t dst = m68k_dreg(regs, dstreg); | |
15591 | src |= dst; | |
15592 | CLEAR_CZNV; | |
15593 | SET_ZFLG (((int8_t)(src)) == 0); | |
15594 | SET_NFLG (((int8_t)(src)) < 0); | |
15595 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
15596 | }}}}m68k_incpc(2); | |
15597 | return 10; | |
15598 | } | |
15599 | unsigned long CPUFUNC(op_8028_4)(uint32_t opcode) /* OR */ | |
15600 | { | |
15601 | uint32_t srcreg = (opcode & 7); | |
15602 | uint32_t dstreg = (opcode >> 9) & 7; | |
15603 | OpcodeFamily = 1; CurrentInstrCycles = 12; | |
15604 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
15605 | { int8_t src = m68k_read_memory_8(srca); | |
15606 | { int8_t dst = m68k_dreg(regs, dstreg); | |
15607 | src |= dst; | |
15608 | CLEAR_CZNV; | |
15609 | SET_ZFLG (((int8_t)(src)) == 0); | |
15610 | SET_NFLG (((int8_t)(src)) < 0); | |
15611 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
15612 | }}}}m68k_incpc(4); | |
15613 | return 12; | |
15614 | } | |
15615 | unsigned long CPUFUNC(op_8030_4)(uint32_t opcode) /* OR */ | |
15616 | { | |
15617 | uint32_t srcreg = (opcode & 7); | |
15618 | uint32_t dstreg = (opcode >> 9) & 7; | |
15619 | OpcodeFamily = 1; CurrentInstrCycles = 14; | |
15620 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
15621 | BusCyclePenalty += 2; | |
15622 | { int8_t src = m68k_read_memory_8(srca); | |
15623 | { int8_t dst = m68k_dreg(regs, dstreg); | |
15624 | src |= dst; | |
15625 | CLEAR_CZNV; | |
15626 | SET_ZFLG (((int8_t)(src)) == 0); | |
15627 | SET_NFLG (((int8_t)(src)) < 0); | |
15628 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
15629 | }}}}m68k_incpc(4); | |
15630 | return 14; | |
15631 | } | |
15632 | unsigned long CPUFUNC(op_8038_4)(uint32_t opcode) /* OR */ | |
15633 | { | |
15634 | uint32_t dstreg = (opcode >> 9) & 7; | |
15635 | OpcodeFamily = 1; CurrentInstrCycles = 12; | |
15636 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
15637 | { int8_t src = m68k_read_memory_8(srca); | |
15638 | { int8_t dst = m68k_dreg(regs, dstreg); | |
15639 | src |= dst; | |
15640 | CLEAR_CZNV; | |
15641 | SET_ZFLG (((int8_t)(src)) == 0); | |
15642 | SET_NFLG (((int8_t)(src)) < 0); | |
15643 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
15644 | }}}}m68k_incpc(4); | |
15645 | return 12; | |
15646 | } | |
15647 | unsigned long CPUFUNC(op_8039_4)(uint32_t opcode) /* OR */ | |
15648 | { | |
15649 | uint32_t dstreg = (opcode >> 9) & 7; | |
15650 | OpcodeFamily = 1; CurrentInstrCycles = 16; | |
15651 | {{ uint32_t srca = get_ilong(2); | |
15652 | { int8_t src = m68k_read_memory_8(srca); | |
15653 | { int8_t dst = m68k_dreg(regs, dstreg); | |
15654 | src |= dst; | |
15655 | CLEAR_CZNV; | |
15656 | SET_ZFLG (((int8_t)(src)) == 0); | |
15657 | SET_NFLG (((int8_t)(src)) < 0); | |
15658 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
15659 | }}}}m68k_incpc(6); | |
15660 | return 16; | |
15661 | } | |
15662 | unsigned long CPUFUNC(op_803a_4)(uint32_t opcode) /* OR */ | |
15663 | { | |
15664 | uint32_t dstreg = (opcode >> 9) & 7; | |
15665 | OpcodeFamily = 1; CurrentInstrCycles = 12; | |
15666 | {{ uint32_t srca = m68k_getpc () + 2; | |
15667 | srca += (int32_t)(int16_t)get_iword(2); | |
15668 | { int8_t src = m68k_read_memory_8(srca); | |
15669 | { int8_t dst = m68k_dreg(regs, dstreg); | |
15670 | src |= dst; | |
15671 | CLEAR_CZNV; | |
15672 | SET_ZFLG (((int8_t)(src)) == 0); | |
15673 | SET_NFLG (((int8_t)(src)) < 0); | |
15674 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
15675 | }}}}m68k_incpc(4); | |
15676 | return 12; | |
15677 | } | |
15678 | unsigned long CPUFUNC(op_803b_4)(uint32_t opcode) /* OR */ | |
15679 | { | |
15680 | uint32_t dstreg = (opcode >> 9) & 7; | |
15681 | OpcodeFamily = 1; CurrentInstrCycles = 14; | |
15682 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
15683 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
15684 | BusCyclePenalty += 2; | |
15685 | { int8_t src = m68k_read_memory_8(srca); | |
15686 | { int8_t dst = m68k_dreg(regs, dstreg); | |
15687 | src |= dst; | |
15688 | CLEAR_CZNV; | |
15689 | SET_ZFLG (((int8_t)(src)) == 0); | |
15690 | SET_NFLG (((int8_t)(src)) < 0); | |
15691 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
15692 | }}}}m68k_incpc(4); | |
15693 | return 14; | |
15694 | } | |
15695 | unsigned long CPUFUNC(op_803c_4)(uint32_t opcode) /* OR */ | |
15696 | { | |
15697 | uint32_t dstreg = (opcode >> 9) & 7; | |
15698 | OpcodeFamily = 1; CurrentInstrCycles = 8; | |
15699 | {{ int8_t src = get_ibyte(2); | |
15700 | { int8_t dst = m68k_dreg(regs, dstreg); | |
15701 | src |= dst; | |
15702 | CLEAR_CZNV; | |
15703 | SET_ZFLG (((int8_t)(src)) == 0); | |
15704 | SET_NFLG (((int8_t)(src)) < 0); | |
15705 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
15706 | }}}m68k_incpc(4); | |
15707 | return 8; | |
15708 | } | |
15709 | unsigned long CPUFUNC(op_8040_4)(uint32_t opcode) /* OR */ | |
15710 | { | |
15711 | uint32_t srcreg = (opcode & 7); | |
15712 | uint32_t dstreg = (opcode >> 9) & 7; | |
15713 | OpcodeFamily = 1; CurrentInstrCycles = 4; | |
15714 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
15715 | { int16_t dst = m68k_dreg(regs, dstreg); | |
15716 | src |= dst; | |
15717 | CLEAR_CZNV; | |
15718 | SET_ZFLG (((int16_t)(src)) == 0); | |
15719 | SET_NFLG (((int16_t)(src)) < 0); | |
15720 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
15721 | }}}m68k_incpc(2); | |
15722 | return 4; | |
15723 | } | |
15724 | unsigned long CPUFUNC(op_8050_4)(uint32_t opcode) /* OR */ | |
15725 | { | |
15726 | uint32_t srcreg = (opcode & 7); | |
15727 | uint32_t dstreg = (opcode >> 9) & 7; | |
15728 | OpcodeFamily = 1; CurrentInstrCycles = 8; | |
15729 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
15730 | { int16_t src = m68k_read_memory_16(srca); | |
15731 | { int16_t dst = m68k_dreg(regs, dstreg); | |
15732 | src |= dst; | |
15733 | CLEAR_CZNV; | |
15734 | SET_ZFLG (((int16_t)(src)) == 0); | |
15735 | SET_NFLG (((int16_t)(src)) < 0); | |
15736 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
15737 | }}}}m68k_incpc(2); | |
15738 | return 8; | |
15739 | } | |
15740 | unsigned long CPUFUNC(op_8058_4)(uint32_t opcode) /* OR */ | |
15741 | { | |
15742 | uint32_t srcreg = (opcode & 7); | |
15743 | uint32_t dstreg = (opcode >> 9) & 7; | |
15744 | OpcodeFamily = 1; CurrentInstrCycles = 8; | |
15745 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
15746 | { int16_t src = m68k_read_memory_16(srca); | |
15747 | m68k_areg(regs, srcreg) += 2; | |
15748 | { int16_t dst = m68k_dreg(regs, dstreg); | |
15749 | src |= dst; | |
15750 | CLEAR_CZNV; | |
15751 | SET_ZFLG (((int16_t)(src)) == 0); | |
15752 | SET_NFLG (((int16_t)(src)) < 0); | |
15753 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
15754 | }}}}m68k_incpc(2); | |
15755 | return 8; | |
15756 | } | |
15757 | unsigned long CPUFUNC(op_8060_4)(uint32_t opcode) /* OR */ | |
15758 | { | |
15759 | uint32_t srcreg = (opcode & 7); | |
15760 | uint32_t dstreg = (opcode >> 9) & 7; | |
15761 | OpcodeFamily = 1; CurrentInstrCycles = 10; | |
15762 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
15763 | { int16_t src = m68k_read_memory_16(srca); | |
15764 | m68k_areg (regs, srcreg) = srca; | |
15765 | { int16_t dst = m68k_dreg(regs, dstreg); | |
15766 | src |= dst; | |
15767 | CLEAR_CZNV; | |
15768 | SET_ZFLG (((int16_t)(src)) == 0); | |
15769 | SET_NFLG (((int16_t)(src)) < 0); | |
15770 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
15771 | }}}}m68k_incpc(2); | |
15772 | return 10; | |
15773 | } | |
15774 | unsigned long CPUFUNC(op_8068_4)(uint32_t opcode) /* OR */ | |
15775 | { | |
15776 | uint32_t srcreg = (opcode & 7); | |
15777 | uint32_t dstreg = (opcode >> 9) & 7; | |
15778 | OpcodeFamily = 1; CurrentInstrCycles = 12; | |
15779 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
15780 | { int16_t src = m68k_read_memory_16(srca); | |
15781 | { int16_t dst = m68k_dreg(regs, dstreg); | |
15782 | src |= dst; | |
15783 | CLEAR_CZNV; | |
15784 | SET_ZFLG (((int16_t)(src)) == 0); | |
15785 | SET_NFLG (((int16_t)(src)) < 0); | |
15786 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
15787 | }}}}m68k_incpc(4); | |
15788 | return 12; | |
15789 | } | |
15790 | unsigned long CPUFUNC(op_8070_4)(uint32_t opcode) /* OR */ | |
15791 | { | |
15792 | uint32_t srcreg = (opcode & 7); | |
15793 | uint32_t dstreg = (opcode >> 9) & 7; | |
15794 | OpcodeFamily = 1; CurrentInstrCycles = 14; | |
15795 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
15796 | BusCyclePenalty += 2; | |
15797 | { int16_t src = m68k_read_memory_16(srca); | |
15798 | { int16_t dst = m68k_dreg(regs, dstreg); | |
15799 | src |= dst; | |
15800 | CLEAR_CZNV; | |
15801 | SET_ZFLG (((int16_t)(src)) == 0); | |
15802 | SET_NFLG (((int16_t)(src)) < 0); | |
15803 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
15804 | }}}}m68k_incpc(4); | |
15805 | return 14; | |
15806 | } | |
15807 | unsigned long CPUFUNC(op_8078_4)(uint32_t opcode) /* OR */ | |
15808 | { | |
15809 | uint32_t dstreg = (opcode >> 9) & 7; | |
15810 | OpcodeFamily = 1; CurrentInstrCycles = 12; | |
15811 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
15812 | { int16_t src = m68k_read_memory_16(srca); | |
15813 | { int16_t dst = m68k_dreg(regs, dstreg); | |
15814 | src |= dst; | |
15815 | CLEAR_CZNV; | |
15816 | SET_ZFLG (((int16_t)(src)) == 0); | |
15817 | SET_NFLG (((int16_t)(src)) < 0); | |
15818 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
15819 | }}}}m68k_incpc(4); | |
15820 | return 12; | |
15821 | } | |
15822 | unsigned long CPUFUNC(op_8079_4)(uint32_t opcode) /* OR */ | |
15823 | { | |
15824 | uint32_t dstreg = (opcode >> 9) & 7; | |
15825 | OpcodeFamily = 1; CurrentInstrCycles = 16; | |
15826 | {{ uint32_t srca = get_ilong(2); | |
15827 | { int16_t src = m68k_read_memory_16(srca); | |
15828 | { int16_t dst = m68k_dreg(regs, dstreg); | |
15829 | src |= dst; | |
15830 | CLEAR_CZNV; | |
15831 | SET_ZFLG (((int16_t)(src)) == 0); | |
15832 | SET_NFLG (((int16_t)(src)) < 0); | |
15833 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
15834 | }}}}m68k_incpc(6); | |
15835 | return 16; | |
15836 | } | |
15837 | unsigned long CPUFUNC(op_807a_4)(uint32_t opcode) /* OR */ | |
15838 | { | |
15839 | uint32_t dstreg = (opcode >> 9) & 7; | |
15840 | OpcodeFamily = 1; CurrentInstrCycles = 12; | |
15841 | {{ uint32_t srca = m68k_getpc () + 2; | |
15842 | srca += (int32_t)(int16_t)get_iword(2); | |
15843 | { int16_t src = m68k_read_memory_16(srca); | |
15844 | { int16_t dst = m68k_dreg(regs, dstreg); | |
15845 | src |= dst; | |
15846 | CLEAR_CZNV; | |
15847 | SET_ZFLG (((int16_t)(src)) == 0); | |
15848 | SET_NFLG (((int16_t)(src)) < 0); | |
15849 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
15850 | }}}}m68k_incpc(4); | |
15851 | return 12; | |
15852 | } | |
15853 | unsigned long CPUFUNC(op_807b_4)(uint32_t opcode) /* OR */ | |
15854 | { | |
15855 | uint32_t dstreg = (opcode >> 9) & 7; | |
15856 | OpcodeFamily = 1; CurrentInstrCycles = 14; | |
15857 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
15858 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
15859 | BusCyclePenalty += 2; | |
15860 | { int16_t src = m68k_read_memory_16(srca); | |
15861 | { int16_t dst = m68k_dreg(regs, dstreg); | |
15862 | src |= dst; | |
15863 | CLEAR_CZNV; | |
15864 | SET_ZFLG (((int16_t)(src)) == 0); | |
15865 | SET_NFLG (((int16_t)(src)) < 0); | |
15866 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
15867 | }}}}m68k_incpc(4); | |
15868 | return 14; | |
15869 | } | |
15870 | unsigned long CPUFUNC(op_807c_4)(uint32_t opcode) /* OR */ | |
15871 | { | |
15872 | uint32_t dstreg = (opcode >> 9) & 7; | |
15873 | OpcodeFamily = 1; CurrentInstrCycles = 8; | |
15874 | {{ int16_t src = get_iword(2); | |
15875 | { int16_t dst = m68k_dreg(regs, dstreg); | |
15876 | src |= dst; | |
15877 | CLEAR_CZNV; | |
15878 | SET_ZFLG (((int16_t)(src)) == 0); | |
15879 | SET_NFLG (((int16_t)(src)) < 0); | |
15880 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
15881 | }}}m68k_incpc(4); | |
15882 | return 8; | |
15883 | } | |
15884 | unsigned long CPUFUNC(op_8080_4)(uint32_t opcode) /* OR */ | |
15885 | { | |
15886 | uint32_t srcreg = (opcode & 7); | |
15887 | uint32_t dstreg = (opcode >> 9) & 7; | |
15888 | OpcodeFamily = 1; CurrentInstrCycles = 8; | |
15889 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
15890 | { int32_t dst = m68k_dreg(regs, dstreg); | |
15891 | src |= dst; | |
15892 | CLEAR_CZNV; | |
15893 | SET_ZFLG (((int32_t)(src)) == 0); | |
15894 | SET_NFLG (((int32_t)(src)) < 0); | |
15895 | m68k_dreg(regs, dstreg) = (src); | |
15896 | }}}m68k_incpc(2); | |
15897 | return 8; | |
15898 | } | |
15899 | unsigned long CPUFUNC(op_8090_4)(uint32_t opcode) /* OR */ | |
15900 | { | |
15901 | uint32_t srcreg = (opcode & 7); | |
15902 | uint32_t dstreg = (opcode >> 9) & 7; | |
15903 | OpcodeFamily = 1; CurrentInstrCycles = 14; | |
15904 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
15905 | { int32_t src = m68k_read_memory_32(srca); | |
15906 | { int32_t dst = m68k_dreg(regs, dstreg); | |
15907 | src |= dst; | |
15908 | CLEAR_CZNV; | |
15909 | SET_ZFLG (((int32_t)(src)) == 0); | |
15910 | SET_NFLG (((int32_t)(src)) < 0); | |
15911 | m68k_dreg(regs, dstreg) = (src); | |
15912 | }}}}m68k_incpc(2); | |
15913 | return 14; | |
15914 | } | |
15915 | unsigned long CPUFUNC(op_8098_4)(uint32_t opcode) /* OR */ | |
15916 | { | |
15917 | uint32_t srcreg = (opcode & 7); | |
15918 | uint32_t dstreg = (opcode >> 9) & 7; | |
15919 | OpcodeFamily = 1; CurrentInstrCycles = 14; | |
15920 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
15921 | { int32_t src = m68k_read_memory_32(srca); | |
15922 | m68k_areg(regs, srcreg) += 4; | |
15923 | { int32_t dst = m68k_dreg(regs, dstreg); | |
15924 | src |= dst; | |
15925 | CLEAR_CZNV; | |
15926 | SET_ZFLG (((int32_t)(src)) == 0); | |
15927 | SET_NFLG (((int32_t)(src)) < 0); | |
15928 | m68k_dreg(regs, dstreg) = (src); | |
15929 | }}}}m68k_incpc(2); | |
15930 | return 14; | |
15931 | } | |
15932 | unsigned long CPUFUNC(op_80a0_4)(uint32_t opcode) /* OR */ | |
15933 | { | |
15934 | uint32_t srcreg = (opcode & 7); | |
15935 | uint32_t dstreg = (opcode >> 9) & 7; | |
15936 | OpcodeFamily = 1; CurrentInstrCycles = 16; | |
15937 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 4; | |
15938 | { int32_t src = m68k_read_memory_32(srca); | |
15939 | m68k_areg (regs, srcreg) = srca; | |
15940 | { int32_t dst = m68k_dreg(regs, dstreg); | |
15941 | src |= dst; | |
15942 | CLEAR_CZNV; | |
15943 | SET_ZFLG (((int32_t)(src)) == 0); | |
15944 | SET_NFLG (((int32_t)(src)) < 0); | |
15945 | m68k_dreg(regs, dstreg) = (src); | |
15946 | }}}}m68k_incpc(2); | |
15947 | return 16; | |
15948 | } | |
15949 | unsigned long CPUFUNC(op_80a8_4)(uint32_t opcode) /* OR */ | |
15950 | { | |
15951 | uint32_t srcreg = (opcode & 7); | |
15952 | uint32_t dstreg = (opcode >> 9) & 7; | |
15953 | OpcodeFamily = 1; CurrentInstrCycles = 18; | |
15954 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
15955 | { int32_t src = m68k_read_memory_32(srca); | |
15956 | { int32_t dst = m68k_dreg(regs, dstreg); | |
15957 | src |= dst; | |
15958 | CLEAR_CZNV; | |
15959 | SET_ZFLG (((int32_t)(src)) == 0); | |
15960 | SET_NFLG (((int32_t)(src)) < 0); | |
15961 | m68k_dreg(regs, dstreg) = (src); | |
15962 | }}}}m68k_incpc(4); | |
15963 | return 18; | |
15964 | } | |
15965 | unsigned long CPUFUNC(op_80b0_4)(uint32_t opcode) /* OR */ | |
15966 | { | |
15967 | uint32_t srcreg = (opcode & 7); | |
15968 | uint32_t dstreg = (opcode >> 9) & 7; | |
15969 | OpcodeFamily = 1; CurrentInstrCycles = 20; | |
15970 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
15971 | BusCyclePenalty += 2; | |
15972 | { int32_t src = m68k_read_memory_32(srca); | |
15973 | { int32_t dst = m68k_dreg(regs, dstreg); | |
15974 | src |= dst; | |
15975 | CLEAR_CZNV; | |
15976 | SET_ZFLG (((int32_t)(src)) == 0); | |
15977 | SET_NFLG (((int32_t)(src)) < 0); | |
15978 | m68k_dreg(regs, dstreg) = (src); | |
15979 | }}}}m68k_incpc(4); | |
15980 | return 20; | |
15981 | } | |
15982 | unsigned long CPUFUNC(op_80b8_4)(uint32_t opcode) /* OR */ | |
15983 | { | |
15984 | uint32_t dstreg = (opcode >> 9) & 7; | |
15985 | OpcodeFamily = 1; CurrentInstrCycles = 18; | |
15986 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
15987 | { int32_t src = m68k_read_memory_32(srca); | |
15988 | { int32_t dst = m68k_dreg(regs, dstreg); | |
15989 | src |= dst; | |
15990 | CLEAR_CZNV; | |
15991 | SET_ZFLG (((int32_t)(src)) == 0); | |
15992 | SET_NFLG (((int32_t)(src)) < 0); | |
15993 | m68k_dreg(regs, dstreg) = (src); | |
15994 | }}}}m68k_incpc(4); | |
15995 | return 18; | |
15996 | } | |
15997 | unsigned long CPUFUNC(op_80b9_4)(uint32_t opcode) /* OR */ | |
15998 | { | |
15999 | uint32_t dstreg = (opcode >> 9) & 7; | |
16000 | OpcodeFamily = 1; CurrentInstrCycles = 22; | |
16001 | {{ uint32_t srca = get_ilong(2); | |
16002 | { int32_t src = m68k_read_memory_32(srca); | |
16003 | { int32_t dst = m68k_dreg(regs, dstreg); | |
16004 | src |= dst; | |
16005 | CLEAR_CZNV; | |
16006 | SET_ZFLG (((int32_t)(src)) == 0); | |
16007 | SET_NFLG (((int32_t)(src)) < 0); | |
16008 | m68k_dreg(regs, dstreg) = (src); | |
16009 | }}}}m68k_incpc(6); | |
16010 | return 22; | |
16011 | } | |
16012 | unsigned long CPUFUNC(op_80ba_4)(uint32_t opcode) /* OR */ | |
16013 | { | |
16014 | uint32_t dstreg = (opcode >> 9) & 7; | |
16015 | OpcodeFamily = 1; CurrentInstrCycles = 18; | |
16016 | {{ uint32_t srca = m68k_getpc () + 2; | |
16017 | srca += (int32_t)(int16_t)get_iword(2); | |
16018 | { int32_t src = m68k_read_memory_32(srca); | |
16019 | { int32_t dst = m68k_dreg(regs, dstreg); | |
16020 | src |= dst; | |
16021 | CLEAR_CZNV; | |
16022 | SET_ZFLG (((int32_t)(src)) == 0); | |
16023 | SET_NFLG (((int32_t)(src)) < 0); | |
16024 | m68k_dreg(regs, dstreg) = (src); | |
16025 | }}}}m68k_incpc(4); | |
16026 | return 18; | |
16027 | } | |
16028 | unsigned long CPUFUNC(op_80bb_4)(uint32_t opcode) /* OR */ | |
16029 | { | |
16030 | uint32_t dstreg = (opcode >> 9) & 7; | |
16031 | OpcodeFamily = 1; CurrentInstrCycles = 20; | |
16032 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
16033 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
16034 | BusCyclePenalty += 2; | |
16035 | { int32_t src = m68k_read_memory_32(srca); | |
16036 | { int32_t dst = m68k_dreg(regs, dstreg); | |
16037 | src |= dst; | |
16038 | CLEAR_CZNV; | |
16039 | SET_ZFLG (((int32_t)(src)) == 0); | |
16040 | SET_NFLG (((int32_t)(src)) < 0); | |
16041 | m68k_dreg(regs, dstreg) = (src); | |
16042 | }}}}m68k_incpc(4); | |
16043 | return 20; | |
16044 | } | |
16045 | unsigned long CPUFUNC(op_80bc_4)(uint32_t opcode) /* OR */ | |
16046 | { | |
16047 | uint32_t dstreg = (opcode >> 9) & 7; | |
16048 | OpcodeFamily = 1; CurrentInstrCycles = 16; | |
16049 | {{ int32_t src = get_ilong(2); | |
16050 | { int32_t dst = m68k_dreg(regs, dstreg); | |
16051 | src |= dst; | |
16052 | CLEAR_CZNV; | |
16053 | SET_ZFLG (((int32_t)(src)) == 0); | |
16054 | SET_NFLG (((int32_t)(src)) < 0); | |
16055 | m68k_dreg(regs, dstreg) = (src); | |
16056 | }}}m68k_incpc(6); | |
16057 | return 16; | |
16058 | } | |
16059 | unsigned long CPUFUNC(op_80c0_4)(uint32_t opcode) /* DIVU */ | |
16060 | { | |
16061 | uint32_t srcreg = (opcode & 7); | |
16062 | uint32_t dstreg = (opcode >> 9) & 7; | |
16063 | unsigned int retcycles = 0; | |
16064 | OpcodeFamily = 60; CurrentInstrCycles = 4; | |
16065 | { uint32_t oldpc = m68k_getpc(); | |
16066 | { int16_t src = m68k_dreg(regs, srcreg); | |
16067 | { int32_t dst = m68k_dreg(regs, dstreg); | |
16068 | m68k_incpc(2); | |
16069 | if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel1093; } else { | |
16070 | uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src; | |
16071 | uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src; | |
16072 | if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else | |
16073 | { | |
16074 | CLEAR_CZNV; | |
16075 | SET_ZFLG (((int16_t)(newv)) == 0); | |
16076 | SET_NFLG (((int16_t)(newv)) < 0); | |
16077 | newv = (newv & 0xffff) | ((uint32_t)rem << 16); | |
16078 | m68k_dreg(regs, dstreg) = (newv); | |
16079 | } | |
16080 | } | |
16081 | retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src); | |
16082 | }}}endlabel1093: ; | |
16083 | return (4+retcycles); | |
16084 | } | |
16085 | unsigned long CPUFUNC(op_80d0_4)(uint32_t opcode) /* DIVU */ | |
16086 | { | |
16087 | uint32_t srcreg = (opcode & 7); | |
16088 | uint32_t dstreg = (opcode >> 9) & 7; | |
16089 | unsigned int retcycles = 0; | |
16090 | OpcodeFamily = 60; CurrentInstrCycles = 8; | |
16091 | { uint32_t oldpc = m68k_getpc(); | |
16092 | { uint32_t srca = m68k_areg(regs, srcreg); | |
16093 | { int16_t src = m68k_read_memory_16(srca); | |
16094 | { int32_t dst = m68k_dreg(regs, dstreg); | |
16095 | m68k_incpc(2); | |
16096 | if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel1094; } else { | |
16097 | uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src; | |
16098 | uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src; | |
16099 | if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else | |
16100 | { | |
16101 | CLEAR_CZNV; | |
16102 | SET_ZFLG (((int16_t)(newv)) == 0); | |
16103 | SET_NFLG (((int16_t)(newv)) < 0); | |
16104 | newv = (newv & 0xffff) | ((uint32_t)rem << 16); | |
16105 | m68k_dreg(regs, dstreg) = (newv); | |
16106 | } | |
16107 | } | |
16108 | retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src); | |
16109 | }}}}endlabel1094: ; | |
16110 | return (8+retcycles); | |
16111 | } | |
16112 | unsigned long CPUFUNC(op_80d8_4)(uint32_t opcode) /* DIVU */ | |
16113 | { | |
16114 | uint32_t srcreg = (opcode & 7); | |
16115 | uint32_t dstreg = (opcode >> 9) & 7; | |
16116 | unsigned int retcycles = 0; | |
16117 | OpcodeFamily = 60; CurrentInstrCycles = 8; | |
16118 | { uint32_t oldpc = m68k_getpc(); | |
16119 | { uint32_t srca = m68k_areg(regs, srcreg); | |
16120 | { int16_t src = m68k_read_memory_16(srca); | |
16121 | m68k_areg(regs, srcreg) += 2; | |
16122 | { int32_t dst = m68k_dreg(regs, dstreg); | |
16123 | m68k_incpc(2); | |
16124 | if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel1095; } else { | |
16125 | uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src; | |
16126 | uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src; | |
16127 | if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else | |
16128 | { | |
16129 | CLEAR_CZNV; | |
16130 | SET_ZFLG (((int16_t)(newv)) == 0); | |
16131 | SET_NFLG (((int16_t)(newv)) < 0); | |
16132 | newv = (newv & 0xffff) | ((uint32_t)rem << 16); | |
16133 | m68k_dreg(regs, dstreg) = (newv); | |
16134 | } | |
16135 | } | |
16136 | retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src); | |
16137 | }}}}endlabel1095: ; | |
16138 | return (8+retcycles); | |
16139 | } | |
16140 | unsigned long CPUFUNC(op_80e0_4)(uint32_t opcode) /* DIVU */ | |
16141 | { | |
16142 | uint32_t srcreg = (opcode & 7); | |
16143 | uint32_t dstreg = (opcode >> 9) & 7; | |
16144 | unsigned int retcycles = 0; | |
16145 | OpcodeFamily = 60; CurrentInstrCycles = 10; | |
16146 | { uint32_t oldpc = m68k_getpc(); | |
16147 | { uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
16148 | { int16_t src = m68k_read_memory_16(srca); | |
16149 | m68k_areg (regs, srcreg) = srca; | |
16150 | { int32_t dst = m68k_dreg(regs, dstreg); | |
16151 | m68k_incpc(2); | |
16152 | if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel1096; } else { | |
16153 | uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src; | |
16154 | uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src; | |
16155 | if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else | |
16156 | { | |
16157 | CLEAR_CZNV; | |
16158 | SET_ZFLG (((int16_t)(newv)) == 0); | |
16159 | SET_NFLG (((int16_t)(newv)) < 0); | |
16160 | newv = (newv & 0xffff) | ((uint32_t)rem << 16); | |
16161 | m68k_dreg(regs, dstreg) = (newv); | |
16162 | } | |
16163 | } | |
16164 | retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src); | |
16165 | }}}}endlabel1096: ; | |
16166 | return (10+retcycles); | |
16167 | } | |
16168 | unsigned long CPUFUNC(op_80e8_4)(uint32_t opcode) /* DIVU */ | |
16169 | { | |
16170 | uint32_t srcreg = (opcode & 7); | |
16171 | uint32_t dstreg = (opcode >> 9) & 7; | |
16172 | unsigned int retcycles = 0; | |
16173 | OpcodeFamily = 60; CurrentInstrCycles = 12; | |
16174 | { uint32_t oldpc = m68k_getpc(); | |
16175 | { uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
16176 | { int16_t src = m68k_read_memory_16(srca); | |
16177 | { int32_t dst = m68k_dreg(regs, dstreg); | |
16178 | m68k_incpc(4); | |
16179 | if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel1097; } else { | |
16180 | uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src; | |
16181 | uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src; | |
16182 | if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else | |
16183 | { | |
16184 | CLEAR_CZNV; | |
16185 | SET_ZFLG (((int16_t)(newv)) == 0); | |
16186 | SET_NFLG (((int16_t)(newv)) < 0); | |
16187 | newv = (newv & 0xffff) | ((uint32_t)rem << 16); | |
16188 | m68k_dreg(regs, dstreg) = (newv); | |
16189 | } | |
16190 | } | |
16191 | retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src); | |
16192 | }}}}endlabel1097: ; | |
16193 | return (12+retcycles); | |
16194 | } | |
16195 | unsigned long CPUFUNC(op_80f0_4)(uint32_t opcode) /* DIVU */ | |
16196 | { | |
16197 | uint32_t srcreg = (opcode & 7); | |
16198 | uint32_t dstreg = (opcode >> 9) & 7; | |
16199 | unsigned int retcycles = 0; | |
16200 | OpcodeFamily = 60; CurrentInstrCycles = 14; | |
16201 | { uint32_t oldpc = m68k_getpc(); | |
16202 | { uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
16203 | BusCyclePenalty += 2; | |
16204 | { int16_t src = m68k_read_memory_16(srca); | |
16205 | { int32_t dst = m68k_dreg(regs, dstreg); | |
16206 | m68k_incpc(4); | |
16207 | if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel1098; } else { | |
16208 | uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src; | |
16209 | uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src; | |
16210 | if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else | |
16211 | { | |
16212 | CLEAR_CZNV; | |
16213 | SET_ZFLG (((int16_t)(newv)) == 0); | |
16214 | SET_NFLG (((int16_t)(newv)) < 0); | |
16215 | newv = (newv & 0xffff) | ((uint32_t)rem << 16); | |
16216 | m68k_dreg(regs, dstreg) = (newv); | |
16217 | } | |
16218 | } | |
16219 | retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src); | |
16220 | }}}}endlabel1098: ; | |
16221 | return (14+retcycles); | |
16222 | } | |
16223 | unsigned long CPUFUNC(op_80f8_4)(uint32_t opcode) /* DIVU */ | |
16224 | { | |
16225 | uint32_t dstreg = (opcode >> 9) & 7; | |
16226 | unsigned int retcycles = 0; | |
16227 | OpcodeFamily = 60; CurrentInstrCycles = 12; | |
16228 | { uint32_t oldpc = m68k_getpc(); | |
16229 | { uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
16230 | { int16_t src = m68k_read_memory_16(srca); | |
16231 | { int32_t dst = m68k_dreg(regs, dstreg); | |
16232 | m68k_incpc(4); | |
16233 | if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel1099; } else { | |
16234 | uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src; | |
16235 | uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src; | |
16236 | if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else | |
16237 | { | |
16238 | CLEAR_CZNV; | |
16239 | SET_ZFLG (((int16_t)(newv)) == 0); | |
16240 | SET_NFLG (((int16_t)(newv)) < 0); | |
16241 | newv = (newv & 0xffff) | ((uint32_t)rem << 16); | |
16242 | m68k_dreg(regs, dstreg) = (newv); | |
16243 | } | |
16244 | } | |
16245 | retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src); | |
16246 | }}}}endlabel1099: ; | |
16247 | return (12+retcycles); | |
16248 | } | |
16249 | unsigned long CPUFUNC(op_80f9_4)(uint32_t opcode) /* DIVU */ | |
16250 | { | |
16251 | uint32_t dstreg = (opcode >> 9) & 7; | |
16252 | unsigned int retcycles = 0; | |
16253 | OpcodeFamily = 60; CurrentInstrCycles = 16; | |
16254 | { uint32_t oldpc = m68k_getpc(); | |
16255 | { uint32_t srca = get_ilong(2); | |
16256 | { int16_t src = m68k_read_memory_16(srca); | |
16257 | { int32_t dst = m68k_dreg(regs, dstreg); | |
16258 | m68k_incpc(6); | |
16259 | if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel1100; } else { | |
16260 | uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src; | |
16261 | uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src; | |
16262 | if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else | |
16263 | { | |
16264 | CLEAR_CZNV; | |
16265 | SET_ZFLG (((int16_t)(newv)) == 0); | |
16266 | SET_NFLG (((int16_t)(newv)) < 0); | |
16267 | newv = (newv & 0xffff) | ((uint32_t)rem << 16); | |
16268 | m68k_dreg(regs, dstreg) = (newv); | |
16269 | } | |
16270 | } | |
16271 | retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src); | |
16272 | }}}}endlabel1100: ; | |
16273 | return (16+retcycles); | |
16274 | } | |
16275 | unsigned long CPUFUNC(op_80fa_4)(uint32_t opcode) /* DIVU */ | |
16276 | { | |
16277 | uint32_t dstreg = (opcode >> 9) & 7; | |
16278 | unsigned int retcycles = 0; | |
16279 | OpcodeFamily = 60; CurrentInstrCycles = 12; | |
16280 | { uint32_t oldpc = m68k_getpc(); | |
16281 | { uint32_t srca = m68k_getpc () + 2; | |
16282 | srca += (int32_t)(int16_t)get_iword(2); | |
16283 | { int16_t src = m68k_read_memory_16(srca); | |
16284 | { int32_t dst = m68k_dreg(regs, dstreg); | |
16285 | m68k_incpc(4); | |
16286 | if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel1101; } else { | |
16287 | uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src; | |
16288 | uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src; | |
16289 | if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else | |
16290 | { | |
16291 | CLEAR_CZNV; | |
16292 | SET_ZFLG (((int16_t)(newv)) == 0); | |
16293 | SET_NFLG (((int16_t)(newv)) < 0); | |
16294 | newv = (newv & 0xffff) | ((uint32_t)rem << 16); | |
16295 | m68k_dreg(regs, dstreg) = (newv); | |
16296 | } | |
16297 | } | |
16298 | retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src); | |
16299 | }}}}endlabel1101: ; | |
16300 | return (12+retcycles); | |
16301 | } | |
16302 | unsigned long CPUFUNC(op_80fb_4)(uint32_t opcode) /* DIVU */ | |
16303 | { | |
16304 | uint32_t dstreg = (opcode >> 9) & 7; | |
16305 | unsigned int retcycles = 0; | |
16306 | OpcodeFamily = 60; CurrentInstrCycles = 14; | |
16307 | { uint32_t oldpc = m68k_getpc(); | |
16308 | { uint32_t tmppc = m68k_getpc() + 2; | |
16309 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
16310 | BusCyclePenalty += 2; | |
16311 | { int16_t src = m68k_read_memory_16(srca); | |
16312 | { int32_t dst = m68k_dreg(regs, dstreg); | |
16313 | m68k_incpc(4); | |
16314 | if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel1102; } else { | |
16315 | uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src; | |
16316 | uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src; | |
16317 | if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else | |
16318 | { | |
16319 | CLEAR_CZNV; | |
16320 | SET_ZFLG (((int16_t)(newv)) == 0); | |
16321 | SET_NFLG (((int16_t)(newv)) < 0); | |
16322 | newv = (newv & 0xffff) | ((uint32_t)rem << 16); | |
16323 | m68k_dreg(regs, dstreg) = (newv); | |
16324 | } | |
16325 | } | |
16326 | retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src); | |
16327 | }}}}endlabel1102: ; | |
16328 | return (14+retcycles); | |
16329 | } | |
16330 | unsigned long CPUFUNC(op_80fc_4)(uint32_t opcode) /* DIVU */ | |
16331 | { | |
16332 | uint32_t dstreg = (opcode >> 9) & 7; | |
16333 | unsigned int retcycles = 0; | |
16334 | OpcodeFamily = 60; CurrentInstrCycles = 8; | |
16335 | { uint32_t oldpc = m68k_getpc(); | |
16336 | { int16_t src = get_iword(2); | |
16337 | { int32_t dst = m68k_dreg(regs, dstreg); | |
16338 | m68k_incpc(4); | |
16339 | if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel1103; } else { | |
16340 | uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src; | |
16341 | uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src; | |
16342 | if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else | |
16343 | { | |
16344 | CLEAR_CZNV; | |
16345 | SET_ZFLG (((int16_t)(newv)) == 0); | |
16346 | SET_NFLG (((int16_t)(newv)) < 0); | |
16347 | newv = (newv & 0xffff) | ((uint32_t)rem << 16); | |
16348 | m68k_dreg(regs, dstreg) = (newv); | |
16349 | } | |
16350 | } | |
16351 | retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src); | |
16352 | }}}endlabel1103: ; | |
16353 | return (8+retcycles); | |
16354 | } | |
16355 | unsigned long CPUFUNC(op_8100_4)(uint32_t opcode) /* SBCD */ | |
16356 | { | |
16357 | uint32_t srcreg = (opcode & 7); | |
16358 | uint32_t dstreg = (opcode >> 9) & 7; | |
16359 | OpcodeFamily = 10; CurrentInstrCycles = 6; | |
16360 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
16361 | { int8_t dst = m68k_dreg(regs, dstreg); | |
16362 | { uint16_t newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG ? 1 : 0); | |
16363 | uint16_t newv_hi = (dst & 0xF0) - (src & 0xF0); | |
16364 | uint16_t newv, tmp_newv; | |
16365 | int bcd = 0; | |
16366 | newv = tmp_newv = newv_hi + newv_lo; | |
16367 | if (newv_lo & 0xF0) { newv -= 6; bcd = 6; }; | |
16368 | if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; } | |
16369 | SET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG ? 1 : 0)) & 0x300) > 0xFF); | |
16370 | COPY_CARRY; | |
16371 | SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); | |
16372 | SET_NFLG (((int8_t)(newv)) < 0); | |
16373 | SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0); | |
16374 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
16375 | }}}}m68k_incpc(2); | |
16376 | return 6; | |
16377 | } | |
16378 | unsigned long CPUFUNC(op_8108_4)(uint32_t opcode) /* SBCD */ | |
16379 | { | |
16380 | uint32_t srcreg = (opcode & 7); | |
16381 | uint32_t dstreg = (opcode >> 9) & 7; | |
16382 | OpcodeFamily = 10; CurrentInstrCycles = 18; | |
16383 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
16384 | { int8_t src = m68k_read_memory_8(srca); | |
16385 | m68k_areg (regs, srcreg) = srca; | |
16386 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
16387 | { int8_t dst = m68k_read_memory_8(dsta); | |
16388 | m68k_areg (regs, dstreg) = dsta; | |
16389 | { uint16_t newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG ? 1 : 0); | |
16390 | uint16_t newv_hi = (dst & 0xF0) - (src & 0xF0); | |
16391 | uint16_t newv, tmp_newv; | |
16392 | int bcd = 0; | |
16393 | newv = tmp_newv = newv_hi + newv_lo; | |
16394 | if (newv_lo & 0xF0) { newv -= 6; bcd = 6; }; | |
16395 | if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; } | |
16396 | SET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG ? 1 : 0)) & 0x300) > 0xFF); | |
16397 | COPY_CARRY; | |
16398 | SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); | |
16399 | SET_NFLG (((int8_t)(newv)) < 0); | |
16400 | SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0); | |
16401 | m68k_write_memory_8(dsta,newv); | |
16402 | }}}}}}m68k_incpc(2); | |
16403 | return 18; | |
16404 | } | |
16405 | unsigned long CPUFUNC(op_8110_4)(uint32_t opcode) /* OR */ | |
16406 | { | |
16407 | uint32_t srcreg = ((opcode >> 9) & 7); | |
16408 | uint32_t dstreg = opcode & 7; | |
16409 | OpcodeFamily = 1; CurrentInstrCycles = 12; | |
16410 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
16411 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
16412 | { int8_t dst = m68k_read_memory_8(dsta); | |
16413 | src |= dst; | |
16414 | CLEAR_CZNV; | |
16415 | SET_ZFLG (((int8_t)(src)) == 0); | |
16416 | SET_NFLG (((int8_t)(src)) < 0); | |
16417 | m68k_write_memory_8(dsta,src); | |
16418 | }}}}m68k_incpc(2); | |
16419 | return 12; | |
16420 | } | |
16421 | unsigned long CPUFUNC(op_8118_4)(uint32_t opcode) /* OR */ | |
16422 | { | |
16423 | uint32_t srcreg = ((opcode >> 9) & 7); | |
16424 | uint32_t dstreg = opcode & 7; | |
16425 | OpcodeFamily = 1; CurrentInstrCycles = 12; | |
16426 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
16427 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
16428 | { int8_t dst = m68k_read_memory_8(dsta); | |
16429 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
16430 | src |= dst; | |
16431 | CLEAR_CZNV; | |
16432 | SET_ZFLG (((int8_t)(src)) == 0); | |
16433 | SET_NFLG (((int8_t)(src)) < 0); | |
16434 | m68k_write_memory_8(dsta,src); | |
16435 | }}}}m68k_incpc(2); | |
16436 | return 12; | |
16437 | } | |
16438 | unsigned long CPUFUNC(op_8120_4)(uint32_t opcode) /* OR */ | |
16439 | { | |
16440 | uint32_t srcreg = ((opcode >> 9) & 7); | |
16441 | uint32_t dstreg = opcode & 7; | |
16442 | OpcodeFamily = 1; CurrentInstrCycles = 14; | |
16443 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
16444 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
16445 | { int8_t dst = m68k_read_memory_8(dsta); | |
16446 | m68k_areg (regs, dstreg) = dsta; | |
16447 | src |= dst; | |
16448 | CLEAR_CZNV; | |
16449 | SET_ZFLG (((int8_t)(src)) == 0); | |
16450 | SET_NFLG (((int8_t)(src)) < 0); | |
16451 | m68k_write_memory_8(dsta,src); | |
16452 | }}}}m68k_incpc(2); | |
16453 | return 14; | |
16454 | } | |
16455 | unsigned long CPUFUNC(op_8128_4)(uint32_t opcode) /* OR */ | |
16456 | { | |
16457 | uint32_t srcreg = ((opcode >> 9) & 7); | |
16458 | uint32_t dstreg = opcode & 7; | |
16459 | OpcodeFamily = 1; CurrentInstrCycles = 16; | |
16460 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
16461 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); | |
16462 | { int8_t dst = m68k_read_memory_8(dsta); | |
16463 | src |= dst; | |
16464 | CLEAR_CZNV; | |
16465 | SET_ZFLG (((int8_t)(src)) == 0); | |
16466 | SET_NFLG (((int8_t)(src)) < 0); | |
16467 | m68k_write_memory_8(dsta,src); | |
16468 | }}}}m68k_incpc(4); | |
16469 | return 16; | |
16470 | } | |
16471 | unsigned long CPUFUNC(op_8130_4)(uint32_t opcode) /* OR */ | |
16472 | { | |
16473 | uint32_t srcreg = ((opcode >> 9) & 7); | |
16474 | uint32_t dstreg = opcode & 7; | |
16475 | OpcodeFamily = 1; CurrentInstrCycles = 18; | |
16476 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
16477 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); | |
16478 | BusCyclePenalty += 2; | |
16479 | { int8_t dst = m68k_read_memory_8(dsta); | |
16480 | src |= dst; | |
16481 | CLEAR_CZNV; | |
16482 | SET_ZFLG (((int8_t)(src)) == 0); | |
16483 | SET_NFLG (((int8_t)(src)) < 0); | |
16484 | m68k_write_memory_8(dsta,src); | |
16485 | }}}}m68k_incpc(4); | |
16486 | return 18; | |
16487 | } | |
16488 | unsigned long CPUFUNC(op_8138_4)(uint32_t opcode) /* OR */ | |
16489 | { | |
16490 | uint32_t srcreg = ((opcode >> 9) & 7); | |
16491 | OpcodeFamily = 1; CurrentInstrCycles = 16; | |
16492 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
16493 | { uint32_t dsta = (int32_t)(int16_t)get_iword(2); | |
16494 | { int8_t dst = m68k_read_memory_8(dsta); | |
16495 | src |= dst; | |
16496 | CLEAR_CZNV; | |
16497 | SET_ZFLG (((int8_t)(src)) == 0); | |
16498 | SET_NFLG (((int8_t)(src)) < 0); | |
16499 | m68k_write_memory_8(dsta,src); | |
16500 | }}}}m68k_incpc(4); | |
16501 | return 16; | |
16502 | } | |
16503 | unsigned long CPUFUNC(op_8139_4)(uint32_t opcode) /* OR */ | |
16504 | { | |
16505 | uint32_t srcreg = ((opcode >> 9) & 7); | |
16506 | OpcodeFamily = 1; CurrentInstrCycles = 20; | |
16507 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
16508 | { uint32_t dsta = get_ilong(2); | |
16509 | { int8_t dst = m68k_read_memory_8(dsta); | |
16510 | src |= dst; | |
16511 | CLEAR_CZNV; | |
16512 | SET_ZFLG (((int8_t)(src)) == 0); | |
16513 | SET_NFLG (((int8_t)(src)) < 0); | |
16514 | m68k_write_memory_8(dsta,src); | |
16515 | }}}}m68k_incpc(6); | |
16516 | return 20; | |
16517 | } | |
16518 | unsigned long CPUFUNC(op_8150_4)(uint32_t opcode) /* OR */ | |
16519 | { | |
16520 | uint32_t srcreg = ((opcode >> 9) & 7); | |
16521 | uint32_t dstreg = opcode & 7; | |
16522 | OpcodeFamily = 1; CurrentInstrCycles = 12; | |
16523 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
16524 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
16525 | { int16_t dst = m68k_read_memory_16(dsta); | |
16526 | src |= dst; | |
16527 | CLEAR_CZNV; | |
16528 | SET_ZFLG (((int16_t)(src)) == 0); | |
16529 | SET_NFLG (((int16_t)(src)) < 0); | |
16530 | m68k_write_memory_16(dsta,src); | |
16531 | }}}}m68k_incpc(2); | |
16532 | return 12; | |
16533 | } | |
16534 | unsigned long CPUFUNC(op_8158_4)(uint32_t opcode) /* OR */ | |
16535 | { | |
16536 | uint32_t srcreg = ((opcode >> 9) & 7); | |
16537 | uint32_t dstreg = opcode & 7; | |
16538 | OpcodeFamily = 1; CurrentInstrCycles = 12; | |
16539 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
16540 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
16541 | { int16_t dst = m68k_read_memory_16(dsta); | |
16542 | m68k_areg(regs, dstreg) += 2; | |
16543 | src |= dst; | |
16544 | CLEAR_CZNV; | |
16545 | SET_ZFLG (((int16_t)(src)) == 0); | |
16546 | SET_NFLG (((int16_t)(src)) < 0); | |
16547 | m68k_write_memory_16(dsta,src); | |
16548 | }}}}m68k_incpc(2); | |
16549 | return 12; | |
16550 | } | |
16551 | unsigned long CPUFUNC(op_8160_4)(uint32_t opcode) /* OR */ | |
16552 | { | |
16553 | uint32_t srcreg = ((opcode >> 9) & 7); | |
16554 | uint32_t dstreg = opcode & 7; | |
16555 | OpcodeFamily = 1; CurrentInstrCycles = 14; | |
16556 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
16557 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
16558 | { int16_t dst = m68k_read_memory_16(dsta); | |
16559 | m68k_areg (regs, dstreg) = dsta; | |
16560 | src |= dst; | |
16561 | CLEAR_CZNV; | |
16562 | SET_ZFLG (((int16_t)(src)) == 0); | |
16563 | SET_NFLG (((int16_t)(src)) < 0); | |
16564 | m68k_write_memory_16(dsta,src); | |
16565 | }}}}m68k_incpc(2); | |
16566 | return 14; | |
16567 | } | |
16568 | unsigned long CPUFUNC(op_8168_4)(uint32_t opcode) /* OR */ | |
16569 | { | |
16570 | uint32_t srcreg = ((opcode >> 9) & 7); | |
16571 | uint32_t dstreg = opcode & 7; | |
16572 | OpcodeFamily = 1; CurrentInstrCycles = 16; | |
16573 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
16574 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); | |
16575 | { int16_t dst = m68k_read_memory_16(dsta); | |
16576 | src |= dst; | |
16577 | CLEAR_CZNV; | |
16578 | SET_ZFLG (((int16_t)(src)) == 0); | |
16579 | SET_NFLG (((int16_t)(src)) < 0); | |
16580 | m68k_write_memory_16(dsta,src); | |
16581 | }}}}m68k_incpc(4); | |
16582 | return 16; | |
16583 | } | |
16584 | unsigned long CPUFUNC(op_8170_4)(uint32_t opcode) /* OR */ | |
16585 | { | |
16586 | uint32_t srcreg = ((opcode >> 9) & 7); | |
16587 | uint32_t dstreg = opcode & 7; | |
16588 | OpcodeFamily = 1; CurrentInstrCycles = 18; | |
16589 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
16590 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); | |
16591 | BusCyclePenalty += 2; | |
16592 | { int16_t dst = m68k_read_memory_16(dsta); | |
16593 | src |= dst; | |
16594 | CLEAR_CZNV; | |
16595 | SET_ZFLG (((int16_t)(src)) == 0); | |
16596 | SET_NFLG (((int16_t)(src)) < 0); | |
16597 | m68k_write_memory_16(dsta,src); | |
16598 | }}}}m68k_incpc(4); | |
16599 | return 18; | |
16600 | } | |
16601 | unsigned long CPUFUNC(op_8178_4)(uint32_t opcode) /* OR */ | |
16602 | { | |
16603 | uint32_t srcreg = ((opcode >> 9) & 7); | |
16604 | OpcodeFamily = 1; CurrentInstrCycles = 16; | |
16605 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
16606 | { uint32_t dsta = (int32_t)(int16_t)get_iword(2); | |
16607 | { int16_t dst = m68k_read_memory_16(dsta); | |
16608 | src |= dst; | |
16609 | CLEAR_CZNV; | |
16610 | SET_ZFLG (((int16_t)(src)) == 0); | |
16611 | SET_NFLG (((int16_t)(src)) < 0); | |
16612 | m68k_write_memory_16(dsta,src); | |
16613 | }}}}m68k_incpc(4); | |
16614 | return 16; | |
16615 | } | |
16616 | unsigned long CPUFUNC(op_8179_4)(uint32_t opcode) /* OR */ | |
16617 | { | |
16618 | uint32_t srcreg = ((opcode >> 9) & 7); | |
16619 | OpcodeFamily = 1; CurrentInstrCycles = 20; | |
16620 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
16621 | { uint32_t dsta = get_ilong(2); | |
16622 | { int16_t dst = m68k_read_memory_16(dsta); | |
16623 | src |= dst; | |
16624 | CLEAR_CZNV; | |
16625 | SET_ZFLG (((int16_t)(src)) == 0); | |
16626 | SET_NFLG (((int16_t)(src)) < 0); | |
16627 | m68k_write_memory_16(dsta,src); | |
16628 | }}}}m68k_incpc(6); | |
16629 | return 20; | |
16630 | } | |
16631 | unsigned long CPUFUNC(op_8190_4)(uint32_t opcode) /* OR */ | |
16632 | { | |
16633 | uint32_t srcreg = ((opcode >> 9) & 7); | |
16634 | uint32_t dstreg = opcode & 7; | |
16635 | OpcodeFamily = 1; CurrentInstrCycles = 20; | |
16636 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
16637 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
16638 | { int32_t dst = m68k_read_memory_32(dsta); | |
16639 | src |= dst; | |
16640 | CLEAR_CZNV; | |
16641 | SET_ZFLG (((int32_t)(src)) == 0); | |
16642 | SET_NFLG (((int32_t)(src)) < 0); | |
16643 | m68k_write_memory_32(dsta,src); | |
16644 | }}}}m68k_incpc(2); | |
16645 | return 20; | |
16646 | } | |
16647 | unsigned long CPUFUNC(op_8198_4)(uint32_t opcode) /* OR */ | |
16648 | { | |
16649 | uint32_t srcreg = ((opcode >> 9) & 7); | |
16650 | uint32_t dstreg = opcode & 7; | |
16651 | OpcodeFamily = 1; CurrentInstrCycles = 20; | |
16652 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
16653 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
16654 | { int32_t dst = m68k_read_memory_32(dsta); | |
16655 | m68k_areg(regs, dstreg) += 4; | |
16656 | src |= dst; | |
16657 | CLEAR_CZNV; | |
16658 | SET_ZFLG (((int32_t)(src)) == 0); | |
16659 | SET_NFLG (((int32_t)(src)) < 0); | |
16660 | m68k_write_memory_32(dsta,src); | |
16661 | }}}}m68k_incpc(2); | |
16662 | return 20; | |
16663 | } | |
16664 | unsigned long CPUFUNC(op_81a0_4)(uint32_t opcode) /* OR */ | |
16665 | { | |
16666 | uint32_t srcreg = ((opcode >> 9) & 7); | |
16667 | uint32_t dstreg = opcode & 7; | |
16668 | OpcodeFamily = 1; CurrentInstrCycles = 22; | |
16669 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
16670 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
16671 | { int32_t dst = m68k_read_memory_32(dsta); | |
16672 | m68k_areg (regs, dstreg) = dsta; | |
16673 | src |= dst; | |
16674 | CLEAR_CZNV; | |
16675 | SET_ZFLG (((int32_t)(src)) == 0); | |
16676 | SET_NFLG (((int32_t)(src)) < 0); | |
16677 | m68k_write_memory_32(dsta,src); | |
16678 | }}}}m68k_incpc(2); | |
16679 | return 22; | |
16680 | } | |
16681 | unsigned long CPUFUNC(op_81a8_4)(uint32_t opcode) /* OR */ | |
16682 | { | |
16683 | uint32_t srcreg = ((opcode >> 9) & 7); | |
16684 | uint32_t dstreg = opcode & 7; | |
16685 | OpcodeFamily = 1; CurrentInstrCycles = 24; | |
16686 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
16687 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); | |
16688 | { int32_t dst = m68k_read_memory_32(dsta); | |
16689 | src |= dst; | |
16690 | CLEAR_CZNV; | |
16691 | SET_ZFLG (((int32_t)(src)) == 0); | |
16692 | SET_NFLG (((int32_t)(src)) < 0); | |
16693 | m68k_write_memory_32(dsta,src); | |
16694 | }}}}m68k_incpc(4); | |
16695 | return 24; | |
16696 | } | |
16697 | unsigned long CPUFUNC(op_81b0_4)(uint32_t opcode) /* OR */ | |
16698 | { | |
16699 | uint32_t srcreg = ((opcode >> 9) & 7); | |
16700 | uint32_t dstreg = opcode & 7; | |
16701 | OpcodeFamily = 1; CurrentInstrCycles = 26; | |
16702 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
16703 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); | |
16704 | BusCyclePenalty += 2; | |
16705 | { int32_t dst = m68k_read_memory_32(dsta); | |
16706 | src |= dst; | |
16707 | CLEAR_CZNV; | |
16708 | SET_ZFLG (((int32_t)(src)) == 0); | |
16709 | SET_NFLG (((int32_t)(src)) < 0); | |
16710 | m68k_write_memory_32(dsta,src); | |
16711 | }}}}m68k_incpc(4); | |
16712 | return 26; | |
16713 | } | |
16714 | unsigned long CPUFUNC(op_81b8_4)(uint32_t opcode) /* OR */ | |
16715 | { | |
16716 | uint32_t srcreg = ((opcode >> 9) & 7); | |
16717 | OpcodeFamily = 1; CurrentInstrCycles = 24; | |
16718 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
16719 | { uint32_t dsta = (int32_t)(int16_t)get_iword(2); | |
16720 | { int32_t dst = m68k_read_memory_32(dsta); | |
16721 | src |= dst; | |
16722 | CLEAR_CZNV; | |
16723 | SET_ZFLG (((int32_t)(src)) == 0); | |
16724 | SET_NFLG (((int32_t)(src)) < 0); | |
16725 | m68k_write_memory_32(dsta,src); | |
16726 | }}}}m68k_incpc(4); | |
16727 | return 24; | |
16728 | } | |
16729 | unsigned long CPUFUNC(op_81b9_4)(uint32_t opcode) /* OR */ | |
16730 | { | |
16731 | uint32_t srcreg = ((opcode >> 9) & 7); | |
16732 | OpcodeFamily = 1; CurrentInstrCycles = 28; | |
16733 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
16734 | { uint32_t dsta = get_ilong(2); | |
16735 | { int32_t dst = m68k_read_memory_32(dsta); | |
16736 | src |= dst; | |
16737 | CLEAR_CZNV; | |
16738 | SET_ZFLG (((int32_t)(src)) == 0); | |
16739 | SET_NFLG (((int32_t)(src)) < 0); | |
16740 | m68k_write_memory_32(dsta,src); | |
16741 | }}}}m68k_incpc(6); | |
16742 | return 28; | |
16743 | } | |
16744 | unsigned long CPUFUNC(op_81c0_4)(uint32_t opcode) /* DIVS */ | |
16745 | { | |
16746 | uint32_t srcreg = (opcode & 7); | |
16747 | uint32_t dstreg = (opcode >> 9) & 7; | |
16748 | unsigned int retcycles = 0; | |
16749 | OpcodeFamily = 61; CurrentInstrCycles = 4; | |
16750 | { uint32_t oldpc = m68k_getpc(); | |
16751 | { int16_t src = m68k_dreg(regs, srcreg); | |
16752 | { int32_t dst = m68k_dreg(regs, dstreg); | |
16753 | m68k_incpc(2); | |
16754 | if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel1127; } else { | |
16755 | int32_t newv = (int32_t)dst / (int32_t)(int16_t)src; | |
16756 | uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src; | |
16757 | if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else | |
16758 | { | |
16759 | if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem; | |
16760 | CLEAR_CZNV; | |
16761 | SET_ZFLG (((int16_t)(newv)) == 0); | |
16762 | SET_NFLG (((int16_t)(newv)) < 0); | |
16763 | newv = (newv & 0xffff) | ((uint32_t)rem << 16); | |
16764 | m68k_dreg(regs, dstreg) = (newv); | |
16765 | } | |
16766 | } | |
16767 | retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src); | |
16768 | }}}endlabel1127: ; | |
16769 | return (4+retcycles); | |
16770 | } | |
16771 | unsigned long CPUFUNC(op_81d0_4)(uint32_t opcode) /* DIVS */ | |
16772 | { | |
16773 | uint32_t srcreg = (opcode & 7); | |
16774 | uint32_t dstreg = (opcode >> 9) & 7; | |
16775 | unsigned int retcycles = 0; | |
16776 | OpcodeFamily = 61; CurrentInstrCycles = 8; | |
16777 | { uint32_t oldpc = m68k_getpc(); | |
16778 | { uint32_t srca = m68k_areg(regs, srcreg); | |
16779 | { int16_t src = m68k_read_memory_16(srca); | |
16780 | { int32_t dst = m68k_dreg(regs, dstreg); | |
16781 | m68k_incpc(2); | |
16782 | if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel1128; } else { | |
16783 | int32_t newv = (int32_t)dst / (int32_t)(int16_t)src; | |
16784 | uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src; | |
16785 | if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else | |
16786 | { | |
16787 | if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem; | |
16788 | CLEAR_CZNV; | |
16789 | SET_ZFLG (((int16_t)(newv)) == 0); | |
16790 | SET_NFLG (((int16_t)(newv)) < 0); | |
16791 | newv = (newv & 0xffff) | ((uint32_t)rem << 16); | |
16792 | m68k_dreg(regs, dstreg) = (newv); | |
16793 | } | |
16794 | } | |
16795 | retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src); | |
16796 | }}}}endlabel1128: ; | |
16797 | return (8+retcycles); | |
16798 | } | |
16799 | unsigned long CPUFUNC(op_81d8_4)(uint32_t opcode) /* DIVS */ | |
16800 | { | |
16801 | uint32_t srcreg = (opcode & 7); | |
16802 | uint32_t dstreg = (opcode >> 9) & 7; | |
16803 | unsigned int retcycles = 0; | |
16804 | OpcodeFamily = 61; CurrentInstrCycles = 8; | |
16805 | { uint32_t oldpc = m68k_getpc(); | |
16806 | { uint32_t srca = m68k_areg(regs, srcreg); | |
16807 | { int16_t src = m68k_read_memory_16(srca); | |
16808 | m68k_areg(regs, srcreg) += 2; | |
16809 | { int32_t dst = m68k_dreg(regs, dstreg); | |
16810 | m68k_incpc(2); | |
16811 | if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel1129; } else { | |
16812 | int32_t newv = (int32_t)dst / (int32_t)(int16_t)src; | |
16813 | uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src; | |
16814 | if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else | |
16815 | { | |
16816 | if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem; | |
16817 | CLEAR_CZNV; | |
16818 | SET_ZFLG (((int16_t)(newv)) == 0); | |
16819 | SET_NFLG (((int16_t)(newv)) < 0); | |
16820 | newv = (newv & 0xffff) | ((uint32_t)rem << 16); | |
16821 | m68k_dreg(regs, dstreg) = (newv); | |
16822 | } | |
16823 | } | |
16824 | retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src); | |
16825 | }}}}endlabel1129: ; | |
16826 | return (8+retcycles); | |
16827 | } | |
16828 | unsigned long CPUFUNC(op_81e0_4)(uint32_t opcode) /* DIVS */ | |
16829 | { | |
16830 | uint32_t srcreg = (opcode & 7); | |
16831 | uint32_t dstreg = (opcode >> 9) & 7; | |
16832 | unsigned int retcycles = 0; | |
16833 | OpcodeFamily = 61; CurrentInstrCycles = 10; | |
16834 | { uint32_t oldpc = m68k_getpc(); | |
16835 | { uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
16836 | { int16_t src = m68k_read_memory_16(srca); | |
16837 | m68k_areg (regs, srcreg) = srca; | |
16838 | { int32_t dst = m68k_dreg(regs, dstreg); | |
16839 | m68k_incpc(2); | |
16840 | if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel1130; } else { | |
16841 | int32_t newv = (int32_t)dst / (int32_t)(int16_t)src; | |
16842 | uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src; | |
16843 | if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else | |
16844 | { | |
16845 | if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem; | |
16846 | CLEAR_CZNV; | |
16847 | SET_ZFLG (((int16_t)(newv)) == 0); | |
16848 | SET_NFLG (((int16_t)(newv)) < 0); | |
16849 | newv = (newv & 0xffff) | ((uint32_t)rem << 16); | |
16850 | m68k_dreg(regs, dstreg) = (newv); | |
16851 | } | |
16852 | } | |
16853 | retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src); | |
16854 | }}}}endlabel1130: ; | |
16855 | return (10+retcycles); | |
16856 | } | |
16857 | unsigned long CPUFUNC(op_81e8_4)(uint32_t opcode) /* DIVS */ | |
16858 | { | |
16859 | uint32_t srcreg = (opcode & 7); | |
16860 | uint32_t dstreg = (opcode >> 9) & 7; | |
16861 | unsigned int retcycles = 0; | |
16862 | OpcodeFamily = 61; CurrentInstrCycles = 12; | |
16863 | { uint32_t oldpc = m68k_getpc(); | |
16864 | { uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
16865 | { int16_t src = m68k_read_memory_16(srca); | |
16866 | { int32_t dst = m68k_dreg(regs, dstreg); | |
16867 | m68k_incpc(4); | |
16868 | if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel1131; } else { | |
16869 | int32_t newv = (int32_t)dst / (int32_t)(int16_t)src; | |
16870 | uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src; | |
16871 | if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else | |
16872 | { | |
16873 | if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem; | |
16874 | CLEAR_CZNV; | |
16875 | SET_ZFLG (((int16_t)(newv)) == 0); | |
16876 | SET_NFLG (((int16_t)(newv)) < 0); | |
16877 | newv = (newv & 0xffff) | ((uint32_t)rem << 16); | |
16878 | m68k_dreg(regs, dstreg) = (newv); | |
16879 | } | |
16880 | } | |
16881 | retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src); | |
16882 | }}}}endlabel1131: ; | |
16883 | return (12+retcycles); | |
16884 | } | |
16885 | unsigned long CPUFUNC(op_81f0_4)(uint32_t opcode) /* DIVS */ | |
16886 | { | |
16887 | uint32_t srcreg = (opcode & 7); | |
16888 | uint32_t dstreg = (opcode >> 9) & 7; | |
16889 | unsigned int retcycles = 0; | |
16890 | OpcodeFamily = 61; CurrentInstrCycles = 14; | |
16891 | { uint32_t oldpc = m68k_getpc(); | |
16892 | { uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
16893 | BusCyclePenalty += 2; | |
16894 | { int16_t src = m68k_read_memory_16(srca); | |
16895 | { int32_t dst = m68k_dreg(regs, dstreg); | |
16896 | m68k_incpc(4); | |
16897 | if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel1132; } else { | |
16898 | int32_t newv = (int32_t)dst / (int32_t)(int16_t)src; | |
16899 | uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src; | |
16900 | if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else | |
16901 | { | |
16902 | if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem; | |
16903 | CLEAR_CZNV; | |
16904 | SET_ZFLG (((int16_t)(newv)) == 0); | |
16905 | SET_NFLG (((int16_t)(newv)) < 0); | |
16906 | newv = (newv & 0xffff) | ((uint32_t)rem << 16); | |
16907 | m68k_dreg(regs, dstreg) = (newv); | |
16908 | } | |
16909 | } | |
16910 | retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src); | |
16911 | }}}}endlabel1132: ; | |
16912 | return (14+retcycles); | |
16913 | } | |
16914 | unsigned long CPUFUNC(op_81f8_4)(uint32_t opcode) /* DIVS */ | |
16915 | { | |
16916 | uint32_t dstreg = (opcode >> 9) & 7; | |
16917 | unsigned int retcycles = 0; | |
16918 | OpcodeFamily = 61; CurrentInstrCycles = 12; | |
16919 | { uint32_t oldpc = m68k_getpc(); | |
16920 | { uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
16921 | { int16_t src = m68k_read_memory_16(srca); | |
16922 | { int32_t dst = m68k_dreg(regs, dstreg); | |
16923 | m68k_incpc(4); | |
16924 | if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel1133; } else { | |
16925 | int32_t newv = (int32_t)dst / (int32_t)(int16_t)src; | |
16926 | uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src; | |
16927 | if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else | |
16928 | { | |
16929 | if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem; | |
16930 | CLEAR_CZNV; | |
16931 | SET_ZFLG (((int16_t)(newv)) == 0); | |
16932 | SET_NFLG (((int16_t)(newv)) < 0); | |
16933 | newv = (newv & 0xffff) | ((uint32_t)rem << 16); | |
16934 | m68k_dreg(regs, dstreg) = (newv); | |
16935 | } | |
16936 | } | |
16937 | retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src); | |
16938 | }}}}endlabel1133: ; | |
16939 | return (12+retcycles); | |
16940 | } | |
16941 | unsigned long CPUFUNC(op_81f9_4)(uint32_t opcode) /* DIVS */ | |
16942 | { | |
16943 | uint32_t dstreg = (opcode >> 9) & 7; | |
16944 | unsigned int retcycles = 0; | |
16945 | OpcodeFamily = 61; CurrentInstrCycles = 16; | |
16946 | { uint32_t oldpc = m68k_getpc(); | |
16947 | { uint32_t srca = get_ilong(2); | |
16948 | { int16_t src = m68k_read_memory_16(srca); | |
16949 | { int32_t dst = m68k_dreg(regs, dstreg); | |
16950 | m68k_incpc(6); | |
16951 | if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel1134; } else { | |
16952 | int32_t newv = (int32_t)dst / (int32_t)(int16_t)src; | |
16953 | uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src; | |
16954 | if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else | |
16955 | { | |
16956 | if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem; | |
16957 | CLEAR_CZNV; | |
16958 | SET_ZFLG (((int16_t)(newv)) == 0); | |
16959 | SET_NFLG (((int16_t)(newv)) < 0); | |
16960 | newv = (newv & 0xffff) | ((uint32_t)rem << 16); | |
16961 | m68k_dreg(regs, dstreg) = (newv); | |
16962 | } | |
16963 | } | |
16964 | retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src); | |
16965 | }}}}endlabel1134: ; | |
16966 | return (16+retcycles); | |
16967 | } | |
16968 | unsigned long CPUFUNC(op_81fa_4)(uint32_t opcode) /* DIVS */ | |
16969 | { | |
16970 | uint32_t dstreg = (opcode >> 9) & 7; | |
16971 | unsigned int retcycles = 0; | |
16972 | OpcodeFamily = 61; CurrentInstrCycles = 12; | |
16973 | { uint32_t oldpc = m68k_getpc(); | |
16974 | { uint32_t srca = m68k_getpc () + 2; | |
16975 | srca += (int32_t)(int16_t)get_iword(2); | |
16976 | { int16_t src = m68k_read_memory_16(srca); | |
16977 | { int32_t dst = m68k_dreg(regs, dstreg); | |
16978 | m68k_incpc(4); | |
16979 | if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel1135; } else { | |
16980 | int32_t newv = (int32_t)dst / (int32_t)(int16_t)src; | |
16981 | uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src; | |
16982 | if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else | |
16983 | { | |
16984 | if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem; | |
16985 | CLEAR_CZNV; | |
16986 | SET_ZFLG (((int16_t)(newv)) == 0); | |
16987 | SET_NFLG (((int16_t)(newv)) < 0); | |
16988 | newv = (newv & 0xffff) | ((uint32_t)rem << 16); | |
16989 | m68k_dreg(regs, dstreg) = (newv); | |
16990 | } | |
16991 | } | |
16992 | retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src); | |
16993 | }}}}endlabel1135: ; | |
16994 | return (12+retcycles); | |
16995 | } | |
16996 | unsigned long CPUFUNC(op_81fb_4)(uint32_t opcode) /* DIVS */ | |
16997 | { | |
16998 | uint32_t dstreg = (opcode >> 9) & 7; | |
16999 | unsigned int retcycles = 0; | |
17000 | OpcodeFamily = 61; CurrentInstrCycles = 14; | |
17001 | { uint32_t oldpc = m68k_getpc(); | |
17002 | { uint32_t tmppc = m68k_getpc() + 2; | |
17003 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
17004 | BusCyclePenalty += 2; | |
17005 | { int16_t src = m68k_read_memory_16(srca); | |
17006 | { int32_t dst = m68k_dreg(regs, dstreg); | |
17007 | m68k_incpc(4); | |
17008 | if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel1136; } else { | |
17009 | int32_t newv = (int32_t)dst / (int32_t)(int16_t)src; | |
17010 | uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src; | |
17011 | if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else | |
17012 | { | |
17013 | if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem; | |
17014 | CLEAR_CZNV; | |
17015 | SET_ZFLG (((int16_t)(newv)) == 0); | |
17016 | SET_NFLG (((int16_t)(newv)) < 0); | |
17017 | newv = (newv & 0xffff) | ((uint32_t)rem << 16); | |
17018 | m68k_dreg(regs, dstreg) = (newv); | |
17019 | } | |
17020 | } | |
17021 | retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src); | |
17022 | }}}}endlabel1136: ; | |
17023 | return (14+retcycles); | |
17024 | } | |
17025 | unsigned long CPUFUNC(op_81fc_4)(uint32_t opcode) /* DIVS */ | |
17026 | { | |
17027 | uint32_t dstreg = (opcode >> 9) & 7; | |
17028 | unsigned int retcycles = 0; | |
17029 | OpcodeFamily = 61; CurrentInstrCycles = 8; | |
17030 | { uint32_t oldpc = m68k_getpc(); | |
17031 | { int16_t src = get_iword(2); | |
17032 | { int32_t dst = m68k_dreg(regs, dstreg); | |
17033 | m68k_incpc(4); | |
17034 | if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel1137; } else { | |
17035 | int32_t newv = (int32_t)dst / (int32_t)(int16_t)src; | |
17036 | uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src; | |
17037 | if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else | |
17038 | { | |
17039 | if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem; | |
17040 | CLEAR_CZNV; | |
17041 | SET_ZFLG (((int16_t)(newv)) == 0); | |
17042 | SET_NFLG (((int16_t)(newv)) < 0); | |
17043 | newv = (newv & 0xffff) | ((uint32_t)rem << 16); | |
17044 | m68k_dreg(regs, dstreg) = (newv); | |
17045 | } | |
17046 | } | |
17047 | retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src); | |
17048 | }}}endlabel1137: ; | |
17049 | return (8+retcycles); | |
17050 | } | |
17051 | unsigned long CPUFUNC(op_9000_4)(uint32_t opcode) /* SUB */ | |
17052 | { | |
17053 | uint32_t srcreg = (opcode & 7); | |
17054 | uint32_t dstreg = (opcode >> 9) & 7; | |
17055 | OpcodeFamily = 7; CurrentInstrCycles = 4; | |
17056 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
17057 | { int8_t dst = m68k_dreg(regs, dstreg); | |
17058 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
17059 | { int flgs = ((int8_t)(src)) < 0; | |
17060 | int flgo = ((int8_t)(dst)) < 0; | |
17061 | int flgn = ((int8_t)(newv)) < 0; | |
17062 | SET_ZFLG (((int8_t)(newv)) == 0); | |
17063 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
17064 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
17065 | COPY_CARRY; | |
17066 | SET_NFLG (flgn != 0); | |
17067 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
17068 | }}}}}}m68k_incpc(2); | |
17069 | return 4; | |
17070 | } | |
17071 | unsigned long CPUFUNC(op_9010_4)(uint32_t opcode) /* SUB */ | |
17072 | { | |
17073 | uint32_t srcreg = (opcode & 7); | |
17074 | uint32_t dstreg = (opcode >> 9) & 7; | |
17075 | OpcodeFamily = 7; CurrentInstrCycles = 8; | |
17076 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
17077 | { int8_t src = m68k_read_memory_8(srca); | |
17078 | { int8_t dst = m68k_dreg(regs, dstreg); | |
17079 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
17080 | { int flgs = ((int8_t)(src)) < 0; | |
17081 | int flgo = ((int8_t)(dst)) < 0; | |
17082 | int flgn = ((int8_t)(newv)) < 0; | |
17083 | SET_ZFLG (((int8_t)(newv)) == 0); | |
17084 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
17085 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
17086 | COPY_CARRY; | |
17087 | SET_NFLG (flgn != 0); | |
17088 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
17089 | }}}}}}}m68k_incpc(2); | |
17090 | return 8; | |
17091 | } | |
17092 | unsigned long CPUFUNC(op_9018_4)(uint32_t opcode) /* SUB */ | |
17093 | { | |
17094 | uint32_t srcreg = (opcode & 7); | |
17095 | uint32_t dstreg = (opcode >> 9) & 7; | |
17096 | OpcodeFamily = 7; CurrentInstrCycles = 8; | |
17097 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
17098 | { int8_t src = m68k_read_memory_8(srca); | |
17099 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
17100 | { int8_t dst = m68k_dreg(regs, dstreg); | |
17101 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
17102 | { int flgs = ((int8_t)(src)) < 0; | |
17103 | int flgo = ((int8_t)(dst)) < 0; | |
17104 | int flgn = ((int8_t)(newv)) < 0; | |
17105 | SET_ZFLG (((int8_t)(newv)) == 0); | |
17106 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
17107 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
17108 | COPY_CARRY; | |
17109 | SET_NFLG (flgn != 0); | |
17110 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
17111 | }}}}}}}m68k_incpc(2); | |
17112 | return 8; | |
17113 | } | |
17114 | unsigned long CPUFUNC(op_9020_4)(uint32_t opcode) /* SUB */ | |
17115 | { | |
17116 | uint32_t srcreg = (opcode & 7); | |
17117 | uint32_t dstreg = (opcode >> 9) & 7; | |
17118 | OpcodeFamily = 7; CurrentInstrCycles = 10; | |
17119 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
17120 | { int8_t src = m68k_read_memory_8(srca); | |
17121 | m68k_areg (regs, srcreg) = srca; | |
17122 | { int8_t dst = m68k_dreg(regs, dstreg); | |
17123 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
17124 | { int flgs = ((int8_t)(src)) < 0; | |
17125 | int flgo = ((int8_t)(dst)) < 0; | |
17126 | int flgn = ((int8_t)(newv)) < 0; | |
17127 | SET_ZFLG (((int8_t)(newv)) == 0); | |
17128 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
17129 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
17130 | COPY_CARRY; | |
17131 | SET_NFLG (flgn != 0); | |
17132 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
17133 | }}}}}}}m68k_incpc(2); | |
17134 | return 10; | |
17135 | } | |
17136 | unsigned long CPUFUNC(op_9028_4)(uint32_t opcode) /* SUB */ | |
17137 | { | |
17138 | uint32_t srcreg = (opcode & 7); | |
17139 | uint32_t dstreg = (opcode >> 9) & 7; | |
17140 | OpcodeFamily = 7; CurrentInstrCycles = 12; | |
17141 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
17142 | { int8_t src = m68k_read_memory_8(srca); | |
17143 | { int8_t dst = m68k_dreg(regs, dstreg); | |
17144 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
17145 | { int flgs = ((int8_t)(src)) < 0; | |
17146 | int flgo = ((int8_t)(dst)) < 0; | |
17147 | int flgn = ((int8_t)(newv)) < 0; | |
17148 | SET_ZFLG (((int8_t)(newv)) == 0); | |
17149 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
17150 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
17151 | COPY_CARRY; | |
17152 | SET_NFLG (flgn != 0); | |
17153 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
17154 | }}}}}}}m68k_incpc(4); | |
17155 | return 12; | |
17156 | } | |
17157 | unsigned long CPUFUNC(op_9030_4)(uint32_t opcode) /* SUB */ | |
17158 | { | |
17159 | uint32_t srcreg = (opcode & 7); | |
17160 | uint32_t dstreg = (opcode >> 9) & 7; | |
17161 | OpcodeFamily = 7; CurrentInstrCycles = 14; | |
17162 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
17163 | BusCyclePenalty += 2; | |
17164 | { int8_t src = m68k_read_memory_8(srca); | |
17165 | { int8_t dst = m68k_dreg(regs, dstreg); | |
17166 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
17167 | { int flgs = ((int8_t)(src)) < 0; | |
17168 | int flgo = ((int8_t)(dst)) < 0; | |
17169 | int flgn = ((int8_t)(newv)) < 0; | |
17170 | SET_ZFLG (((int8_t)(newv)) == 0); | |
17171 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
17172 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
17173 | COPY_CARRY; | |
17174 | SET_NFLG (flgn != 0); | |
17175 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
17176 | }}}}}}}m68k_incpc(4); | |
17177 | return 14; | |
17178 | } | |
17179 | unsigned long CPUFUNC(op_9038_4)(uint32_t opcode) /* SUB */ | |
17180 | { | |
17181 | uint32_t dstreg = (opcode >> 9) & 7; | |
17182 | OpcodeFamily = 7; CurrentInstrCycles = 12; | |
17183 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
17184 | { int8_t src = m68k_read_memory_8(srca); | |
17185 | { int8_t dst = m68k_dreg(regs, dstreg); | |
17186 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
17187 | { int flgs = ((int8_t)(src)) < 0; | |
17188 | int flgo = ((int8_t)(dst)) < 0; | |
17189 | int flgn = ((int8_t)(newv)) < 0; | |
17190 | SET_ZFLG (((int8_t)(newv)) == 0); | |
17191 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
17192 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
17193 | COPY_CARRY; | |
17194 | SET_NFLG (flgn != 0); | |
17195 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
17196 | }}}}}}}m68k_incpc(4); | |
17197 | return 12; | |
17198 | } | |
17199 | unsigned long CPUFUNC(op_9039_4)(uint32_t opcode) /* SUB */ | |
17200 | { | |
17201 | uint32_t dstreg = (opcode >> 9) & 7; | |
17202 | OpcodeFamily = 7; CurrentInstrCycles = 16; | |
17203 | {{ uint32_t srca = get_ilong(2); | |
17204 | { int8_t src = m68k_read_memory_8(srca); | |
17205 | { int8_t dst = m68k_dreg(regs, dstreg); | |
17206 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
17207 | { int flgs = ((int8_t)(src)) < 0; | |
17208 | int flgo = ((int8_t)(dst)) < 0; | |
17209 | int flgn = ((int8_t)(newv)) < 0; | |
17210 | SET_ZFLG (((int8_t)(newv)) == 0); | |
17211 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
17212 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
17213 | COPY_CARRY; | |
17214 | SET_NFLG (flgn != 0); | |
17215 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
17216 | }}}}}}}m68k_incpc(6); | |
17217 | return 16; | |
17218 | } | |
17219 | unsigned long CPUFUNC(op_903a_4)(uint32_t opcode) /* SUB */ | |
17220 | { | |
17221 | uint32_t dstreg = (opcode >> 9) & 7; | |
17222 | OpcodeFamily = 7; CurrentInstrCycles = 12; | |
17223 | {{ uint32_t srca = m68k_getpc () + 2; | |
17224 | srca += (int32_t)(int16_t)get_iword(2); | |
17225 | { int8_t src = m68k_read_memory_8(srca); | |
17226 | { int8_t dst = m68k_dreg(regs, dstreg); | |
17227 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
17228 | { int flgs = ((int8_t)(src)) < 0; | |
17229 | int flgo = ((int8_t)(dst)) < 0; | |
17230 | int flgn = ((int8_t)(newv)) < 0; | |
17231 | SET_ZFLG (((int8_t)(newv)) == 0); | |
17232 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
17233 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
17234 | COPY_CARRY; | |
17235 | SET_NFLG (flgn != 0); | |
17236 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
17237 | }}}}}}}m68k_incpc(4); | |
17238 | return 12; | |
17239 | } | |
17240 | unsigned long CPUFUNC(op_903b_4)(uint32_t opcode) /* SUB */ | |
17241 | { | |
17242 | uint32_t dstreg = (opcode >> 9) & 7; | |
17243 | OpcodeFamily = 7; CurrentInstrCycles = 14; | |
17244 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
17245 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
17246 | BusCyclePenalty += 2; | |
17247 | { int8_t src = m68k_read_memory_8(srca); | |
17248 | { int8_t dst = m68k_dreg(regs, dstreg); | |
17249 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
17250 | { int flgs = ((int8_t)(src)) < 0; | |
17251 | int flgo = ((int8_t)(dst)) < 0; | |
17252 | int flgn = ((int8_t)(newv)) < 0; | |
17253 | SET_ZFLG (((int8_t)(newv)) == 0); | |
17254 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
17255 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
17256 | COPY_CARRY; | |
17257 | SET_NFLG (flgn != 0); | |
17258 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
17259 | }}}}}}}m68k_incpc(4); | |
17260 | return 14; | |
17261 | } | |
17262 | unsigned long CPUFUNC(op_903c_4)(uint32_t opcode) /* SUB */ | |
17263 | { | |
17264 | uint32_t dstreg = (opcode >> 9) & 7; | |
17265 | OpcodeFamily = 7; CurrentInstrCycles = 8; | |
17266 | {{ int8_t src = get_ibyte(2); | |
17267 | { int8_t dst = m68k_dreg(regs, dstreg); | |
17268 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
17269 | { int flgs = ((int8_t)(src)) < 0; | |
17270 | int flgo = ((int8_t)(dst)) < 0; | |
17271 | int flgn = ((int8_t)(newv)) < 0; | |
17272 | SET_ZFLG (((int8_t)(newv)) == 0); | |
17273 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
17274 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
17275 | COPY_CARRY; | |
17276 | SET_NFLG (flgn != 0); | |
17277 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
17278 | }}}}}}m68k_incpc(4); | |
17279 | return 8; | |
17280 | } | |
17281 | unsigned long CPUFUNC(op_9040_4)(uint32_t opcode) /* SUB */ | |
17282 | { | |
17283 | uint32_t srcreg = (opcode & 7); | |
17284 | uint32_t dstreg = (opcode >> 9) & 7; | |
17285 | OpcodeFamily = 7; CurrentInstrCycles = 4; | |
17286 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
17287 | { int16_t dst = m68k_dreg(regs, dstreg); | |
17288 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
17289 | { int flgs = ((int16_t)(src)) < 0; | |
17290 | int flgo = ((int16_t)(dst)) < 0; | |
17291 | int flgn = ((int16_t)(newv)) < 0; | |
17292 | SET_ZFLG (((int16_t)(newv)) == 0); | |
17293 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
17294 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
17295 | COPY_CARRY; | |
17296 | SET_NFLG (flgn != 0); | |
17297 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
17298 | }}}}}}m68k_incpc(2); | |
17299 | return 4; | |
17300 | } | |
17301 | unsigned long CPUFUNC(op_9048_4)(uint32_t opcode) /* SUB */ | |
17302 | { | |
17303 | uint32_t srcreg = (opcode & 7); | |
17304 | uint32_t dstreg = (opcode >> 9) & 7; | |
17305 | OpcodeFamily = 7; CurrentInstrCycles = 4; | |
17306 | {{ int16_t src = m68k_areg(regs, srcreg); | |
17307 | { int16_t dst = m68k_dreg(regs, dstreg); | |
17308 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
17309 | { int flgs = ((int16_t)(src)) < 0; | |
17310 | int flgo = ((int16_t)(dst)) < 0; | |
17311 | int flgn = ((int16_t)(newv)) < 0; | |
17312 | SET_ZFLG (((int16_t)(newv)) == 0); | |
17313 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
17314 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
17315 | COPY_CARRY; | |
17316 | SET_NFLG (flgn != 0); | |
17317 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
17318 | }}}}}}m68k_incpc(2); | |
17319 | return 4; | |
17320 | } | |
17321 | unsigned long CPUFUNC(op_9050_4)(uint32_t opcode) /* SUB */ | |
17322 | { | |
17323 | uint32_t srcreg = (opcode & 7); | |
17324 | uint32_t dstreg = (opcode >> 9) & 7; | |
17325 | OpcodeFamily = 7; CurrentInstrCycles = 8; | |
17326 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
17327 | { int16_t src = m68k_read_memory_16(srca); | |
17328 | { int16_t dst = m68k_dreg(regs, dstreg); | |
17329 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
17330 | { int flgs = ((int16_t)(src)) < 0; | |
17331 | int flgo = ((int16_t)(dst)) < 0; | |
17332 | int flgn = ((int16_t)(newv)) < 0; | |
17333 | SET_ZFLG (((int16_t)(newv)) == 0); | |
17334 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
17335 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
17336 | COPY_CARRY; | |
17337 | SET_NFLG (flgn != 0); | |
17338 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
17339 | }}}}}}}m68k_incpc(2); | |
17340 | return 8; | |
17341 | } | |
17342 | unsigned long CPUFUNC(op_9058_4)(uint32_t opcode) /* SUB */ | |
17343 | { | |
17344 | uint32_t srcreg = (opcode & 7); | |
17345 | uint32_t dstreg = (opcode >> 9) & 7; | |
17346 | OpcodeFamily = 7; CurrentInstrCycles = 8; | |
17347 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
17348 | { int16_t src = m68k_read_memory_16(srca); | |
17349 | m68k_areg(regs, srcreg) += 2; | |
17350 | { int16_t dst = m68k_dreg(regs, dstreg); | |
17351 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
17352 | { int flgs = ((int16_t)(src)) < 0; | |
17353 | int flgo = ((int16_t)(dst)) < 0; | |
17354 | int flgn = ((int16_t)(newv)) < 0; | |
17355 | SET_ZFLG (((int16_t)(newv)) == 0); | |
17356 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
17357 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
17358 | COPY_CARRY; | |
17359 | SET_NFLG (flgn != 0); | |
17360 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
17361 | }}}}}}}m68k_incpc(2); | |
17362 | return 8; | |
17363 | } | |
17364 | unsigned long CPUFUNC(op_9060_4)(uint32_t opcode) /* SUB */ | |
17365 | { | |
17366 | uint32_t srcreg = (opcode & 7); | |
17367 | uint32_t dstreg = (opcode >> 9) & 7; | |
17368 | OpcodeFamily = 7; CurrentInstrCycles = 10; | |
17369 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
17370 | { int16_t src = m68k_read_memory_16(srca); | |
17371 | m68k_areg (regs, srcreg) = srca; | |
17372 | { int16_t dst = m68k_dreg(regs, dstreg); | |
17373 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
17374 | { int flgs = ((int16_t)(src)) < 0; | |
17375 | int flgo = ((int16_t)(dst)) < 0; | |
17376 | int flgn = ((int16_t)(newv)) < 0; | |
17377 | SET_ZFLG (((int16_t)(newv)) == 0); | |
17378 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
17379 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
17380 | COPY_CARRY; | |
17381 | SET_NFLG (flgn != 0); | |
17382 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
17383 | }}}}}}}m68k_incpc(2); | |
17384 | return 10; | |
17385 | } | |
17386 | unsigned long CPUFUNC(op_9068_4)(uint32_t opcode) /* SUB */ | |
17387 | { | |
17388 | uint32_t srcreg = (opcode & 7); | |
17389 | uint32_t dstreg = (opcode >> 9) & 7; | |
17390 | OpcodeFamily = 7; CurrentInstrCycles = 12; | |
17391 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
17392 | { int16_t src = m68k_read_memory_16(srca); | |
17393 | { int16_t dst = m68k_dreg(regs, dstreg); | |
17394 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
17395 | { int flgs = ((int16_t)(src)) < 0; | |
17396 | int flgo = ((int16_t)(dst)) < 0; | |
17397 | int flgn = ((int16_t)(newv)) < 0; | |
17398 | SET_ZFLG (((int16_t)(newv)) == 0); | |
17399 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
17400 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
17401 | COPY_CARRY; | |
17402 | SET_NFLG (flgn != 0); | |
17403 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
17404 | }}}}}}}m68k_incpc(4); | |
17405 | return 12; | |
17406 | } | |
17407 | unsigned long CPUFUNC(op_9070_4)(uint32_t opcode) /* SUB */ | |
17408 | { | |
17409 | uint32_t srcreg = (opcode & 7); | |
17410 | uint32_t dstreg = (opcode >> 9) & 7; | |
17411 | OpcodeFamily = 7; CurrentInstrCycles = 14; | |
17412 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
17413 | BusCyclePenalty += 2; | |
17414 | { int16_t src = m68k_read_memory_16(srca); | |
17415 | { int16_t dst = m68k_dreg(regs, dstreg); | |
17416 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
17417 | { int flgs = ((int16_t)(src)) < 0; | |
17418 | int flgo = ((int16_t)(dst)) < 0; | |
17419 | int flgn = ((int16_t)(newv)) < 0; | |
17420 | SET_ZFLG (((int16_t)(newv)) == 0); | |
17421 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
17422 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
17423 | COPY_CARRY; | |
17424 | SET_NFLG (flgn != 0); | |
17425 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
17426 | }}}}}}}m68k_incpc(4); | |
17427 | return 14; | |
17428 | } | |
17429 | unsigned long CPUFUNC(op_9078_4)(uint32_t opcode) /* SUB */ | |
17430 | { | |
17431 | uint32_t dstreg = (opcode >> 9) & 7; | |
17432 | OpcodeFamily = 7; CurrentInstrCycles = 12; | |
17433 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
17434 | { int16_t src = m68k_read_memory_16(srca); | |
17435 | { int16_t dst = m68k_dreg(regs, dstreg); | |
17436 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
17437 | { int flgs = ((int16_t)(src)) < 0; | |
17438 | int flgo = ((int16_t)(dst)) < 0; | |
17439 | int flgn = ((int16_t)(newv)) < 0; | |
17440 | SET_ZFLG (((int16_t)(newv)) == 0); | |
17441 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
17442 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
17443 | COPY_CARRY; | |
17444 | SET_NFLG (flgn != 0); | |
17445 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
17446 | }}}}}}}m68k_incpc(4); | |
17447 | return 12; | |
17448 | } | |
17449 | unsigned long CPUFUNC(op_9079_4)(uint32_t opcode) /* SUB */ | |
17450 | { | |
17451 | uint32_t dstreg = (opcode >> 9) & 7; | |
17452 | OpcodeFamily = 7; CurrentInstrCycles = 16; | |
17453 | {{ uint32_t srca = get_ilong(2); | |
17454 | { int16_t src = m68k_read_memory_16(srca); | |
17455 | { int16_t dst = m68k_dreg(regs, dstreg); | |
17456 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
17457 | { int flgs = ((int16_t)(src)) < 0; | |
17458 | int flgo = ((int16_t)(dst)) < 0; | |
17459 | int flgn = ((int16_t)(newv)) < 0; | |
17460 | SET_ZFLG (((int16_t)(newv)) == 0); | |
17461 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
17462 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
17463 | COPY_CARRY; | |
17464 | SET_NFLG (flgn != 0); | |
17465 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
17466 | }}}}}}}m68k_incpc(6); | |
17467 | return 16; | |
17468 | } | |
17469 | unsigned long CPUFUNC(op_907a_4)(uint32_t opcode) /* SUB */ | |
17470 | { | |
17471 | uint32_t dstreg = (opcode >> 9) & 7; | |
17472 | OpcodeFamily = 7; CurrentInstrCycles = 12; | |
17473 | {{ uint32_t srca = m68k_getpc () + 2; | |
17474 | srca += (int32_t)(int16_t)get_iword(2); | |
17475 | { int16_t src = m68k_read_memory_16(srca); | |
17476 | { int16_t dst = m68k_dreg(regs, dstreg); | |
17477 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
17478 | { int flgs = ((int16_t)(src)) < 0; | |
17479 | int flgo = ((int16_t)(dst)) < 0; | |
17480 | int flgn = ((int16_t)(newv)) < 0; | |
17481 | SET_ZFLG (((int16_t)(newv)) == 0); | |
17482 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
17483 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
17484 | COPY_CARRY; | |
17485 | SET_NFLG (flgn != 0); | |
17486 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
17487 | }}}}}}}m68k_incpc(4); | |
17488 | return 12; | |
17489 | } | |
17490 | unsigned long CPUFUNC(op_907b_4)(uint32_t opcode) /* SUB */ | |
17491 | { | |
17492 | uint32_t dstreg = (opcode >> 9) & 7; | |
17493 | OpcodeFamily = 7; CurrentInstrCycles = 14; | |
17494 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
17495 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
17496 | BusCyclePenalty += 2; | |
17497 | { int16_t src = m68k_read_memory_16(srca); | |
17498 | { int16_t dst = m68k_dreg(regs, dstreg); | |
17499 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
17500 | { int flgs = ((int16_t)(src)) < 0; | |
17501 | int flgo = ((int16_t)(dst)) < 0; | |
17502 | int flgn = ((int16_t)(newv)) < 0; | |
17503 | SET_ZFLG (((int16_t)(newv)) == 0); | |
17504 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
17505 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
17506 | COPY_CARRY; | |
17507 | SET_NFLG (flgn != 0); | |
17508 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
17509 | }}}}}}}m68k_incpc(4); | |
17510 | return 14; | |
17511 | } | |
17512 | unsigned long CPUFUNC(op_907c_4)(uint32_t opcode) /* SUB */ | |
17513 | { | |
17514 | uint32_t dstreg = (opcode >> 9) & 7; | |
17515 | OpcodeFamily = 7; CurrentInstrCycles = 8; | |
17516 | {{ int16_t src = get_iword(2); | |
17517 | { int16_t dst = m68k_dreg(regs, dstreg); | |
17518 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
17519 | { int flgs = ((int16_t)(src)) < 0; | |
17520 | int flgo = ((int16_t)(dst)) < 0; | |
17521 | int flgn = ((int16_t)(newv)) < 0; | |
17522 | SET_ZFLG (((int16_t)(newv)) == 0); | |
17523 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
17524 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
17525 | COPY_CARRY; | |
17526 | SET_NFLG (flgn != 0); | |
17527 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
17528 | }}}}}}m68k_incpc(4); | |
17529 | return 8; | |
17530 | } | |
17531 | unsigned long CPUFUNC(op_9080_4)(uint32_t opcode) /* SUB */ | |
17532 | { | |
17533 | uint32_t srcreg = (opcode & 7); | |
17534 | uint32_t dstreg = (opcode >> 9) & 7; | |
17535 | OpcodeFamily = 7; CurrentInstrCycles = 8; | |
17536 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
17537 | { int32_t dst = m68k_dreg(regs, dstreg); | |
17538 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
17539 | { int flgs = ((int32_t)(src)) < 0; | |
17540 | int flgo = ((int32_t)(dst)) < 0; | |
17541 | int flgn = ((int32_t)(newv)) < 0; | |
17542 | SET_ZFLG (((int32_t)(newv)) == 0); | |
17543 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
17544 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
17545 | COPY_CARRY; | |
17546 | SET_NFLG (flgn != 0); | |
17547 | m68k_dreg(regs, dstreg) = (newv); | |
17548 | }}}}}}m68k_incpc(2); | |
17549 | return 8; | |
17550 | } | |
17551 | unsigned long CPUFUNC(op_9088_4)(uint32_t opcode) /* SUB */ | |
17552 | { | |
17553 | uint32_t srcreg = (opcode & 7); | |
17554 | uint32_t dstreg = (opcode >> 9) & 7; | |
17555 | OpcodeFamily = 7; CurrentInstrCycles = 8; | |
17556 | {{ int32_t src = m68k_areg(regs, srcreg); | |
17557 | { int32_t dst = m68k_dreg(regs, dstreg); | |
17558 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
17559 | { int flgs = ((int32_t)(src)) < 0; | |
17560 | int flgo = ((int32_t)(dst)) < 0; | |
17561 | int flgn = ((int32_t)(newv)) < 0; | |
17562 | SET_ZFLG (((int32_t)(newv)) == 0); | |
17563 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
17564 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
17565 | COPY_CARRY; | |
17566 | SET_NFLG (flgn != 0); | |
17567 | m68k_dreg(regs, dstreg) = (newv); | |
17568 | }}}}}}m68k_incpc(2); | |
17569 | return 8; | |
17570 | } | |
17571 | unsigned long CPUFUNC(op_9090_4)(uint32_t opcode) /* SUB */ | |
17572 | { | |
17573 | uint32_t srcreg = (opcode & 7); | |
17574 | uint32_t dstreg = (opcode >> 9) & 7; | |
17575 | OpcodeFamily = 7; CurrentInstrCycles = 14; | |
17576 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
17577 | { int32_t src = m68k_read_memory_32(srca); | |
17578 | { int32_t dst = m68k_dreg(regs, dstreg); | |
17579 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
17580 | { int flgs = ((int32_t)(src)) < 0; | |
17581 | int flgo = ((int32_t)(dst)) < 0; | |
17582 | int flgn = ((int32_t)(newv)) < 0; | |
17583 | SET_ZFLG (((int32_t)(newv)) == 0); | |
17584 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
17585 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
17586 | COPY_CARRY; | |
17587 | SET_NFLG (flgn != 0); | |
17588 | m68k_dreg(regs, dstreg) = (newv); | |
17589 | }}}}}}}m68k_incpc(2); | |
17590 | return 14; | |
17591 | } | |
17592 | unsigned long CPUFUNC(op_9098_4)(uint32_t opcode) /* SUB */ | |
17593 | { | |
17594 | uint32_t srcreg = (opcode & 7); | |
17595 | uint32_t dstreg = (opcode >> 9) & 7; | |
17596 | OpcodeFamily = 7; CurrentInstrCycles = 14; | |
17597 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
17598 | { int32_t src = m68k_read_memory_32(srca); | |
17599 | m68k_areg(regs, srcreg) += 4; | |
17600 | { int32_t dst = m68k_dreg(regs, dstreg); | |
17601 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
17602 | { int flgs = ((int32_t)(src)) < 0; | |
17603 | int flgo = ((int32_t)(dst)) < 0; | |
17604 | int flgn = ((int32_t)(newv)) < 0; | |
17605 | SET_ZFLG (((int32_t)(newv)) == 0); | |
17606 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
17607 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
17608 | COPY_CARRY; | |
17609 | SET_NFLG (flgn != 0); | |
17610 | m68k_dreg(regs, dstreg) = (newv); | |
17611 | }}}}}}}m68k_incpc(2); | |
17612 | return 14; | |
17613 | } | |
17614 | unsigned long CPUFUNC(op_90a0_4)(uint32_t opcode) /* SUB */ | |
17615 | { | |
17616 | uint32_t srcreg = (opcode & 7); | |
17617 | uint32_t dstreg = (opcode >> 9) & 7; | |
17618 | OpcodeFamily = 7; CurrentInstrCycles = 16; | |
17619 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 4; | |
17620 | { int32_t src = m68k_read_memory_32(srca); | |
17621 | m68k_areg (regs, srcreg) = srca; | |
17622 | { int32_t dst = m68k_dreg(regs, dstreg); | |
17623 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
17624 | { int flgs = ((int32_t)(src)) < 0; | |
17625 | int flgo = ((int32_t)(dst)) < 0; | |
17626 | int flgn = ((int32_t)(newv)) < 0; | |
17627 | SET_ZFLG (((int32_t)(newv)) == 0); | |
17628 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
17629 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
17630 | COPY_CARRY; | |
17631 | SET_NFLG (flgn != 0); | |
17632 | m68k_dreg(regs, dstreg) = (newv); | |
17633 | }}}}}}}m68k_incpc(2); | |
17634 | return 16; | |
17635 | } | |
17636 | unsigned long CPUFUNC(op_90a8_4)(uint32_t opcode) /* SUB */ | |
17637 | { | |
17638 | uint32_t srcreg = (opcode & 7); | |
17639 | uint32_t dstreg = (opcode >> 9) & 7; | |
17640 | OpcodeFamily = 7; CurrentInstrCycles = 18; | |
17641 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
17642 | { int32_t src = m68k_read_memory_32(srca); | |
17643 | { int32_t dst = m68k_dreg(regs, dstreg); | |
17644 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
17645 | { int flgs = ((int32_t)(src)) < 0; | |
17646 | int flgo = ((int32_t)(dst)) < 0; | |
17647 | int flgn = ((int32_t)(newv)) < 0; | |
17648 | SET_ZFLG (((int32_t)(newv)) == 0); | |
17649 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
17650 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
17651 | COPY_CARRY; | |
17652 | SET_NFLG (flgn != 0); | |
17653 | m68k_dreg(regs, dstreg) = (newv); | |
17654 | }}}}}}}m68k_incpc(4); | |
17655 | return 18; | |
17656 | } | |
17657 | unsigned long CPUFUNC(op_90b0_4)(uint32_t opcode) /* SUB */ | |
17658 | { | |
17659 | uint32_t srcreg = (opcode & 7); | |
17660 | uint32_t dstreg = (opcode >> 9) & 7; | |
17661 | OpcodeFamily = 7; CurrentInstrCycles = 20; | |
17662 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
17663 | BusCyclePenalty += 2; | |
17664 | { int32_t src = m68k_read_memory_32(srca); | |
17665 | { int32_t dst = m68k_dreg(regs, dstreg); | |
17666 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
17667 | { int flgs = ((int32_t)(src)) < 0; | |
17668 | int flgo = ((int32_t)(dst)) < 0; | |
17669 | int flgn = ((int32_t)(newv)) < 0; | |
17670 | SET_ZFLG (((int32_t)(newv)) == 0); | |
17671 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
17672 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
17673 | COPY_CARRY; | |
17674 | SET_NFLG (flgn != 0); | |
17675 | m68k_dreg(regs, dstreg) = (newv); | |
17676 | }}}}}}}m68k_incpc(4); | |
17677 | return 20; | |
17678 | } | |
17679 | unsigned long CPUFUNC(op_90b8_4)(uint32_t opcode) /* SUB */ | |
17680 | { | |
17681 | uint32_t dstreg = (opcode >> 9) & 7; | |
17682 | OpcodeFamily = 7; CurrentInstrCycles = 18; | |
17683 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
17684 | { int32_t src = m68k_read_memory_32(srca); | |
17685 | { int32_t dst = m68k_dreg(regs, dstreg); | |
17686 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
17687 | { int flgs = ((int32_t)(src)) < 0; | |
17688 | int flgo = ((int32_t)(dst)) < 0; | |
17689 | int flgn = ((int32_t)(newv)) < 0; | |
17690 | SET_ZFLG (((int32_t)(newv)) == 0); | |
17691 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
17692 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
17693 | COPY_CARRY; | |
17694 | SET_NFLG (flgn != 0); | |
17695 | m68k_dreg(regs, dstreg) = (newv); | |
17696 | }}}}}}}m68k_incpc(4); | |
17697 | return 18; | |
17698 | } | |
17699 | unsigned long CPUFUNC(op_90b9_4)(uint32_t opcode) /* SUB */ | |
17700 | { | |
17701 | uint32_t dstreg = (opcode >> 9) & 7; | |
17702 | OpcodeFamily = 7; CurrentInstrCycles = 22; | |
17703 | {{ uint32_t srca = get_ilong(2); | |
17704 | { int32_t src = m68k_read_memory_32(srca); | |
17705 | { int32_t dst = m68k_dreg(regs, dstreg); | |
17706 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
17707 | { int flgs = ((int32_t)(src)) < 0; | |
17708 | int flgo = ((int32_t)(dst)) < 0; | |
17709 | int flgn = ((int32_t)(newv)) < 0; | |
17710 | SET_ZFLG (((int32_t)(newv)) == 0); | |
17711 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
17712 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
17713 | COPY_CARRY; | |
17714 | SET_NFLG (flgn != 0); | |
17715 | m68k_dreg(regs, dstreg) = (newv); | |
17716 | }}}}}}}m68k_incpc(6); | |
17717 | return 22; | |
17718 | } | |
17719 | unsigned long CPUFUNC(op_90ba_4)(uint32_t opcode) /* SUB */ | |
17720 | { | |
17721 | uint32_t dstreg = (opcode >> 9) & 7; | |
17722 | OpcodeFamily = 7; CurrentInstrCycles = 18; | |
17723 | {{ uint32_t srca = m68k_getpc () + 2; | |
17724 | srca += (int32_t)(int16_t)get_iword(2); | |
17725 | { int32_t src = m68k_read_memory_32(srca); | |
17726 | { int32_t dst = m68k_dreg(regs, dstreg); | |
17727 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
17728 | { int flgs = ((int32_t)(src)) < 0; | |
17729 | int flgo = ((int32_t)(dst)) < 0; | |
17730 | int flgn = ((int32_t)(newv)) < 0; | |
17731 | SET_ZFLG (((int32_t)(newv)) == 0); | |
17732 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
17733 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
17734 | COPY_CARRY; | |
17735 | SET_NFLG (flgn != 0); | |
17736 | m68k_dreg(regs, dstreg) = (newv); | |
17737 | }}}}}}}m68k_incpc(4); | |
17738 | return 18; | |
17739 | } | |
17740 | unsigned long CPUFUNC(op_90bb_4)(uint32_t opcode) /* SUB */ | |
17741 | { | |
17742 | uint32_t dstreg = (opcode >> 9) & 7; | |
17743 | OpcodeFamily = 7; CurrentInstrCycles = 20; | |
17744 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
17745 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
17746 | BusCyclePenalty += 2; | |
17747 | { int32_t src = m68k_read_memory_32(srca); | |
17748 | { int32_t dst = m68k_dreg(regs, dstreg); | |
17749 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
17750 | { int flgs = ((int32_t)(src)) < 0; | |
17751 | int flgo = ((int32_t)(dst)) < 0; | |
17752 | int flgn = ((int32_t)(newv)) < 0; | |
17753 | SET_ZFLG (((int32_t)(newv)) == 0); | |
17754 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
17755 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
17756 | COPY_CARRY; | |
17757 | SET_NFLG (flgn != 0); | |
17758 | m68k_dreg(regs, dstreg) = (newv); | |
17759 | }}}}}}}m68k_incpc(4); | |
17760 | return 20; | |
17761 | } | |
17762 | unsigned long CPUFUNC(op_90bc_4)(uint32_t opcode) /* SUB */ | |
17763 | { | |
17764 | uint32_t dstreg = (opcode >> 9) & 7; | |
17765 | OpcodeFamily = 7; CurrentInstrCycles = 16; | |
17766 | {{ int32_t src = get_ilong(2); | |
17767 | { int32_t dst = m68k_dreg(regs, dstreg); | |
17768 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
17769 | { int flgs = ((int32_t)(src)) < 0; | |
17770 | int flgo = ((int32_t)(dst)) < 0; | |
17771 | int flgn = ((int32_t)(newv)) < 0; | |
17772 | SET_ZFLG (((int32_t)(newv)) == 0); | |
17773 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
17774 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
17775 | COPY_CARRY; | |
17776 | SET_NFLG (flgn != 0); | |
17777 | m68k_dreg(regs, dstreg) = (newv); | |
17778 | }}}}}}m68k_incpc(6); | |
17779 | return 16; | |
17780 | } | |
17781 | unsigned long CPUFUNC(op_90c0_4)(uint32_t opcode) /* SUBA */ | |
17782 | { | |
17783 | uint32_t srcreg = (opcode & 7); | |
17784 | uint32_t dstreg = (opcode >> 9) & 7; | |
17785 | OpcodeFamily = 8; CurrentInstrCycles = 8; | |
17786 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
17787 | { int32_t dst = m68k_areg(regs, dstreg); | |
17788 | { uint32_t newv = dst - src; | |
17789 | m68k_areg(regs, dstreg) = (newv); | |
17790 | }}}}m68k_incpc(2); | |
17791 | return 8; | |
17792 | } | |
17793 | unsigned long CPUFUNC(op_90c8_4)(uint32_t opcode) /* SUBA */ | |
17794 | { | |
17795 | uint32_t srcreg = (opcode & 7); | |
17796 | uint32_t dstreg = (opcode >> 9) & 7; | |
17797 | OpcodeFamily = 8; CurrentInstrCycles = 8; | |
17798 | {{ int16_t src = m68k_areg(regs, srcreg); | |
17799 | { int32_t dst = m68k_areg(regs, dstreg); | |
17800 | { uint32_t newv = dst - src; | |
17801 | m68k_areg(regs, dstreg) = (newv); | |
17802 | }}}}m68k_incpc(2); | |
17803 | return 8; | |
17804 | } | |
17805 | unsigned long CPUFUNC(op_90d0_4)(uint32_t opcode) /* SUBA */ | |
17806 | { | |
17807 | uint32_t srcreg = (opcode & 7); | |
17808 | uint32_t dstreg = (opcode >> 9) & 7; | |
17809 | OpcodeFamily = 8; CurrentInstrCycles = 12; | |
17810 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
17811 | { int16_t src = m68k_read_memory_16(srca); | |
17812 | { int32_t dst = m68k_areg(regs, dstreg); | |
17813 | { uint32_t newv = dst - src; | |
17814 | m68k_areg(regs, dstreg) = (newv); | |
17815 | }}}}}m68k_incpc(2); | |
17816 | return 12; | |
17817 | } | |
17818 | unsigned long CPUFUNC(op_90d8_4)(uint32_t opcode) /* SUBA */ | |
17819 | { | |
17820 | uint32_t srcreg = (opcode & 7); | |
17821 | uint32_t dstreg = (opcode >> 9) & 7; | |
17822 | OpcodeFamily = 8; CurrentInstrCycles = 12; | |
17823 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
17824 | { int16_t src = m68k_read_memory_16(srca); | |
17825 | m68k_areg(regs, srcreg) += 2; | |
17826 | { int32_t dst = m68k_areg(regs, dstreg); | |
17827 | { uint32_t newv = dst - src; | |
17828 | m68k_areg(regs, dstreg) = (newv); | |
17829 | }}}}}m68k_incpc(2); | |
17830 | return 12; | |
17831 | } | |
17832 | unsigned long CPUFUNC(op_90e0_4)(uint32_t opcode) /* SUBA */ | |
17833 | { | |
17834 | uint32_t srcreg = (opcode & 7); | |
17835 | uint32_t dstreg = (opcode >> 9) & 7; | |
17836 | OpcodeFamily = 8; CurrentInstrCycles = 14; | |
17837 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
17838 | { int16_t src = m68k_read_memory_16(srca); | |
17839 | m68k_areg (regs, srcreg) = srca; | |
17840 | { int32_t dst = m68k_areg(regs, dstreg); | |
17841 | { uint32_t newv = dst - src; | |
17842 | m68k_areg(regs, dstreg) = (newv); | |
17843 | }}}}}m68k_incpc(2); | |
17844 | return 14; | |
17845 | } | |
17846 | unsigned long CPUFUNC(op_90e8_4)(uint32_t opcode) /* SUBA */ | |
17847 | { | |
17848 | uint32_t srcreg = (opcode & 7); | |
17849 | uint32_t dstreg = (opcode >> 9) & 7; | |
17850 | OpcodeFamily = 8; CurrentInstrCycles = 16; | |
17851 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
17852 | { int16_t src = m68k_read_memory_16(srca); | |
17853 | { int32_t dst = m68k_areg(regs, dstreg); | |
17854 | { uint32_t newv = dst - src; | |
17855 | m68k_areg(regs, dstreg) = (newv); | |
17856 | }}}}}m68k_incpc(4); | |
17857 | return 16; | |
17858 | } | |
17859 | unsigned long CPUFUNC(op_90f0_4)(uint32_t opcode) /* SUBA */ | |
17860 | { | |
17861 | uint32_t srcreg = (opcode & 7); | |
17862 | uint32_t dstreg = (opcode >> 9) & 7; | |
17863 | OpcodeFamily = 8; CurrentInstrCycles = 18; | |
17864 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
17865 | BusCyclePenalty += 2; | |
17866 | { int16_t src = m68k_read_memory_16(srca); | |
17867 | { int32_t dst = m68k_areg(regs, dstreg); | |
17868 | { uint32_t newv = dst - src; | |
17869 | m68k_areg(regs, dstreg) = (newv); | |
17870 | }}}}}m68k_incpc(4); | |
17871 | return 18; | |
17872 | } | |
17873 | unsigned long CPUFUNC(op_90f8_4)(uint32_t opcode) /* SUBA */ | |
17874 | { | |
17875 | uint32_t dstreg = (opcode >> 9) & 7; | |
17876 | OpcodeFamily = 8; CurrentInstrCycles = 16; | |
17877 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
17878 | { int16_t src = m68k_read_memory_16(srca); | |
17879 | { int32_t dst = m68k_areg(regs, dstreg); | |
17880 | { uint32_t newv = dst - src; | |
17881 | m68k_areg(regs, dstreg) = (newv); | |
17882 | }}}}}m68k_incpc(4); | |
17883 | return 16; | |
17884 | } | |
17885 | unsigned long CPUFUNC(op_90f9_4)(uint32_t opcode) /* SUBA */ | |
17886 | { | |
17887 | uint32_t dstreg = (opcode >> 9) & 7; | |
17888 | OpcodeFamily = 8; CurrentInstrCycles = 20; | |
17889 | {{ uint32_t srca = get_ilong(2); | |
17890 | { int16_t src = m68k_read_memory_16(srca); | |
17891 | { int32_t dst = m68k_areg(regs, dstreg); | |
17892 | { uint32_t newv = dst - src; | |
17893 | m68k_areg(regs, dstreg) = (newv); | |
17894 | }}}}}m68k_incpc(6); | |
17895 | return 20; | |
17896 | } | |
17897 | unsigned long CPUFUNC(op_90fa_4)(uint32_t opcode) /* SUBA */ | |
17898 | { | |
17899 | uint32_t dstreg = (opcode >> 9) & 7; | |
17900 | OpcodeFamily = 8; CurrentInstrCycles = 16; | |
17901 | {{ uint32_t srca = m68k_getpc () + 2; | |
17902 | srca += (int32_t)(int16_t)get_iword(2); | |
17903 | { int16_t src = m68k_read_memory_16(srca); | |
17904 | { int32_t dst = m68k_areg(regs, dstreg); | |
17905 | { uint32_t newv = dst - src; | |
17906 | m68k_areg(regs, dstreg) = (newv); | |
17907 | }}}}}m68k_incpc(4); | |
17908 | return 16; | |
17909 | } | |
17910 | unsigned long CPUFUNC(op_90fb_4)(uint32_t opcode) /* SUBA */ | |
17911 | { | |
17912 | uint32_t dstreg = (opcode >> 9) & 7; | |
17913 | OpcodeFamily = 8; CurrentInstrCycles = 18; | |
17914 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
17915 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
17916 | BusCyclePenalty += 2; | |
17917 | { int16_t src = m68k_read_memory_16(srca); | |
17918 | { int32_t dst = m68k_areg(regs, dstreg); | |
17919 | { uint32_t newv = dst - src; | |
17920 | m68k_areg(regs, dstreg) = (newv); | |
17921 | }}}}}m68k_incpc(4); | |
17922 | return 18; | |
17923 | } | |
17924 | unsigned long CPUFUNC(op_90fc_4)(uint32_t opcode) /* SUBA */ | |
17925 | { | |
17926 | uint32_t dstreg = (opcode >> 9) & 7; | |
17927 | OpcodeFamily = 8; CurrentInstrCycles = 12; | |
17928 | {{ int16_t src = get_iword(2); | |
17929 | { int32_t dst = m68k_areg(regs, dstreg); | |
17930 | { uint32_t newv = dst - src; | |
17931 | m68k_areg(regs, dstreg) = (newv); | |
17932 | }}}}m68k_incpc(4); | |
17933 | return 12; | |
17934 | } | |
17935 | unsigned long CPUFUNC(op_9100_4)(uint32_t opcode) /* SUBX */ | |
17936 | { | |
17937 | uint32_t srcreg = (opcode & 7); | |
17938 | uint32_t dstreg = (opcode >> 9) & 7; | |
17939 | OpcodeFamily = 9; CurrentInstrCycles = 4; | |
17940 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
17941 | { int8_t dst = m68k_dreg(regs, dstreg); | |
17942 | { uint32_t newv = dst - src - (GET_XFLG ? 1 : 0); | |
17943 | { int flgs = ((int8_t)(src)) < 0; | |
17944 | int flgo = ((int8_t)(dst)) < 0; | |
17945 | int flgn = ((int8_t)(newv)) < 0; | |
17946 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
17947 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
17948 | COPY_CARRY; | |
17949 | SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); | |
17950 | SET_NFLG (((int8_t)(newv)) < 0); | |
17951 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
17952 | }}}}}m68k_incpc(2); | |
17953 | return 4; | |
17954 | } | |
17955 | unsigned long CPUFUNC(op_9108_4)(uint32_t opcode) /* SUBX */ | |
17956 | { | |
17957 | uint32_t srcreg = (opcode & 7); | |
17958 | uint32_t dstreg = (opcode >> 9) & 7; | |
17959 | OpcodeFamily = 9; CurrentInstrCycles = 18; | |
17960 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
17961 | { int8_t src = m68k_read_memory_8(srca); | |
17962 | m68k_areg (regs, srcreg) = srca; | |
17963 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
17964 | { int8_t dst = m68k_read_memory_8(dsta); | |
17965 | m68k_areg (regs, dstreg) = dsta; | |
17966 | { uint32_t newv = dst - src - (GET_XFLG ? 1 : 0); | |
17967 | { int flgs = ((int8_t)(src)) < 0; | |
17968 | int flgo = ((int8_t)(dst)) < 0; | |
17969 | int flgn = ((int8_t)(newv)) < 0; | |
17970 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
17971 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
17972 | COPY_CARRY; | |
17973 | SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); | |
17974 | SET_NFLG (((int8_t)(newv)) < 0); | |
17975 | m68k_write_memory_8(dsta,newv); | |
17976 | }}}}}}}m68k_incpc(2); | |
17977 | return 18; | |
17978 | } | |
17979 | unsigned long CPUFUNC(op_9110_4)(uint32_t opcode) /* SUB */ | |
17980 | { | |
17981 | uint32_t srcreg = ((opcode >> 9) & 7); | |
17982 | uint32_t dstreg = opcode & 7; | |
17983 | OpcodeFamily = 7; CurrentInstrCycles = 12; | |
17984 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
17985 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
17986 | { int8_t dst = m68k_read_memory_8(dsta); | |
17987 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
17988 | { int flgs = ((int8_t)(src)) < 0; | |
17989 | int flgo = ((int8_t)(dst)) < 0; | |
17990 | int flgn = ((int8_t)(newv)) < 0; | |
17991 | SET_ZFLG (((int8_t)(newv)) == 0); | |
17992 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
17993 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
17994 | COPY_CARRY; | |
17995 | SET_NFLG (flgn != 0); | |
17996 | m68k_write_memory_8(dsta,newv); | |
17997 | }}}}}}}m68k_incpc(2); | |
17998 | return 12; | |
17999 | } | |
18000 | unsigned long CPUFUNC(op_9118_4)(uint32_t opcode) /* SUB */ | |
18001 | { | |
18002 | uint32_t srcreg = ((opcode >> 9) & 7); | |
18003 | uint32_t dstreg = opcode & 7; | |
18004 | OpcodeFamily = 7; CurrentInstrCycles = 12; | |
18005 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
18006 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
18007 | { int8_t dst = m68k_read_memory_8(dsta); | |
18008 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
18009 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
18010 | { int flgs = ((int8_t)(src)) < 0; | |
18011 | int flgo = ((int8_t)(dst)) < 0; | |
18012 | int flgn = ((int8_t)(newv)) < 0; | |
18013 | SET_ZFLG (((int8_t)(newv)) == 0); | |
18014 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
18015 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
18016 | COPY_CARRY; | |
18017 | SET_NFLG (flgn != 0); | |
18018 | m68k_write_memory_8(dsta,newv); | |
18019 | }}}}}}}m68k_incpc(2); | |
18020 | return 12; | |
18021 | } | |
18022 | unsigned long CPUFUNC(op_9120_4)(uint32_t opcode) /* SUB */ | |
18023 | { | |
18024 | uint32_t srcreg = ((opcode >> 9) & 7); | |
18025 | uint32_t dstreg = opcode & 7; | |
18026 | OpcodeFamily = 7; CurrentInstrCycles = 14; | |
18027 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
18028 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
18029 | { int8_t dst = m68k_read_memory_8(dsta); | |
18030 | m68k_areg (regs, dstreg) = dsta; | |
18031 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
18032 | { int flgs = ((int8_t)(src)) < 0; | |
18033 | int flgo = ((int8_t)(dst)) < 0; | |
18034 | int flgn = ((int8_t)(newv)) < 0; | |
18035 | SET_ZFLG (((int8_t)(newv)) == 0); | |
18036 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
18037 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
18038 | COPY_CARRY; | |
18039 | SET_NFLG (flgn != 0); | |
18040 | m68k_write_memory_8(dsta,newv); | |
18041 | }}}}}}}m68k_incpc(2); | |
18042 | return 14; | |
18043 | } | |
18044 | unsigned long CPUFUNC(op_9128_4)(uint32_t opcode) /* SUB */ | |
18045 | { | |
18046 | uint32_t srcreg = ((opcode >> 9) & 7); | |
18047 | uint32_t dstreg = opcode & 7; | |
18048 | OpcodeFamily = 7; CurrentInstrCycles = 16; | |
18049 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
18050 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); | |
18051 | { int8_t dst = m68k_read_memory_8(dsta); | |
18052 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
18053 | { int flgs = ((int8_t)(src)) < 0; | |
18054 | int flgo = ((int8_t)(dst)) < 0; | |
18055 | int flgn = ((int8_t)(newv)) < 0; | |
18056 | SET_ZFLG (((int8_t)(newv)) == 0); | |
18057 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
18058 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
18059 | COPY_CARRY; | |
18060 | SET_NFLG (flgn != 0); | |
18061 | m68k_write_memory_8(dsta,newv); | |
18062 | }}}}}}}m68k_incpc(4); | |
18063 | return 16; | |
18064 | } | |
18065 | unsigned long CPUFUNC(op_9130_4)(uint32_t opcode) /* SUB */ | |
18066 | { | |
18067 | uint32_t srcreg = ((opcode >> 9) & 7); | |
18068 | uint32_t dstreg = opcode & 7; | |
18069 | OpcodeFamily = 7; CurrentInstrCycles = 18; | |
18070 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
18071 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); | |
18072 | BusCyclePenalty += 2; | |
18073 | { int8_t dst = m68k_read_memory_8(dsta); | |
18074 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
18075 | { int flgs = ((int8_t)(src)) < 0; | |
18076 | int flgo = ((int8_t)(dst)) < 0; | |
18077 | int flgn = ((int8_t)(newv)) < 0; | |
18078 | SET_ZFLG (((int8_t)(newv)) == 0); | |
18079 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
18080 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
18081 | COPY_CARRY; | |
18082 | SET_NFLG (flgn != 0); | |
18083 | m68k_write_memory_8(dsta,newv); | |
18084 | }}}}}}}m68k_incpc(4); | |
18085 | return 18; | |
18086 | } | |
18087 | unsigned long CPUFUNC(op_9138_4)(uint32_t opcode) /* SUB */ | |
18088 | { | |
18089 | uint32_t srcreg = ((opcode >> 9) & 7); | |
18090 | OpcodeFamily = 7; CurrentInstrCycles = 16; | |
18091 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
18092 | { uint32_t dsta = (int32_t)(int16_t)get_iword(2); | |
18093 | { int8_t dst = m68k_read_memory_8(dsta); | |
18094 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
18095 | { int flgs = ((int8_t)(src)) < 0; | |
18096 | int flgo = ((int8_t)(dst)) < 0; | |
18097 | int flgn = ((int8_t)(newv)) < 0; | |
18098 | SET_ZFLG (((int8_t)(newv)) == 0); | |
18099 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
18100 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
18101 | COPY_CARRY; | |
18102 | SET_NFLG (flgn != 0); | |
18103 | m68k_write_memory_8(dsta,newv); | |
18104 | }}}}}}}m68k_incpc(4); | |
18105 | return 16; | |
18106 | } | |
18107 | unsigned long CPUFUNC(op_9139_4)(uint32_t opcode) /* SUB */ | |
18108 | { | |
18109 | uint32_t srcreg = ((opcode >> 9) & 7); | |
18110 | OpcodeFamily = 7; CurrentInstrCycles = 20; | |
18111 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
18112 | { uint32_t dsta = get_ilong(2); | |
18113 | { int8_t dst = m68k_read_memory_8(dsta); | |
18114 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
18115 | { int flgs = ((int8_t)(src)) < 0; | |
18116 | int flgo = ((int8_t)(dst)) < 0; | |
18117 | int flgn = ((int8_t)(newv)) < 0; | |
18118 | SET_ZFLG (((int8_t)(newv)) == 0); | |
18119 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
18120 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
18121 | COPY_CARRY; | |
18122 | SET_NFLG (flgn != 0); | |
18123 | m68k_write_memory_8(dsta,newv); | |
18124 | }}}}}}}m68k_incpc(6); | |
18125 | return 20; | |
18126 | } | |
18127 | unsigned long CPUFUNC(op_9140_4)(uint32_t opcode) /* SUBX */ | |
18128 | { | |
18129 | uint32_t srcreg = (opcode & 7); | |
18130 | uint32_t dstreg = (opcode >> 9) & 7; | |
18131 | OpcodeFamily = 9; CurrentInstrCycles = 4; | |
18132 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
18133 | { int16_t dst = m68k_dreg(regs, dstreg); | |
18134 | { uint32_t newv = dst - src - (GET_XFLG ? 1 : 0); | |
18135 | { int flgs = ((int16_t)(src)) < 0; | |
18136 | int flgo = ((int16_t)(dst)) < 0; | |
18137 | int flgn = ((int16_t)(newv)) < 0; | |
18138 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
18139 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
18140 | COPY_CARRY; | |
18141 | SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0)); | |
18142 | SET_NFLG (((int16_t)(newv)) < 0); | |
18143 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
18144 | }}}}}m68k_incpc(2); | |
18145 | return 4; | |
18146 | } | |
18147 | unsigned long CPUFUNC(op_9148_4)(uint32_t opcode) /* SUBX */ | |
18148 | { | |
18149 | uint32_t srcreg = (opcode & 7); | |
18150 | uint32_t dstreg = (opcode >> 9) & 7; | |
18151 | OpcodeFamily = 9; CurrentInstrCycles = 18; | |
18152 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
18153 | { int16_t src = m68k_read_memory_16(srca); | |
18154 | m68k_areg (regs, srcreg) = srca; | |
18155 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
18156 | { int16_t dst = m68k_read_memory_16(dsta); | |
18157 | m68k_areg (regs, dstreg) = dsta; | |
18158 | { uint32_t newv = dst - src - (GET_XFLG ? 1 : 0); | |
18159 | { int flgs = ((int16_t)(src)) < 0; | |
18160 | int flgo = ((int16_t)(dst)) < 0; | |
18161 | int flgn = ((int16_t)(newv)) < 0; | |
18162 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
18163 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
18164 | COPY_CARRY; | |
18165 | SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0)); | |
18166 | SET_NFLG (((int16_t)(newv)) < 0); | |
18167 | m68k_write_memory_16(dsta,newv); | |
18168 | }}}}}}}m68k_incpc(2); | |
18169 | return 18; | |
18170 | } | |
18171 | unsigned long CPUFUNC(op_9150_4)(uint32_t opcode) /* SUB */ | |
18172 | { | |
18173 | uint32_t srcreg = ((opcode >> 9) & 7); | |
18174 | uint32_t dstreg = opcode & 7; | |
18175 | OpcodeFamily = 7; CurrentInstrCycles = 12; | |
18176 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
18177 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
18178 | { int16_t dst = m68k_read_memory_16(dsta); | |
18179 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
18180 | { int flgs = ((int16_t)(src)) < 0; | |
18181 | int flgo = ((int16_t)(dst)) < 0; | |
18182 | int flgn = ((int16_t)(newv)) < 0; | |
18183 | SET_ZFLG (((int16_t)(newv)) == 0); | |
18184 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
18185 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
18186 | COPY_CARRY; | |
18187 | SET_NFLG (flgn != 0); | |
18188 | m68k_write_memory_16(dsta,newv); | |
18189 | }}}}}}}m68k_incpc(2); | |
18190 | return 12; | |
18191 | } | |
18192 | unsigned long CPUFUNC(op_9158_4)(uint32_t opcode) /* SUB */ | |
18193 | { | |
18194 | uint32_t srcreg = ((opcode >> 9) & 7); | |
18195 | uint32_t dstreg = opcode & 7; | |
18196 | OpcodeFamily = 7; CurrentInstrCycles = 12; | |
18197 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
18198 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
18199 | { int16_t dst = m68k_read_memory_16(dsta); | |
18200 | m68k_areg(regs, dstreg) += 2; | |
18201 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
18202 | { int flgs = ((int16_t)(src)) < 0; | |
18203 | int flgo = ((int16_t)(dst)) < 0; | |
18204 | int flgn = ((int16_t)(newv)) < 0; | |
18205 | SET_ZFLG (((int16_t)(newv)) == 0); | |
18206 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
18207 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
18208 | COPY_CARRY; | |
18209 | SET_NFLG (flgn != 0); | |
18210 | m68k_write_memory_16(dsta,newv); | |
18211 | }}}}}}}m68k_incpc(2); | |
18212 | return 12; | |
18213 | } | |
18214 | unsigned long CPUFUNC(op_9160_4)(uint32_t opcode) /* SUB */ | |
18215 | { | |
18216 | uint32_t srcreg = ((opcode >> 9) & 7); | |
18217 | uint32_t dstreg = opcode & 7; | |
18218 | OpcodeFamily = 7; CurrentInstrCycles = 14; | |
18219 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
18220 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
18221 | { int16_t dst = m68k_read_memory_16(dsta); | |
18222 | m68k_areg (regs, dstreg) = dsta; | |
18223 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
18224 | { int flgs = ((int16_t)(src)) < 0; | |
18225 | int flgo = ((int16_t)(dst)) < 0; | |
18226 | int flgn = ((int16_t)(newv)) < 0; | |
18227 | SET_ZFLG (((int16_t)(newv)) == 0); | |
18228 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
18229 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
18230 | COPY_CARRY; | |
18231 | SET_NFLG (flgn != 0); | |
18232 | m68k_write_memory_16(dsta,newv); | |
18233 | }}}}}}}m68k_incpc(2); | |
18234 | return 14; | |
18235 | } | |
18236 | unsigned long CPUFUNC(op_9168_4)(uint32_t opcode) /* SUB */ | |
18237 | { | |
18238 | uint32_t srcreg = ((opcode >> 9) & 7); | |
18239 | uint32_t dstreg = opcode & 7; | |
18240 | OpcodeFamily = 7; CurrentInstrCycles = 16; | |
18241 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
18242 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); | |
18243 | { int16_t dst = m68k_read_memory_16(dsta); | |
18244 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
18245 | { int flgs = ((int16_t)(src)) < 0; | |
18246 | int flgo = ((int16_t)(dst)) < 0; | |
18247 | int flgn = ((int16_t)(newv)) < 0; | |
18248 | SET_ZFLG (((int16_t)(newv)) == 0); | |
18249 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
18250 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
18251 | COPY_CARRY; | |
18252 | SET_NFLG (flgn != 0); | |
18253 | m68k_write_memory_16(dsta,newv); | |
18254 | }}}}}}}m68k_incpc(4); | |
18255 | return 16; | |
18256 | } | |
18257 | unsigned long CPUFUNC(op_9170_4)(uint32_t opcode) /* SUB */ | |
18258 | { | |
18259 | uint32_t srcreg = ((opcode >> 9) & 7); | |
18260 | uint32_t dstreg = opcode & 7; | |
18261 | OpcodeFamily = 7; CurrentInstrCycles = 18; | |
18262 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
18263 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); | |
18264 | BusCyclePenalty += 2; | |
18265 | { int16_t dst = m68k_read_memory_16(dsta); | |
18266 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
18267 | { int flgs = ((int16_t)(src)) < 0; | |
18268 | int flgo = ((int16_t)(dst)) < 0; | |
18269 | int flgn = ((int16_t)(newv)) < 0; | |
18270 | SET_ZFLG (((int16_t)(newv)) == 0); | |
18271 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
18272 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
18273 | COPY_CARRY; | |
18274 | SET_NFLG (flgn != 0); | |
18275 | m68k_write_memory_16(dsta,newv); | |
18276 | }}}}}}}m68k_incpc(4); | |
18277 | return 18; | |
18278 | } | |
18279 | unsigned long CPUFUNC(op_9178_4)(uint32_t opcode) /* SUB */ | |
18280 | { | |
18281 | uint32_t srcreg = ((opcode >> 9) & 7); | |
18282 | OpcodeFamily = 7; CurrentInstrCycles = 16; | |
18283 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
18284 | { uint32_t dsta = (int32_t)(int16_t)get_iword(2); | |
18285 | { int16_t dst = m68k_read_memory_16(dsta); | |
18286 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
18287 | { int flgs = ((int16_t)(src)) < 0; | |
18288 | int flgo = ((int16_t)(dst)) < 0; | |
18289 | int flgn = ((int16_t)(newv)) < 0; | |
18290 | SET_ZFLG (((int16_t)(newv)) == 0); | |
18291 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
18292 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
18293 | COPY_CARRY; | |
18294 | SET_NFLG (flgn != 0); | |
18295 | m68k_write_memory_16(dsta,newv); | |
18296 | }}}}}}}m68k_incpc(4); | |
18297 | return 16; | |
18298 | } | |
18299 | unsigned long CPUFUNC(op_9179_4)(uint32_t opcode) /* SUB */ | |
18300 | { | |
18301 | uint32_t srcreg = ((opcode >> 9) & 7); | |
18302 | OpcodeFamily = 7; CurrentInstrCycles = 20; | |
18303 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
18304 | { uint32_t dsta = get_ilong(2); | |
18305 | { int16_t dst = m68k_read_memory_16(dsta); | |
18306 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
18307 | { int flgs = ((int16_t)(src)) < 0; | |
18308 | int flgo = ((int16_t)(dst)) < 0; | |
18309 | int flgn = ((int16_t)(newv)) < 0; | |
18310 | SET_ZFLG (((int16_t)(newv)) == 0); | |
18311 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
18312 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
18313 | COPY_CARRY; | |
18314 | SET_NFLG (flgn != 0); | |
18315 | m68k_write_memory_16(dsta,newv); | |
18316 | }}}}}}}m68k_incpc(6); | |
18317 | return 20; | |
18318 | } | |
18319 | unsigned long CPUFUNC(op_9180_4)(uint32_t opcode) /* SUBX */ | |
18320 | { | |
18321 | uint32_t srcreg = (opcode & 7); | |
18322 | uint32_t dstreg = (opcode >> 9) & 7; | |
18323 | OpcodeFamily = 9; CurrentInstrCycles = 8; | |
18324 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
18325 | { int32_t dst = m68k_dreg(regs, dstreg); | |
18326 | { uint32_t newv = dst - src - (GET_XFLG ? 1 : 0); | |
18327 | { int flgs = ((int32_t)(src)) < 0; | |
18328 | int flgo = ((int32_t)(dst)) < 0; | |
18329 | int flgn = ((int32_t)(newv)) < 0; | |
18330 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
18331 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
18332 | COPY_CARRY; | |
18333 | SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0)); | |
18334 | SET_NFLG (((int32_t)(newv)) < 0); | |
18335 | m68k_dreg(regs, dstreg) = (newv); | |
18336 | }}}}}m68k_incpc(2); | |
18337 | return 8; | |
18338 | } | |
18339 | unsigned long CPUFUNC(op_9188_4)(uint32_t opcode) /* SUBX */ | |
18340 | { | |
18341 | uint32_t srcreg = (opcode & 7); | |
18342 | uint32_t dstreg = (opcode >> 9) & 7; | |
18343 | OpcodeFamily = 9; CurrentInstrCycles = 30; | |
18344 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 4; | |
18345 | { int32_t src = m68k_read_memory_32(srca); | |
18346 | m68k_areg (regs, srcreg) = srca; | |
18347 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
18348 | { int32_t dst = m68k_read_memory_32(dsta); | |
18349 | m68k_areg (regs, dstreg) = dsta; | |
18350 | { uint32_t newv = dst - src - (GET_XFLG ? 1 : 0); | |
18351 | { int flgs = ((int32_t)(src)) < 0; | |
18352 | int flgo = ((int32_t)(dst)) < 0; | |
18353 | int flgn = ((int32_t)(newv)) < 0; | |
18354 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
18355 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
18356 | COPY_CARRY; | |
18357 | SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0)); | |
18358 | SET_NFLG (((int32_t)(newv)) < 0); | |
18359 | m68k_write_memory_32(dsta,newv); | |
18360 | }}}}}}}m68k_incpc(2); | |
18361 | return 30; | |
18362 | } | |
18363 | unsigned long CPUFUNC(op_9190_4)(uint32_t opcode) /* SUB */ | |
18364 | { | |
18365 | uint32_t srcreg = ((opcode >> 9) & 7); | |
18366 | uint32_t dstreg = opcode & 7; | |
18367 | OpcodeFamily = 7; CurrentInstrCycles = 20; | |
18368 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
18369 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
18370 | { int32_t dst = m68k_read_memory_32(dsta); | |
18371 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
18372 | { int flgs = ((int32_t)(src)) < 0; | |
18373 | int flgo = ((int32_t)(dst)) < 0; | |
18374 | int flgn = ((int32_t)(newv)) < 0; | |
18375 | SET_ZFLG (((int32_t)(newv)) == 0); | |
18376 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
18377 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
18378 | COPY_CARRY; | |
18379 | SET_NFLG (flgn != 0); | |
18380 | m68k_write_memory_32(dsta,newv); | |
18381 | }}}}}}}m68k_incpc(2); | |
18382 | return 20; | |
18383 | } | |
18384 | unsigned long CPUFUNC(op_9198_4)(uint32_t opcode) /* SUB */ | |
18385 | { | |
18386 | uint32_t srcreg = ((opcode >> 9) & 7); | |
18387 | uint32_t dstreg = opcode & 7; | |
18388 | OpcodeFamily = 7; CurrentInstrCycles = 20; | |
18389 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
18390 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
18391 | { int32_t dst = m68k_read_memory_32(dsta); | |
18392 | m68k_areg(regs, dstreg) += 4; | |
18393 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
18394 | { int flgs = ((int32_t)(src)) < 0; | |
18395 | int flgo = ((int32_t)(dst)) < 0; | |
18396 | int flgn = ((int32_t)(newv)) < 0; | |
18397 | SET_ZFLG (((int32_t)(newv)) == 0); | |
18398 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
18399 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
18400 | COPY_CARRY; | |
18401 | SET_NFLG (flgn != 0); | |
18402 | m68k_write_memory_32(dsta,newv); | |
18403 | }}}}}}}m68k_incpc(2); | |
18404 | return 20; | |
18405 | } | |
18406 | unsigned long CPUFUNC(op_91a0_4)(uint32_t opcode) /* SUB */ | |
18407 | { | |
18408 | uint32_t srcreg = ((opcode >> 9) & 7); | |
18409 | uint32_t dstreg = opcode & 7; | |
18410 | OpcodeFamily = 7; CurrentInstrCycles = 22; | |
18411 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
18412 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
18413 | { int32_t dst = m68k_read_memory_32(dsta); | |
18414 | m68k_areg (regs, dstreg) = dsta; | |
18415 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
18416 | { int flgs = ((int32_t)(src)) < 0; | |
18417 | int flgo = ((int32_t)(dst)) < 0; | |
18418 | int flgn = ((int32_t)(newv)) < 0; | |
18419 | SET_ZFLG (((int32_t)(newv)) == 0); | |
18420 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
18421 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
18422 | COPY_CARRY; | |
18423 | SET_NFLG (flgn != 0); | |
18424 | m68k_write_memory_32(dsta,newv); | |
18425 | }}}}}}}m68k_incpc(2); | |
18426 | return 22; | |
18427 | } | |
18428 | unsigned long CPUFUNC(op_91a8_4)(uint32_t opcode) /* SUB */ | |
18429 | { | |
18430 | uint32_t srcreg = ((opcode >> 9) & 7); | |
18431 | uint32_t dstreg = opcode & 7; | |
18432 | OpcodeFamily = 7; CurrentInstrCycles = 24; | |
18433 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
18434 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); | |
18435 | { int32_t dst = m68k_read_memory_32(dsta); | |
18436 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
18437 | { int flgs = ((int32_t)(src)) < 0; | |
18438 | int flgo = ((int32_t)(dst)) < 0; | |
18439 | int flgn = ((int32_t)(newv)) < 0; | |
18440 | SET_ZFLG (((int32_t)(newv)) == 0); | |
18441 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
18442 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
18443 | COPY_CARRY; | |
18444 | SET_NFLG (flgn != 0); | |
18445 | m68k_write_memory_32(dsta,newv); | |
18446 | }}}}}}}m68k_incpc(4); | |
18447 | return 24; | |
18448 | } | |
18449 | unsigned long CPUFUNC(op_91b0_4)(uint32_t opcode) /* SUB */ | |
18450 | { | |
18451 | uint32_t srcreg = ((opcode >> 9) & 7); | |
18452 | uint32_t dstreg = opcode & 7; | |
18453 | OpcodeFamily = 7; CurrentInstrCycles = 26; | |
18454 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
18455 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); | |
18456 | BusCyclePenalty += 2; | |
18457 | { int32_t dst = m68k_read_memory_32(dsta); | |
18458 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
18459 | { int flgs = ((int32_t)(src)) < 0; | |
18460 | int flgo = ((int32_t)(dst)) < 0; | |
18461 | int flgn = ((int32_t)(newv)) < 0; | |
18462 | SET_ZFLG (((int32_t)(newv)) == 0); | |
18463 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
18464 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
18465 | COPY_CARRY; | |
18466 | SET_NFLG (flgn != 0); | |
18467 | m68k_write_memory_32(dsta,newv); | |
18468 | }}}}}}}m68k_incpc(4); | |
18469 | return 26; | |
18470 | } | |
18471 | unsigned long CPUFUNC(op_91b8_4)(uint32_t opcode) /* SUB */ | |
18472 | { | |
18473 | uint32_t srcreg = ((opcode >> 9) & 7); | |
18474 | OpcodeFamily = 7; CurrentInstrCycles = 24; | |
18475 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
18476 | { uint32_t dsta = (int32_t)(int16_t)get_iword(2); | |
18477 | { int32_t dst = m68k_read_memory_32(dsta); | |
18478 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
18479 | { int flgs = ((int32_t)(src)) < 0; | |
18480 | int flgo = ((int32_t)(dst)) < 0; | |
18481 | int flgn = ((int32_t)(newv)) < 0; | |
18482 | SET_ZFLG (((int32_t)(newv)) == 0); | |
18483 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
18484 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
18485 | COPY_CARRY; | |
18486 | SET_NFLG (flgn != 0); | |
18487 | m68k_write_memory_32(dsta,newv); | |
18488 | }}}}}}}m68k_incpc(4); | |
18489 | return 24; | |
18490 | } | |
18491 | unsigned long CPUFUNC(op_91b9_4)(uint32_t opcode) /* SUB */ | |
18492 | { | |
18493 | uint32_t srcreg = ((opcode >> 9) & 7); | |
18494 | OpcodeFamily = 7; CurrentInstrCycles = 28; | |
18495 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
18496 | { uint32_t dsta = get_ilong(2); | |
18497 | { int32_t dst = m68k_read_memory_32(dsta); | |
18498 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
18499 | { int flgs = ((int32_t)(src)) < 0; | |
18500 | int flgo = ((int32_t)(dst)) < 0; | |
18501 | int flgn = ((int32_t)(newv)) < 0; | |
18502 | SET_ZFLG (((int32_t)(newv)) == 0); | |
18503 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
18504 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
18505 | COPY_CARRY; | |
18506 | SET_NFLG (flgn != 0); | |
18507 | m68k_write_memory_32(dsta,newv); | |
18508 | }}}}}}}m68k_incpc(6); | |
18509 | return 28; | |
18510 | } | |
18511 | unsigned long CPUFUNC(op_91c0_4)(uint32_t opcode) /* SUBA */ | |
18512 | { | |
18513 | uint32_t srcreg = (opcode & 7); | |
18514 | uint32_t dstreg = (opcode >> 9) & 7; | |
18515 | OpcodeFamily = 8; CurrentInstrCycles = 8; | |
18516 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
18517 | { int32_t dst = m68k_areg(regs, dstreg); | |
18518 | { uint32_t newv = dst - src; | |
18519 | m68k_areg(regs, dstreg) = (newv); | |
18520 | }}}}m68k_incpc(2); | |
18521 | return 8; | |
18522 | } | |
18523 | unsigned long CPUFUNC(op_91c8_4)(uint32_t opcode) /* SUBA */ | |
18524 | { | |
18525 | uint32_t srcreg = (opcode & 7); | |
18526 | uint32_t dstreg = (opcode >> 9) & 7; | |
18527 | OpcodeFamily = 8; CurrentInstrCycles = 8; | |
18528 | {{ int32_t src = m68k_areg(regs, srcreg); | |
18529 | { int32_t dst = m68k_areg(regs, dstreg); | |
18530 | { uint32_t newv = dst - src; | |
18531 | m68k_areg(regs, dstreg) = (newv); | |
18532 | }}}}m68k_incpc(2); | |
18533 | return 8; | |
18534 | } | |
18535 | unsigned long CPUFUNC(op_91d0_4)(uint32_t opcode) /* SUBA */ | |
18536 | { | |
18537 | uint32_t srcreg = (opcode & 7); | |
18538 | uint32_t dstreg = (opcode >> 9) & 7; | |
18539 | OpcodeFamily = 8; CurrentInstrCycles = 14; | |
18540 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
18541 | { int32_t src = m68k_read_memory_32(srca); | |
18542 | { int32_t dst = m68k_areg(regs, dstreg); | |
18543 | { uint32_t newv = dst - src; | |
18544 | m68k_areg(regs, dstreg) = (newv); | |
18545 | }}}}}m68k_incpc(2); | |
18546 | return 14; | |
18547 | } | |
18548 | unsigned long CPUFUNC(op_91d8_4)(uint32_t opcode) /* SUBA */ | |
18549 | { | |
18550 | uint32_t srcreg = (opcode & 7); | |
18551 | uint32_t dstreg = (opcode >> 9) & 7; | |
18552 | OpcodeFamily = 8; CurrentInstrCycles = 14; | |
18553 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
18554 | { int32_t src = m68k_read_memory_32(srca); | |
18555 | m68k_areg(regs, srcreg) += 4; | |
18556 | { int32_t dst = m68k_areg(regs, dstreg); | |
18557 | { uint32_t newv = dst - src; | |
18558 | m68k_areg(regs, dstreg) = (newv); | |
18559 | }}}}}m68k_incpc(2); | |
18560 | return 14; | |
18561 | } | |
18562 | unsigned long CPUFUNC(op_91e0_4)(uint32_t opcode) /* SUBA */ | |
18563 | { | |
18564 | uint32_t srcreg = (opcode & 7); | |
18565 | uint32_t dstreg = (opcode >> 9) & 7; | |
18566 | OpcodeFamily = 8; CurrentInstrCycles = 16; | |
18567 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 4; | |
18568 | { int32_t src = m68k_read_memory_32(srca); | |
18569 | m68k_areg (regs, srcreg) = srca; | |
18570 | { int32_t dst = m68k_areg(regs, dstreg); | |
18571 | { uint32_t newv = dst - src; | |
18572 | m68k_areg(regs, dstreg) = (newv); | |
18573 | }}}}}m68k_incpc(2); | |
18574 | return 16; | |
18575 | } | |
18576 | unsigned long CPUFUNC(op_91e8_4)(uint32_t opcode) /* SUBA */ | |
18577 | { | |
18578 | uint32_t srcreg = (opcode & 7); | |
18579 | uint32_t dstreg = (opcode >> 9) & 7; | |
18580 | OpcodeFamily = 8; CurrentInstrCycles = 18; | |
18581 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
18582 | { int32_t src = m68k_read_memory_32(srca); | |
18583 | { int32_t dst = m68k_areg(regs, dstreg); | |
18584 | { uint32_t newv = dst - src; | |
18585 | m68k_areg(regs, dstreg) = (newv); | |
18586 | }}}}}m68k_incpc(4); | |
18587 | return 18; | |
18588 | } | |
18589 | unsigned long CPUFUNC(op_91f0_4)(uint32_t opcode) /* SUBA */ | |
18590 | { | |
18591 | uint32_t srcreg = (opcode & 7); | |
18592 | uint32_t dstreg = (opcode >> 9) & 7; | |
18593 | OpcodeFamily = 8; CurrentInstrCycles = 20; | |
18594 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
18595 | BusCyclePenalty += 2; | |
18596 | { int32_t src = m68k_read_memory_32(srca); | |
18597 | { int32_t dst = m68k_areg(regs, dstreg); | |
18598 | { uint32_t newv = dst - src; | |
18599 | m68k_areg(regs, dstreg) = (newv); | |
18600 | }}}}}m68k_incpc(4); | |
18601 | return 20; | |
18602 | } | |
18603 | unsigned long CPUFUNC(op_91f8_4)(uint32_t opcode) /* SUBA */ | |
18604 | { | |
18605 | uint32_t dstreg = (opcode >> 9) & 7; | |
18606 | OpcodeFamily = 8; CurrentInstrCycles = 18; | |
18607 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
18608 | { int32_t src = m68k_read_memory_32(srca); | |
18609 | { int32_t dst = m68k_areg(regs, dstreg); | |
18610 | { uint32_t newv = dst - src; | |
18611 | m68k_areg(regs, dstreg) = (newv); | |
18612 | }}}}}m68k_incpc(4); | |
18613 | return 18; | |
18614 | } | |
18615 | unsigned long CPUFUNC(op_91f9_4)(uint32_t opcode) /* SUBA */ | |
18616 | { | |
18617 | uint32_t dstreg = (opcode >> 9) & 7; | |
18618 | OpcodeFamily = 8; CurrentInstrCycles = 22; | |
18619 | {{ uint32_t srca = get_ilong(2); | |
18620 | { int32_t src = m68k_read_memory_32(srca); | |
18621 | { int32_t dst = m68k_areg(regs, dstreg); | |
18622 | { uint32_t newv = dst - src; | |
18623 | m68k_areg(regs, dstreg) = (newv); | |
18624 | }}}}}m68k_incpc(6); | |
18625 | return 22; | |
18626 | } | |
18627 | unsigned long CPUFUNC(op_91fa_4)(uint32_t opcode) /* SUBA */ | |
18628 | { | |
18629 | uint32_t dstreg = (opcode >> 9) & 7; | |
18630 | OpcodeFamily = 8; CurrentInstrCycles = 18; | |
18631 | {{ uint32_t srca = m68k_getpc () + 2; | |
18632 | srca += (int32_t)(int16_t)get_iword(2); | |
18633 | { int32_t src = m68k_read_memory_32(srca); | |
18634 | { int32_t dst = m68k_areg(regs, dstreg); | |
18635 | { uint32_t newv = dst - src; | |
18636 | m68k_areg(regs, dstreg) = (newv); | |
18637 | }}}}}m68k_incpc(4); | |
18638 | return 18; | |
18639 | } | |
18640 | unsigned long CPUFUNC(op_91fb_4)(uint32_t opcode) /* SUBA */ | |
18641 | { | |
18642 | uint32_t dstreg = (opcode >> 9) & 7; | |
18643 | OpcodeFamily = 8; CurrentInstrCycles = 20; | |
18644 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
18645 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
18646 | BusCyclePenalty += 2; | |
18647 | { int32_t src = m68k_read_memory_32(srca); | |
18648 | { int32_t dst = m68k_areg(regs, dstreg); | |
18649 | { uint32_t newv = dst - src; | |
18650 | m68k_areg(regs, dstreg) = (newv); | |
18651 | }}}}}m68k_incpc(4); | |
18652 | return 20; | |
18653 | } | |
18654 | unsigned long CPUFUNC(op_91fc_4)(uint32_t opcode) /* SUBA */ | |
18655 | { | |
18656 | uint32_t dstreg = (opcode >> 9) & 7; | |
18657 | OpcodeFamily = 8; CurrentInstrCycles = 16; | |
18658 | {{ int32_t src = get_ilong(2); | |
18659 | { int32_t dst = m68k_areg(regs, dstreg); | |
18660 | { uint32_t newv = dst - src; | |
18661 | m68k_areg(regs, dstreg) = (newv); | |
18662 | }}}}m68k_incpc(6); | |
18663 | return 16; | |
18664 | } | |
18665 | unsigned long CPUFUNC(op_b000_4)(uint32_t opcode) /* CMP */ | |
18666 | { | |
18667 | uint32_t srcreg = (opcode & 7); | |
18668 | uint32_t dstreg = (opcode >> 9) & 7; | |
18669 | OpcodeFamily = 25; CurrentInstrCycles = 4; | |
18670 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
18671 | { int8_t dst = m68k_dreg(regs, dstreg); | |
18672 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
18673 | { int flgs = ((int8_t)(src)) < 0; | |
18674 | int flgo = ((int8_t)(dst)) < 0; | |
18675 | int flgn = ((int8_t)(newv)) < 0; | |
18676 | SET_ZFLG (((int8_t)(newv)) == 0); | |
18677 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
18678 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
18679 | SET_NFLG (flgn != 0); | |
18680 | }}}}}}m68k_incpc(2); | |
18681 | return 4; | |
18682 | } | |
18683 | unsigned long CPUFUNC(op_b010_4)(uint32_t opcode) /* CMP */ | |
18684 | { | |
18685 | uint32_t srcreg = (opcode & 7); | |
18686 | uint32_t dstreg = (opcode >> 9) & 7; | |
18687 | OpcodeFamily = 25; CurrentInstrCycles = 8; | |
18688 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
18689 | { int8_t src = m68k_read_memory_8(srca); | |
18690 | { int8_t dst = m68k_dreg(regs, dstreg); | |
18691 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
18692 | { int flgs = ((int8_t)(src)) < 0; | |
18693 | int flgo = ((int8_t)(dst)) < 0; | |
18694 | int flgn = ((int8_t)(newv)) < 0; | |
18695 | SET_ZFLG (((int8_t)(newv)) == 0); | |
18696 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
18697 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
18698 | SET_NFLG (flgn != 0); | |
18699 | }}}}}}}m68k_incpc(2); | |
18700 | return 8; | |
18701 | } | |
18702 | unsigned long CPUFUNC(op_b018_4)(uint32_t opcode) /* CMP */ | |
18703 | { | |
18704 | uint32_t srcreg = (opcode & 7); | |
18705 | uint32_t dstreg = (opcode >> 9) & 7; | |
18706 | OpcodeFamily = 25; CurrentInstrCycles = 8; | |
18707 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
18708 | { int8_t src = m68k_read_memory_8(srca); | |
18709 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
18710 | { int8_t dst = m68k_dreg(regs, dstreg); | |
18711 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
18712 | { int flgs = ((int8_t)(src)) < 0; | |
18713 | int flgo = ((int8_t)(dst)) < 0; | |
18714 | int flgn = ((int8_t)(newv)) < 0; | |
18715 | SET_ZFLG (((int8_t)(newv)) == 0); | |
18716 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
18717 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
18718 | SET_NFLG (flgn != 0); | |
18719 | }}}}}}}m68k_incpc(2); | |
18720 | return 8; | |
18721 | } | |
18722 | unsigned long CPUFUNC(op_b020_4)(uint32_t opcode) /* CMP */ | |
18723 | { | |
18724 | uint32_t srcreg = (opcode & 7); | |
18725 | uint32_t dstreg = (opcode >> 9) & 7; | |
18726 | OpcodeFamily = 25; CurrentInstrCycles = 10; | |
18727 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
18728 | { int8_t src = m68k_read_memory_8(srca); | |
18729 | m68k_areg (regs, srcreg) = srca; | |
18730 | { int8_t dst = m68k_dreg(regs, dstreg); | |
18731 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
18732 | { int flgs = ((int8_t)(src)) < 0; | |
18733 | int flgo = ((int8_t)(dst)) < 0; | |
18734 | int flgn = ((int8_t)(newv)) < 0; | |
18735 | SET_ZFLG (((int8_t)(newv)) == 0); | |
18736 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
18737 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
18738 | SET_NFLG (flgn != 0); | |
18739 | }}}}}}}m68k_incpc(2); | |
18740 | return 10; | |
18741 | } | |
18742 | unsigned long CPUFUNC(op_b028_4)(uint32_t opcode) /* CMP */ | |
18743 | { | |
18744 | uint32_t srcreg = (opcode & 7); | |
18745 | uint32_t dstreg = (opcode >> 9) & 7; | |
18746 | OpcodeFamily = 25; CurrentInstrCycles = 12; | |
18747 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
18748 | { int8_t src = m68k_read_memory_8(srca); | |
18749 | { int8_t dst = m68k_dreg(regs, dstreg); | |
18750 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
18751 | { int flgs = ((int8_t)(src)) < 0; | |
18752 | int flgo = ((int8_t)(dst)) < 0; | |
18753 | int flgn = ((int8_t)(newv)) < 0; | |
18754 | SET_ZFLG (((int8_t)(newv)) == 0); | |
18755 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
18756 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
18757 | SET_NFLG (flgn != 0); | |
18758 | }}}}}}}m68k_incpc(4); | |
18759 | return 12; | |
18760 | } | |
18761 | unsigned long CPUFUNC(op_b030_4)(uint32_t opcode) /* CMP */ | |
18762 | { | |
18763 | uint32_t srcreg = (opcode & 7); | |
18764 | uint32_t dstreg = (opcode >> 9) & 7; | |
18765 | OpcodeFamily = 25; CurrentInstrCycles = 14; | |
18766 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
18767 | BusCyclePenalty += 2; | |
18768 | { int8_t src = m68k_read_memory_8(srca); | |
18769 | { int8_t dst = m68k_dreg(regs, dstreg); | |
18770 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
18771 | { int flgs = ((int8_t)(src)) < 0; | |
18772 | int flgo = ((int8_t)(dst)) < 0; | |
18773 | int flgn = ((int8_t)(newv)) < 0; | |
18774 | SET_ZFLG (((int8_t)(newv)) == 0); | |
18775 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
18776 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
18777 | SET_NFLG (flgn != 0); | |
18778 | }}}}}}}m68k_incpc(4); | |
18779 | return 14; | |
18780 | } | |
18781 | unsigned long CPUFUNC(op_b038_4)(uint32_t opcode) /* CMP */ | |
18782 | { | |
18783 | uint32_t dstreg = (opcode >> 9) & 7; | |
18784 | OpcodeFamily = 25; CurrentInstrCycles = 12; | |
18785 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
18786 | { int8_t src = m68k_read_memory_8(srca); | |
18787 | { int8_t dst = m68k_dreg(regs, dstreg); | |
18788 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
18789 | { int flgs = ((int8_t)(src)) < 0; | |
18790 | int flgo = ((int8_t)(dst)) < 0; | |
18791 | int flgn = ((int8_t)(newv)) < 0; | |
18792 | SET_ZFLG (((int8_t)(newv)) == 0); | |
18793 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
18794 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
18795 | SET_NFLG (flgn != 0); | |
18796 | }}}}}}}m68k_incpc(4); | |
18797 | return 12; | |
18798 | } | |
18799 | unsigned long CPUFUNC(op_b039_4)(uint32_t opcode) /* CMP */ | |
18800 | { | |
18801 | uint32_t dstreg = (opcode >> 9) & 7; | |
18802 | OpcodeFamily = 25; CurrentInstrCycles = 16; | |
18803 | {{ uint32_t srca = get_ilong(2); | |
18804 | { int8_t src = m68k_read_memory_8(srca); | |
18805 | { int8_t dst = m68k_dreg(regs, dstreg); | |
18806 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
18807 | { int flgs = ((int8_t)(src)) < 0; | |
18808 | int flgo = ((int8_t)(dst)) < 0; | |
18809 | int flgn = ((int8_t)(newv)) < 0; | |
18810 | SET_ZFLG (((int8_t)(newv)) == 0); | |
18811 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
18812 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
18813 | SET_NFLG (flgn != 0); | |
18814 | }}}}}}}m68k_incpc(6); | |
18815 | return 16; | |
18816 | } | |
18817 | unsigned long CPUFUNC(op_b03a_4)(uint32_t opcode) /* CMP */ | |
18818 | { | |
18819 | uint32_t dstreg = (opcode >> 9) & 7; | |
18820 | OpcodeFamily = 25; CurrentInstrCycles = 12; | |
18821 | {{ uint32_t srca = m68k_getpc () + 2; | |
18822 | srca += (int32_t)(int16_t)get_iword(2); | |
18823 | { int8_t src = m68k_read_memory_8(srca); | |
18824 | { int8_t dst = m68k_dreg(regs, dstreg); | |
18825 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
18826 | { int flgs = ((int8_t)(src)) < 0; | |
18827 | int flgo = ((int8_t)(dst)) < 0; | |
18828 | int flgn = ((int8_t)(newv)) < 0; | |
18829 | SET_ZFLG (((int8_t)(newv)) == 0); | |
18830 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
18831 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
18832 | SET_NFLG (flgn != 0); | |
18833 | }}}}}}}m68k_incpc(4); | |
18834 | return 12; | |
18835 | } | |
18836 | unsigned long CPUFUNC(op_b03b_4)(uint32_t opcode) /* CMP */ | |
18837 | { | |
18838 | uint32_t dstreg = (opcode >> 9) & 7; | |
18839 | OpcodeFamily = 25; CurrentInstrCycles = 14; | |
18840 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
18841 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
18842 | BusCyclePenalty += 2; | |
18843 | { int8_t src = m68k_read_memory_8(srca); | |
18844 | { int8_t dst = m68k_dreg(regs, dstreg); | |
18845 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
18846 | { int flgs = ((int8_t)(src)) < 0; | |
18847 | int flgo = ((int8_t)(dst)) < 0; | |
18848 | int flgn = ((int8_t)(newv)) < 0; | |
18849 | SET_ZFLG (((int8_t)(newv)) == 0); | |
18850 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
18851 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
18852 | SET_NFLG (flgn != 0); | |
18853 | }}}}}}}m68k_incpc(4); | |
18854 | return 14; | |
18855 | } | |
18856 | #endif | |
18857 | ||
18858 | #ifdef PART_7 | |
18859 | unsigned long CPUFUNC(op_b03c_4)(uint32_t opcode) /* CMP */ | |
18860 | { | |
18861 | uint32_t dstreg = (opcode >> 9) & 7; | |
18862 | OpcodeFamily = 25; CurrentInstrCycles = 8; | |
18863 | {{ int8_t src = get_ibyte(2); | |
18864 | { int8_t dst = m68k_dreg(regs, dstreg); | |
18865 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
18866 | { int flgs = ((int8_t)(src)) < 0; | |
18867 | int flgo = ((int8_t)(dst)) < 0; | |
18868 | int flgn = ((int8_t)(newv)) < 0; | |
18869 | SET_ZFLG (((int8_t)(newv)) == 0); | |
18870 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
18871 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
18872 | SET_NFLG (flgn != 0); | |
18873 | }}}}}}m68k_incpc(4); | |
18874 | return 8; | |
18875 | } | |
18876 | unsigned long CPUFUNC(op_b040_4)(uint32_t opcode) /* CMP */ | |
18877 | { | |
18878 | uint32_t srcreg = (opcode & 7); | |
18879 | uint32_t dstreg = (opcode >> 9) & 7; | |
18880 | OpcodeFamily = 25; CurrentInstrCycles = 4; | |
18881 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
18882 | { int16_t dst = m68k_dreg(regs, dstreg); | |
18883 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
18884 | { int flgs = ((int16_t)(src)) < 0; | |
18885 | int flgo = ((int16_t)(dst)) < 0; | |
18886 | int flgn = ((int16_t)(newv)) < 0; | |
18887 | SET_ZFLG (((int16_t)(newv)) == 0); | |
18888 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
18889 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
18890 | SET_NFLG (flgn != 0); | |
18891 | }}}}}}m68k_incpc(2); | |
18892 | return 4; | |
18893 | } | |
18894 | unsigned long CPUFUNC(op_b048_4)(uint32_t opcode) /* CMP */ | |
18895 | { | |
18896 | uint32_t srcreg = (opcode & 7); | |
18897 | uint32_t dstreg = (opcode >> 9) & 7; | |
18898 | OpcodeFamily = 25; CurrentInstrCycles = 4; | |
18899 | {{ int16_t src = m68k_areg(regs, srcreg); | |
18900 | { int16_t dst = m68k_dreg(regs, dstreg); | |
18901 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
18902 | { int flgs = ((int16_t)(src)) < 0; | |
18903 | int flgo = ((int16_t)(dst)) < 0; | |
18904 | int flgn = ((int16_t)(newv)) < 0; | |
18905 | SET_ZFLG (((int16_t)(newv)) == 0); | |
18906 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
18907 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
18908 | SET_NFLG (flgn != 0); | |
18909 | }}}}}}m68k_incpc(2); | |
18910 | return 4; | |
18911 | } | |
18912 | unsigned long CPUFUNC(op_b050_4)(uint32_t opcode) /* CMP */ | |
18913 | { | |
18914 | uint32_t srcreg = (opcode & 7); | |
18915 | uint32_t dstreg = (opcode >> 9) & 7; | |
18916 | OpcodeFamily = 25; CurrentInstrCycles = 8; | |
18917 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
18918 | { int16_t src = m68k_read_memory_16(srca); | |
18919 | { int16_t dst = m68k_dreg(regs, dstreg); | |
18920 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
18921 | { int flgs = ((int16_t)(src)) < 0; | |
18922 | int flgo = ((int16_t)(dst)) < 0; | |
18923 | int flgn = ((int16_t)(newv)) < 0; | |
18924 | SET_ZFLG (((int16_t)(newv)) == 0); | |
18925 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
18926 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
18927 | SET_NFLG (flgn != 0); | |
18928 | }}}}}}}m68k_incpc(2); | |
18929 | return 8; | |
18930 | } | |
18931 | unsigned long CPUFUNC(op_b058_4)(uint32_t opcode) /* CMP */ | |
18932 | { | |
18933 | uint32_t srcreg = (opcode & 7); | |
18934 | uint32_t dstreg = (opcode >> 9) & 7; | |
18935 | OpcodeFamily = 25; CurrentInstrCycles = 8; | |
18936 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
18937 | { int16_t src = m68k_read_memory_16(srca); | |
18938 | m68k_areg(regs, srcreg) += 2; | |
18939 | { int16_t dst = m68k_dreg(regs, dstreg); | |
18940 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
18941 | { int flgs = ((int16_t)(src)) < 0; | |
18942 | int flgo = ((int16_t)(dst)) < 0; | |
18943 | int flgn = ((int16_t)(newv)) < 0; | |
18944 | SET_ZFLG (((int16_t)(newv)) == 0); | |
18945 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
18946 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
18947 | SET_NFLG (flgn != 0); | |
18948 | }}}}}}}m68k_incpc(2); | |
18949 | return 8; | |
18950 | } | |
18951 | unsigned long CPUFUNC(op_b060_4)(uint32_t opcode) /* CMP */ | |
18952 | { | |
18953 | uint32_t srcreg = (opcode & 7); | |
18954 | uint32_t dstreg = (opcode >> 9) & 7; | |
18955 | OpcodeFamily = 25; CurrentInstrCycles = 10; | |
18956 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
18957 | { int16_t src = m68k_read_memory_16(srca); | |
18958 | m68k_areg (regs, srcreg) = srca; | |
18959 | { int16_t dst = m68k_dreg(regs, dstreg); | |
18960 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
18961 | { int flgs = ((int16_t)(src)) < 0; | |
18962 | int flgo = ((int16_t)(dst)) < 0; | |
18963 | int flgn = ((int16_t)(newv)) < 0; | |
18964 | SET_ZFLG (((int16_t)(newv)) == 0); | |
18965 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
18966 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
18967 | SET_NFLG (flgn != 0); | |
18968 | }}}}}}}m68k_incpc(2); | |
18969 | return 10; | |
18970 | } | |
18971 | unsigned long CPUFUNC(op_b068_4)(uint32_t opcode) /* CMP */ | |
18972 | { | |
18973 | uint32_t srcreg = (opcode & 7); | |
18974 | uint32_t dstreg = (opcode >> 9) & 7; | |
18975 | OpcodeFamily = 25; CurrentInstrCycles = 12; | |
18976 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
18977 | { int16_t src = m68k_read_memory_16(srca); | |
18978 | { int16_t dst = m68k_dreg(regs, dstreg); | |
18979 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
18980 | { int flgs = ((int16_t)(src)) < 0; | |
18981 | int flgo = ((int16_t)(dst)) < 0; | |
18982 | int flgn = ((int16_t)(newv)) < 0; | |
18983 | SET_ZFLG (((int16_t)(newv)) == 0); | |
18984 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
18985 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
18986 | SET_NFLG (flgn != 0); | |
18987 | }}}}}}}m68k_incpc(4); | |
18988 | return 12; | |
18989 | } | |
18990 | unsigned long CPUFUNC(op_b070_4)(uint32_t opcode) /* CMP */ | |
18991 | { | |
18992 | uint32_t srcreg = (opcode & 7); | |
18993 | uint32_t dstreg = (opcode >> 9) & 7; | |
18994 | OpcodeFamily = 25; CurrentInstrCycles = 14; | |
18995 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
18996 | BusCyclePenalty += 2; | |
18997 | { int16_t src = m68k_read_memory_16(srca); | |
18998 | { int16_t dst = m68k_dreg(regs, dstreg); | |
18999 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
19000 | { int flgs = ((int16_t)(src)) < 0; | |
19001 | int flgo = ((int16_t)(dst)) < 0; | |
19002 | int flgn = ((int16_t)(newv)) < 0; | |
19003 | SET_ZFLG (((int16_t)(newv)) == 0); | |
19004 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
19005 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
19006 | SET_NFLG (flgn != 0); | |
19007 | }}}}}}}m68k_incpc(4); | |
19008 | return 14; | |
19009 | } | |
19010 | unsigned long CPUFUNC(op_b078_4)(uint32_t opcode) /* CMP */ | |
19011 | { | |
19012 | uint32_t dstreg = (opcode >> 9) & 7; | |
19013 | OpcodeFamily = 25; CurrentInstrCycles = 12; | |
19014 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
19015 | { int16_t src = m68k_read_memory_16(srca); | |
19016 | { int16_t dst = m68k_dreg(regs, dstreg); | |
19017 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
19018 | { int flgs = ((int16_t)(src)) < 0; | |
19019 | int flgo = ((int16_t)(dst)) < 0; | |
19020 | int flgn = ((int16_t)(newv)) < 0; | |
19021 | SET_ZFLG (((int16_t)(newv)) == 0); | |
19022 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
19023 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
19024 | SET_NFLG (flgn != 0); | |
19025 | }}}}}}}m68k_incpc(4); | |
19026 | return 12; | |
19027 | } | |
19028 | unsigned long CPUFUNC(op_b079_4)(uint32_t opcode) /* CMP */ | |
19029 | { | |
19030 | uint32_t dstreg = (opcode >> 9) & 7; | |
19031 | OpcodeFamily = 25; CurrentInstrCycles = 16; | |
19032 | {{ uint32_t srca = get_ilong(2); | |
19033 | { int16_t src = m68k_read_memory_16(srca); | |
19034 | { int16_t dst = m68k_dreg(regs, dstreg); | |
19035 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
19036 | { int flgs = ((int16_t)(src)) < 0; | |
19037 | int flgo = ((int16_t)(dst)) < 0; | |
19038 | int flgn = ((int16_t)(newv)) < 0; | |
19039 | SET_ZFLG (((int16_t)(newv)) == 0); | |
19040 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
19041 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
19042 | SET_NFLG (flgn != 0); | |
19043 | }}}}}}}m68k_incpc(6); | |
19044 | return 16; | |
19045 | } | |
19046 | unsigned long CPUFUNC(op_b07a_4)(uint32_t opcode) /* CMP */ | |
19047 | { | |
19048 | uint32_t dstreg = (opcode >> 9) & 7; | |
19049 | OpcodeFamily = 25; CurrentInstrCycles = 12; | |
19050 | {{ uint32_t srca = m68k_getpc () + 2; | |
19051 | srca += (int32_t)(int16_t)get_iword(2); | |
19052 | { int16_t src = m68k_read_memory_16(srca); | |
19053 | { int16_t dst = m68k_dreg(regs, dstreg); | |
19054 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
19055 | { int flgs = ((int16_t)(src)) < 0; | |
19056 | int flgo = ((int16_t)(dst)) < 0; | |
19057 | int flgn = ((int16_t)(newv)) < 0; | |
19058 | SET_ZFLG (((int16_t)(newv)) == 0); | |
19059 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
19060 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
19061 | SET_NFLG (flgn != 0); | |
19062 | }}}}}}}m68k_incpc(4); | |
19063 | return 12; | |
19064 | } | |
19065 | unsigned long CPUFUNC(op_b07b_4)(uint32_t opcode) /* CMP */ | |
19066 | { | |
19067 | uint32_t dstreg = (opcode >> 9) & 7; | |
19068 | OpcodeFamily = 25; CurrentInstrCycles = 14; | |
19069 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
19070 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
19071 | BusCyclePenalty += 2; | |
19072 | { int16_t src = m68k_read_memory_16(srca); | |
19073 | { int16_t dst = m68k_dreg(regs, dstreg); | |
19074 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
19075 | { int flgs = ((int16_t)(src)) < 0; | |
19076 | int flgo = ((int16_t)(dst)) < 0; | |
19077 | int flgn = ((int16_t)(newv)) < 0; | |
19078 | SET_ZFLG (((int16_t)(newv)) == 0); | |
19079 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
19080 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
19081 | SET_NFLG (flgn != 0); | |
19082 | }}}}}}}m68k_incpc(4); | |
19083 | return 14; | |
19084 | } | |
19085 | unsigned long CPUFUNC(op_b07c_4)(uint32_t opcode) /* CMP */ | |
19086 | { | |
19087 | uint32_t dstreg = (opcode >> 9) & 7; | |
19088 | OpcodeFamily = 25; CurrentInstrCycles = 8; | |
19089 | {{ int16_t src = get_iword(2); | |
19090 | { int16_t dst = m68k_dreg(regs, dstreg); | |
19091 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
19092 | { int flgs = ((int16_t)(src)) < 0; | |
19093 | int flgo = ((int16_t)(dst)) < 0; | |
19094 | int flgn = ((int16_t)(newv)) < 0; | |
19095 | SET_ZFLG (((int16_t)(newv)) == 0); | |
19096 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
19097 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
19098 | SET_NFLG (flgn != 0); | |
19099 | }}}}}}m68k_incpc(4); | |
19100 | return 8; | |
19101 | } | |
19102 | unsigned long CPUFUNC(op_b080_4)(uint32_t opcode) /* CMP */ | |
19103 | { | |
19104 | uint32_t srcreg = (opcode & 7); | |
19105 | uint32_t dstreg = (opcode >> 9) & 7; | |
19106 | OpcodeFamily = 25; CurrentInstrCycles = 6; | |
19107 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
19108 | { int32_t dst = m68k_dreg(regs, dstreg); | |
19109 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
19110 | { int flgs = ((int32_t)(src)) < 0; | |
19111 | int flgo = ((int32_t)(dst)) < 0; | |
19112 | int flgn = ((int32_t)(newv)) < 0; | |
19113 | SET_ZFLG (((int32_t)(newv)) == 0); | |
19114 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
19115 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
19116 | SET_NFLG (flgn != 0); | |
19117 | }}}}}}m68k_incpc(2); | |
19118 | return 6; | |
19119 | } | |
19120 | unsigned long CPUFUNC(op_b088_4)(uint32_t opcode) /* CMP */ | |
19121 | { | |
19122 | uint32_t srcreg = (opcode & 7); | |
19123 | uint32_t dstreg = (opcode >> 9) & 7; | |
19124 | OpcodeFamily = 25; CurrentInstrCycles = 6; | |
19125 | {{ int32_t src = m68k_areg(regs, srcreg); | |
19126 | { int32_t dst = m68k_dreg(regs, dstreg); | |
19127 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
19128 | { int flgs = ((int32_t)(src)) < 0; | |
19129 | int flgo = ((int32_t)(dst)) < 0; | |
19130 | int flgn = ((int32_t)(newv)) < 0; | |
19131 | SET_ZFLG (((int32_t)(newv)) == 0); | |
19132 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
19133 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
19134 | SET_NFLG (flgn != 0); | |
19135 | }}}}}}m68k_incpc(2); | |
19136 | return 6; | |
19137 | } | |
19138 | unsigned long CPUFUNC(op_b090_4)(uint32_t opcode) /* CMP */ | |
19139 | { | |
19140 | uint32_t srcreg = (opcode & 7); | |
19141 | uint32_t dstreg = (opcode >> 9) & 7; | |
19142 | OpcodeFamily = 25; CurrentInstrCycles = 14; | |
19143 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
19144 | { int32_t src = m68k_read_memory_32(srca); | |
19145 | { int32_t dst = m68k_dreg(regs, dstreg); | |
19146 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
19147 | { int flgs = ((int32_t)(src)) < 0; | |
19148 | int flgo = ((int32_t)(dst)) < 0; | |
19149 | int flgn = ((int32_t)(newv)) < 0; | |
19150 | SET_ZFLG (((int32_t)(newv)) == 0); | |
19151 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
19152 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
19153 | SET_NFLG (flgn != 0); | |
19154 | }}}}}}}m68k_incpc(2); | |
19155 | return 14; | |
19156 | } | |
19157 | unsigned long CPUFUNC(op_b098_4)(uint32_t opcode) /* CMP */ | |
19158 | { | |
19159 | uint32_t srcreg = (opcode & 7); | |
19160 | uint32_t dstreg = (opcode >> 9) & 7; | |
19161 | OpcodeFamily = 25; CurrentInstrCycles = 14; | |
19162 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
19163 | { int32_t src = m68k_read_memory_32(srca); | |
19164 | m68k_areg(regs, srcreg) += 4; | |
19165 | { int32_t dst = m68k_dreg(regs, dstreg); | |
19166 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
19167 | { int flgs = ((int32_t)(src)) < 0; | |
19168 | int flgo = ((int32_t)(dst)) < 0; | |
19169 | int flgn = ((int32_t)(newv)) < 0; | |
19170 | SET_ZFLG (((int32_t)(newv)) == 0); | |
19171 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
19172 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
19173 | SET_NFLG (flgn != 0); | |
19174 | }}}}}}}m68k_incpc(2); | |
19175 | return 14; | |
19176 | } | |
19177 | unsigned long CPUFUNC(op_b0a0_4)(uint32_t opcode) /* CMP */ | |
19178 | { | |
19179 | uint32_t srcreg = (opcode & 7); | |
19180 | uint32_t dstreg = (opcode >> 9) & 7; | |
19181 | OpcodeFamily = 25; CurrentInstrCycles = 16; | |
19182 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 4; | |
19183 | { int32_t src = m68k_read_memory_32(srca); | |
19184 | m68k_areg (regs, srcreg) = srca; | |
19185 | { int32_t dst = m68k_dreg(regs, dstreg); | |
19186 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
19187 | { int flgs = ((int32_t)(src)) < 0; | |
19188 | int flgo = ((int32_t)(dst)) < 0; | |
19189 | int flgn = ((int32_t)(newv)) < 0; | |
19190 | SET_ZFLG (((int32_t)(newv)) == 0); | |
19191 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
19192 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
19193 | SET_NFLG (flgn != 0); | |
19194 | }}}}}}}m68k_incpc(2); | |
19195 | return 16; | |
19196 | } | |
19197 | unsigned long CPUFUNC(op_b0a8_4)(uint32_t opcode) /* CMP */ | |
19198 | { | |
19199 | uint32_t srcreg = (opcode & 7); | |
19200 | uint32_t dstreg = (opcode >> 9) & 7; | |
19201 | OpcodeFamily = 25; CurrentInstrCycles = 18; | |
19202 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
19203 | { int32_t src = m68k_read_memory_32(srca); | |
19204 | { int32_t dst = m68k_dreg(regs, dstreg); | |
19205 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
19206 | { int flgs = ((int32_t)(src)) < 0; | |
19207 | int flgo = ((int32_t)(dst)) < 0; | |
19208 | int flgn = ((int32_t)(newv)) < 0; | |
19209 | SET_ZFLG (((int32_t)(newv)) == 0); | |
19210 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
19211 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
19212 | SET_NFLG (flgn != 0); | |
19213 | }}}}}}}m68k_incpc(4); | |
19214 | return 18; | |
19215 | } | |
19216 | unsigned long CPUFUNC(op_b0b0_4)(uint32_t opcode) /* CMP */ | |
19217 | { | |
19218 | uint32_t srcreg = (opcode & 7); | |
19219 | uint32_t dstreg = (opcode >> 9) & 7; | |
19220 | OpcodeFamily = 25; CurrentInstrCycles = 20; | |
19221 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
19222 | BusCyclePenalty += 2; | |
19223 | { int32_t src = m68k_read_memory_32(srca); | |
19224 | { int32_t dst = m68k_dreg(regs, dstreg); | |
19225 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
19226 | { int flgs = ((int32_t)(src)) < 0; | |
19227 | int flgo = ((int32_t)(dst)) < 0; | |
19228 | int flgn = ((int32_t)(newv)) < 0; | |
19229 | SET_ZFLG (((int32_t)(newv)) == 0); | |
19230 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
19231 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
19232 | SET_NFLG (flgn != 0); | |
19233 | }}}}}}}m68k_incpc(4); | |
19234 | return 20; | |
19235 | } | |
19236 | unsigned long CPUFUNC(op_b0b8_4)(uint32_t opcode) /* CMP */ | |
19237 | { | |
19238 | uint32_t dstreg = (opcode >> 9) & 7; | |
19239 | OpcodeFamily = 25; CurrentInstrCycles = 18; | |
19240 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
19241 | { int32_t src = m68k_read_memory_32(srca); | |
19242 | { int32_t dst = m68k_dreg(regs, dstreg); | |
19243 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
19244 | { int flgs = ((int32_t)(src)) < 0; | |
19245 | int flgo = ((int32_t)(dst)) < 0; | |
19246 | int flgn = ((int32_t)(newv)) < 0; | |
19247 | SET_ZFLG (((int32_t)(newv)) == 0); | |
19248 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
19249 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
19250 | SET_NFLG (flgn != 0); | |
19251 | }}}}}}}m68k_incpc(4); | |
19252 | return 18; | |
19253 | } | |
19254 | unsigned long CPUFUNC(op_b0b9_4)(uint32_t opcode) /* CMP */ | |
19255 | { | |
19256 | uint32_t dstreg = (opcode >> 9) & 7; | |
19257 | OpcodeFamily = 25; CurrentInstrCycles = 22; | |
19258 | {{ uint32_t srca = get_ilong(2); | |
19259 | { int32_t src = m68k_read_memory_32(srca); | |
19260 | { int32_t dst = m68k_dreg(regs, dstreg); | |
19261 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
19262 | { int flgs = ((int32_t)(src)) < 0; | |
19263 | int flgo = ((int32_t)(dst)) < 0; | |
19264 | int flgn = ((int32_t)(newv)) < 0; | |
19265 | SET_ZFLG (((int32_t)(newv)) == 0); | |
19266 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
19267 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
19268 | SET_NFLG (flgn != 0); | |
19269 | }}}}}}}m68k_incpc(6); | |
19270 | return 22; | |
19271 | } | |
19272 | unsigned long CPUFUNC(op_b0ba_4)(uint32_t opcode) /* CMP */ | |
19273 | { | |
19274 | uint32_t dstreg = (opcode >> 9) & 7; | |
19275 | OpcodeFamily = 25; CurrentInstrCycles = 18; | |
19276 | {{ uint32_t srca = m68k_getpc () + 2; | |
19277 | srca += (int32_t)(int16_t)get_iword(2); | |
19278 | { int32_t src = m68k_read_memory_32(srca); | |
19279 | { int32_t dst = m68k_dreg(regs, dstreg); | |
19280 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
19281 | { int flgs = ((int32_t)(src)) < 0; | |
19282 | int flgo = ((int32_t)(dst)) < 0; | |
19283 | int flgn = ((int32_t)(newv)) < 0; | |
19284 | SET_ZFLG (((int32_t)(newv)) == 0); | |
19285 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
19286 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
19287 | SET_NFLG (flgn != 0); | |
19288 | }}}}}}}m68k_incpc(4); | |
19289 | return 18; | |
19290 | } | |
19291 | unsigned long CPUFUNC(op_b0bb_4)(uint32_t opcode) /* CMP */ | |
19292 | { | |
19293 | uint32_t dstreg = (opcode >> 9) & 7; | |
19294 | OpcodeFamily = 25; CurrentInstrCycles = 20; | |
19295 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
19296 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
19297 | BusCyclePenalty += 2; | |
19298 | { int32_t src = m68k_read_memory_32(srca); | |
19299 | { int32_t dst = m68k_dreg(regs, dstreg); | |
19300 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
19301 | { int flgs = ((int32_t)(src)) < 0; | |
19302 | int flgo = ((int32_t)(dst)) < 0; | |
19303 | int flgn = ((int32_t)(newv)) < 0; | |
19304 | SET_ZFLG (((int32_t)(newv)) == 0); | |
19305 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
19306 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
19307 | SET_NFLG (flgn != 0); | |
19308 | }}}}}}}m68k_incpc(4); | |
19309 | return 20; | |
19310 | } | |
19311 | unsigned long CPUFUNC(op_b0bc_4)(uint32_t opcode) /* CMP */ | |
19312 | { | |
19313 | uint32_t dstreg = (opcode >> 9) & 7; | |
19314 | OpcodeFamily = 25; CurrentInstrCycles = 14; | |
19315 | {{ int32_t src = get_ilong(2); | |
19316 | { int32_t dst = m68k_dreg(regs, dstreg); | |
19317 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
19318 | { int flgs = ((int32_t)(src)) < 0; | |
19319 | int flgo = ((int32_t)(dst)) < 0; | |
19320 | int flgn = ((int32_t)(newv)) < 0; | |
19321 | SET_ZFLG (((int32_t)(newv)) == 0); | |
19322 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
19323 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
19324 | SET_NFLG (flgn != 0); | |
19325 | }}}}}}m68k_incpc(6); | |
19326 | return 14; | |
19327 | } | |
19328 | unsigned long CPUFUNC(op_b0c0_4)(uint32_t opcode) /* CMPA */ | |
19329 | { | |
19330 | uint32_t srcreg = (opcode & 7); | |
19331 | uint32_t dstreg = (opcode >> 9) & 7; | |
19332 | OpcodeFamily = 27; CurrentInstrCycles = 6; | |
19333 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
19334 | { int32_t dst = m68k_areg(regs, dstreg); | |
19335 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
19336 | { int flgs = ((int32_t)(src)) < 0; | |
19337 | int flgo = ((int32_t)(dst)) < 0; | |
19338 | int flgn = ((int32_t)(newv)) < 0; | |
19339 | SET_ZFLG (((int32_t)(newv)) == 0); | |
19340 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
19341 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
19342 | SET_NFLG (flgn != 0); | |
19343 | }}}}}}m68k_incpc(2); | |
19344 | return 6; | |
19345 | } | |
19346 | unsigned long CPUFUNC(op_b0c8_4)(uint32_t opcode) /* CMPA */ | |
19347 | { | |
19348 | uint32_t srcreg = (opcode & 7); | |
19349 | uint32_t dstreg = (opcode >> 9) & 7; | |
19350 | OpcodeFamily = 27; CurrentInstrCycles = 6; | |
19351 | {{ int16_t src = m68k_areg(regs, srcreg); | |
19352 | { int32_t dst = m68k_areg(regs, dstreg); | |
19353 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
19354 | { int flgs = ((int32_t)(src)) < 0; | |
19355 | int flgo = ((int32_t)(dst)) < 0; | |
19356 | int flgn = ((int32_t)(newv)) < 0; | |
19357 | SET_ZFLG (((int32_t)(newv)) == 0); | |
19358 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
19359 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
19360 | SET_NFLG (flgn != 0); | |
19361 | }}}}}}m68k_incpc(2); | |
19362 | return 6; | |
19363 | } | |
19364 | unsigned long CPUFUNC(op_b0d0_4)(uint32_t opcode) /* CMPA */ | |
19365 | { | |
19366 | uint32_t srcreg = (opcode & 7); | |
19367 | uint32_t dstreg = (opcode >> 9) & 7; | |
19368 | OpcodeFamily = 27; CurrentInstrCycles = 10; | |
19369 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
19370 | { int16_t src = m68k_read_memory_16(srca); | |
19371 | { int32_t dst = m68k_areg(regs, dstreg); | |
19372 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
19373 | { int flgs = ((int32_t)(src)) < 0; | |
19374 | int flgo = ((int32_t)(dst)) < 0; | |
19375 | int flgn = ((int32_t)(newv)) < 0; | |
19376 | SET_ZFLG (((int32_t)(newv)) == 0); | |
19377 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
19378 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
19379 | SET_NFLG (flgn != 0); | |
19380 | }}}}}}}m68k_incpc(2); | |
19381 | return 10; | |
19382 | } | |
19383 | unsigned long CPUFUNC(op_b0d8_4)(uint32_t opcode) /* CMPA */ | |
19384 | { | |
19385 | uint32_t srcreg = (opcode & 7); | |
19386 | uint32_t dstreg = (opcode >> 9) & 7; | |
19387 | OpcodeFamily = 27; CurrentInstrCycles = 10; | |
19388 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
19389 | { int16_t src = m68k_read_memory_16(srca); | |
19390 | m68k_areg(regs, srcreg) += 2; | |
19391 | { int32_t dst = m68k_areg(regs, dstreg); | |
19392 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
19393 | { int flgs = ((int32_t)(src)) < 0; | |
19394 | int flgo = ((int32_t)(dst)) < 0; | |
19395 | int flgn = ((int32_t)(newv)) < 0; | |
19396 | SET_ZFLG (((int32_t)(newv)) == 0); | |
19397 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
19398 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
19399 | SET_NFLG (flgn != 0); | |
19400 | }}}}}}}m68k_incpc(2); | |
19401 | return 10; | |
19402 | } | |
19403 | unsigned long CPUFUNC(op_b0e0_4)(uint32_t opcode) /* CMPA */ | |
19404 | { | |
19405 | uint32_t srcreg = (opcode & 7); | |
19406 | uint32_t dstreg = (opcode >> 9) & 7; | |
19407 | OpcodeFamily = 27; CurrentInstrCycles = 12; | |
19408 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
19409 | { int16_t src = m68k_read_memory_16(srca); | |
19410 | m68k_areg (regs, srcreg) = srca; | |
19411 | { int32_t dst = m68k_areg(regs, dstreg); | |
19412 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
19413 | { int flgs = ((int32_t)(src)) < 0; | |
19414 | int flgo = ((int32_t)(dst)) < 0; | |
19415 | int flgn = ((int32_t)(newv)) < 0; | |
19416 | SET_ZFLG (((int32_t)(newv)) == 0); | |
19417 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
19418 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
19419 | SET_NFLG (flgn != 0); | |
19420 | }}}}}}}m68k_incpc(2); | |
19421 | return 12; | |
19422 | } | |
19423 | unsigned long CPUFUNC(op_b0e8_4)(uint32_t opcode) /* CMPA */ | |
19424 | { | |
19425 | uint32_t srcreg = (opcode & 7); | |
19426 | uint32_t dstreg = (opcode >> 9) & 7; | |
19427 | OpcodeFamily = 27; CurrentInstrCycles = 14; | |
19428 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
19429 | { int16_t src = m68k_read_memory_16(srca); | |
19430 | { int32_t dst = m68k_areg(regs, dstreg); | |
19431 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
19432 | { int flgs = ((int32_t)(src)) < 0; | |
19433 | int flgo = ((int32_t)(dst)) < 0; | |
19434 | int flgn = ((int32_t)(newv)) < 0; | |
19435 | SET_ZFLG (((int32_t)(newv)) == 0); | |
19436 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
19437 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
19438 | SET_NFLG (flgn != 0); | |
19439 | }}}}}}}m68k_incpc(4); | |
19440 | return 14; | |
19441 | } | |
19442 | unsigned long CPUFUNC(op_b0f0_4)(uint32_t opcode) /* CMPA */ | |
19443 | { | |
19444 | uint32_t srcreg = (opcode & 7); | |
19445 | uint32_t dstreg = (opcode >> 9) & 7; | |
19446 | OpcodeFamily = 27; CurrentInstrCycles = 16; | |
19447 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
19448 | BusCyclePenalty += 2; | |
19449 | { int16_t src = m68k_read_memory_16(srca); | |
19450 | { int32_t dst = m68k_areg(regs, dstreg); | |
19451 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
19452 | { int flgs = ((int32_t)(src)) < 0; | |
19453 | int flgo = ((int32_t)(dst)) < 0; | |
19454 | int flgn = ((int32_t)(newv)) < 0; | |
19455 | SET_ZFLG (((int32_t)(newv)) == 0); | |
19456 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
19457 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
19458 | SET_NFLG (flgn != 0); | |
19459 | }}}}}}}m68k_incpc(4); | |
19460 | return 16; | |
19461 | } | |
19462 | unsigned long CPUFUNC(op_b0f8_4)(uint32_t opcode) /* CMPA */ | |
19463 | { | |
19464 | uint32_t dstreg = (opcode >> 9) & 7; | |
19465 | OpcodeFamily = 27; CurrentInstrCycles = 14; | |
19466 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
19467 | { int16_t src = m68k_read_memory_16(srca); | |
19468 | { int32_t dst = m68k_areg(regs, dstreg); | |
19469 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
19470 | { int flgs = ((int32_t)(src)) < 0; | |
19471 | int flgo = ((int32_t)(dst)) < 0; | |
19472 | int flgn = ((int32_t)(newv)) < 0; | |
19473 | SET_ZFLG (((int32_t)(newv)) == 0); | |
19474 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
19475 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
19476 | SET_NFLG (flgn != 0); | |
19477 | }}}}}}}m68k_incpc(4); | |
19478 | return 14; | |
19479 | } | |
19480 | unsigned long CPUFUNC(op_b0f9_4)(uint32_t opcode) /* CMPA */ | |
19481 | { | |
19482 | uint32_t dstreg = (opcode >> 9) & 7; | |
19483 | OpcodeFamily = 27; CurrentInstrCycles = 18; | |
19484 | {{ uint32_t srca = get_ilong(2); | |
19485 | { int16_t src = m68k_read_memory_16(srca); | |
19486 | { int32_t dst = m68k_areg(regs, dstreg); | |
19487 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
19488 | { int flgs = ((int32_t)(src)) < 0; | |
19489 | int flgo = ((int32_t)(dst)) < 0; | |
19490 | int flgn = ((int32_t)(newv)) < 0; | |
19491 | SET_ZFLG (((int32_t)(newv)) == 0); | |
19492 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
19493 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
19494 | SET_NFLG (flgn != 0); | |
19495 | }}}}}}}m68k_incpc(6); | |
19496 | return 18; | |
19497 | } | |
19498 | unsigned long CPUFUNC(op_b0fa_4)(uint32_t opcode) /* CMPA */ | |
19499 | { | |
19500 | uint32_t dstreg = (opcode >> 9) & 7; | |
19501 | OpcodeFamily = 27; CurrentInstrCycles = 14; | |
19502 | {{ uint32_t srca = m68k_getpc () + 2; | |
19503 | srca += (int32_t)(int16_t)get_iword(2); | |
19504 | { int16_t src = m68k_read_memory_16(srca); | |
19505 | { int32_t dst = m68k_areg(regs, dstreg); | |
19506 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
19507 | { int flgs = ((int32_t)(src)) < 0; | |
19508 | int flgo = ((int32_t)(dst)) < 0; | |
19509 | int flgn = ((int32_t)(newv)) < 0; | |
19510 | SET_ZFLG (((int32_t)(newv)) == 0); | |
19511 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
19512 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
19513 | SET_NFLG (flgn != 0); | |
19514 | }}}}}}}m68k_incpc(4); | |
19515 | return 14; | |
19516 | } | |
19517 | unsigned long CPUFUNC(op_b0fb_4)(uint32_t opcode) /* CMPA */ | |
19518 | { | |
19519 | uint32_t dstreg = (opcode >> 9) & 7; | |
19520 | OpcodeFamily = 27; CurrentInstrCycles = 16; | |
19521 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
19522 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
19523 | BusCyclePenalty += 2; | |
19524 | { int16_t src = m68k_read_memory_16(srca); | |
19525 | { int32_t dst = m68k_areg(regs, dstreg); | |
19526 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
19527 | { int flgs = ((int32_t)(src)) < 0; | |
19528 | int flgo = ((int32_t)(dst)) < 0; | |
19529 | int flgn = ((int32_t)(newv)) < 0; | |
19530 | SET_ZFLG (((int32_t)(newv)) == 0); | |
19531 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
19532 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
19533 | SET_NFLG (flgn != 0); | |
19534 | }}}}}}}m68k_incpc(4); | |
19535 | return 16; | |
19536 | } | |
19537 | unsigned long CPUFUNC(op_b0fc_4)(uint32_t opcode) /* CMPA */ | |
19538 | { | |
19539 | uint32_t dstreg = (opcode >> 9) & 7; | |
19540 | OpcodeFamily = 27; CurrentInstrCycles = 10; | |
19541 | {{ int16_t src = get_iword(2); | |
19542 | { int32_t dst = m68k_areg(regs, dstreg); | |
19543 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
19544 | { int flgs = ((int32_t)(src)) < 0; | |
19545 | int flgo = ((int32_t)(dst)) < 0; | |
19546 | int flgn = ((int32_t)(newv)) < 0; | |
19547 | SET_ZFLG (((int32_t)(newv)) == 0); | |
19548 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
19549 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
19550 | SET_NFLG (flgn != 0); | |
19551 | }}}}}}m68k_incpc(4); | |
19552 | return 10; | |
19553 | } | |
19554 | unsigned long CPUFUNC(op_b100_4)(uint32_t opcode) /* EOR */ | |
19555 | { | |
19556 | uint32_t srcreg = ((opcode >> 9) & 7); | |
19557 | uint32_t dstreg = opcode & 7; | |
19558 | OpcodeFamily = 3; CurrentInstrCycles = 4; | |
19559 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
19560 | { int8_t dst = m68k_dreg(regs, dstreg); | |
19561 | src ^= dst; | |
19562 | CLEAR_CZNV; | |
19563 | SET_ZFLG (((int8_t)(src)) == 0); | |
19564 | SET_NFLG (((int8_t)(src)) < 0); | |
19565 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
19566 | }}}m68k_incpc(2); | |
19567 | return 4; | |
19568 | } | |
19569 | unsigned long CPUFUNC(op_b108_4)(uint32_t opcode) /* CMPM */ | |
19570 | { | |
19571 | uint32_t srcreg = (opcode & 7); | |
19572 | uint32_t dstreg = (opcode >> 9) & 7; | |
19573 | OpcodeFamily = 26; CurrentInstrCycles = 12; | |
19574 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
19575 | { int8_t src = m68k_read_memory_8(srca); | |
19576 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
19577 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
19578 | { int8_t dst = m68k_read_memory_8(dsta); | |
19579 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
19580 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
19581 | { int flgs = ((int8_t)(src)) < 0; | |
19582 | int flgo = ((int8_t)(dst)) < 0; | |
19583 | int flgn = ((int8_t)(newv)) < 0; | |
19584 | SET_ZFLG (((int8_t)(newv)) == 0); | |
19585 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
19586 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
19587 | SET_NFLG (flgn != 0); | |
19588 | }}}}}}}}m68k_incpc(2); | |
19589 | return 12; | |
19590 | } | |
19591 | unsigned long CPUFUNC(op_b110_4)(uint32_t opcode) /* EOR */ | |
19592 | { | |
19593 | uint32_t srcreg = ((opcode >> 9) & 7); | |
19594 | uint32_t dstreg = opcode & 7; | |
19595 | OpcodeFamily = 3; CurrentInstrCycles = 12; | |
19596 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
19597 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
19598 | { int8_t dst = m68k_read_memory_8(dsta); | |
19599 | src ^= dst; | |
19600 | CLEAR_CZNV; | |
19601 | SET_ZFLG (((int8_t)(src)) == 0); | |
19602 | SET_NFLG (((int8_t)(src)) < 0); | |
19603 | m68k_write_memory_8(dsta,src); | |
19604 | }}}}m68k_incpc(2); | |
19605 | return 12; | |
19606 | } | |
19607 | unsigned long CPUFUNC(op_b118_4)(uint32_t opcode) /* EOR */ | |
19608 | { | |
19609 | uint32_t srcreg = ((opcode >> 9) & 7); | |
19610 | uint32_t dstreg = opcode & 7; | |
19611 | OpcodeFamily = 3; CurrentInstrCycles = 12; | |
19612 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
19613 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
19614 | { int8_t dst = m68k_read_memory_8(dsta); | |
19615 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
19616 | src ^= dst; | |
19617 | CLEAR_CZNV; | |
19618 | SET_ZFLG (((int8_t)(src)) == 0); | |
19619 | SET_NFLG (((int8_t)(src)) < 0); | |
19620 | m68k_write_memory_8(dsta,src); | |
19621 | }}}}m68k_incpc(2); | |
19622 | return 12; | |
19623 | } | |
19624 | unsigned long CPUFUNC(op_b120_4)(uint32_t opcode) /* EOR */ | |
19625 | { | |
19626 | uint32_t srcreg = ((opcode >> 9) & 7); | |
19627 | uint32_t dstreg = opcode & 7; | |
19628 | OpcodeFamily = 3; CurrentInstrCycles = 14; | |
19629 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
19630 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
19631 | { int8_t dst = m68k_read_memory_8(dsta); | |
19632 | m68k_areg (regs, dstreg) = dsta; | |
19633 | src ^= dst; | |
19634 | CLEAR_CZNV; | |
19635 | SET_ZFLG (((int8_t)(src)) == 0); | |
19636 | SET_NFLG (((int8_t)(src)) < 0); | |
19637 | m68k_write_memory_8(dsta,src); | |
19638 | }}}}m68k_incpc(2); | |
19639 | return 14; | |
19640 | } | |
19641 | unsigned long CPUFUNC(op_b128_4)(uint32_t opcode) /* EOR */ | |
19642 | { | |
19643 | uint32_t srcreg = ((opcode >> 9) & 7); | |
19644 | uint32_t dstreg = opcode & 7; | |
19645 | OpcodeFamily = 3; CurrentInstrCycles = 16; | |
19646 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
19647 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); | |
19648 | { int8_t dst = m68k_read_memory_8(dsta); | |
19649 | src ^= dst; | |
19650 | CLEAR_CZNV; | |
19651 | SET_ZFLG (((int8_t)(src)) == 0); | |
19652 | SET_NFLG (((int8_t)(src)) < 0); | |
19653 | m68k_write_memory_8(dsta,src); | |
19654 | }}}}m68k_incpc(4); | |
19655 | return 16; | |
19656 | } | |
19657 | unsigned long CPUFUNC(op_b130_4)(uint32_t opcode) /* EOR */ | |
19658 | { | |
19659 | uint32_t srcreg = ((opcode >> 9) & 7); | |
19660 | uint32_t dstreg = opcode & 7; | |
19661 | OpcodeFamily = 3; CurrentInstrCycles = 18; | |
19662 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
19663 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); | |
19664 | BusCyclePenalty += 2; | |
19665 | { int8_t dst = m68k_read_memory_8(dsta); | |
19666 | src ^= dst; | |
19667 | CLEAR_CZNV; | |
19668 | SET_ZFLG (((int8_t)(src)) == 0); | |
19669 | SET_NFLG (((int8_t)(src)) < 0); | |
19670 | m68k_write_memory_8(dsta,src); | |
19671 | }}}}m68k_incpc(4); | |
19672 | return 18; | |
19673 | } | |
19674 | unsigned long CPUFUNC(op_b138_4)(uint32_t opcode) /* EOR */ | |
19675 | { | |
19676 | uint32_t srcreg = ((opcode >> 9) & 7); | |
19677 | OpcodeFamily = 3; CurrentInstrCycles = 16; | |
19678 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
19679 | { uint32_t dsta = (int32_t)(int16_t)get_iword(2); | |
19680 | { int8_t dst = m68k_read_memory_8(dsta); | |
19681 | src ^= dst; | |
19682 | CLEAR_CZNV; | |
19683 | SET_ZFLG (((int8_t)(src)) == 0); | |
19684 | SET_NFLG (((int8_t)(src)) < 0); | |
19685 | m68k_write_memory_8(dsta,src); | |
19686 | }}}}m68k_incpc(4); | |
19687 | return 16; | |
19688 | } | |
19689 | unsigned long CPUFUNC(op_b139_4)(uint32_t opcode) /* EOR */ | |
19690 | { | |
19691 | uint32_t srcreg = ((opcode >> 9) & 7); | |
19692 | OpcodeFamily = 3; CurrentInstrCycles = 20; | |
19693 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
19694 | { uint32_t dsta = get_ilong(2); | |
19695 | { int8_t dst = m68k_read_memory_8(dsta); | |
19696 | src ^= dst; | |
19697 | CLEAR_CZNV; | |
19698 | SET_ZFLG (((int8_t)(src)) == 0); | |
19699 | SET_NFLG (((int8_t)(src)) < 0); | |
19700 | m68k_write_memory_8(dsta,src); | |
19701 | }}}}m68k_incpc(6); | |
19702 | return 20; | |
19703 | } | |
19704 | unsigned long CPUFUNC(op_b140_4)(uint32_t opcode) /* EOR */ | |
19705 | { | |
19706 | uint32_t srcreg = ((opcode >> 9) & 7); | |
19707 | uint32_t dstreg = opcode & 7; | |
19708 | OpcodeFamily = 3; CurrentInstrCycles = 4; | |
19709 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
19710 | { int16_t dst = m68k_dreg(regs, dstreg); | |
19711 | src ^= dst; | |
19712 | CLEAR_CZNV; | |
19713 | SET_ZFLG (((int16_t)(src)) == 0); | |
19714 | SET_NFLG (((int16_t)(src)) < 0); | |
19715 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
19716 | }}}m68k_incpc(2); | |
19717 | return 4; | |
19718 | } | |
19719 | unsigned long CPUFUNC(op_b148_4)(uint32_t opcode) /* CMPM */ | |
19720 | { | |
19721 | uint32_t srcreg = (opcode & 7); | |
19722 | uint32_t dstreg = (opcode >> 9) & 7; | |
19723 | OpcodeFamily = 26; CurrentInstrCycles = 12; | |
19724 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
19725 | { int16_t src = m68k_read_memory_16(srca); | |
19726 | m68k_areg(regs, srcreg) += 2; | |
19727 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
19728 | { int16_t dst = m68k_read_memory_16(dsta); | |
19729 | m68k_areg(regs, dstreg) += 2; | |
19730 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
19731 | { int flgs = ((int16_t)(src)) < 0; | |
19732 | int flgo = ((int16_t)(dst)) < 0; | |
19733 | int flgn = ((int16_t)(newv)) < 0; | |
19734 | SET_ZFLG (((int16_t)(newv)) == 0); | |
19735 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
19736 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
19737 | SET_NFLG (flgn != 0); | |
19738 | }}}}}}}}m68k_incpc(2); | |
19739 | return 12; | |
19740 | } | |
19741 | unsigned long CPUFUNC(op_b150_4)(uint32_t opcode) /* EOR */ | |
19742 | { | |
19743 | uint32_t srcreg = ((opcode >> 9) & 7); | |
19744 | uint32_t dstreg = opcode & 7; | |
19745 | OpcodeFamily = 3; CurrentInstrCycles = 12; | |
19746 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
19747 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
19748 | { int16_t dst = m68k_read_memory_16(dsta); | |
19749 | src ^= dst; | |
19750 | CLEAR_CZNV; | |
19751 | SET_ZFLG (((int16_t)(src)) == 0); | |
19752 | SET_NFLG (((int16_t)(src)) < 0); | |
19753 | m68k_write_memory_16(dsta,src); | |
19754 | }}}}m68k_incpc(2); | |
19755 | return 12; | |
19756 | } | |
19757 | unsigned long CPUFUNC(op_b158_4)(uint32_t opcode) /* EOR */ | |
19758 | { | |
19759 | uint32_t srcreg = ((opcode >> 9) & 7); | |
19760 | uint32_t dstreg = opcode & 7; | |
19761 | OpcodeFamily = 3; CurrentInstrCycles = 12; | |
19762 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
19763 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
19764 | { int16_t dst = m68k_read_memory_16(dsta); | |
19765 | m68k_areg(regs, dstreg) += 2; | |
19766 | src ^= dst; | |
19767 | CLEAR_CZNV; | |
19768 | SET_ZFLG (((int16_t)(src)) == 0); | |
19769 | SET_NFLG (((int16_t)(src)) < 0); | |
19770 | m68k_write_memory_16(dsta,src); | |
19771 | }}}}m68k_incpc(2); | |
19772 | return 12; | |
19773 | } | |
19774 | unsigned long CPUFUNC(op_b160_4)(uint32_t opcode) /* EOR */ | |
19775 | { | |
19776 | uint32_t srcreg = ((opcode >> 9) & 7); | |
19777 | uint32_t dstreg = opcode & 7; | |
19778 | OpcodeFamily = 3; CurrentInstrCycles = 14; | |
19779 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
19780 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
19781 | { int16_t dst = m68k_read_memory_16(dsta); | |
19782 | m68k_areg (regs, dstreg) = dsta; | |
19783 | src ^= dst; | |
19784 | CLEAR_CZNV; | |
19785 | SET_ZFLG (((int16_t)(src)) == 0); | |
19786 | SET_NFLG (((int16_t)(src)) < 0); | |
19787 | m68k_write_memory_16(dsta,src); | |
19788 | }}}}m68k_incpc(2); | |
19789 | return 14; | |
19790 | } | |
19791 | unsigned long CPUFUNC(op_b168_4)(uint32_t opcode) /* EOR */ | |
19792 | { | |
19793 | uint32_t srcreg = ((opcode >> 9) & 7); | |
19794 | uint32_t dstreg = opcode & 7; | |
19795 | OpcodeFamily = 3; CurrentInstrCycles = 16; | |
19796 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
19797 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); | |
19798 | { int16_t dst = m68k_read_memory_16(dsta); | |
19799 | src ^= dst; | |
19800 | CLEAR_CZNV; | |
19801 | SET_ZFLG (((int16_t)(src)) == 0); | |
19802 | SET_NFLG (((int16_t)(src)) < 0); | |
19803 | m68k_write_memory_16(dsta,src); | |
19804 | }}}}m68k_incpc(4); | |
19805 | return 16; | |
19806 | } | |
19807 | unsigned long CPUFUNC(op_b170_4)(uint32_t opcode) /* EOR */ | |
19808 | { | |
19809 | uint32_t srcreg = ((opcode >> 9) & 7); | |
19810 | uint32_t dstreg = opcode & 7; | |
19811 | OpcodeFamily = 3; CurrentInstrCycles = 18; | |
19812 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
19813 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); | |
19814 | BusCyclePenalty += 2; | |
19815 | { int16_t dst = m68k_read_memory_16(dsta); | |
19816 | src ^= dst; | |
19817 | CLEAR_CZNV; | |
19818 | SET_ZFLG (((int16_t)(src)) == 0); | |
19819 | SET_NFLG (((int16_t)(src)) < 0); | |
19820 | m68k_write_memory_16(dsta,src); | |
19821 | }}}}m68k_incpc(4); | |
19822 | return 18; | |
19823 | } | |
19824 | unsigned long CPUFUNC(op_b178_4)(uint32_t opcode) /* EOR */ | |
19825 | { | |
19826 | uint32_t srcreg = ((opcode >> 9) & 7); | |
19827 | OpcodeFamily = 3; CurrentInstrCycles = 16; | |
19828 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
19829 | { uint32_t dsta = (int32_t)(int16_t)get_iword(2); | |
19830 | { int16_t dst = m68k_read_memory_16(dsta); | |
19831 | src ^= dst; | |
19832 | CLEAR_CZNV; | |
19833 | SET_ZFLG (((int16_t)(src)) == 0); | |
19834 | SET_NFLG (((int16_t)(src)) < 0); | |
19835 | m68k_write_memory_16(dsta,src); | |
19836 | }}}}m68k_incpc(4); | |
19837 | return 16; | |
19838 | } | |
19839 | unsigned long CPUFUNC(op_b179_4)(uint32_t opcode) /* EOR */ | |
19840 | { | |
19841 | uint32_t srcreg = ((opcode >> 9) & 7); | |
19842 | OpcodeFamily = 3; CurrentInstrCycles = 20; | |
19843 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
19844 | { uint32_t dsta = get_ilong(2); | |
19845 | { int16_t dst = m68k_read_memory_16(dsta); | |
19846 | src ^= dst; | |
19847 | CLEAR_CZNV; | |
19848 | SET_ZFLG (((int16_t)(src)) == 0); | |
19849 | SET_NFLG (((int16_t)(src)) < 0); | |
19850 | m68k_write_memory_16(dsta,src); | |
19851 | }}}}m68k_incpc(6); | |
19852 | return 20; | |
19853 | } | |
19854 | unsigned long CPUFUNC(op_b180_4)(uint32_t opcode) /* EOR */ | |
19855 | { | |
19856 | uint32_t srcreg = ((opcode >> 9) & 7); | |
19857 | uint32_t dstreg = opcode & 7; | |
19858 | OpcodeFamily = 3; CurrentInstrCycles = 8; | |
19859 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
19860 | { int32_t dst = m68k_dreg(regs, dstreg); | |
19861 | src ^= dst; | |
19862 | CLEAR_CZNV; | |
19863 | SET_ZFLG (((int32_t)(src)) == 0); | |
19864 | SET_NFLG (((int32_t)(src)) < 0); | |
19865 | m68k_dreg(regs, dstreg) = (src); | |
19866 | }}}m68k_incpc(2); | |
19867 | return 8; | |
19868 | } | |
19869 | unsigned long CPUFUNC(op_b188_4)(uint32_t opcode) /* CMPM */ | |
19870 | { | |
19871 | uint32_t srcreg = (opcode & 7); | |
19872 | uint32_t dstreg = (opcode >> 9) & 7; | |
19873 | OpcodeFamily = 26; CurrentInstrCycles = 20; | |
19874 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
19875 | { int32_t src = m68k_read_memory_32(srca); | |
19876 | m68k_areg(regs, srcreg) += 4; | |
19877 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
19878 | { int32_t dst = m68k_read_memory_32(dsta); | |
19879 | m68k_areg(regs, dstreg) += 4; | |
19880 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
19881 | { int flgs = ((int32_t)(src)) < 0; | |
19882 | int flgo = ((int32_t)(dst)) < 0; | |
19883 | int flgn = ((int32_t)(newv)) < 0; | |
19884 | SET_ZFLG (((int32_t)(newv)) == 0); | |
19885 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
19886 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
19887 | SET_NFLG (flgn != 0); | |
19888 | }}}}}}}}m68k_incpc(2); | |
19889 | return 20; | |
19890 | } | |
19891 | unsigned long CPUFUNC(op_b190_4)(uint32_t opcode) /* EOR */ | |
19892 | { | |
19893 | uint32_t srcreg = ((opcode >> 9) & 7); | |
19894 | uint32_t dstreg = opcode & 7; | |
19895 | OpcodeFamily = 3; CurrentInstrCycles = 20; | |
19896 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
19897 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
19898 | { int32_t dst = m68k_read_memory_32(dsta); | |
19899 | src ^= dst; | |
19900 | CLEAR_CZNV; | |
19901 | SET_ZFLG (((int32_t)(src)) == 0); | |
19902 | SET_NFLG (((int32_t)(src)) < 0); | |
19903 | m68k_write_memory_32(dsta,src); | |
19904 | }}}}m68k_incpc(2); | |
19905 | return 20; | |
19906 | } | |
19907 | unsigned long CPUFUNC(op_b198_4)(uint32_t opcode) /* EOR */ | |
19908 | { | |
19909 | uint32_t srcreg = ((opcode >> 9) & 7); | |
19910 | uint32_t dstreg = opcode & 7; | |
19911 | OpcodeFamily = 3; CurrentInstrCycles = 20; | |
19912 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
19913 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
19914 | { int32_t dst = m68k_read_memory_32(dsta); | |
19915 | m68k_areg(regs, dstreg) += 4; | |
19916 | src ^= dst; | |
19917 | CLEAR_CZNV; | |
19918 | SET_ZFLG (((int32_t)(src)) == 0); | |
19919 | SET_NFLG (((int32_t)(src)) < 0); | |
19920 | m68k_write_memory_32(dsta,src); | |
19921 | }}}}m68k_incpc(2); | |
19922 | return 20; | |
19923 | } | |
19924 | unsigned long CPUFUNC(op_b1a0_4)(uint32_t opcode) /* EOR */ | |
19925 | { | |
19926 | uint32_t srcreg = ((opcode >> 9) & 7); | |
19927 | uint32_t dstreg = opcode & 7; | |
19928 | OpcodeFamily = 3; CurrentInstrCycles = 22; | |
19929 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
19930 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
19931 | { int32_t dst = m68k_read_memory_32(dsta); | |
19932 | m68k_areg (regs, dstreg) = dsta; | |
19933 | src ^= dst; | |
19934 | CLEAR_CZNV; | |
19935 | SET_ZFLG (((int32_t)(src)) == 0); | |
19936 | SET_NFLG (((int32_t)(src)) < 0); | |
19937 | m68k_write_memory_32(dsta,src); | |
19938 | }}}}m68k_incpc(2); | |
19939 | return 22; | |
19940 | } | |
19941 | unsigned long CPUFUNC(op_b1a8_4)(uint32_t opcode) /* EOR */ | |
19942 | { | |
19943 | uint32_t srcreg = ((opcode >> 9) & 7); | |
19944 | uint32_t dstreg = opcode & 7; | |
19945 | OpcodeFamily = 3; CurrentInstrCycles = 24; | |
19946 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
19947 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); | |
19948 | { int32_t dst = m68k_read_memory_32(dsta); | |
19949 | src ^= dst; | |
19950 | CLEAR_CZNV; | |
19951 | SET_ZFLG (((int32_t)(src)) == 0); | |
19952 | SET_NFLG (((int32_t)(src)) < 0); | |
19953 | m68k_write_memory_32(dsta,src); | |
19954 | }}}}m68k_incpc(4); | |
19955 | return 24; | |
19956 | } | |
19957 | unsigned long CPUFUNC(op_b1b0_4)(uint32_t opcode) /* EOR */ | |
19958 | { | |
19959 | uint32_t srcreg = ((opcode >> 9) & 7); | |
19960 | uint32_t dstreg = opcode & 7; | |
19961 | OpcodeFamily = 3; CurrentInstrCycles = 26; | |
19962 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
19963 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); | |
19964 | BusCyclePenalty += 2; | |
19965 | { int32_t dst = m68k_read_memory_32(dsta); | |
19966 | src ^= dst; | |
19967 | CLEAR_CZNV; | |
19968 | SET_ZFLG (((int32_t)(src)) == 0); | |
19969 | SET_NFLG (((int32_t)(src)) < 0); | |
19970 | m68k_write_memory_32(dsta,src); | |
19971 | }}}}m68k_incpc(4); | |
19972 | return 26; | |
19973 | } | |
19974 | unsigned long CPUFUNC(op_b1b8_4)(uint32_t opcode) /* EOR */ | |
19975 | { | |
19976 | uint32_t srcreg = ((opcode >> 9) & 7); | |
19977 | OpcodeFamily = 3; CurrentInstrCycles = 24; | |
19978 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
19979 | { uint32_t dsta = (int32_t)(int16_t)get_iword(2); | |
19980 | { int32_t dst = m68k_read_memory_32(dsta); | |
19981 | src ^= dst; | |
19982 | CLEAR_CZNV; | |
19983 | SET_ZFLG (((int32_t)(src)) == 0); | |
19984 | SET_NFLG (((int32_t)(src)) < 0); | |
19985 | m68k_write_memory_32(dsta,src); | |
19986 | }}}}m68k_incpc(4); | |
19987 | return 24; | |
19988 | } | |
19989 | unsigned long CPUFUNC(op_b1b9_4)(uint32_t opcode) /* EOR */ | |
19990 | { | |
19991 | uint32_t srcreg = ((opcode >> 9) & 7); | |
19992 | OpcodeFamily = 3; CurrentInstrCycles = 28; | |
19993 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
19994 | { uint32_t dsta = get_ilong(2); | |
19995 | { int32_t dst = m68k_read_memory_32(dsta); | |
19996 | src ^= dst; | |
19997 | CLEAR_CZNV; | |
19998 | SET_ZFLG (((int32_t)(src)) == 0); | |
19999 | SET_NFLG (((int32_t)(src)) < 0); | |
20000 | m68k_write_memory_32(dsta,src); | |
20001 | }}}}m68k_incpc(6); | |
20002 | return 28; | |
20003 | } | |
20004 | unsigned long CPUFUNC(op_b1c0_4)(uint32_t opcode) /* CMPA */ | |
20005 | { | |
20006 | uint32_t srcreg = (opcode & 7); | |
20007 | uint32_t dstreg = (opcode >> 9) & 7; | |
20008 | OpcodeFamily = 27; CurrentInstrCycles = 6; | |
20009 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
20010 | { int32_t dst = m68k_areg(regs, dstreg); | |
20011 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
20012 | { int flgs = ((int32_t)(src)) < 0; | |
20013 | int flgo = ((int32_t)(dst)) < 0; | |
20014 | int flgn = ((int32_t)(newv)) < 0; | |
20015 | SET_ZFLG (((int32_t)(newv)) == 0); | |
20016 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
20017 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
20018 | SET_NFLG (flgn != 0); | |
20019 | }}}}}}m68k_incpc(2); | |
20020 | return 6; | |
20021 | } | |
20022 | unsigned long CPUFUNC(op_b1c8_4)(uint32_t opcode) /* CMPA */ | |
20023 | { | |
20024 | uint32_t srcreg = (opcode & 7); | |
20025 | uint32_t dstreg = (opcode >> 9) & 7; | |
20026 | OpcodeFamily = 27; CurrentInstrCycles = 6; | |
20027 | {{ int32_t src = m68k_areg(regs, srcreg); | |
20028 | { int32_t dst = m68k_areg(regs, dstreg); | |
20029 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
20030 | { int flgs = ((int32_t)(src)) < 0; | |
20031 | int flgo = ((int32_t)(dst)) < 0; | |
20032 | int flgn = ((int32_t)(newv)) < 0; | |
20033 | SET_ZFLG (((int32_t)(newv)) == 0); | |
20034 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
20035 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
20036 | SET_NFLG (flgn != 0); | |
20037 | }}}}}}m68k_incpc(2); | |
20038 | return 6; | |
20039 | } | |
20040 | unsigned long CPUFUNC(op_b1d0_4)(uint32_t opcode) /* CMPA */ | |
20041 | { | |
20042 | uint32_t srcreg = (opcode & 7); | |
20043 | uint32_t dstreg = (opcode >> 9) & 7; | |
20044 | OpcodeFamily = 27; CurrentInstrCycles = 14; | |
20045 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
20046 | { int32_t src = m68k_read_memory_32(srca); | |
20047 | { int32_t dst = m68k_areg(regs, dstreg); | |
20048 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
20049 | { int flgs = ((int32_t)(src)) < 0; | |
20050 | int flgo = ((int32_t)(dst)) < 0; | |
20051 | int flgn = ((int32_t)(newv)) < 0; | |
20052 | SET_ZFLG (((int32_t)(newv)) == 0); | |
20053 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
20054 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
20055 | SET_NFLG (flgn != 0); | |
20056 | }}}}}}}m68k_incpc(2); | |
20057 | return 14; | |
20058 | } | |
20059 | unsigned long CPUFUNC(op_b1d8_4)(uint32_t opcode) /* CMPA */ | |
20060 | { | |
20061 | uint32_t srcreg = (opcode & 7); | |
20062 | uint32_t dstreg = (opcode >> 9) & 7; | |
20063 | OpcodeFamily = 27; CurrentInstrCycles = 14; | |
20064 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
20065 | { int32_t src = m68k_read_memory_32(srca); | |
20066 | m68k_areg(regs, srcreg) += 4; | |
20067 | { int32_t dst = m68k_areg(regs, dstreg); | |
20068 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
20069 | { int flgs = ((int32_t)(src)) < 0; | |
20070 | int flgo = ((int32_t)(dst)) < 0; | |
20071 | int flgn = ((int32_t)(newv)) < 0; | |
20072 | SET_ZFLG (((int32_t)(newv)) == 0); | |
20073 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
20074 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
20075 | SET_NFLG (flgn != 0); | |
20076 | }}}}}}}m68k_incpc(2); | |
20077 | return 14; | |
20078 | } | |
20079 | unsigned long CPUFUNC(op_b1e0_4)(uint32_t opcode) /* CMPA */ | |
20080 | { | |
20081 | uint32_t srcreg = (opcode & 7); | |
20082 | uint32_t dstreg = (opcode >> 9) & 7; | |
20083 | OpcodeFamily = 27; CurrentInstrCycles = 16; | |
20084 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 4; | |
20085 | { int32_t src = m68k_read_memory_32(srca); | |
20086 | m68k_areg (regs, srcreg) = srca; | |
20087 | { int32_t dst = m68k_areg(regs, dstreg); | |
20088 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
20089 | { int flgs = ((int32_t)(src)) < 0; | |
20090 | int flgo = ((int32_t)(dst)) < 0; | |
20091 | int flgn = ((int32_t)(newv)) < 0; | |
20092 | SET_ZFLG (((int32_t)(newv)) == 0); | |
20093 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
20094 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
20095 | SET_NFLG (flgn != 0); | |
20096 | }}}}}}}m68k_incpc(2); | |
20097 | return 16; | |
20098 | } | |
20099 | unsigned long CPUFUNC(op_b1e8_4)(uint32_t opcode) /* CMPA */ | |
20100 | { | |
20101 | uint32_t srcreg = (opcode & 7); | |
20102 | uint32_t dstreg = (opcode >> 9) & 7; | |
20103 | OpcodeFamily = 27; CurrentInstrCycles = 18; | |
20104 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
20105 | { int32_t src = m68k_read_memory_32(srca); | |
20106 | { int32_t dst = m68k_areg(regs, dstreg); | |
20107 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
20108 | { int flgs = ((int32_t)(src)) < 0; | |
20109 | int flgo = ((int32_t)(dst)) < 0; | |
20110 | int flgn = ((int32_t)(newv)) < 0; | |
20111 | SET_ZFLG (((int32_t)(newv)) == 0); | |
20112 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
20113 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
20114 | SET_NFLG (flgn != 0); | |
20115 | }}}}}}}m68k_incpc(4); | |
20116 | return 18; | |
20117 | } | |
20118 | unsigned long CPUFUNC(op_b1f0_4)(uint32_t opcode) /* CMPA */ | |
20119 | { | |
20120 | uint32_t srcreg = (opcode & 7); | |
20121 | uint32_t dstreg = (opcode >> 9) & 7; | |
20122 | OpcodeFamily = 27; CurrentInstrCycles = 20; | |
20123 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
20124 | BusCyclePenalty += 2; | |
20125 | { int32_t src = m68k_read_memory_32(srca); | |
20126 | { int32_t dst = m68k_areg(regs, dstreg); | |
20127 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
20128 | { int flgs = ((int32_t)(src)) < 0; | |
20129 | int flgo = ((int32_t)(dst)) < 0; | |
20130 | int flgn = ((int32_t)(newv)) < 0; | |
20131 | SET_ZFLG (((int32_t)(newv)) == 0); | |
20132 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
20133 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
20134 | SET_NFLG (flgn != 0); | |
20135 | }}}}}}}m68k_incpc(4); | |
20136 | return 20; | |
20137 | } | |
20138 | unsigned long CPUFUNC(op_b1f8_4)(uint32_t opcode) /* CMPA */ | |
20139 | { | |
20140 | uint32_t dstreg = (opcode >> 9) & 7; | |
20141 | OpcodeFamily = 27; CurrentInstrCycles = 18; | |
20142 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
20143 | { int32_t src = m68k_read_memory_32(srca); | |
20144 | { int32_t dst = m68k_areg(regs, dstreg); | |
20145 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
20146 | { int flgs = ((int32_t)(src)) < 0; | |
20147 | int flgo = ((int32_t)(dst)) < 0; | |
20148 | int flgn = ((int32_t)(newv)) < 0; | |
20149 | SET_ZFLG (((int32_t)(newv)) == 0); | |
20150 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
20151 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
20152 | SET_NFLG (flgn != 0); | |
20153 | }}}}}}}m68k_incpc(4); | |
20154 | return 18; | |
20155 | } | |
20156 | unsigned long CPUFUNC(op_b1f9_4)(uint32_t opcode) /* CMPA */ | |
20157 | { | |
20158 | uint32_t dstreg = (opcode >> 9) & 7; | |
20159 | OpcodeFamily = 27; CurrentInstrCycles = 22; | |
20160 | {{ uint32_t srca = get_ilong(2); | |
20161 | { int32_t src = m68k_read_memory_32(srca); | |
20162 | { int32_t dst = m68k_areg(regs, dstreg); | |
20163 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
20164 | { int flgs = ((int32_t)(src)) < 0; | |
20165 | int flgo = ((int32_t)(dst)) < 0; | |
20166 | int flgn = ((int32_t)(newv)) < 0; | |
20167 | SET_ZFLG (((int32_t)(newv)) == 0); | |
20168 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
20169 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
20170 | SET_NFLG (flgn != 0); | |
20171 | }}}}}}}m68k_incpc(6); | |
20172 | return 22; | |
20173 | } | |
20174 | unsigned long CPUFUNC(op_b1fa_4)(uint32_t opcode) /* CMPA */ | |
20175 | { | |
20176 | uint32_t dstreg = (opcode >> 9) & 7; | |
20177 | OpcodeFamily = 27; CurrentInstrCycles = 18; | |
20178 | {{ uint32_t srca = m68k_getpc () + 2; | |
20179 | srca += (int32_t)(int16_t)get_iword(2); | |
20180 | { int32_t src = m68k_read_memory_32(srca); | |
20181 | { int32_t dst = m68k_areg(regs, dstreg); | |
20182 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
20183 | { int flgs = ((int32_t)(src)) < 0; | |
20184 | int flgo = ((int32_t)(dst)) < 0; | |
20185 | int flgn = ((int32_t)(newv)) < 0; | |
20186 | SET_ZFLG (((int32_t)(newv)) == 0); | |
20187 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
20188 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
20189 | SET_NFLG (flgn != 0); | |
20190 | }}}}}}}m68k_incpc(4); | |
20191 | return 18; | |
20192 | } | |
20193 | unsigned long CPUFUNC(op_b1fb_4)(uint32_t opcode) /* CMPA */ | |
20194 | { | |
20195 | uint32_t dstreg = (opcode >> 9) & 7; | |
20196 | OpcodeFamily = 27; CurrentInstrCycles = 20; | |
20197 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
20198 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
20199 | BusCyclePenalty += 2; | |
20200 | { int32_t src = m68k_read_memory_32(srca); | |
20201 | { int32_t dst = m68k_areg(regs, dstreg); | |
20202 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
20203 | { int flgs = ((int32_t)(src)) < 0; | |
20204 | int flgo = ((int32_t)(dst)) < 0; | |
20205 | int flgn = ((int32_t)(newv)) < 0; | |
20206 | SET_ZFLG (((int32_t)(newv)) == 0); | |
20207 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
20208 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
20209 | SET_NFLG (flgn != 0); | |
20210 | }}}}}}}m68k_incpc(4); | |
20211 | return 20; | |
20212 | } | |
20213 | unsigned long CPUFUNC(op_b1fc_4)(uint32_t opcode) /* CMPA */ | |
20214 | { | |
20215 | uint32_t dstreg = (opcode >> 9) & 7; | |
20216 | OpcodeFamily = 27; CurrentInstrCycles = 14; | |
20217 | {{ int32_t src = get_ilong(2); | |
20218 | { int32_t dst = m68k_areg(regs, dstreg); | |
20219 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
20220 | { int flgs = ((int32_t)(src)) < 0; | |
20221 | int flgo = ((int32_t)(dst)) < 0; | |
20222 | int flgn = ((int32_t)(newv)) < 0; | |
20223 | SET_ZFLG (((int32_t)(newv)) == 0); | |
20224 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
20225 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
20226 | SET_NFLG (flgn != 0); | |
20227 | }}}}}}m68k_incpc(6); | |
20228 | return 14; | |
20229 | } | |
20230 | unsigned long CPUFUNC(op_c000_4)(uint32_t opcode) /* AND */ | |
20231 | { | |
20232 | uint32_t srcreg = (opcode & 7); | |
20233 | uint32_t dstreg = (opcode >> 9) & 7; | |
20234 | OpcodeFamily = 2; CurrentInstrCycles = 4; | |
20235 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
20236 | { int8_t dst = m68k_dreg(regs, dstreg); | |
20237 | src &= dst; | |
20238 | CLEAR_CZNV; | |
20239 | SET_ZFLG (((int8_t)(src)) == 0); | |
20240 | SET_NFLG (((int8_t)(src)) < 0); | |
20241 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
20242 | }}}m68k_incpc(2); | |
20243 | return 4; | |
20244 | } | |
20245 | unsigned long CPUFUNC(op_c010_4)(uint32_t opcode) /* AND */ | |
20246 | { | |
20247 | uint32_t srcreg = (opcode & 7); | |
20248 | uint32_t dstreg = (opcode >> 9) & 7; | |
20249 | OpcodeFamily = 2; CurrentInstrCycles = 8; | |
20250 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
20251 | { int8_t src = m68k_read_memory_8(srca); | |
20252 | { int8_t dst = m68k_dreg(regs, dstreg); | |
20253 | src &= dst; | |
20254 | CLEAR_CZNV; | |
20255 | SET_ZFLG (((int8_t)(src)) == 0); | |
20256 | SET_NFLG (((int8_t)(src)) < 0); | |
20257 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
20258 | }}}}m68k_incpc(2); | |
20259 | return 8; | |
20260 | } | |
20261 | unsigned long CPUFUNC(op_c018_4)(uint32_t opcode) /* AND */ | |
20262 | { | |
20263 | uint32_t srcreg = (opcode & 7); | |
20264 | uint32_t dstreg = (opcode >> 9) & 7; | |
20265 | OpcodeFamily = 2; CurrentInstrCycles = 8; | |
20266 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
20267 | { int8_t src = m68k_read_memory_8(srca); | |
20268 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
20269 | { int8_t dst = m68k_dreg(regs, dstreg); | |
20270 | src &= dst; | |
20271 | CLEAR_CZNV; | |
20272 | SET_ZFLG (((int8_t)(src)) == 0); | |
20273 | SET_NFLG (((int8_t)(src)) < 0); | |
20274 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
20275 | }}}}m68k_incpc(2); | |
20276 | return 8; | |
20277 | } | |
20278 | unsigned long CPUFUNC(op_c020_4)(uint32_t opcode) /* AND */ | |
20279 | { | |
20280 | uint32_t srcreg = (opcode & 7); | |
20281 | uint32_t dstreg = (opcode >> 9) & 7; | |
20282 | OpcodeFamily = 2; CurrentInstrCycles = 10; | |
20283 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
20284 | { int8_t src = m68k_read_memory_8(srca); | |
20285 | m68k_areg (regs, srcreg) = srca; | |
20286 | { int8_t dst = m68k_dreg(regs, dstreg); | |
20287 | src &= dst; | |
20288 | CLEAR_CZNV; | |
20289 | SET_ZFLG (((int8_t)(src)) == 0); | |
20290 | SET_NFLG (((int8_t)(src)) < 0); | |
20291 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
20292 | }}}}m68k_incpc(2); | |
20293 | return 10; | |
20294 | } | |
20295 | unsigned long CPUFUNC(op_c028_4)(uint32_t opcode) /* AND */ | |
20296 | { | |
20297 | uint32_t srcreg = (opcode & 7); | |
20298 | uint32_t dstreg = (opcode >> 9) & 7; | |
20299 | OpcodeFamily = 2; CurrentInstrCycles = 12; | |
20300 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
20301 | { int8_t src = m68k_read_memory_8(srca); | |
20302 | { int8_t dst = m68k_dreg(regs, dstreg); | |
20303 | src &= dst; | |
20304 | CLEAR_CZNV; | |
20305 | SET_ZFLG (((int8_t)(src)) == 0); | |
20306 | SET_NFLG (((int8_t)(src)) < 0); | |
20307 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
20308 | }}}}m68k_incpc(4); | |
20309 | return 12; | |
20310 | } | |
20311 | unsigned long CPUFUNC(op_c030_4)(uint32_t opcode) /* AND */ | |
20312 | { | |
20313 | uint32_t srcreg = (opcode & 7); | |
20314 | uint32_t dstreg = (opcode >> 9) & 7; | |
20315 | OpcodeFamily = 2; CurrentInstrCycles = 14; | |
20316 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
20317 | BusCyclePenalty += 2; | |
20318 | { int8_t src = m68k_read_memory_8(srca); | |
20319 | { int8_t dst = m68k_dreg(regs, dstreg); | |
20320 | src &= dst; | |
20321 | CLEAR_CZNV; | |
20322 | SET_ZFLG (((int8_t)(src)) == 0); | |
20323 | SET_NFLG (((int8_t)(src)) < 0); | |
20324 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
20325 | }}}}m68k_incpc(4); | |
20326 | return 14; | |
20327 | } | |
20328 | unsigned long CPUFUNC(op_c038_4)(uint32_t opcode) /* AND */ | |
20329 | { | |
20330 | uint32_t dstreg = (opcode >> 9) & 7; | |
20331 | OpcodeFamily = 2; CurrentInstrCycles = 12; | |
20332 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
20333 | { int8_t src = m68k_read_memory_8(srca); | |
20334 | { int8_t dst = m68k_dreg(regs, dstreg); | |
20335 | src &= dst; | |
20336 | CLEAR_CZNV; | |
20337 | SET_ZFLG (((int8_t)(src)) == 0); | |
20338 | SET_NFLG (((int8_t)(src)) < 0); | |
20339 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
20340 | }}}}m68k_incpc(4); | |
20341 | return 12; | |
20342 | } | |
20343 | unsigned long CPUFUNC(op_c039_4)(uint32_t opcode) /* AND */ | |
20344 | { | |
20345 | uint32_t dstreg = (opcode >> 9) & 7; | |
20346 | OpcodeFamily = 2; CurrentInstrCycles = 16; | |
20347 | {{ uint32_t srca = get_ilong(2); | |
20348 | { int8_t src = m68k_read_memory_8(srca); | |
20349 | { int8_t dst = m68k_dreg(regs, dstreg); | |
20350 | src &= dst; | |
20351 | CLEAR_CZNV; | |
20352 | SET_ZFLG (((int8_t)(src)) == 0); | |
20353 | SET_NFLG (((int8_t)(src)) < 0); | |
20354 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
20355 | }}}}m68k_incpc(6); | |
20356 | return 16; | |
20357 | } | |
20358 | unsigned long CPUFUNC(op_c03a_4)(uint32_t opcode) /* AND */ | |
20359 | { | |
20360 | uint32_t dstreg = (opcode >> 9) & 7; | |
20361 | OpcodeFamily = 2; CurrentInstrCycles = 12; | |
20362 | {{ uint32_t srca = m68k_getpc () + 2; | |
20363 | srca += (int32_t)(int16_t)get_iword(2); | |
20364 | { int8_t src = m68k_read_memory_8(srca); | |
20365 | { int8_t dst = m68k_dreg(regs, dstreg); | |
20366 | src &= dst; | |
20367 | CLEAR_CZNV; | |
20368 | SET_ZFLG (((int8_t)(src)) == 0); | |
20369 | SET_NFLG (((int8_t)(src)) < 0); | |
20370 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
20371 | }}}}m68k_incpc(4); | |
20372 | return 12; | |
20373 | } | |
20374 | unsigned long CPUFUNC(op_c03b_4)(uint32_t opcode) /* AND */ | |
20375 | { | |
20376 | uint32_t dstreg = (opcode >> 9) & 7; | |
20377 | OpcodeFamily = 2; CurrentInstrCycles = 14; | |
20378 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
20379 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
20380 | BusCyclePenalty += 2; | |
20381 | { int8_t src = m68k_read_memory_8(srca); | |
20382 | { int8_t dst = m68k_dreg(regs, dstreg); | |
20383 | src &= dst; | |
20384 | CLEAR_CZNV; | |
20385 | SET_ZFLG (((int8_t)(src)) == 0); | |
20386 | SET_NFLG (((int8_t)(src)) < 0); | |
20387 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
20388 | }}}}m68k_incpc(4); | |
20389 | return 14; | |
20390 | } | |
20391 | unsigned long CPUFUNC(op_c03c_4)(uint32_t opcode) /* AND */ | |
20392 | { | |
20393 | uint32_t dstreg = (opcode >> 9) & 7; | |
20394 | OpcodeFamily = 2; CurrentInstrCycles = 8; | |
20395 | {{ int8_t src = get_ibyte(2); | |
20396 | { int8_t dst = m68k_dreg(regs, dstreg); | |
20397 | src &= dst; | |
20398 | CLEAR_CZNV; | |
20399 | SET_ZFLG (((int8_t)(src)) == 0); | |
20400 | SET_NFLG (((int8_t)(src)) < 0); | |
20401 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
20402 | }}}m68k_incpc(4); | |
20403 | return 8; | |
20404 | } | |
20405 | unsigned long CPUFUNC(op_c040_4)(uint32_t opcode) /* AND */ | |
20406 | { | |
20407 | uint32_t srcreg = (opcode & 7); | |
20408 | uint32_t dstreg = (opcode >> 9) & 7; | |
20409 | OpcodeFamily = 2; CurrentInstrCycles = 4; | |
20410 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
20411 | { int16_t dst = m68k_dreg(regs, dstreg); | |
20412 | src &= dst; | |
20413 | CLEAR_CZNV; | |
20414 | SET_ZFLG (((int16_t)(src)) == 0); | |
20415 | SET_NFLG (((int16_t)(src)) < 0); | |
20416 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
20417 | }}}m68k_incpc(2); | |
20418 | return 4; | |
20419 | } | |
20420 | unsigned long CPUFUNC(op_c050_4)(uint32_t opcode) /* AND */ | |
20421 | { | |
20422 | uint32_t srcreg = (opcode & 7); | |
20423 | uint32_t dstreg = (opcode >> 9) & 7; | |
20424 | OpcodeFamily = 2; CurrentInstrCycles = 8; | |
20425 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
20426 | { int16_t src = m68k_read_memory_16(srca); | |
20427 | { int16_t dst = m68k_dreg(regs, dstreg); | |
20428 | src &= dst; | |
20429 | CLEAR_CZNV; | |
20430 | SET_ZFLG (((int16_t)(src)) == 0); | |
20431 | SET_NFLG (((int16_t)(src)) < 0); | |
20432 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
20433 | }}}}m68k_incpc(2); | |
20434 | return 8; | |
20435 | } | |
20436 | unsigned long CPUFUNC(op_c058_4)(uint32_t opcode) /* AND */ | |
20437 | { | |
20438 | uint32_t srcreg = (opcode & 7); | |
20439 | uint32_t dstreg = (opcode >> 9) & 7; | |
20440 | OpcodeFamily = 2; CurrentInstrCycles = 8; | |
20441 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
20442 | { int16_t src = m68k_read_memory_16(srca); | |
20443 | m68k_areg(regs, srcreg) += 2; | |
20444 | { int16_t dst = m68k_dreg(regs, dstreg); | |
20445 | src &= dst; | |
20446 | CLEAR_CZNV; | |
20447 | SET_ZFLG (((int16_t)(src)) == 0); | |
20448 | SET_NFLG (((int16_t)(src)) < 0); | |
20449 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
20450 | }}}}m68k_incpc(2); | |
20451 | return 8; | |
20452 | } | |
20453 | unsigned long CPUFUNC(op_c060_4)(uint32_t opcode) /* AND */ | |
20454 | { | |
20455 | uint32_t srcreg = (opcode & 7); | |
20456 | uint32_t dstreg = (opcode >> 9) & 7; | |
20457 | OpcodeFamily = 2; CurrentInstrCycles = 10; | |
20458 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
20459 | { int16_t src = m68k_read_memory_16(srca); | |
20460 | m68k_areg (regs, srcreg) = srca; | |
20461 | { int16_t dst = m68k_dreg(regs, dstreg); | |
20462 | src &= dst; | |
20463 | CLEAR_CZNV; | |
20464 | SET_ZFLG (((int16_t)(src)) == 0); | |
20465 | SET_NFLG (((int16_t)(src)) < 0); | |
20466 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
20467 | }}}}m68k_incpc(2); | |
20468 | return 10; | |
20469 | } | |
20470 | unsigned long CPUFUNC(op_c068_4)(uint32_t opcode) /* AND */ | |
20471 | { | |
20472 | uint32_t srcreg = (opcode & 7); | |
20473 | uint32_t dstreg = (opcode >> 9) & 7; | |
20474 | OpcodeFamily = 2; CurrentInstrCycles = 12; | |
20475 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
20476 | { int16_t src = m68k_read_memory_16(srca); | |
20477 | { int16_t dst = m68k_dreg(regs, dstreg); | |
20478 | src &= dst; | |
20479 | CLEAR_CZNV; | |
20480 | SET_ZFLG (((int16_t)(src)) == 0); | |
20481 | SET_NFLG (((int16_t)(src)) < 0); | |
20482 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
20483 | }}}}m68k_incpc(4); | |
20484 | return 12; | |
20485 | } | |
20486 | unsigned long CPUFUNC(op_c070_4)(uint32_t opcode) /* AND */ | |
20487 | { | |
20488 | uint32_t srcreg = (opcode & 7); | |
20489 | uint32_t dstreg = (opcode >> 9) & 7; | |
20490 | OpcodeFamily = 2; CurrentInstrCycles = 14; | |
20491 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
20492 | BusCyclePenalty += 2; | |
20493 | { int16_t src = m68k_read_memory_16(srca); | |
20494 | { int16_t dst = m68k_dreg(regs, dstreg); | |
20495 | src &= dst; | |
20496 | CLEAR_CZNV; | |
20497 | SET_ZFLG (((int16_t)(src)) == 0); | |
20498 | SET_NFLG (((int16_t)(src)) < 0); | |
20499 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
20500 | }}}}m68k_incpc(4); | |
20501 | return 14; | |
20502 | } | |
20503 | unsigned long CPUFUNC(op_c078_4)(uint32_t opcode) /* AND */ | |
20504 | { | |
20505 | uint32_t dstreg = (opcode >> 9) & 7; | |
20506 | OpcodeFamily = 2; CurrentInstrCycles = 12; | |
20507 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
20508 | { int16_t src = m68k_read_memory_16(srca); | |
20509 | { int16_t dst = m68k_dreg(regs, dstreg); | |
20510 | src &= dst; | |
20511 | CLEAR_CZNV; | |
20512 | SET_ZFLG (((int16_t)(src)) == 0); | |
20513 | SET_NFLG (((int16_t)(src)) < 0); | |
20514 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
20515 | }}}}m68k_incpc(4); | |
20516 | return 12; | |
20517 | } | |
20518 | unsigned long CPUFUNC(op_c079_4)(uint32_t opcode) /* AND */ | |
20519 | { | |
20520 | uint32_t dstreg = (opcode >> 9) & 7; | |
20521 | OpcodeFamily = 2; CurrentInstrCycles = 16; | |
20522 | {{ uint32_t srca = get_ilong(2); | |
20523 | { int16_t src = m68k_read_memory_16(srca); | |
20524 | { int16_t dst = m68k_dreg(regs, dstreg); | |
20525 | src &= dst; | |
20526 | CLEAR_CZNV; | |
20527 | SET_ZFLG (((int16_t)(src)) == 0); | |
20528 | SET_NFLG (((int16_t)(src)) < 0); | |
20529 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
20530 | }}}}m68k_incpc(6); | |
20531 | return 16; | |
20532 | } | |
20533 | unsigned long CPUFUNC(op_c07a_4)(uint32_t opcode) /* AND */ | |
20534 | { | |
20535 | uint32_t dstreg = (opcode >> 9) & 7; | |
20536 | OpcodeFamily = 2; CurrentInstrCycles = 12; | |
20537 | {{ uint32_t srca = m68k_getpc () + 2; | |
20538 | srca += (int32_t)(int16_t)get_iword(2); | |
20539 | { int16_t src = m68k_read_memory_16(srca); | |
20540 | { int16_t dst = m68k_dreg(regs, dstreg); | |
20541 | src &= dst; | |
20542 | CLEAR_CZNV; | |
20543 | SET_ZFLG (((int16_t)(src)) == 0); | |
20544 | SET_NFLG (((int16_t)(src)) < 0); | |
20545 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
20546 | }}}}m68k_incpc(4); | |
20547 | return 12; | |
20548 | } | |
20549 | unsigned long CPUFUNC(op_c07b_4)(uint32_t opcode) /* AND */ | |
20550 | { | |
20551 | uint32_t dstreg = (opcode >> 9) & 7; | |
20552 | OpcodeFamily = 2; CurrentInstrCycles = 14; | |
20553 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
20554 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
20555 | BusCyclePenalty += 2; | |
20556 | { int16_t src = m68k_read_memory_16(srca); | |
20557 | { int16_t dst = m68k_dreg(regs, dstreg); | |
20558 | src &= dst; | |
20559 | CLEAR_CZNV; | |
20560 | SET_ZFLG (((int16_t)(src)) == 0); | |
20561 | SET_NFLG (((int16_t)(src)) < 0); | |
20562 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
20563 | }}}}m68k_incpc(4); | |
20564 | return 14; | |
20565 | } | |
20566 | unsigned long CPUFUNC(op_c07c_4)(uint32_t opcode) /* AND */ | |
20567 | { | |
20568 | uint32_t dstreg = (opcode >> 9) & 7; | |
20569 | OpcodeFamily = 2; CurrentInstrCycles = 8; | |
20570 | {{ int16_t src = get_iword(2); | |
20571 | { int16_t dst = m68k_dreg(regs, dstreg); | |
20572 | src &= dst; | |
20573 | CLEAR_CZNV; | |
20574 | SET_ZFLG (((int16_t)(src)) == 0); | |
20575 | SET_NFLG (((int16_t)(src)) < 0); | |
20576 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
20577 | }}}m68k_incpc(4); | |
20578 | return 8; | |
20579 | } | |
20580 | unsigned long CPUFUNC(op_c080_4)(uint32_t opcode) /* AND */ | |
20581 | { | |
20582 | uint32_t srcreg = (opcode & 7); | |
20583 | uint32_t dstreg = (opcode >> 9) & 7; | |
20584 | OpcodeFamily = 2; CurrentInstrCycles = 8; | |
20585 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
20586 | { int32_t dst = m68k_dreg(regs, dstreg); | |
20587 | src &= dst; | |
20588 | CLEAR_CZNV; | |
20589 | SET_ZFLG (((int32_t)(src)) == 0); | |
20590 | SET_NFLG (((int32_t)(src)) < 0); | |
20591 | m68k_dreg(regs, dstreg) = (src); | |
20592 | }}}m68k_incpc(2); | |
20593 | return 8; | |
20594 | } | |
20595 | unsigned long CPUFUNC(op_c090_4)(uint32_t opcode) /* AND */ | |
20596 | { | |
20597 | uint32_t srcreg = (opcode & 7); | |
20598 | uint32_t dstreg = (opcode >> 9) & 7; | |
20599 | OpcodeFamily = 2; CurrentInstrCycles = 14; | |
20600 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
20601 | { int32_t src = m68k_read_memory_32(srca); | |
20602 | { int32_t dst = m68k_dreg(regs, dstreg); | |
20603 | src &= dst; | |
20604 | CLEAR_CZNV; | |
20605 | SET_ZFLG (((int32_t)(src)) == 0); | |
20606 | SET_NFLG (((int32_t)(src)) < 0); | |
20607 | m68k_dreg(regs, dstreg) = (src); | |
20608 | }}}}m68k_incpc(2); | |
20609 | return 14; | |
20610 | } | |
20611 | unsigned long CPUFUNC(op_c098_4)(uint32_t opcode) /* AND */ | |
20612 | { | |
20613 | uint32_t srcreg = (opcode & 7); | |
20614 | uint32_t dstreg = (opcode >> 9) & 7; | |
20615 | OpcodeFamily = 2; CurrentInstrCycles = 14; | |
20616 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
20617 | { int32_t src = m68k_read_memory_32(srca); | |
20618 | m68k_areg(regs, srcreg) += 4; | |
20619 | { int32_t dst = m68k_dreg(regs, dstreg); | |
20620 | src &= dst; | |
20621 | CLEAR_CZNV; | |
20622 | SET_ZFLG (((int32_t)(src)) == 0); | |
20623 | SET_NFLG (((int32_t)(src)) < 0); | |
20624 | m68k_dreg(regs, dstreg) = (src); | |
20625 | }}}}m68k_incpc(2); | |
20626 | return 14; | |
20627 | } | |
20628 | unsigned long CPUFUNC(op_c0a0_4)(uint32_t opcode) /* AND */ | |
20629 | { | |
20630 | uint32_t srcreg = (opcode & 7); | |
20631 | uint32_t dstreg = (opcode >> 9) & 7; | |
20632 | OpcodeFamily = 2; CurrentInstrCycles = 16; | |
20633 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 4; | |
20634 | { int32_t src = m68k_read_memory_32(srca); | |
20635 | m68k_areg (regs, srcreg) = srca; | |
20636 | { int32_t dst = m68k_dreg(regs, dstreg); | |
20637 | src &= dst; | |
20638 | CLEAR_CZNV; | |
20639 | SET_ZFLG (((int32_t)(src)) == 0); | |
20640 | SET_NFLG (((int32_t)(src)) < 0); | |
20641 | m68k_dreg(regs, dstreg) = (src); | |
20642 | }}}}m68k_incpc(2); | |
20643 | return 16; | |
20644 | } | |
20645 | unsigned long CPUFUNC(op_c0a8_4)(uint32_t opcode) /* AND */ | |
20646 | { | |
20647 | uint32_t srcreg = (opcode & 7); | |
20648 | uint32_t dstreg = (opcode >> 9) & 7; | |
20649 | OpcodeFamily = 2; CurrentInstrCycles = 18; | |
20650 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
20651 | { int32_t src = m68k_read_memory_32(srca); | |
20652 | { int32_t dst = m68k_dreg(regs, dstreg); | |
20653 | src &= dst; | |
20654 | CLEAR_CZNV; | |
20655 | SET_ZFLG (((int32_t)(src)) == 0); | |
20656 | SET_NFLG (((int32_t)(src)) < 0); | |
20657 | m68k_dreg(regs, dstreg) = (src); | |
20658 | }}}}m68k_incpc(4); | |
20659 | return 18; | |
20660 | } | |
20661 | unsigned long CPUFUNC(op_c0b0_4)(uint32_t opcode) /* AND */ | |
20662 | { | |
20663 | uint32_t srcreg = (opcode & 7); | |
20664 | uint32_t dstreg = (opcode >> 9) & 7; | |
20665 | OpcodeFamily = 2; CurrentInstrCycles = 20; | |
20666 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
20667 | BusCyclePenalty += 2; | |
20668 | { int32_t src = m68k_read_memory_32(srca); | |
20669 | { int32_t dst = m68k_dreg(regs, dstreg); | |
20670 | src &= dst; | |
20671 | CLEAR_CZNV; | |
20672 | SET_ZFLG (((int32_t)(src)) == 0); | |
20673 | SET_NFLG (((int32_t)(src)) < 0); | |
20674 | m68k_dreg(regs, dstreg) = (src); | |
20675 | }}}}m68k_incpc(4); | |
20676 | return 20; | |
20677 | } | |
20678 | unsigned long CPUFUNC(op_c0b8_4)(uint32_t opcode) /* AND */ | |
20679 | { | |
20680 | uint32_t dstreg = (opcode >> 9) & 7; | |
20681 | OpcodeFamily = 2; CurrentInstrCycles = 18; | |
20682 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
20683 | { int32_t src = m68k_read_memory_32(srca); | |
20684 | { int32_t dst = m68k_dreg(regs, dstreg); | |
20685 | src &= dst; | |
20686 | CLEAR_CZNV; | |
20687 | SET_ZFLG (((int32_t)(src)) == 0); | |
20688 | SET_NFLG (((int32_t)(src)) < 0); | |
20689 | m68k_dreg(regs, dstreg) = (src); | |
20690 | }}}}m68k_incpc(4); | |
20691 | return 18; | |
20692 | } | |
20693 | unsigned long CPUFUNC(op_c0b9_4)(uint32_t opcode) /* AND */ | |
20694 | { | |
20695 | uint32_t dstreg = (opcode >> 9) & 7; | |
20696 | OpcodeFamily = 2; CurrentInstrCycles = 22; | |
20697 | {{ uint32_t srca = get_ilong(2); | |
20698 | { int32_t src = m68k_read_memory_32(srca); | |
20699 | { int32_t dst = m68k_dreg(regs, dstreg); | |
20700 | src &= dst; | |
20701 | CLEAR_CZNV; | |
20702 | SET_ZFLG (((int32_t)(src)) == 0); | |
20703 | SET_NFLG (((int32_t)(src)) < 0); | |
20704 | m68k_dreg(regs, dstreg) = (src); | |
20705 | }}}}m68k_incpc(6); | |
20706 | return 22; | |
20707 | } | |
20708 | unsigned long CPUFUNC(op_c0ba_4)(uint32_t opcode) /* AND */ | |
20709 | { | |
20710 | uint32_t dstreg = (opcode >> 9) & 7; | |
20711 | OpcodeFamily = 2; CurrentInstrCycles = 18; | |
20712 | {{ uint32_t srca = m68k_getpc () + 2; | |
20713 | srca += (int32_t)(int16_t)get_iword(2); | |
20714 | { int32_t src = m68k_read_memory_32(srca); | |
20715 | { int32_t dst = m68k_dreg(regs, dstreg); | |
20716 | src &= dst; | |
20717 | CLEAR_CZNV; | |
20718 | SET_ZFLG (((int32_t)(src)) == 0); | |
20719 | SET_NFLG (((int32_t)(src)) < 0); | |
20720 | m68k_dreg(regs, dstreg) = (src); | |
20721 | }}}}m68k_incpc(4); | |
20722 | return 18; | |
20723 | } | |
20724 | unsigned long CPUFUNC(op_c0bb_4)(uint32_t opcode) /* AND */ | |
20725 | { | |
20726 | uint32_t dstreg = (opcode >> 9) & 7; | |
20727 | OpcodeFamily = 2; CurrentInstrCycles = 20; | |
20728 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
20729 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
20730 | BusCyclePenalty += 2; | |
20731 | { int32_t src = m68k_read_memory_32(srca); | |
20732 | { int32_t dst = m68k_dreg(regs, dstreg); | |
20733 | src &= dst; | |
20734 | CLEAR_CZNV; | |
20735 | SET_ZFLG (((int32_t)(src)) == 0); | |
20736 | SET_NFLG (((int32_t)(src)) < 0); | |
20737 | m68k_dreg(regs, dstreg) = (src); | |
20738 | }}}}m68k_incpc(4); | |
20739 | return 20; | |
20740 | } | |
20741 | unsigned long CPUFUNC(op_c0bc_4)(uint32_t opcode) /* AND */ | |
20742 | { | |
20743 | uint32_t dstreg = (opcode >> 9) & 7; | |
20744 | OpcodeFamily = 2; CurrentInstrCycles = 16; | |
20745 | {{ int32_t src = get_ilong(2); | |
20746 | { int32_t dst = m68k_dreg(regs, dstreg); | |
20747 | src &= dst; | |
20748 | CLEAR_CZNV; | |
20749 | SET_ZFLG (((int32_t)(src)) == 0); | |
20750 | SET_NFLG (((int32_t)(src)) < 0); | |
20751 | m68k_dreg(regs, dstreg) = (src); | |
20752 | }}}m68k_incpc(6); | |
20753 | return 16; | |
20754 | } | |
20755 | unsigned long CPUFUNC(op_c0c0_4)(uint32_t opcode) /* MULU */ | |
20756 | { | |
20757 | uint32_t srcreg = (opcode & 7); | |
20758 | uint32_t dstreg = (opcode >> 9) & 7; | |
20759 | unsigned int retcycles = 0; | |
20760 | OpcodeFamily = 62; CurrentInstrCycles = 38; | |
20761 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
20762 | { int16_t dst = m68k_dreg(regs, dstreg); | |
20763 | { uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src; | |
20764 | CLEAR_CZNV; | |
20765 | SET_ZFLG (((int32_t)(newv)) == 0); | |
20766 | SET_NFLG (((int32_t)(newv)) < 0); | |
20767 | m68k_dreg(regs, dstreg) = (newv); | |
20768 | while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; } | |
20769 | }}}}m68k_incpc(2); | |
20770 | return (38+retcycles*2); | |
20771 | } | |
20772 | unsigned long CPUFUNC(op_c0d0_4)(uint32_t opcode) /* MULU */ | |
20773 | { | |
20774 | uint32_t srcreg = (opcode & 7); | |
20775 | uint32_t dstreg = (opcode >> 9) & 7; | |
20776 | unsigned int retcycles = 0; | |
20777 | OpcodeFamily = 62; CurrentInstrCycles = 42; | |
20778 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
20779 | { int16_t src = m68k_read_memory_16(srca); | |
20780 | { int16_t dst = m68k_dreg(regs, dstreg); | |
20781 | { uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src; | |
20782 | CLEAR_CZNV; | |
20783 | SET_ZFLG (((int32_t)(newv)) == 0); | |
20784 | SET_NFLG (((int32_t)(newv)) < 0); | |
20785 | m68k_dreg(regs, dstreg) = (newv); | |
20786 | while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; } | |
20787 | }}}}}m68k_incpc(2); | |
20788 | return (42+retcycles*2); | |
20789 | } | |
20790 | unsigned long CPUFUNC(op_c0d8_4)(uint32_t opcode) /* MULU */ | |
20791 | { | |
20792 | uint32_t srcreg = (opcode & 7); | |
20793 | uint32_t dstreg = (opcode >> 9) & 7; | |
20794 | unsigned int retcycles = 0; | |
20795 | OpcodeFamily = 62; CurrentInstrCycles = 42; | |
20796 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
20797 | { int16_t src = m68k_read_memory_16(srca); | |
20798 | m68k_areg(regs, srcreg) += 2; | |
20799 | { int16_t dst = m68k_dreg(regs, dstreg); | |
20800 | { uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src; | |
20801 | CLEAR_CZNV; | |
20802 | SET_ZFLG (((int32_t)(newv)) == 0); | |
20803 | SET_NFLG (((int32_t)(newv)) < 0); | |
20804 | m68k_dreg(regs, dstreg) = (newv); | |
20805 | while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; } | |
20806 | }}}}}m68k_incpc(2); | |
20807 | return (42+retcycles*2); | |
20808 | } | |
20809 | unsigned long CPUFUNC(op_c0e0_4)(uint32_t opcode) /* MULU */ | |
20810 | { | |
20811 | uint32_t srcreg = (opcode & 7); | |
20812 | uint32_t dstreg = (opcode >> 9) & 7; | |
20813 | unsigned int retcycles = 0; | |
20814 | OpcodeFamily = 62; CurrentInstrCycles = 44; | |
20815 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
20816 | { int16_t src = m68k_read_memory_16(srca); | |
20817 | m68k_areg (regs, srcreg) = srca; | |
20818 | { int16_t dst = m68k_dreg(regs, dstreg); | |
20819 | { uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src; | |
20820 | CLEAR_CZNV; | |
20821 | SET_ZFLG (((int32_t)(newv)) == 0); | |
20822 | SET_NFLG (((int32_t)(newv)) < 0); | |
20823 | m68k_dreg(regs, dstreg) = (newv); | |
20824 | while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; } | |
20825 | }}}}}m68k_incpc(2); | |
20826 | return (44+retcycles*2); | |
20827 | } | |
20828 | unsigned long CPUFUNC(op_c0e8_4)(uint32_t opcode) /* MULU */ | |
20829 | { | |
20830 | uint32_t srcreg = (opcode & 7); | |
20831 | uint32_t dstreg = (opcode >> 9) & 7; | |
20832 | unsigned int retcycles = 0; | |
20833 | OpcodeFamily = 62; CurrentInstrCycles = 46; | |
20834 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
20835 | { int16_t src = m68k_read_memory_16(srca); | |
20836 | { int16_t dst = m68k_dreg(regs, dstreg); | |
20837 | { uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src; | |
20838 | CLEAR_CZNV; | |
20839 | SET_ZFLG (((int32_t)(newv)) == 0); | |
20840 | SET_NFLG (((int32_t)(newv)) < 0); | |
20841 | m68k_dreg(regs, dstreg) = (newv); | |
20842 | while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; } | |
20843 | }}}}}m68k_incpc(4); | |
20844 | return (46+retcycles*2); | |
20845 | } | |
20846 | unsigned long CPUFUNC(op_c0f0_4)(uint32_t opcode) /* MULU */ | |
20847 | { | |
20848 | uint32_t srcreg = (opcode & 7); | |
20849 | uint32_t dstreg = (opcode >> 9) & 7; | |
20850 | unsigned int retcycles = 0; | |
20851 | OpcodeFamily = 62; CurrentInstrCycles = 48; | |
20852 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
20853 | BusCyclePenalty += 2; | |
20854 | { int16_t src = m68k_read_memory_16(srca); | |
20855 | { int16_t dst = m68k_dreg(regs, dstreg); | |
20856 | { uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src; | |
20857 | CLEAR_CZNV; | |
20858 | SET_ZFLG (((int32_t)(newv)) == 0); | |
20859 | SET_NFLG (((int32_t)(newv)) < 0); | |
20860 | m68k_dreg(regs, dstreg) = (newv); | |
20861 | while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; } | |
20862 | }}}}}m68k_incpc(4); | |
20863 | return (48+retcycles*2); | |
20864 | } | |
20865 | unsigned long CPUFUNC(op_c0f8_4)(uint32_t opcode) /* MULU */ | |
20866 | { | |
20867 | uint32_t dstreg = (opcode >> 9) & 7; | |
20868 | unsigned int retcycles = 0; | |
20869 | OpcodeFamily = 62; CurrentInstrCycles = 46; | |
20870 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
20871 | { int16_t src = m68k_read_memory_16(srca); | |
20872 | { int16_t dst = m68k_dreg(regs, dstreg); | |
20873 | { uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src; | |
20874 | CLEAR_CZNV; | |
20875 | SET_ZFLG (((int32_t)(newv)) == 0); | |
20876 | SET_NFLG (((int32_t)(newv)) < 0); | |
20877 | m68k_dreg(regs, dstreg) = (newv); | |
20878 | while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; } | |
20879 | }}}}}m68k_incpc(4); | |
20880 | return (46+retcycles*2); | |
20881 | } | |
20882 | unsigned long CPUFUNC(op_c0f9_4)(uint32_t opcode) /* MULU */ | |
20883 | { | |
20884 | uint32_t dstreg = (opcode >> 9) & 7; | |
20885 | unsigned int retcycles = 0; | |
20886 | OpcodeFamily = 62; CurrentInstrCycles = 50; | |
20887 | {{ uint32_t srca = get_ilong(2); | |
20888 | { int16_t src = m68k_read_memory_16(srca); | |
20889 | { int16_t dst = m68k_dreg(regs, dstreg); | |
20890 | { uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src; | |
20891 | CLEAR_CZNV; | |
20892 | SET_ZFLG (((int32_t)(newv)) == 0); | |
20893 | SET_NFLG (((int32_t)(newv)) < 0); | |
20894 | m68k_dreg(regs, dstreg) = (newv); | |
20895 | while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; } | |
20896 | }}}}}m68k_incpc(6); | |
20897 | return (50+retcycles*2); | |
20898 | } | |
20899 | unsigned long CPUFUNC(op_c0fa_4)(uint32_t opcode) /* MULU */ | |
20900 | { | |
20901 | uint32_t dstreg = (opcode >> 9) & 7; | |
20902 | unsigned int retcycles = 0; | |
20903 | OpcodeFamily = 62; CurrentInstrCycles = 46; | |
20904 | {{ uint32_t srca = m68k_getpc () + 2; | |
20905 | srca += (int32_t)(int16_t)get_iword(2); | |
20906 | { int16_t src = m68k_read_memory_16(srca); | |
20907 | { int16_t dst = m68k_dreg(regs, dstreg); | |
20908 | { uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src; | |
20909 | CLEAR_CZNV; | |
20910 | SET_ZFLG (((int32_t)(newv)) == 0); | |
20911 | SET_NFLG (((int32_t)(newv)) < 0); | |
20912 | m68k_dreg(regs, dstreg) = (newv); | |
20913 | while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; } | |
20914 | }}}}}m68k_incpc(4); | |
20915 | return (46+retcycles*2); | |
20916 | } | |
20917 | unsigned long CPUFUNC(op_c0fb_4)(uint32_t opcode) /* MULU */ | |
20918 | { | |
20919 | uint32_t dstreg = (opcode >> 9) & 7; | |
20920 | unsigned int retcycles = 0; | |
20921 | OpcodeFamily = 62; CurrentInstrCycles = 48; | |
20922 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
20923 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
20924 | BusCyclePenalty += 2; | |
20925 | { int16_t src = m68k_read_memory_16(srca); | |
20926 | { int16_t dst = m68k_dreg(regs, dstreg); | |
20927 | { uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src; | |
20928 | CLEAR_CZNV; | |
20929 | SET_ZFLG (((int32_t)(newv)) == 0); | |
20930 | SET_NFLG (((int32_t)(newv)) < 0); | |
20931 | m68k_dreg(regs, dstreg) = (newv); | |
20932 | while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; } | |
20933 | }}}}}m68k_incpc(4); | |
20934 | return (48+retcycles*2); | |
20935 | } | |
20936 | unsigned long CPUFUNC(op_c0fc_4)(uint32_t opcode) /* MULU */ | |
20937 | { | |
20938 | uint32_t dstreg = (opcode >> 9) & 7; | |
20939 | unsigned int retcycles = 0; | |
20940 | OpcodeFamily = 62; CurrentInstrCycles = 42; | |
20941 | {{ int16_t src = get_iword(2); | |
20942 | { int16_t dst = m68k_dreg(regs, dstreg); | |
20943 | { uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src; | |
20944 | CLEAR_CZNV; | |
20945 | SET_ZFLG (((int32_t)(newv)) == 0); | |
20946 | SET_NFLG (((int32_t)(newv)) < 0); | |
20947 | m68k_dreg(regs, dstreg) = (newv); | |
20948 | while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; } | |
20949 | }}}}m68k_incpc(4); | |
20950 | return (42+retcycles*2); | |
20951 | } | |
20952 | unsigned long CPUFUNC(op_c100_4)(uint32_t opcode) /* ABCD */ | |
20953 | { | |
20954 | uint32_t srcreg = (opcode & 7); | |
20955 | uint32_t dstreg = (opcode >> 9) & 7; | |
20956 | OpcodeFamily = 14; CurrentInstrCycles = 6; | |
20957 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
20958 | { int8_t dst = m68k_dreg(regs, dstreg); | |
20959 | { uint16_t newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG ? 1 : 0); | |
20960 | uint16_t newv_hi = (src & 0xF0) + (dst & 0xF0); | |
20961 | uint16_t newv, tmp_newv; | |
20962 | int cflg; | |
20963 | newv = tmp_newv = newv_hi + newv_lo; if (newv_lo > 9) { newv += 6; } | |
20964 | cflg = (newv & 0x3F0) > 0x90; | |
20965 | if (cflg) newv += 0x60; | |
20966 | SET_CFLG (cflg); | |
20967 | COPY_CARRY; | |
20968 | SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); | |
20969 | SET_NFLG (((int8_t)(newv)) < 0); | |
20970 | SET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0); | |
20971 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
20972 | }}}}m68k_incpc(2); | |
20973 | return 6; | |
20974 | } | |
20975 | unsigned long CPUFUNC(op_c108_4)(uint32_t opcode) /* ABCD */ | |
20976 | { | |
20977 | uint32_t srcreg = (opcode & 7); | |
20978 | uint32_t dstreg = (opcode >> 9) & 7; | |
20979 | OpcodeFamily = 14; CurrentInstrCycles = 18; | |
20980 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
20981 | { int8_t src = m68k_read_memory_8(srca); | |
20982 | m68k_areg (regs, srcreg) = srca; | |
20983 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
20984 | { int8_t dst = m68k_read_memory_8(dsta); | |
20985 | m68k_areg (regs, dstreg) = dsta; | |
20986 | { uint16_t newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG ? 1 : 0); | |
20987 | uint16_t newv_hi = (src & 0xF0) + (dst & 0xF0); | |
20988 | uint16_t newv, tmp_newv; | |
20989 | int cflg; | |
20990 | newv = tmp_newv = newv_hi + newv_lo; if (newv_lo > 9) { newv += 6; } | |
20991 | cflg = (newv & 0x3F0) > 0x90; | |
20992 | if (cflg) newv += 0x60; | |
20993 | SET_CFLG (cflg); | |
20994 | COPY_CARRY; | |
20995 | SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); | |
20996 | SET_NFLG (((int8_t)(newv)) < 0); | |
20997 | SET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0); | |
20998 | m68k_write_memory_8(dsta,newv); | |
20999 | }}}}}}m68k_incpc(2); | |
21000 | return 18; | |
21001 | } | |
21002 | unsigned long CPUFUNC(op_c110_4)(uint32_t opcode) /* AND */ | |
21003 | { | |
21004 | uint32_t srcreg = ((opcode >> 9) & 7); | |
21005 | uint32_t dstreg = opcode & 7; | |
21006 | OpcodeFamily = 2; CurrentInstrCycles = 12; | |
21007 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
21008 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
21009 | { int8_t dst = m68k_read_memory_8(dsta); | |
21010 | src &= dst; | |
21011 | CLEAR_CZNV; | |
21012 | SET_ZFLG (((int8_t)(src)) == 0); | |
21013 | SET_NFLG (((int8_t)(src)) < 0); | |
21014 | m68k_write_memory_8(dsta,src); | |
21015 | }}}}m68k_incpc(2); | |
21016 | return 12; | |
21017 | } | |
21018 | unsigned long CPUFUNC(op_c118_4)(uint32_t opcode) /* AND */ | |
21019 | { | |
21020 | uint32_t srcreg = ((opcode >> 9) & 7); | |
21021 | uint32_t dstreg = opcode & 7; | |
21022 | OpcodeFamily = 2; CurrentInstrCycles = 12; | |
21023 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
21024 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
21025 | { int8_t dst = m68k_read_memory_8(dsta); | |
21026 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
21027 | src &= dst; | |
21028 | CLEAR_CZNV; | |
21029 | SET_ZFLG (((int8_t)(src)) == 0); | |
21030 | SET_NFLG (((int8_t)(src)) < 0); | |
21031 | m68k_write_memory_8(dsta,src); | |
21032 | }}}}m68k_incpc(2); | |
21033 | return 12; | |
21034 | } | |
21035 | unsigned long CPUFUNC(op_c120_4)(uint32_t opcode) /* AND */ | |
21036 | { | |
21037 | uint32_t srcreg = ((opcode >> 9) & 7); | |
21038 | uint32_t dstreg = opcode & 7; | |
21039 | OpcodeFamily = 2; CurrentInstrCycles = 14; | |
21040 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
21041 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
21042 | { int8_t dst = m68k_read_memory_8(dsta); | |
21043 | m68k_areg (regs, dstreg) = dsta; | |
21044 | src &= dst; | |
21045 | CLEAR_CZNV; | |
21046 | SET_ZFLG (((int8_t)(src)) == 0); | |
21047 | SET_NFLG (((int8_t)(src)) < 0); | |
21048 | m68k_write_memory_8(dsta,src); | |
21049 | }}}}m68k_incpc(2); | |
21050 | return 14; | |
21051 | } | |
21052 | unsigned long CPUFUNC(op_c128_4)(uint32_t opcode) /* AND */ | |
21053 | { | |
21054 | uint32_t srcreg = ((opcode >> 9) & 7); | |
21055 | uint32_t dstreg = opcode & 7; | |
21056 | OpcodeFamily = 2; CurrentInstrCycles = 16; | |
21057 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
21058 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); | |
21059 | { int8_t dst = m68k_read_memory_8(dsta); | |
21060 | src &= dst; | |
21061 | CLEAR_CZNV; | |
21062 | SET_ZFLG (((int8_t)(src)) == 0); | |
21063 | SET_NFLG (((int8_t)(src)) < 0); | |
21064 | m68k_write_memory_8(dsta,src); | |
21065 | }}}}m68k_incpc(4); | |
21066 | return 16; | |
21067 | } | |
21068 | unsigned long CPUFUNC(op_c130_4)(uint32_t opcode) /* AND */ | |
21069 | { | |
21070 | uint32_t srcreg = ((opcode >> 9) & 7); | |
21071 | uint32_t dstreg = opcode & 7; | |
21072 | OpcodeFamily = 2; CurrentInstrCycles = 18; | |
21073 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
21074 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); | |
21075 | BusCyclePenalty += 2; | |
21076 | { int8_t dst = m68k_read_memory_8(dsta); | |
21077 | src &= dst; | |
21078 | CLEAR_CZNV; | |
21079 | SET_ZFLG (((int8_t)(src)) == 0); | |
21080 | SET_NFLG (((int8_t)(src)) < 0); | |
21081 | m68k_write_memory_8(dsta,src); | |
21082 | }}}}m68k_incpc(4); | |
21083 | return 18; | |
21084 | } | |
21085 | unsigned long CPUFUNC(op_c138_4)(uint32_t opcode) /* AND */ | |
21086 | { | |
21087 | uint32_t srcreg = ((opcode >> 9) & 7); | |
21088 | OpcodeFamily = 2; CurrentInstrCycles = 16; | |
21089 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
21090 | { uint32_t dsta = (int32_t)(int16_t)get_iword(2); | |
21091 | { int8_t dst = m68k_read_memory_8(dsta); | |
21092 | src &= dst; | |
21093 | CLEAR_CZNV; | |
21094 | SET_ZFLG (((int8_t)(src)) == 0); | |
21095 | SET_NFLG (((int8_t)(src)) < 0); | |
21096 | m68k_write_memory_8(dsta,src); | |
21097 | }}}}m68k_incpc(4); | |
21098 | return 16; | |
21099 | } | |
21100 | unsigned long CPUFUNC(op_c139_4)(uint32_t opcode) /* AND */ | |
21101 | { | |
21102 | uint32_t srcreg = ((opcode >> 9) & 7); | |
21103 | OpcodeFamily = 2; CurrentInstrCycles = 20; | |
21104 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
21105 | { uint32_t dsta = get_ilong(2); | |
21106 | { int8_t dst = m68k_read_memory_8(dsta); | |
21107 | src &= dst; | |
21108 | CLEAR_CZNV; | |
21109 | SET_ZFLG (((int8_t)(src)) == 0); | |
21110 | SET_NFLG (((int8_t)(src)) < 0); | |
21111 | m68k_write_memory_8(dsta,src); | |
21112 | }}}}m68k_incpc(6); | |
21113 | return 20; | |
21114 | } | |
21115 | unsigned long CPUFUNC(op_c140_4)(uint32_t opcode) /* EXG */ | |
21116 | { | |
21117 | uint32_t srcreg = ((opcode >> 9) & 7); | |
21118 | uint32_t dstreg = opcode & 7; | |
21119 | OpcodeFamily = 35; CurrentInstrCycles = 6; | |
21120 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
21121 | { int32_t dst = m68k_dreg(regs, dstreg); | |
21122 | m68k_dreg(regs, srcreg) = (dst); | |
21123 | m68k_dreg(regs, dstreg) = (src); | |
21124 | }}}m68k_incpc(2); | |
21125 | return 6; | |
21126 | } | |
21127 | unsigned long CPUFUNC(op_c148_4)(uint32_t opcode) /* EXG */ | |
21128 | { | |
21129 | uint32_t srcreg = ((opcode >> 9) & 7); | |
21130 | uint32_t dstreg = opcode & 7; | |
21131 | OpcodeFamily = 35; CurrentInstrCycles = 6; | |
21132 | {{ int32_t src = m68k_areg(regs, srcreg); | |
21133 | { int32_t dst = m68k_areg(regs, dstreg); | |
21134 | m68k_areg(regs, srcreg) = (dst); | |
21135 | m68k_areg(regs, dstreg) = (src); | |
21136 | }}}m68k_incpc(2); | |
21137 | return 6; | |
21138 | } | |
21139 | unsigned long CPUFUNC(op_c150_4)(uint32_t opcode) /* AND */ | |
21140 | { | |
21141 | uint32_t srcreg = ((opcode >> 9) & 7); | |
21142 | uint32_t dstreg = opcode & 7; | |
21143 | OpcodeFamily = 2; CurrentInstrCycles = 12; | |
21144 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
21145 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
21146 | { int16_t dst = m68k_read_memory_16(dsta); | |
21147 | src &= dst; | |
21148 | CLEAR_CZNV; | |
21149 | SET_ZFLG (((int16_t)(src)) == 0); | |
21150 | SET_NFLG (((int16_t)(src)) < 0); | |
21151 | m68k_write_memory_16(dsta,src); | |
21152 | }}}}m68k_incpc(2); | |
21153 | return 12; | |
21154 | } | |
21155 | unsigned long CPUFUNC(op_c158_4)(uint32_t opcode) /* AND */ | |
21156 | { | |
21157 | uint32_t srcreg = ((opcode >> 9) & 7); | |
21158 | uint32_t dstreg = opcode & 7; | |
21159 | OpcodeFamily = 2; CurrentInstrCycles = 12; | |
21160 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
21161 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
21162 | { int16_t dst = m68k_read_memory_16(dsta); | |
21163 | m68k_areg(regs, dstreg) += 2; | |
21164 | src &= dst; | |
21165 | CLEAR_CZNV; | |
21166 | SET_ZFLG (((int16_t)(src)) == 0); | |
21167 | SET_NFLG (((int16_t)(src)) < 0); | |
21168 | m68k_write_memory_16(dsta,src); | |
21169 | }}}}m68k_incpc(2); | |
21170 | return 12; | |
21171 | } | |
21172 | unsigned long CPUFUNC(op_c160_4)(uint32_t opcode) /* AND */ | |
21173 | { | |
21174 | uint32_t srcreg = ((opcode >> 9) & 7); | |
21175 | uint32_t dstreg = opcode & 7; | |
21176 | OpcodeFamily = 2; CurrentInstrCycles = 14; | |
21177 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
21178 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
21179 | { int16_t dst = m68k_read_memory_16(dsta); | |
21180 | m68k_areg (regs, dstreg) = dsta; | |
21181 | src &= dst; | |
21182 | CLEAR_CZNV; | |
21183 | SET_ZFLG (((int16_t)(src)) == 0); | |
21184 | SET_NFLG (((int16_t)(src)) < 0); | |
21185 | m68k_write_memory_16(dsta,src); | |
21186 | }}}}m68k_incpc(2); | |
21187 | return 14; | |
21188 | } | |
21189 | unsigned long CPUFUNC(op_c168_4)(uint32_t opcode) /* AND */ | |
21190 | { | |
21191 | uint32_t srcreg = ((opcode >> 9) & 7); | |
21192 | uint32_t dstreg = opcode & 7; | |
21193 | OpcodeFamily = 2; CurrentInstrCycles = 16; | |
21194 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
21195 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); | |
21196 | { int16_t dst = m68k_read_memory_16(dsta); | |
21197 | src &= dst; | |
21198 | CLEAR_CZNV; | |
21199 | SET_ZFLG (((int16_t)(src)) == 0); | |
21200 | SET_NFLG (((int16_t)(src)) < 0); | |
21201 | m68k_write_memory_16(dsta,src); | |
21202 | }}}}m68k_incpc(4); | |
21203 | return 16; | |
21204 | } | |
21205 | unsigned long CPUFUNC(op_c170_4)(uint32_t opcode) /* AND */ | |
21206 | { | |
21207 | uint32_t srcreg = ((opcode >> 9) & 7); | |
21208 | uint32_t dstreg = opcode & 7; | |
21209 | OpcodeFamily = 2; CurrentInstrCycles = 18; | |
21210 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
21211 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); | |
21212 | BusCyclePenalty += 2; | |
21213 | { int16_t dst = m68k_read_memory_16(dsta); | |
21214 | src &= dst; | |
21215 | CLEAR_CZNV; | |
21216 | SET_ZFLG (((int16_t)(src)) == 0); | |
21217 | SET_NFLG (((int16_t)(src)) < 0); | |
21218 | m68k_write_memory_16(dsta,src); | |
21219 | }}}}m68k_incpc(4); | |
21220 | return 18; | |
21221 | } | |
21222 | unsigned long CPUFUNC(op_c178_4)(uint32_t opcode) /* AND */ | |
21223 | { | |
21224 | uint32_t srcreg = ((opcode >> 9) & 7); | |
21225 | OpcodeFamily = 2; CurrentInstrCycles = 16; | |
21226 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
21227 | { uint32_t dsta = (int32_t)(int16_t)get_iword(2); | |
21228 | { int16_t dst = m68k_read_memory_16(dsta); | |
21229 | src &= dst; | |
21230 | CLEAR_CZNV; | |
21231 | SET_ZFLG (((int16_t)(src)) == 0); | |
21232 | SET_NFLG (((int16_t)(src)) < 0); | |
21233 | m68k_write_memory_16(dsta,src); | |
21234 | }}}}m68k_incpc(4); | |
21235 | return 16; | |
21236 | } | |
21237 | unsigned long CPUFUNC(op_c179_4)(uint32_t opcode) /* AND */ | |
21238 | { | |
21239 | uint32_t srcreg = ((opcode >> 9) & 7); | |
21240 | OpcodeFamily = 2; CurrentInstrCycles = 20; | |
21241 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
21242 | { uint32_t dsta = get_ilong(2); | |
21243 | { int16_t dst = m68k_read_memory_16(dsta); | |
21244 | src &= dst; | |
21245 | CLEAR_CZNV; | |
21246 | SET_ZFLG (((int16_t)(src)) == 0); | |
21247 | SET_NFLG (((int16_t)(src)) < 0); | |
21248 | m68k_write_memory_16(dsta,src); | |
21249 | }}}}m68k_incpc(6); | |
21250 | return 20; | |
21251 | } | |
21252 | unsigned long CPUFUNC(op_c188_4)(uint32_t opcode) /* EXG */ | |
21253 | { | |
21254 | uint32_t srcreg = ((opcode >> 9) & 7); | |
21255 | uint32_t dstreg = opcode & 7; | |
21256 | OpcodeFamily = 35; CurrentInstrCycles = 6; | |
21257 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
21258 | { int32_t dst = m68k_areg(regs, dstreg); | |
21259 | m68k_dreg(regs, srcreg) = (dst); | |
21260 | m68k_areg(regs, dstreg) = (src); | |
21261 | }}}m68k_incpc(2); | |
21262 | return 6; | |
21263 | } | |
21264 | unsigned long CPUFUNC(op_c190_4)(uint32_t opcode) /* AND */ | |
21265 | { | |
21266 | uint32_t srcreg = ((opcode >> 9) & 7); | |
21267 | uint32_t dstreg = opcode & 7; | |
21268 | OpcodeFamily = 2; CurrentInstrCycles = 20; | |
21269 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
21270 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
21271 | { int32_t dst = m68k_read_memory_32(dsta); | |
21272 | src &= dst; | |
21273 | CLEAR_CZNV; | |
21274 | SET_ZFLG (((int32_t)(src)) == 0); | |
21275 | SET_NFLG (((int32_t)(src)) < 0); | |
21276 | m68k_write_memory_32(dsta,src); | |
21277 | }}}}m68k_incpc(2); | |
21278 | return 20; | |
21279 | } | |
21280 | unsigned long CPUFUNC(op_c198_4)(uint32_t opcode) /* AND */ | |
21281 | { | |
21282 | uint32_t srcreg = ((opcode >> 9) & 7); | |
21283 | uint32_t dstreg = opcode & 7; | |
21284 | OpcodeFamily = 2; CurrentInstrCycles = 20; | |
21285 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
21286 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
21287 | { int32_t dst = m68k_read_memory_32(dsta); | |
21288 | m68k_areg(regs, dstreg) += 4; | |
21289 | src &= dst; | |
21290 | CLEAR_CZNV; | |
21291 | SET_ZFLG (((int32_t)(src)) == 0); | |
21292 | SET_NFLG (((int32_t)(src)) < 0); | |
21293 | m68k_write_memory_32(dsta,src); | |
21294 | }}}}m68k_incpc(2); | |
21295 | return 20; | |
21296 | } | |
21297 | unsigned long CPUFUNC(op_c1a0_4)(uint32_t opcode) /* AND */ | |
21298 | { | |
21299 | uint32_t srcreg = ((opcode >> 9) & 7); | |
21300 | uint32_t dstreg = opcode & 7; | |
21301 | OpcodeFamily = 2; CurrentInstrCycles = 22; | |
21302 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
21303 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
21304 | { int32_t dst = m68k_read_memory_32(dsta); | |
21305 | m68k_areg (regs, dstreg) = dsta; | |
21306 | src &= dst; | |
21307 | CLEAR_CZNV; | |
21308 | SET_ZFLG (((int32_t)(src)) == 0); | |
21309 | SET_NFLG (((int32_t)(src)) < 0); | |
21310 | m68k_write_memory_32(dsta,src); | |
21311 | }}}}m68k_incpc(2); | |
21312 | return 22; | |
21313 | } | |
21314 | unsigned long CPUFUNC(op_c1a8_4)(uint32_t opcode) /* AND */ | |
21315 | { | |
21316 | uint32_t srcreg = ((opcode >> 9) & 7); | |
21317 | uint32_t dstreg = opcode & 7; | |
21318 | OpcodeFamily = 2; CurrentInstrCycles = 24; | |
21319 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
21320 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); | |
21321 | { int32_t dst = m68k_read_memory_32(dsta); | |
21322 | src &= dst; | |
21323 | CLEAR_CZNV; | |
21324 | SET_ZFLG (((int32_t)(src)) == 0); | |
21325 | SET_NFLG (((int32_t)(src)) < 0); | |
21326 | m68k_write_memory_32(dsta,src); | |
21327 | }}}}m68k_incpc(4); | |
21328 | return 24; | |
21329 | } | |
21330 | unsigned long CPUFUNC(op_c1b0_4)(uint32_t opcode) /* AND */ | |
21331 | { | |
21332 | uint32_t srcreg = ((opcode >> 9) & 7); | |
21333 | uint32_t dstreg = opcode & 7; | |
21334 | OpcodeFamily = 2; CurrentInstrCycles = 26; | |
21335 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
21336 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); | |
21337 | BusCyclePenalty += 2; | |
21338 | { int32_t dst = m68k_read_memory_32(dsta); | |
21339 | src &= dst; | |
21340 | CLEAR_CZNV; | |
21341 | SET_ZFLG (((int32_t)(src)) == 0); | |
21342 | SET_NFLG (((int32_t)(src)) < 0); | |
21343 | m68k_write_memory_32(dsta,src); | |
21344 | }}}}m68k_incpc(4); | |
21345 | return 26; | |
21346 | } | |
21347 | unsigned long CPUFUNC(op_c1b8_4)(uint32_t opcode) /* AND */ | |
21348 | { | |
21349 | uint32_t srcreg = ((opcode >> 9) & 7); | |
21350 | OpcodeFamily = 2; CurrentInstrCycles = 24; | |
21351 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
21352 | { uint32_t dsta = (int32_t)(int16_t)get_iword(2); | |
21353 | { int32_t dst = m68k_read_memory_32(dsta); | |
21354 | src &= dst; | |
21355 | CLEAR_CZNV; | |
21356 | SET_ZFLG (((int32_t)(src)) == 0); | |
21357 | SET_NFLG (((int32_t)(src)) < 0); | |
21358 | m68k_write_memory_32(dsta,src); | |
21359 | }}}}m68k_incpc(4); | |
21360 | return 24; | |
21361 | } | |
21362 | unsigned long CPUFUNC(op_c1b9_4)(uint32_t opcode) /* AND */ | |
21363 | { | |
21364 | uint32_t srcreg = ((opcode >> 9) & 7); | |
21365 | OpcodeFamily = 2; CurrentInstrCycles = 28; | |
21366 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
21367 | { uint32_t dsta = get_ilong(2); | |
21368 | { int32_t dst = m68k_read_memory_32(dsta); | |
21369 | src &= dst; | |
21370 | CLEAR_CZNV; | |
21371 | SET_ZFLG (((int32_t)(src)) == 0); | |
21372 | SET_NFLG (((int32_t)(src)) < 0); | |
21373 | m68k_write_memory_32(dsta,src); | |
21374 | }}}}m68k_incpc(6); | |
21375 | return 28; | |
21376 | } | |
21377 | unsigned long CPUFUNC(op_c1c0_4)(uint32_t opcode) /* MULS */ | |
21378 | { | |
21379 | uint32_t srcreg = (opcode & 7); | |
21380 | uint32_t dstreg = (opcode >> 9) & 7; | |
21381 | unsigned int retcycles = 0; | |
21382 | OpcodeFamily = 63; CurrentInstrCycles = 38; | |
21383 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
21384 | { int16_t dst = m68k_dreg(regs, dstreg); | |
21385 | { uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src; | |
21386 | uint32_t src2; | |
21387 | CLEAR_CZNV; | |
21388 | SET_ZFLG (((int32_t)(newv)) == 0); | |
21389 | SET_NFLG (((int32_t)(newv)) < 0); | |
21390 | m68k_dreg(regs, dstreg) = (newv); | |
21391 | src2 = ((uint32_t)src) << 1; | |
21392 | while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; } | |
21393 | }}}}m68k_incpc(2); | |
21394 | return (38+retcycles*2); | |
21395 | } | |
21396 | unsigned long CPUFUNC(op_c1d0_4)(uint32_t opcode) /* MULS */ | |
21397 | { | |
21398 | uint32_t srcreg = (opcode & 7); | |
21399 | uint32_t dstreg = (opcode >> 9) & 7; | |
21400 | unsigned int retcycles = 0; | |
21401 | OpcodeFamily = 63; CurrentInstrCycles = 42; | |
21402 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
21403 | { int16_t src = m68k_read_memory_16(srca); | |
21404 | { int16_t dst = m68k_dreg(regs, dstreg); | |
21405 | { uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src; | |
21406 | uint32_t src2; | |
21407 | CLEAR_CZNV; | |
21408 | SET_ZFLG (((int32_t)(newv)) == 0); | |
21409 | SET_NFLG (((int32_t)(newv)) < 0); | |
21410 | m68k_dreg(regs, dstreg) = (newv); | |
21411 | src2 = ((uint32_t)src) << 1; | |
21412 | while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; } | |
21413 | }}}}}m68k_incpc(2); | |
21414 | return (42+retcycles*2); | |
21415 | } | |
21416 | unsigned long CPUFUNC(op_c1d8_4)(uint32_t opcode) /* MULS */ | |
21417 | { | |
21418 | uint32_t srcreg = (opcode & 7); | |
21419 | uint32_t dstreg = (opcode >> 9) & 7; | |
21420 | unsigned int retcycles = 0; | |
21421 | OpcodeFamily = 63; CurrentInstrCycles = 42; | |
21422 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
21423 | { int16_t src = m68k_read_memory_16(srca); | |
21424 | m68k_areg(regs, srcreg) += 2; | |
21425 | { int16_t dst = m68k_dreg(regs, dstreg); | |
21426 | { uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src; | |
21427 | uint32_t src2; | |
21428 | CLEAR_CZNV; | |
21429 | SET_ZFLG (((int32_t)(newv)) == 0); | |
21430 | SET_NFLG (((int32_t)(newv)) < 0); | |
21431 | m68k_dreg(regs, dstreg) = (newv); | |
21432 | src2 = ((uint32_t)src) << 1; | |
21433 | while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; } | |
21434 | }}}}}m68k_incpc(2); | |
21435 | return (42+retcycles*2); | |
21436 | } | |
21437 | unsigned long CPUFUNC(op_c1e0_4)(uint32_t opcode) /* MULS */ | |
21438 | { | |
21439 | uint32_t srcreg = (opcode & 7); | |
21440 | uint32_t dstreg = (opcode >> 9) & 7; | |
21441 | unsigned int retcycles = 0; | |
21442 | OpcodeFamily = 63; CurrentInstrCycles = 44; | |
21443 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
21444 | { int16_t src = m68k_read_memory_16(srca); | |
21445 | m68k_areg (regs, srcreg) = srca; | |
21446 | { int16_t dst = m68k_dreg(regs, dstreg); | |
21447 | { uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src; | |
21448 | uint32_t src2; | |
21449 | CLEAR_CZNV; | |
21450 | SET_ZFLG (((int32_t)(newv)) == 0); | |
21451 | SET_NFLG (((int32_t)(newv)) < 0); | |
21452 | m68k_dreg(regs, dstreg) = (newv); | |
21453 | src2 = ((uint32_t)src) << 1; | |
21454 | while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; } | |
21455 | }}}}}m68k_incpc(2); | |
21456 | return (44+retcycles*2); | |
21457 | } | |
21458 | unsigned long CPUFUNC(op_c1e8_4)(uint32_t opcode) /* MULS */ | |
21459 | { | |
21460 | uint32_t srcreg = (opcode & 7); | |
21461 | uint32_t dstreg = (opcode >> 9) & 7; | |
21462 | unsigned int retcycles = 0; | |
21463 | OpcodeFamily = 63; CurrentInstrCycles = 46; | |
21464 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
21465 | { int16_t src = m68k_read_memory_16(srca); | |
21466 | { int16_t dst = m68k_dreg(regs, dstreg); | |
21467 | { uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src; | |
21468 | uint32_t src2; | |
21469 | CLEAR_CZNV; | |
21470 | SET_ZFLG (((int32_t)(newv)) == 0); | |
21471 | SET_NFLG (((int32_t)(newv)) < 0); | |
21472 | m68k_dreg(regs, dstreg) = (newv); | |
21473 | src2 = ((uint32_t)src) << 1; | |
21474 | while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; } | |
21475 | }}}}}m68k_incpc(4); | |
21476 | return (46+retcycles*2); | |
21477 | } | |
21478 | unsigned long CPUFUNC(op_c1f0_4)(uint32_t opcode) /* MULS */ | |
21479 | { | |
21480 | uint32_t srcreg = (opcode & 7); | |
21481 | uint32_t dstreg = (opcode >> 9) & 7; | |
21482 | unsigned int retcycles = 0; | |
21483 | OpcodeFamily = 63; CurrentInstrCycles = 48; | |
21484 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
21485 | BusCyclePenalty += 2; | |
21486 | { int16_t src = m68k_read_memory_16(srca); | |
21487 | { int16_t dst = m68k_dreg(regs, dstreg); | |
21488 | { uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src; | |
21489 | uint32_t src2; | |
21490 | CLEAR_CZNV; | |
21491 | SET_ZFLG (((int32_t)(newv)) == 0); | |
21492 | SET_NFLG (((int32_t)(newv)) < 0); | |
21493 | m68k_dreg(regs, dstreg) = (newv); | |
21494 | src2 = ((uint32_t)src) << 1; | |
21495 | while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; } | |
21496 | }}}}}m68k_incpc(4); | |
21497 | return (48+retcycles*2); | |
21498 | } | |
21499 | unsigned long CPUFUNC(op_c1f8_4)(uint32_t opcode) /* MULS */ | |
21500 | { | |
21501 | uint32_t dstreg = (opcode >> 9) & 7; | |
21502 | unsigned int retcycles = 0; | |
21503 | OpcodeFamily = 63; CurrentInstrCycles = 46; | |
21504 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
21505 | { int16_t src = m68k_read_memory_16(srca); | |
21506 | { int16_t dst = m68k_dreg(regs, dstreg); | |
21507 | { uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src; | |
21508 | uint32_t src2; | |
21509 | CLEAR_CZNV; | |
21510 | SET_ZFLG (((int32_t)(newv)) == 0); | |
21511 | SET_NFLG (((int32_t)(newv)) < 0); | |
21512 | m68k_dreg(regs, dstreg) = (newv); | |
21513 | src2 = ((uint32_t)src) << 1; | |
21514 | while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; } | |
21515 | }}}}}m68k_incpc(4); | |
21516 | return (46+retcycles*2); | |
21517 | } | |
21518 | unsigned long CPUFUNC(op_c1f9_4)(uint32_t opcode) /* MULS */ | |
21519 | { | |
21520 | uint32_t dstreg = (opcode >> 9) & 7; | |
21521 | unsigned int retcycles = 0; | |
21522 | OpcodeFamily = 63; CurrentInstrCycles = 50; | |
21523 | {{ uint32_t srca = get_ilong(2); | |
21524 | { int16_t src = m68k_read_memory_16(srca); | |
21525 | { int16_t dst = m68k_dreg(regs, dstreg); | |
21526 | { uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src; | |
21527 | uint32_t src2; | |
21528 | CLEAR_CZNV; | |
21529 | SET_ZFLG (((int32_t)(newv)) == 0); | |
21530 | SET_NFLG (((int32_t)(newv)) < 0); | |
21531 | m68k_dreg(regs, dstreg) = (newv); | |
21532 | src2 = ((uint32_t)src) << 1; | |
21533 | while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; } | |
21534 | }}}}}m68k_incpc(6); | |
21535 | return (50+retcycles*2); | |
21536 | } | |
21537 | unsigned long CPUFUNC(op_c1fa_4)(uint32_t opcode) /* MULS */ | |
21538 | { | |
21539 | uint32_t dstreg = (opcode >> 9) & 7; | |
21540 | unsigned int retcycles = 0; | |
21541 | OpcodeFamily = 63; CurrentInstrCycles = 46; | |
21542 | {{ uint32_t srca = m68k_getpc () + 2; | |
21543 | srca += (int32_t)(int16_t)get_iword(2); | |
21544 | { int16_t src = m68k_read_memory_16(srca); | |
21545 | { int16_t dst = m68k_dreg(regs, dstreg); | |
21546 | { uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src; | |
21547 | uint32_t src2; | |
21548 | CLEAR_CZNV; | |
21549 | SET_ZFLG (((int32_t)(newv)) == 0); | |
21550 | SET_NFLG (((int32_t)(newv)) < 0); | |
21551 | m68k_dreg(regs, dstreg) = (newv); | |
21552 | src2 = ((uint32_t)src) << 1; | |
21553 | while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; } | |
21554 | }}}}}m68k_incpc(4); | |
21555 | return (46+retcycles*2); | |
21556 | } | |
21557 | unsigned long CPUFUNC(op_c1fb_4)(uint32_t opcode) /* MULS */ | |
21558 | { | |
21559 | uint32_t dstreg = (opcode >> 9) & 7; | |
21560 | unsigned int retcycles = 0; | |
21561 | OpcodeFamily = 63; CurrentInstrCycles = 48; | |
21562 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
21563 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
21564 | BusCyclePenalty += 2; | |
21565 | { int16_t src = m68k_read_memory_16(srca); | |
21566 | { int16_t dst = m68k_dreg(regs, dstreg); | |
21567 | { uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src; | |
21568 | uint32_t src2; | |
21569 | CLEAR_CZNV; | |
21570 | SET_ZFLG (((int32_t)(newv)) == 0); | |
21571 | SET_NFLG (((int32_t)(newv)) < 0); | |
21572 | m68k_dreg(regs, dstreg) = (newv); | |
21573 | src2 = ((uint32_t)src) << 1; | |
21574 | while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; } | |
21575 | }}}}}m68k_incpc(4); | |
21576 | return (48+retcycles*2); | |
21577 | } | |
21578 | unsigned long CPUFUNC(op_c1fc_4)(uint32_t opcode) /* MULS */ | |
21579 | { | |
21580 | uint32_t dstreg = (opcode >> 9) & 7; | |
21581 | unsigned int retcycles = 0; | |
21582 | OpcodeFamily = 63; CurrentInstrCycles = 42; | |
21583 | {{ int16_t src = get_iword(2); | |
21584 | { int16_t dst = m68k_dreg(regs, dstreg); | |
21585 | { uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src; | |
21586 | uint32_t src2; | |
21587 | CLEAR_CZNV; | |
21588 | SET_ZFLG (((int32_t)(newv)) == 0); | |
21589 | SET_NFLG (((int32_t)(newv)) < 0); | |
21590 | m68k_dreg(regs, dstreg) = (newv); | |
21591 | src2 = ((uint32_t)src) << 1; | |
21592 | while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; } | |
21593 | }}}}m68k_incpc(4); | |
21594 | return (42+retcycles*2); | |
21595 | } | |
21596 | unsigned long CPUFUNC(op_d000_4)(uint32_t opcode) /* ADD */ | |
21597 | { | |
21598 | uint32_t srcreg = (opcode & 7); | |
21599 | uint32_t dstreg = (opcode >> 9) & 7; | |
21600 | OpcodeFamily = 11; CurrentInstrCycles = 4; | |
21601 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
21602 | { int8_t dst = m68k_dreg(regs, dstreg); | |
21603 | { refill_prefetch (m68k_getpc(), 2); | |
21604 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
21605 | { int flgs = ((int8_t)(src)) < 0; | |
21606 | int flgo = ((int8_t)(dst)) < 0; | |
21607 | int flgn = ((int8_t)(newv)) < 0; | |
21608 | SET_ZFLG (((int8_t)(newv)) == 0); | |
21609 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
21610 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
21611 | COPY_CARRY; | |
21612 | SET_NFLG (flgn != 0); | |
21613 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
21614 | }}}}}}m68k_incpc(2); | |
21615 | return 4; | |
21616 | } | |
21617 | unsigned long CPUFUNC(op_d010_4)(uint32_t opcode) /* ADD */ | |
21618 | { | |
21619 | uint32_t srcreg = (opcode & 7); | |
21620 | uint32_t dstreg = (opcode >> 9) & 7; | |
21621 | OpcodeFamily = 11; CurrentInstrCycles = 8; | |
21622 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
21623 | { int8_t src = m68k_read_memory_8(srca); | |
21624 | { int8_t dst = m68k_dreg(regs, dstreg); | |
21625 | { refill_prefetch (m68k_getpc(), 2); | |
21626 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
21627 | { int flgs = ((int8_t)(src)) < 0; | |
21628 | int flgo = ((int8_t)(dst)) < 0; | |
21629 | int flgn = ((int8_t)(newv)) < 0; | |
21630 | SET_ZFLG (((int8_t)(newv)) == 0); | |
21631 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
21632 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
21633 | COPY_CARRY; | |
21634 | SET_NFLG (flgn != 0); | |
21635 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
21636 | }}}}}}}m68k_incpc(2); | |
21637 | return 8; | |
21638 | } | |
21639 | unsigned long CPUFUNC(op_d018_4)(uint32_t opcode) /* ADD */ | |
21640 | { | |
21641 | uint32_t srcreg = (opcode & 7); | |
21642 | uint32_t dstreg = (opcode >> 9) & 7; | |
21643 | OpcodeFamily = 11; CurrentInstrCycles = 8; | |
21644 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
21645 | { int8_t src = m68k_read_memory_8(srca); | |
21646 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
21647 | { int8_t dst = m68k_dreg(regs, dstreg); | |
21648 | { refill_prefetch (m68k_getpc(), 2); | |
21649 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
21650 | { int flgs = ((int8_t)(src)) < 0; | |
21651 | int flgo = ((int8_t)(dst)) < 0; | |
21652 | int flgn = ((int8_t)(newv)) < 0; | |
21653 | SET_ZFLG (((int8_t)(newv)) == 0); | |
21654 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
21655 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
21656 | COPY_CARRY; | |
21657 | SET_NFLG (flgn != 0); | |
21658 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
21659 | }}}}}}}m68k_incpc(2); | |
21660 | return 8; | |
21661 | } | |
21662 | unsigned long CPUFUNC(op_d020_4)(uint32_t opcode) /* ADD */ | |
21663 | { | |
21664 | uint32_t srcreg = (opcode & 7); | |
21665 | uint32_t dstreg = (opcode >> 9) & 7; | |
21666 | OpcodeFamily = 11; CurrentInstrCycles = 10; | |
21667 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
21668 | { int8_t src = m68k_read_memory_8(srca); | |
21669 | m68k_areg (regs, srcreg) = srca; | |
21670 | { int8_t dst = m68k_dreg(regs, dstreg); | |
21671 | { refill_prefetch (m68k_getpc(), 2); | |
21672 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
21673 | { int flgs = ((int8_t)(src)) < 0; | |
21674 | int flgo = ((int8_t)(dst)) < 0; | |
21675 | int flgn = ((int8_t)(newv)) < 0; | |
21676 | SET_ZFLG (((int8_t)(newv)) == 0); | |
21677 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
21678 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
21679 | COPY_CARRY; | |
21680 | SET_NFLG (flgn != 0); | |
21681 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
21682 | }}}}}}}m68k_incpc(2); | |
21683 | return 10; | |
21684 | } | |
21685 | unsigned long CPUFUNC(op_d028_4)(uint32_t opcode) /* ADD */ | |
21686 | { | |
21687 | uint32_t srcreg = (opcode & 7); | |
21688 | uint32_t dstreg = (opcode >> 9) & 7; | |
21689 | OpcodeFamily = 11; CurrentInstrCycles = 12; | |
21690 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
21691 | { int8_t src = m68k_read_memory_8(srca); | |
21692 | { int8_t dst = m68k_dreg(regs, dstreg); | |
21693 | { refill_prefetch (m68k_getpc(), 2); | |
21694 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
21695 | { int flgs = ((int8_t)(src)) < 0; | |
21696 | int flgo = ((int8_t)(dst)) < 0; | |
21697 | int flgn = ((int8_t)(newv)) < 0; | |
21698 | SET_ZFLG (((int8_t)(newv)) == 0); | |
21699 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
21700 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
21701 | COPY_CARRY; | |
21702 | SET_NFLG (flgn != 0); | |
21703 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
21704 | }}}}}}}m68k_incpc(4); | |
21705 | return 12; | |
21706 | } | |
21707 | unsigned long CPUFUNC(op_d030_4)(uint32_t opcode) /* ADD */ | |
21708 | { | |
21709 | uint32_t srcreg = (opcode & 7); | |
21710 | uint32_t dstreg = (opcode >> 9) & 7; | |
21711 | OpcodeFamily = 11; CurrentInstrCycles = 14; | |
21712 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
21713 | BusCyclePenalty += 2; | |
21714 | { int8_t src = m68k_read_memory_8(srca); | |
21715 | { int8_t dst = m68k_dreg(regs, dstreg); | |
21716 | { refill_prefetch (m68k_getpc(), 2); | |
21717 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
21718 | { int flgs = ((int8_t)(src)) < 0; | |
21719 | int flgo = ((int8_t)(dst)) < 0; | |
21720 | int flgn = ((int8_t)(newv)) < 0; | |
21721 | SET_ZFLG (((int8_t)(newv)) == 0); | |
21722 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
21723 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
21724 | COPY_CARRY; | |
21725 | SET_NFLG (flgn != 0); | |
21726 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
21727 | }}}}}}}m68k_incpc(4); | |
21728 | return 14; | |
21729 | } | |
21730 | unsigned long CPUFUNC(op_d038_4)(uint32_t opcode) /* ADD */ | |
21731 | { | |
21732 | uint32_t dstreg = (opcode >> 9) & 7; | |
21733 | OpcodeFamily = 11; CurrentInstrCycles = 12; | |
21734 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
21735 | { int8_t src = m68k_read_memory_8(srca); | |
21736 | { int8_t dst = m68k_dreg(regs, dstreg); | |
21737 | { refill_prefetch (m68k_getpc(), 2); | |
21738 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
21739 | { int flgs = ((int8_t)(src)) < 0; | |
21740 | int flgo = ((int8_t)(dst)) < 0; | |
21741 | int flgn = ((int8_t)(newv)) < 0; | |
21742 | SET_ZFLG (((int8_t)(newv)) == 0); | |
21743 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
21744 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
21745 | COPY_CARRY; | |
21746 | SET_NFLG (flgn != 0); | |
21747 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
21748 | }}}}}}}m68k_incpc(4); | |
21749 | return 12; | |
21750 | } | |
21751 | unsigned long CPUFUNC(op_d039_4)(uint32_t opcode) /* ADD */ | |
21752 | { | |
21753 | uint32_t dstreg = (opcode >> 9) & 7; | |
21754 | OpcodeFamily = 11; CurrentInstrCycles = 16; | |
21755 | {{ uint32_t srca = get_ilong(2); | |
21756 | { int8_t src = m68k_read_memory_8(srca); | |
21757 | { int8_t dst = m68k_dreg(regs, dstreg); | |
21758 | { refill_prefetch (m68k_getpc(), 2); | |
21759 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
21760 | { int flgs = ((int8_t)(src)) < 0; | |
21761 | int flgo = ((int8_t)(dst)) < 0; | |
21762 | int flgn = ((int8_t)(newv)) < 0; | |
21763 | SET_ZFLG (((int8_t)(newv)) == 0); | |
21764 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
21765 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
21766 | COPY_CARRY; | |
21767 | SET_NFLG (flgn != 0); | |
21768 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
21769 | }}}}}}}m68k_incpc(6); | |
21770 | return 16; | |
21771 | } | |
21772 | unsigned long CPUFUNC(op_d03a_4)(uint32_t opcode) /* ADD */ | |
21773 | { | |
21774 | uint32_t dstreg = (opcode >> 9) & 7; | |
21775 | OpcodeFamily = 11; CurrentInstrCycles = 12; | |
21776 | {{ uint32_t srca = m68k_getpc () + 2; | |
21777 | srca += (int32_t)(int16_t)get_iword(2); | |
21778 | { int8_t src = m68k_read_memory_8(srca); | |
21779 | { int8_t dst = m68k_dreg(regs, dstreg); | |
21780 | { refill_prefetch (m68k_getpc(), 2); | |
21781 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
21782 | { int flgs = ((int8_t)(src)) < 0; | |
21783 | int flgo = ((int8_t)(dst)) < 0; | |
21784 | int flgn = ((int8_t)(newv)) < 0; | |
21785 | SET_ZFLG (((int8_t)(newv)) == 0); | |
21786 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
21787 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
21788 | COPY_CARRY; | |
21789 | SET_NFLG (flgn != 0); | |
21790 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
21791 | }}}}}}}m68k_incpc(4); | |
21792 | return 12; | |
21793 | } | |
21794 | unsigned long CPUFUNC(op_d03b_4)(uint32_t opcode) /* ADD */ | |
21795 | { | |
21796 | uint32_t dstreg = (opcode >> 9) & 7; | |
21797 | OpcodeFamily = 11; CurrentInstrCycles = 14; | |
21798 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
21799 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
21800 | BusCyclePenalty += 2; | |
21801 | { int8_t src = m68k_read_memory_8(srca); | |
21802 | { int8_t dst = m68k_dreg(regs, dstreg); | |
21803 | { refill_prefetch (m68k_getpc(), 2); | |
21804 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
21805 | { int flgs = ((int8_t)(src)) < 0; | |
21806 | int flgo = ((int8_t)(dst)) < 0; | |
21807 | int flgn = ((int8_t)(newv)) < 0; | |
21808 | SET_ZFLG (((int8_t)(newv)) == 0); | |
21809 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
21810 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
21811 | COPY_CARRY; | |
21812 | SET_NFLG (flgn != 0); | |
21813 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
21814 | }}}}}}}m68k_incpc(4); | |
21815 | return 14; | |
21816 | } | |
21817 | unsigned long CPUFUNC(op_d03c_4)(uint32_t opcode) /* ADD */ | |
21818 | { | |
21819 | uint32_t dstreg = (opcode >> 9) & 7; | |
21820 | OpcodeFamily = 11; CurrentInstrCycles = 8; | |
21821 | {{ int8_t src = get_ibyte(2); | |
21822 | { int8_t dst = m68k_dreg(regs, dstreg); | |
21823 | { refill_prefetch (m68k_getpc(), 2); | |
21824 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
21825 | { int flgs = ((int8_t)(src)) < 0; | |
21826 | int flgo = ((int8_t)(dst)) < 0; | |
21827 | int flgn = ((int8_t)(newv)) < 0; | |
21828 | SET_ZFLG (((int8_t)(newv)) == 0); | |
21829 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
21830 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
21831 | COPY_CARRY; | |
21832 | SET_NFLG (flgn != 0); | |
21833 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
21834 | }}}}}}m68k_incpc(4); | |
21835 | return 8; | |
21836 | } | |
21837 | unsigned long CPUFUNC(op_d040_4)(uint32_t opcode) /* ADD */ | |
21838 | { | |
21839 | uint32_t srcreg = (opcode & 7); | |
21840 | uint32_t dstreg = (opcode >> 9) & 7; | |
21841 | OpcodeFamily = 11; CurrentInstrCycles = 4; | |
21842 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
21843 | { int16_t dst = m68k_dreg(regs, dstreg); | |
21844 | { refill_prefetch (m68k_getpc(), 2); | |
21845 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
21846 | { int flgs = ((int16_t)(src)) < 0; | |
21847 | int flgo = ((int16_t)(dst)) < 0; | |
21848 | int flgn = ((int16_t)(newv)) < 0; | |
21849 | SET_ZFLG (((int16_t)(newv)) == 0); | |
21850 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
21851 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
21852 | COPY_CARRY; | |
21853 | SET_NFLG (flgn != 0); | |
21854 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
21855 | }}}}}}m68k_incpc(2); | |
21856 | return 4; | |
21857 | } | |
21858 | unsigned long CPUFUNC(op_d048_4)(uint32_t opcode) /* ADD */ | |
21859 | { | |
21860 | uint32_t srcreg = (opcode & 7); | |
21861 | uint32_t dstreg = (opcode >> 9) & 7; | |
21862 | OpcodeFamily = 11; CurrentInstrCycles = 4; | |
21863 | {{ int16_t src = m68k_areg(regs, srcreg); | |
21864 | { int16_t dst = m68k_dreg(regs, dstreg); | |
21865 | { refill_prefetch (m68k_getpc(), 2); | |
21866 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
21867 | { int flgs = ((int16_t)(src)) < 0; | |
21868 | int flgo = ((int16_t)(dst)) < 0; | |
21869 | int flgn = ((int16_t)(newv)) < 0; | |
21870 | SET_ZFLG (((int16_t)(newv)) == 0); | |
21871 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
21872 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
21873 | COPY_CARRY; | |
21874 | SET_NFLG (flgn != 0); | |
21875 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
21876 | }}}}}}m68k_incpc(2); | |
21877 | return 4; | |
21878 | } | |
21879 | unsigned long CPUFUNC(op_d050_4)(uint32_t opcode) /* ADD */ | |
21880 | { | |
21881 | uint32_t srcreg = (opcode & 7); | |
21882 | uint32_t dstreg = (opcode >> 9) & 7; | |
21883 | OpcodeFamily = 11; CurrentInstrCycles = 8; | |
21884 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
21885 | { int16_t src = m68k_read_memory_16(srca); | |
21886 | { int16_t dst = m68k_dreg(regs, dstreg); | |
21887 | { refill_prefetch (m68k_getpc(), 2); | |
21888 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
21889 | { int flgs = ((int16_t)(src)) < 0; | |
21890 | int flgo = ((int16_t)(dst)) < 0; | |
21891 | int flgn = ((int16_t)(newv)) < 0; | |
21892 | SET_ZFLG (((int16_t)(newv)) == 0); | |
21893 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
21894 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
21895 | COPY_CARRY; | |
21896 | SET_NFLG (flgn != 0); | |
21897 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
21898 | }}}}}}}m68k_incpc(2); | |
21899 | return 8; | |
21900 | } | |
21901 | unsigned long CPUFUNC(op_d058_4)(uint32_t opcode) /* ADD */ | |
21902 | { | |
21903 | uint32_t srcreg = (opcode & 7); | |
21904 | uint32_t dstreg = (opcode >> 9) & 7; | |
21905 | OpcodeFamily = 11; CurrentInstrCycles = 8; | |
21906 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
21907 | { int16_t src = m68k_read_memory_16(srca); | |
21908 | m68k_areg(regs, srcreg) += 2; | |
21909 | { int16_t dst = m68k_dreg(regs, dstreg); | |
21910 | { refill_prefetch (m68k_getpc(), 2); | |
21911 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
21912 | { int flgs = ((int16_t)(src)) < 0; | |
21913 | int flgo = ((int16_t)(dst)) < 0; | |
21914 | int flgn = ((int16_t)(newv)) < 0; | |
21915 | SET_ZFLG (((int16_t)(newv)) == 0); | |
21916 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
21917 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
21918 | COPY_CARRY; | |
21919 | SET_NFLG (flgn != 0); | |
21920 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
21921 | }}}}}}}m68k_incpc(2); | |
21922 | return 8; | |
21923 | } | |
21924 | unsigned long CPUFUNC(op_d060_4)(uint32_t opcode) /* ADD */ | |
21925 | { | |
21926 | uint32_t srcreg = (opcode & 7); | |
21927 | uint32_t dstreg = (opcode >> 9) & 7; | |
21928 | OpcodeFamily = 11; CurrentInstrCycles = 10; | |
21929 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
21930 | { int16_t src = m68k_read_memory_16(srca); | |
21931 | m68k_areg (regs, srcreg) = srca; | |
21932 | { int16_t dst = m68k_dreg(regs, dstreg); | |
21933 | { refill_prefetch (m68k_getpc(), 2); | |
21934 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
21935 | { int flgs = ((int16_t)(src)) < 0; | |
21936 | int flgo = ((int16_t)(dst)) < 0; | |
21937 | int flgn = ((int16_t)(newv)) < 0; | |
21938 | SET_ZFLG (((int16_t)(newv)) == 0); | |
21939 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
21940 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
21941 | COPY_CARRY; | |
21942 | SET_NFLG (flgn != 0); | |
21943 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
21944 | }}}}}}}m68k_incpc(2); | |
21945 | return 10; | |
21946 | } | |
21947 | unsigned long CPUFUNC(op_d068_4)(uint32_t opcode) /* ADD */ | |
21948 | { | |
21949 | uint32_t srcreg = (opcode & 7); | |
21950 | uint32_t dstreg = (opcode >> 9) & 7; | |
21951 | OpcodeFamily = 11; CurrentInstrCycles = 12; | |
21952 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
21953 | { int16_t src = m68k_read_memory_16(srca); | |
21954 | { int16_t dst = m68k_dreg(regs, dstreg); | |
21955 | { refill_prefetch (m68k_getpc(), 2); | |
21956 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
21957 | { int flgs = ((int16_t)(src)) < 0; | |
21958 | int flgo = ((int16_t)(dst)) < 0; | |
21959 | int flgn = ((int16_t)(newv)) < 0; | |
21960 | SET_ZFLG (((int16_t)(newv)) == 0); | |
21961 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
21962 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
21963 | COPY_CARRY; | |
21964 | SET_NFLG (flgn != 0); | |
21965 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
21966 | }}}}}}}m68k_incpc(4); | |
21967 | return 12; | |
21968 | } | |
21969 | unsigned long CPUFUNC(op_d070_4)(uint32_t opcode) /* ADD */ | |
21970 | { | |
21971 | uint32_t srcreg = (opcode & 7); | |
21972 | uint32_t dstreg = (opcode >> 9) & 7; | |
21973 | OpcodeFamily = 11; CurrentInstrCycles = 14; | |
21974 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
21975 | BusCyclePenalty += 2; | |
21976 | { int16_t src = m68k_read_memory_16(srca); | |
21977 | { int16_t dst = m68k_dreg(regs, dstreg); | |
21978 | { refill_prefetch (m68k_getpc(), 2); | |
21979 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
21980 | { int flgs = ((int16_t)(src)) < 0; | |
21981 | int flgo = ((int16_t)(dst)) < 0; | |
21982 | int flgn = ((int16_t)(newv)) < 0; | |
21983 | SET_ZFLG (((int16_t)(newv)) == 0); | |
21984 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
21985 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
21986 | COPY_CARRY; | |
21987 | SET_NFLG (flgn != 0); | |
21988 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
21989 | }}}}}}}m68k_incpc(4); | |
21990 | return 14; | |
21991 | } | |
21992 | unsigned long CPUFUNC(op_d078_4)(uint32_t opcode) /* ADD */ | |
21993 | { | |
21994 | uint32_t dstreg = (opcode >> 9) & 7; | |
21995 | OpcodeFamily = 11; CurrentInstrCycles = 12; | |
21996 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
21997 | { int16_t src = m68k_read_memory_16(srca); | |
21998 | { int16_t dst = m68k_dreg(regs, dstreg); | |
21999 | { refill_prefetch (m68k_getpc(), 2); | |
22000 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
22001 | { int flgs = ((int16_t)(src)) < 0; | |
22002 | int flgo = ((int16_t)(dst)) < 0; | |
22003 | int flgn = ((int16_t)(newv)) < 0; | |
22004 | SET_ZFLG (((int16_t)(newv)) == 0); | |
22005 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
22006 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
22007 | COPY_CARRY; | |
22008 | SET_NFLG (flgn != 0); | |
22009 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
22010 | }}}}}}}m68k_incpc(4); | |
22011 | return 12; | |
22012 | } | |
22013 | unsigned long CPUFUNC(op_d079_4)(uint32_t opcode) /* ADD */ | |
22014 | { | |
22015 | uint32_t dstreg = (opcode >> 9) & 7; | |
22016 | OpcodeFamily = 11; CurrentInstrCycles = 16; | |
22017 | {{ uint32_t srca = get_ilong(2); | |
22018 | { int16_t src = m68k_read_memory_16(srca); | |
22019 | { int16_t dst = m68k_dreg(regs, dstreg); | |
22020 | { refill_prefetch (m68k_getpc(), 2); | |
22021 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
22022 | { int flgs = ((int16_t)(src)) < 0; | |
22023 | int flgo = ((int16_t)(dst)) < 0; | |
22024 | int flgn = ((int16_t)(newv)) < 0; | |
22025 | SET_ZFLG (((int16_t)(newv)) == 0); | |
22026 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
22027 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
22028 | COPY_CARRY; | |
22029 | SET_NFLG (flgn != 0); | |
22030 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
22031 | }}}}}}}m68k_incpc(6); | |
22032 | return 16; | |
22033 | } | |
22034 | unsigned long CPUFUNC(op_d07a_4)(uint32_t opcode) /* ADD */ | |
22035 | { | |
22036 | uint32_t dstreg = (opcode >> 9) & 7; | |
22037 | OpcodeFamily = 11; CurrentInstrCycles = 12; | |
22038 | {{ uint32_t srca = m68k_getpc () + 2; | |
22039 | srca += (int32_t)(int16_t)get_iword(2); | |
22040 | { int16_t src = m68k_read_memory_16(srca); | |
22041 | { int16_t dst = m68k_dreg(regs, dstreg); | |
22042 | { refill_prefetch (m68k_getpc(), 2); | |
22043 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
22044 | { int flgs = ((int16_t)(src)) < 0; | |
22045 | int flgo = ((int16_t)(dst)) < 0; | |
22046 | int flgn = ((int16_t)(newv)) < 0; | |
22047 | SET_ZFLG (((int16_t)(newv)) == 0); | |
22048 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
22049 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
22050 | COPY_CARRY; | |
22051 | SET_NFLG (flgn != 0); | |
22052 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
22053 | }}}}}}}m68k_incpc(4); | |
22054 | return 12; | |
22055 | } | |
22056 | unsigned long CPUFUNC(op_d07b_4)(uint32_t opcode) /* ADD */ | |
22057 | { | |
22058 | uint32_t dstreg = (opcode >> 9) & 7; | |
22059 | OpcodeFamily = 11; CurrentInstrCycles = 14; | |
22060 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
22061 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
22062 | BusCyclePenalty += 2; | |
22063 | { int16_t src = m68k_read_memory_16(srca); | |
22064 | { int16_t dst = m68k_dreg(regs, dstreg); | |
22065 | { refill_prefetch (m68k_getpc(), 2); | |
22066 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
22067 | { int flgs = ((int16_t)(src)) < 0; | |
22068 | int flgo = ((int16_t)(dst)) < 0; | |
22069 | int flgn = ((int16_t)(newv)) < 0; | |
22070 | SET_ZFLG (((int16_t)(newv)) == 0); | |
22071 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
22072 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
22073 | COPY_CARRY; | |
22074 | SET_NFLG (flgn != 0); | |
22075 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
22076 | }}}}}}}m68k_incpc(4); | |
22077 | return 14; | |
22078 | } | |
22079 | unsigned long CPUFUNC(op_d07c_4)(uint32_t opcode) /* ADD */ | |
22080 | { | |
22081 | uint32_t dstreg = (opcode >> 9) & 7; | |
22082 | OpcodeFamily = 11; CurrentInstrCycles = 8; | |
22083 | {{ int16_t src = get_iword(2); | |
22084 | { int16_t dst = m68k_dreg(regs, dstreg); | |
22085 | { refill_prefetch (m68k_getpc(), 2); | |
22086 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
22087 | { int flgs = ((int16_t)(src)) < 0; | |
22088 | int flgo = ((int16_t)(dst)) < 0; | |
22089 | int flgn = ((int16_t)(newv)) < 0; | |
22090 | SET_ZFLG (((int16_t)(newv)) == 0); | |
22091 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
22092 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
22093 | COPY_CARRY; | |
22094 | SET_NFLG (flgn != 0); | |
22095 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
22096 | }}}}}}m68k_incpc(4); | |
22097 | return 8; | |
22098 | } | |
22099 | unsigned long CPUFUNC(op_d080_4)(uint32_t opcode) /* ADD */ | |
22100 | { | |
22101 | uint32_t srcreg = (opcode & 7); | |
22102 | uint32_t dstreg = (opcode >> 9) & 7; | |
22103 | OpcodeFamily = 11; CurrentInstrCycles = 8; | |
22104 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
22105 | { int32_t dst = m68k_dreg(regs, dstreg); | |
22106 | { refill_prefetch (m68k_getpc(), 2); | |
22107 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
22108 | { int flgs = ((int32_t)(src)) < 0; | |
22109 | int flgo = ((int32_t)(dst)) < 0; | |
22110 | int flgn = ((int32_t)(newv)) < 0; | |
22111 | SET_ZFLG (((int32_t)(newv)) == 0); | |
22112 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
22113 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
22114 | COPY_CARRY; | |
22115 | SET_NFLG (flgn != 0); | |
22116 | m68k_dreg(regs, dstreg) = (newv); | |
22117 | }}}}}}m68k_incpc(2); | |
22118 | return 8; | |
22119 | } | |
22120 | unsigned long CPUFUNC(op_d088_4)(uint32_t opcode) /* ADD */ | |
22121 | { | |
22122 | uint32_t srcreg = (opcode & 7); | |
22123 | uint32_t dstreg = (opcode >> 9) & 7; | |
22124 | OpcodeFamily = 11; CurrentInstrCycles = 8; | |
22125 | {{ int32_t src = m68k_areg(regs, srcreg); | |
22126 | { int32_t dst = m68k_dreg(regs, dstreg); | |
22127 | { refill_prefetch (m68k_getpc(), 2); | |
22128 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
22129 | { int flgs = ((int32_t)(src)) < 0; | |
22130 | int flgo = ((int32_t)(dst)) < 0; | |
22131 | int flgn = ((int32_t)(newv)) < 0; | |
22132 | SET_ZFLG (((int32_t)(newv)) == 0); | |
22133 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
22134 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
22135 | COPY_CARRY; | |
22136 | SET_NFLG (flgn != 0); | |
22137 | m68k_dreg(regs, dstreg) = (newv); | |
22138 | }}}}}}m68k_incpc(2); | |
22139 | return 8; | |
22140 | } | |
22141 | unsigned long CPUFUNC(op_d090_4)(uint32_t opcode) /* ADD */ | |
22142 | { | |
22143 | uint32_t srcreg = (opcode & 7); | |
22144 | uint32_t dstreg = (opcode >> 9) & 7; | |
22145 | OpcodeFamily = 11; CurrentInstrCycles = 14; | |
22146 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
22147 | { int32_t src = m68k_read_memory_32(srca); | |
22148 | { int32_t dst = m68k_dreg(regs, dstreg); | |
22149 | { refill_prefetch (m68k_getpc(), 2); | |
22150 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
22151 | { int flgs = ((int32_t)(src)) < 0; | |
22152 | int flgo = ((int32_t)(dst)) < 0; | |
22153 | int flgn = ((int32_t)(newv)) < 0; | |
22154 | SET_ZFLG (((int32_t)(newv)) == 0); | |
22155 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
22156 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
22157 | COPY_CARRY; | |
22158 | SET_NFLG (flgn != 0); | |
22159 | m68k_dreg(regs, dstreg) = (newv); | |
22160 | }}}}}}}m68k_incpc(2); | |
22161 | return 14; | |
22162 | } | |
22163 | unsigned long CPUFUNC(op_d098_4)(uint32_t opcode) /* ADD */ | |
22164 | { | |
22165 | uint32_t srcreg = (opcode & 7); | |
22166 | uint32_t dstreg = (opcode >> 9) & 7; | |
22167 | OpcodeFamily = 11; CurrentInstrCycles = 14; | |
22168 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
22169 | { int32_t src = m68k_read_memory_32(srca); | |
22170 | m68k_areg(regs, srcreg) += 4; | |
22171 | { int32_t dst = m68k_dreg(regs, dstreg); | |
22172 | { refill_prefetch (m68k_getpc(), 2); | |
22173 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
22174 | { int flgs = ((int32_t)(src)) < 0; | |
22175 | int flgo = ((int32_t)(dst)) < 0; | |
22176 | int flgn = ((int32_t)(newv)) < 0; | |
22177 | SET_ZFLG (((int32_t)(newv)) == 0); | |
22178 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
22179 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
22180 | COPY_CARRY; | |
22181 | SET_NFLG (flgn != 0); | |
22182 | m68k_dreg(regs, dstreg) = (newv); | |
22183 | }}}}}}}m68k_incpc(2); | |
22184 | return 14; | |
22185 | } | |
22186 | unsigned long CPUFUNC(op_d0a0_4)(uint32_t opcode) /* ADD */ | |
22187 | { | |
22188 | uint32_t srcreg = (opcode & 7); | |
22189 | uint32_t dstreg = (opcode >> 9) & 7; | |
22190 | OpcodeFamily = 11; CurrentInstrCycles = 16; | |
22191 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 4; | |
22192 | { int32_t src = m68k_read_memory_32(srca); | |
22193 | m68k_areg (regs, srcreg) = srca; | |
22194 | { int32_t dst = m68k_dreg(regs, dstreg); | |
22195 | { refill_prefetch (m68k_getpc(), 2); | |
22196 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
22197 | { int flgs = ((int32_t)(src)) < 0; | |
22198 | int flgo = ((int32_t)(dst)) < 0; | |
22199 | int flgn = ((int32_t)(newv)) < 0; | |
22200 | SET_ZFLG (((int32_t)(newv)) == 0); | |
22201 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
22202 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
22203 | COPY_CARRY; | |
22204 | SET_NFLG (flgn != 0); | |
22205 | m68k_dreg(regs, dstreg) = (newv); | |
22206 | }}}}}}}m68k_incpc(2); | |
22207 | return 16; | |
22208 | } | |
22209 | unsigned long CPUFUNC(op_d0a8_4)(uint32_t opcode) /* ADD */ | |
22210 | { | |
22211 | uint32_t srcreg = (opcode & 7); | |
22212 | uint32_t dstreg = (opcode >> 9) & 7; | |
22213 | OpcodeFamily = 11; CurrentInstrCycles = 18; | |
22214 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
22215 | { int32_t src = m68k_read_memory_32(srca); | |
22216 | { int32_t dst = m68k_dreg(regs, dstreg); | |
22217 | { refill_prefetch (m68k_getpc(), 2); | |
22218 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
22219 | { int flgs = ((int32_t)(src)) < 0; | |
22220 | int flgo = ((int32_t)(dst)) < 0; | |
22221 | int flgn = ((int32_t)(newv)) < 0; | |
22222 | SET_ZFLG (((int32_t)(newv)) == 0); | |
22223 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
22224 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
22225 | COPY_CARRY; | |
22226 | SET_NFLG (flgn != 0); | |
22227 | m68k_dreg(regs, dstreg) = (newv); | |
22228 | }}}}}}}m68k_incpc(4); | |
22229 | return 18; | |
22230 | } | |
22231 | unsigned long CPUFUNC(op_d0b0_4)(uint32_t opcode) /* ADD */ | |
22232 | { | |
22233 | uint32_t srcreg = (opcode & 7); | |
22234 | uint32_t dstreg = (opcode >> 9) & 7; | |
22235 | OpcodeFamily = 11; CurrentInstrCycles = 20; | |
22236 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
22237 | BusCyclePenalty += 2; | |
22238 | { int32_t src = m68k_read_memory_32(srca); | |
22239 | { int32_t dst = m68k_dreg(regs, dstreg); | |
22240 | { refill_prefetch (m68k_getpc(), 2); | |
22241 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
22242 | { int flgs = ((int32_t)(src)) < 0; | |
22243 | int flgo = ((int32_t)(dst)) < 0; | |
22244 | int flgn = ((int32_t)(newv)) < 0; | |
22245 | SET_ZFLG (((int32_t)(newv)) == 0); | |
22246 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
22247 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
22248 | COPY_CARRY; | |
22249 | SET_NFLG (flgn != 0); | |
22250 | m68k_dreg(regs, dstreg) = (newv); | |
22251 | }}}}}}}m68k_incpc(4); | |
22252 | return 20; | |
22253 | } | |
22254 | unsigned long CPUFUNC(op_d0b8_4)(uint32_t opcode) /* ADD */ | |
22255 | { | |
22256 | uint32_t dstreg = (opcode >> 9) & 7; | |
22257 | OpcodeFamily = 11; CurrentInstrCycles = 18; | |
22258 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
22259 | { int32_t src = m68k_read_memory_32(srca); | |
22260 | { int32_t dst = m68k_dreg(regs, dstreg); | |
22261 | { refill_prefetch (m68k_getpc(), 2); | |
22262 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
22263 | { int flgs = ((int32_t)(src)) < 0; | |
22264 | int flgo = ((int32_t)(dst)) < 0; | |
22265 | int flgn = ((int32_t)(newv)) < 0; | |
22266 | SET_ZFLG (((int32_t)(newv)) == 0); | |
22267 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
22268 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
22269 | COPY_CARRY; | |
22270 | SET_NFLG (flgn != 0); | |
22271 | m68k_dreg(regs, dstreg) = (newv); | |
22272 | }}}}}}}m68k_incpc(4); | |
22273 | return 18; | |
22274 | } | |
22275 | unsigned long CPUFUNC(op_d0b9_4)(uint32_t opcode) /* ADD */ | |
22276 | { | |
22277 | uint32_t dstreg = (opcode >> 9) & 7; | |
22278 | OpcodeFamily = 11; CurrentInstrCycles = 22; | |
22279 | {{ uint32_t srca = get_ilong(2); | |
22280 | { int32_t src = m68k_read_memory_32(srca); | |
22281 | { int32_t dst = m68k_dreg(regs, dstreg); | |
22282 | { refill_prefetch (m68k_getpc(), 2); | |
22283 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
22284 | { int flgs = ((int32_t)(src)) < 0; | |
22285 | int flgo = ((int32_t)(dst)) < 0; | |
22286 | int flgn = ((int32_t)(newv)) < 0; | |
22287 | SET_ZFLG (((int32_t)(newv)) == 0); | |
22288 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
22289 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
22290 | COPY_CARRY; | |
22291 | SET_NFLG (flgn != 0); | |
22292 | m68k_dreg(regs, dstreg) = (newv); | |
22293 | }}}}}}}m68k_incpc(6); | |
22294 | return 22; | |
22295 | } | |
22296 | unsigned long CPUFUNC(op_d0ba_4)(uint32_t opcode) /* ADD */ | |
22297 | { | |
22298 | uint32_t dstreg = (opcode >> 9) & 7; | |
22299 | OpcodeFamily = 11; CurrentInstrCycles = 18; | |
22300 | {{ uint32_t srca = m68k_getpc () + 2; | |
22301 | srca += (int32_t)(int16_t)get_iword(2); | |
22302 | { int32_t src = m68k_read_memory_32(srca); | |
22303 | { int32_t dst = m68k_dreg(regs, dstreg); | |
22304 | { refill_prefetch (m68k_getpc(), 2); | |
22305 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
22306 | { int flgs = ((int32_t)(src)) < 0; | |
22307 | int flgo = ((int32_t)(dst)) < 0; | |
22308 | int flgn = ((int32_t)(newv)) < 0; | |
22309 | SET_ZFLG (((int32_t)(newv)) == 0); | |
22310 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
22311 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
22312 | COPY_CARRY; | |
22313 | SET_NFLG (flgn != 0); | |
22314 | m68k_dreg(regs, dstreg) = (newv); | |
22315 | }}}}}}}m68k_incpc(4); | |
22316 | return 18; | |
22317 | } | |
22318 | unsigned long CPUFUNC(op_d0bb_4)(uint32_t opcode) /* ADD */ | |
22319 | { | |
22320 | uint32_t dstreg = (opcode >> 9) & 7; | |
22321 | OpcodeFamily = 11; CurrentInstrCycles = 20; | |
22322 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
22323 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
22324 | BusCyclePenalty += 2; | |
22325 | { int32_t src = m68k_read_memory_32(srca); | |
22326 | { int32_t dst = m68k_dreg(regs, dstreg); | |
22327 | { refill_prefetch (m68k_getpc(), 2); | |
22328 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
22329 | { int flgs = ((int32_t)(src)) < 0; | |
22330 | int flgo = ((int32_t)(dst)) < 0; | |
22331 | int flgn = ((int32_t)(newv)) < 0; | |
22332 | SET_ZFLG (((int32_t)(newv)) == 0); | |
22333 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
22334 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
22335 | COPY_CARRY; | |
22336 | SET_NFLG (flgn != 0); | |
22337 | m68k_dreg(regs, dstreg) = (newv); | |
22338 | }}}}}}}m68k_incpc(4); | |
22339 | return 20; | |
22340 | } | |
22341 | unsigned long CPUFUNC(op_d0bc_4)(uint32_t opcode) /* ADD */ | |
22342 | { | |
22343 | uint32_t dstreg = (opcode >> 9) & 7; | |
22344 | OpcodeFamily = 11; CurrentInstrCycles = 16; | |
22345 | {{ int32_t src = get_ilong(2); | |
22346 | { int32_t dst = m68k_dreg(regs, dstreg); | |
22347 | { refill_prefetch (m68k_getpc(), 2); | |
22348 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
22349 | { int flgs = ((int32_t)(src)) < 0; | |
22350 | int flgo = ((int32_t)(dst)) < 0; | |
22351 | int flgn = ((int32_t)(newv)) < 0; | |
22352 | SET_ZFLG (((int32_t)(newv)) == 0); | |
22353 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
22354 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
22355 | COPY_CARRY; | |
22356 | SET_NFLG (flgn != 0); | |
22357 | m68k_dreg(regs, dstreg) = (newv); | |
22358 | }}}}}}m68k_incpc(6); | |
22359 | return 16; | |
22360 | } | |
22361 | unsigned long CPUFUNC(op_d0c0_4)(uint32_t opcode) /* ADDA */ | |
22362 | { | |
22363 | uint32_t srcreg = (opcode & 7); | |
22364 | uint32_t dstreg = (opcode >> 9) & 7; | |
22365 | OpcodeFamily = 12; CurrentInstrCycles = 8; | |
22366 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
22367 | { int32_t dst = m68k_areg(regs, dstreg); | |
22368 | { uint32_t newv = dst + src; | |
22369 | m68k_areg(regs, dstreg) = (newv); | |
22370 | }}}}m68k_incpc(2); | |
22371 | return 8; | |
22372 | } | |
22373 | unsigned long CPUFUNC(op_d0c8_4)(uint32_t opcode) /* ADDA */ | |
22374 | { | |
22375 | uint32_t srcreg = (opcode & 7); | |
22376 | uint32_t dstreg = (opcode >> 9) & 7; | |
22377 | OpcodeFamily = 12; CurrentInstrCycles = 8; | |
22378 | {{ int16_t src = m68k_areg(regs, srcreg); | |
22379 | { int32_t dst = m68k_areg(regs, dstreg); | |
22380 | { uint32_t newv = dst + src; | |
22381 | m68k_areg(regs, dstreg) = (newv); | |
22382 | }}}}m68k_incpc(2); | |
22383 | return 8; | |
22384 | } | |
22385 | unsigned long CPUFUNC(op_d0d0_4)(uint32_t opcode) /* ADDA */ | |
22386 | { | |
22387 | uint32_t srcreg = (opcode & 7); | |
22388 | uint32_t dstreg = (opcode >> 9) & 7; | |
22389 | OpcodeFamily = 12; CurrentInstrCycles = 12; | |
22390 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
22391 | { int16_t src = m68k_read_memory_16(srca); | |
22392 | { int32_t dst = m68k_areg(regs, dstreg); | |
22393 | { uint32_t newv = dst + src; | |
22394 | m68k_areg(regs, dstreg) = (newv); | |
22395 | }}}}}m68k_incpc(2); | |
22396 | return 12; | |
22397 | } | |
22398 | unsigned long CPUFUNC(op_d0d8_4)(uint32_t opcode) /* ADDA */ | |
22399 | { | |
22400 | uint32_t srcreg = (opcode & 7); | |
22401 | uint32_t dstreg = (opcode >> 9) & 7; | |
22402 | OpcodeFamily = 12; CurrentInstrCycles = 12; | |
22403 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
22404 | { int16_t src = m68k_read_memory_16(srca); | |
22405 | m68k_areg(regs, srcreg) += 2; | |
22406 | { int32_t dst = m68k_areg(regs, dstreg); | |
22407 | { uint32_t newv = dst + src; | |
22408 | m68k_areg(regs, dstreg) = (newv); | |
22409 | }}}}}m68k_incpc(2); | |
22410 | return 12; | |
22411 | } | |
22412 | unsigned long CPUFUNC(op_d0e0_4)(uint32_t opcode) /* ADDA */ | |
22413 | { | |
22414 | uint32_t srcreg = (opcode & 7); | |
22415 | uint32_t dstreg = (opcode >> 9) & 7; | |
22416 | OpcodeFamily = 12; CurrentInstrCycles = 14; | |
22417 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
22418 | { int16_t src = m68k_read_memory_16(srca); | |
22419 | m68k_areg (regs, srcreg) = srca; | |
22420 | { int32_t dst = m68k_areg(regs, dstreg); | |
22421 | { uint32_t newv = dst + src; | |
22422 | m68k_areg(regs, dstreg) = (newv); | |
22423 | }}}}}m68k_incpc(2); | |
22424 | return 14; | |
22425 | } | |
22426 | unsigned long CPUFUNC(op_d0e8_4)(uint32_t opcode) /* ADDA */ | |
22427 | { | |
22428 | uint32_t srcreg = (opcode & 7); | |
22429 | uint32_t dstreg = (opcode >> 9) & 7; | |
22430 | OpcodeFamily = 12; CurrentInstrCycles = 16; | |
22431 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
22432 | { int16_t src = m68k_read_memory_16(srca); | |
22433 | { int32_t dst = m68k_areg(regs, dstreg); | |
22434 | { uint32_t newv = dst + src; | |
22435 | m68k_areg(regs, dstreg) = (newv); | |
22436 | }}}}}m68k_incpc(4); | |
22437 | return 16; | |
22438 | } | |
22439 | unsigned long CPUFUNC(op_d0f0_4)(uint32_t opcode) /* ADDA */ | |
22440 | { | |
22441 | uint32_t srcreg = (opcode & 7); | |
22442 | uint32_t dstreg = (opcode >> 9) & 7; | |
22443 | OpcodeFamily = 12; CurrentInstrCycles = 18; | |
22444 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
22445 | BusCyclePenalty += 2; | |
22446 | { int16_t src = m68k_read_memory_16(srca); | |
22447 | { int32_t dst = m68k_areg(regs, dstreg); | |
22448 | { uint32_t newv = dst + src; | |
22449 | m68k_areg(regs, dstreg) = (newv); | |
22450 | }}}}}m68k_incpc(4); | |
22451 | return 18; | |
22452 | } | |
22453 | unsigned long CPUFUNC(op_d0f8_4)(uint32_t opcode) /* ADDA */ | |
22454 | { | |
22455 | uint32_t dstreg = (opcode >> 9) & 7; | |
22456 | OpcodeFamily = 12; CurrentInstrCycles = 16; | |
22457 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
22458 | { int16_t src = m68k_read_memory_16(srca); | |
22459 | { int32_t dst = m68k_areg(regs, dstreg); | |
22460 | { uint32_t newv = dst + src; | |
22461 | m68k_areg(regs, dstreg) = (newv); | |
22462 | }}}}}m68k_incpc(4); | |
22463 | return 16; | |
22464 | } | |
22465 | unsigned long CPUFUNC(op_d0f9_4)(uint32_t opcode) /* ADDA */ | |
22466 | { | |
22467 | uint32_t dstreg = (opcode >> 9) & 7; | |
22468 | OpcodeFamily = 12; CurrentInstrCycles = 20; | |
22469 | {{ uint32_t srca = get_ilong(2); | |
22470 | { int16_t src = m68k_read_memory_16(srca); | |
22471 | { int32_t dst = m68k_areg(regs, dstreg); | |
22472 | { uint32_t newv = dst + src; | |
22473 | m68k_areg(regs, dstreg) = (newv); | |
22474 | }}}}}m68k_incpc(6); | |
22475 | return 20; | |
22476 | } | |
22477 | unsigned long CPUFUNC(op_d0fa_4)(uint32_t opcode) /* ADDA */ | |
22478 | { | |
22479 | uint32_t dstreg = (opcode >> 9) & 7; | |
22480 | OpcodeFamily = 12; CurrentInstrCycles = 16; | |
22481 | {{ uint32_t srca = m68k_getpc () + 2; | |
22482 | srca += (int32_t)(int16_t)get_iword(2); | |
22483 | { int16_t src = m68k_read_memory_16(srca); | |
22484 | { int32_t dst = m68k_areg(regs, dstreg); | |
22485 | { uint32_t newv = dst + src; | |
22486 | m68k_areg(regs, dstreg) = (newv); | |
22487 | }}}}}m68k_incpc(4); | |
22488 | return 16; | |
22489 | } | |
22490 | unsigned long CPUFUNC(op_d0fb_4)(uint32_t opcode) /* ADDA */ | |
22491 | { | |
22492 | uint32_t dstreg = (opcode >> 9) & 7; | |
22493 | OpcodeFamily = 12; CurrentInstrCycles = 18; | |
22494 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
22495 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
22496 | BusCyclePenalty += 2; | |
22497 | { int16_t src = m68k_read_memory_16(srca); | |
22498 | { int32_t dst = m68k_areg(regs, dstreg); | |
22499 | { uint32_t newv = dst + src; | |
22500 | m68k_areg(regs, dstreg) = (newv); | |
22501 | }}}}}m68k_incpc(4); | |
22502 | return 18; | |
22503 | } | |
22504 | unsigned long CPUFUNC(op_d0fc_4)(uint32_t opcode) /* ADDA */ | |
22505 | { | |
22506 | uint32_t dstreg = (opcode >> 9) & 7; | |
22507 | OpcodeFamily = 12; CurrentInstrCycles = 12; | |
22508 | {{ int16_t src = get_iword(2); | |
22509 | { int32_t dst = m68k_areg(regs, dstreg); | |
22510 | { uint32_t newv = dst + src; | |
22511 | m68k_areg(regs, dstreg) = (newv); | |
22512 | }}}}m68k_incpc(4); | |
22513 | return 12; | |
22514 | } | |
22515 | unsigned long CPUFUNC(op_d100_4)(uint32_t opcode) /* ADDX */ | |
22516 | { | |
22517 | uint32_t srcreg = (opcode & 7); | |
22518 | uint32_t dstreg = (opcode >> 9) & 7; | |
22519 | OpcodeFamily = 13; CurrentInstrCycles = 4; | |
22520 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
22521 | { int8_t dst = m68k_dreg(regs, dstreg); | |
22522 | { uint32_t newv = dst + src + (GET_XFLG ? 1 : 0); | |
22523 | { int flgs = ((int8_t)(src)) < 0; | |
22524 | int flgo = ((int8_t)(dst)) < 0; | |
22525 | int flgn = ((int8_t)(newv)) < 0; | |
22526 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
22527 | SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn))); | |
22528 | COPY_CARRY; | |
22529 | SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); | |
22530 | SET_NFLG (((int8_t)(newv)) < 0); | |
22531 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
22532 | }}}}}m68k_incpc(2); | |
22533 | return 4; | |
22534 | } | |
22535 | unsigned long CPUFUNC(op_d108_4)(uint32_t opcode) /* ADDX */ | |
22536 | { | |
22537 | uint32_t srcreg = (opcode & 7); | |
22538 | uint32_t dstreg = (opcode >> 9) & 7; | |
22539 | OpcodeFamily = 13; CurrentInstrCycles = 18; | |
22540 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
22541 | { int8_t src = m68k_read_memory_8(srca); | |
22542 | m68k_areg (regs, srcreg) = srca; | |
22543 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
22544 | { int8_t dst = m68k_read_memory_8(dsta); | |
22545 | m68k_areg (regs, dstreg) = dsta; | |
22546 | { uint32_t newv = dst + src + (GET_XFLG ? 1 : 0); | |
22547 | { int flgs = ((int8_t)(src)) < 0; | |
22548 | int flgo = ((int8_t)(dst)) < 0; | |
22549 | int flgn = ((int8_t)(newv)) < 0; | |
22550 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
22551 | SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn))); | |
22552 | COPY_CARRY; | |
22553 | SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); | |
22554 | SET_NFLG (((int8_t)(newv)) < 0); | |
22555 | m68k_write_memory_8(dsta,newv); | |
22556 | }}}}}}}m68k_incpc(2); | |
22557 | return 18; | |
22558 | } | |
22559 | unsigned long CPUFUNC(op_d110_4)(uint32_t opcode) /* ADD */ | |
22560 | { | |
22561 | uint32_t srcreg = ((opcode >> 9) & 7); | |
22562 | uint32_t dstreg = opcode & 7; | |
22563 | OpcodeFamily = 11; CurrentInstrCycles = 12; | |
22564 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
22565 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
22566 | { int8_t dst = m68k_read_memory_8(dsta); | |
22567 | { refill_prefetch (m68k_getpc(), 2); | |
22568 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
22569 | { int flgs = ((int8_t)(src)) < 0; | |
22570 | int flgo = ((int8_t)(dst)) < 0; | |
22571 | int flgn = ((int8_t)(newv)) < 0; | |
22572 | SET_ZFLG (((int8_t)(newv)) == 0); | |
22573 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
22574 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
22575 | COPY_CARRY; | |
22576 | SET_NFLG (flgn != 0); | |
22577 | m68k_write_memory_8(dsta,newv); | |
22578 | }}}}}}}m68k_incpc(2); | |
22579 | return 12; | |
22580 | } | |
22581 | unsigned long CPUFUNC(op_d118_4)(uint32_t opcode) /* ADD */ | |
22582 | { | |
22583 | uint32_t srcreg = ((opcode >> 9) & 7); | |
22584 | uint32_t dstreg = opcode & 7; | |
22585 | OpcodeFamily = 11; CurrentInstrCycles = 12; | |
22586 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
22587 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
22588 | { int8_t dst = m68k_read_memory_8(dsta); | |
22589 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
22590 | { refill_prefetch (m68k_getpc(), 2); | |
22591 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
22592 | { int flgs = ((int8_t)(src)) < 0; | |
22593 | int flgo = ((int8_t)(dst)) < 0; | |
22594 | int flgn = ((int8_t)(newv)) < 0; | |
22595 | SET_ZFLG (((int8_t)(newv)) == 0); | |
22596 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
22597 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
22598 | COPY_CARRY; | |
22599 | SET_NFLG (flgn != 0); | |
22600 | m68k_write_memory_8(dsta,newv); | |
22601 | }}}}}}}m68k_incpc(2); | |
22602 | return 12; | |
22603 | } | |
22604 | unsigned long CPUFUNC(op_d120_4)(uint32_t opcode) /* ADD */ | |
22605 | { | |
22606 | uint32_t srcreg = ((opcode >> 9) & 7); | |
22607 | uint32_t dstreg = opcode & 7; | |
22608 | OpcodeFamily = 11; CurrentInstrCycles = 14; | |
22609 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
22610 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
22611 | { int8_t dst = m68k_read_memory_8(dsta); | |
22612 | m68k_areg (regs, dstreg) = dsta; | |
22613 | { refill_prefetch (m68k_getpc(), 2); | |
22614 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
22615 | { int flgs = ((int8_t)(src)) < 0; | |
22616 | int flgo = ((int8_t)(dst)) < 0; | |
22617 | int flgn = ((int8_t)(newv)) < 0; | |
22618 | SET_ZFLG (((int8_t)(newv)) == 0); | |
22619 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
22620 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
22621 | COPY_CARRY; | |
22622 | SET_NFLG (flgn != 0); | |
22623 | m68k_write_memory_8(dsta,newv); | |
22624 | }}}}}}}m68k_incpc(2); | |
22625 | return 14; | |
22626 | } | |
22627 | unsigned long CPUFUNC(op_d128_4)(uint32_t opcode) /* ADD */ | |
22628 | { | |
22629 | uint32_t srcreg = ((opcode >> 9) & 7); | |
22630 | uint32_t dstreg = opcode & 7; | |
22631 | OpcodeFamily = 11; CurrentInstrCycles = 16; | |
22632 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
22633 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); | |
22634 | { int8_t dst = m68k_read_memory_8(dsta); | |
22635 | { refill_prefetch (m68k_getpc(), 2); | |
22636 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
22637 | { int flgs = ((int8_t)(src)) < 0; | |
22638 | int flgo = ((int8_t)(dst)) < 0; | |
22639 | int flgn = ((int8_t)(newv)) < 0; | |
22640 | SET_ZFLG (((int8_t)(newv)) == 0); | |
22641 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
22642 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
22643 | COPY_CARRY; | |
22644 | SET_NFLG (flgn != 0); | |
22645 | m68k_write_memory_8(dsta,newv); | |
22646 | }}}}}}}m68k_incpc(4); | |
22647 | return 16; | |
22648 | } | |
22649 | unsigned long CPUFUNC(op_d130_4)(uint32_t opcode) /* ADD */ | |
22650 | { | |
22651 | uint32_t srcreg = ((opcode >> 9) & 7); | |
22652 | uint32_t dstreg = opcode & 7; | |
22653 | OpcodeFamily = 11; CurrentInstrCycles = 18; | |
22654 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
22655 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); | |
22656 | BusCyclePenalty += 2; | |
22657 | { int8_t dst = m68k_read_memory_8(dsta); | |
22658 | { refill_prefetch (m68k_getpc(), 2); | |
22659 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
22660 | { int flgs = ((int8_t)(src)) < 0; | |
22661 | int flgo = ((int8_t)(dst)) < 0; | |
22662 | int flgn = ((int8_t)(newv)) < 0; | |
22663 | SET_ZFLG (((int8_t)(newv)) == 0); | |
22664 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
22665 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
22666 | COPY_CARRY; | |
22667 | SET_NFLG (flgn != 0); | |
22668 | m68k_write_memory_8(dsta,newv); | |
22669 | }}}}}}}m68k_incpc(4); | |
22670 | return 18; | |
22671 | } | |
22672 | unsigned long CPUFUNC(op_d138_4)(uint32_t opcode) /* ADD */ | |
22673 | { | |
22674 | uint32_t srcreg = ((opcode >> 9) & 7); | |
22675 | OpcodeFamily = 11; CurrentInstrCycles = 16; | |
22676 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
22677 | { uint32_t dsta = (int32_t)(int16_t)get_iword(2); | |
22678 | { int8_t dst = m68k_read_memory_8(dsta); | |
22679 | { refill_prefetch (m68k_getpc(), 2); | |
22680 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
22681 | { int flgs = ((int8_t)(src)) < 0; | |
22682 | int flgo = ((int8_t)(dst)) < 0; | |
22683 | int flgn = ((int8_t)(newv)) < 0; | |
22684 | SET_ZFLG (((int8_t)(newv)) == 0); | |
22685 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
22686 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
22687 | COPY_CARRY; | |
22688 | SET_NFLG (flgn != 0); | |
22689 | m68k_write_memory_8(dsta,newv); | |
22690 | }}}}}}}m68k_incpc(4); | |
22691 | return 16; | |
22692 | } | |
22693 | unsigned long CPUFUNC(op_d139_4)(uint32_t opcode) /* ADD */ | |
22694 | { | |
22695 | uint32_t srcreg = ((opcode >> 9) & 7); | |
22696 | OpcodeFamily = 11; CurrentInstrCycles = 20; | |
22697 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
22698 | { uint32_t dsta = get_ilong(2); | |
22699 | { int8_t dst = m68k_read_memory_8(dsta); | |
22700 | { refill_prefetch (m68k_getpc(), 2); | |
22701 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
22702 | { int flgs = ((int8_t)(src)) < 0; | |
22703 | int flgo = ((int8_t)(dst)) < 0; | |
22704 | int flgn = ((int8_t)(newv)) < 0; | |
22705 | SET_ZFLG (((int8_t)(newv)) == 0); | |
22706 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
22707 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
22708 | COPY_CARRY; | |
22709 | SET_NFLG (flgn != 0); | |
22710 | m68k_write_memory_8(dsta,newv); | |
22711 | }}}}}}}m68k_incpc(6); | |
22712 | return 20; | |
22713 | } | |
22714 | unsigned long CPUFUNC(op_d140_4)(uint32_t opcode) /* ADDX */ | |
22715 | { | |
22716 | uint32_t srcreg = (opcode & 7); | |
22717 | uint32_t dstreg = (opcode >> 9) & 7; | |
22718 | OpcodeFamily = 13; CurrentInstrCycles = 4; | |
22719 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
22720 | { int16_t dst = m68k_dreg(regs, dstreg); | |
22721 | { uint32_t newv = dst + src + (GET_XFLG ? 1 : 0); | |
22722 | { int flgs = ((int16_t)(src)) < 0; | |
22723 | int flgo = ((int16_t)(dst)) < 0; | |
22724 | int flgn = ((int16_t)(newv)) < 0; | |
22725 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
22726 | SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn))); | |
22727 | COPY_CARRY; | |
22728 | SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0)); | |
22729 | SET_NFLG (((int16_t)(newv)) < 0); | |
22730 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
22731 | }}}}}m68k_incpc(2); | |
22732 | return 4; | |
22733 | } | |
22734 | unsigned long CPUFUNC(op_d148_4)(uint32_t opcode) /* ADDX */ | |
22735 | { | |
22736 | uint32_t srcreg = (opcode & 7); | |
22737 | uint32_t dstreg = (opcode >> 9) & 7; | |
22738 | OpcodeFamily = 13; CurrentInstrCycles = 18; | |
22739 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
22740 | { int16_t src = m68k_read_memory_16(srca); | |
22741 | m68k_areg (regs, srcreg) = srca; | |
22742 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
22743 | { int16_t dst = m68k_read_memory_16(dsta); | |
22744 | m68k_areg (regs, dstreg) = dsta; | |
22745 | { uint32_t newv = dst + src + (GET_XFLG ? 1 : 0); | |
22746 | { int flgs = ((int16_t)(src)) < 0; | |
22747 | int flgo = ((int16_t)(dst)) < 0; | |
22748 | int flgn = ((int16_t)(newv)) < 0; | |
22749 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
22750 | SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn))); | |
22751 | COPY_CARRY; | |
22752 | SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0)); | |
22753 | SET_NFLG (((int16_t)(newv)) < 0); | |
22754 | m68k_write_memory_16(dsta,newv); | |
22755 | }}}}}}}m68k_incpc(2); | |
22756 | return 18; | |
22757 | } | |
22758 | unsigned long CPUFUNC(op_d150_4)(uint32_t opcode) /* ADD */ | |
22759 | { | |
22760 | uint32_t srcreg = ((opcode >> 9) & 7); | |
22761 | uint32_t dstreg = opcode & 7; | |
22762 | OpcodeFamily = 11; CurrentInstrCycles = 12; | |
22763 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
22764 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
22765 | { int16_t dst = m68k_read_memory_16(dsta); | |
22766 | { refill_prefetch (m68k_getpc(), 2); | |
22767 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
22768 | { int flgs = ((int16_t)(src)) < 0; | |
22769 | int flgo = ((int16_t)(dst)) < 0; | |
22770 | int flgn = ((int16_t)(newv)) < 0; | |
22771 | SET_ZFLG (((int16_t)(newv)) == 0); | |
22772 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
22773 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
22774 | COPY_CARRY; | |
22775 | SET_NFLG (flgn != 0); | |
22776 | m68k_write_memory_16(dsta,newv); | |
22777 | }}}}}}}m68k_incpc(2); | |
22778 | return 12; | |
22779 | } | |
22780 | unsigned long CPUFUNC(op_d158_4)(uint32_t opcode) /* ADD */ | |
22781 | { | |
22782 | uint32_t srcreg = ((opcode >> 9) & 7); | |
22783 | uint32_t dstreg = opcode & 7; | |
22784 | OpcodeFamily = 11; CurrentInstrCycles = 12; | |
22785 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
22786 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
22787 | { int16_t dst = m68k_read_memory_16(dsta); | |
22788 | m68k_areg(regs, dstreg) += 2; | |
22789 | { refill_prefetch (m68k_getpc(), 2); | |
22790 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
22791 | { int flgs = ((int16_t)(src)) < 0; | |
22792 | int flgo = ((int16_t)(dst)) < 0; | |
22793 | int flgn = ((int16_t)(newv)) < 0; | |
22794 | SET_ZFLG (((int16_t)(newv)) == 0); | |
22795 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
22796 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
22797 | COPY_CARRY; | |
22798 | SET_NFLG (flgn != 0); | |
22799 | m68k_write_memory_16(dsta,newv); | |
22800 | }}}}}}}m68k_incpc(2); | |
22801 | return 12; | |
22802 | } | |
22803 | unsigned long CPUFUNC(op_d160_4)(uint32_t opcode) /* ADD */ | |
22804 | { | |
22805 | uint32_t srcreg = ((opcode >> 9) & 7); | |
22806 | uint32_t dstreg = opcode & 7; | |
22807 | OpcodeFamily = 11; CurrentInstrCycles = 14; | |
22808 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
22809 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
22810 | { int16_t dst = m68k_read_memory_16(dsta); | |
22811 | m68k_areg (regs, dstreg) = dsta; | |
22812 | { refill_prefetch (m68k_getpc(), 2); | |
22813 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
22814 | { int flgs = ((int16_t)(src)) < 0; | |
22815 | int flgo = ((int16_t)(dst)) < 0; | |
22816 | int flgn = ((int16_t)(newv)) < 0; | |
22817 | SET_ZFLG (((int16_t)(newv)) == 0); | |
22818 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
22819 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
22820 | COPY_CARRY; | |
22821 | SET_NFLG (flgn != 0); | |
22822 | m68k_write_memory_16(dsta,newv); | |
22823 | }}}}}}}m68k_incpc(2); | |
22824 | return 14; | |
22825 | } | |
22826 | unsigned long CPUFUNC(op_d168_4)(uint32_t opcode) /* ADD */ | |
22827 | { | |
22828 | uint32_t srcreg = ((opcode >> 9) & 7); | |
22829 | uint32_t dstreg = opcode & 7; | |
22830 | OpcodeFamily = 11; CurrentInstrCycles = 16; | |
22831 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
22832 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); | |
22833 | { int16_t dst = m68k_read_memory_16(dsta); | |
22834 | { refill_prefetch (m68k_getpc(), 2); | |
22835 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
22836 | { int flgs = ((int16_t)(src)) < 0; | |
22837 | int flgo = ((int16_t)(dst)) < 0; | |
22838 | int flgn = ((int16_t)(newv)) < 0; | |
22839 | SET_ZFLG (((int16_t)(newv)) == 0); | |
22840 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
22841 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
22842 | COPY_CARRY; | |
22843 | SET_NFLG (flgn != 0); | |
22844 | m68k_write_memory_16(dsta,newv); | |
22845 | }}}}}}}m68k_incpc(4); | |
22846 | return 16; | |
22847 | } | |
22848 | unsigned long CPUFUNC(op_d170_4)(uint32_t opcode) /* ADD */ | |
22849 | { | |
22850 | uint32_t srcreg = ((opcode >> 9) & 7); | |
22851 | uint32_t dstreg = opcode & 7; | |
22852 | OpcodeFamily = 11; CurrentInstrCycles = 18; | |
22853 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
22854 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); | |
22855 | BusCyclePenalty += 2; | |
22856 | { int16_t dst = m68k_read_memory_16(dsta); | |
22857 | { refill_prefetch (m68k_getpc(), 2); | |
22858 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
22859 | { int flgs = ((int16_t)(src)) < 0; | |
22860 | int flgo = ((int16_t)(dst)) < 0; | |
22861 | int flgn = ((int16_t)(newv)) < 0; | |
22862 | SET_ZFLG (((int16_t)(newv)) == 0); | |
22863 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
22864 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
22865 | COPY_CARRY; | |
22866 | SET_NFLG (flgn != 0); | |
22867 | m68k_write_memory_16(dsta,newv); | |
22868 | }}}}}}}m68k_incpc(4); | |
22869 | return 18; | |
22870 | } | |
22871 | unsigned long CPUFUNC(op_d178_4)(uint32_t opcode) /* ADD */ | |
22872 | { | |
22873 | uint32_t srcreg = ((opcode >> 9) & 7); | |
22874 | OpcodeFamily = 11; CurrentInstrCycles = 16; | |
22875 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
22876 | { uint32_t dsta = (int32_t)(int16_t)get_iword(2); | |
22877 | { int16_t dst = m68k_read_memory_16(dsta); | |
22878 | { refill_prefetch (m68k_getpc(), 2); | |
22879 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
22880 | { int flgs = ((int16_t)(src)) < 0; | |
22881 | int flgo = ((int16_t)(dst)) < 0; | |
22882 | int flgn = ((int16_t)(newv)) < 0; | |
22883 | SET_ZFLG (((int16_t)(newv)) == 0); | |
22884 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
22885 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
22886 | COPY_CARRY; | |
22887 | SET_NFLG (flgn != 0); | |
22888 | m68k_write_memory_16(dsta,newv); | |
22889 | }}}}}}}m68k_incpc(4); | |
22890 | return 16; | |
22891 | } | |
22892 | unsigned long CPUFUNC(op_d179_4)(uint32_t opcode) /* ADD */ | |
22893 | { | |
22894 | uint32_t srcreg = ((opcode >> 9) & 7); | |
22895 | OpcodeFamily = 11; CurrentInstrCycles = 20; | |
22896 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
22897 | { uint32_t dsta = get_ilong(2); | |
22898 | { int16_t dst = m68k_read_memory_16(dsta); | |
22899 | { refill_prefetch (m68k_getpc(), 2); | |
22900 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
22901 | { int flgs = ((int16_t)(src)) < 0; | |
22902 | int flgo = ((int16_t)(dst)) < 0; | |
22903 | int flgn = ((int16_t)(newv)) < 0; | |
22904 | SET_ZFLG (((int16_t)(newv)) == 0); | |
22905 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
22906 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
22907 | COPY_CARRY; | |
22908 | SET_NFLG (flgn != 0); | |
22909 | m68k_write_memory_16(dsta,newv); | |
22910 | }}}}}}}m68k_incpc(6); | |
22911 | return 20; | |
22912 | } | |
22913 | unsigned long CPUFUNC(op_d180_4)(uint32_t opcode) /* ADDX */ | |
22914 | { | |
22915 | uint32_t srcreg = (opcode & 7); | |
22916 | uint32_t dstreg = (opcode >> 9) & 7; | |
22917 | OpcodeFamily = 13; CurrentInstrCycles = 8; | |
22918 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
22919 | { int32_t dst = m68k_dreg(regs, dstreg); | |
22920 | { uint32_t newv = dst + src + (GET_XFLG ? 1 : 0); | |
22921 | { int flgs = ((int32_t)(src)) < 0; | |
22922 | int flgo = ((int32_t)(dst)) < 0; | |
22923 | int flgn = ((int32_t)(newv)) < 0; | |
22924 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
22925 | SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn))); | |
22926 | COPY_CARRY; | |
22927 | SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0)); | |
22928 | SET_NFLG (((int32_t)(newv)) < 0); | |
22929 | m68k_dreg(regs, dstreg) = (newv); | |
22930 | }}}}}m68k_incpc(2); | |
22931 | return 8; | |
22932 | } | |
22933 | unsigned long CPUFUNC(op_d188_4)(uint32_t opcode) /* ADDX */ | |
22934 | { | |
22935 | uint32_t srcreg = (opcode & 7); | |
22936 | uint32_t dstreg = (opcode >> 9) & 7; | |
22937 | OpcodeFamily = 13; CurrentInstrCycles = 30; | |
22938 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 4; | |
22939 | { int32_t src = m68k_read_memory_32(srca); | |
22940 | m68k_areg (regs, srcreg) = srca; | |
22941 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
22942 | { int32_t dst = m68k_read_memory_32(dsta); | |
22943 | m68k_areg (regs, dstreg) = dsta; | |
22944 | { uint32_t newv = dst + src + (GET_XFLG ? 1 : 0); | |
22945 | { int flgs = ((int32_t)(src)) < 0; | |
22946 | int flgo = ((int32_t)(dst)) < 0; | |
22947 | int flgn = ((int32_t)(newv)) < 0; | |
22948 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
22949 | SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn))); | |
22950 | COPY_CARRY; | |
22951 | SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0)); | |
22952 | SET_NFLG (((int32_t)(newv)) < 0); | |
22953 | m68k_write_memory_32(dsta,newv); | |
22954 | }}}}}}}m68k_incpc(2); | |
22955 | return 30; | |
22956 | } | |
22957 | unsigned long CPUFUNC(op_d190_4)(uint32_t opcode) /* ADD */ | |
22958 | { | |
22959 | uint32_t srcreg = ((opcode >> 9) & 7); | |
22960 | uint32_t dstreg = opcode & 7; | |
22961 | OpcodeFamily = 11; CurrentInstrCycles = 20; | |
22962 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
22963 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
22964 | { int32_t dst = m68k_read_memory_32(dsta); | |
22965 | { refill_prefetch (m68k_getpc(), 2); | |
22966 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
22967 | { int flgs = ((int32_t)(src)) < 0; | |
22968 | int flgo = ((int32_t)(dst)) < 0; | |
22969 | int flgn = ((int32_t)(newv)) < 0; | |
22970 | SET_ZFLG (((int32_t)(newv)) == 0); | |
22971 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
22972 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
22973 | COPY_CARRY; | |
22974 | SET_NFLG (flgn != 0); | |
22975 | m68k_write_memory_32(dsta,newv); | |
22976 | }}}}}}}m68k_incpc(2); | |
22977 | return 20; | |
22978 | } | |
22979 | unsigned long CPUFUNC(op_d198_4)(uint32_t opcode) /* ADD */ | |
22980 | { | |
22981 | uint32_t srcreg = ((opcode >> 9) & 7); | |
22982 | uint32_t dstreg = opcode & 7; | |
22983 | OpcodeFamily = 11; CurrentInstrCycles = 20; | |
22984 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
22985 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
22986 | { int32_t dst = m68k_read_memory_32(dsta); | |
22987 | m68k_areg(regs, dstreg) += 4; | |
22988 | { refill_prefetch (m68k_getpc(), 2); | |
22989 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
22990 | { int flgs = ((int32_t)(src)) < 0; | |
22991 | int flgo = ((int32_t)(dst)) < 0; | |
22992 | int flgn = ((int32_t)(newv)) < 0; | |
22993 | SET_ZFLG (((int32_t)(newv)) == 0); | |
22994 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
22995 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
22996 | COPY_CARRY; | |
22997 | SET_NFLG (flgn != 0); | |
22998 | m68k_write_memory_32(dsta,newv); | |
22999 | }}}}}}}m68k_incpc(2); | |
23000 | return 20; | |
23001 | } | |
23002 | unsigned long CPUFUNC(op_d1a0_4)(uint32_t opcode) /* ADD */ | |
23003 | { | |
23004 | uint32_t srcreg = ((opcode >> 9) & 7); | |
23005 | uint32_t dstreg = opcode & 7; | |
23006 | OpcodeFamily = 11; CurrentInstrCycles = 22; | |
23007 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
23008 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
23009 | { int32_t dst = m68k_read_memory_32(dsta); | |
23010 | m68k_areg (regs, dstreg) = dsta; | |
23011 | { refill_prefetch (m68k_getpc(), 2); | |
23012 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
23013 | { int flgs = ((int32_t)(src)) < 0; | |
23014 | int flgo = ((int32_t)(dst)) < 0; | |
23015 | int flgn = ((int32_t)(newv)) < 0; | |
23016 | SET_ZFLG (((int32_t)(newv)) == 0); | |
23017 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
23018 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
23019 | COPY_CARRY; | |
23020 | SET_NFLG (flgn != 0); | |
23021 | m68k_write_memory_32(dsta,newv); | |
23022 | }}}}}}}m68k_incpc(2); | |
23023 | return 22; | |
23024 | } | |
23025 | unsigned long CPUFUNC(op_d1a8_4)(uint32_t opcode) /* ADD */ | |
23026 | { | |
23027 | uint32_t srcreg = ((opcode >> 9) & 7); | |
23028 | uint32_t dstreg = opcode & 7; | |
23029 | OpcodeFamily = 11; CurrentInstrCycles = 24; | |
23030 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
23031 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword(2); | |
23032 | { int32_t dst = m68k_read_memory_32(dsta); | |
23033 | { refill_prefetch (m68k_getpc(), 2); | |
23034 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
23035 | { int flgs = ((int32_t)(src)) < 0; | |
23036 | int flgo = ((int32_t)(dst)) < 0; | |
23037 | int flgn = ((int32_t)(newv)) < 0; | |
23038 | SET_ZFLG (((int32_t)(newv)) == 0); | |
23039 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
23040 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
23041 | COPY_CARRY; | |
23042 | SET_NFLG (flgn != 0); | |
23043 | m68k_write_memory_32(dsta,newv); | |
23044 | }}}}}}}m68k_incpc(4); | |
23045 | return 24; | |
23046 | } | |
23047 | unsigned long CPUFUNC(op_d1b0_4)(uint32_t opcode) /* ADD */ | |
23048 | { | |
23049 | uint32_t srcreg = ((opcode >> 9) & 7); | |
23050 | uint32_t dstreg = opcode & 7; | |
23051 | OpcodeFamily = 11; CurrentInstrCycles = 26; | |
23052 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
23053 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword(2)); | |
23054 | BusCyclePenalty += 2; | |
23055 | { int32_t dst = m68k_read_memory_32(dsta); | |
23056 | { refill_prefetch (m68k_getpc(), 2); | |
23057 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
23058 | { int flgs = ((int32_t)(src)) < 0; | |
23059 | int flgo = ((int32_t)(dst)) < 0; | |
23060 | int flgn = ((int32_t)(newv)) < 0; | |
23061 | SET_ZFLG (((int32_t)(newv)) == 0); | |
23062 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
23063 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
23064 | COPY_CARRY; | |
23065 | SET_NFLG (flgn != 0); | |
23066 | m68k_write_memory_32(dsta,newv); | |
23067 | }}}}}}}m68k_incpc(4); | |
23068 | return 26; | |
23069 | } | |
23070 | unsigned long CPUFUNC(op_d1b8_4)(uint32_t opcode) /* ADD */ | |
23071 | { | |
23072 | uint32_t srcreg = ((opcode >> 9) & 7); | |
23073 | OpcodeFamily = 11; CurrentInstrCycles = 24; | |
23074 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
23075 | { uint32_t dsta = (int32_t)(int16_t)get_iword(2); | |
23076 | { int32_t dst = m68k_read_memory_32(dsta); | |
23077 | { refill_prefetch (m68k_getpc(), 2); | |
23078 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
23079 | { int flgs = ((int32_t)(src)) < 0; | |
23080 | int flgo = ((int32_t)(dst)) < 0; | |
23081 | int flgn = ((int32_t)(newv)) < 0; | |
23082 | SET_ZFLG (((int32_t)(newv)) == 0); | |
23083 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
23084 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
23085 | COPY_CARRY; | |
23086 | SET_NFLG (flgn != 0); | |
23087 | m68k_write_memory_32(dsta,newv); | |
23088 | }}}}}}}m68k_incpc(4); | |
23089 | return 24; | |
23090 | } | |
23091 | unsigned long CPUFUNC(op_d1b9_4)(uint32_t opcode) /* ADD */ | |
23092 | { | |
23093 | uint32_t srcreg = ((opcode >> 9) & 7); | |
23094 | OpcodeFamily = 11; CurrentInstrCycles = 28; | |
23095 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
23096 | { uint32_t dsta = get_ilong(2); | |
23097 | { int32_t dst = m68k_read_memory_32(dsta); | |
23098 | { refill_prefetch (m68k_getpc(), 2); | |
23099 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
23100 | { int flgs = ((int32_t)(src)) < 0; | |
23101 | int flgo = ((int32_t)(dst)) < 0; | |
23102 | int flgn = ((int32_t)(newv)) < 0; | |
23103 | SET_ZFLG (((int32_t)(newv)) == 0); | |
23104 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
23105 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
23106 | COPY_CARRY; | |
23107 | SET_NFLG (flgn != 0); | |
23108 | m68k_write_memory_32(dsta,newv); | |
23109 | }}}}}}}m68k_incpc(6); | |
23110 | return 28; | |
23111 | } | |
23112 | unsigned long CPUFUNC(op_d1c0_4)(uint32_t opcode) /* ADDA */ | |
23113 | { | |
23114 | uint32_t srcreg = (opcode & 7); | |
23115 | uint32_t dstreg = (opcode >> 9) & 7; | |
23116 | OpcodeFamily = 12; CurrentInstrCycles = 8; | |
23117 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
23118 | { int32_t dst = m68k_areg(regs, dstreg); | |
23119 | { uint32_t newv = dst + src; | |
23120 | m68k_areg(regs, dstreg) = (newv); | |
23121 | }}}}m68k_incpc(2); | |
23122 | return 8; | |
23123 | } | |
23124 | unsigned long CPUFUNC(op_d1c8_4)(uint32_t opcode) /* ADDA */ | |
23125 | { | |
23126 | uint32_t srcreg = (opcode & 7); | |
23127 | uint32_t dstreg = (opcode >> 9) & 7; | |
23128 | OpcodeFamily = 12; CurrentInstrCycles = 8; | |
23129 | {{ int32_t src = m68k_areg(regs, srcreg); | |
23130 | { int32_t dst = m68k_areg(regs, dstreg); | |
23131 | { uint32_t newv = dst + src; | |
23132 | m68k_areg(regs, dstreg) = (newv); | |
23133 | }}}}m68k_incpc(2); | |
23134 | return 8; | |
23135 | } | |
23136 | unsigned long CPUFUNC(op_d1d0_4)(uint32_t opcode) /* ADDA */ | |
23137 | { | |
23138 | uint32_t srcreg = (opcode & 7); | |
23139 | uint32_t dstreg = (opcode >> 9) & 7; | |
23140 | OpcodeFamily = 12; CurrentInstrCycles = 14; | |
23141 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
23142 | { int32_t src = m68k_read_memory_32(srca); | |
23143 | { int32_t dst = m68k_areg(regs, dstreg); | |
23144 | { uint32_t newv = dst + src; | |
23145 | m68k_areg(regs, dstreg) = (newv); | |
23146 | }}}}}m68k_incpc(2); | |
23147 | return 14; | |
23148 | } | |
23149 | #endif | |
23150 | ||
23151 | #ifdef PART_8 | |
23152 | unsigned long CPUFUNC(op_d1d8_4)(uint32_t opcode) /* ADDA */ | |
23153 | { | |
23154 | uint32_t srcreg = (opcode & 7); | |
23155 | uint32_t dstreg = (opcode >> 9) & 7; | |
23156 | OpcodeFamily = 12; CurrentInstrCycles = 14; | |
23157 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
23158 | { int32_t src = m68k_read_memory_32(srca); | |
23159 | m68k_areg(regs, srcreg) += 4; | |
23160 | { int32_t dst = m68k_areg(regs, dstreg); | |
23161 | { uint32_t newv = dst + src; | |
23162 | m68k_areg(regs, dstreg) = (newv); | |
23163 | }}}}}m68k_incpc(2); | |
23164 | return 14; | |
23165 | } | |
23166 | unsigned long CPUFUNC(op_d1e0_4)(uint32_t opcode) /* ADDA */ | |
23167 | { | |
23168 | uint32_t srcreg = (opcode & 7); | |
23169 | uint32_t dstreg = (opcode >> 9) & 7; | |
23170 | OpcodeFamily = 12; CurrentInstrCycles = 16; | |
23171 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 4; | |
23172 | { int32_t src = m68k_read_memory_32(srca); | |
23173 | m68k_areg (regs, srcreg) = srca; | |
23174 | { int32_t dst = m68k_areg(regs, dstreg); | |
23175 | { uint32_t newv = dst + src; | |
23176 | m68k_areg(regs, dstreg) = (newv); | |
23177 | }}}}}m68k_incpc(2); | |
23178 | return 16; | |
23179 | } | |
23180 | unsigned long CPUFUNC(op_d1e8_4)(uint32_t opcode) /* ADDA */ | |
23181 | { | |
23182 | uint32_t srcreg = (opcode & 7); | |
23183 | uint32_t dstreg = (opcode >> 9) & 7; | |
23184 | OpcodeFamily = 12; CurrentInstrCycles = 18; | |
23185 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
23186 | { int32_t src = m68k_read_memory_32(srca); | |
23187 | { int32_t dst = m68k_areg(regs, dstreg); | |
23188 | { uint32_t newv = dst + src; | |
23189 | m68k_areg(regs, dstreg) = (newv); | |
23190 | }}}}}m68k_incpc(4); | |
23191 | return 18; | |
23192 | } | |
23193 | unsigned long CPUFUNC(op_d1f0_4)(uint32_t opcode) /* ADDA */ | |
23194 | { | |
23195 | uint32_t srcreg = (opcode & 7); | |
23196 | uint32_t dstreg = (opcode >> 9) & 7; | |
23197 | OpcodeFamily = 12; CurrentInstrCycles = 20; | |
23198 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
23199 | BusCyclePenalty += 2; | |
23200 | { int32_t src = m68k_read_memory_32(srca); | |
23201 | { int32_t dst = m68k_areg(regs, dstreg); | |
23202 | { uint32_t newv = dst + src; | |
23203 | m68k_areg(regs, dstreg) = (newv); | |
23204 | }}}}}m68k_incpc(4); | |
23205 | return 20; | |
23206 | } | |
23207 | unsigned long CPUFUNC(op_d1f8_4)(uint32_t opcode) /* ADDA */ | |
23208 | { | |
23209 | uint32_t dstreg = (opcode >> 9) & 7; | |
23210 | OpcodeFamily = 12; CurrentInstrCycles = 18; | |
23211 | {{ uint32_t srca = (int32_t)(int16_t)get_iword(2); | |
23212 | { int32_t src = m68k_read_memory_32(srca); | |
23213 | { int32_t dst = m68k_areg(regs, dstreg); | |
23214 | { uint32_t newv = dst + src; | |
23215 | m68k_areg(regs, dstreg) = (newv); | |
23216 | }}}}}m68k_incpc(4); | |
23217 | return 18; | |
23218 | } | |
23219 | unsigned long CPUFUNC(op_d1f9_4)(uint32_t opcode) /* ADDA */ | |
23220 | { | |
23221 | uint32_t dstreg = (opcode >> 9) & 7; | |
23222 | OpcodeFamily = 12; CurrentInstrCycles = 22; | |
23223 | {{ uint32_t srca = get_ilong(2); | |
23224 | { int32_t src = m68k_read_memory_32(srca); | |
23225 | { int32_t dst = m68k_areg(regs, dstreg); | |
23226 | { uint32_t newv = dst + src; | |
23227 | m68k_areg(regs, dstreg) = (newv); | |
23228 | }}}}}m68k_incpc(6); | |
23229 | return 22; | |
23230 | } | |
23231 | unsigned long CPUFUNC(op_d1fa_4)(uint32_t opcode) /* ADDA */ | |
23232 | { | |
23233 | uint32_t dstreg = (opcode >> 9) & 7; | |
23234 | OpcodeFamily = 12; CurrentInstrCycles = 18; | |
23235 | {{ uint32_t srca = m68k_getpc () + 2; | |
23236 | srca += (int32_t)(int16_t)get_iword(2); | |
23237 | { int32_t src = m68k_read_memory_32(srca); | |
23238 | { int32_t dst = m68k_areg(regs, dstreg); | |
23239 | { uint32_t newv = dst + src; | |
23240 | m68k_areg(regs, dstreg) = (newv); | |
23241 | }}}}}m68k_incpc(4); | |
23242 | return 18; | |
23243 | } | |
23244 | unsigned long CPUFUNC(op_d1fb_4)(uint32_t opcode) /* ADDA */ | |
23245 | { | |
23246 | uint32_t dstreg = (opcode >> 9) & 7; | |
23247 | OpcodeFamily = 12; CurrentInstrCycles = 20; | |
23248 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
23249 | uint32_t srca = get_disp_ea_000(tmppc, get_iword(2)); | |
23250 | BusCyclePenalty += 2; | |
23251 | { int32_t src = m68k_read_memory_32(srca); | |
23252 | { int32_t dst = m68k_areg(regs, dstreg); | |
23253 | { uint32_t newv = dst + src; | |
23254 | m68k_areg(regs, dstreg) = (newv); | |
23255 | }}}}}m68k_incpc(4); | |
23256 | return 20; | |
23257 | } | |
23258 | unsigned long CPUFUNC(op_d1fc_4)(uint32_t opcode) /* ADDA */ | |
23259 | { | |
23260 | uint32_t dstreg = (opcode >> 9) & 7; | |
23261 | OpcodeFamily = 12; CurrentInstrCycles = 16; | |
23262 | {{ int32_t src = get_ilong(2); | |
23263 | { int32_t dst = m68k_areg(regs, dstreg); | |
23264 | { uint32_t newv = dst + src; | |
23265 | m68k_areg(regs, dstreg) = (newv); | |
23266 | }}}}m68k_incpc(6); | |
23267 | return 16; | |
23268 | } | |
23269 | unsigned long CPUFUNC(op_e000_4)(uint32_t opcode) /* ASR */ | |
23270 | { | |
23271 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
23272 | uint32_t dstreg = opcode & 7; | |
23273 | unsigned int retcycles = 0; | |
23274 | OpcodeFamily = 64; CurrentInstrCycles = 4; | |
23275 | {{ uint32_t cnt = srcreg; | |
23276 | { int8_t data = m68k_dreg(regs, dstreg); | |
23277 | { uint32_t val = (uint8_t)data; | |
23278 | uint32_t sign = (0x80 & val) >> 7; | |
23279 | cnt &= 63; | |
23280 | retcycles = cnt; | |
23281 | CLEAR_CZNV; | |
23282 | if (cnt >= 8) { | |
23283 | val = 0xff & (uint32_t)-sign; | |
23284 | SET_CFLG (sign); | |
23285 | COPY_CARRY; | |
23286 | } else { | |
23287 | val >>= cnt - 1; | |
23288 | SET_CFLG (val & 1); | |
23289 | COPY_CARRY; | |
23290 | val >>= 1; | |
23291 | val |= (0xff << (8 - cnt)) & (uint32_t)-sign; | |
23292 | val &= 0xff; | |
23293 | } | |
23294 | SET_ZFLG (((int8_t)(val)) == 0); | |
23295 | SET_NFLG (((int8_t)(val)) < 0); | |
23296 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); | |
23297 | }}}}m68k_incpc(2); | |
23298 | return (6+retcycles*2); | |
23299 | } | |
23300 | unsigned long CPUFUNC(op_e008_4)(uint32_t opcode) /* LSR */ | |
23301 | { | |
23302 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
23303 | uint32_t dstreg = opcode & 7; | |
23304 | unsigned int retcycles = 0; | |
23305 | OpcodeFamily = 66; CurrentInstrCycles = 4; | |
23306 | {{ uint32_t cnt = srcreg; | |
23307 | { int8_t data = m68k_dreg(regs, dstreg); | |
23308 | { uint32_t val = (uint8_t)data; | |
23309 | cnt &= 63; | |
23310 | retcycles = cnt; | |
23311 | CLEAR_CZNV; | |
23312 | if (cnt >= 8) { | |
23313 | SET_CFLG ((cnt == 8) & (val >> 7)); | |
23314 | COPY_CARRY; | |
23315 | val = 0; | |
23316 | } else { | |
23317 | val >>= cnt - 1; | |
23318 | SET_CFLG (val & 1); | |
23319 | COPY_CARRY; | |
23320 | val >>= 1; | |
23321 | } | |
23322 | SET_ZFLG (((int8_t)(val)) == 0); | |
23323 | SET_NFLG (((int8_t)(val)) < 0); | |
23324 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); | |
23325 | }}}}m68k_incpc(2); | |
23326 | return (6+retcycles*2); | |
23327 | } | |
23328 | unsigned long CPUFUNC(op_e010_4)(uint32_t opcode) /* ROXR */ | |
23329 | { | |
23330 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
23331 | uint32_t dstreg = opcode & 7; | |
23332 | unsigned int retcycles = 0; | |
23333 | OpcodeFamily = 71; CurrentInstrCycles = 4; | |
23334 | {{ uint32_t cnt = srcreg; | |
23335 | { int8_t data = m68k_dreg(regs, dstreg); | |
23336 | { uint32_t val = (uint8_t)data; | |
23337 | cnt &= 63; | |
23338 | retcycles = cnt; | |
23339 | CLEAR_CZNV; | |
23340 | { cnt--; | |
23341 | { | |
23342 | uint32_t carry; | |
23343 | uint32_t hival = (val << 1) | GET_XFLG; | |
23344 | hival <<= (7 - cnt); | |
23345 | val >>= cnt; | |
23346 | carry = val & 1; | |
23347 | val >>= 1; | |
23348 | val |= hival; | |
23349 | SET_XFLG (carry); | |
23350 | val &= 0xff; | |
23351 | } } | |
23352 | SET_CFLG (GET_XFLG); | |
23353 | SET_ZFLG (((int8_t)(val)) == 0); | |
23354 | SET_NFLG (((int8_t)(val)) < 0); | |
23355 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); | |
23356 | }}}}m68k_incpc(2); | |
23357 | return (6+retcycles*2); | |
23358 | } | |
23359 | unsigned long CPUFUNC(op_e018_4)(uint32_t opcode) /* ROR */ | |
23360 | { | |
23361 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
23362 | uint32_t dstreg = opcode & 7; | |
23363 | unsigned int retcycles = 0; | |
23364 | OpcodeFamily = 69; CurrentInstrCycles = 4; | |
23365 | {{ uint32_t cnt = srcreg; | |
23366 | { int8_t data = m68k_dreg(regs, dstreg); | |
23367 | { uint32_t val = (uint8_t)data; | |
23368 | cnt &= 63; | |
23369 | retcycles = cnt; | |
23370 | CLEAR_CZNV; | |
23371 | { uint32_t hival; | |
23372 | cnt &= 7; | |
23373 | hival = val << (8 - cnt); | |
23374 | val >>= cnt; | |
23375 | val |= hival; | |
23376 | val &= 0xff; | |
23377 | SET_CFLG ((val & 0x80) >> 7); | |
23378 | } | |
23379 | SET_ZFLG (((int8_t)(val)) == 0); | |
23380 | SET_NFLG (((int8_t)(val)) < 0); | |
23381 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); | |
23382 | }}}}m68k_incpc(2); | |
23383 | return (6+retcycles*2); | |
23384 | } | |
23385 | unsigned long CPUFUNC(op_e020_4)(uint32_t opcode) /* ASR */ | |
23386 | { | |
23387 | uint32_t srcreg = ((opcode >> 9) & 7); | |
23388 | uint32_t dstreg = opcode & 7; | |
23389 | unsigned int retcycles = 0; | |
23390 | OpcodeFamily = 64; CurrentInstrCycles = 4; | |
23391 | {{ int8_t cnt = m68k_dreg(regs, srcreg); | |
23392 | { int8_t data = m68k_dreg(regs, dstreg); | |
23393 | { uint32_t val = (uint8_t)data; | |
23394 | uint32_t sign = (0x80 & val) >> 7; | |
23395 | cnt &= 63; | |
23396 | retcycles = cnt; | |
23397 | CLEAR_CZNV; | |
23398 | if (cnt >= 8) { | |
23399 | val = 0xff & (uint32_t)-sign; | |
23400 | SET_CFLG (sign); | |
23401 | COPY_CARRY; | |
23402 | } else if (cnt > 0) { | |
23403 | val >>= cnt - 1; | |
23404 | SET_CFLG (val & 1); | |
23405 | COPY_CARRY; | |
23406 | val >>= 1; | |
23407 | val |= (0xff << (8 - cnt)) & (uint32_t)-sign; | |
23408 | val &= 0xff; | |
23409 | } | |
23410 | SET_ZFLG (((int8_t)(val)) == 0); | |
23411 | SET_NFLG (((int8_t)(val)) < 0); | |
23412 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); | |
23413 | }}}}m68k_incpc(2); | |
23414 | return (6+retcycles*2); | |
23415 | } | |
23416 | unsigned long CPUFUNC(op_e028_4)(uint32_t opcode) /* LSR */ | |
23417 | { | |
23418 | uint32_t srcreg = ((opcode >> 9) & 7); | |
23419 | uint32_t dstreg = opcode & 7; | |
23420 | unsigned int retcycles = 0; | |
23421 | OpcodeFamily = 66; CurrentInstrCycles = 4; | |
23422 | {{ int8_t cnt = m68k_dreg(regs, srcreg); | |
23423 | { int8_t data = m68k_dreg(regs, dstreg); | |
23424 | { uint32_t val = (uint8_t)data; | |
23425 | cnt &= 63; | |
23426 | retcycles = cnt; | |
23427 | CLEAR_CZNV; | |
23428 | if (cnt >= 8) { | |
23429 | SET_CFLG ((cnt == 8) & (val >> 7)); | |
23430 | COPY_CARRY; | |
23431 | val = 0; | |
23432 | } else if (cnt > 0) { | |
23433 | val >>= cnt - 1; | |
23434 | SET_CFLG (val & 1); | |
23435 | COPY_CARRY; | |
23436 | val >>= 1; | |
23437 | } | |
23438 | SET_ZFLG (((int8_t)(val)) == 0); | |
23439 | SET_NFLG (((int8_t)(val)) < 0); | |
23440 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); | |
23441 | }}}}m68k_incpc(2); | |
23442 | return (6+retcycles*2); | |
23443 | } | |
23444 | unsigned long CPUFUNC(op_e030_4)(uint32_t opcode) /* ROXR */ | |
23445 | { | |
23446 | uint32_t srcreg = ((opcode >> 9) & 7); | |
23447 | uint32_t dstreg = opcode & 7; | |
23448 | unsigned int retcycles = 0; | |
23449 | OpcodeFamily = 71; CurrentInstrCycles = 4; | |
23450 | {{ int8_t cnt = m68k_dreg(regs, srcreg); | |
23451 | { int8_t data = m68k_dreg(regs, dstreg); | |
23452 | { uint32_t val = (uint8_t)data; | |
23453 | cnt &= 63; | |
23454 | retcycles = cnt; | |
23455 | CLEAR_CZNV; | |
23456 | if (cnt >= 36) cnt -= 36; | |
23457 | if (cnt >= 18) cnt -= 18; | |
23458 | if (cnt >= 9) cnt -= 9; | |
23459 | if (cnt > 0) { | |
23460 | cnt--; | |
23461 | { | |
23462 | uint32_t carry; | |
23463 | uint32_t hival = (val << 1) | GET_XFLG; | |
23464 | hival <<= (7 - cnt); | |
23465 | val >>= cnt; | |
23466 | carry = val & 1; | |
23467 | val >>= 1; | |
23468 | val |= hival; | |
23469 | SET_XFLG (carry); | |
23470 | val &= 0xff; | |
23471 | } } | |
23472 | SET_CFLG (GET_XFLG); | |
23473 | SET_ZFLG (((int8_t)(val)) == 0); | |
23474 | SET_NFLG (((int8_t)(val)) < 0); | |
23475 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); | |
23476 | }}}}m68k_incpc(2); | |
23477 | return (6+retcycles*2); | |
23478 | } | |
23479 | unsigned long CPUFUNC(op_e038_4)(uint32_t opcode) /* ROR */ | |
23480 | { | |
23481 | uint32_t srcreg = ((opcode >> 9) & 7); | |
23482 | uint32_t dstreg = opcode & 7; | |
23483 | unsigned int retcycles = 0; | |
23484 | OpcodeFamily = 69; CurrentInstrCycles = 4; | |
23485 | {{ int8_t cnt = m68k_dreg(regs, srcreg); | |
23486 | { int8_t data = m68k_dreg(regs, dstreg); | |
23487 | { uint32_t val = (uint8_t)data; | |
23488 | cnt &= 63; | |
23489 | retcycles = cnt; | |
23490 | CLEAR_CZNV; | |
23491 | if (cnt > 0) { uint32_t hival; | |
23492 | cnt &= 7; | |
23493 | hival = val << (8 - cnt); | |
23494 | val >>= cnt; | |
23495 | val |= hival; | |
23496 | val &= 0xff; | |
23497 | SET_CFLG ((val & 0x80) >> 7); | |
23498 | } | |
23499 | SET_ZFLG (((int8_t)(val)) == 0); | |
23500 | SET_NFLG (((int8_t)(val)) < 0); | |
23501 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); | |
23502 | }}}}m68k_incpc(2); | |
23503 | return (6+retcycles*2); | |
23504 | } | |
23505 | unsigned long CPUFUNC(op_e040_4)(uint32_t opcode) /* ASR */ | |
23506 | { | |
23507 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
23508 | uint32_t dstreg = opcode & 7; | |
23509 | unsigned int retcycles = 0; | |
23510 | OpcodeFamily = 64; CurrentInstrCycles = 4; | |
23511 | {{ uint32_t cnt = srcreg; | |
23512 | { int16_t data = m68k_dreg(regs, dstreg); | |
23513 | { uint32_t val = (uint16_t)data; | |
23514 | uint32_t sign = (0x8000 & val) >> 15; | |
23515 | cnt &= 63; | |
23516 | retcycles = cnt; | |
23517 | CLEAR_CZNV; | |
23518 | if (cnt >= 16) { | |
23519 | val = 0xffff & (uint32_t)-sign; | |
23520 | SET_CFLG (sign); | |
23521 | COPY_CARRY; | |
23522 | } else { | |
23523 | val >>= cnt - 1; | |
23524 | SET_CFLG (val & 1); | |
23525 | COPY_CARRY; | |
23526 | val >>= 1; | |
23527 | val |= (0xffff << (16 - cnt)) & (uint32_t)-sign; | |
23528 | val &= 0xffff; | |
23529 | } | |
23530 | SET_ZFLG (((int16_t)(val)) == 0); | |
23531 | SET_NFLG (((int16_t)(val)) < 0); | |
23532 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); | |
23533 | }}}}m68k_incpc(2); | |
23534 | return (6+retcycles*2); | |
23535 | } | |
23536 | unsigned long CPUFUNC(op_e048_4)(uint32_t opcode) /* LSR */ | |
23537 | { | |
23538 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
23539 | uint32_t dstreg = opcode & 7; | |
23540 | unsigned int retcycles = 0; | |
23541 | OpcodeFamily = 66; CurrentInstrCycles = 4; | |
23542 | {{ uint32_t cnt = srcreg; | |
23543 | { int16_t data = m68k_dreg(regs, dstreg); | |
23544 | { uint32_t val = (uint16_t)data; | |
23545 | cnt &= 63; | |
23546 | retcycles = cnt; | |
23547 | CLEAR_CZNV; | |
23548 | if (cnt >= 16) { | |
23549 | SET_CFLG ((cnt == 16) & (val >> 15)); | |
23550 | COPY_CARRY; | |
23551 | val = 0; | |
23552 | } else { | |
23553 | val >>= cnt - 1; | |
23554 | SET_CFLG (val & 1); | |
23555 | COPY_CARRY; | |
23556 | val >>= 1; | |
23557 | } | |
23558 | SET_ZFLG (((int16_t)(val)) == 0); | |
23559 | SET_NFLG (((int16_t)(val)) < 0); | |
23560 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); | |
23561 | }}}}m68k_incpc(2); | |
23562 | return (6+retcycles*2); | |
23563 | } | |
23564 | unsigned long CPUFUNC(op_e050_4)(uint32_t opcode) /* ROXR */ | |
23565 | { | |
23566 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
23567 | uint32_t dstreg = opcode & 7; | |
23568 | unsigned int retcycles = 0; | |
23569 | OpcodeFamily = 71; CurrentInstrCycles = 4; | |
23570 | {{ uint32_t cnt = srcreg; | |
23571 | { int16_t data = m68k_dreg(regs, dstreg); | |
23572 | { uint32_t val = (uint16_t)data; | |
23573 | cnt &= 63; | |
23574 | retcycles = cnt; | |
23575 | CLEAR_CZNV; | |
23576 | { cnt--; | |
23577 | { | |
23578 | uint32_t carry; | |
23579 | uint32_t hival = (val << 1) | GET_XFLG; | |
23580 | hival <<= (15 - cnt); | |
23581 | val >>= cnt; | |
23582 | carry = val & 1; | |
23583 | val >>= 1; | |
23584 | val |= hival; | |
23585 | SET_XFLG (carry); | |
23586 | val &= 0xffff; | |
23587 | } } | |
23588 | SET_CFLG (GET_XFLG); | |
23589 | SET_ZFLG (((int16_t)(val)) == 0); | |
23590 | SET_NFLG (((int16_t)(val)) < 0); | |
23591 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); | |
23592 | }}}}m68k_incpc(2); | |
23593 | return (6+retcycles*2); | |
23594 | } | |
23595 | unsigned long CPUFUNC(op_e058_4)(uint32_t opcode) /* ROR */ | |
23596 | { | |
23597 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
23598 | uint32_t dstreg = opcode & 7; | |
23599 | unsigned int retcycles = 0; | |
23600 | OpcodeFamily = 69; CurrentInstrCycles = 4; | |
23601 | {{ uint32_t cnt = srcreg; | |
23602 | { int16_t data = m68k_dreg(regs, dstreg); | |
23603 | { uint32_t val = (uint16_t)data; | |
23604 | cnt &= 63; | |
23605 | retcycles = cnt; | |
23606 | CLEAR_CZNV; | |
23607 | { uint32_t hival; | |
23608 | cnt &= 15; | |
23609 | hival = val << (16 - cnt); | |
23610 | val >>= cnt; | |
23611 | val |= hival; | |
23612 | val &= 0xffff; | |
23613 | SET_CFLG ((val & 0x8000) >> 15); | |
23614 | } | |
23615 | SET_ZFLG (((int16_t)(val)) == 0); | |
23616 | SET_NFLG (((int16_t)(val)) < 0); | |
23617 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); | |
23618 | }}}}m68k_incpc(2); | |
23619 | return (6+retcycles*2); | |
23620 | } | |
23621 | unsigned long CPUFUNC(op_e060_4)(uint32_t opcode) /* ASR */ | |
23622 | { | |
23623 | uint32_t srcreg = ((opcode >> 9) & 7); | |
23624 | uint32_t dstreg = opcode & 7; | |
23625 | unsigned int retcycles = 0; | |
23626 | OpcodeFamily = 64; CurrentInstrCycles = 4; | |
23627 | {{ int16_t cnt = m68k_dreg(regs, srcreg); | |
23628 | { int16_t data = m68k_dreg(regs, dstreg); | |
23629 | { uint32_t val = (uint16_t)data; | |
23630 | uint32_t sign = (0x8000 & val) >> 15; | |
23631 | cnt &= 63; | |
23632 | retcycles = cnt; | |
23633 | CLEAR_CZNV; | |
23634 | if (cnt >= 16) { | |
23635 | val = 0xffff & (uint32_t)-sign; | |
23636 | SET_CFLG (sign); | |
23637 | COPY_CARRY; | |
23638 | } else if (cnt > 0) { | |
23639 | val >>= cnt - 1; | |
23640 | SET_CFLG (val & 1); | |
23641 | COPY_CARRY; | |
23642 | val >>= 1; | |
23643 | val |= (0xffff << (16 - cnt)) & (uint32_t)-sign; | |
23644 | val &= 0xffff; | |
23645 | } | |
23646 | SET_ZFLG (((int16_t)(val)) == 0); | |
23647 | SET_NFLG (((int16_t)(val)) < 0); | |
23648 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); | |
23649 | }}}}m68k_incpc(2); | |
23650 | return (6+retcycles*2); | |
23651 | } | |
23652 | unsigned long CPUFUNC(op_e068_4)(uint32_t opcode) /* LSR */ | |
23653 | { | |
23654 | uint32_t srcreg = ((opcode >> 9) & 7); | |
23655 | uint32_t dstreg = opcode & 7; | |
23656 | unsigned int retcycles = 0; | |
23657 | OpcodeFamily = 66; CurrentInstrCycles = 4; | |
23658 | {{ int16_t cnt = m68k_dreg(regs, srcreg); | |
23659 | { int16_t data = m68k_dreg(regs, dstreg); | |
23660 | { uint32_t val = (uint16_t)data; | |
23661 | cnt &= 63; | |
23662 | retcycles = cnt; | |
23663 | CLEAR_CZNV; | |
23664 | if (cnt >= 16) { | |
23665 | SET_CFLG ((cnt == 16) & (val >> 15)); | |
23666 | COPY_CARRY; | |
23667 | val = 0; | |
23668 | } else if (cnt > 0) { | |
23669 | val >>= cnt - 1; | |
23670 | SET_CFLG (val & 1); | |
23671 | COPY_CARRY; | |
23672 | val >>= 1; | |
23673 | } | |
23674 | SET_ZFLG (((int16_t)(val)) == 0); | |
23675 | SET_NFLG (((int16_t)(val)) < 0); | |
23676 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); | |
23677 | }}}}m68k_incpc(2); | |
23678 | return (6+retcycles*2); | |
23679 | } | |
23680 | unsigned long CPUFUNC(op_e070_4)(uint32_t opcode) /* ROXR */ | |
23681 | { | |
23682 | uint32_t srcreg = ((opcode >> 9) & 7); | |
23683 | uint32_t dstreg = opcode & 7; | |
23684 | unsigned int retcycles = 0; | |
23685 | OpcodeFamily = 71; CurrentInstrCycles = 4; | |
23686 | {{ int16_t cnt = m68k_dreg(regs, srcreg); | |
23687 | { int16_t data = m68k_dreg(regs, dstreg); | |
23688 | { uint32_t val = (uint16_t)data; | |
23689 | cnt &= 63; | |
23690 | retcycles = cnt; | |
23691 | CLEAR_CZNV; | |
23692 | if (cnt >= 34) cnt -= 34; | |
23693 | if (cnt >= 17) cnt -= 17; | |
23694 | if (cnt > 0) { | |
23695 | cnt--; | |
23696 | { | |
23697 | uint32_t carry; | |
23698 | uint32_t hival = (val << 1) | GET_XFLG; | |
23699 | hival <<= (15 - cnt); | |
23700 | val >>= cnt; | |
23701 | carry = val & 1; | |
23702 | val >>= 1; | |
23703 | val |= hival; | |
23704 | SET_XFLG (carry); | |
23705 | val &= 0xffff; | |
23706 | } } | |
23707 | SET_CFLG (GET_XFLG); | |
23708 | SET_ZFLG (((int16_t)(val)) == 0); | |
23709 | SET_NFLG (((int16_t)(val)) < 0); | |
23710 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); | |
23711 | }}}}m68k_incpc(2); | |
23712 | return (6+retcycles*2); | |
23713 | } | |
23714 | unsigned long CPUFUNC(op_e078_4)(uint32_t opcode) /* ROR */ | |
23715 | { | |
23716 | uint32_t srcreg = ((opcode >> 9) & 7); | |
23717 | uint32_t dstreg = opcode & 7; | |
23718 | unsigned int retcycles = 0; | |
23719 | OpcodeFamily = 69; CurrentInstrCycles = 4; | |
23720 | {{ int16_t cnt = m68k_dreg(regs, srcreg); | |
23721 | { int16_t data = m68k_dreg(regs, dstreg); | |
23722 | { uint32_t val = (uint16_t)data; | |
23723 | cnt &= 63; | |
23724 | retcycles = cnt; | |
23725 | CLEAR_CZNV; | |
23726 | if (cnt > 0) { uint32_t hival; | |
23727 | cnt &= 15; | |
23728 | hival = val << (16 - cnt); | |
23729 | val >>= cnt; | |
23730 | val |= hival; | |
23731 | val &= 0xffff; | |
23732 | SET_CFLG ((val & 0x8000) >> 15); | |
23733 | } | |
23734 | SET_ZFLG (((int16_t)(val)) == 0); | |
23735 | SET_NFLG (((int16_t)(val)) < 0); | |
23736 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); | |
23737 | }}}}m68k_incpc(2); | |
23738 | return (6+retcycles*2); | |
23739 | } | |
23740 | unsigned long CPUFUNC(op_e080_4)(uint32_t opcode) /* ASR */ | |
23741 | { | |
23742 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
23743 | uint32_t dstreg = opcode & 7; | |
23744 | unsigned int retcycles = 0; | |
23745 | OpcodeFamily = 64; CurrentInstrCycles = 4; | |
23746 | {{ uint32_t cnt = srcreg; | |
23747 | { int32_t data = m68k_dreg(regs, dstreg); | |
23748 | { uint32_t val = data; | |
23749 | uint32_t sign = (0x80000000 & val) >> 31; | |
23750 | cnt &= 63; | |
23751 | retcycles = cnt; | |
23752 | CLEAR_CZNV; | |
23753 | if (cnt >= 32) { | |
23754 | val = 0xffffffff & (uint32_t)-sign; | |
23755 | SET_CFLG (sign); | |
23756 | COPY_CARRY; | |
23757 | } else { | |
23758 | val >>= cnt - 1; | |
23759 | SET_CFLG (val & 1); | |
23760 | COPY_CARRY; | |
23761 | val >>= 1; | |
23762 | val |= (0xffffffff << (32 - cnt)) & (uint32_t)-sign; | |
23763 | val &= 0xffffffff; | |
23764 | } | |
23765 | SET_ZFLG (((int32_t)(val)) == 0); | |
23766 | SET_NFLG (((int32_t)(val)) < 0); | |
23767 | m68k_dreg(regs, dstreg) = (val); | |
23768 | }}}}m68k_incpc(2); | |
23769 | return (8+retcycles*2); | |
23770 | } | |
23771 | unsigned long CPUFUNC(op_e088_4)(uint32_t opcode) /* LSR */ | |
23772 | { | |
23773 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
23774 | uint32_t dstreg = opcode & 7; | |
23775 | unsigned int retcycles = 0; | |
23776 | OpcodeFamily = 66; CurrentInstrCycles = 4; | |
23777 | {{ uint32_t cnt = srcreg; | |
23778 | { int32_t data = m68k_dreg(regs, dstreg); | |
23779 | { uint32_t val = data; | |
23780 | cnt &= 63; | |
23781 | retcycles = cnt; | |
23782 | CLEAR_CZNV; | |
23783 | if (cnt >= 32) { | |
23784 | SET_CFLG ((cnt == 32) & (val >> 31)); | |
23785 | COPY_CARRY; | |
23786 | val = 0; | |
23787 | } else { | |
23788 | val >>= cnt - 1; | |
23789 | SET_CFLG (val & 1); | |
23790 | COPY_CARRY; | |
23791 | val >>= 1; | |
23792 | } | |
23793 | SET_ZFLG (((int32_t)(val)) == 0); | |
23794 | SET_NFLG (((int32_t)(val)) < 0); | |
23795 | m68k_dreg(regs, dstreg) = (val); | |
23796 | }}}}m68k_incpc(2); | |
23797 | return (8+retcycles*2); | |
23798 | } | |
23799 | unsigned long CPUFUNC(op_e090_4)(uint32_t opcode) /* ROXR */ | |
23800 | { | |
23801 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
23802 | uint32_t dstreg = opcode & 7; | |
23803 | unsigned int retcycles = 0; | |
23804 | OpcodeFamily = 71; CurrentInstrCycles = 4; | |
23805 | {{ uint32_t cnt = srcreg; | |
23806 | { int32_t data = m68k_dreg(regs, dstreg); | |
23807 | { uint32_t val = data; | |
23808 | cnt &= 63; | |
23809 | retcycles = cnt; | |
23810 | CLEAR_CZNV; | |
23811 | { cnt--; | |
23812 | { | |
23813 | uint32_t carry; | |
23814 | uint32_t hival = (val << 1) | GET_XFLG; | |
23815 | hival <<= (31 - cnt); | |
23816 | val >>= cnt; | |
23817 | carry = val & 1; | |
23818 | val >>= 1; | |
23819 | val |= hival; | |
23820 | SET_XFLG (carry); | |
23821 | val &= 0xffffffff; | |
23822 | } } | |
23823 | SET_CFLG (GET_XFLG); | |
23824 | SET_ZFLG (((int32_t)(val)) == 0); | |
23825 | SET_NFLG (((int32_t)(val)) < 0); | |
23826 | m68k_dreg(regs, dstreg) = (val); | |
23827 | }}}}m68k_incpc(2); | |
23828 | return (8+retcycles*2); | |
23829 | } | |
23830 | unsigned long CPUFUNC(op_e098_4)(uint32_t opcode) /* ROR */ | |
23831 | { | |
23832 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
23833 | uint32_t dstreg = opcode & 7; | |
23834 | unsigned int retcycles = 0; | |
23835 | OpcodeFamily = 69; CurrentInstrCycles = 4; | |
23836 | {{ uint32_t cnt = srcreg; | |
23837 | { int32_t data = m68k_dreg(regs, dstreg); | |
23838 | { uint32_t val = data; | |
23839 | cnt &= 63; | |
23840 | retcycles = cnt; | |
23841 | CLEAR_CZNV; | |
23842 | { uint32_t hival; | |
23843 | cnt &= 31; | |
23844 | hival = val << (32 - cnt); | |
23845 | val >>= cnt; | |
23846 | val |= hival; | |
23847 | val &= 0xffffffff; | |
23848 | SET_CFLG ((val & 0x80000000) >> 31); | |
23849 | } | |
23850 | SET_ZFLG (((int32_t)(val)) == 0); | |
23851 | SET_NFLG (((int32_t)(val)) < 0); | |
23852 | m68k_dreg(regs, dstreg) = (val); | |
23853 | }}}}m68k_incpc(2); | |
23854 | return (8+retcycles*2); | |
23855 | } | |
23856 | unsigned long CPUFUNC(op_e0a0_4)(uint32_t opcode) /* ASR */ | |
23857 | { | |
23858 | uint32_t srcreg = ((opcode >> 9) & 7); | |
23859 | uint32_t dstreg = opcode & 7; | |
23860 | unsigned int retcycles = 0; | |
23861 | OpcodeFamily = 64; CurrentInstrCycles = 4; | |
23862 | {{ int32_t cnt = m68k_dreg(regs, srcreg); | |
23863 | { int32_t data = m68k_dreg(regs, dstreg); | |
23864 | { uint32_t val = data; | |
23865 | uint32_t sign = (0x80000000 & val) >> 31; | |
23866 | cnt &= 63; | |
23867 | retcycles = cnt; | |
23868 | CLEAR_CZNV; | |
23869 | if (cnt >= 32) { | |
23870 | val = 0xffffffff & (uint32_t)-sign; | |
23871 | SET_CFLG (sign); | |
23872 | COPY_CARRY; | |
23873 | } else if (cnt > 0) { | |
23874 | val >>= cnt - 1; | |
23875 | SET_CFLG (val & 1); | |
23876 | COPY_CARRY; | |
23877 | val >>= 1; | |
23878 | val |= (0xffffffff << (32 - cnt)) & (uint32_t)-sign; | |
23879 | val &= 0xffffffff; | |
23880 | } | |
23881 | SET_ZFLG (((int32_t)(val)) == 0); | |
23882 | SET_NFLG (((int32_t)(val)) < 0); | |
23883 | m68k_dreg(regs, dstreg) = (val); | |
23884 | }}}}m68k_incpc(2); | |
23885 | return (8+retcycles*2); | |
23886 | } | |
23887 | unsigned long CPUFUNC(op_e0a8_4)(uint32_t opcode) /* LSR */ | |
23888 | { | |
23889 | uint32_t srcreg = ((opcode >> 9) & 7); | |
23890 | uint32_t dstreg = opcode & 7; | |
23891 | unsigned int retcycles = 0; | |
23892 | OpcodeFamily = 66; CurrentInstrCycles = 4; | |
23893 | {{ int32_t cnt = m68k_dreg(regs, srcreg); | |
23894 | { int32_t data = m68k_dreg(regs, dstreg); | |
23895 | { uint32_t val = data; | |
23896 | cnt &= 63; | |
23897 | retcycles = cnt; | |
23898 | CLEAR_CZNV; | |
23899 | if (cnt >= 32) { | |
23900 | SET_CFLG ((cnt == 32) & (val >> 31)); | |
23901 | COPY_CARRY; | |
23902 | val = 0; | |
23903 | } else if (cnt > 0) { | |
23904 | val >>= cnt - 1; | |
23905 | SET_CFLG (val & 1); | |
23906 | COPY_CARRY; | |
23907 | val >>= 1; | |
23908 | } | |
23909 | SET_ZFLG (((int32_t)(val)) == 0); | |
23910 | SET_NFLG (((int32_t)(val)) < 0); | |
23911 | m68k_dreg(regs, dstreg) = (val); | |
23912 | }}}}m68k_incpc(2); | |
23913 | return (8+retcycles*2); | |
23914 | } | |
23915 | unsigned long CPUFUNC(op_e0b0_4)(uint32_t opcode) /* ROXR */ | |
23916 | { | |
23917 | uint32_t srcreg = ((opcode >> 9) & 7); | |
23918 | uint32_t dstreg = opcode & 7; | |
23919 | unsigned int retcycles = 0; | |
23920 | OpcodeFamily = 71; CurrentInstrCycles = 4; | |
23921 | {{ int32_t cnt = m68k_dreg(regs, srcreg); | |
23922 | { int32_t data = m68k_dreg(regs, dstreg); | |
23923 | { uint32_t val = data; | |
23924 | cnt &= 63; | |
23925 | retcycles = cnt; | |
23926 | CLEAR_CZNV; | |
23927 | if (cnt >= 33) cnt -= 33; | |
23928 | if (cnt > 0) { | |
23929 | cnt--; | |
23930 | { | |
23931 | uint32_t carry; | |
23932 | uint32_t hival = (val << 1) | GET_XFLG; | |
23933 | hival <<= (31 - cnt); | |
23934 | val >>= cnt; | |
23935 | carry = val & 1; | |
23936 | val >>= 1; | |
23937 | val |= hival; | |
23938 | SET_XFLG (carry); | |
23939 | val &= 0xffffffff; | |
23940 | } } | |
23941 | SET_CFLG (GET_XFLG); | |
23942 | SET_ZFLG (((int32_t)(val)) == 0); | |
23943 | SET_NFLG (((int32_t)(val)) < 0); | |
23944 | m68k_dreg(regs, dstreg) = (val); | |
23945 | }}}}m68k_incpc(2); | |
23946 | return (8+retcycles*2); | |
23947 | } | |
23948 | unsigned long CPUFUNC(op_e0b8_4)(uint32_t opcode) /* ROR */ | |
23949 | { | |
23950 | uint32_t srcreg = ((opcode >> 9) & 7); | |
23951 | uint32_t dstreg = opcode & 7; | |
23952 | unsigned int retcycles = 0; | |
23953 | OpcodeFamily = 69; CurrentInstrCycles = 4; | |
23954 | {{ int32_t cnt = m68k_dreg(regs, srcreg); | |
23955 | { int32_t data = m68k_dreg(regs, dstreg); | |
23956 | { uint32_t val = data; | |
23957 | cnt &= 63; | |
23958 | retcycles = cnt; | |
23959 | CLEAR_CZNV; | |
23960 | if (cnt > 0) { uint32_t hival; | |
23961 | cnt &= 31; | |
23962 | hival = val << (32 - cnt); | |
23963 | val >>= cnt; | |
23964 | val |= hival; | |
23965 | val &= 0xffffffff; | |
23966 | SET_CFLG ((val & 0x80000000) >> 31); | |
23967 | } | |
23968 | SET_ZFLG (((int32_t)(val)) == 0); | |
23969 | SET_NFLG (((int32_t)(val)) < 0); | |
23970 | m68k_dreg(regs, dstreg) = (val); | |
23971 | }}}}m68k_incpc(2); | |
23972 | return (8+retcycles*2); | |
23973 | } | |
23974 | unsigned long CPUFUNC(op_e0d0_4)(uint32_t opcode) /* ASRW */ | |
23975 | { | |
23976 | uint32_t srcreg = (opcode & 7); | |
23977 | OpcodeFamily = 72; CurrentInstrCycles = 12; | |
23978 | {{ uint32_t dataa = m68k_areg(regs, srcreg); | |
23979 | { int16_t data = m68k_read_memory_16(dataa); | |
23980 | { uint32_t val = (uint16_t)data; | |
23981 | uint32_t sign = 0x8000 & val; | |
23982 | uint32_t cflg = val & 1; | |
23983 | val = (val >> 1) | sign; | |
23984 | CLEAR_CZNV; | |
23985 | SET_ZFLG (((int16_t)(val)) == 0); | |
23986 | SET_NFLG (((int16_t)(val)) < 0); | |
23987 | SET_CFLG (cflg); | |
23988 | COPY_CARRY; | |
23989 | m68k_write_memory_16(dataa,val); | |
23990 | }}}}m68k_incpc(2); | |
23991 | return 12; | |
23992 | } | |
23993 | unsigned long CPUFUNC(op_e0d8_4)(uint32_t opcode) /* ASRW */ | |
23994 | { | |
23995 | uint32_t srcreg = (opcode & 7); | |
23996 | OpcodeFamily = 72; CurrentInstrCycles = 12; | |
23997 | {{ uint32_t dataa = m68k_areg(regs, srcreg); | |
23998 | { int16_t data = m68k_read_memory_16(dataa); | |
23999 | m68k_areg(regs, srcreg) += 2; | |
24000 | { uint32_t val = (uint16_t)data; | |
24001 | uint32_t sign = 0x8000 & val; | |
24002 | uint32_t cflg = val & 1; | |
24003 | val = (val >> 1) | sign; | |
24004 | CLEAR_CZNV; | |
24005 | SET_ZFLG (((int16_t)(val)) == 0); | |
24006 | SET_NFLG (((int16_t)(val)) < 0); | |
24007 | SET_CFLG (cflg); | |
24008 | COPY_CARRY; | |
24009 | m68k_write_memory_16(dataa,val); | |
24010 | }}}}m68k_incpc(2); | |
24011 | return 12; | |
24012 | } | |
24013 | unsigned long CPUFUNC(op_e0e0_4)(uint32_t opcode) /* ASRW */ | |
24014 | { | |
24015 | uint32_t srcreg = (opcode & 7); | |
24016 | OpcodeFamily = 72; CurrentInstrCycles = 14; | |
24017 | {{ uint32_t dataa = m68k_areg(regs, srcreg) - 2; | |
24018 | { int16_t data = m68k_read_memory_16(dataa); | |
24019 | m68k_areg (regs, srcreg) = dataa; | |
24020 | { uint32_t val = (uint16_t)data; | |
24021 | uint32_t sign = 0x8000 & val; | |
24022 | uint32_t cflg = val & 1; | |
24023 | val = (val >> 1) | sign; | |
24024 | CLEAR_CZNV; | |
24025 | SET_ZFLG (((int16_t)(val)) == 0); | |
24026 | SET_NFLG (((int16_t)(val)) < 0); | |
24027 | SET_CFLG (cflg); | |
24028 | COPY_CARRY; | |
24029 | m68k_write_memory_16(dataa,val); | |
24030 | }}}}m68k_incpc(2); | |
24031 | return 14; | |
24032 | } | |
24033 | unsigned long CPUFUNC(op_e0e8_4)(uint32_t opcode) /* ASRW */ | |
24034 | { | |
24035 | uint32_t srcreg = (opcode & 7); | |
24036 | OpcodeFamily = 72; CurrentInstrCycles = 16; | |
24037 | {{ uint32_t dataa = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
24038 | { int16_t data = m68k_read_memory_16(dataa); | |
24039 | { uint32_t val = (uint16_t)data; | |
24040 | uint32_t sign = 0x8000 & val; | |
24041 | uint32_t cflg = val & 1; | |
24042 | val = (val >> 1) | sign; | |
24043 | CLEAR_CZNV; | |
24044 | SET_ZFLG (((int16_t)(val)) == 0); | |
24045 | SET_NFLG (((int16_t)(val)) < 0); | |
24046 | SET_CFLG (cflg); | |
24047 | COPY_CARRY; | |
24048 | m68k_write_memory_16(dataa,val); | |
24049 | }}}}m68k_incpc(4); | |
24050 | return 16; | |
24051 | } | |
24052 | unsigned long CPUFUNC(op_e0f0_4)(uint32_t opcode) /* ASRW */ | |
24053 | { | |
24054 | uint32_t srcreg = (opcode & 7); | |
24055 | OpcodeFamily = 72; CurrentInstrCycles = 18; | |
24056 | {{ uint32_t dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
24057 | BusCyclePenalty += 2; | |
24058 | { int16_t data = m68k_read_memory_16(dataa); | |
24059 | { uint32_t val = (uint16_t)data; | |
24060 | uint32_t sign = 0x8000 & val; | |
24061 | uint32_t cflg = val & 1; | |
24062 | val = (val >> 1) | sign; | |
24063 | CLEAR_CZNV; | |
24064 | SET_ZFLG (((int16_t)(val)) == 0); | |
24065 | SET_NFLG (((int16_t)(val)) < 0); | |
24066 | SET_CFLG (cflg); | |
24067 | COPY_CARRY; | |
24068 | m68k_write_memory_16(dataa,val); | |
24069 | }}}}m68k_incpc(4); | |
24070 | return 18; | |
24071 | } | |
24072 | unsigned long CPUFUNC(op_e0f8_4)(uint32_t opcode) /* ASRW */ | |
24073 | { | |
24074 | OpcodeFamily = 72; CurrentInstrCycles = 16; | |
24075 | {{ uint32_t dataa = (int32_t)(int16_t)get_iword(2); | |
24076 | { int16_t data = m68k_read_memory_16(dataa); | |
24077 | { uint32_t val = (uint16_t)data; | |
24078 | uint32_t sign = 0x8000 & val; | |
24079 | uint32_t cflg = val & 1; | |
24080 | val = (val >> 1) | sign; | |
24081 | CLEAR_CZNV; | |
24082 | SET_ZFLG (((int16_t)(val)) == 0); | |
24083 | SET_NFLG (((int16_t)(val)) < 0); | |
24084 | SET_CFLG (cflg); | |
24085 | COPY_CARRY; | |
24086 | m68k_write_memory_16(dataa,val); | |
24087 | }}}}m68k_incpc(4); | |
24088 | return 16; | |
24089 | } | |
24090 | unsigned long CPUFUNC(op_e0f9_4)(uint32_t opcode) /* ASRW */ | |
24091 | { | |
24092 | OpcodeFamily = 72; CurrentInstrCycles = 20; | |
24093 | {{ uint32_t dataa = get_ilong(2); | |
24094 | { int16_t data = m68k_read_memory_16(dataa); | |
24095 | { uint32_t val = (uint16_t)data; | |
24096 | uint32_t sign = 0x8000 & val; | |
24097 | uint32_t cflg = val & 1; | |
24098 | val = (val >> 1) | sign; | |
24099 | CLEAR_CZNV; | |
24100 | SET_ZFLG (((int16_t)(val)) == 0); | |
24101 | SET_NFLG (((int16_t)(val)) < 0); | |
24102 | SET_CFLG (cflg); | |
24103 | COPY_CARRY; | |
24104 | m68k_write_memory_16(dataa,val); | |
24105 | }}}}m68k_incpc(6); | |
24106 | return 20; | |
24107 | } | |
24108 | unsigned long CPUFUNC(op_e100_4)(uint32_t opcode) /* ASL */ | |
24109 | { | |
24110 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
24111 | uint32_t dstreg = opcode & 7; | |
24112 | unsigned int retcycles = 0; | |
24113 | OpcodeFamily = 65; CurrentInstrCycles = 4; | |
24114 | {{ uint32_t cnt = srcreg; | |
24115 | { int8_t data = m68k_dreg(regs, dstreg); | |
24116 | { uint32_t val = (uint8_t)data; | |
24117 | cnt &= 63; | |
24118 | retcycles = cnt; | |
24119 | CLEAR_CZNV; | |
24120 | if (cnt >= 8) { | |
24121 | SET_VFLG (val != 0); | |
24122 | SET_CFLG (cnt == 8 ? val & 1 : 0); | |
24123 | COPY_CARRY; | |
24124 | val = 0; | |
24125 | } else { | |
24126 | uint32_t mask = (0xff << (7 - cnt)) & 0xff; | |
24127 | SET_VFLG ((val & mask) != mask && (val & mask) != 0); | |
24128 | val <<= cnt - 1; | |
24129 | SET_CFLG ((val & 0x80) >> 7); | |
24130 | COPY_CARRY; | |
24131 | val <<= 1; | |
24132 | val &= 0xff; | |
24133 | } | |
24134 | SET_ZFLG (((int8_t)(val)) == 0); | |
24135 | SET_NFLG (((int8_t)(val)) < 0); | |
24136 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); | |
24137 | }}}}m68k_incpc(2); | |
24138 | return (6+retcycles*2); | |
24139 | } | |
24140 | unsigned long CPUFUNC(op_e108_4)(uint32_t opcode) /* LSL */ | |
24141 | { | |
24142 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
24143 | uint32_t dstreg = opcode & 7; | |
24144 | unsigned int retcycles = 0; | |
24145 | OpcodeFamily = 67; CurrentInstrCycles = 4; | |
24146 | {{ uint32_t cnt = srcreg; | |
24147 | { int8_t data = m68k_dreg(regs, dstreg); | |
24148 | { uint32_t val = (uint8_t)data; | |
24149 | cnt &= 63; | |
24150 | retcycles = cnt; | |
24151 | CLEAR_CZNV; | |
24152 | if (cnt >= 8) { | |
24153 | SET_CFLG (cnt == 8 ? val & 1 : 0); | |
24154 | COPY_CARRY; | |
24155 | val = 0; | |
24156 | } else { | |
24157 | val <<= (cnt - 1); | |
24158 | SET_CFLG ((val & 0x80) >> 7); | |
24159 | COPY_CARRY; | |
24160 | val <<= 1; | |
24161 | val &= 0xff; | |
24162 | } | |
24163 | SET_ZFLG (((int8_t)(val)) == 0); | |
24164 | SET_NFLG (((int8_t)(val)) < 0); | |
24165 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); | |
24166 | }}}}m68k_incpc(2); | |
24167 | return (6+retcycles*2); | |
24168 | } | |
24169 | unsigned long CPUFUNC(op_e110_4)(uint32_t opcode) /* ROXL */ | |
24170 | { | |
24171 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
24172 | uint32_t dstreg = opcode & 7; | |
24173 | unsigned int retcycles = 0; | |
24174 | OpcodeFamily = 70; CurrentInstrCycles = 4; | |
24175 | {{ uint32_t cnt = srcreg; | |
24176 | { int8_t data = m68k_dreg(regs, dstreg); | |
24177 | { uint32_t val = (uint8_t)data; | |
24178 | cnt &= 63; | |
24179 | retcycles = cnt; | |
24180 | CLEAR_CZNV; | |
24181 | { cnt--; | |
24182 | { | |
24183 | uint32_t carry; | |
24184 | uint32_t loval = val >> (7 - cnt); | |
24185 | carry = loval & 1; | |
24186 | val = (((val << 1) | GET_XFLG) << cnt) | (loval >> 1); | |
24187 | SET_XFLG (carry); | |
24188 | val &= 0xff; | |
24189 | } } | |
24190 | SET_CFLG (GET_XFLG); | |
24191 | SET_ZFLG (((int8_t)(val)) == 0); | |
24192 | SET_NFLG (((int8_t)(val)) < 0); | |
24193 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); | |
24194 | }}}}m68k_incpc(2); | |
24195 | return (6+retcycles*2); | |
24196 | } | |
24197 | unsigned long CPUFUNC(op_e118_4)(uint32_t opcode) /* ROL */ | |
24198 | { | |
24199 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
24200 | uint32_t dstreg = opcode & 7; | |
24201 | unsigned int retcycles = 0; | |
24202 | OpcodeFamily = 68; CurrentInstrCycles = 4; | |
24203 | {{ uint32_t cnt = srcreg; | |
24204 | { int8_t data = m68k_dreg(regs, dstreg); | |
24205 | { uint32_t val = (uint8_t)data; | |
24206 | cnt &= 63; | |
24207 | retcycles = cnt; | |
24208 | CLEAR_CZNV; | |
24209 | { uint32_t loval; | |
24210 | cnt &= 7; | |
24211 | loval = val >> (8 - cnt); | |
24212 | val <<= cnt; | |
24213 | val |= loval; | |
24214 | val &= 0xff; | |
24215 | SET_CFLG (val & 1); | |
24216 | } | |
24217 | SET_ZFLG (((int8_t)(val)) == 0); | |
24218 | SET_NFLG (((int8_t)(val)) < 0); | |
24219 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); | |
24220 | }}}}m68k_incpc(2); | |
24221 | return (6+retcycles*2); | |
24222 | } | |
24223 | unsigned long CPUFUNC(op_e120_4)(uint32_t opcode) /* ASL */ | |
24224 | { | |
24225 | uint32_t srcreg = ((opcode >> 9) & 7); | |
24226 | uint32_t dstreg = opcode & 7; | |
24227 | unsigned int retcycles = 0; | |
24228 | OpcodeFamily = 65; CurrentInstrCycles = 4; | |
24229 | {{ int8_t cnt = m68k_dreg(regs, srcreg); | |
24230 | { int8_t data = m68k_dreg(regs, dstreg); | |
24231 | { uint32_t val = (uint8_t)data; | |
24232 | cnt &= 63; | |
24233 | retcycles = cnt; | |
24234 | CLEAR_CZNV; | |
24235 | if (cnt >= 8) { | |
24236 | SET_VFLG (val != 0); | |
24237 | SET_CFLG (cnt == 8 ? val & 1 : 0); | |
24238 | COPY_CARRY; | |
24239 | val = 0; | |
24240 | } else if (cnt > 0) { | |
24241 | uint32_t mask = (0xff << (7 - cnt)) & 0xff; | |
24242 | SET_VFLG ((val & mask) != mask && (val & mask) != 0); | |
24243 | val <<= cnt - 1; | |
24244 | SET_CFLG ((val & 0x80) >> 7); | |
24245 | COPY_CARRY; | |
24246 | val <<= 1; | |
24247 | val &= 0xff; | |
24248 | } | |
24249 | SET_ZFLG (((int8_t)(val)) == 0); | |
24250 | SET_NFLG (((int8_t)(val)) < 0); | |
24251 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); | |
24252 | }}}}m68k_incpc(2); | |
24253 | return (6+retcycles*2); | |
24254 | } | |
24255 | unsigned long CPUFUNC(op_e128_4)(uint32_t opcode) /* LSL */ | |
24256 | { | |
24257 | uint32_t srcreg = ((opcode >> 9) & 7); | |
24258 | uint32_t dstreg = opcode & 7; | |
24259 | unsigned int retcycles = 0; | |
24260 | OpcodeFamily = 67; CurrentInstrCycles = 4; | |
24261 | {{ int8_t cnt = m68k_dreg(regs, srcreg); | |
24262 | { int8_t data = m68k_dreg(regs, dstreg); | |
24263 | { uint32_t val = (uint8_t)data; | |
24264 | cnt &= 63; | |
24265 | retcycles = cnt; | |
24266 | CLEAR_CZNV; | |
24267 | if (cnt >= 8) { | |
24268 | SET_CFLG (cnt == 8 ? val & 1 : 0); | |
24269 | COPY_CARRY; | |
24270 | val = 0; | |
24271 | } else if (cnt > 0) { | |
24272 | val <<= (cnt - 1); | |
24273 | SET_CFLG ((val & 0x80) >> 7); | |
24274 | COPY_CARRY; | |
24275 | val <<= 1; | |
24276 | val &= 0xff; | |
24277 | } | |
24278 | SET_ZFLG (((int8_t)(val)) == 0); | |
24279 | SET_NFLG (((int8_t)(val)) < 0); | |
24280 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); | |
24281 | }}}}m68k_incpc(2); | |
24282 | return (6+retcycles*2); | |
24283 | } | |
24284 | unsigned long CPUFUNC(op_e130_4)(uint32_t opcode) /* ROXL */ | |
24285 | { | |
24286 | uint32_t srcreg = ((opcode >> 9) & 7); | |
24287 | uint32_t dstreg = opcode & 7; | |
24288 | unsigned int retcycles = 0; | |
24289 | OpcodeFamily = 70; CurrentInstrCycles = 4; | |
24290 | {{ int8_t cnt = m68k_dreg(regs, srcreg); | |
24291 | { int8_t data = m68k_dreg(regs, dstreg); | |
24292 | { uint32_t val = (uint8_t)data; | |
24293 | cnt &= 63; | |
24294 | retcycles = cnt; | |
24295 | CLEAR_CZNV; | |
24296 | if (cnt >= 36) cnt -= 36; | |
24297 | if (cnt >= 18) cnt -= 18; | |
24298 | if (cnt >= 9) cnt -= 9; | |
24299 | if (cnt > 0) { | |
24300 | cnt--; | |
24301 | { | |
24302 | uint32_t carry; | |
24303 | uint32_t loval = val >> (7 - cnt); | |
24304 | carry = loval & 1; | |
24305 | val = (((val << 1) | GET_XFLG) << cnt) | (loval >> 1); | |
24306 | SET_XFLG (carry); | |
24307 | val &= 0xff; | |
24308 | } } | |
24309 | SET_CFLG (GET_XFLG); | |
24310 | SET_ZFLG (((int8_t)(val)) == 0); | |
24311 | SET_NFLG (((int8_t)(val)) < 0); | |
24312 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); | |
24313 | }}}}m68k_incpc(2); | |
24314 | return (6+retcycles*2); | |
24315 | } | |
24316 | unsigned long CPUFUNC(op_e138_4)(uint32_t opcode) /* ROL */ | |
24317 | { | |
24318 | uint32_t srcreg = ((opcode >> 9) & 7); | |
24319 | uint32_t dstreg = opcode & 7; | |
24320 | unsigned int retcycles = 0; | |
24321 | OpcodeFamily = 68; CurrentInstrCycles = 4; | |
24322 | {{ int8_t cnt = m68k_dreg(regs, srcreg); | |
24323 | { int8_t data = m68k_dreg(regs, dstreg); | |
24324 | { uint32_t val = (uint8_t)data; | |
24325 | cnt &= 63; | |
24326 | retcycles = cnt; | |
24327 | CLEAR_CZNV; | |
24328 | if (cnt > 0) { | |
24329 | uint32_t loval; | |
24330 | cnt &= 7; | |
24331 | loval = val >> (8 - cnt); | |
24332 | val <<= cnt; | |
24333 | val |= loval; | |
24334 | val &= 0xff; | |
24335 | SET_CFLG (val & 1); | |
24336 | } | |
24337 | SET_ZFLG (((int8_t)(val)) == 0); | |
24338 | SET_NFLG (((int8_t)(val)) < 0); | |
24339 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); | |
24340 | }}}}m68k_incpc(2); | |
24341 | return (6+retcycles*2); | |
24342 | } | |
24343 | unsigned long CPUFUNC(op_e140_4)(uint32_t opcode) /* ASL */ | |
24344 | { | |
24345 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
24346 | uint32_t dstreg = opcode & 7; | |
24347 | unsigned int retcycles = 0; | |
24348 | OpcodeFamily = 65; CurrentInstrCycles = 4; | |
24349 | {{ uint32_t cnt = srcreg; | |
24350 | { int16_t data = m68k_dreg(regs, dstreg); | |
24351 | { uint32_t val = (uint16_t)data; | |
24352 | cnt &= 63; | |
24353 | retcycles = cnt; | |
24354 | CLEAR_CZNV; | |
24355 | if (cnt >= 16) { | |
24356 | SET_VFLG (val != 0); | |
24357 | SET_CFLG (cnt == 16 ? val & 1 : 0); | |
24358 | COPY_CARRY; | |
24359 | val = 0; | |
24360 | } else { | |
24361 | uint32_t mask = (0xffff << (15 - cnt)) & 0xffff; | |
24362 | SET_VFLG ((val & mask) != mask && (val & mask) != 0); | |
24363 | val <<= cnt - 1; | |
24364 | SET_CFLG ((val & 0x8000) >> 15); | |
24365 | COPY_CARRY; | |
24366 | val <<= 1; | |
24367 | val &= 0xffff; | |
24368 | } | |
24369 | SET_ZFLG (((int16_t)(val)) == 0); | |
24370 | SET_NFLG (((int16_t)(val)) < 0); | |
24371 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); | |
24372 | }}}}m68k_incpc(2); | |
24373 | return (6+retcycles*2); | |
24374 | } | |
24375 | unsigned long CPUFUNC(op_e148_4)(uint32_t opcode) /* LSL */ | |
24376 | { | |
24377 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
24378 | uint32_t dstreg = opcode & 7; | |
24379 | unsigned int retcycles = 0; | |
24380 | OpcodeFamily = 67; CurrentInstrCycles = 4; | |
24381 | {{ uint32_t cnt = srcreg; | |
24382 | { int16_t data = m68k_dreg(regs, dstreg); | |
24383 | { uint32_t val = (uint16_t)data; | |
24384 | cnt &= 63; | |
24385 | retcycles = cnt; | |
24386 | CLEAR_CZNV; | |
24387 | if (cnt >= 16) { | |
24388 | SET_CFLG (cnt == 16 ? val & 1 : 0); | |
24389 | COPY_CARRY; | |
24390 | val = 0; | |
24391 | } else { | |
24392 | val <<= (cnt - 1); | |
24393 | SET_CFLG ((val & 0x8000) >> 15); | |
24394 | COPY_CARRY; | |
24395 | val <<= 1; | |
24396 | val &= 0xffff; | |
24397 | } | |
24398 | SET_ZFLG (((int16_t)(val)) == 0); | |
24399 | SET_NFLG (((int16_t)(val)) < 0); | |
24400 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); | |
24401 | }}}}m68k_incpc(2); | |
24402 | return (6+retcycles*2); | |
24403 | } | |
24404 | unsigned long CPUFUNC(op_e150_4)(uint32_t opcode) /* ROXL */ | |
24405 | { | |
24406 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
24407 | uint32_t dstreg = opcode & 7; | |
24408 | unsigned int retcycles = 0; | |
24409 | OpcodeFamily = 70; CurrentInstrCycles = 4; | |
24410 | {{ uint32_t cnt = srcreg; | |
24411 | { int16_t data = m68k_dreg(regs, dstreg); | |
24412 | { uint32_t val = (uint16_t)data; | |
24413 | cnt &= 63; | |
24414 | retcycles = cnt; | |
24415 | CLEAR_CZNV; | |
24416 | { cnt--; | |
24417 | { | |
24418 | uint32_t carry; | |
24419 | uint32_t loval = val >> (15 - cnt); | |
24420 | carry = loval & 1; | |
24421 | val = (((val << 1) | GET_XFLG) << cnt) | (loval >> 1); | |
24422 | SET_XFLG (carry); | |
24423 | val &= 0xffff; | |
24424 | } } | |
24425 | SET_CFLG (GET_XFLG); | |
24426 | SET_ZFLG (((int16_t)(val)) == 0); | |
24427 | SET_NFLG (((int16_t)(val)) < 0); | |
24428 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); | |
24429 | }}}}m68k_incpc(2); | |
24430 | return (6+retcycles*2); | |
24431 | } | |
24432 | unsigned long CPUFUNC(op_e158_4)(uint32_t opcode) /* ROL */ | |
24433 | { | |
24434 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
24435 | uint32_t dstreg = opcode & 7; | |
24436 | unsigned int retcycles = 0; | |
24437 | OpcodeFamily = 68; CurrentInstrCycles = 4; | |
24438 | {{ uint32_t cnt = srcreg; | |
24439 | { int16_t data = m68k_dreg(regs, dstreg); | |
24440 | { uint32_t val = (uint16_t)data; | |
24441 | cnt &= 63; | |
24442 | retcycles = cnt; | |
24443 | CLEAR_CZNV; | |
24444 | { uint32_t loval; | |
24445 | cnt &= 15; | |
24446 | loval = val >> (16 - cnt); | |
24447 | val <<= cnt; | |
24448 | val |= loval; | |
24449 | val &= 0xffff; | |
24450 | SET_CFLG (val & 1); | |
24451 | } | |
24452 | SET_ZFLG (((int16_t)(val)) == 0); | |
24453 | SET_NFLG (((int16_t)(val)) < 0); | |
24454 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); | |
24455 | }}}}m68k_incpc(2); | |
24456 | return (6+retcycles*2); | |
24457 | } | |
24458 | unsigned long CPUFUNC(op_e160_4)(uint32_t opcode) /* ASL */ | |
24459 | { | |
24460 | uint32_t srcreg = ((opcode >> 9) & 7); | |
24461 | uint32_t dstreg = opcode & 7; | |
24462 | unsigned int retcycles = 0; | |
24463 | OpcodeFamily = 65; CurrentInstrCycles = 4; | |
24464 | {{ int16_t cnt = m68k_dreg(regs, srcreg); | |
24465 | { int16_t data = m68k_dreg(regs, dstreg); | |
24466 | { uint32_t val = (uint16_t)data; | |
24467 | cnt &= 63; | |
24468 | retcycles = cnt; | |
24469 | CLEAR_CZNV; | |
24470 | if (cnt >= 16) { | |
24471 | SET_VFLG (val != 0); | |
24472 | SET_CFLG (cnt == 16 ? val & 1 : 0); | |
24473 | COPY_CARRY; | |
24474 | val = 0; | |
24475 | } else if (cnt > 0) { | |
24476 | uint32_t mask = (0xffff << (15 - cnt)) & 0xffff; | |
24477 | SET_VFLG ((val & mask) != mask && (val & mask) != 0); | |
24478 | val <<= cnt - 1; | |
24479 | SET_CFLG ((val & 0x8000) >> 15); | |
24480 | COPY_CARRY; | |
24481 | val <<= 1; | |
24482 | val &= 0xffff; | |
24483 | } | |
24484 | SET_ZFLG (((int16_t)(val)) == 0); | |
24485 | SET_NFLG (((int16_t)(val)) < 0); | |
24486 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); | |
24487 | }}}}m68k_incpc(2); | |
24488 | return (6+retcycles*2); | |
24489 | } | |
24490 | unsigned long CPUFUNC(op_e168_4)(uint32_t opcode) /* LSL */ | |
24491 | { | |
24492 | uint32_t srcreg = ((opcode >> 9) & 7); | |
24493 | uint32_t dstreg = opcode & 7; | |
24494 | unsigned int retcycles = 0; | |
24495 | OpcodeFamily = 67; CurrentInstrCycles = 4; | |
24496 | {{ int16_t cnt = m68k_dreg(regs, srcreg); | |
24497 | { int16_t data = m68k_dreg(regs, dstreg); | |
24498 | { uint32_t val = (uint16_t)data; | |
24499 | cnt &= 63; | |
24500 | retcycles = cnt; | |
24501 | CLEAR_CZNV; | |
24502 | if (cnt >= 16) { | |
24503 | SET_CFLG (cnt == 16 ? val & 1 : 0); | |
24504 | COPY_CARRY; | |
24505 | val = 0; | |
24506 | } else if (cnt > 0) { | |
24507 | val <<= (cnt - 1); | |
24508 | SET_CFLG ((val & 0x8000) >> 15); | |
24509 | COPY_CARRY; | |
24510 | val <<= 1; | |
24511 | val &= 0xffff; | |
24512 | } | |
24513 | SET_ZFLG (((int16_t)(val)) == 0); | |
24514 | SET_NFLG (((int16_t)(val)) < 0); | |
24515 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); | |
24516 | }}}}m68k_incpc(2); | |
24517 | return (6+retcycles*2); | |
24518 | } | |
24519 | unsigned long CPUFUNC(op_e170_4)(uint32_t opcode) /* ROXL */ | |
24520 | { | |
24521 | uint32_t srcreg = ((opcode >> 9) & 7); | |
24522 | uint32_t dstreg = opcode & 7; | |
24523 | unsigned int retcycles = 0; | |
24524 | OpcodeFamily = 70; CurrentInstrCycles = 4; | |
24525 | {{ int16_t cnt = m68k_dreg(regs, srcreg); | |
24526 | { int16_t data = m68k_dreg(regs, dstreg); | |
24527 | { uint32_t val = (uint16_t)data; | |
24528 | cnt &= 63; | |
24529 | retcycles = cnt; | |
24530 | CLEAR_CZNV; | |
24531 | if (cnt >= 34) cnt -= 34; | |
24532 | if (cnt >= 17) cnt -= 17; | |
24533 | if (cnt > 0) { | |
24534 | cnt--; | |
24535 | { | |
24536 | uint32_t carry; | |
24537 | uint32_t loval = val >> (15 - cnt); | |
24538 | carry = loval & 1; | |
24539 | val = (((val << 1) | GET_XFLG) << cnt) | (loval >> 1); | |
24540 | SET_XFLG (carry); | |
24541 | val &= 0xffff; | |
24542 | } } | |
24543 | SET_CFLG (GET_XFLG); | |
24544 | SET_ZFLG (((int16_t)(val)) == 0); | |
24545 | SET_NFLG (((int16_t)(val)) < 0); | |
24546 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); | |
24547 | }}}}m68k_incpc(2); | |
24548 | return (6+retcycles*2); | |
24549 | } | |
24550 | unsigned long CPUFUNC(op_e178_4)(uint32_t opcode) /* ROL */ | |
24551 | { | |
24552 | uint32_t srcreg = ((opcode >> 9) & 7); | |
24553 | uint32_t dstreg = opcode & 7; | |
24554 | unsigned int retcycles = 0; | |
24555 | OpcodeFamily = 68; CurrentInstrCycles = 4; | |
24556 | {{ int16_t cnt = m68k_dreg(regs, srcreg); | |
24557 | { int16_t data = m68k_dreg(regs, dstreg); | |
24558 | { uint32_t val = (uint16_t)data; | |
24559 | cnt &= 63; | |
24560 | retcycles = cnt; | |
24561 | CLEAR_CZNV; | |
24562 | if (cnt > 0) { | |
24563 | uint32_t loval; | |
24564 | cnt &= 15; | |
24565 | loval = val >> (16 - cnt); | |
24566 | val <<= cnt; | |
24567 | val |= loval; | |
24568 | val &= 0xffff; | |
24569 | SET_CFLG (val & 1); | |
24570 | } | |
24571 | SET_ZFLG (((int16_t)(val)) == 0); | |
24572 | SET_NFLG (((int16_t)(val)) < 0); | |
24573 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); | |
24574 | }}}}m68k_incpc(2); | |
24575 | return (6+retcycles*2); | |
24576 | } | |
24577 | unsigned long CPUFUNC(op_e180_4)(uint32_t opcode) /* ASL */ | |
24578 | { | |
24579 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
24580 | uint32_t dstreg = opcode & 7; | |
24581 | unsigned int retcycles = 0; | |
24582 | OpcodeFamily = 65; CurrentInstrCycles = 4; | |
24583 | {{ uint32_t cnt = srcreg; | |
24584 | { int32_t data = m68k_dreg(regs, dstreg); | |
24585 | { uint32_t val = data; | |
24586 | cnt &= 63; | |
24587 | retcycles = cnt; | |
24588 | CLEAR_CZNV; | |
24589 | if (cnt >= 32) { | |
24590 | SET_VFLG (val != 0); | |
24591 | SET_CFLG (cnt == 32 ? val & 1 : 0); | |
24592 | COPY_CARRY; | |
24593 | val = 0; | |
24594 | } else { | |
24595 | uint32_t mask = (0xffffffff << (31 - cnt)) & 0xffffffff; | |
24596 | SET_VFLG ((val & mask) != mask && (val & mask) != 0); | |
24597 | val <<= cnt - 1; | |
24598 | SET_CFLG ((val & 0x80000000) >> 31); | |
24599 | COPY_CARRY; | |
24600 | val <<= 1; | |
24601 | val &= 0xffffffff; | |
24602 | } | |
24603 | SET_ZFLG (((int32_t)(val)) == 0); | |
24604 | SET_NFLG (((int32_t)(val)) < 0); | |
24605 | m68k_dreg(regs, dstreg) = (val); | |
24606 | }}}}m68k_incpc(2); | |
24607 | return (8+retcycles*2); | |
24608 | } | |
24609 | unsigned long CPUFUNC(op_e188_4)(uint32_t opcode) /* LSL */ | |
24610 | { | |
24611 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
24612 | uint32_t dstreg = opcode & 7; | |
24613 | unsigned int retcycles = 0; | |
24614 | OpcodeFamily = 67; CurrentInstrCycles = 4; | |
24615 | {{ uint32_t cnt = srcreg; | |
24616 | { int32_t data = m68k_dreg(regs, dstreg); | |
24617 | { uint32_t val = data; | |
24618 | cnt &= 63; | |
24619 | retcycles = cnt; | |
24620 | CLEAR_CZNV; | |
24621 | if (cnt >= 32) { | |
24622 | SET_CFLG (cnt == 32 ? val & 1 : 0); | |
24623 | COPY_CARRY; | |
24624 | val = 0; | |
24625 | } else { | |
24626 | val <<= (cnt - 1); | |
24627 | SET_CFLG ((val & 0x80000000) >> 31); | |
24628 | COPY_CARRY; | |
24629 | val <<= 1; | |
24630 | val &= 0xffffffff; | |
24631 | } | |
24632 | SET_ZFLG (((int32_t)(val)) == 0); | |
24633 | SET_NFLG (((int32_t)(val)) < 0); | |
24634 | m68k_dreg(regs, dstreg) = (val); | |
24635 | }}}}m68k_incpc(2); | |
24636 | return (8+retcycles*2); | |
24637 | } | |
24638 | unsigned long CPUFUNC(op_e190_4)(uint32_t opcode) /* ROXL */ | |
24639 | { | |
24640 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
24641 | uint32_t dstreg = opcode & 7; | |
24642 | unsigned int retcycles = 0; | |
24643 | OpcodeFamily = 70; CurrentInstrCycles = 4; | |
24644 | {{ uint32_t cnt = srcreg; | |
24645 | { int32_t data = m68k_dreg(regs, dstreg); | |
24646 | { uint32_t val = data; | |
24647 | cnt &= 63; | |
24648 | retcycles = cnt; | |
24649 | CLEAR_CZNV; | |
24650 | { cnt--; | |
24651 | { | |
24652 | uint32_t carry; | |
24653 | uint32_t loval = val >> (31 - cnt); | |
24654 | carry = loval & 1; | |
24655 | val = (((val << 1) | GET_XFLG) << cnt) | (loval >> 1); | |
24656 | SET_XFLG (carry); | |
24657 | val &= 0xffffffff; | |
24658 | } } | |
24659 | SET_CFLG (GET_XFLG); | |
24660 | SET_ZFLG (((int32_t)(val)) == 0); | |
24661 | SET_NFLG (((int32_t)(val)) < 0); | |
24662 | m68k_dreg(regs, dstreg) = (val); | |
24663 | }}}}m68k_incpc(2); | |
24664 | return (8+retcycles*2); | |
24665 | } | |
24666 | unsigned long CPUFUNC(op_e198_4)(uint32_t opcode) /* ROL */ | |
24667 | { | |
24668 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
24669 | uint32_t dstreg = opcode & 7; | |
24670 | unsigned int retcycles = 0; | |
24671 | OpcodeFamily = 68; CurrentInstrCycles = 4; | |
24672 | {{ uint32_t cnt = srcreg; | |
24673 | { int32_t data = m68k_dreg(regs, dstreg); | |
24674 | { uint32_t val = data; | |
24675 | cnt &= 63; | |
24676 | retcycles = cnt; | |
24677 | CLEAR_CZNV; | |
24678 | { uint32_t loval; | |
24679 | cnt &= 31; | |
24680 | loval = val >> (32 - cnt); | |
24681 | val <<= cnt; | |
24682 | val |= loval; | |
24683 | val &= 0xffffffff; | |
24684 | SET_CFLG (val & 1); | |
24685 | } | |
24686 | SET_ZFLG (((int32_t)(val)) == 0); | |
24687 | SET_NFLG (((int32_t)(val)) < 0); | |
24688 | m68k_dreg(regs, dstreg) = (val); | |
24689 | }}}}m68k_incpc(2); | |
24690 | return (8+retcycles*2); | |
24691 | } | |
24692 | unsigned long CPUFUNC(op_e1a0_4)(uint32_t opcode) /* ASL */ | |
24693 | { | |
24694 | uint32_t srcreg = ((opcode >> 9) & 7); | |
24695 | uint32_t dstreg = opcode & 7; | |
24696 | unsigned int retcycles = 0; | |
24697 | OpcodeFamily = 65; CurrentInstrCycles = 4; | |
24698 | {{ int32_t cnt = m68k_dreg(regs, srcreg); | |
24699 | { int32_t data = m68k_dreg(regs, dstreg); | |
24700 | { uint32_t val = data; | |
24701 | cnt &= 63; | |
24702 | retcycles = cnt; | |
24703 | CLEAR_CZNV; | |
24704 | if (cnt >= 32) { | |
24705 | SET_VFLG (val != 0); | |
24706 | SET_CFLG (cnt == 32 ? val & 1 : 0); | |
24707 | COPY_CARRY; | |
24708 | val = 0; | |
24709 | } else if (cnt > 0) { | |
24710 | uint32_t mask = (0xffffffff << (31 - cnt)) & 0xffffffff; | |
24711 | SET_VFLG ((val & mask) != mask && (val & mask) != 0); | |
24712 | val <<= cnt - 1; | |
24713 | SET_CFLG ((val & 0x80000000) >> 31); | |
24714 | COPY_CARRY; | |
24715 | val <<= 1; | |
24716 | val &= 0xffffffff; | |
24717 | } | |
24718 | SET_ZFLG (((int32_t)(val)) == 0); | |
24719 | SET_NFLG (((int32_t)(val)) < 0); | |
24720 | m68k_dreg(regs, dstreg) = (val); | |
24721 | }}}}m68k_incpc(2); | |
24722 | return (8+retcycles*2); | |
24723 | } | |
24724 | unsigned long CPUFUNC(op_e1a8_4)(uint32_t opcode) /* LSL */ | |
24725 | { | |
24726 | uint32_t srcreg = ((opcode >> 9) & 7); | |
24727 | uint32_t dstreg = opcode & 7; | |
24728 | unsigned int retcycles = 0; | |
24729 | OpcodeFamily = 67; CurrentInstrCycles = 4; | |
24730 | {{ int32_t cnt = m68k_dreg(regs, srcreg); | |
24731 | { int32_t data = m68k_dreg(regs, dstreg); | |
24732 | { uint32_t val = data; | |
24733 | cnt &= 63; | |
24734 | retcycles = cnt; | |
24735 | CLEAR_CZNV; | |
24736 | if (cnt >= 32) { | |
24737 | SET_CFLG (cnt == 32 ? val & 1 : 0); | |
24738 | COPY_CARRY; | |
24739 | val = 0; | |
24740 | } else if (cnt > 0) { | |
24741 | val <<= (cnt - 1); | |
24742 | SET_CFLG ((val & 0x80000000) >> 31); | |
24743 | COPY_CARRY; | |
24744 | val <<= 1; | |
24745 | val &= 0xffffffff; | |
24746 | } | |
24747 | SET_ZFLG (((int32_t)(val)) == 0); | |
24748 | SET_NFLG (((int32_t)(val)) < 0); | |
24749 | m68k_dreg(regs, dstreg) = (val); | |
24750 | }}}}m68k_incpc(2); | |
24751 | return (8+retcycles*2); | |
24752 | } | |
24753 | unsigned long CPUFUNC(op_e1b0_4)(uint32_t opcode) /* ROXL */ | |
24754 | { | |
24755 | uint32_t srcreg = ((opcode >> 9) & 7); | |
24756 | uint32_t dstreg = opcode & 7; | |
24757 | unsigned int retcycles = 0; | |
24758 | OpcodeFamily = 70; CurrentInstrCycles = 4; | |
24759 | {{ int32_t cnt = m68k_dreg(regs, srcreg); | |
24760 | { int32_t data = m68k_dreg(regs, dstreg); | |
24761 | { uint32_t val = data; | |
24762 | cnt &= 63; | |
24763 | retcycles = cnt; | |
24764 | CLEAR_CZNV; | |
24765 | if (cnt >= 33) cnt -= 33; | |
24766 | if (cnt > 0) { | |
24767 | cnt--; | |
24768 | { | |
24769 | uint32_t carry; | |
24770 | uint32_t loval = val >> (31 - cnt); | |
24771 | carry = loval & 1; | |
24772 | val = (((val << 1) | GET_XFLG) << cnt) | (loval >> 1); | |
24773 | SET_XFLG (carry); | |
24774 | val &= 0xffffffff; | |
24775 | } } | |
24776 | SET_CFLG (GET_XFLG); | |
24777 | SET_ZFLG (((int32_t)(val)) == 0); | |
24778 | SET_NFLG (((int32_t)(val)) < 0); | |
24779 | m68k_dreg(regs, dstreg) = (val); | |
24780 | }}}}m68k_incpc(2); | |
24781 | return (8+retcycles*2); | |
24782 | } | |
24783 | unsigned long CPUFUNC(op_e1b8_4)(uint32_t opcode) /* ROL */ | |
24784 | { | |
24785 | uint32_t srcreg = ((opcode >> 9) & 7); | |
24786 | uint32_t dstreg = opcode & 7; | |
24787 | unsigned int retcycles = 0; | |
24788 | OpcodeFamily = 68; CurrentInstrCycles = 4; | |
24789 | {{ int32_t cnt = m68k_dreg(regs, srcreg); | |
24790 | { int32_t data = m68k_dreg(regs, dstreg); | |
24791 | { uint32_t val = data; | |
24792 | cnt &= 63; | |
24793 | retcycles = cnt; | |
24794 | CLEAR_CZNV; | |
24795 | if (cnt > 0) { | |
24796 | uint32_t loval; | |
24797 | cnt &= 31; | |
24798 | loval = val >> (32 - cnt); | |
24799 | val <<= cnt; | |
24800 | val |= loval; | |
24801 | val &= 0xffffffff; | |
24802 | SET_CFLG (val & 1); | |
24803 | } | |
24804 | SET_ZFLG (((int32_t)(val)) == 0); | |
24805 | SET_NFLG (((int32_t)(val)) < 0); | |
24806 | m68k_dreg(regs, dstreg) = (val); | |
24807 | }}}}m68k_incpc(2); | |
24808 | return (8+retcycles*2); | |
24809 | } | |
24810 | unsigned long CPUFUNC(op_e1d0_4)(uint32_t opcode) /* ASLW */ | |
24811 | { | |
24812 | uint32_t srcreg = (opcode & 7); | |
24813 | OpcodeFamily = 73; CurrentInstrCycles = 12; | |
24814 | {{ uint32_t dataa = m68k_areg(regs, srcreg); | |
24815 | { int16_t data = m68k_read_memory_16(dataa); | |
24816 | { uint32_t val = (uint16_t)data; | |
24817 | uint32_t sign = 0x8000 & val; | |
24818 | uint32_t sign2; | |
24819 | val <<= 1; | |
24820 | CLEAR_CZNV; | |
24821 | SET_ZFLG (((int16_t)(val)) == 0); | |
24822 | SET_NFLG (((int16_t)(val)) < 0); | |
24823 | sign2 = 0x8000 & val; | |
24824 | SET_CFLG (sign != 0); | |
24825 | COPY_CARRY; | |
24826 | SET_VFLG (GET_VFLG | (sign2 != sign)); | |
24827 | m68k_write_memory_16(dataa,val); | |
24828 | }}}}m68k_incpc(2); | |
24829 | return 12; | |
24830 | } | |
24831 | unsigned long CPUFUNC(op_e1d8_4)(uint32_t opcode) /* ASLW */ | |
24832 | { | |
24833 | uint32_t srcreg = (opcode & 7); | |
24834 | OpcodeFamily = 73; CurrentInstrCycles = 12; | |
24835 | {{ uint32_t dataa = m68k_areg(regs, srcreg); | |
24836 | { int16_t data = m68k_read_memory_16(dataa); | |
24837 | m68k_areg(regs, srcreg) += 2; | |
24838 | { uint32_t val = (uint16_t)data; | |
24839 | uint32_t sign = 0x8000 & val; | |
24840 | uint32_t sign2; | |
24841 | val <<= 1; | |
24842 | CLEAR_CZNV; | |
24843 | SET_ZFLG (((int16_t)(val)) == 0); | |
24844 | SET_NFLG (((int16_t)(val)) < 0); | |
24845 | sign2 = 0x8000 & val; | |
24846 | SET_CFLG (sign != 0); | |
24847 | COPY_CARRY; | |
24848 | SET_VFLG (GET_VFLG | (sign2 != sign)); | |
24849 | m68k_write_memory_16(dataa,val); | |
24850 | }}}}m68k_incpc(2); | |
24851 | return 12; | |
24852 | } | |
24853 | unsigned long CPUFUNC(op_e1e0_4)(uint32_t opcode) /* ASLW */ | |
24854 | { | |
24855 | uint32_t srcreg = (opcode & 7); | |
24856 | OpcodeFamily = 73; CurrentInstrCycles = 14; | |
24857 | {{ uint32_t dataa = m68k_areg(regs, srcreg) - 2; | |
24858 | { int16_t data = m68k_read_memory_16(dataa); | |
24859 | m68k_areg (regs, srcreg) = dataa; | |
24860 | { uint32_t val = (uint16_t)data; | |
24861 | uint32_t sign = 0x8000 & val; | |
24862 | uint32_t sign2; | |
24863 | val <<= 1; | |
24864 | CLEAR_CZNV; | |
24865 | SET_ZFLG (((int16_t)(val)) == 0); | |
24866 | SET_NFLG (((int16_t)(val)) < 0); | |
24867 | sign2 = 0x8000 & val; | |
24868 | SET_CFLG (sign != 0); | |
24869 | COPY_CARRY; | |
24870 | SET_VFLG (GET_VFLG | (sign2 != sign)); | |
24871 | m68k_write_memory_16(dataa,val); | |
24872 | }}}}m68k_incpc(2); | |
24873 | return 14; | |
24874 | } | |
24875 | unsigned long CPUFUNC(op_e1e8_4)(uint32_t opcode) /* ASLW */ | |
24876 | { | |
24877 | uint32_t srcreg = (opcode & 7); | |
24878 | OpcodeFamily = 73; CurrentInstrCycles = 16; | |
24879 | {{ uint32_t dataa = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
24880 | { int16_t data = m68k_read_memory_16(dataa); | |
24881 | { uint32_t val = (uint16_t)data; | |
24882 | uint32_t sign = 0x8000 & val; | |
24883 | uint32_t sign2; | |
24884 | val <<= 1; | |
24885 | CLEAR_CZNV; | |
24886 | SET_ZFLG (((int16_t)(val)) == 0); | |
24887 | SET_NFLG (((int16_t)(val)) < 0); | |
24888 | sign2 = 0x8000 & val; | |
24889 | SET_CFLG (sign != 0); | |
24890 | COPY_CARRY; | |
24891 | SET_VFLG (GET_VFLG | (sign2 != sign)); | |
24892 | m68k_write_memory_16(dataa,val); | |
24893 | }}}}m68k_incpc(4); | |
24894 | return 16; | |
24895 | } | |
24896 | unsigned long CPUFUNC(op_e1f0_4)(uint32_t opcode) /* ASLW */ | |
24897 | { | |
24898 | uint32_t srcreg = (opcode & 7); | |
24899 | OpcodeFamily = 73; CurrentInstrCycles = 18; | |
24900 | {{ uint32_t dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
24901 | BusCyclePenalty += 2; | |
24902 | { int16_t data = m68k_read_memory_16(dataa); | |
24903 | { uint32_t val = (uint16_t)data; | |
24904 | uint32_t sign = 0x8000 & val; | |
24905 | uint32_t sign2; | |
24906 | val <<= 1; | |
24907 | CLEAR_CZNV; | |
24908 | SET_ZFLG (((int16_t)(val)) == 0); | |
24909 | SET_NFLG (((int16_t)(val)) < 0); | |
24910 | sign2 = 0x8000 & val; | |
24911 | SET_CFLG (sign != 0); | |
24912 | COPY_CARRY; | |
24913 | SET_VFLG (GET_VFLG | (sign2 != sign)); | |
24914 | m68k_write_memory_16(dataa,val); | |
24915 | }}}}m68k_incpc(4); | |
24916 | return 18; | |
24917 | } | |
24918 | unsigned long CPUFUNC(op_e1f8_4)(uint32_t opcode) /* ASLW */ | |
24919 | { | |
24920 | OpcodeFamily = 73; CurrentInstrCycles = 16; | |
24921 | {{ uint32_t dataa = (int32_t)(int16_t)get_iword(2); | |
24922 | { int16_t data = m68k_read_memory_16(dataa); | |
24923 | { uint32_t val = (uint16_t)data; | |
24924 | uint32_t sign = 0x8000 & val; | |
24925 | uint32_t sign2; | |
24926 | val <<= 1; | |
24927 | CLEAR_CZNV; | |
24928 | SET_ZFLG (((int16_t)(val)) == 0); | |
24929 | SET_NFLG (((int16_t)(val)) < 0); | |
24930 | sign2 = 0x8000 & val; | |
24931 | SET_CFLG (sign != 0); | |
24932 | COPY_CARRY; | |
24933 | SET_VFLG (GET_VFLG | (sign2 != sign)); | |
24934 | m68k_write_memory_16(dataa,val); | |
24935 | }}}}m68k_incpc(4); | |
24936 | return 16; | |
24937 | } | |
24938 | unsigned long CPUFUNC(op_e1f9_4)(uint32_t opcode) /* ASLW */ | |
24939 | { | |
24940 | OpcodeFamily = 73; CurrentInstrCycles = 20; | |
24941 | {{ uint32_t dataa = get_ilong(2); | |
24942 | { int16_t data = m68k_read_memory_16(dataa); | |
24943 | { uint32_t val = (uint16_t)data; | |
24944 | uint32_t sign = 0x8000 & val; | |
24945 | uint32_t sign2; | |
24946 | val <<= 1; | |
24947 | CLEAR_CZNV; | |
24948 | SET_ZFLG (((int16_t)(val)) == 0); | |
24949 | SET_NFLG (((int16_t)(val)) < 0); | |
24950 | sign2 = 0x8000 & val; | |
24951 | SET_CFLG (sign != 0); | |
24952 | COPY_CARRY; | |
24953 | SET_VFLG (GET_VFLG | (sign2 != sign)); | |
24954 | m68k_write_memory_16(dataa,val); | |
24955 | }}}}m68k_incpc(6); | |
24956 | return 20; | |
24957 | } | |
24958 | unsigned long CPUFUNC(op_e2d0_4)(uint32_t opcode) /* LSRW */ | |
24959 | { | |
24960 | uint32_t srcreg = (opcode & 7); | |
24961 | OpcodeFamily = 74; CurrentInstrCycles = 12; | |
24962 | {{ uint32_t dataa = m68k_areg(regs, srcreg); | |
24963 | { int16_t data = m68k_read_memory_16(dataa); | |
24964 | { uint32_t val = (uint16_t)data; | |
24965 | uint32_t carry = val & 1; | |
24966 | val >>= 1; | |
24967 | CLEAR_CZNV; | |
24968 | SET_ZFLG (((int16_t)(val)) == 0); | |
24969 | SET_NFLG (((int16_t)(val)) < 0); | |
24970 | SET_CFLG (carry); | |
24971 | COPY_CARRY; | |
24972 | m68k_write_memory_16(dataa,val); | |
24973 | }}}}m68k_incpc(2); | |
24974 | return 12; | |
24975 | } | |
24976 | unsigned long CPUFUNC(op_e2d8_4)(uint32_t opcode) /* LSRW */ | |
24977 | { | |
24978 | uint32_t srcreg = (opcode & 7); | |
24979 | OpcodeFamily = 74; CurrentInstrCycles = 12; | |
24980 | {{ uint32_t dataa = m68k_areg(regs, srcreg); | |
24981 | { int16_t data = m68k_read_memory_16(dataa); | |
24982 | m68k_areg(regs, srcreg) += 2; | |
24983 | { uint32_t val = (uint16_t)data; | |
24984 | uint32_t carry = val & 1; | |
24985 | val >>= 1; | |
24986 | CLEAR_CZNV; | |
24987 | SET_ZFLG (((int16_t)(val)) == 0); | |
24988 | SET_NFLG (((int16_t)(val)) < 0); | |
24989 | SET_CFLG (carry); | |
24990 | COPY_CARRY; | |
24991 | m68k_write_memory_16(dataa,val); | |
24992 | }}}}m68k_incpc(2); | |
24993 | return 12; | |
24994 | } | |
24995 | unsigned long CPUFUNC(op_e2e0_4)(uint32_t opcode) /* LSRW */ | |
24996 | { | |
24997 | uint32_t srcreg = (opcode & 7); | |
24998 | OpcodeFamily = 74; CurrentInstrCycles = 14; | |
24999 | {{ uint32_t dataa = m68k_areg(regs, srcreg) - 2; | |
25000 | { int16_t data = m68k_read_memory_16(dataa); | |
25001 | m68k_areg (regs, srcreg) = dataa; | |
25002 | { uint32_t val = (uint16_t)data; | |
25003 | uint32_t carry = val & 1; | |
25004 | val >>= 1; | |
25005 | CLEAR_CZNV; | |
25006 | SET_ZFLG (((int16_t)(val)) == 0); | |
25007 | SET_NFLG (((int16_t)(val)) < 0); | |
25008 | SET_CFLG (carry); | |
25009 | COPY_CARRY; | |
25010 | m68k_write_memory_16(dataa,val); | |
25011 | }}}}m68k_incpc(2); | |
25012 | return 14; | |
25013 | } | |
25014 | unsigned long CPUFUNC(op_e2e8_4)(uint32_t opcode) /* LSRW */ | |
25015 | { | |
25016 | uint32_t srcreg = (opcode & 7); | |
25017 | OpcodeFamily = 74; CurrentInstrCycles = 16; | |
25018 | {{ uint32_t dataa = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
25019 | { int16_t data = m68k_read_memory_16(dataa); | |
25020 | { uint32_t val = (uint16_t)data; | |
25021 | uint32_t carry = val & 1; | |
25022 | val >>= 1; | |
25023 | CLEAR_CZNV; | |
25024 | SET_ZFLG (((int16_t)(val)) == 0); | |
25025 | SET_NFLG (((int16_t)(val)) < 0); | |
25026 | SET_CFLG (carry); | |
25027 | COPY_CARRY; | |
25028 | m68k_write_memory_16(dataa,val); | |
25029 | }}}}m68k_incpc(4); | |
25030 | return 16; | |
25031 | } | |
25032 | unsigned long CPUFUNC(op_e2f0_4)(uint32_t opcode) /* LSRW */ | |
25033 | { | |
25034 | uint32_t srcreg = (opcode & 7); | |
25035 | OpcodeFamily = 74; CurrentInstrCycles = 18; | |
25036 | {{ uint32_t dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
25037 | BusCyclePenalty += 2; | |
25038 | { int16_t data = m68k_read_memory_16(dataa); | |
25039 | { uint32_t val = (uint16_t)data; | |
25040 | uint32_t carry = val & 1; | |
25041 | val >>= 1; | |
25042 | CLEAR_CZNV; | |
25043 | SET_ZFLG (((int16_t)(val)) == 0); | |
25044 | SET_NFLG (((int16_t)(val)) < 0); | |
25045 | SET_CFLG (carry); | |
25046 | COPY_CARRY; | |
25047 | m68k_write_memory_16(dataa,val); | |
25048 | }}}}m68k_incpc(4); | |
25049 | return 18; | |
25050 | } | |
25051 | unsigned long CPUFUNC(op_e2f8_4)(uint32_t opcode) /* LSRW */ | |
25052 | { | |
25053 | OpcodeFamily = 74; CurrentInstrCycles = 16; | |
25054 | {{ uint32_t dataa = (int32_t)(int16_t)get_iword(2); | |
25055 | { int16_t data = m68k_read_memory_16(dataa); | |
25056 | { uint32_t val = (uint16_t)data; | |
25057 | uint32_t carry = val & 1; | |
25058 | val >>= 1; | |
25059 | CLEAR_CZNV; | |
25060 | SET_ZFLG (((int16_t)(val)) == 0); | |
25061 | SET_NFLG (((int16_t)(val)) < 0); | |
25062 | SET_CFLG (carry); | |
25063 | COPY_CARRY; | |
25064 | m68k_write_memory_16(dataa,val); | |
25065 | }}}}m68k_incpc(4); | |
25066 | return 16; | |
25067 | } | |
25068 | unsigned long CPUFUNC(op_e2f9_4)(uint32_t opcode) /* LSRW */ | |
25069 | { | |
25070 | OpcodeFamily = 74; CurrentInstrCycles = 20; | |
25071 | {{ uint32_t dataa = get_ilong(2); | |
25072 | { int16_t data = m68k_read_memory_16(dataa); | |
25073 | { uint32_t val = (uint16_t)data; | |
25074 | uint32_t carry = val & 1; | |
25075 | val >>= 1; | |
25076 | CLEAR_CZNV; | |
25077 | SET_ZFLG (((int16_t)(val)) == 0); | |
25078 | SET_NFLG (((int16_t)(val)) < 0); | |
25079 | SET_CFLG (carry); | |
25080 | COPY_CARRY; | |
25081 | m68k_write_memory_16(dataa,val); | |
25082 | }}}}m68k_incpc(6); | |
25083 | return 20; | |
25084 | } | |
25085 | unsigned long CPUFUNC(op_e3d0_4)(uint32_t opcode) /* LSLW */ | |
25086 | { | |
25087 | uint32_t srcreg = (opcode & 7); | |
25088 | OpcodeFamily = 75; CurrentInstrCycles = 12; | |
25089 | {{ uint32_t dataa = m68k_areg(regs, srcreg); | |
25090 | { int16_t data = m68k_read_memory_16(dataa); | |
25091 | { uint16_t val = data; | |
25092 | uint32_t carry = val & 0x8000; | |
25093 | val <<= 1; | |
25094 | CLEAR_CZNV; | |
25095 | SET_ZFLG (((int16_t)(val)) == 0); | |
25096 | SET_NFLG (((int16_t)(val)) < 0); | |
25097 | SET_CFLG (carry >> 15); | |
25098 | COPY_CARRY; | |
25099 | m68k_write_memory_16(dataa,val); | |
25100 | }}}}m68k_incpc(2); | |
25101 | return 12; | |
25102 | } | |
25103 | unsigned long CPUFUNC(op_e3d8_4)(uint32_t opcode) /* LSLW */ | |
25104 | { | |
25105 | uint32_t srcreg = (opcode & 7); | |
25106 | OpcodeFamily = 75; CurrentInstrCycles = 12; | |
25107 | {{ uint32_t dataa = m68k_areg(regs, srcreg); | |
25108 | { int16_t data = m68k_read_memory_16(dataa); | |
25109 | m68k_areg(regs, srcreg) += 2; | |
25110 | { uint16_t val = data; | |
25111 | uint32_t carry = val & 0x8000; | |
25112 | val <<= 1; | |
25113 | CLEAR_CZNV; | |
25114 | SET_ZFLG (((int16_t)(val)) == 0); | |
25115 | SET_NFLG (((int16_t)(val)) < 0); | |
25116 | SET_CFLG (carry >> 15); | |
25117 | COPY_CARRY; | |
25118 | m68k_write_memory_16(dataa,val); | |
25119 | }}}}m68k_incpc(2); | |
25120 | return 12; | |
25121 | } | |
25122 | unsigned long CPUFUNC(op_e3e0_4)(uint32_t opcode) /* LSLW */ | |
25123 | { | |
25124 | uint32_t srcreg = (opcode & 7); | |
25125 | OpcodeFamily = 75; CurrentInstrCycles = 14; | |
25126 | {{ uint32_t dataa = m68k_areg(regs, srcreg) - 2; | |
25127 | { int16_t data = m68k_read_memory_16(dataa); | |
25128 | m68k_areg (regs, srcreg) = dataa; | |
25129 | { uint16_t val = data; | |
25130 | uint32_t carry = val & 0x8000; | |
25131 | val <<= 1; | |
25132 | CLEAR_CZNV; | |
25133 | SET_ZFLG (((int16_t)(val)) == 0); | |
25134 | SET_NFLG (((int16_t)(val)) < 0); | |
25135 | SET_CFLG (carry >> 15); | |
25136 | COPY_CARRY; | |
25137 | m68k_write_memory_16(dataa,val); | |
25138 | }}}}m68k_incpc(2); | |
25139 | return 14; | |
25140 | } | |
25141 | unsigned long CPUFUNC(op_e3e8_4)(uint32_t opcode) /* LSLW */ | |
25142 | { | |
25143 | uint32_t srcreg = (opcode & 7); | |
25144 | OpcodeFamily = 75; CurrentInstrCycles = 16; | |
25145 | {{ uint32_t dataa = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
25146 | { int16_t data = m68k_read_memory_16(dataa); | |
25147 | { uint16_t val = data; | |
25148 | uint32_t carry = val & 0x8000; | |
25149 | val <<= 1; | |
25150 | CLEAR_CZNV; | |
25151 | SET_ZFLG (((int16_t)(val)) == 0); | |
25152 | SET_NFLG (((int16_t)(val)) < 0); | |
25153 | SET_CFLG (carry >> 15); | |
25154 | COPY_CARRY; | |
25155 | m68k_write_memory_16(dataa,val); | |
25156 | }}}}m68k_incpc(4); | |
25157 | return 16; | |
25158 | } | |
25159 | unsigned long CPUFUNC(op_e3f0_4)(uint32_t opcode) /* LSLW */ | |
25160 | { | |
25161 | uint32_t srcreg = (opcode & 7); | |
25162 | OpcodeFamily = 75; CurrentInstrCycles = 18; | |
25163 | {{ uint32_t dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
25164 | BusCyclePenalty += 2; | |
25165 | { int16_t data = m68k_read_memory_16(dataa); | |
25166 | { uint16_t val = data; | |
25167 | uint32_t carry = val & 0x8000; | |
25168 | val <<= 1; | |
25169 | CLEAR_CZNV; | |
25170 | SET_ZFLG (((int16_t)(val)) == 0); | |
25171 | SET_NFLG (((int16_t)(val)) < 0); | |
25172 | SET_CFLG (carry >> 15); | |
25173 | COPY_CARRY; | |
25174 | m68k_write_memory_16(dataa,val); | |
25175 | }}}}m68k_incpc(4); | |
25176 | return 18; | |
25177 | } | |
25178 | unsigned long CPUFUNC(op_e3f8_4)(uint32_t opcode) /* LSLW */ | |
25179 | { | |
25180 | OpcodeFamily = 75; CurrentInstrCycles = 16; | |
25181 | {{ uint32_t dataa = (int32_t)(int16_t)get_iword(2); | |
25182 | { int16_t data = m68k_read_memory_16(dataa); | |
25183 | { uint16_t val = data; | |
25184 | uint32_t carry = val & 0x8000; | |
25185 | val <<= 1; | |
25186 | CLEAR_CZNV; | |
25187 | SET_ZFLG (((int16_t)(val)) == 0); | |
25188 | SET_NFLG (((int16_t)(val)) < 0); | |
25189 | SET_CFLG (carry >> 15); | |
25190 | COPY_CARRY; | |
25191 | m68k_write_memory_16(dataa,val); | |
25192 | }}}}m68k_incpc(4); | |
25193 | return 16; | |
25194 | } | |
25195 | unsigned long CPUFUNC(op_e3f9_4)(uint32_t opcode) /* LSLW */ | |
25196 | { | |
25197 | OpcodeFamily = 75; CurrentInstrCycles = 20; | |
25198 | {{ uint32_t dataa = get_ilong(2); | |
25199 | { int16_t data = m68k_read_memory_16(dataa); | |
25200 | { uint16_t val = data; | |
25201 | uint32_t carry = val & 0x8000; | |
25202 | val <<= 1; | |
25203 | CLEAR_CZNV; | |
25204 | SET_ZFLG (((int16_t)(val)) == 0); | |
25205 | SET_NFLG (((int16_t)(val)) < 0); | |
25206 | SET_CFLG (carry >> 15); | |
25207 | COPY_CARRY; | |
25208 | m68k_write_memory_16(dataa,val); | |
25209 | }}}}m68k_incpc(6); | |
25210 | return 20; | |
25211 | } | |
25212 | unsigned long CPUFUNC(op_e4d0_4)(uint32_t opcode) /* ROXRW */ | |
25213 | { | |
25214 | uint32_t srcreg = (opcode & 7); | |
25215 | OpcodeFamily = 79; CurrentInstrCycles = 12; | |
25216 | {{ uint32_t dataa = m68k_areg(regs, srcreg); | |
25217 | { int16_t data = m68k_read_memory_16(dataa); | |
25218 | { uint16_t val = data; | |
25219 | uint32_t carry = val & 1; | |
25220 | val >>= 1; | |
25221 | if (GET_XFLG) val |= 0x8000; | |
25222 | CLEAR_CZNV; | |
25223 | SET_ZFLG (((int16_t)(val)) == 0); | |
25224 | SET_NFLG (((int16_t)(val)) < 0); | |
25225 | SET_CFLG (carry); | |
25226 | COPY_CARRY; | |
25227 | m68k_write_memory_16(dataa,val); | |
25228 | }}}}m68k_incpc(2); | |
25229 | return 12; | |
25230 | } | |
25231 | unsigned long CPUFUNC(op_e4d8_4)(uint32_t opcode) /* ROXRW */ | |
25232 | { | |
25233 | uint32_t srcreg = (opcode & 7); | |
25234 | OpcodeFamily = 79; CurrentInstrCycles = 12; | |
25235 | {{ uint32_t dataa = m68k_areg(regs, srcreg); | |
25236 | { int16_t data = m68k_read_memory_16(dataa); | |
25237 | m68k_areg(regs, srcreg) += 2; | |
25238 | { uint16_t val = data; | |
25239 | uint32_t carry = val & 1; | |
25240 | val >>= 1; | |
25241 | if (GET_XFLG) val |= 0x8000; | |
25242 | CLEAR_CZNV; | |
25243 | SET_ZFLG (((int16_t)(val)) == 0); | |
25244 | SET_NFLG (((int16_t)(val)) < 0); | |
25245 | SET_CFLG (carry); | |
25246 | COPY_CARRY; | |
25247 | m68k_write_memory_16(dataa,val); | |
25248 | }}}}m68k_incpc(2); | |
25249 | return 12; | |
25250 | } | |
25251 | unsigned long CPUFUNC(op_e4e0_4)(uint32_t opcode) /* ROXRW */ | |
25252 | { | |
25253 | uint32_t srcreg = (opcode & 7); | |
25254 | OpcodeFamily = 79; CurrentInstrCycles = 14; | |
25255 | {{ uint32_t dataa = m68k_areg(regs, srcreg) - 2; | |
25256 | { int16_t data = m68k_read_memory_16(dataa); | |
25257 | m68k_areg (regs, srcreg) = dataa; | |
25258 | { uint16_t val = data; | |
25259 | uint32_t carry = val & 1; | |
25260 | val >>= 1; | |
25261 | if (GET_XFLG) val |= 0x8000; | |
25262 | CLEAR_CZNV; | |
25263 | SET_ZFLG (((int16_t)(val)) == 0); | |
25264 | SET_NFLG (((int16_t)(val)) < 0); | |
25265 | SET_CFLG (carry); | |
25266 | COPY_CARRY; | |
25267 | m68k_write_memory_16(dataa,val); | |
25268 | }}}}m68k_incpc(2); | |
25269 | return 14; | |
25270 | } | |
25271 | unsigned long CPUFUNC(op_e4e8_4)(uint32_t opcode) /* ROXRW */ | |
25272 | { | |
25273 | uint32_t srcreg = (opcode & 7); | |
25274 | OpcodeFamily = 79; CurrentInstrCycles = 16; | |
25275 | {{ uint32_t dataa = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
25276 | { int16_t data = m68k_read_memory_16(dataa); | |
25277 | { uint16_t val = data; | |
25278 | uint32_t carry = val & 1; | |
25279 | val >>= 1; | |
25280 | if (GET_XFLG) val |= 0x8000; | |
25281 | CLEAR_CZNV; | |
25282 | SET_ZFLG (((int16_t)(val)) == 0); | |
25283 | SET_NFLG (((int16_t)(val)) < 0); | |
25284 | SET_CFLG (carry); | |
25285 | COPY_CARRY; | |
25286 | m68k_write_memory_16(dataa,val); | |
25287 | }}}}m68k_incpc(4); | |
25288 | return 16; | |
25289 | } | |
25290 | unsigned long CPUFUNC(op_e4f0_4)(uint32_t opcode) /* ROXRW */ | |
25291 | { | |
25292 | uint32_t srcreg = (opcode & 7); | |
25293 | OpcodeFamily = 79; CurrentInstrCycles = 18; | |
25294 | {{ uint32_t dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
25295 | BusCyclePenalty += 2; | |
25296 | { int16_t data = m68k_read_memory_16(dataa); | |
25297 | { uint16_t val = data; | |
25298 | uint32_t carry = val & 1; | |
25299 | val >>= 1; | |
25300 | if (GET_XFLG) val |= 0x8000; | |
25301 | CLEAR_CZNV; | |
25302 | SET_ZFLG (((int16_t)(val)) == 0); | |
25303 | SET_NFLG (((int16_t)(val)) < 0); | |
25304 | SET_CFLG (carry); | |
25305 | COPY_CARRY; | |
25306 | m68k_write_memory_16(dataa,val); | |
25307 | }}}}m68k_incpc(4); | |
25308 | return 18; | |
25309 | } | |
25310 | unsigned long CPUFUNC(op_e4f8_4)(uint32_t opcode) /* ROXRW */ | |
25311 | { | |
25312 | OpcodeFamily = 79; CurrentInstrCycles = 16; | |
25313 | {{ uint32_t dataa = (int32_t)(int16_t)get_iword(2); | |
25314 | { int16_t data = m68k_read_memory_16(dataa); | |
25315 | { uint16_t val = data; | |
25316 | uint32_t carry = val & 1; | |
25317 | val >>= 1; | |
25318 | if (GET_XFLG) val |= 0x8000; | |
25319 | CLEAR_CZNV; | |
25320 | SET_ZFLG (((int16_t)(val)) == 0); | |
25321 | SET_NFLG (((int16_t)(val)) < 0); | |
25322 | SET_CFLG (carry); | |
25323 | COPY_CARRY; | |
25324 | m68k_write_memory_16(dataa,val); | |
25325 | }}}}m68k_incpc(4); | |
25326 | return 16; | |
25327 | } | |
25328 | unsigned long CPUFUNC(op_e4f9_4)(uint32_t opcode) /* ROXRW */ | |
25329 | { | |
25330 | OpcodeFamily = 79; CurrentInstrCycles = 20; | |
25331 | {{ uint32_t dataa = get_ilong(2); | |
25332 | { int16_t data = m68k_read_memory_16(dataa); | |
25333 | { uint16_t val = data; | |
25334 | uint32_t carry = val & 1; | |
25335 | val >>= 1; | |
25336 | if (GET_XFLG) val |= 0x8000; | |
25337 | CLEAR_CZNV; | |
25338 | SET_ZFLG (((int16_t)(val)) == 0); | |
25339 | SET_NFLG (((int16_t)(val)) < 0); | |
25340 | SET_CFLG (carry); | |
25341 | COPY_CARRY; | |
25342 | m68k_write_memory_16(dataa,val); | |
25343 | }}}}m68k_incpc(6); | |
25344 | return 20; | |
25345 | } | |
25346 | unsigned long CPUFUNC(op_e5d0_4)(uint32_t opcode) /* ROXLW */ | |
25347 | { | |
25348 | uint32_t srcreg = (opcode & 7); | |
25349 | OpcodeFamily = 78; CurrentInstrCycles = 12; | |
25350 | {{ uint32_t dataa = m68k_areg(regs, srcreg); | |
25351 | { int16_t data = m68k_read_memory_16(dataa); | |
25352 | { uint16_t val = data; | |
25353 | uint32_t carry = val & 0x8000; | |
25354 | val <<= 1; | |
25355 | if (GET_XFLG) val |= 1; | |
25356 | CLEAR_CZNV; | |
25357 | SET_ZFLG (((int16_t)(val)) == 0); | |
25358 | SET_NFLG (((int16_t)(val)) < 0); | |
25359 | SET_CFLG (carry >> 15); | |
25360 | COPY_CARRY; | |
25361 | m68k_write_memory_16(dataa,val); | |
25362 | }}}}m68k_incpc(2); | |
25363 | return 12; | |
25364 | } | |
25365 | unsigned long CPUFUNC(op_e5d8_4)(uint32_t opcode) /* ROXLW */ | |
25366 | { | |
25367 | uint32_t srcreg = (opcode & 7); | |
25368 | OpcodeFamily = 78; CurrentInstrCycles = 12; | |
25369 | {{ uint32_t dataa = m68k_areg(regs, srcreg); | |
25370 | { int16_t data = m68k_read_memory_16(dataa); | |
25371 | m68k_areg(regs, srcreg) += 2; | |
25372 | { uint16_t val = data; | |
25373 | uint32_t carry = val & 0x8000; | |
25374 | val <<= 1; | |
25375 | if (GET_XFLG) val |= 1; | |
25376 | CLEAR_CZNV; | |
25377 | SET_ZFLG (((int16_t)(val)) == 0); | |
25378 | SET_NFLG (((int16_t)(val)) < 0); | |
25379 | SET_CFLG (carry >> 15); | |
25380 | COPY_CARRY; | |
25381 | m68k_write_memory_16(dataa,val); | |
25382 | }}}}m68k_incpc(2); | |
25383 | return 12; | |
25384 | } | |
25385 | unsigned long CPUFUNC(op_e5e0_4)(uint32_t opcode) /* ROXLW */ | |
25386 | { | |
25387 | uint32_t srcreg = (opcode & 7); | |
25388 | OpcodeFamily = 78; CurrentInstrCycles = 14; | |
25389 | {{ uint32_t dataa = m68k_areg(regs, srcreg) - 2; | |
25390 | { int16_t data = m68k_read_memory_16(dataa); | |
25391 | m68k_areg (regs, srcreg) = dataa; | |
25392 | { uint16_t val = data; | |
25393 | uint32_t carry = val & 0x8000; | |
25394 | val <<= 1; | |
25395 | if (GET_XFLG) val |= 1; | |
25396 | CLEAR_CZNV; | |
25397 | SET_ZFLG (((int16_t)(val)) == 0); | |
25398 | SET_NFLG (((int16_t)(val)) < 0); | |
25399 | SET_CFLG (carry >> 15); | |
25400 | COPY_CARRY; | |
25401 | m68k_write_memory_16(dataa,val); | |
25402 | }}}}m68k_incpc(2); | |
25403 | return 14; | |
25404 | } | |
25405 | unsigned long CPUFUNC(op_e5e8_4)(uint32_t opcode) /* ROXLW */ | |
25406 | { | |
25407 | uint32_t srcreg = (opcode & 7); | |
25408 | OpcodeFamily = 78; CurrentInstrCycles = 16; | |
25409 | {{ uint32_t dataa = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
25410 | { int16_t data = m68k_read_memory_16(dataa); | |
25411 | { uint16_t val = data; | |
25412 | uint32_t carry = val & 0x8000; | |
25413 | val <<= 1; | |
25414 | if (GET_XFLG) val |= 1; | |
25415 | CLEAR_CZNV; | |
25416 | SET_ZFLG (((int16_t)(val)) == 0); | |
25417 | SET_NFLG (((int16_t)(val)) < 0); | |
25418 | SET_CFLG (carry >> 15); | |
25419 | COPY_CARRY; | |
25420 | m68k_write_memory_16(dataa,val); | |
25421 | }}}}m68k_incpc(4); | |
25422 | return 16; | |
25423 | } | |
25424 | unsigned long CPUFUNC(op_e5f0_4)(uint32_t opcode) /* ROXLW */ | |
25425 | { | |
25426 | uint32_t srcreg = (opcode & 7); | |
25427 | OpcodeFamily = 78; CurrentInstrCycles = 18; | |
25428 | {{ uint32_t dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
25429 | BusCyclePenalty += 2; | |
25430 | { int16_t data = m68k_read_memory_16(dataa); | |
25431 | { uint16_t val = data; | |
25432 | uint32_t carry = val & 0x8000; | |
25433 | val <<= 1; | |
25434 | if (GET_XFLG) val |= 1; | |
25435 | CLEAR_CZNV; | |
25436 | SET_ZFLG (((int16_t)(val)) == 0); | |
25437 | SET_NFLG (((int16_t)(val)) < 0); | |
25438 | SET_CFLG (carry >> 15); | |
25439 | COPY_CARRY; | |
25440 | m68k_write_memory_16(dataa,val); | |
25441 | }}}}m68k_incpc(4); | |
25442 | return 18; | |
25443 | } | |
25444 | unsigned long CPUFUNC(op_e5f8_4)(uint32_t opcode) /* ROXLW */ | |
25445 | { | |
25446 | OpcodeFamily = 78; CurrentInstrCycles = 16; | |
25447 | {{ uint32_t dataa = (int32_t)(int16_t)get_iword(2); | |
25448 | { int16_t data = m68k_read_memory_16(dataa); | |
25449 | { uint16_t val = data; | |
25450 | uint32_t carry = val & 0x8000; | |
25451 | val <<= 1; | |
25452 | if (GET_XFLG) val |= 1; | |
25453 | CLEAR_CZNV; | |
25454 | SET_ZFLG (((int16_t)(val)) == 0); | |
25455 | SET_NFLG (((int16_t)(val)) < 0); | |
25456 | SET_CFLG (carry >> 15); | |
25457 | COPY_CARRY; | |
25458 | m68k_write_memory_16(dataa,val); | |
25459 | }}}}m68k_incpc(4); | |
25460 | return 16; | |
25461 | } | |
25462 | unsigned long CPUFUNC(op_e5f9_4)(uint32_t opcode) /* ROXLW */ | |
25463 | { | |
25464 | OpcodeFamily = 78; CurrentInstrCycles = 20; | |
25465 | {{ uint32_t dataa = get_ilong(2); | |
25466 | { int16_t data = m68k_read_memory_16(dataa); | |
25467 | { uint16_t val = data; | |
25468 | uint32_t carry = val & 0x8000; | |
25469 | val <<= 1; | |
25470 | if (GET_XFLG) val |= 1; | |
25471 | CLEAR_CZNV; | |
25472 | SET_ZFLG (((int16_t)(val)) == 0); | |
25473 | SET_NFLG (((int16_t)(val)) < 0); | |
25474 | SET_CFLG (carry >> 15); | |
25475 | COPY_CARRY; | |
25476 | m68k_write_memory_16(dataa,val); | |
25477 | }}}}m68k_incpc(6); | |
25478 | return 20; | |
25479 | } | |
25480 | unsigned long CPUFUNC(op_e6d0_4)(uint32_t opcode) /* RORW */ | |
25481 | { | |
25482 | uint32_t srcreg = (opcode & 7); | |
25483 | OpcodeFamily = 77; CurrentInstrCycles = 12; | |
25484 | {{ uint32_t dataa = m68k_areg(regs, srcreg); | |
25485 | { int16_t data = m68k_read_memory_16(dataa); | |
25486 | { uint16_t val = data; | |
25487 | uint32_t carry = val & 1; | |
25488 | val >>= 1; | |
25489 | if (carry) val |= 0x8000; | |
25490 | CLEAR_CZNV; | |
25491 | SET_ZFLG (((int16_t)(val)) == 0); | |
25492 | SET_NFLG (((int16_t)(val)) < 0); | |
25493 | SET_CFLG (carry); | |
25494 | m68k_write_memory_16(dataa,val); | |
25495 | }}}}m68k_incpc(2); | |
25496 | return 12; | |
25497 | } | |
25498 | unsigned long CPUFUNC(op_e6d8_4)(uint32_t opcode) /* RORW */ | |
25499 | { | |
25500 | uint32_t srcreg = (opcode & 7); | |
25501 | OpcodeFamily = 77; CurrentInstrCycles = 12; | |
25502 | {{ uint32_t dataa = m68k_areg(regs, srcreg); | |
25503 | { int16_t data = m68k_read_memory_16(dataa); | |
25504 | m68k_areg(regs, srcreg) += 2; | |
25505 | { uint16_t val = data; | |
25506 | uint32_t carry = val & 1; | |
25507 | val >>= 1; | |
25508 | if (carry) val |= 0x8000; | |
25509 | CLEAR_CZNV; | |
25510 | SET_ZFLG (((int16_t)(val)) == 0); | |
25511 | SET_NFLG (((int16_t)(val)) < 0); | |
25512 | SET_CFLG (carry); | |
25513 | m68k_write_memory_16(dataa,val); | |
25514 | }}}}m68k_incpc(2); | |
25515 | return 12; | |
25516 | } | |
25517 | unsigned long CPUFUNC(op_e6e0_4)(uint32_t opcode) /* RORW */ | |
25518 | { | |
25519 | uint32_t srcreg = (opcode & 7); | |
25520 | OpcodeFamily = 77; CurrentInstrCycles = 14; | |
25521 | {{ uint32_t dataa = m68k_areg(regs, srcreg) - 2; | |
25522 | { int16_t data = m68k_read_memory_16(dataa); | |
25523 | m68k_areg (regs, srcreg) = dataa; | |
25524 | { uint16_t val = data; | |
25525 | uint32_t carry = val & 1; | |
25526 | val >>= 1; | |
25527 | if (carry) val |= 0x8000; | |
25528 | CLEAR_CZNV; | |
25529 | SET_ZFLG (((int16_t)(val)) == 0); | |
25530 | SET_NFLG (((int16_t)(val)) < 0); | |
25531 | SET_CFLG (carry); | |
25532 | m68k_write_memory_16(dataa,val); | |
25533 | }}}}m68k_incpc(2); | |
25534 | return 14; | |
25535 | } | |
25536 | unsigned long CPUFUNC(op_e6e8_4)(uint32_t opcode) /* RORW */ | |
25537 | { | |
25538 | uint32_t srcreg = (opcode & 7); | |
25539 | OpcodeFamily = 77; CurrentInstrCycles = 16; | |
25540 | {{ uint32_t dataa = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
25541 | { int16_t data = m68k_read_memory_16(dataa); | |
25542 | { uint16_t val = data; | |
25543 | uint32_t carry = val & 1; | |
25544 | val >>= 1; | |
25545 | if (carry) val |= 0x8000; | |
25546 | CLEAR_CZNV; | |
25547 | SET_ZFLG (((int16_t)(val)) == 0); | |
25548 | SET_NFLG (((int16_t)(val)) < 0); | |
25549 | SET_CFLG (carry); | |
25550 | m68k_write_memory_16(dataa,val); | |
25551 | }}}}m68k_incpc(4); | |
25552 | return 16; | |
25553 | } | |
25554 | unsigned long CPUFUNC(op_e6f0_4)(uint32_t opcode) /* RORW */ | |
25555 | { | |
25556 | uint32_t srcreg = (opcode & 7); | |
25557 | OpcodeFamily = 77; CurrentInstrCycles = 18; | |
25558 | {{ uint32_t dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
25559 | BusCyclePenalty += 2; | |
25560 | { int16_t data = m68k_read_memory_16(dataa); | |
25561 | { uint16_t val = data; | |
25562 | uint32_t carry = val & 1; | |
25563 | val >>= 1; | |
25564 | if (carry) val |= 0x8000; | |
25565 | CLEAR_CZNV; | |
25566 | SET_ZFLG (((int16_t)(val)) == 0); | |
25567 | SET_NFLG (((int16_t)(val)) < 0); | |
25568 | SET_CFLG (carry); | |
25569 | m68k_write_memory_16(dataa,val); | |
25570 | }}}}m68k_incpc(4); | |
25571 | return 18; | |
25572 | } | |
25573 | unsigned long CPUFUNC(op_e6f8_4)(uint32_t opcode) /* RORW */ | |
25574 | { | |
25575 | OpcodeFamily = 77; CurrentInstrCycles = 16; | |
25576 | {{ uint32_t dataa = (int32_t)(int16_t)get_iword(2); | |
25577 | { int16_t data = m68k_read_memory_16(dataa); | |
25578 | { uint16_t val = data; | |
25579 | uint32_t carry = val & 1; | |
25580 | val >>= 1; | |
25581 | if (carry) val |= 0x8000; | |
25582 | CLEAR_CZNV; | |
25583 | SET_ZFLG (((int16_t)(val)) == 0); | |
25584 | SET_NFLG (((int16_t)(val)) < 0); | |
25585 | SET_CFLG (carry); | |
25586 | m68k_write_memory_16(dataa,val); | |
25587 | }}}}m68k_incpc(4); | |
25588 | return 16; | |
25589 | } | |
25590 | unsigned long CPUFUNC(op_e6f9_4)(uint32_t opcode) /* RORW */ | |
25591 | { | |
25592 | OpcodeFamily = 77; CurrentInstrCycles = 20; | |
25593 | {{ uint32_t dataa = get_ilong(2); | |
25594 | { int16_t data = m68k_read_memory_16(dataa); | |
25595 | { uint16_t val = data; | |
25596 | uint32_t carry = val & 1; | |
25597 | val >>= 1; | |
25598 | if (carry) val |= 0x8000; | |
25599 | CLEAR_CZNV; | |
25600 | SET_ZFLG (((int16_t)(val)) == 0); | |
25601 | SET_NFLG (((int16_t)(val)) < 0); | |
25602 | SET_CFLG (carry); | |
25603 | m68k_write_memory_16(dataa,val); | |
25604 | }}}}m68k_incpc(6); | |
25605 | return 20; | |
25606 | } | |
25607 | unsigned long CPUFUNC(op_e7d0_4)(uint32_t opcode) /* ROLW */ | |
25608 | { | |
25609 | uint32_t srcreg = (opcode & 7); | |
25610 | OpcodeFamily = 76; CurrentInstrCycles = 12; | |
25611 | {{ uint32_t dataa = m68k_areg(regs, srcreg); | |
25612 | { int16_t data = m68k_read_memory_16(dataa); | |
25613 | { uint16_t val = data; | |
25614 | uint32_t carry = val & 0x8000; | |
25615 | val <<= 1; | |
25616 | if (carry) val |= 1; | |
25617 | CLEAR_CZNV; | |
25618 | SET_ZFLG (((int16_t)(val)) == 0); | |
25619 | SET_NFLG (((int16_t)(val)) < 0); | |
25620 | SET_CFLG (carry >> 15); | |
25621 | m68k_write_memory_16(dataa,val); | |
25622 | }}}}m68k_incpc(2); | |
25623 | return 12; | |
25624 | } | |
25625 | unsigned long CPUFUNC(op_e7d8_4)(uint32_t opcode) /* ROLW */ | |
25626 | { | |
25627 | uint32_t srcreg = (opcode & 7); | |
25628 | OpcodeFamily = 76; CurrentInstrCycles = 12; | |
25629 | {{ uint32_t dataa = m68k_areg(regs, srcreg); | |
25630 | { int16_t data = m68k_read_memory_16(dataa); | |
25631 | m68k_areg(regs, srcreg) += 2; | |
25632 | { uint16_t val = data; | |
25633 | uint32_t carry = val & 0x8000; | |
25634 | val <<= 1; | |
25635 | if (carry) val |= 1; | |
25636 | CLEAR_CZNV; | |
25637 | SET_ZFLG (((int16_t)(val)) == 0); | |
25638 | SET_NFLG (((int16_t)(val)) < 0); | |
25639 | SET_CFLG (carry >> 15); | |
25640 | m68k_write_memory_16(dataa,val); | |
25641 | }}}}m68k_incpc(2); | |
25642 | return 12; | |
25643 | } | |
25644 | unsigned long CPUFUNC(op_e7e0_4)(uint32_t opcode) /* ROLW */ | |
25645 | { | |
25646 | uint32_t srcreg = (opcode & 7); | |
25647 | OpcodeFamily = 76; CurrentInstrCycles = 14; | |
25648 | {{ uint32_t dataa = m68k_areg(regs, srcreg) - 2; | |
25649 | { int16_t data = m68k_read_memory_16(dataa); | |
25650 | m68k_areg (regs, srcreg) = dataa; | |
25651 | { uint16_t val = data; | |
25652 | uint32_t carry = val & 0x8000; | |
25653 | val <<= 1; | |
25654 | if (carry) val |= 1; | |
25655 | CLEAR_CZNV; | |
25656 | SET_ZFLG (((int16_t)(val)) == 0); | |
25657 | SET_NFLG (((int16_t)(val)) < 0); | |
25658 | SET_CFLG (carry >> 15); | |
25659 | m68k_write_memory_16(dataa,val); | |
25660 | }}}}m68k_incpc(2); | |
25661 | return 14; | |
25662 | } | |
25663 | unsigned long CPUFUNC(op_e7e8_4)(uint32_t opcode) /* ROLW */ | |
25664 | { | |
25665 | uint32_t srcreg = (opcode & 7); | |
25666 | OpcodeFamily = 76; CurrentInstrCycles = 16; | |
25667 | {{ uint32_t dataa = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword(2); | |
25668 | { int16_t data = m68k_read_memory_16(dataa); | |
25669 | { uint16_t val = data; | |
25670 | uint32_t carry = val & 0x8000; | |
25671 | val <<= 1; | |
25672 | if (carry) val |= 1; | |
25673 | CLEAR_CZNV; | |
25674 | SET_ZFLG (((int16_t)(val)) == 0); | |
25675 | SET_NFLG (((int16_t)(val)) < 0); | |
25676 | SET_CFLG (carry >> 15); | |
25677 | m68k_write_memory_16(dataa,val); | |
25678 | }}}}m68k_incpc(4); | |
25679 | return 16; | |
25680 | } | |
25681 | unsigned long CPUFUNC(op_e7f0_4)(uint32_t opcode) /* ROLW */ | |
25682 | { | |
25683 | uint32_t srcreg = (opcode & 7); | |
25684 | OpcodeFamily = 76; CurrentInstrCycles = 18; | |
25685 | {{ uint32_t dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword(2)); | |
25686 | BusCyclePenalty += 2; | |
25687 | { int16_t data = m68k_read_memory_16(dataa); | |
25688 | { uint16_t val = data; | |
25689 | uint32_t carry = val & 0x8000; | |
25690 | val <<= 1; | |
25691 | if (carry) val |= 1; | |
25692 | CLEAR_CZNV; | |
25693 | SET_ZFLG (((int16_t)(val)) == 0); | |
25694 | SET_NFLG (((int16_t)(val)) < 0); | |
25695 | SET_CFLG (carry >> 15); | |
25696 | m68k_write_memory_16(dataa,val); | |
25697 | }}}}m68k_incpc(4); | |
25698 | return 18; | |
25699 | } | |
25700 | unsigned long CPUFUNC(op_e7f8_4)(uint32_t opcode) /* ROLW */ | |
25701 | { | |
25702 | OpcodeFamily = 76; CurrentInstrCycles = 16; | |
25703 | {{ uint32_t dataa = (int32_t)(int16_t)get_iword(2); | |
25704 | { int16_t data = m68k_read_memory_16(dataa); | |
25705 | { uint16_t val = data; | |
25706 | uint32_t carry = val & 0x8000; | |
25707 | val <<= 1; | |
25708 | if (carry) val |= 1; | |
25709 | CLEAR_CZNV; | |
25710 | SET_ZFLG (((int16_t)(val)) == 0); | |
25711 | SET_NFLG (((int16_t)(val)) < 0); | |
25712 | SET_CFLG (carry >> 15); | |
25713 | m68k_write_memory_16(dataa,val); | |
25714 | }}}}m68k_incpc(4); | |
25715 | return 16; | |
25716 | } | |
25717 | unsigned long CPUFUNC(op_e7f9_4)(uint32_t opcode) /* ROLW */ | |
25718 | { | |
25719 | OpcodeFamily = 76; CurrentInstrCycles = 20; | |
25720 | {{ uint32_t dataa = get_ilong(2); | |
25721 | { int16_t data = m68k_read_memory_16(dataa); | |
25722 | { uint16_t val = data; | |
25723 | uint32_t carry = val & 0x8000; | |
25724 | val <<= 1; | |
25725 | if (carry) val |= 1; | |
25726 | CLEAR_CZNV; | |
25727 | SET_ZFLG (((int16_t)(val)) == 0); | |
25728 | SET_NFLG (((int16_t)(val)) < 0); | |
25729 | SET_CFLG (carry >> 15); | |
25730 | m68k_write_memory_16(dataa,val); | |
25731 | }}}}m68k_incpc(6); | |
25732 | return 20; | |
25733 | } | |
25734 | #endif | |
25735 | ||
25736 | ||
25737 | #if !defined(PART_1) && !defined(PART_2) && !defined(PART_3) && !defined(PART_4) && !defined(PART_5) && !defined(PART_6) && !defined(PART_7) && !defined(PART_8) | |
25738 | #define PART_1 1 | |
25739 | #define PART_2 1 | |
25740 | #define PART_3 1 | |
25741 | #define PART_4 1 | |
25742 | #define PART_5 1 | |
25743 | #define PART_6 1 | |
25744 | #define PART_7 1 | |
25745 | #define PART_8 1 | |
25746 | #endif | |
25747 | ||
25748 | #ifdef PART_1 | |
25749 | unsigned long CPUFUNC(op_0_5)(uint32_t opcode) /* OR */ | |
25750 | { | |
25751 | uint32_t dstreg = opcode & 7; | |
25752 | OpcodeFamily = 1; CurrentInstrCycles = 8; | |
25753 | {{ int8_t src = get_ibyte_prefetch(2); | |
25754 | { int8_t dst = m68k_dreg(regs, dstreg); | |
25755 | src |= dst; | |
25756 | CLEAR_CZNV; | |
25757 | SET_ZFLG (((int8_t)(src)) == 0); | |
25758 | SET_NFLG (((int8_t)(src)) < 0); | |
25759 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
25760 | }}}m68k_incpc(4); | |
25761 | fill_prefetch_0 (); | |
25762 | return 8; | |
25763 | } | |
25764 | unsigned long CPUFUNC(op_10_5)(uint32_t opcode) /* OR */ | |
25765 | { | |
25766 | uint32_t dstreg = opcode & 7; | |
25767 | OpcodeFamily = 1; CurrentInstrCycles = 16; | |
25768 | {{ int8_t src = get_ibyte_prefetch(2); | |
25769 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
25770 | { int8_t dst = m68k_read_memory_8(dsta); | |
25771 | src |= dst; | |
25772 | CLEAR_CZNV; | |
25773 | SET_ZFLG (((int8_t)(src)) == 0); | |
25774 | SET_NFLG (((int8_t)(src)) < 0); | |
25775 | m68k_incpc(4); | |
25776 | fill_prefetch_0 (); | |
25777 | m68k_write_memory_8(dsta,src); | |
25778 | }}}}return 16; | |
25779 | } | |
25780 | unsigned long CPUFUNC(op_18_5)(uint32_t opcode) /* OR */ | |
25781 | { | |
25782 | uint32_t dstreg = opcode & 7; | |
25783 | OpcodeFamily = 1; CurrentInstrCycles = 16; | |
25784 | {{ int8_t src = get_ibyte_prefetch(2); | |
25785 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
25786 | { int8_t dst = m68k_read_memory_8(dsta); | |
25787 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
25788 | src |= dst; | |
25789 | CLEAR_CZNV; | |
25790 | SET_ZFLG (((int8_t)(src)) == 0); | |
25791 | SET_NFLG (((int8_t)(src)) < 0); | |
25792 | m68k_incpc(4); | |
25793 | fill_prefetch_0 (); | |
25794 | m68k_write_memory_8(dsta,src); | |
25795 | }}}}return 16; | |
25796 | } | |
25797 | unsigned long CPUFUNC(op_20_5)(uint32_t opcode) /* OR */ | |
25798 | { | |
25799 | uint32_t dstreg = opcode & 7; | |
25800 | OpcodeFamily = 1; CurrentInstrCycles = 18; | |
25801 | {{ int8_t src = get_ibyte_prefetch(2); | |
25802 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
25803 | { int8_t dst = m68k_read_memory_8(dsta); | |
25804 | m68k_areg (regs, dstreg) = dsta; | |
25805 | src |= dst; | |
25806 | CLEAR_CZNV; | |
25807 | SET_ZFLG (((int8_t)(src)) == 0); | |
25808 | SET_NFLG (((int8_t)(src)) < 0); | |
25809 | m68k_incpc(4); | |
25810 | fill_prefetch_0 (); | |
25811 | m68k_write_memory_8(dsta,src); | |
25812 | }}}}return 18; | |
25813 | } | |
25814 | unsigned long CPUFUNC(op_28_5)(uint32_t opcode) /* OR */ | |
25815 | { | |
25816 | uint32_t dstreg = opcode & 7; | |
25817 | OpcodeFamily = 1; CurrentInstrCycles = 20; | |
25818 | {{ int8_t src = get_ibyte_prefetch(2); | |
25819 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); | |
25820 | { int8_t dst = m68k_read_memory_8(dsta); | |
25821 | src |= dst; | |
25822 | CLEAR_CZNV; | |
25823 | SET_ZFLG (((int8_t)(src)) == 0); | |
25824 | SET_NFLG (((int8_t)(src)) < 0); | |
25825 | m68k_incpc(6); | |
25826 | fill_prefetch_0 (); | |
25827 | m68k_write_memory_8(dsta,src); | |
25828 | }}}}return 20; | |
25829 | } | |
25830 | unsigned long CPUFUNC(op_30_5)(uint32_t opcode) /* OR */ | |
25831 | { | |
25832 | uint32_t dstreg = opcode & 7; | |
25833 | OpcodeFamily = 1; CurrentInstrCycles = 22; | |
25834 | {{ int8_t src = get_ibyte_prefetch(2); | |
25835 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); | |
25836 | BusCyclePenalty += 2; | |
25837 | { int8_t dst = m68k_read_memory_8(dsta); | |
25838 | src |= dst; | |
25839 | CLEAR_CZNV; | |
25840 | SET_ZFLG (((int8_t)(src)) == 0); | |
25841 | SET_NFLG (((int8_t)(src)) < 0); | |
25842 | m68k_incpc(6); | |
25843 | fill_prefetch_0 (); | |
25844 | m68k_write_memory_8(dsta,src); | |
25845 | }}}}return 22; | |
25846 | } | |
25847 | unsigned long CPUFUNC(op_38_5)(uint32_t opcode) /* OR */ | |
25848 | { | |
25849 | OpcodeFamily = 1; CurrentInstrCycles = 20; | |
25850 | {{ int8_t src = get_ibyte_prefetch(2); | |
25851 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); | |
25852 | { int8_t dst = m68k_read_memory_8(dsta); | |
25853 | src |= dst; | |
25854 | CLEAR_CZNV; | |
25855 | SET_ZFLG (((int8_t)(src)) == 0); | |
25856 | SET_NFLG (((int8_t)(src)) < 0); | |
25857 | m68k_incpc(6); | |
25858 | fill_prefetch_0 (); | |
25859 | m68k_write_memory_8(dsta,src); | |
25860 | }}}}return 20; | |
25861 | } | |
25862 | unsigned long CPUFUNC(op_39_5)(uint32_t opcode) /* OR */ | |
25863 | { | |
25864 | OpcodeFamily = 1; CurrentInstrCycles = 24; | |
25865 | {{ int8_t src = get_ibyte_prefetch(2); | |
25866 | { uint32_t dsta = get_ilong_prefetch(4); | |
25867 | { int8_t dst = m68k_read_memory_8(dsta); | |
25868 | src |= dst; | |
25869 | CLEAR_CZNV; | |
25870 | SET_ZFLG (((int8_t)(src)) == 0); | |
25871 | SET_NFLG (((int8_t)(src)) < 0); | |
25872 | m68k_incpc(8); | |
25873 | fill_prefetch_0 (); | |
25874 | m68k_write_memory_8(dsta,src); | |
25875 | }}}}return 24; | |
25876 | } | |
25877 | unsigned long CPUFUNC(op_3c_5)(uint32_t opcode) /* ORSR */ | |
25878 | { | |
25879 | OpcodeFamily = 4; CurrentInstrCycles = 20; | |
25880 | { MakeSR(); | |
25881 | { int16_t src = get_iword_prefetch(2); | |
25882 | src &= 0xFF; | |
25883 | regs.sr |= src; | |
25884 | MakeFromSR(); | |
25885 | }}m68k_incpc(4); | |
25886 | fill_prefetch_0 (); | |
25887 | return 20; | |
25888 | } | |
25889 | unsigned long CPUFUNC(op_40_5)(uint32_t opcode) /* OR */ | |
25890 | { | |
25891 | uint32_t dstreg = opcode & 7; | |
25892 | OpcodeFamily = 1; CurrentInstrCycles = 8; | |
25893 | {{ int16_t src = get_iword_prefetch(2); | |
25894 | { int16_t dst = m68k_dreg(regs, dstreg); | |
25895 | src |= dst; | |
25896 | CLEAR_CZNV; | |
25897 | SET_ZFLG (((int16_t)(src)) == 0); | |
25898 | SET_NFLG (((int16_t)(src)) < 0); | |
25899 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
25900 | }}}m68k_incpc(4); | |
25901 | fill_prefetch_0 (); | |
25902 | return 8; | |
25903 | } | |
25904 | unsigned long CPUFUNC(op_50_5)(uint32_t opcode) /* OR */ | |
25905 | { | |
25906 | uint32_t dstreg = opcode & 7; | |
25907 | OpcodeFamily = 1; CurrentInstrCycles = 16; | |
25908 | {{ int16_t src = get_iword_prefetch(2); | |
25909 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
25910 | if ((dsta & 1) != 0) { | |
25911 | last_fault_for_exception_3 = dsta; | |
25912 | last_op_for_exception_3 = opcode; | |
25913 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
25914 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
25915 | goto endlabel1591; | |
25916 | } | |
25917 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
25918 | src |= dst; | |
25919 | CLEAR_CZNV; | |
25920 | SET_ZFLG (((int16_t)(src)) == 0); | |
25921 | SET_NFLG (((int16_t)(src)) < 0); | |
25922 | m68k_incpc(4); | |
25923 | fill_prefetch_0 (); | |
25924 | m68k_write_memory_16(dsta,src); | |
25925 | }}}}}endlabel1591: ; | |
25926 | return 16; | |
25927 | } | |
25928 | unsigned long CPUFUNC(op_58_5)(uint32_t opcode) /* OR */ | |
25929 | { | |
25930 | uint32_t dstreg = opcode & 7; | |
25931 | OpcodeFamily = 1; CurrentInstrCycles = 16; | |
25932 | {{ int16_t src = get_iword_prefetch(2); | |
25933 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
25934 | if ((dsta & 1) != 0) { | |
25935 | last_fault_for_exception_3 = dsta; | |
25936 | last_op_for_exception_3 = opcode; | |
25937 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
25938 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
25939 | goto endlabel1592; | |
25940 | } | |
25941 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
25942 | m68k_areg(regs, dstreg) += 2; | |
25943 | src |= dst; | |
25944 | CLEAR_CZNV; | |
25945 | SET_ZFLG (((int16_t)(src)) == 0); | |
25946 | SET_NFLG (((int16_t)(src)) < 0); | |
25947 | m68k_incpc(4); | |
25948 | fill_prefetch_0 (); | |
25949 | m68k_write_memory_16(dsta,src); | |
25950 | }}}}}endlabel1592: ; | |
25951 | return 16; | |
25952 | } | |
25953 | unsigned long CPUFUNC(op_60_5)(uint32_t opcode) /* OR */ | |
25954 | { | |
25955 | uint32_t dstreg = opcode & 7; | |
25956 | OpcodeFamily = 1; CurrentInstrCycles = 18; | |
25957 | {{ int16_t src = get_iword_prefetch(2); | |
25958 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
25959 | if ((dsta & 1) != 0) { | |
25960 | last_fault_for_exception_3 = dsta; | |
25961 | last_op_for_exception_3 = opcode; | |
25962 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
25963 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
25964 | goto endlabel1593; | |
25965 | } | |
25966 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
25967 | m68k_areg (regs, dstreg) = dsta; | |
25968 | src |= dst; | |
25969 | CLEAR_CZNV; | |
25970 | SET_ZFLG (((int16_t)(src)) == 0); | |
25971 | SET_NFLG (((int16_t)(src)) < 0); | |
25972 | m68k_incpc(4); | |
25973 | fill_prefetch_0 (); | |
25974 | m68k_write_memory_16(dsta,src); | |
25975 | }}}}}endlabel1593: ; | |
25976 | return 18; | |
25977 | } | |
25978 | unsigned long CPUFUNC(op_68_5)(uint32_t opcode) /* OR */ | |
25979 | { | |
25980 | uint32_t dstreg = opcode & 7; | |
25981 | OpcodeFamily = 1; CurrentInstrCycles = 20; | |
25982 | {{ int16_t src = get_iword_prefetch(2); | |
25983 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); | |
25984 | if ((dsta & 1) != 0) { | |
25985 | last_fault_for_exception_3 = dsta; | |
25986 | last_op_for_exception_3 = opcode; | |
25987 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
25988 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
25989 | goto endlabel1594; | |
25990 | } | |
25991 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
25992 | src |= dst; | |
25993 | CLEAR_CZNV; | |
25994 | SET_ZFLG (((int16_t)(src)) == 0); | |
25995 | SET_NFLG (((int16_t)(src)) < 0); | |
25996 | m68k_incpc(6); | |
25997 | fill_prefetch_0 (); | |
25998 | m68k_write_memory_16(dsta,src); | |
25999 | }}}}}endlabel1594: ; | |
26000 | return 20; | |
26001 | } | |
26002 | unsigned long CPUFUNC(op_70_5)(uint32_t opcode) /* OR */ | |
26003 | { | |
26004 | uint32_t dstreg = opcode & 7; | |
26005 | OpcodeFamily = 1; CurrentInstrCycles = 22; | |
26006 | {{ int16_t src = get_iword_prefetch(2); | |
26007 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); | |
26008 | BusCyclePenalty += 2; | |
26009 | if ((dsta & 1) != 0) { | |
26010 | last_fault_for_exception_3 = dsta; | |
26011 | last_op_for_exception_3 = opcode; | |
26012 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
26013 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
26014 | goto endlabel1595; | |
26015 | } | |
26016 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
26017 | src |= dst; | |
26018 | CLEAR_CZNV; | |
26019 | SET_ZFLG (((int16_t)(src)) == 0); | |
26020 | SET_NFLG (((int16_t)(src)) < 0); | |
26021 | m68k_incpc(6); | |
26022 | fill_prefetch_0 (); | |
26023 | m68k_write_memory_16(dsta,src); | |
26024 | }}}}}endlabel1595: ; | |
26025 | return 22; | |
26026 | } | |
26027 | unsigned long CPUFUNC(op_78_5)(uint32_t opcode) /* OR */ | |
26028 | { | |
26029 | OpcodeFamily = 1; CurrentInstrCycles = 20; | |
26030 | {{ int16_t src = get_iword_prefetch(2); | |
26031 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); | |
26032 | if ((dsta & 1) != 0) { | |
26033 | last_fault_for_exception_3 = dsta; | |
26034 | last_op_for_exception_3 = opcode; | |
26035 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
26036 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
26037 | goto endlabel1596; | |
26038 | } | |
26039 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
26040 | src |= dst; | |
26041 | CLEAR_CZNV; | |
26042 | SET_ZFLG (((int16_t)(src)) == 0); | |
26043 | SET_NFLG (((int16_t)(src)) < 0); | |
26044 | m68k_incpc(6); | |
26045 | fill_prefetch_0 (); | |
26046 | m68k_write_memory_16(dsta,src); | |
26047 | }}}}}endlabel1596: ; | |
26048 | return 20; | |
26049 | } | |
26050 | unsigned long CPUFUNC(op_79_5)(uint32_t opcode) /* OR */ | |
26051 | { | |
26052 | OpcodeFamily = 1; CurrentInstrCycles = 24; | |
26053 | {{ int16_t src = get_iword_prefetch(2); | |
26054 | { uint32_t dsta = get_ilong_prefetch(4); | |
26055 | if ((dsta & 1) != 0) { | |
26056 | last_fault_for_exception_3 = dsta; | |
26057 | last_op_for_exception_3 = opcode; | |
26058 | last_addr_for_exception_3 = m68k_getpc() + 8; | |
26059 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
26060 | goto endlabel1597; | |
26061 | } | |
26062 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
26063 | src |= dst; | |
26064 | CLEAR_CZNV; | |
26065 | SET_ZFLG (((int16_t)(src)) == 0); | |
26066 | SET_NFLG (((int16_t)(src)) < 0); | |
26067 | m68k_incpc(8); | |
26068 | fill_prefetch_0 (); | |
26069 | m68k_write_memory_16(dsta,src); | |
26070 | }}}}}endlabel1597: ; | |
26071 | return 24; | |
26072 | } | |
26073 | unsigned long CPUFUNC(op_7c_5)(uint32_t opcode) /* ORSR */ | |
26074 | { | |
26075 | OpcodeFamily = 4; CurrentInstrCycles = 20; | |
26076 | {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel1598; } | |
26077 | { MakeSR(); | |
26078 | { int16_t src = get_iword_prefetch(2); | |
26079 | regs.sr |= src; | |
26080 | MakeFromSR(); | |
26081 | }}}m68k_incpc(4); | |
26082 | fill_prefetch_0 (); | |
26083 | endlabel1598: ; | |
26084 | return 20; | |
26085 | } | |
26086 | unsigned long CPUFUNC(op_80_5)(uint32_t opcode) /* OR */ | |
26087 | { | |
26088 | uint32_t dstreg = opcode & 7; | |
26089 | OpcodeFamily = 1; CurrentInstrCycles = 16; | |
26090 | {{ int32_t src = get_ilong_prefetch(2); | |
26091 | { int32_t dst = m68k_dreg(regs, dstreg); | |
26092 | src |= dst; | |
26093 | CLEAR_CZNV; | |
26094 | SET_ZFLG (((int32_t)(src)) == 0); | |
26095 | SET_NFLG (((int32_t)(src)) < 0); | |
26096 | m68k_dreg(regs, dstreg) = (src); | |
26097 | }}}m68k_incpc(6); | |
26098 | fill_prefetch_0 (); | |
26099 | return 16; | |
26100 | } | |
26101 | unsigned long CPUFUNC(op_90_5)(uint32_t opcode) /* OR */ | |
26102 | { | |
26103 | uint32_t dstreg = opcode & 7; | |
26104 | OpcodeFamily = 1; CurrentInstrCycles = 28; | |
26105 | {{ int32_t src = get_ilong_prefetch(2); | |
26106 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
26107 | if ((dsta & 1) != 0) { | |
26108 | last_fault_for_exception_3 = dsta; | |
26109 | last_op_for_exception_3 = opcode; | |
26110 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
26111 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
26112 | goto endlabel1600; | |
26113 | } | |
26114 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
26115 | src |= dst; | |
26116 | CLEAR_CZNV; | |
26117 | SET_ZFLG (((int32_t)(src)) == 0); | |
26118 | SET_NFLG (((int32_t)(src)) < 0); | |
26119 | m68k_incpc(6); | |
26120 | fill_prefetch_0 (); | |
26121 | m68k_write_memory_32(dsta,src); | |
26122 | }}}}}endlabel1600: ; | |
26123 | return 28; | |
26124 | } | |
26125 | unsigned long CPUFUNC(op_98_5)(uint32_t opcode) /* OR */ | |
26126 | { | |
26127 | uint32_t dstreg = opcode & 7; | |
26128 | OpcodeFamily = 1; CurrentInstrCycles = 28; | |
26129 | {{ int32_t src = get_ilong_prefetch(2); | |
26130 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
26131 | if ((dsta & 1) != 0) { | |
26132 | last_fault_for_exception_3 = dsta; | |
26133 | last_op_for_exception_3 = opcode; | |
26134 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
26135 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
26136 | goto endlabel1601; | |
26137 | } | |
26138 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
26139 | m68k_areg(regs, dstreg) += 4; | |
26140 | src |= dst; | |
26141 | CLEAR_CZNV; | |
26142 | SET_ZFLG (((int32_t)(src)) == 0); | |
26143 | SET_NFLG (((int32_t)(src)) < 0); | |
26144 | m68k_incpc(6); | |
26145 | fill_prefetch_0 (); | |
26146 | m68k_write_memory_32(dsta,src); | |
26147 | }}}}}endlabel1601: ; | |
26148 | return 28; | |
26149 | } | |
26150 | unsigned long CPUFUNC(op_a0_5)(uint32_t opcode) /* OR */ | |
26151 | { | |
26152 | uint32_t dstreg = opcode & 7; | |
26153 | OpcodeFamily = 1; CurrentInstrCycles = 30; | |
26154 | {{ int32_t src = get_ilong_prefetch(2); | |
26155 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
26156 | if ((dsta & 1) != 0) { | |
26157 | last_fault_for_exception_3 = dsta; | |
26158 | last_op_for_exception_3 = opcode; | |
26159 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
26160 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
26161 | goto endlabel1602; | |
26162 | } | |
26163 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
26164 | m68k_areg (regs, dstreg) = dsta; | |
26165 | src |= dst; | |
26166 | CLEAR_CZNV; | |
26167 | SET_ZFLG (((int32_t)(src)) == 0); | |
26168 | SET_NFLG (((int32_t)(src)) < 0); | |
26169 | m68k_incpc(6); | |
26170 | fill_prefetch_0 (); | |
26171 | m68k_write_memory_32(dsta,src); | |
26172 | }}}}}endlabel1602: ; | |
26173 | return 30; | |
26174 | } | |
26175 | unsigned long CPUFUNC(op_a8_5)(uint32_t opcode) /* OR */ | |
26176 | { | |
26177 | uint32_t dstreg = opcode & 7; | |
26178 | OpcodeFamily = 1; CurrentInstrCycles = 32; | |
26179 | {{ int32_t src = get_ilong_prefetch(2); | |
26180 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(6); | |
26181 | if ((dsta & 1) != 0) { | |
26182 | last_fault_for_exception_3 = dsta; | |
26183 | last_op_for_exception_3 = opcode; | |
26184 | last_addr_for_exception_3 = m68k_getpc() + 8; | |
26185 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
26186 | goto endlabel1603; | |
26187 | } | |
26188 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
26189 | src |= dst; | |
26190 | CLEAR_CZNV; | |
26191 | SET_ZFLG (((int32_t)(src)) == 0); | |
26192 | SET_NFLG (((int32_t)(src)) < 0); | |
26193 | m68k_incpc(8); | |
26194 | fill_prefetch_0 (); | |
26195 | m68k_write_memory_32(dsta,src); | |
26196 | }}}}}endlabel1603: ; | |
26197 | return 32; | |
26198 | } | |
26199 | unsigned long CPUFUNC(op_b0_5)(uint32_t opcode) /* OR */ | |
26200 | { | |
26201 | uint32_t dstreg = opcode & 7; | |
26202 | OpcodeFamily = 1; CurrentInstrCycles = 34; | |
26203 | {{ int32_t src = get_ilong_prefetch(2); | |
26204 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(6)); | |
26205 | BusCyclePenalty += 2; | |
26206 | if ((dsta & 1) != 0) { | |
26207 | last_fault_for_exception_3 = dsta; | |
26208 | last_op_for_exception_3 = opcode; | |
26209 | last_addr_for_exception_3 = m68k_getpc() + 8; | |
26210 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
26211 | goto endlabel1604; | |
26212 | } | |
26213 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
26214 | src |= dst; | |
26215 | CLEAR_CZNV; | |
26216 | SET_ZFLG (((int32_t)(src)) == 0); | |
26217 | SET_NFLG (((int32_t)(src)) < 0); | |
26218 | m68k_incpc(8); | |
26219 | fill_prefetch_0 (); | |
26220 | m68k_write_memory_32(dsta,src); | |
26221 | }}}}}endlabel1604: ; | |
26222 | return 34; | |
26223 | } | |
26224 | unsigned long CPUFUNC(op_b8_5)(uint32_t opcode) /* OR */ | |
26225 | { | |
26226 | OpcodeFamily = 1; CurrentInstrCycles = 32; | |
26227 | {{ int32_t src = get_ilong_prefetch(2); | |
26228 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(6); | |
26229 | if ((dsta & 1) != 0) { | |
26230 | last_fault_for_exception_3 = dsta; | |
26231 | last_op_for_exception_3 = opcode; | |
26232 | last_addr_for_exception_3 = m68k_getpc() + 8; | |
26233 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
26234 | goto endlabel1605; | |
26235 | } | |
26236 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
26237 | src |= dst; | |
26238 | CLEAR_CZNV; | |
26239 | SET_ZFLG (((int32_t)(src)) == 0); | |
26240 | SET_NFLG (((int32_t)(src)) < 0); | |
26241 | m68k_incpc(8); | |
26242 | fill_prefetch_0 (); | |
26243 | m68k_write_memory_32(dsta,src); | |
26244 | }}}}}endlabel1605: ; | |
26245 | return 32; | |
26246 | } | |
26247 | unsigned long CPUFUNC(op_b9_5)(uint32_t opcode) /* OR */ | |
26248 | { | |
26249 | OpcodeFamily = 1; CurrentInstrCycles = 36; | |
26250 | {{ int32_t src = get_ilong_prefetch(2); | |
26251 | { uint32_t dsta = get_ilong_prefetch(6); | |
26252 | if ((dsta & 1) != 0) { | |
26253 | last_fault_for_exception_3 = dsta; | |
26254 | last_op_for_exception_3 = opcode; | |
26255 | last_addr_for_exception_3 = m68k_getpc() + 10; | |
26256 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
26257 | goto endlabel1606; | |
26258 | } | |
26259 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
26260 | src |= dst; | |
26261 | CLEAR_CZNV; | |
26262 | SET_ZFLG (((int32_t)(src)) == 0); | |
26263 | SET_NFLG (((int32_t)(src)) < 0); | |
26264 | m68k_incpc(10); | |
26265 | fill_prefetch_0 (); | |
26266 | m68k_write_memory_32(dsta,src); | |
26267 | }}}}}endlabel1606: ; | |
26268 | return 36; | |
26269 | } | |
26270 | unsigned long CPUFUNC(op_100_5)(uint32_t opcode) /* BTST */ | |
26271 | { | |
26272 | uint32_t srcreg = ((opcode >> 9) & 7); | |
26273 | uint32_t dstreg = opcode & 7; | |
26274 | OpcodeFamily = 21; CurrentInstrCycles = 6; | |
26275 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
26276 | { int32_t dst = m68k_dreg(regs, dstreg); | |
26277 | src &= 31; | |
26278 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
26279 | }}}m68k_incpc(2); | |
26280 | fill_prefetch_2 (); | |
26281 | return 6; | |
26282 | } | |
26283 | unsigned long CPUFUNC(op_108_5)(uint32_t opcode) /* MVPMR */ | |
26284 | { | |
26285 | uint32_t srcreg = (opcode & 7); | |
26286 | uint32_t dstreg = (opcode >> 9) & 7; | |
26287 | OpcodeFamily = 29; CurrentInstrCycles = 16; | |
26288 | { uint32_t memp = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
26289 | { uint16_t val = (m68k_read_memory_8(memp) << 8) + m68k_read_memory_8(memp + 2); | |
26290 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); | |
26291 | }}m68k_incpc(4); | |
26292 | fill_prefetch_0 (); | |
26293 | return 16; | |
26294 | } | |
26295 | unsigned long CPUFUNC(op_110_5)(uint32_t opcode) /* BTST */ | |
26296 | { | |
26297 | uint32_t srcreg = ((opcode >> 9) & 7); | |
26298 | uint32_t dstreg = opcode & 7; | |
26299 | OpcodeFamily = 21; CurrentInstrCycles = 8; | |
26300 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
26301 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
26302 | { int8_t dst = m68k_read_memory_8(dsta); | |
26303 | src &= 7; | |
26304 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
26305 | }}}}m68k_incpc(2); | |
26306 | fill_prefetch_2 (); | |
26307 | return 8; | |
26308 | } | |
26309 | unsigned long CPUFUNC(op_118_5)(uint32_t opcode) /* BTST */ | |
26310 | { | |
26311 | uint32_t srcreg = ((opcode >> 9) & 7); | |
26312 | uint32_t dstreg = opcode & 7; | |
26313 | OpcodeFamily = 21; CurrentInstrCycles = 8; | |
26314 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
26315 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
26316 | { int8_t dst = m68k_read_memory_8(dsta); | |
26317 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
26318 | src &= 7; | |
26319 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
26320 | }}}}m68k_incpc(2); | |
26321 | fill_prefetch_2 (); | |
26322 | return 8; | |
26323 | } | |
26324 | unsigned long CPUFUNC(op_120_5)(uint32_t opcode) /* BTST */ | |
26325 | { | |
26326 | uint32_t srcreg = ((opcode >> 9) & 7); | |
26327 | uint32_t dstreg = opcode & 7; | |
26328 | OpcodeFamily = 21; CurrentInstrCycles = 10; | |
26329 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
26330 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
26331 | { int8_t dst = m68k_read_memory_8(dsta); | |
26332 | m68k_areg (regs, dstreg) = dsta; | |
26333 | src &= 7; | |
26334 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
26335 | }}}}m68k_incpc(2); | |
26336 | fill_prefetch_2 (); | |
26337 | return 10; | |
26338 | } | |
26339 | unsigned long CPUFUNC(op_128_5)(uint32_t opcode) /* BTST */ | |
26340 | { | |
26341 | uint32_t srcreg = ((opcode >> 9) & 7); | |
26342 | uint32_t dstreg = opcode & 7; | |
26343 | OpcodeFamily = 21; CurrentInstrCycles = 12; | |
26344 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
26345 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
26346 | { int8_t dst = m68k_read_memory_8(dsta); | |
26347 | src &= 7; | |
26348 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
26349 | }}}}m68k_incpc(4); | |
26350 | fill_prefetch_0 (); | |
26351 | return 12; | |
26352 | } | |
26353 | unsigned long CPUFUNC(op_130_5)(uint32_t opcode) /* BTST */ | |
26354 | { | |
26355 | uint32_t srcreg = ((opcode >> 9) & 7); | |
26356 | uint32_t dstreg = opcode & 7; | |
26357 | OpcodeFamily = 21; CurrentInstrCycles = 14; | |
26358 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
26359 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); | |
26360 | BusCyclePenalty += 2; | |
26361 | { int8_t dst = m68k_read_memory_8(dsta); | |
26362 | src &= 7; | |
26363 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
26364 | }}}}m68k_incpc(4); | |
26365 | fill_prefetch_0 (); | |
26366 | return 14; | |
26367 | } | |
26368 | unsigned long CPUFUNC(op_138_5)(uint32_t opcode) /* BTST */ | |
26369 | { | |
26370 | uint32_t srcreg = ((opcode >> 9) & 7); | |
26371 | OpcodeFamily = 21; CurrentInstrCycles = 12; | |
26372 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
26373 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); | |
26374 | { int8_t dst = m68k_read_memory_8(dsta); | |
26375 | src &= 7; | |
26376 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
26377 | }}}}m68k_incpc(4); | |
26378 | fill_prefetch_0 (); | |
26379 | return 12; | |
26380 | } | |
26381 | unsigned long CPUFUNC(op_139_5)(uint32_t opcode) /* BTST */ | |
26382 | { | |
26383 | uint32_t srcreg = ((opcode >> 9) & 7); | |
26384 | OpcodeFamily = 21; CurrentInstrCycles = 16; | |
26385 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
26386 | { uint32_t dsta = get_ilong_prefetch(2); | |
26387 | { int8_t dst = m68k_read_memory_8(dsta); | |
26388 | src &= 7; | |
26389 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
26390 | }}}}m68k_incpc(6); | |
26391 | fill_prefetch_0 (); | |
26392 | return 16; | |
26393 | } | |
26394 | unsigned long CPUFUNC(op_13a_5)(uint32_t opcode) /* BTST */ | |
26395 | { | |
26396 | uint32_t srcreg = ((opcode >> 9) & 7); | |
26397 | uint32_t dstreg = 2; | |
26398 | OpcodeFamily = 21; CurrentInstrCycles = 12; | |
26399 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
26400 | { uint32_t dsta = m68k_getpc () + 2; | |
26401 | dsta += (int32_t)(int16_t)get_iword_prefetch(2); | |
26402 | { int8_t dst = m68k_read_memory_8(dsta); | |
26403 | src &= 7; | |
26404 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
26405 | }}}}m68k_incpc(4); | |
26406 | fill_prefetch_0 (); | |
26407 | return 12; | |
26408 | } | |
26409 | unsigned long CPUFUNC(op_13b_5)(uint32_t opcode) /* BTST */ | |
26410 | { | |
26411 | uint32_t srcreg = ((opcode >> 9) & 7); | |
26412 | uint32_t dstreg = 3; | |
26413 | OpcodeFamily = 21; CurrentInstrCycles = 14; | |
26414 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
26415 | { uint32_t tmppc = m68k_getpc() + 2; | |
26416 | uint32_t dsta = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
26417 | BusCyclePenalty += 2; | |
26418 | { int8_t dst = m68k_read_memory_8(dsta); | |
26419 | src &= 7; | |
26420 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
26421 | }}}}m68k_incpc(4); | |
26422 | fill_prefetch_0 (); | |
26423 | return 14; | |
26424 | } | |
26425 | unsigned long CPUFUNC(op_13c_5)(uint32_t opcode) /* BTST */ | |
26426 | { | |
26427 | uint32_t srcreg = ((opcode >> 9) & 7); | |
26428 | OpcodeFamily = 21; CurrentInstrCycles = 8; | |
26429 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
26430 | { int8_t dst = get_ibyte_prefetch(2); | |
26431 | src &= 7; | |
26432 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
26433 | }}}m68k_incpc(4); | |
26434 | fill_prefetch_0 (); | |
26435 | return 8; | |
26436 | } | |
26437 | unsigned long CPUFUNC(op_140_5)(uint32_t opcode) /* BCHG */ | |
26438 | { | |
26439 | uint32_t srcreg = ((opcode >> 9) & 7); | |
26440 | uint32_t dstreg = opcode & 7; | |
26441 | OpcodeFamily = 22; CurrentInstrCycles = 8; | |
26442 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
26443 | { int32_t dst = m68k_dreg(regs, dstreg); | |
26444 | src &= 31; | |
26445 | dst ^= (1 << src); | |
26446 | SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); | |
26447 | m68k_dreg(regs, dstreg) = (dst); | |
26448 | }}}m68k_incpc(2); | |
26449 | fill_prefetch_2 (); | |
26450 | return 8; | |
26451 | } | |
26452 | unsigned long CPUFUNC(op_148_5)(uint32_t opcode) /* MVPMR */ | |
26453 | { | |
26454 | uint32_t srcreg = (opcode & 7); | |
26455 | uint32_t dstreg = (opcode >> 9) & 7; | |
26456 | OpcodeFamily = 29; CurrentInstrCycles = 24; | |
26457 | { uint32_t memp = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
26458 | { uint32_t val = (m68k_read_memory_8(memp) << 24) + (m68k_read_memory_8(memp + 2) << 16) | |
26459 | + (m68k_read_memory_8(memp + 4) << 8) + m68k_read_memory_8(memp + 6); | |
26460 | m68k_dreg(regs, dstreg) = (val); | |
26461 | }}m68k_incpc(4); | |
26462 | fill_prefetch_0 (); | |
26463 | return 24; | |
26464 | } | |
26465 | unsigned long CPUFUNC(op_150_5)(uint32_t opcode) /* BCHG */ | |
26466 | { | |
26467 | uint32_t srcreg = ((opcode >> 9) & 7); | |
26468 | uint32_t dstreg = opcode & 7; | |
26469 | OpcodeFamily = 22; CurrentInstrCycles = 12; | |
26470 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
26471 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
26472 | { int8_t dst = m68k_read_memory_8(dsta); | |
26473 | src &= 7; | |
26474 | dst ^= (1 << src); | |
26475 | SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); | |
26476 | m68k_incpc(2); | |
26477 | fill_prefetch_2 (); | |
26478 | m68k_write_memory_8(dsta,dst); | |
26479 | }}}}return 12; | |
26480 | } | |
26481 | unsigned long CPUFUNC(op_158_5)(uint32_t opcode) /* BCHG */ | |
26482 | { | |
26483 | uint32_t srcreg = ((opcode >> 9) & 7); | |
26484 | uint32_t dstreg = opcode & 7; | |
26485 | OpcodeFamily = 22; CurrentInstrCycles = 12; | |
26486 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
26487 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
26488 | { int8_t dst = m68k_read_memory_8(dsta); | |
26489 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
26490 | src &= 7; | |
26491 | dst ^= (1 << src); | |
26492 | SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); | |
26493 | m68k_incpc(2); | |
26494 | fill_prefetch_2 (); | |
26495 | m68k_write_memory_8(dsta,dst); | |
26496 | }}}}return 12; | |
26497 | } | |
26498 | unsigned long CPUFUNC(op_160_5)(uint32_t opcode) /* BCHG */ | |
26499 | { | |
26500 | uint32_t srcreg = ((opcode >> 9) & 7); | |
26501 | uint32_t dstreg = opcode & 7; | |
26502 | OpcodeFamily = 22; CurrentInstrCycles = 14; | |
26503 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
26504 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
26505 | { int8_t dst = m68k_read_memory_8(dsta); | |
26506 | m68k_areg (regs, dstreg) = dsta; | |
26507 | src &= 7; | |
26508 | dst ^= (1 << src); | |
26509 | SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); | |
26510 | m68k_incpc(2); | |
26511 | fill_prefetch_2 (); | |
26512 | m68k_write_memory_8(dsta,dst); | |
26513 | }}}}return 14; | |
26514 | } | |
26515 | unsigned long CPUFUNC(op_168_5)(uint32_t opcode) /* BCHG */ | |
26516 | { | |
26517 | uint32_t srcreg = ((opcode >> 9) & 7); | |
26518 | uint32_t dstreg = opcode & 7; | |
26519 | OpcodeFamily = 22; CurrentInstrCycles = 16; | |
26520 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
26521 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
26522 | { int8_t dst = m68k_read_memory_8(dsta); | |
26523 | src &= 7; | |
26524 | dst ^= (1 << src); | |
26525 | SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); | |
26526 | m68k_incpc(4); | |
26527 | fill_prefetch_0 (); | |
26528 | m68k_write_memory_8(dsta,dst); | |
26529 | }}}}return 16; | |
26530 | } | |
26531 | unsigned long CPUFUNC(op_170_5)(uint32_t opcode) /* BCHG */ | |
26532 | { | |
26533 | uint32_t srcreg = ((opcode >> 9) & 7); | |
26534 | uint32_t dstreg = opcode & 7; | |
26535 | OpcodeFamily = 22; CurrentInstrCycles = 18; | |
26536 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
26537 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); | |
26538 | BusCyclePenalty += 2; | |
26539 | { int8_t dst = m68k_read_memory_8(dsta); | |
26540 | src &= 7; | |
26541 | dst ^= (1 << src); | |
26542 | SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); | |
26543 | m68k_incpc(4); | |
26544 | fill_prefetch_0 (); | |
26545 | m68k_write_memory_8(dsta,dst); | |
26546 | }}}}return 18; | |
26547 | } | |
26548 | unsigned long CPUFUNC(op_178_5)(uint32_t opcode) /* BCHG */ | |
26549 | { | |
26550 | uint32_t srcreg = ((opcode >> 9) & 7); | |
26551 | OpcodeFamily = 22; CurrentInstrCycles = 16; | |
26552 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
26553 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); | |
26554 | { int8_t dst = m68k_read_memory_8(dsta); | |
26555 | src &= 7; | |
26556 | dst ^= (1 << src); | |
26557 | SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); | |
26558 | m68k_incpc(4); | |
26559 | fill_prefetch_0 (); | |
26560 | m68k_write_memory_8(dsta,dst); | |
26561 | }}}}return 16; | |
26562 | } | |
26563 | unsigned long CPUFUNC(op_179_5)(uint32_t opcode) /* BCHG */ | |
26564 | { | |
26565 | uint32_t srcreg = ((opcode >> 9) & 7); | |
26566 | OpcodeFamily = 22; CurrentInstrCycles = 20; | |
26567 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
26568 | { uint32_t dsta = get_ilong_prefetch(2); | |
26569 | { int8_t dst = m68k_read_memory_8(dsta); | |
26570 | src &= 7; | |
26571 | dst ^= (1 << src); | |
26572 | SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); | |
26573 | m68k_incpc(6); | |
26574 | fill_prefetch_0 (); | |
26575 | m68k_write_memory_8(dsta,dst); | |
26576 | }}}}return 20; | |
26577 | } | |
26578 | unsigned long CPUFUNC(op_17a_5)(uint32_t opcode) /* BCHG */ | |
26579 | { | |
26580 | uint32_t srcreg = ((opcode >> 9) & 7); | |
26581 | uint32_t dstreg = 2; | |
26582 | OpcodeFamily = 22; CurrentInstrCycles = 16; | |
26583 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
26584 | { uint32_t dsta = m68k_getpc () + 2; | |
26585 | dsta += (int32_t)(int16_t)get_iword_prefetch(2); | |
26586 | { int8_t dst = m68k_read_memory_8(dsta); | |
26587 | src &= 7; | |
26588 | dst ^= (1 << src); | |
26589 | SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); | |
26590 | m68k_incpc(4); | |
26591 | fill_prefetch_0 (); | |
26592 | m68k_write_memory_8(dsta,dst); | |
26593 | }}}}return 16; | |
26594 | } | |
26595 | unsigned long CPUFUNC(op_17b_5)(uint32_t opcode) /* BCHG */ | |
26596 | { | |
26597 | uint32_t srcreg = ((opcode >> 9) & 7); | |
26598 | uint32_t dstreg = 3; | |
26599 | OpcodeFamily = 22; CurrentInstrCycles = 18; | |
26600 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
26601 | { uint32_t tmppc = m68k_getpc() + 2; | |
26602 | uint32_t dsta = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
26603 | BusCyclePenalty += 2; | |
26604 | { int8_t dst = m68k_read_memory_8(dsta); | |
26605 | src &= 7; | |
26606 | dst ^= (1 << src); | |
26607 | SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); | |
26608 | m68k_incpc(4); | |
26609 | fill_prefetch_0 (); | |
26610 | m68k_write_memory_8(dsta,dst); | |
26611 | }}}}return 18; | |
26612 | } | |
26613 | unsigned long CPUFUNC(op_180_5)(uint32_t opcode) /* BCLR */ | |
26614 | { | |
26615 | uint32_t srcreg = ((opcode >> 9) & 7); | |
26616 | uint32_t dstreg = opcode & 7; | |
26617 | OpcodeFamily = 23; CurrentInstrCycles = 10; | |
26618 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
26619 | { int32_t dst = m68k_dreg(regs, dstreg); | |
26620 | src &= 31; | |
26621 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
26622 | dst &= ~(1 << src); | |
26623 | m68k_dreg(regs, dstreg) = (dst); | |
26624 | if ( src < 16 ) { m68k_incpc(2); return 8; } | |
26625 | }}}m68k_incpc(2); | |
26626 | fill_prefetch_2 (); | |
26627 | return 10; | |
26628 | } | |
26629 | unsigned long CPUFUNC(op_188_5)(uint32_t opcode) /* MVPRM */ | |
26630 | { | |
26631 | uint32_t srcreg = ((opcode >> 9) & 7); | |
26632 | uint32_t dstreg = opcode & 7; | |
26633 | OpcodeFamily = 28; CurrentInstrCycles = 16; | |
26634 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
26635 | uint32_t memp = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
26636 | m68k_write_memory_8(memp, src >> 8); m68k_write_memory_8(memp + 2, src); | |
26637 | }}m68k_incpc(4); | |
26638 | fill_prefetch_0 (); | |
26639 | return 16; | |
26640 | } | |
26641 | unsigned long CPUFUNC(op_190_5)(uint32_t opcode) /* BCLR */ | |
26642 | { | |
26643 | uint32_t srcreg = ((opcode >> 9) & 7); | |
26644 | uint32_t dstreg = opcode & 7; | |
26645 | OpcodeFamily = 23; CurrentInstrCycles = 12; | |
26646 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
26647 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
26648 | { int8_t dst = m68k_read_memory_8(dsta); | |
26649 | src &= 7; | |
26650 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
26651 | dst &= ~(1 << src); | |
26652 | m68k_incpc(2); | |
26653 | fill_prefetch_2 (); | |
26654 | m68k_write_memory_8(dsta,dst); | |
26655 | }}}}return 12; | |
26656 | } | |
26657 | unsigned long CPUFUNC(op_198_5)(uint32_t opcode) /* BCLR */ | |
26658 | { | |
26659 | uint32_t srcreg = ((opcode >> 9) & 7); | |
26660 | uint32_t dstreg = opcode & 7; | |
26661 | OpcodeFamily = 23; CurrentInstrCycles = 12; | |
26662 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
26663 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
26664 | { int8_t dst = m68k_read_memory_8(dsta); | |
26665 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
26666 | src &= 7; | |
26667 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
26668 | dst &= ~(1 << src); | |
26669 | m68k_incpc(2); | |
26670 | fill_prefetch_2 (); | |
26671 | m68k_write_memory_8(dsta,dst); | |
26672 | }}}}return 12; | |
26673 | } | |
26674 | unsigned long CPUFUNC(op_1a0_5)(uint32_t opcode) /* BCLR */ | |
26675 | { | |
26676 | uint32_t srcreg = ((opcode >> 9) & 7); | |
26677 | uint32_t dstreg = opcode & 7; | |
26678 | OpcodeFamily = 23; CurrentInstrCycles = 14; | |
26679 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
26680 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
26681 | { int8_t dst = m68k_read_memory_8(dsta); | |
26682 | m68k_areg (regs, dstreg) = dsta; | |
26683 | src &= 7; | |
26684 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
26685 | dst &= ~(1 << src); | |
26686 | m68k_incpc(2); | |
26687 | fill_prefetch_2 (); | |
26688 | m68k_write_memory_8(dsta,dst); | |
26689 | }}}}return 14; | |
26690 | } | |
26691 | unsigned long CPUFUNC(op_1a8_5)(uint32_t opcode) /* BCLR */ | |
26692 | { | |
26693 | uint32_t srcreg = ((opcode >> 9) & 7); | |
26694 | uint32_t dstreg = opcode & 7; | |
26695 | OpcodeFamily = 23; CurrentInstrCycles = 16; | |
26696 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
26697 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
26698 | { int8_t dst = m68k_read_memory_8(dsta); | |
26699 | src &= 7; | |
26700 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
26701 | dst &= ~(1 << src); | |
26702 | m68k_incpc(4); | |
26703 | fill_prefetch_0 (); | |
26704 | m68k_write_memory_8(dsta,dst); | |
26705 | }}}}return 16; | |
26706 | } | |
26707 | unsigned long CPUFUNC(op_1b0_5)(uint32_t opcode) /* BCLR */ | |
26708 | { | |
26709 | uint32_t srcreg = ((opcode >> 9) & 7); | |
26710 | uint32_t dstreg = opcode & 7; | |
26711 | OpcodeFamily = 23; CurrentInstrCycles = 18; | |
26712 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
26713 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); | |
26714 | BusCyclePenalty += 2; | |
26715 | { int8_t dst = m68k_read_memory_8(dsta); | |
26716 | src &= 7; | |
26717 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
26718 | dst &= ~(1 << src); | |
26719 | m68k_incpc(4); | |
26720 | fill_prefetch_0 (); | |
26721 | m68k_write_memory_8(dsta,dst); | |
26722 | }}}}return 18; | |
26723 | } | |
26724 | unsigned long CPUFUNC(op_1b8_5)(uint32_t opcode) /* BCLR */ | |
26725 | { | |
26726 | uint32_t srcreg = ((opcode >> 9) & 7); | |
26727 | OpcodeFamily = 23; CurrentInstrCycles = 16; | |
26728 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
26729 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); | |
26730 | { int8_t dst = m68k_read_memory_8(dsta); | |
26731 | src &= 7; | |
26732 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
26733 | dst &= ~(1 << src); | |
26734 | m68k_incpc(4); | |
26735 | fill_prefetch_0 (); | |
26736 | m68k_write_memory_8(dsta,dst); | |
26737 | }}}}return 16; | |
26738 | } | |
26739 | unsigned long CPUFUNC(op_1b9_5)(uint32_t opcode) /* BCLR */ | |
26740 | { | |
26741 | uint32_t srcreg = ((opcode >> 9) & 7); | |
26742 | OpcodeFamily = 23; CurrentInstrCycles = 20; | |
26743 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
26744 | { uint32_t dsta = get_ilong_prefetch(2); | |
26745 | { int8_t dst = m68k_read_memory_8(dsta); | |
26746 | src &= 7; | |
26747 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
26748 | dst &= ~(1 << src); | |
26749 | m68k_incpc(6); | |
26750 | fill_prefetch_0 (); | |
26751 | m68k_write_memory_8(dsta,dst); | |
26752 | }}}}return 20; | |
26753 | } | |
26754 | unsigned long CPUFUNC(op_1ba_5)(uint32_t opcode) /* BCLR */ | |
26755 | { | |
26756 | uint32_t srcreg = ((opcode >> 9) & 7); | |
26757 | uint32_t dstreg = 2; | |
26758 | OpcodeFamily = 23; CurrentInstrCycles = 16; | |
26759 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
26760 | { uint32_t dsta = m68k_getpc () + 2; | |
26761 | dsta += (int32_t)(int16_t)get_iword_prefetch(2); | |
26762 | { int8_t dst = m68k_read_memory_8(dsta); | |
26763 | src &= 7; | |
26764 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
26765 | dst &= ~(1 << src); | |
26766 | m68k_incpc(4); | |
26767 | fill_prefetch_0 (); | |
26768 | m68k_write_memory_8(dsta,dst); | |
26769 | }}}}return 16; | |
26770 | } | |
26771 | unsigned long CPUFUNC(op_1bb_5)(uint32_t opcode) /* BCLR */ | |
26772 | { | |
26773 | uint32_t srcreg = ((opcode >> 9) & 7); | |
26774 | uint32_t dstreg = 3; | |
26775 | OpcodeFamily = 23; CurrentInstrCycles = 18; | |
26776 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
26777 | { uint32_t tmppc = m68k_getpc() + 2; | |
26778 | uint32_t dsta = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
26779 | BusCyclePenalty += 2; | |
26780 | { int8_t dst = m68k_read_memory_8(dsta); | |
26781 | src &= 7; | |
26782 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
26783 | dst &= ~(1 << src); | |
26784 | m68k_incpc(4); | |
26785 | fill_prefetch_0 (); | |
26786 | m68k_write_memory_8(dsta,dst); | |
26787 | }}}}return 18; | |
26788 | } | |
26789 | unsigned long CPUFUNC(op_1c0_5)(uint32_t opcode) /* BSET */ | |
26790 | { | |
26791 | uint32_t srcreg = ((opcode >> 9) & 7); | |
26792 | uint32_t dstreg = opcode & 7; | |
26793 | OpcodeFamily = 24; CurrentInstrCycles = 8; | |
26794 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
26795 | { int32_t dst = m68k_dreg(regs, dstreg); | |
26796 | src &= 31; | |
26797 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
26798 | dst |= (1 << src); | |
26799 | m68k_dreg(regs, dstreg) = (dst); | |
26800 | }}}m68k_incpc(2); | |
26801 | fill_prefetch_2 (); | |
26802 | return 8; | |
26803 | } | |
26804 | unsigned long CPUFUNC(op_1c8_5)(uint32_t opcode) /* MVPRM */ | |
26805 | { | |
26806 | uint32_t srcreg = ((opcode >> 9) & 7); | |
26807 | uint32_t dstreg = opcode & 7; | |
26808 | OpcodeFamily = 28; CurrentInstrCycles = 24; | |
26809 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
26810 | uint32_t memp = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
26811 | m68k_write_memory_8(memp, src >> 24); m68k_write_memory_8(memp + 2, src >> 16); | |
26812 | m68k_write_memory_8(memp + 4, src >> 8); m68k_write_memory_8(memp + 6, src); | |
26813 | }}m68k_incpc(4); | |
26814 | fill_prefetch_0 (); | |
26815 | return 24; | |
26816 | } | |
26817 | unsigned long CPUFUNC(op_1d0_5)(uint32_t opcode) /* BSET */ | |
26818 | { | |
26819 | uint32_t srcreg = ((opcode >> 9) & 7); | |
26820 | uint32_t dstreg = opcode & 7; | |
26821 | OpcodeFamily = 24; CurrentInstrCycles = 12; | |
26822 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
26823 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
26824 | { int8_t dst = m68k_read_memory_8(dsta); | |
26825 | src &= 7; | |
26826 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
26827 | dst |= (1 << src); | |
26828 | m68k_incpc(2); | |
26829 | fill_prefetch_2 (); | |
26830 | m68k_write_memory_8(dsta,dst); | |
26831 | }}}}return 12; | |
26832 | } | |
26833 | unsigned long CPUFUNC(op_1d8_5)(uint32_t opcode) /* BSET */ | |
26834 | { | |
26835 | uint32_t srcreg = ((opcode >> 9) & 7); | |
26836 | uint32_t dstreg = opcode & 7; | |
26837 | OpcodeFamily = 24; CurrentInstrCycles = 12; | |
26838 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
26839 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
26840 | { int8_t dst = m68k_read_memory_8(dsta); | |
26841 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
26842 | src &= 7; | |
26843 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
26844 | dst |= (1 << src); | |
26845 | m68k_incpc(2); | |
26846 | fill_prefetch_2 (); | |
26847 | m68k_write_memory_8(dsta,dst); | |
26848 | }}}}return 12; | |
26849 | } | |
26850 | unsigned long CPUFUNC(op_1e0_5)(uint32_t opcode) /* BSET */ | |
26851 | { | |
26852 | uint32_t srcreg = ((opcode >> 9) & 7); | |
26853 | uint32_t dstreg = opcode & 7; | |
26854 | OpcodeFamily = 24; CurrentInstrCycles = 14; | |
26855 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
26856 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
26857 | { int8_t dst = m68k_read_memory_8(dsta); | |
26858 | m68k_areg (regs, dstreg) = dsta; | |
26859 | src &= 7; | |
26860 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
26861 | dst |= (1 << src); | |
26862 | m68k_incpc(2); | |
26863 | fill_prefetch_2 (); | |
26864 | m68k_write_memory_8(dsta,dst); | |
26865 | }}}}return 14; | |
26866 | } | |
26867 | unsigned long CPUFUNC(op_1e8_5)(uint32_t opcode) /* BSET */ | |
26868 | { | |
26869 | uint32_t srcreg = ((opcode >> 9) & 7); | |
26870 | uint32_t dstreg = opcode & 7; | |
26871 | OpcodeFamily = 24; CurrentInstrCycles = 16; | |
26872 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
26873 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
26874 | { int8_t dst = m68k_read_memory_8(dsta); | |
26875 | src &= 7; | |
26876 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
26877 | dst |= (1 << src); | |
26878 | m68k_incpc(4); | |
26879 | fill_prefetch_0 (); | |
26880 | m68k_write_memory_8(dsta,dst); | |
26881 | }}}}return 16; | |
26882 | } | |
26883 | unsigned long CPUFUNC(op_1f0_5)(uint32_t opcode) /* BSET */ | |
26884 | { | |
26885 | uint32_t srcreg = ((opcode >> 9) & 7); | |
26886 | uint32_t dstreg = opcode & 7; | |
26887 | OpcodeFamily = 24; CurrentInstrCycles = 18; | |
26888 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
26889 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); | |
26890 | BusCyclePenalty += 2; | |
26891 | { int8_t dst = m68k_read_memory_8(dsta); | |
26892 | src &= 7; | |
26893 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
26894 | dst |= (1 << src); | |
26895 | m68k_incpc(4); | |
26896 | fill_prefetch_0 (); | |
26897 | m68k_write_memory_8(dsta,dst); | |
26898 | }}}}return 18; | |
26899 | } | |
26900 | unsigned long CPUFUNC(op_1f8_5)(uint32_t opcode) /* BSET */ | |
26901 | { | |
26902 | uint32_t srcreg = ((opcode >> 9) & 7); | |
26903 | OpcodeFamily = 24; CurrentInstrCycles = 16; | |
26904 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
26905 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); | |
26906 | { int8_t dst = m68k_read_memory_8(dsta); | |
26907 | src &= 7; | |
26908 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
26909 | dst |= (1 << src); | |
26910 | m68k_incpc(4); | |
26911 | fill_prefetch_0 (); | |
26912 | m68k_write_memory_8(dsta,dst); | |
26913 | }}}}return 16; | |
26914 | } | |
26915 | unsigned long CPUFUNC(op_1f9_5)(uint32_t opcode) /* BSET */ | |
26916 | { | |
26917 | uint32_t srcreg = ((opcode >> 9) & 7); | |
26918 | OpcodeFamily = 24; CurrentInstrCycles = 20; | |
26919 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
26920 | { uint32_t dsta = get_ilong_prefetch(2); | |
26921 | { int8_t dst = m68k_read_memory_8(dsta); | |
26922 | src &= 7; | |
26923 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
26924 | dst |= (1 << src); | |
26925 | m68k_incpc(6); | |
26926 | fill_prefetch_0 (); | |
26927 | m68k_write_memory_8(dsta,dst); | |
26928 | }}}}return 20; | |
26929 | } | |
26930 | unsigned long CPUFUNC(op_1fa_5)(uint32_t opcode) /* BSET */ | |
26931 | { | |
26932 | uint32_t srcreg = ((opcode >> 9) & 7); | |
26933 | uint32_t dstreg = 2; | |
26934 | OpcodeFamily = 24; CurrentInstrCycles = 16; | |
26935 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
26936 | { uint32_t dsta = m68k_getpc () + 2; | |
26937 | dsta += (int32_t)(int16_t)get_iword_prefetch(2); | |
26938 | { int8_t dst = m68k_read_memory_8(dsta); | |
26939 | src &= 7; | |
26940 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
26941 | dst |= (1 << src); | |
26942 | m68k_incpc(4); | |
26943 | fill_prefetch_0 (); | |
26944 | m68k_write_memory_8(dsta,dst); | |
26945 | }}}}return 16; | |
26946 | } | |
26947 | unsigned long CPUFUNC(op_1fb_5)(uint32_t opcode) /* BSET */ | |
26948 | { | |
26949 | uint32_t srcreg = ((opcode >> 9) & 7); | |
26950 | uint32_t dstreg = 3; | |
26951 | OpcodeFamily = 24; CurrentInstrCycles = 18; | |
26952 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
26953 | { uint32_t tmppc = m68k_getpc() + 2; | |
26954 | uint32_t dsta = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
26955 | BusCyclePenalty += 2; | |
26956 | { int8_t dst = m68k_read_memory_8(dsta); | |
26957 | src &= 7; | |
26958 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
26959 | dst |= (1 << src); | |
26960 | m68k_incpc(4); | |
26961 | fill_prefetch_0 (); | |
26962 | m68k_write_memory_8(dsta,dst); | |
26963 | }}}}return 18; | |
26964 | } | |
26965 | unsigned long CPUFUNC(op_200_5)(uint32_t opcode) /* AND */ | |
26966 | { | |
26967 | uint32_t dstreg = opcode & 7; | |
26968 | OpcodeFamily = 2; CurrentInstrCycles = 8; | |
26969 | {{ int8_t src = get_ibyte_prefetch(2); | |
26970 | { int8_t dst = m68k_dreg(regs, dstreg); | |
26971 | src &= dst; | |
26972 | CLEAR_CZNV; | |
26973 | SET_ZFLG (((int8_t)(src)) == 0); | |
26974 | SET_NFLG (((int8_t)(src)) < 0); | |
26975 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
26976 | }}}m68k_incpc(4); | |
26977 | fill_prefetch_0 (); | |
26978 | return 8; | |
26979 | } | |
26980 | unsigned long CPUFUNC(op_210_5)(uint32_t opcode) /* AND */ | |
26981 | { | |
26982 | uint32_t dstreg = opcode & 7; | |
26983 | OpcodeFamily = 2; CurrentInstrCycles = 16; | |
26984 | {{ int8_t src = get_ibyte_prefetch(2); | |
26985 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
26986 | { int8_t dst = m68k_read_memory_8(dsta); | |
26987 | src &= dst; | |
26988 | CLEAR_CZNV; | |
26989 | SET_ZFLG (((int8_t)(src)) == 0); | |
26990 | SET_NFLG (((int8_t)(src)) < 0); | |
26991 | m68k_incpc(4); | |
26992 | fill_prefetch_0 (); | |
26993 | m68k_write_memory_8(dsta,src); | |
26994 | }}}}return 16; | |
26995 | } | |
26996 | unsigned long CPUFUNC(op_218_5)(uint32_t opcode) /* AND */ | |
26997 | { | |
26998 | uint32_t dstreg = opcode & 7; | |
26999 | OpcodeFamily = 2; CurrentInstrCycles = 16; | |
27000 | {{ int8_t src = get_ibyte_prefetch(2); | |
27001 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
27002 | { int8_t dst = m68k_read_memory_8(dsta); | |
27003 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
27004 | src &= dst; | |
27005 | CLEAR_CZNV; | |
27006 | SET_ZFLG (((int8_t)(src)) == 0); | |
27007 | SET_NFLG (((int8_t)(src)) < 0); | |
27008 | m68k_incpc(4); | |
27009 | fill_prefetch_0 (); | |
27010 | m68k_write_memory_8(dsta,src); | |
27011 | }}}}return 16; | |
27012 | } | |
27013 | unsigned long CPUFUNC(op_220_5)(uint32_t opcode) /* AND */ | |
27014 | { | |
27015 | uint32_t dstreg = opcode & 7; | |
27016 | OpcodeFamily = 2; CurrentInstrCycles = 18; | |
27017 | {{ int8_t src = get_ibyte_prefetch(2); | |
27018 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
27019 | { int8_t dst = m68k_read_memory_8(dsta); | |
27020 | m68k_areg (regs, dstreg) = dsta; | |
27021 | src &= dst; | |
27022 | CLEAR_CZNV; | |
27023 | SET_ZFLG (((int8_t)(src)) == 0); | |
27024 | SET_NFLG (((int8_t)(src)) < 0); | |
27025 | m68k_incpc(4); | |
27026 | fill_prefetch_0 (); | |
27027 | m68k_write_memory_8(dsta,src); | |
27028 | }}}}return 18; | |
27029 | } | |
27030 | unsigned long CPUFUNC(op_228_5)(uint32_t opcode) /* AND */ | |
27031 | { | |
27032 | uint32_t dstreg = opcode & 7; | |
27033 | OpcodeFamily = 2; CurrentInstrCycles = 20; | |
27034 | {{ int8_t src = get_ibyte_prefetch(2); | |
27035 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); | |
27036 | { int8_t dst = m68k_read_memory_8(dsta); | |
27037 | src &= dst; | |
27038 | CLEAR_CZNV; | |
27039 | SET_ZFLG (((int8_t)(src)) == 0); | |
27040 | SET_NFLG (((int8_t)(src)) < 0); | |
27041 | m68k_incpc(6); | |
27042 | fill_prefetch_0 (); | |
27043 | m68k_write_memory_8(dsta,src); | |
27044 | }}}}return 20; | |
27045 | } | |
27046 | unsigned long CPUFUNC(op_230_5)(uint32_t opcode) /* AND */ | |
27047 | { | |
27048 | uint32_t dstreg = opcode & 7; | |
27049 | OpcodeFamily = 2; CurrentInstrCycles = 22; | |
27050 | {{ int8_t src = get_ibyte_prefetch(2); | |
27051 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); | |
27052 | BusCyclePenalty += 2; | |
27053 | { int8_t dst = m68k_read_memory_8(dsta); | |
27054 | src &= dst; | |
27055 | CLEAR_CZNV; | |
27056 | SET_ZFLG (((int8_t)(src)) == 0); | |
27057 | SET_NFLG (((int8_t)(src)) < 0); | |
27058 | m68k_incpc(6); | |
27059 | fill_prefetch_0 (); | |
27060 | m68k_write_memory_8(dsta,src); | |
27061 | }}}}return 22; | |
27062 | } | |
27063 | unsigned long CPUFUNC(op_238_5)(uint32_t opcode) /* AND */ | |
27064 | { | |
27065 | OpcodeFamily = 2; CurrentInstrCycles = 20; | |
27066 | {{ int8_t src = get_ibyte_prefetch(2); | |
27067 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); | |
27068 | { int8_t dst = m68k_read_memory_8(dsta); | |
27069 | src &= dst; | |
27070 | CLEAR_CZNV; | |
27071 | SET_ZFLG (((int8_t)(src)) == 0); | |
27072 | SET_NFLG (((int8_t)(src)) < 0); | |
27073 | m68k_incpc(6); | |
27074 | fill_prefetch_0 (); | |
27075 | m68k_write_memory_8(dsta,src); | |
27076 | }}}}return 20; | |
27077 | } | |
27078 | unsigned long CPUFUNC(op_239_5)(uint32_t opcode) /* AND */ | |
27079 | { | |
27080 | OpcodeFamily = 2; CurrentInstrCycles = 24; | |
27081 | {{ int8_t src = get_ibyte_prefetch(2); | |
27082 | { uint32_t dsta = get_ilong_prefetch(4); | |
27083 | { int8_t dst = m68k_read_memory_8(dsta); | |
27084 | src &= dst; | |
27085 | CLEAR_CZNV; | |
27086 | SET_ZFLG (((int8_t)(src)) == 0); | |
27087 | SET_NFLG (((int8_t)(src)) < 0); | |
27088 | m68k_incpc(8); | |
27089 | fill_prefetch_0 (); | |
27090 | m68k_write_memory_8(dsta,src); | |
27091 | }}}}return 24; | |
27092 | } | |
27093 | unsigned long CPUFUNC(op_23c_5)(uint32_t opcode) /* ANDSR */ | |
27094 | { | |
27095 | OpcodeFamily = 5; CurrentInstrCycles = 20; | |
27096 | { MakeSR(); | |
27097 | { int16_t src = get_iword_prefetch(2); | |
27098 | src |= 0xFF00; | |
27099 | regs.sr &= src; | |
27100 | MakeFromSR(); | |
27101 | }}m68k_incpc(4); | |
27102 | fill_prefetch_0 (); | |
27103 | return 20; | |
27104 | } | |
27105 | unsigned long CPUFUNC(op_240_5)(uint32_t opcode) /* AND */ | |
27106 | { | |
27107 | uint32_t dstreg = opcode & 7; | |
27108 | OpcodeFamily = 2; CurrentInstrCycles = 8; | |
27109 | {{ int16_t src = get_iword_prefetch(2); | |
27110 | { int16_t dst = m68k_dreg(regs, dstreg); | |
27111 | src &= dst; | |
27112 | CLEAR_CZNV; | |
27113 | SET_ZFLG (((int16_t)(src)) == 0); | |
27114 | SET_NFLG (((int16_t)(src)) < 0); | |
27115 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
27116 | }}}m68k_incpc(4); | |
27117 | fill_prefetch_0 (); | |
27118 | return 8; | |
27119 | } | |
27120 | unsigned long CPUFUNC(op_250_5)(uint32_t opcode) /* AND */ | |
27121 | { | |
27122 | uint32_t dstreg = opcode & 7; | |
27123 | OpcodeFamily = 2; CurrentInstrCycles = 16; | |
27124 | {{ int16_t src = get_iword_prefetch(2); | |
27125 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
27126 | if ((dsta & 1) != 0) { | |
27127 | last_fault_for_exception_3 = dsta; | |
27128 | last_op_for_exception_3 = opcode; | |
27129 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
27130 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
27131 | goto endlabel1662; | |
27132 | } | |
27133 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
27134 | src &= dst; | |
27135 | CLEAR_CZNV; | |
27136 | SET_ZFLG (((int16_t)(src)) == 0); | |
27137 | SET_NFLG (((int16_t)(src)) < 0); | |
27138 | m68k_incpc(4); | |
27139 | fill_prefetch_0 (); | |
27140 | m68k_write_memory_16(dsta,src); | |
27141 | }}}}}endlabel1662: ; | |
27142 | return 16; | |
27143 | } | |
27144 | unsigned long CPUFUNC(op_258_5)(uint32_t opcode) /* AND */ | |
27145 | { | |
27146 | uint32_t dstreg = opcode & 7; | |
27147 | OpcodeFamily = 2; CurrentInstrCycles = 16; | |
27148 | {{ int16_t src = get_iword_prefetch(2); | |
27149 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
27150 | if ((dsta & 1) != 0) { | |
27151 | last_fault_for_exception_3 = dsta; | |
27152 | last_op_for_exception_3 = opcode; | |
27153 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
27154 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
27155 | goto endlabel1663; | |
27156 | } | |
27157 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
27158 | m68k_areg(regs, dstreg) += 2; | |
27159 | src &= dst; | |
27160 | CLEAR_CZNV; | |
27161 | SET_ZFLG (((int16_t)(src)) == 0); | |
27162 | SET_NFLG (((int16_t)(src)) < 0); | |
27163 | m68k_incpc(4); | |
27164 | fill_prefetch_0 (); | |
27165 | m68k_write_memory_16(dsta,src); | |
27166 | }}}}}endlabel1663: ; | |
27167 | return 16; | |
27168 | } | |
27169 | unsigned long CPUFUNC(op_260_5)(uint32_t opcode) /* AND */ | |
27170 | { | |
27171 | uint32_t dstreg = opcode & 7; | |
27172 | OpcodeFamily = 2; CurrentInstrCycles = 18; | |
27173 | {{ int16_t src = get_iword_prefetch(2); | |
27174 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
27175 | if ((dsta & 1) != 0) { | |
27176 | last_fault_for_exception_3 = dsta; | |
27177 | last_op_for_exception_3 = opcode; | |
27178 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
27179 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
27180 | goto endlabel1664; | |
27181 | } | |
27182 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
27183 | m68k_areg (regs, dstreg) = dsta; | |
27184 | src &= dst; | |
27185 | CLEAR_CZNV; | |
27186 | SET_ZFLG (((int16_t)(src)) == 0); | |
27187 | SET_NFLG (((int16_t)(src)) < 0); | |
27188 | m68k_incpc(4); | |
27189 | fill_prefetch_0 (); | |
27190 | m68k_write_memory_16(dsta,src); | |
27191 | }}}}}endlabel1664: ; | |
27192 | return 18; | |
27193 | } | |
27194 | unsigned long CPUFUNC(op_268_5)(uint32_t opcode) /* AND */ | |
27195 | { | |
27196 | uint32_t dstreg = opcode & 7; | |
27197 | OpcodeFamily = 2; CurrentInstrCycles = 20; | |
27198 | {{ int16_t src = get_iword_prefetch(2); | |
27199 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); | |
27200 | if ((dsta & 1) != 0) { | |
27201 | last_fault_for_exception_3 = dsta; | |
27202 | last_op_for_exception_3 = opcode; | |
27203 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
27204 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
27205 | goto endlabel1665; | |
27206 | } | |
27207 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
27208 | src &= dst; | |
27209 | CLEAR_CZNV; | |
27210 | SET_ZFLG (((int16_t)(src)) == 0); | |
27211 | SET_NFLG (((int16_t)(src)) < 0); | |
27212 | m68k_incpc(6); | |
27213 | fill_prefetch_0 (); | |
27214 | m68k_write_memory_16(dsta,src); | |
27215 | }}}}}endlabel1665: ; | |
27216 | return 20; | |
27217 | } | |
27218 | unsigned long CPUFUNC(op_270_5)(uint32_t opcode) /* AND */ | |
27219 | { | |
27220 | uint32_t dstreg = opcode & 7; | |
27221 | OpcodeFamily = 2; CurrentInstrCycles = 22; | |
27222 | {{ int16_t src = get_iword_prefetch(2); | |
27223 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); | |
27224 | BusCyclePenalty += 2; | |
27225 | if ((dsta & 1) != 0) { | |
27226 | last_fault_for_exception_3 = dsta; | |
27227 | last_op_for_exception_3 = opcode; | |
27228 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
27229 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
27230 | goto endlabel1666; | |
27231 | } | |
27232 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
27233 | src &= dst; | |
27234 | CLEAR_CZNV; | |
27235 | SET_ZFLG (((int16_t)(src)) == 0); | |
27236 | SET_NFLG (((int16_t)(src)) < 0); | |
27237 | m68k_incpc(6); | |
27238 | fill_prefetch_0 (); | |
27239 | m68k_write_memory_16(dsta,src); | |
27240 | }}}}}endlabel1666: ; | |
27241 | return 22; | |
27242 | } | |
27243 | unsigned long CPUFUNC(op_278_5)(uint32_t opcode) /* AND */ | |
27244 | { | |
27245 | OpcodeFamily = 2; CurrentInstrCycles = 20; | |
27246 | {{ int16_t src = get_iword_prefetch(2); | |
27247 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); | |
27248 | if ((dsta & 1) != 0) { | |
27249 | last_fault_for_exception_3 = dsta; | |
27250 | last_op_for_exception_3 = opcode; | |
27251 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
27252 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
27253 | goto endlabel1667; | |
27254 | } | |
27255 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
27256 | src &= dst; | |
27257 | CLEAR_CZNV; | |
27258 | SET_ZFLG (((int16_t)(src)) == 0); | |
27259 | SET_NFLG (((int16_t)(src)) < 0); | |
27260 | m68k_incpc(6); | |
27261 | fill_prefetch_0 (); | |
27262 | m68k_write_memory_16(dsta,src); | |
27263 | }}}}}endlabel1667: ; | |
27264 | return 20; | |
27265 | } | |
27266 | unsigned long CPUFUNC(op_279_5)(uint32_t opcode) /* AND */ | |
27267 | { | |
27268 | OpcodeFamily = 2; CurrentInstrCycles = 24; | |
27269 | {{ int16_t src = get_iword_prefetch(2); | |
27270 | { uint32_t dsta = get_ilong_prefetch(4); | |
27271 | if ((dsta & 1) != 0) { | |
27272 | last_fault_for_exception_3 = dsta; | |
27273 | last_op_for_exception_3 = opcode; | |
27274 | last_addr_for_exception_3 = m68k_getpc() + 8; | |
27275 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
27276 | goto endlabel1668; | |
27277 | } | |
27278 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
27279 | src &= dst; | |
27280 | CLEAR_CZNV; | |
27281 | SET_ZFLG (((int16_t)(src)) == 0); | |
27282 | SET_NFLG (((int16_t)(src)) < 0); | |
27283 | m68k_incpc(8); | |
27284 | fill_prefetch_0 (); | |
27285 | m68k_write_memory_16(dsta,src); | |
27286 | }}}}}endlabel1668: ; | |
27287 | return 24; | |
27288 | } | |
27289 | unsigned long CPUFUNC(op_27c_5)(uint32_t opcode) /* ANDSR */ | |
27290 | { | |
27291 | OpcodeFamily = 5; CurrentInstrCycles = 20; | |
27292 | {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel1669; } | |
27293 | { MakeSR(); | |
27294 | { int16_t src = get_iword_prefetch(2); | |
27295 | regs.sr &= src; | |
27296 | MakeFromSR(); | |
27297 | }}}m68k_incpc(4); | |
27298 | fill_prefetch_0 (); | |
27299 | endlabel1669: ; | |
27300 | return 20; | |
27301 | } | |
27302 | unsigned long CPUFUNC(op_280_5)(uint32_t opcode) /* AND */ | |
27303 | { | |
27304 | uint32_t dstreg = opcode & 7; | |
27305 | OpcodeFamily = 2; CurrentInstrCycles = 16; | |
27306 | {{ int32_t src = get_ilong_prefetch(2); | |
27307 | { int32_t dst = m68k_dreg(regs, dstreg); | |
27308 | src &= dst; | |
27309 | CLEAR_CZNV; | |
27310 | SET_ZFLG (((int32_t)(src)) == 0); | |
27311 | SET_NFLG (((int32_t)(src)) < 0); | |
27312 | m68k_dreg(regs, dstreg) = (src); | |
27313 | }}}m68k_incpc(6); | |
27314 | fill_prefetch_0 (); | |
27315 | return 16; | |
27316 | } | |
27317 | unsigned long CPUFUNC(op_290_5)(uint32_t opcode) /* AND */ | |
27318 | { | |
27319 | uint32_t dstreg = opcode & 7; | |
27320 | OpcodeFamily = 2; CurrentInstrCycles = 28; | |
27321 | {{ int32_t src = get_ilong_prefetch(2); | |
27322 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
27323 | if ((dsta & 1) != 0) { | |
27324 | last_fault_for_exception_3 = dsta; | |
27325 | last_op_for_exception_3 = opcode; | |
27326 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
27327 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
27328 | goto endlabel1671; | |
27329 | } | |
27330 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
27331 | src &= dst; | |
27332 | CLEAR_CZNV; | |
27333 | SET_ZFLG (((int32_t)(src)) == 0); | |
27334 | SET_NFLG (((int32_t)(src)) < 0); | |
27335 | m68k_incpc(6); | |
27336 | fill_prefetch_0 (); | |
27337 | m68k_write_memory_32(dsta,src); | |
27338 | }}}}}endlabel1671: ; | |
27339 | return 28; | |
27340 | } | |
27341 | unsigned long CPUFUNC(op_298_5)(uint32_t opcode) /* AND */ | |
27342 | { | |
27343 | uint32_t dstreg = opcode & 7; | |
27344 | OpcodeFamily = 2; CurrentInstrCycles = 28; | |
27345 | {{ int32_t src = get_ilong_prefetch(2); | |
27346 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
27347 | if ((dsta & 1) != 0) { | |
27348 | last_fault_for_exception_3 = dsta; | |
27349 | last_op_for_exception_3 = opcode; | |
27350 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
27351 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
27352 | goto endlabel1672; | |
27353 | } | |
27354 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
27355 | m68k_areg(regs, dstreg) += 4; | |
27356 | src &= dst; | |
27357 | CLEAR_CZNV; | |
27358 | SET_ZFLG (((int32_t)(src)) == 0); | |
27359 | SET_NFLG (((int32_t)(src)) < 0); | |
27360 | m68k_incpc(6); | |
27361 | fill_prefetch_0 (); | |
27362 | m68k_write_memory_32(dsta,src); | |
27363 | }}}}}endlabel1672: ; | |
27364 | return 28; | |
27365 | } | |
27366 | unsigned long CPUFUNC(op_2a0_5)(uint32_t opcode) /* AND */ | |
27367 | { | |
27368 | uint32_t dstreg = opcode & 7; | |
27369 | OpcodeFamily = 2; CurrentInstrCycles = 30; | |
27370 | {{ int32_t src = get_ilong_prefetch(2); | |
27371 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
27372 | if ((dsta & 1) != 0) { | |
27373 | last_fault_for_exception_3 = dsta; | |
27374 | last_op_for_exception_3 = opcode; | |
27375 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
27376 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
27377 | goto endlabel1673; | |
27378 | } | |
27379 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
27380 | m68k_areg (regs, dstreg) = dsta; | |
27381 | src &= dst; | |
27382 | CLEAR_CZNV; | |
27383 | SET_ZFLG (((int32_t)(src)) == 0); | |
27384 | SET_NFLG (((int32_t)(src)) < 0); | |
27385 | m68k_incpc(6); | |
27386 | fill_prefetch_0 (); | |
27387 | m68k_write_memory_32(dsta,src); | |
27388 | }}}}}endlabel1673: ; | |
27389 | return 30; | |
27390 | } | |
27391 | unsigned long CPUFUNC(op_2a8_5)(uint32_t opcode) /* AND */ | |
27392 | { | |
27393 | uint32_t dstreg = opcode & 7; | |
27394 | OpcodeFamily = 2; CurrentInstrCycles = 32; | |
27395 | {{ int32_t src = get_ilong_prefetch(2); | |
27396 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(6); | |
27397 | if ((dsta & 1) != 0) { | |
27398 | last_fault_for_exception_3 = dsta; | |
27399 | last_op_for_exception_3 = opcode; | |
27400 | last_addr_for_exception_3 = m68k_getpc() + 8; | |
27401 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
27402 | goto endlabel1674; | |
27403 | } | |
27404 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
27405 | src &= dst; | |
27406 | CLEAR_CZNV; | |
27407 | SET_ZFLG (((int32_t)(src)) == 0); | |
27408 | SET_NFLG (((int32_t)(src)) < 0); | |
27409 | m68k_incpc(8); | |
27410 | fill_prefetch_0 (); | |
27411 | m68k_write_memory_32(dsta,src); | |
27412 | }}}}}endlabel1674: ; | |
27413 | return 32; | |
27414 | } | |
27415 | unsigned long CPUFUNC(op_2b0_5)(uint32_t opcode) /* AND */ | |
27416 | { | |
27417 | uint32_t dstreg = opcode & 7; | |
27418 | OpcodeFamily = 2; CurrentInstrCycles = 34; | |
27419 | {{ int32_t src = get_ilong_prefetch(2); | |
27420 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(6)); | |
27421 | BusCyclePenalty += 2; | |
27422 | if ((dsta & 1) != 0) { | |
27423 | last_fault_for_exception_3 = dsta; | |
27424 | last_op_for_exception_3 = opcode; | |
27425 | last_addr_for_exception_3 = m68k_getpc() + 8; | |
27426 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
27427 | goto endlabel1675; | |
27428 | } | |
27429 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
27430 | src &= dst; | |
27431 | CLEAR_CZNV; | |
27432 | SET_ZFLG (((int32_t)(src)) == 0); | |
27433 | SET_NFLG (((int32_t)(src)) < 0); | |
27434 | m68k_incpc(8); | |
27435 | fill_prefetch_0 (); | |
27436 | m68k_write_memory_32(dsta,src); | |
27437 | }}}}}endlabel1675: ; | |
27438 | return 34; | |
27439 | } | |
27440 | unsigned long CPUFUNC(op_2b8_5)(uint32_t opcode) /* AND */ | |
27441 | { | |
27442 | OpcodeFamily = 2; CurrentInstrCycles = 32; | |
27443 | {{ int32_t src = get_ilong_prefetch(2); | |
27444 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(6); | |
27445 | if ((dsta & 1) != 0) { | |
27446 | last_fault_for_exception_3 = dsta; | |
27447 | last_op_for_exception_3 = opcode; | |
27448 | last_addr_for_exception_3 = m68k_getpc() + 8; | |
27449 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
27450 | goto endlabel1676; | |
27451 | } | |
27452 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
27453 | src &= dst; | |
27454 | CLEAR_CZNV; | |
27455 | SET_ZFLG (((int32_t)(src)) == 0); | |
27456 | SET_NFLG (((int32_t)(src)) < 0); | |
27457 | m68k_incpc(8); | |
27458 | fill_prefetch_0 (); | |
27459 | m68k_write_memory_32(dsta,src); | |
27460 | }}}}}endlabel1676: ; | |
27461 | return 32; | |
27462 | } | |
27463 | unsigned long CPUFUNC(op_2b9_5)(uint32_t opcode) /* AND */ | |
27464 | { | |
27465 | OpcodeFamily = 2; CurrentInstrCycles = 36; | |
27466 | {{ int32_t src = get_ilong_prefetch(2); | |
27467 | { uint32_t dsta = get_ilong_prefetch(6); | |
27468 | if ((dsta & 1) != 0) { | |
27469 | last_fault_for_exception_3 = dsta; | |
27470 | last_op_for_exception_3 = opcode; | |
27471 | last_addr_for_exception_3 = m68k_getpc() + 10; | |
27472 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
27473 | goto endlabel1677; | |
27474 | } | |
27475 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
27476 | src &= dst; | |
27477 | CLEAR_CZNV; | |
27478 | SET_ZFLG (((int32_t)(src)) == 0); | |
27479 | SET_NFLG (((int32_t)(src)) < 0); | |
27480 | m68k_incpc(10); | |
27481 | fill_prefetch_0 (); | |
27482 | m68k_write_memory_32(dsta,src); | |
27483 | }}}}}endlabel1677: ; | |
27484 | return 36; | |
27485 | } | |
27486 | unsigned long CPUFUNC(op_400_5)(uint32_t opcode) /* SUB */ | |
27487 | { | |
27488 | uint32_t dstreg = opcode & 7; | |
27489 | OpcodeFamily = 7; CurrentInstrCycles = 8; | |
27490 | {{ int8_t src = get_ibyte_prefetch(2); | |
27491 | { int8_t dst = m68k_dreg(regs, dstreg); | |
27492 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
27493 | { int flgs = ((int8_t)(src)) < 0; | |
27494 | int flgo = ((int8_t)(dst)) < 0; | |
27495 | int flgn = ((int8_t)(newv)) < 0; | |
27496 | SET_ZFLG (((int8_t)(newv)) == 0); | |
27497 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
27498 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
27499 | COPY_CARRY; | |
27500 | SET_NFLG (flgn != 0); | |
27501 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
27502 | }}}}}}m68k_incpc(4); | |
27503 | fill_prefetch_0 (); | |
27504 | return 8; | |
27505 | } | |
27506 | unsigned long CPUFUNC(op_410_5)(uint32_t opcode) /* SUB */ | |
27507 | { | |
27508 | uint32_t dstreg = opcode & 7; | |
27509 | OpcodeFamily = 7; CurrentInstrCycles = 16; | |
27510 | {{ int8_t src = get_ibyte_prefetch(2); | |
27511 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
27512 | { int8_t dst = m68k_read_memory_8(dsta); | |
27513 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
27514 | { int flgs = ((int8_t)(src)) < 0; | |
27515 | int flgo = ((int8_t)(dst)) < 0; | |
27516 | int flgn = ((int8_t)(newv)) < 0; | |
27517 | SET_ZFLG (((int8_t)(newv)) == 0); | |
27518 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
27519 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
27520 | COPY_CARRY; | |
27521 | SET_NFLG (flgn != 0); | |
27522 | m68k_incpc(4); | |
27523 | fill_prefetch_0 (); | |
27524 | m68k_write_memory_8(dsta,newv); | |
27525 | }}}}}}}return 16; | |
27526 | } | |
27527 | unsigned long CPUFUNC(op_418_5)(uint32_t opcode) /* SUB */ | |
27528 | { | |
27529 | uint32_t dstreg = opcode & 7; | |
27530 | OpcodeFamily = 7; CurrentInstrCycles = 16; | |
27531 | {{ int8_t src = get_ibyte_prefetch(2); | |
27532 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
27533 | { int8_t dst = m68k_read_memory_8(dsta); | |
27534 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
27535 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
27536 | { int flgs = ((int8_t)(src)) < 0; | |
27537 | int flgo = ((int8_t)(dst)) < 0; | |
27538 | int flgn = ((int8_t)(newv)) < 0; | |
27539 | SET_ZFLG (((int8_t)(newv)) == 0); | |
27540 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
27541 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
27542 | COPY_CARRY; | |
27543 | SET_NFLG (flgn != 0); | |
27544 | m68k_incpc(4); | |
27545 | fill_prefetch_0 (); | |
27546 | m68k_write_memory_8(dsta,newv); | |
27547 | }}}}}}}return 16; | |
27548 | } | |
27549 | unsigned long CPUFUNC(op_420_5)(uint32_t opcode) /* SUB */ | |
27550 | { | |
27551 | uint32_t dstreg = opcode & 7; | |
27552 | OpcodeFamily = 7; CurrentInstrCycles = 18; | |
27553 | {{ int8_t src = get_ibyte_prefetch(2); | |
27554 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
27555 | { int8_t dst = m68k_read_memory_8(dsta); | |
27556 | m68k_areg (regs, dstreg) = dsta; | |
27557 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
27558 | { int flgs = ((int8_t)(src)) < 0; | |
27559 | int flgo = ((int8_t)(dst)) < 0; | |
27560 | int flgn = ((int8_t)(newv)) < 0; | |
27561 | SET_ZFLG (((int8_t)(newv)) == 0); | |
27562 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
27563 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
27564 | COPY_CARRY; | |
27565 | SET_NFLG (flgn != 0); | |
27566 | m68k_incpc(4); | |
27567 | fill_prefetch_0 (); | |
27568 | m68k_write_memory_8(dsta,newv); | |
27569 | }}}}}}}return 18; | |
27570 | } | |
27571 | unsigned long CPUFUNC(op_428_5)(uint32_t opcode) /* SUB */ | |
27572 | { | |
27573 | uint32_t dstreg = opcode & 7; | |
27574 | OpcodeFamily = 7; CurrentInstrCycles = 20; | |
27575 | {{ int8_t src = get_ibyte_prefetch(2); | |
27576 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); | |
27577 | { int8_t dst = m68k_read_memory_8(dsta); | |
27578 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
27579 | { int flgs = ((int8_t)(src)) < 0; | |
27580 | int flgo = ((int8_t)(dst)) < 0; | |
27581 | int flgn = ((int8_t)(newv)) < 0; | |
27582 | SET_ZFLG (((int8_t)(newv)) == 0); | |
27583 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
27584 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
27585 | COPY_CARRY; | |
27586 | SET_NFLG (flgn != 0); | |
27587 | m68k_incpc(6); | |
27588 | fill_prefetch_0 (); | |
27589 | m68k_write_memory_8(dsta,newv); | |
27590 | }}}}}}}return 20; | |
27591 | } | |
27592 | unsigned long CPUFUNC(op_430_5)(uint32_t opcode) /* SUB */ | |
27593 | { | |
27594 | uint32_t dstreg = opcode & 7; | |
27595 | OpcodeFamily = 7; CurrentInstrCycles = 22; | |
27596 | {{ int8_t src = get_ibyte_prefetch(2); | |
27597 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); | |
27598 | BusCyclePenalty += 2; | |
27599 | { int8_t dst = m68k_read_memory_8(dsta); | |
27600 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
27601 | { int flgs = ((int8_t)(src)) < 0; | |
27602 | int flgo = ((int8_t)(dst)) < 0; | |
27603 | int flgn = ((int8_t)(newv)) < 0; | |
27604 | SET_ZFLG (((int8_t)(newv)) == 0); | |
27605 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
27606 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
27607 | COPY_CARRY; | |
27608 | SET_NFLG (flgn != 0); | |
27609 | m68k_incpc(6); | |
27610 | fill_prefetch_0 (); | |
27611 | m68k_write_memory_8(dsta,newv); | |
27612 | }}}}}}}return 22; | |
27613 | } | |
27614 | unsigned long CPUFUNC(op_438_5)(uint32_t opcode) /* SUB */ | |
27615 | { | |
27616 | OpcodeFamily = 7; CurrentInstrCycles = 20; | |
27617 | {{ int8_t src = get_ibyte_prefetch(2); | |
27618 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); | |
27619 | { int8_t dst = m68k_read_memory_8(dsta); | |
27620 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
27621 | { int flgs = ((int8_t)(src)) < 0; | |
27622 | int flgo = ((int8_t)(dst)) < 0; | |
27623 | int flgn = ((int8_t)(newv)) < 0; | |
27624 | SET_ZFLG (((int8_t)(newv)) == 0); | |
27625 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
27626 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
27627 | COPY_CARRY; | |
27628 | SET_NFLG (flgn != 0); | |
27629 | m68k_incpc(6); | |
27630 | fill_prefetch_0 (); | |
27631 | m68k_write_memory_8(dsta,newv); | |
27632 | }}}}}}}return 20; | |
27633 | } | |
27634 | unsigned long CPUFUNC(op_439_5)(uint32_t opcode) /* SUB */ | |
27635 | { | |
27636 | OpcodeFamily = 7; CurrentInstrCycles = 24; | |
27637 | {{ int8_t src = get_ibyte_prefetch(2); | |
27638 | { uint32_t dsta = get_ilong_prefetch(4); | |
27639 | { int8_t dst = m68k_read_memory_8(dsta); | |
27640 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
27641 | { int flgs = ((int8_t)(src)) < 0; | |
27642 | int flgo = ((int8_t)(dst)) < 0; | |
27643 | int flgn = ((int8_t)(newv)) < 0; | |
27644 | SET_ZFLG (((int8_t)(newv)) == 0); | |
27645 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
27646 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
27647 | COPY_CARRY; | |
27648 | SET_NFLG (flgn != 0); | |
27649 | m68k_incpc(8); | |
27650 | fill_prefetch_0 (); | |
27651 | m68k_write_memory_8(dsta,newv); | |
27652 | }}}}}}}return 24; | |
27653 | } | |
27654 | unsigned long CPUFUNC(op_440_5)(uint32_t opcode) /* SUB */ | |
27655 | { | |
27656 | uint32_t dstreg = opcode & 7; | |
27657 | OpcodeFamily = 7; CurrentInstrCycles = 8; | |
27658 | {{ int16_t src = get_iword_prefetch(2); | |
27659 | { int16_t dst = m68k_dreg(regs, dstreg); | |
27660 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
27661 | { int flgs = ((int16_t)(src)) < 0; | |
27662 | int flgo = ((int16_t)(dst)) < 0; | |
27663 | int flgn = ((int16_t)(newv)) < 0; | |
27664 | SET_ZFLG (((int16_t)(newv)) == 0); | |
27665 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
27666 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
27667 | COPY_CARRY; | |
27668 | SET_NFLG (flgn != 0); | |
27669 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
27670 | }}}}}}m68k_incpc(4); | |
27671 | fill_prefetch_0 (); | |
27672 | return 8; | |
27673 | } | |
27674 | unsigned long CPUFUNC(op_450_5)(uint32_t opcode) /* SUB */ | |
27675 | { | |
27676 | uint32_t dstreg = opcode & 7; | |
27677 | OpcodeFamily = 7; CurrentInstrCycles = 16; | |
27678 | {{ int16_t src = get_iword_prefetch(2); | |
27679 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
27680 | if ((dsta & 1) != 0) { | |
27681 | last_fault_for_exception_3 = dsta; | |
27682 | last_op_for_exception_3 = opcode; | |
27683 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
27684 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
27685 | goto endlabel1687; | |
27686 | } | |
27687 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
27688 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
27689 | { int flgs = ((int16_t)(src)) < 0; | |
27690 | int flgo = ((int16_t)(dst)) < 0; | |
27691 | int flgn = ((int16_t)(newv)) < 0; | |
27692 | SET_ZFLG (((int16_t)(newv)) == 0); | |
27693 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
27694 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
27695 | COPY_CARRY; | |
27696 | SET_NFLG (flgn != 0); | |
27697 | m68k_incpc(4); | |
27698 | fill_prefetch_0 (); | |
27699 | m68k_write_memory_16(dsta,newv); | |
27700 | }}}}}}}}endlabel1687: ; | |
27701 | return 16; | |
27702 | } | |
27703 | unsigned long CPUFUNC(op_458_5)(uint32_t opcode) /* SUB */ | |
27704 | { | |
27705 | uint32_t dstreg = opcode & 7; | |
27706 | OpcodeFamily = 7; CurrentInstrCycles = 16; | |
27707 | {{ int16_t src = get_iword_prefetch(2); | |
27708 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
27709 | if ((dsta & 1) != 0) { | |
27710 | last_fault_for_exception_3 = dsta; | |
27711 | last_op_for_exception_3 = opcode; | |
27712 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
27713 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
27714 | goto endlabel1688; | |
27715 | } | |
27716 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
27717 | m68k_areg(regs, dstreg) += 2; | |
27718 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
27719 | { int flgs = ((int16_t)(src)) < 0; | |
27720 | int flgo = ((int16_t)(dst)) < 0; | |
27721 | int flgn = ((int16_t)(newv)) < 0; | |
27722 | SET_ZFLG (((int16_t)(newv)) == 0); | |
27723 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
27724 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
27725 | COPY_CARRY; | |
27726 | SET_NFLG (flgn != 0); | |
27727 | m68k_incpc(4); | |
27728 | fill_prefetch_0 (); | |
27729 | m68k_write_memory_16(dsta,newv); | |
27730 | }}}}}}}}endlabel1688: ; | |
27731 | return 16; | |
27732 | } | |
27733 | unsigned long CPUFUNC(op_460_5)(uint32_t opcode) /* SUB */ | |
27734 | { | |
27735 | uint32_t dstreg = opcode & 7; | |
27736 | OpcodeFamily = 7; CurrentInstrCycles = 18; | |
27737 | {{ int16_t src = get_iword_prefetch(2); | |
27738 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
27739 | if ((dsta & 1) != 0) { | |
27740 | last_fault_for_exception_3 = dsta; | |
27741 | last_op_for_exception_3 = opcode; | |
27742 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
27743 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
27744 | goto endlabel1689; | |
27745 | } | |
27746 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
27747 | m68k_areg (regs, dstreg) = dsta; | |
27748 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
27749 | { int flgs = ((int16_t)(src)) < 0; | |
27750 | int flgo = ((int16_t)(dst)) < 0; | |
27751 | int flgn = ((int16_t)(newv)) < 0; | |
27752 | SET_ZFLG (((int16_t)(newv)) == 0); | |
27753 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
27754 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
27755 | COPY_CARRY; | |
27756 | SET_NFLG (flgn != 0); | |
27757 | m68k_incpc(4); | |
27758 | fill_prefetch_0 (); | |
27759 | m68k_write_memory_16(dsta,newv); | |
27760 | }}}}}}}}endlabel1689: ; | |
27761 | return 18; | |
27762 | } | |
27763 | unsigned long CPUFUNC(op_468_5)(uint32_t opcode) /* SUB */ | |
27764 | { | |
27765 | uint32_t dstreg = opcode & 7; | |
27766 | OpcodeFamily = 7; CurrentInstrCycles = 20; | |
27767 | {{ int16_t src = get_iword_prefetch(2); | |
27768 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); | |
27769 | if ((dsta & 1) != 0) { | |
27770 | last_fault_for_exception_3 = dsta; | |
27771 | last_op_for_exception_3 = opcode; | |
27772 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
27773 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
27774 | goto endlabel1690; | |
27775 | } | |
27776 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
27777 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
27778 | { int flgs = ((int16_t)(src)) < 0; | |
27779 | int flgo = ((int16_t)(dst)) < 0; | |
27780 | int flgn = ((int16_t)(newv)) < 0; | |
27781 | SET_ZFLG (((int16_t)(newv)) == 0); | |
27782 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
27783 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
27784 | COPY_CARRY; | |
27785 | SET_NFLG (flgn != 0); | |
27786 | m68k_incpc(6); | |
27787 | fill_prefetch_0 (); | |
27788 | m68k_write_memory_16(dsta,newv); | |
27789 | }}}}}}}}endlabel1690: ; | |
27790 | return 20; | |
27791 | } | |
27792 | unsigned long CPUFUNC(op_470_5)(uint32_t opcode) /* SUB */ | |
27793 | { | |
27794 | uint32_t dstreg = opcode & 7; | |
27795 | OpcodeFamily = 7; CurrentInstrCycles = 22; | |
27796 | {{ int16_t src = get_iword_prefetch(2); | |
27797 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); | |
27798 | BusCyclePenalty += 2; | |
27799 | if ((dsta & 1) != 0) { | |
27800 | last_fault_for_exception_3 = dsta; | |
27801 | last_op_for_exception_3 = opcode; | |
27802 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
27803 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
27804 | goto endlabel1691; | |
27805 | } | |
27806 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
27807 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
27808 | { int flgs = ((int16_t)(src)) < 0; | |
27809 | int flgo = ((int16_t)(dst)) < 0; | |
27810 | int flgn = ((int16_t)(newv)) < 0; | |
27811 | SET_ZFLG (((int16_t)(newv)) == 0); | |
27812 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
27813 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
27814 | COPY_CARRY; | |
27815 | SET_NFLG (flgn != 0); | |
27816 | m68k_incpc(6); | |
27817 | fill_prefetch_0 (); | |
27818 | m68k_write_memory_16(dsta,newv); | |
27819 | }}}}}}}}endlabel1691: ; | |
27820 | return 22; | |
27821 | } | |
27822 | unsigned long CPUFUNC(op_478_5)(uint32_t opcode) /* SUB */ | |
27823 | { | |
27824 | OpcodeFamily = 7; CurrentInstrCycles = 20; | |
27825 | {{ int16_t src = get_iword_prefetch(2); | |
27826 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); | |
27827 | if ((dsta & 1) != 0) { | |
27828 | last_fault_for_exception_3 = dsta; | |
27829 | last_op_for_exception_3 = opcode; | |
27830 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
27831 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
27832 | goto endlabel1692; | |
27833 | } | |
27834 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
27835 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
27836 | { int flgs = ((int16_t)(src)) < 0; | |
27837 | int flgo = ((int16_t)(dst)) < 0; | |
27838 | int flgn = ((int16_t)(newv)) < 0; | |
27839 | SET_ZFLG (((int16_t)(newv)) == 0); | |
27840 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
27841 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
27842 | COPY_CARRY; | |
27843 | SET_NFLG (flgn != 0); | |
27844 | m68k_incpc(6); | |
27845 | fill_prefetch_0 (); | |
27846 | m68k_write_memory_16(dsta,newv); | |
27847 | }}}}}}}}endlabel1692: ; | |
27848 | return 20; | |
27849 | } | |
27850 | unsigned long CPUFUNC(op_479_5)(uint32_t opcode) /* SUB */ | |
27851 | { | |
27852 | OpcodeFamily = 7; CurrentInstrCycles = 24; | |
27853 | {{ int16_t src = get_iword_prefetch(2); | |
27854 | { uint32_t dsta = get_ilong_prefetch(4); | |
27855 | if ((dsta & 1) != 0) { | |
27856 | last_fault_for_exception_3 = dsta; | |
27857 | last_op_for_exception_3 = opcode; | |
27858 | last_addr_for_exception_3 = m68k_getpc() + 8; | |
27859 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
27860 | goto endlabel1693; | |
27861 | } | |
27862 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
27863 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
27864 | { int flgs = ((int16_t)(src)) < 0; | |
27865 | int flgo = ((int16_t)(dst)) < 0; | |
27866 | int flgn = ((int16_t)(newv)) < 0; | |
27867 | SET_ZFLG (((int16_t)(newv)) == 0); | |
27868 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
27869 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
27870 | COPY_CARRY; | |
27871 | SET_NFLG (flgn != 0); | |
27872 | m68k_incpc(8); | |
27873 | fill_prefetch_0 (); | |
27874 | m68k_write_memory_16(dsta,newv); | |
27875 | }}}}}}}}endlabel1693: ; | |
27876 | return 24; | |
27877 | } | |
27878 | unsigned long CPUFUNC(op_480_5)(uint32_t opcode) /* SUB */ | |
27879 | { | |
27880 | uint32_t dstreg = opcode & 7; | |
27881 | OpcodeFamily = 7; CurrentInstrCycles = 16; | |
27882 | {{ int32_t src = get_ilong_prefetch(2); | |
27883 | { int32_t dst = m68k_dreg(regs, dstreg); | |
27884 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
27885 | { int flgs = ((int32_t)(src)) < 0; | |
27886 | int flgo = ((int32_t)(dst)) < 0; | |
27887 | int flgn = ((int32_t)(newv)) < 0; | |
27888 | SET_ZFLG (((int32_t)(newv)) == 0); | |
27889 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
27890 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
27891 | COPY_CARRY; | |
27892 | SET_NFLG (flgn != 0); | |
27893 | m68k_dreg(regs, dstreg) = (newv); | |
27894 | }}}}}}m68k_incpc(6); | |
27895 | fill_prefetch_0 (); | |
27896 | return 16; | |
27897 | } | |
27898 | unsigned long CPUFUNC(op_490_5)(uint32_t opcode) /* SUB */ | |
27899 | { | |
27900 | uint32_t dstreg = opcode & 7; | |
27901 | OpcodeFamily = 7; CurrentInstrCycles = 28; | |
27902 | {{ int32_t src = get_ilong_prefetch(2); | |
27903 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
27904 | if ((dsta & 1) != 0) { | |
27905 | last_fault_for_exception_3 = dsta; | |
27906 | last_op_for_exception_3 = opcode; | |
27907 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
27908 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
27909 | goto endlabel1695; | |
27910 | } | |
27911 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
27912 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
27913 | { int flgs = ((int32_t)(src)) < 0; | |
27914 | int flgo = ((int32_t)(dst)) < 0; | |
27915 | int flgn = ((int32_t)(newv)) < 0; | |
27916 | SET_ZFLG (((int32_t)(newv)) == 0); | |
27917 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
27918 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
27919 | COPY_CARRY; | |
27920 | SET_NFLG (flgn != 0); | |
27921 | m68k_incpc(6); | |
27922 | fill_prefetch_0 (); | |
27923 | m68k_write_memory_32(dsta,newv); | |
27924 | }}}}}}}}endlabel1695: ; | |
27925 | return 28; | |
27926 | } | |
27927 | unsigned long CPUFUNC(op_498_5)(uint32_t opcode) /* SUB */ | |
27928 | { | |
27929 | uint32_t dstreg = opcode & 7; | |
27930 | OpcodeFamily = 7; CurrentInstrCycles = 28; | |
27931 | {{ int32_t src = get_ilong_prefetch(2); | |
27932 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
27933 | if ((dsta & 1) != 0) { | |
27934 | last_fault_for_exception_3 = dsta; | |
27935 | last_op_for_exception_3 = opcode; | |
27936 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
27937 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
27938 | goto endlabel1696; | |
27939 | } | |
27940 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
27941 | m68k_areg(regs, dstreg) += 4; | |
27942 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
27943 | { int flgs = ((int32_t)(src)) < 0; | |
27944 | int flgo = ((int32_t)(dst)) < 0; | |
27945 | int flgn = ((int32_t)(newv)) < 0; | |
27946 | SET_ZFLG (((int32_t)(newv)) == 0); | |
27947 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
27948 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
27949 | COPY_CARRY; | |
27950 | SET_NFLG (flgn != 0); | |
27951 | m68k_incpc(6); | |
27952 | fill_prefetch_0 (); | |
27953 | m68k_write_memory_32(dsta,newv); | |
27954 | }}}}}}}}endlabel1696: ; | |
27955 | return 28; | |
27956 | } | |
27957 | unsigned long CPUFUNC(op_4a0_5)(uint32_t opcode) /* SUB */ | |
27958 | { | |
27959 | uint32_t dstreg = opcode & 7; | |
27960 | OpcodeFamily = 7; CurrentInstrCycles = 30; | |
27961 | {{ int32_t src = get_ilong_prefetch(2); | |
27962 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
27963 | if ((dsta & 1) != 0) { | |
27964 | last_fault_for_exception_3 = dsta; | |
27965 | last_op_for_exception_3 = opcode; | |
27966 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
27967 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
27968 | goto endlabel1697; | |
27969 | } | |
27970 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
27971 | m68k_areg (regs, dstreg) = dsta; | |
27972 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
27973 | { int flgs = ((int32_t)(src)) < 0; | |
27974 | int flgo = ((int32_t)(dst)) < 0; | |
27975 | int flgn = ((int32_t)(newv)) < 0; | |
27976 | SET_ZFLG (((int32_t)(newv)) == 0); | |
27977 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
27978 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
27979 | COPY_CARRY; | |
27980 | SET_NFLG (flgn != 0); | |
27981 | m68k_incpc(6); | |
27982 | fill_prefetch_0 (); | |
27983 | m68k_write_memory_32(dsta,newv); | |
27984 | }}}}}}}}endlabel1697: ; | |
27985 | return 30; | |
27986 | } | |
27987 | unsigned long CPUFUNC(op_4a8_5)(uint32_t opcode) /* SUB */ | |
27988 | { | |
27989 | uint32_t dstreg = opcode & 7; | |
27990 | OpcodeFamily = 7; CurrentInstrCycles = 32; | |
27991 | {{ int32_t src = get_ilong_prefetch(2); | |
27992 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(6); | |
27993 | if ((dsta & 1) != 0) { | |
27994 | last_fault_for_exception_3 = dsta; | |
27995 | last_op_for_exception_3 = opcode; | |
27996 | last_addr_for_exception_3 = m68k_getpc() + 8; | |
27997 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
27998 | goto endlabel1698; | |
27999 | } | |
28000 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
28001 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
28002 | { int flgs = ((int32_t)(src)) < 0; | |
28003 | int flgo = ((int32_t)(dst)) < 0; | |
28004 | int flgn = ((int32_t)(newv)) < 0; | |
28005 | SET_ZFLG (((int32_t)(newv)) == 0); | |
28006 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
28007 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
28008 | COPY_CARRY; | |
28009 | SET_NFLG (flgn != 0); | |
28010 | m68k_incpc(8); | |
28011 | fill_prefetch_0 (); | |
28012 | m68k_write_memory_32(dsta,newv); | |
28013 | }}}}}}}}endlabel1698: ; | |
28014 | return 32; | |
28015 | } | |
28016 | unsigned long CPUFUNC(op_4b0_5)(uint32_t opcode) /* SUB */ | |
28017 | { | |
28018 | uint32_t dstreg = opcode & 7; | |
28019 | OpcodeFamily = 7; CurrentInstrCycles = 34; | |
28020 | {{ int32_t src = get_ilong_prefetch(2); | |
28021 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(6)); | |
28022 | BusCyclePenalty += 2; | |
28023 | if ((dsta & 1) != 0) { | |
28024 | last_fault_for_exception_3 = dsta; | |
28025 | last_op_for_exception_3 = opcode; | |
28026 | last_addr_for_exception_3 = m68k_getpc() + 8; | |
28027 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
28028 | goto endlabel1699; | |
28029 | } | |
28030 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
28031 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
28032 | { int flgs = ((int32_t)(src)) < 0; | |
28033 | int flgo = ((int32_t)(dst)) < 0; | |
28034 | int flgn = ((int32_t)(newv)) < 0; | |
28035 | SET_ZFLG (((int32_t)(newv)) == 0); | |
28036 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
28037 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
28038 | COPY_CARRY; | |
28039 | SET_NFLG (flgn != 0); | |
28040 | m68k_incpc(8); | |
28041 | fill_prefetch_0 (); | |
28042 | m68k_write_memory_32(dsta,newv); | |
28043 | }}}}}}}}endlabel1699: ; | |
28044 | return 34; | |
28045 | } | |
28046 | unsigned long CPUFUNC(op_4b8_5)(uint32_t opcode) /* SUB */ | |
28047 | { | |
28048 | OpcodeFamily = 7; CurrentInstrCycles = 32; | |
28049 | {{ int32_t src = get_ilong_prefetch(2); | |
28050 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(6); | |
28051 | if ((dsta & 1) != 0) { | |
28052 | last_fault_for_exception_3 = dsta; | |
28053 | last_op_for_exception_3 = opcode; | |
28054 | last_addr_for_exception_3 = m68k_getpc() + 8; | |
28055 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
28056 | goto endlabel1700; | |
28057 | } | |
28058 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
28059 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
28060 | { int flgs = ((int32_t)(src)) < 0; | |
28061 | int flgo = ((int32_t)(dst)) < 0; | |
28062 | int flgn = ((int32_t)(newv)) < 0; | |
28063 | SET_ZFLG (((int32_t)(newv)) == 0); | |
28064 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
28065 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
28066 | COPY_CARRY; | |
28067 | SET_NFLG (flgn != 0); | |
28068 | m68k_incpc(8); | |
28069 | fill_prefetch_0 (); | |
28070 | m68k_write_memory_32(dsta,newv); | |
28071 | }}}}}}}}endlabel1700: ; | |
28072 | return 32; | |
28073 | } | |
28074 | unsigned long CPUFUNC(op_4b9_5)(uint32_t opcode) /* SUB */ | |
28075 | { | |
28076 | OpcodeFamily = 7; CurrentInstrCycles = 36; | |
28077 | {{ int32_t src = get_ilong_prefetch(2); | |
28078 | { uint32_t dsta = get_ilong_prefetch(6); | |
28079 | if ((dsta & 1) != 0) { | |
28080 | last_fault_for_exception_3 = dsta; | |
28081 | last_op_for_exception_3 = opcode; | |
28082 | last_addr_for_exception_3 = m68k_getpc() + 10; | |
28083 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
28084 | goto endlabel1701; | |
28085 | } | |
28086 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
28087 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
28088 | { int flgs = ((int32_t)(src)) < 0; | |
28089 | int flgo = ((int32_t)(dst)) < 0; | |
28090 | int flgn = ((int32_t)(newv)) < 0; | |
28091 | SET_ZFLG (((int32_t)(newv)) == 0); | |
28092 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
28093 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
28094 | COPY_CARRY; | |
28095 | SET_NFLG (flgn != 0); | |
28096 | m68k_incpc(10); | |
28097 | fill_prefetch_0 (); | |
28098 | m68k_write_memory_32(dsta,newv); | |
28099 | }}}}}}}}endlabel1701: ; | |
28100 | return 36; | |
28101 | } | |
28102 | unsigned long CPUFUNC(op_600_5)(uint32_t opcode) /* ADD */ | |
28103 | { | |
28104 | uint32_t dstreg = opcode & 7; | |
28105 | OpcodeFamily = 11; CurrentInstrCycles = 8; | |
28106 | {{ int8_t src = get_ibyte_prefetch(2); | |
28107 | { int8_t dst = m68k_dreg(regs, dstreg); | |
28108 | { refill_prefetch (m68k_getpc(), 2); | |
28109 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
28110 | { int flgs = ((int8_t)(src)) < 0; | |
28111 | int flgo = ((int8_t)(dst)) < 0; | |
28112 | int flgn = ((int8_t)(newv)) < 0; | |
28113 | SET_ZFLG (((int8_t)(newv)) == 0); | |
28114 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
28115 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
28116 | COPY_CARRY; | |
28117 | SET_NFLG (flgn != 0); | |
28118 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
28119 | }}}}}}m68k_incpc(4); | |
28120 | fill_prefetch_0 (); | |
28121 | return 8; | |
28122 | } | |
28123 | unsigned long CPUFUNC(op_610_5)(uint32_t opcode) /* ADD */ | |
28124 | { | |
28125 | uint32_t dstreg = opcode & 7; | |
28126 | OpcodeFamily = 11; CurrentInstrCycles = 16; | |
28127 | {{ int8_t src = get_ibyte_prefetch(2); | |
28128 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
28129 | { int8_t dst = m68k_read_memory_8(dsta); | |
28130 | { refill_prefetch (m68k_getpc(), 2); | |
28131 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
28132 | { int flgs = ((int8_t)(src)) < 0; | |
28133 | int flgo = ((int8_t)(dst)) < 0; | |
28134 | int flgn = ((int8_t)(newv)) < 0; | |
28135 | SET_ZFLG (((int8_t)(newv)) == 0); | |
28136 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
28137 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
28138 | COPY_CARRY; | |
28139 | SET_NFLG (flgn != 0); | |
28140 | m68k_incpc(4); | |
28141 | fill_prefetch_0 (); | |
28142 | m68k_write_memory_8(dsta,newv); | |
28143 | }}}}}}}return 16; | |
28144 | } | |
28145 | unsigned long CPUFUNC(op_618_5)(uint32_t opcode) /* ADD */ | |
28146 | { | |
28147 | uint32_t dstreg = opcode & 7; | |
28148 | OpcodeFamily = 11; CurrentInstrCycles = 16; | |
28149 | {{ int8_t src = get_ibyte_prefetch(2); | |
28150 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
28151 | { int8_t dst = m68k_read_memory_8(dsta); | |
28152 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
28153 | { refill_prefetch (m68k_getpc(), 2); | |
28154 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
28155 | { int flgs = ((int8_t)(src)) < 0; | |
28156 | int flgo = ((int8_t)(dst)) < 0; | |
28157 | int flgn = ((int8_t)(newv)) < 0; | |
28158 | SET_ZFLG (((int8_t)(newv)) == 0); | |
28159 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
28160 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
28161 | COPY_CARRY; | |
28162 | SET_NFLG (flgn != 0); | |
28163 | m68k_incpc(4); | |
28164 | fill_prefetch_0 (); | |
28165 | m68k_write_memory_8(dsta,newv); | |
28166 | }}}}}}}return 16; | |
28167 | } | |
28168 | unsigned long CPUFUNC(op_620_5)(uint32_t opcode) /* ADD */ | |
28169 | { | |
28170 | uint32_t dstreg = opcode & 7; | |
28171 | OpcodeFamily = 11; CurrentInstrCycles = 18; | |
28172 | {{ int8_t src = get_ibyte_prefetch(2); | |
28173 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
28174 | { int8_t dst = m68k_read_memory_8(dsta); | |
28175 | m68k_areg (regs, dstreg) = dsta; | |
28176 | { refill_prefetch (m68k_getpc(), 2); | |
28177 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
28178 | { int flgs = ((int8_t)(src)) < 0; | |
28179 | int flgo = ((int8_t)(dst)) < 0; | |
28180 | int flgn = ((int8_t)(newv)) < 0; | |
28181 | SET_ZFLG (((int8_t)(newv)) == 0); | |
28182 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
28183 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
28184 | COPY_CARRY; | |
28185 | SET_NFLG (flgn != 0); | |
28186 | m68k_incpc(4); | |
28187 | fill_prefetch_0 (); | |
28188 | m68k_write_memory_8(dsta,newv); | |
28189 | }}}}}}}return 18; | |
28190 | } | |
28191 | unsigned long CPUFUNC(op_628_5)(uint32_t opcode) /* ADD */ | |
28192 | { | |
28193 | uint32_t dstreg = opcode & 7; | |
28194 | OpcodeFamily = 11; CurrentInstrCycles = 20; | |
28195 | {{ int8_t src = get_ibyte_prefetch(2); | |
28196 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); | |
28197 | { int8_t dst = m68k_read_memory_8(dsta); | |
28198 | { refill_prefetch (m68k_getpc(), 2); | |
28199 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
28200 | { int flgs = ((int8_t)(src)) < 0; | |
28201 | int flgo = ((int8_t)(dst)) < 0; | |
28202 | int flgn = ((int8_t)(newv)) < 0; | |
28203 | SET_ZFLG (((int8_t)(newv)) == 0); | |
28204 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
28205 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
28206 | COPY_CARRY; | |
28207 | SET_NFLG (flgn != 0); | |
28208 | m68k_incpc(6); | |
28209 | fill_prefetch_0 (); | |
28210 | m68k_write_memory_8(dsta,newv); | |
28211 | }}}}}}}return 20; | |
28212 | } | |
28213 | unsigned long CPUFUNC(op_630_5)(uint32_t opcode) /* ADD */ | |
28214 | { | |
28215 | uint32_t dstreg = opcode & 7; | |
28216 | OpcodeFamily = 11; CurrentInstrCycles = 22; | |
28217 | {{ int8_t src = get_ibyte_prefetch(2); | |
28218 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); | |
28219 | BusCyclePenalty += 2; | |
28220 | { int8_t dst = m68k_read_memory_8(dsta); | |
28221 | { refill_prefetch (m68k_getpc(), 2); | |
28222 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
28223 | { int flgs = ((int8_t)(src)) < 0; | |
28224 | int flgo = ((int8_t)(dst)) < 0; | |
28225 | int flgn = ((int8_t)(newv)) < 0; | |
28226 | SET_ZFLG (((int8_t)(newv)) == 0); | |
28227 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
28228 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
28229 | COPY_CARRY; | |
28230 | SET_NFLG (flgn != 0); | |
28231 | m68k_incpc(6); | |
28232 | fill_prefetch_0 (); | |
28233 | m68k_write_memory_8(dsta,newv); | |
28234 | }}}}}}}return 22; | |
28235 | } | |
28236 | unsigned long CPUFUNC(op_638_5)(uint32_t opcode) /* ADD */ | |
28237 | { | |
28238 | OpcodeFamily = 11; CurrentInstrCycles = 20; | |
28239 | {{ int8_t src = get_ibyte_prefetch(2); | |
28240 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); | |
28241 | { int8_t dst = m68k_read_memory_8(dsta); | |
28242 | { refill_prefetch (m68k_getpc(), 2); | |
28243 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
28244 | { int flgs = ((int8_t)(src)) < 0; | |
28245 | int flgo = ((int8_t)(dst)) < 0; | |
28246 | int flgn = ((int8_t)(newv)) < 0; | |
28247 | SET_ZFLG (((int8_t)(newv)) == 0); | |
28248 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
28249 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
28250 | COPY_CARRY; | |
28251 | SET_NFLG (flgn != 0); | |
28252 | m68k_incpc(6); | |
28253 | fill_prefetch_0 (); | |
28254 | m68k_write_memory_8(dsta,newv); | |
28255 | }}}}}}}return 20; | |
28256 | } | |
28257 | unsigned long CPUFUNC(op_639_5)(uint32_t opcode) /* ADD */ | |
28258 | { | |
28259 | OpcodeFamily = 11; CurrentInstrCycles = 24; | |
28260 | {{ int8_t src = get_ibyte_prefetch(2); | |
28261 | { uint32_t dsta = get_ilong_prefetch(4); | |
28262 | { int8_t dst = m68k_read_memory_8(dsta); | |
28263 | { refill_prefetch (m68k_getpc(), 2); | |
28264 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
28265 | { int flgs = ((int8_t)(src)) < 0; | |
28266 | int flgo = ((int8_t)(dst)) < 0; | |
28267 | int flgn = ((int8_t)(newv)) < 0; | |
28268 | SET_ZFLG (((int8_t)(newv)) == 0); | |
28269 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
28270 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
28271 | COPY_CARRY; | |
28272 | SET_NFLG (flgn != 0); | |
28273 | m68k_incpc(8); | |
28274 | fill_prefetch_0 (); | |
28275 | m68k_write_memory_8(dsta,newv); | |
28276 | }}}}}}}return 24; | |
28277 | } | |
28278 | unsigned long CPUFUNC(op_640_5)(uint32_t opcode) /* ADD */ | |
28279 | { | |
28280 | uint32_t dstreg = opcode & 7; | |
28281 | OpcodeFamily = 11; CurrentInstrCycles = 8; | |
28282 | {{ int16_t src = get_iword_prefetch(2); | |
28283 | { int16_t dst = m68k_dreg(regs, dstreg); | |
28284 | { refill_prefetch (m68k_getpc(), 2); | |
28285 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
28286 | { int flgs = ((int16_t)(src)) < 0; | |
28287 | int flgo = ((int16_t)(dst)) < 0; | |
28288 | int flgn = ((int16_t)(newv)) < 0; | |
28289 | SET_ZFLG (((int16_t)(newv)) == 0); | |
28290 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
28291 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
28292 | COPY_CARRY; | |
28293 | SET_NFLG (flgn != 0); | |
28294 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
28295 | }}}}}}m68k_incpc(4); | |
28296 | fill_prefetch_0 (); | |
28297 | return 8; | |
28298 | } | |
28299 | unsigned long CPUFUNC(op_650_5)(uint32_t opcode) /* ADD */ | |
28300 | { | |
28301 | uint32_t dstreg = opcode & 7; | |
28302 | OpcodeFamily = 11; CurrentInstrCycles = 16; | |
28303 | {{ int16_t src = get_iword_prefetch(2); | |
28304 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
28305 | if ((dsta & 1) != 0) { | |
28306 | last_fault_for_exception_3 = dsta; | |
28307 | last_op_for_exception_3 = opcode; | |
28308 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
28309 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
28310 | goto endlabel1711; | |
28311 | } | |
28312 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
28313 | { refill_prefetch (m68k_getpc(), 2); | |
28314 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
28315 | { int flgs = ((int16_t)(src)) < 0; | |
28316 | int flgo = ((int16_t)(dst)) < 0; | |
28317 | int flgn = ((int16_t)(newv)) < 0; | |
28318 | SET_ZFLG (((int16_t)(newv)) == 0); | |
28319 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
28320 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
28321 | COPY_CARRY; | |
28322 | SET_NFLG (flgn != 0); | |
28323 | m68k_incpc(4); | |
28324 | fill_prefetch_0 (); | |
28325 | m68k_write_memory_16(dsta,newv); | |
28326 | }}}}}}}}endlabel1711: ; | |
28327 | return 16; | |
28328 | } | |
28329 | unsigned long CPUFUNC(op_658_5)(uint32_t opcode) /* ADD */ | |
28330 | { | |
28331 | uint32_t dstreg = opcode & 7; | |
28332 | OpcodeFamily = 11; CurrentInstrCycles = 16; | |
28333 | {{ int16_t src = get_iword_prefetch(2); | |
28334 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
28335 | if ((dsta & 1) != 0) { | |
28336 | last_fault_for_exception_3 = dsta; | |
28337 | last_op_for_exception_3 = opcode; | |
28338 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
28339 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
28340 | goto endlabel1712; | |
28341 | } | |
28342 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
28343 | m68k_areg(regs, dstreg) += 2; | |
28344 | { refill_prefetch (m68k_getpc(), 2); | |
28345 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
28346 | { int flgs = ((int16_t)(src)) < 0; | |
28347 | int flgo = ((int16_t)(dst)) < 0; | |
28348 | int flgn = ((int16_t)(newv)) < 0; | |
28349 | SET_ZFLG (((int16_t)(newv)) == 0); | |
28350 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
28351 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
28352 | COPY_CARRY; | |
28353 | SET_NFLG (flgn != 0); | |
28354 | m68k_incpc(4); | |
28355 | fill_prefetch_0 (); | |
28356 | m68k_write_memory_16(dsta,newv); | |
28357 | }}}}}}}}endlabel1712: ; | |
28358 | return 16; | |
28359 | } | |
28360 | unsigned long CPUFUNC(op_660_5)(uint32_t opcode) /* ADD */ | |
28361 | { | |
28362 | uint32_t dstreg = opcode & 7; | |
28363 | OpcodeFamily = 11; CurrentInstrCycles = 18; | |
28364 | {{ int16_t src = get_iword_prefetch(2); | |
28365 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
28366 | if ((dsta & 1) != 0) { | |
28367 | last_fault_for_exception_3 = dsta; | |
28368 | last_op_for_exception_3 = opcode; | |
28369 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
28370 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
28371 | goto endlabel1713; | |
28372 | } | |
28373 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
28374 | m68k_areg (regs, dstreg) = dsta; | |
28375 | { refill_prefetch (m68k_getpc(), 2); | |
28376 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
28377 | { int flgs = ((int16_t)(src)) < 0; | |
28378 | int flgo = ((int16_t)(dst)) < 0; | |
28379 | int flgn = ((int16_t)(newv)) < 0; | |
28380 | SET_ZFLG (((int16_t)(newv)) == 0); | |
28381 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
28382 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
28383 | COPY_CARRY; | |
28384 | SET_NFLG (flgn != 0); | |
28385 | m68k_incpc(4); | |
28386 | fill_prefetch_0 (); | |
28387 | m68k_write_memory_16(dsta,newv); | |
28388 | }}}}}}}}endlabel1713: ; | |
28389 | return 18; | |
28390 | } | |
28391 | unsigned long CPUFUNC(op_668_5)(uint32_t opcode) /* ADD */ | |
28392 | { | |
28393 | uint32_t dstreg = opcode & 7; | |
28394 | OpcodeFamily = 11; CurrentInstrCycles = 20; | |
28395 | {{ int16_t src = get_iword_prefetch(2); | |
28396 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); | |
28397 | if ((dsta & 1) != 0) { | |
28398 | last_fault_for_exception_3 = dsta; | |
28399 | last_op_for_exception_3 = opcode; | |
28400 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
28401 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
28402 | goto endlabel1714; | |
28403 | } | |
28404 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
28405 | { refill_prefetch (m68k_getpc(), 2); | |
28406 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
28407 | { int flgs = ((int16_t)(src)) < 0; | |
28408 | int flgo = ((int16_t)(dst)) < 0; | |
28409 | int flgn = ((int16_t)(newv)) < 0; | |
28410 | SET_ZFLG (((int16_t)(newv)) == 0); | |
28411 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
28412 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
28413 | COPY_CARRY; | |
28414 | SET_NFLG (flgn != 0); | |
28415 | m68k_incpc(6); | |
28416 | fill_prefetch_0 (); | |
28417 | m68k_write_memory_16(dsta,newv); | |
28418 | }}}}}}}}endlabel1714: ; | |
28419 | return 20; | |
28420 | } | |
28421 | unsigned long CPUFUNC(op_670_5)(uint32_t opcode) /* ADD */ | |
28422 | { | |
28423 | uint32_t dstreg = opcode & 7; | |
28424 | OpcodeFamily = 11; CurrentInstrCycles = 22; | |
28425 | {{ int16_t src = get_iword_prefetch(2); | |
28426 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); | |
28427 | BusCyclePenalty += 2; | |
28428 | if ((dsta & 1) != 0) { | |
28429 | last_fault_for_exception_3 = dsta; | |
28430 | last_op_for_exception_3 = opcode; | |
28431 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
28432 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
28433 | goto endlabel1715; | |
28434 | } | |
28435 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
28436 | { refill_prefetch (m68k_getpc(), 2); | |
28437 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
28438 | { int flgs = ((int16_t)(src)) < 0; | |
28439 | int flgo = ((int16_t)(dst)) < 0; | |
28440 | int flgn = ((int16_t)(newv)) < 0; | |
28441 | SET_ZFLG (((int16_t)(newv)) == 0); | |
28442 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
28443 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
28444 | COPY_CARRY; | |
28445 | SET_NFLG (flgn != 0); | |
28446 | m68k_incpc(6); | |
28447 | fill_prefetch_0 (); | |
28448 | m68k_write_memory_16(dsta,newv); | |
28449 | }}}}}}}}endlabel1715: ; | |
28450 | return 22; | |
28451 | } | |
28452 | unsigned long CPUFUNC(op_678_5)(uint32_t opcode) /* ADD */ | |
28453 | { | |
28454 | OpcodeFamily = 11; CurrentInstrCycles = 20; | |
28455 | {{ int16_t src = get_iword_prefetch(2); | |
28456 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); | |
28457 | if ((dsta & 1) != 0) { | |
28458 | last_fault_for_exception_3 = dsta; | |
28459 | last_op_for_exception_3 = opcode; | |
28460 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
28461 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
28462 | goto endlabel1716; | |
28463 | } | |
28464 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
28465 | { refill_prefetch (m68k_getpc(), 2); | |
28466 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
28467 | { int flgs = ((int16_t)(src)) < 0; | |
28468 | int flgo = ((int16_t)(dst)) < 0; | |
28469 | int flgn = ((int16_t)(newv)) < 0; | |
28470 | SET_ZFLG (((int16_t)(newv)) == 0); | |
28471 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
28472 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
28473 | COPY_CARRY; | |
28474 | SET_NFLG (flgn != 0); | |
28475 | m68k_incpc(6); | |
28476 | fill_prefetch_0 (); | |
28477 | m68k_write_memory_16(dsta,newv); | |
28478 | }}}}}}}}endlabel1716: ; | |
28479 | return 20; | |
28480 | } | |
28481 | unsigned long CPUFUNC(op_679_5)(uint32_t opcode) /* ADD */ | |
28482 | { | |
28483 | OpcodeFamily = 11; CurrentInstrCycles = 24; | |
28484 | {{ int16_t src = get_iword_prefetch(2); | |
28485 | { uint32_t dsta = get_ilong_prefetch(4); | |
28486 | if ((dsta & 1) != 0) { | |
28487 | last_fault_for_exception_3 = dsta; | |
28488 | last_op_for_exception_3 = opcode; | |
28489 | last_addr_for_exception_3 = m68k_getpc() + 8; | |
28490 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
28491 | goto endlabel1717; | |
28492 | } | |
28493 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
28494 | { refill_prefetch (m68k_getpc(), 2); | |
28495 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
28496 | { int flgs = ((int16_t)(src)) < 0; | |
28497 | int flgo = ((int16_t)(dst)) < 0; | |
28498 | int flgn = ((int16_t)(newv)) < 0; | |
28499 | SET_ZFLG (((int16_t)(newv)) == 0); | |
28500 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
28501 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
28502 | COPY_CARRY; | |
28503 | SET_NFLG (flgn != 0); | |
28504 | m68k_incpc(8); | |
28505 | fill_prefetch_0 (); | |
28506 | m68k_write_memory_16(dsta,newv); | |
28507 | }}}}}}}}endlabel1717: ; | |
28508 | return 24; | |
28509 | } | |
28510 | unsigned long CPUFUNC(op_680_5)(uint32_t opcode) /* ADD */ | |
28511 | { | |
28512 | uint32_t dstreg = opcode & 7; | |
28513 | OpcodeFamily = 11; CurrentInstrCycles = 16; | |
28514 | {{ int32_t src = get_ilong_prefetch(2); | |
28515 | { int32_t dst = m68k_dreg(regs, dstreg); | |
28516 | { refill_prefetch (m68k_getpc(), 2); | |
28517 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
28518 | { int flgs = ((int32_t)(src)) < 0; | |
28519 | int flgo = ((int32_t)(dst)) < 0; | |
28520 | int flgn = ((int32_t)(newv)) < 0; | |
28521 | SET_ZFLG (((int32_t)(newv)) == 0); | |
28522 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
28523 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
28524 | COPY_CARRY; | |
28525 | SET_NFLG (flgn != 0); | |
28526 | m68k_dreg(regs, dstreg) = (newv); | |
28527 | }}}}}}m68k_incpc(6); | |
28528 | fill_prefetch_0 (); | |
28529 | return 16; | |
28530 | } | |
28531 | unsigned long CPUFUNC(op_690_5)(uint32_t opcode) /* ADD */ | |
28532 | { | |
28533 | uint32_t dstreg = opcode & 7; | |
28534 | OpcodeFamily = 11; CurrentInstrCycles = 28; | |
28535 | {{ int32_t src = get_ilong_prefetch(2); | |
28536 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
28537 | if ((dsta & 1) != 0) { | |
28538 | last_fault_for_exception_3 = dsta; | |
28539 | last_op_for_exception_3 = opcode; | |
28540 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
28541 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
28542 | goto endlabel1719; | |
28543 | } | |
28544 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
28545 | { refill_prefetch (m68k_getpc(), 2); | |
28546 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
28547 | { int flgs = ((int32_t)(src)) < 0; | |
28548 | int flgo = ((int32_t)(dst)) < 0; | |
28549 | int flgn = ((int32_t)(newv)) < 0; | |
28550 | SET_ZFLG (((int32_t)(newv)) == 0); | |
28551 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
28552 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
28553 | COPY_CARRY; | |
28554 | SET_NFLG (flgn != 0); | |
28555 | m68k_incpc(6); | |
28556 | fill_prefetch_0 (); | |
28557 | m68k_write_memory_32(dsta,newv); | |
28558 | }}}}}}}}endlabel1719: ; | |
28559 | return 28; | |
28560 | } | |
28561 | unsigned long CPUFUNC(op_698_5)(uint32_t opcode) /* ADD */ | |
28562 | { | |
28563 | uint32_t dstreg = opcode & 7; | |
28564 | OpcodeFamily = 11; CurrentInstrCycles = 28; | |
28565 | {{ int32_t src = get_ilong_prefetch(2); | |
28566 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
28567 | if ((dsta & 1) != 0) { | |
28568 | last_fault_for_exception_3 = dsta; | |
28569 | last_op_for_exception_3 = opcode; | |
28570 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
28571 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
28572 | goto endlabel1720; | |
28573 | } | |
28574 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
28575 | m68k_areg(regs, dstreg) += 4; | |
28576 | { refill_prefetch (m68k_getpc(), 2); | |
28577 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
28578 | { int flgs = ((int32_t)(src)) < 0; | |
28579 | int flgo = ((int32_t)(dst)) < 0; | |
28580 | int flgn = ((int32_t)(newv)) < 0; | |
28581 | SET_ZFLG (((int32_t)(newv)) == 0); | |
28582 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
28583 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
28584 | COPY_CARRY; | |
28585 | SET_NFLG (flgn != 0); | |
28586 | m68k_incpc(6); | |
28587 | fill_prefetch_0 (); | |
28588 | m68k_write_memory_32(dsta,newv); | |
28589 | }}}}}}}}endlabel1720: ; | |
28590 | return 28; | |
28591 | } | |
28592 | unsigned long CPUFUNC(op_6a0_5)(uint32_t opcode) /* ADD */ | |
28593 | { | |
28594 | uint32_t dstreg = opcode & 7; | |
28595 | OpcodeFamily = 11; CurrentInstrCycles = 30; | |
28596 | {{ int32_t src = get_ilong_prefetch(2); | |
28597 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
28598 | if ((dsta & 1) != 0) { | |
28599 | last_fault_for_exception_3 = dsta; | |
28600 | last_op_for_exception_3 = opcode; | |
28601 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
28602 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
28603 | goto endlabel1721; | |
28604 | } | |
28605 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
28606 | m68k_areg (regs, dstreg) = dsta; | |
28607 | { refill_prefetch (m68k_getpc(), 2); | |
28608 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
28609 | { int flgs = ((int32_t)(src)) < 0; | |
28610 | int flgo = ((int32_t)(dst)) < 0; | |
28611 | int flgn = ((int32_t)(newv)) < 0; | |
28612 | SET_ZFLG (((int32_t)(newv)) == 0); | |
28613 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
28614 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
28615 | COPY_CARRY; | |
28616 | SET_NFLG (flgn != 0); | |
28617 | m68k_incpc(6); | |
28618 | fill_prefetch_0 (); | |
28619 | m68k_write_memory_32(dsta,newv); | |
28620 | }}}}}}}}endlabel1721: ; | |
28621 | return 30; | |
28622 | } | |
28623 | unsigned long CPUFUNC(op_6a8_5)(uint32_t opcode) /* ADD */ | |
28624 | { | |
28625 | uint32_t dstreg = opcode & 7; | |
28626 | OpcodeFamily = 11; CurrentInstrCycles = 32; | |
28627 | {{ int32_t src = get_ilong_prefetch(2); | |
28628 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(6); | |
28629 | if ((dsta & 1) != 0) { | |
28630 | last_fault_for_exception_3 = dsta; | |
28631 | last_op_for_exception_3 = opcode; | |
28632 | last_addr_for_exception_3 = m68k_getpc() + 8; | |
28633 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
28634 | goto endlabel1722; | |
28635 | } | |
28636 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
28637 | { refill_prefetch (m68k_getpc(), 2); | |
28638 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
28639 | { int flgs = ((int32_t)(src)) < 0; | |
28640 | int flgo = ((int32_t)(dst)) < 0; | |
28641 | int flgn = ((int32_t)(newv)) < 0; | |
28642 | SET_ZFLG (((int32_t)(newv)) == 0); | |
28643 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
28644 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
28645 | COPY_CARRY; | |
28646 | SET_NFLG (flgn != 0); | |
28647 | m68k_incpc(8); | |
28648 | fill_prefetch_0 (); | |
28649 | m68k_write_memory_32(dsta,newv); | |
28650 | }}}}}}}}endlabel1722: ; | |
28651 | return 32; | |
28652 | } | |
28653 | unsigned long CPUFUNC(op_6b0_5)(uint32_t opcode) /* ADD */ | |
28654 | { | |
28655 | uint32_t dstreg = opcode & 7; | |
28656 | OpcodeFamily = 11; CurrentInstrCycles = 34; | |
28657 | {{ int32_t src = get_ilong_prefetch(2); | |
28658 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(6)); | |
28659 | BusCyclePenalty += 2; | |
28660 | if ((dsta & 1) != 0) { | |
28661 | last_fault_for_exception_3 = dsta; | |
28662 | last_op_for_exception_3 = opcode; | |
28663 | last_addr_for_exception_3 = m68k_getpc() + 8; | |
28664 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
28665 | goto endlabel1723; | |
28666 | } | |
28667 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
28668 | { refill_prefetch (m68k_getpc(), 2); | |
28669 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
28670 | { int flgs = ((int32_t)(src)) < 0; | |
28671 | int flgo = ((int32_t)(dst)) < 0; | |
28672 | int flgn = ((int32_t)(newv)) < 0; | |
28673 | SET_ZFLG (((int32_t)(newv)) == 0); | |
28674 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
28675 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
28676 | COPY_CARRY; | |
28677 | SET_NFLG (flgn != 0); | |
28678 | m68k_incpc(8); | |
28679 | fill_prefetch_0 (); | |
28680 | m68k_write_memory_32(dsta,newv); | |
28681 | }}}}}}}}endlabel1723: ; | |
28682 | return 34; | |
28683 | } | |
28684 | unsigned long CPUFUNC(op_6b8_5)(uint32_t opcode) /* ADD */ | |
28685 | { | |
28686 | OpcodeFamily = 11; CurrentInstrCycles = 32; | |
28687 | {{ int32_t src = get_ilong_prefetch(2); | |
28688 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(6); | |
28689 | if ((dsta & 1) != 0) { | |
28690 | last_fault_for_exception_3 = dsta; | |
28691 | last_op_for_exception_3 = opcode; | |
28692 | last_addr_for_exception_3 = m68k_getpc() + 8; | |
28693 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
28694 | goto endlabel1724; | |
28695 | } | |
28696 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
28697 | { refill_prefetch (m68k_getpc(), 2); | |
28698 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
28699 | { int flgs = ((int32_t)(src)) < 0; | |
28700 | int flgo = ((int32_t)(dst)) < 0; | |
28701 | int flgn = ((int32_t)(newv)) < 0; | |
28702 | SET_ZFLG (((int32_t)(newv)) == 0); | |
28703 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
28704 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
28705 | COPY_CARRY; | |
28706 | SET_NFLG (flgn != 0); | |
28707 | m68k_incpc(8); | |
28708 | fill_prefetch_0 (); | |
28709 | m68k_write_memory_32(dsta,newv); | |
28710 | }}}}}}}}endlabel1724: ; | |
28711 | return 32; | |
28712 | } | |
28713 | unsigned long CPUFUNC(op_6b9_5)(uint32_t opcode) /* ADD */ | |
28714 | { | |
28715 | OpcodeFamily = 11; CurrentInstrCycles = 36; | |
28716 | {{ int32_t src = get_ilong_prefetch(2); | |
28717 | { uint32_t dsta = get_ilong_prefetch(6); | |
28718 | if ((dsta & 1) != 0) { | |
28719 | last_fault_for_exception_3 = dsta; | |
28720 | last_op_for_exception_3 = opcode; | |
28721 | last_addr_for_exception_3 = m68k_getpc() + 10; | |
28722 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
28723 | goto endlabel1725; | |
28724 | } | |
28725 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
28726 | { refill_prefetch (m68k_getpc(), 2); | |
28727 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
28728 | { int flgs = ((int32_t)(src)) < 0; | |
28729 | int flgo = ((int32_t)(dst)) < 0; | |
28730 | int flgn = ((int32_t)(newv)) < 0; | |
28731 | SET_ZFLG (((int32_t)(newv)) == 0); | |
28732 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
28733 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
28734 | COPY_CARRY; | |
28735 | SET_NFLG (flgn != 0); | |
28736 | m68k_incpc(10); | |
28737 | fill_prefetch_0 (); | |
28738 | m68k_write_memory_32(dsta,newv); | |
28739 | }}}}}}}}endlabel1725: ; | |
28740 | return 36; | |
28741 | } | |
28742 | unsigned long CPUFUNC(op_800_5)(uint32_t opcode) /* BTST */ | |
28743 | { | |
28744 | uint32_t dstreg = opcode & 7; | |
28745 | OpcodeFamily = 21; CurrentInstrCycles = 10; | |
28746 | {{ int16_t src = get_iword_prefetch(2); | |
28747 | { int32_t dst = m68k_dreg(regs, dstreg); | |
28748 | src &= 31; | |
28749 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
28750 | }}}m68k_incpc(4); | |
28751 | fill_prefetch_0 (); | |
28752 | return 10; | |
28753 | } | |
28754 | unsigned long CPUFUNC(op_810_5)(uint32_t opcode) /* BTST */ | |
28755 | { | |
28756 | uint32_t dstreg = opcode & 7; | |
28757 | OpcodeFamily = 21; CurrentInstrCycles = 12; | |
28758 | {{ int16_t src = get_iword_prefetch(2); | |
28759 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
28760 | { int8_t dst = m68k_read_memory_8(dsta); | |
28761 | src &= 7; | |
28762 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
28763 | }}}}m68k_incpc(4); | |
28764 | fill_prefetch_0 (); | |
28765 | return 12; | |
28766 | } | |
28767 | unsigned long CPUFUNC(op_818_5)(uint32_t opcode) /* BTST */ | |
28768 | { | |
28769 | uint32_t dstreg = opcode & 7; | |
28770 | OpcodeFamily = 21; CurrentInstrCycles = 12; | |
28771 | {{ int16_t src = get_iword_prefetch(2); | |
28772 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
28773 | { int8_t dst = m68k_read_memory_8(dsta); | |
28774 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
28775 | src &= 7; | |
28776 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
28777 | }}}}m68k_incpc(4); | |
28778 | fill_prefetch_0 (); | |
28779 | return 12; | |
28780 | } | |
28781 | unsigned long CPUFUNC(op_820_5)(uint32_t opcode) /* BTST */ | |
28782 | { | |
28783 | uint32_t dstreg = opcode & 7; | |
28784 | OpcodeFamily = 21; CurrentInstrCycles = 14; | |
28785 | {{ int16_t src = get_iword_prefetch(2); | |
28786 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
28787 | { int8_t dst = m68k_read_memory_8(dsta); | |
28788 | m68k_areg (regs, dstreg) = dsta; | |
28789 | src &= 7; | |
28790 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
28791 | }}}}m68k_incpc(4); | |
28792 | fill_prefetch_0 (); | |
28793 | return 14; | |
28794 | } | |
28795 | unsigned long CPUFUNC(op_828_5)(uint32_t opcode) /* BTST */ | |
28796 | { | |
28797 | uint32_t dstreg = opcode & 7; | |
28798 | OpcodeFamily = 21; CurrentInstrCycles = 16; | |
28799 | {{ int16_t src = get_iword_prefetch(2); | |
28800 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); | |
28801 | { int8_t dst = m68k_read_memory_8(dsta); | |
28802 | src &= 7; | |
28803 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
28804 | }}}}m68k_incpc(6); | |
28805 | fill_prefetch_0 (); | |
28806 | return 16; | |
28807 | } | |
28808 | unsigned long CPUFUNC(op_830_5)(uint32_t opcode) /* BTST */ | |
28809 | { | |
28810 | uint32_t dstreg = opcode & 7; | |
28811 | OpcodeFamily = 21; CurrentInstrCycles = 18; | |
28812 | {{ int16_t src = get_iword_prefetch(2); | |
28813 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); | |
28814 | BusCyclePenalty += 2; | |
28815 | { int8_t dst = m68k_read_memory_8(dsta); | |
28816 | src &= 7; | |
28817 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
28818 | }}}}m68k_incpc(6); | |
28819 | fill_prefetch_0 (); | |
28820 | return 18; | |
28821 | } | |
28822 | unsigned long CPUFUNC(op_838_5)(uint32_t opcode) /* BTST */ | |
28823 | { | |
28824 | OpcodeFamily = 21; CurrentInstrCycles = 16; | |
28825 | {{ int16_t src = get_iword_prefetch(2); | |
28826 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); | |
28827 | { int8_t dst = m68k_read_memory_8(dsta); | |
28828 | src &= 7; | |
28829 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
28830 | }}}}m68k_incpc(6); | |
28831 | fill_prefetch_0 (); | |
28832 | return 16; | |
28833 | } | |
28834 | unsigned long CPUFUNC(op_839_5)(uint32_t opcode) /* BTST */ | |
28835 | { | |
28836 | OpcodeFamily = 21; CurrentInstrCycles = 20; | |
28837 | {{ int16_t src = get_iword_prefetch(2); | |
28838 | { uint32_t dsta = get_ilong_prefetch(4); | |
28839 | { int8_t dst = m68k_read_memory_8(dsta); | |
28840 | src &= 7; | |
28841 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
28842 | }}}}m68k_incpc(8); | |
28843 | fill_prefetch_0 (); | |
28844 | return 20; | |
28845 | } | |
28846 | unsigned long CPUFUNC(op_83a_5)(uint32_t opcode) /* BTST */ | |
28847 | { | |
28848 | uint32_t dstreg = 2; | |
28849 | OpcodeFamily = 21; CurrentInstrCycles = 16; | |
28850 | {{ int16_t src = get_iword_prefetch(2); | |
28851 | { uint32_t dsta = m68k_getpc () + 4; | |
28852 | dsta += (int32_t)(int16_t)get_iword_prefetch(4); | |
28853 | { int8_t dst = m68k_read_memory_8(dsta); | |
28854 | src &= 7; | |
28855 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
28856 | }}}}m68k_incpc(6); | |
28857 | fill_prefetch_0 (); | |
28858 | return 16; | |
28859 | } | |
28860 | unsigned long CPUFUNC(op_83b_5)(uint32_t opcode) /* BTST */ | |
28861 | { | |
28862 | uint32_t dstreg = 3; | |
28863 | OpcodeFamily = 21; CurrentInstrCycles = 18; | |
28864 | {{ int16_t src = get_iword_prefetch(2); | |
28865 | { uint32_t tmppc = m68k_getpc() + 4; | |
28866 | uint32_t dsta = get_disp_ea_000(tmppc, get_iword_prefetch(4)); | |
28867 | BusCyclePenalty += 2; | |
28868 | { int8_t dst = m68k_read_memory_8(dsta); | |
28869 | src &= 7; | |
28870 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
28871 | }}}}m68k_incpc(6); | |
28872 | fill_prefetch_0 (); | |
28873 | return 18; | |
28874 | } | |
28875 | unsigned long CPUFUNC(op_83c_5)(uint32_t opcode) /* BTST */ | |
28876 | { | |
28877 | OpcodeFamily = 21; CurrentInstrCycles = 12; | |
28878 | {{ int16_t src = get_iword_prefetch(2); | |
28879 | { int8_t dst = get_ibyte_prefetch(4); | |
28880 | src &= 7; | |
28881 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
28882 | }}}m68k_incpc(6); | |
28883 | fill_prefetch_0 (); | |
28884 | return 12; | |
28885 | } | |
28886 | unsigned long CPUFUNC(op_840_5)(uint32_t opcode) /* BCHG */ | |
28887 | { | |
28888 | uint32_t dstreg = opcode & 7; | |
28889 | OpcodeFamily = 22; CurrentInstrCycles = 12; | |
28890 | {{ int16_t src = get_iword_prefetch(2); | |
28891 | { int32_t dst = m68k_dreg(regs, dstreg); | |
28892 | src &= 31; | |
28893 | dst ^= (1 << src); | |
28894 | SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); | |
28895 | m68k_dreg(regs, dstreg) = (dst); | |
28896 | }}}m68k_incpc(4); | |
28897 | fill_prefetch_0 (); | |
28898 | return 12; | |
28899 | } | |
28900 | unsigned long CPUFUNC(op_850_5)(uint32_t opcode) /* BCHG */ | |
28901 | { | |
28902 | uint32_t dstreg = opcode & 7; | |
28903 | OpcodeFamily = 22; CurrentInstrCycles = 16; | |
28904 | {{ int16_t src = get_iword_prefetch(2); | |
28905 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
28906 | { int8_t dst = m68k_read_memory_8(dsta); | |
28907 | src &= 7; | |
28908 | dst ^= (1 << src); | |
28909 | SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); | |
28910 | m68k_incpc(4); | |
28911 | fill_prefetch_0 (); | |
28912 | m68k_write_memory_8(dsta,dst); | |
28913 | }}}}return 16; | |
28914 | } | |
28915 | unsigned long CPUFUNC(op_858_5)(uint32_t opcode) /* BCHG */ | |
28916 | { | |
28917 | uint32_t dstreg = opcode & 7; | |
28918 | OpcodeFamily = 22; CurrentInstrCycles = 16; | |
28919 | {{ int16_t src = get_iword_prefetch(2); | |
28920 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
28921 | { int8_t dst = m68k_read_memory_8(dsta); | |
28922 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
28923 | src &= 7; | |
28924 | dst ^= (1 << src); | |
28925 | SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); | |
28926 | m68k_incpc(4); | |
28927 | fill_prefetch_0 (); | |
28928 | m68k_write_memory_8(dsta,dst); | |
28929 | }}}}return 16; | |
28930 | } | |
28931 | unsigned long CPUFUNC(op_860_5)(uint32_t opcode) /* BCHG */ | |
28932 | { | |
28933 | uint32_t dstreg = opcode & 7; | |
28934 | OpcodeFamily = 22; CurrentInstrCycles = 18; | |
28935 | {{ int16_t src = get_iword_prefetch(2); | |
28936 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
28937 | { int8_t dst = m68k_read_memory_8(dsta); | |
28938 | m68k_areg (regs, dstreg) = dsta; | |
28939 | src &= 7; | |
28940 | dst ^= (1 << src); | |
28941 | SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); | |
28942 | m68k_incpc(4); | |
28943 | fill_prefetch_0 (); | |
28944 | m68k_write_memory_8(dsta,dst); | |
28945 | }}}}return 18; | |
28946 | } | |
28947 | unsigned long CPUFUNC(op_868_5)(uint32_t opcode) /* BCHG */ | |
28948 | { | |
28949 | uint32_t dstreg = opcode & 7; | |
28950 | OpcodeFamily = 22; CurrentInstrCycles = 20; | |
28951 | {{ int16_t src = get_iword_prefetch(2); | |
28952 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); | |
28953 | { int8_t dst = m68k_read_memory_8(dsta); | |
28954 | src &= 7; | |
28955 | dst ^= (1 << src); | |
28956 | SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); | |
28957 | m68k_incpc(6); | |
28958 | fill_prefetch_0 (); | |
28959 | m68k_write_memory_8(dsta,dst); | |
28960 | }}}}return 20; | |
28961 | } | |
28962 | unsigned long CPUFUNC(op_870_5)(uint32_t opcode) /* BCHG */ | |
28963 | { | |
28964 | uint32_t dstreg = opcode & 7; | |
28965 | OpcodeFamily = 22; CurrentInstrCycles = 22; | |
28966 | {{ int16_t src = get_iword_prefetch(2); | |
28967 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); | |
28968 | BusCyclePenalty += 2; | |
28969 | { int8_t dst = m68k_read_memory_8(dsta); | |
28970 | src &= 7; | |
28971 | dst ^= (1 << src); | |
28972 | SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); | |
28973 | m68k_incpc(6); | |
28974 | fill_prefetch_0 (); | |
28975 | m68k_write_memory_8(dsta,dst); | |
28976 | }}}}return 22; | |
28977 | } | |
28978 | unsigned long CPUFUNC(op_878_5)(uint32_t opcode) /* BCHG */ | |
28979 | { | |
28980 | OpcodeFamily = 22; CurrentInstrCycles = 20; | |
28981 | {{ int16_t src = get_iword_prefetch(2); | |
28982 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); | |
28983 | { int8_t dst = m68k_read_memory_8(dsta); | |
28984 | src &= 7; | |
28985 | dst ^= (1 << src); | |
28986 | SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); | |
28987 | m68k_incpc(6); | |
28988 | fill_prefetch_0 (); | |
28989 | m68k_write_memory_8(dsta,dst); | |
28990 | }}}}return 20; | |
28991 | } | |
28992 | unsigned long CPUFUNC(op_879_5)(uint32_t opcode) /* BCHG */ | |
28993 | { | |
28994 | OpcodeFamily = 22; CurrentInstrCycles = 24; | |
28995 | {{ int16_t src = get_iword_prefetch(2); | |
28996 | { uint32_t dsta = get_ilong_prefetch(4); | |
28997 | { int8_t dst = m68k_read_memory_8(dsta); | |
28998 | src &= 7; | |
28999 | dst ^= (1 << src); | |
29000 | SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); | |
29001 | m68k_incpc(8); | |
29002 | fill_prefetch_0 (); | |
29003 | m68k_write_memory_8(dsta,dst); | |
29004 | }}}}return 24; | |
29005 | } | |
29006 | unsigned long CPUFUNC(op_87a_5)(uint32_t opcode) /* BCHG */ | |
29007 | { | |
29008 | uint32_t dstreg = 2; | |
29009 | OpcodeFamily = 22; CurrentInstrCycles = 20; | |
29010 | {{ int16_t src = get_iword_prefetch(2); | |
29011 | { uint32_t dsta = m68k_getpc () + 4; | |
29012 | dsta += (int32_t)(int16_t)get_iword_prefetch(4); | |
29013 | { int8_t dst = m68k_read_memory_8(dsta); | |
29014 | src &= 7; | |
29015 | dst ^= (1 << src); | |
29016 | SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); | |
29017 | m68k_incpc(6); | |
29018 | fill_prefetch_0 (); | |
29019 | m68k_write_memory_8(dsta,dst); | |
29020 | }}}}return 20; | |
29021 | } | |
29022 | unsigned long CPUFUNC(op_87b_5)(uint32_t opcode) /* BCHG */ | |
29023 | { | |
29024 | uint32_t dstreg = 3; | |
29025 | OpcodeFamily = 22; CurrentInstrCycles = 22; | |
29026 | {{ int16_t src = get_iword_prefetch(2); | |
29027 | { uint32_t tmppc = m68k_getpc() + 4; | |
29028 | uint32_t dsta = get_disp_ea_000(tmppc, get_iword_prefetch(4)); | |
29029 | BusCyclePenalty += 2; | |
29030 | { int8_t dst = m68k_read_memory_8(dsta); | |
29031 | src &= 7; | |
29032 | dst ^= (1 << src); | |
29033 | SET_ZFLG (((uint32_t)dst & (1 << src)) >> src); | |
29034 | m68k_incpc(6); | |
29035 | fill_prefetch_0 (); | |
29036 | m68k_write_memory_8(dsta,dst); | |
29037 | }}}}return 22; | |
29038 | } | |
29039 | unsigned long CPUFUNC(op_880_5)(uint32_t opcode) /* BCLR */ | |
29040 | { | |
29041 | uint32_t dstreg = opcode & 7; | |
29042 | OpcodeFamily = 23; CurrentInstrCycles = 14; | |
29043 | {{ int16_t src = get_iword_prefetch(2); | |
29044 | { int32_t dst = m68k_dreg(regs, dstreg); | |
29045 | src &= 31; | |
29046 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
29047 | dst &= ~(1 << src); | |
29048 | m68k_dreg(regs, dstreg) = (dst); | |
29049 | if ( src < 16 ) { m68k_incpc(4); return 12; } | |
29050 | }}}m68k_incpc(4); | |
29051 | fill_prefetch_0 (); | |
29052 | return 14; | |
29053 | } | |
29054 | unsigned long CPUFUNC(op_890_5)(uint32_t opcode) /* BCLR */ | |
29055 | { | |
29056 | uint32_t dstreg = opcode & 7; | |
29057 | OpcodeFamily = 23; CurrentInstrCycles = 16; | |
29058 | {{ int16_t src = get_iword_prefetch(2); | |
29059 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
29060 | { int8_t dst = m68k_read_memory_8(dsta); | |
29061 | src &= 7; | |
29062 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
29063 | dst &= ~(1 << src); | |
29064 | m68k_incpc(4); | |
29065 | fill_prefetch_0 (); | |
29066 | m68k_write_memory_8(dsta,dst); | |
29067 | }}}}return 16; | |
29068 | } | |
29069 | unsigned long CPUFUNC(op_898_5)(uint32_t opcode) /* BCLR */ | |
29070 | { | |
29071 | uint32_t dstreg = opcode & 7; | |
29072 | OpcodeFamily = 23; CurrentInstrCycles = 16; | |
29073 | {{ int16_t src = get_iword_prefetch(2); | |
29074 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
29075 | { int8_t dst = m68k_read_memory_8(dsta); | |
29076 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
29077 | src &= 7; | |
29078 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
29079 | dst &= ~(1 << src); | |
29080 | m68k_incpc(4); | |
29081 | fill_prefetch_0 (); | |
29082 | m68k_write_memory_8(dsta,dst); | |
29083 | }}}}return 16; | |
29084 | } | |
29085 | unsigned long CPUFUNC(op_8a0_5)(uint32_t opcode) /* BCLR */ | |
29086 | { | |
29087 | uint32_t dstreg = opcode & 7; | |
29088 | OpcodeFamily = 23; CurrentInstrCycles = 18; | |
29089 | {{ int16_t src = get_iword_prefetch(2); | |
29090 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
29091 | { int8_t dst = m68k_read_memory_8(dsta); | |
29092 | m68k_areg (regs, dstreg) = dsta; | |
29093 | src &= 7; | |
29094 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
29095 | dst &= ~(1 << src); | |
29096 | m68k_incpc(4); | |
29097 | fill_prefetch_0 (); | |
29098 | m68k_write_memory_8(dsta,dst); | |
29099 | }}}}return 18; | |
29100 | } | |
29101 | unsigned long CPUFUNC(op_8a8_5)(uint32_t opcode) /* BCLR */ | |
29102 | { | |
29103 | uint32_t dstreg = opcode & 7; | |
29104 | OpcodeFamily = 23; CurrentInstrCycles = 20; | |
29105 | {{ int16_t src = get_iword_prefetch(2); | |
29106 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); | |
29107 | { int8_t dst = m68k_read_memory_8(dsta); | |
29108 | src &= 7; | |
29109 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
29110 | dst &= ~(1 << src); | |
29111 | m68k_incpc(6); | |
29112 | fill_prefetch_0 (); | |
29113 | m68k_write_memory_8(dsta,dst); | |
29114 | }}}}return 20; | |
29115 | } | |
29116 | unsigned long CPUFUNC(op_8b0_5)(uint32_t opcode) /* BCLR */ | |
29117 | { | |
29118 | uint32_t dstreg = opcode & 7; | |
29119 | OpcodeFamily = 23; CurrentInstrCycles = 22; | |
29120 | {{ int16_t src = get_iword_prefetch(2); | |
29121 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); | |
29122 | BusCyclePenalty += 2; | |
29123 | { int8_t dst = m68k_read_memory_8(dsta); | |
29124 | src &= 7; | |
29125 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
29126 | dst &= ~(1 << src); | |
29127 | m68k_incpc(6); | |
29128 | fill_prefetch_0 (); | |
29129 | m68k_write_memory_8(dsta,dst); | |
29130 | }}}}return 22; | |
29131 | } | |
29132 | unsigned long CPUFUNC(op_8b8_5)(uint32_t opcode) /* BCLR */ | |
29133 | { | |
29134 | OpcodeFamily = 23; CurrentInstrCycles = 20; | |
29135 | {{ int16_t src = get_iword_prefetch(2); | |
29136 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); | |
29137 | { int8_t dst = m68k_read_memory_8(dsta); | |
29138 | src &= 7; | |
29139 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
29140 | dst &= ~(1 << src); | |
29141 | m68k_incpc(6); | |
29142 | fill_prefetch_0 (); | |
29143 | m68k_write_memory_8(dsta,dst); | |
29144 | }}}}return 20; | |
29145 | } | |
29146 | unsigned long CPUFUNC(op_8b9_5)(uint32_t opcode) /* BCLR */ | |
29147 | { | |
29148 | OpcodeFamily = 23; CurrentInstrCycles = 24; | |
29149 | {{ int16_t src = get_iword_prefetch(2); | |
29150 | { uint32_t dsta = get_ilong_prefetch(4); | |
29151 | { int8_t dst = m68k_read_memory_8(dsta); | |
29152 | src &= 7; | |
29153 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
29154 | dst &= ~(1 << src); | |
29155 | m68k_incpc(8); | |
29156 | fill_prefetch_0 (); | |
29157 | m68k_write_memory_8(dsta,dst); | |
29158 | }}}}return 24; | |
29159 | } | |
29160 | unsigned long CPUFUNC(op_8ba_5)(uint32_t opcode) /* BCLR */ | |
29161 | { | |
29162 | uint32_t dstreg = 2; | |
29163 | OpcodeFamily = 23; CurrentInstrCycles = 20; | |
29164 | {{ int16_t src = get_iword_prefetch(2); | |
29165 | { uint32_t dsta = m68k_getpc () + 4; | |
29166 | dsta += (int32_t)(int16_t)get_iword_prefetch(4); | |
29167 | { int8_t dst = m68k_read_memory_8(dsta); | |
29168 | src &= 7; | |
29169 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
29170 | dst &= ~(1 << src); | |
29171 | m68k_incpc(6); | |
29172 | fill_prefetch_0 (); | |
29173 | m68k_write_memory_8(dsta,dst); | |
29174 | }}}}return 20; | |
29175 | } | |
29176 | unsigned long CPUFUNC(op_8bb_5)(uint32_t opcode) /* BCLR */ | |
29177 | { | |
29178 | uint32_t dstreg = 3; | |
29179 | OpcodeFamily = 23; CurrentInstrCycles = 22; | |
29180 | {{ int16_t src = get_iword_prefetch(2); | |
29181 | { uint32_t tmppc = m68k_getpc() + 4; | |
29182 | uint32_t dsta = get_disp_ea_000(tmppc, get_iword_prefetch(4)); | |
29183 | BusCyclePenalty += 2; | |
29184 | { int8_t dst = m68k_read_memory_8(dsta); | |
29185 | src &= 7; | |
29186 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
29187 | dst &= ~(1 << src); | |
29188 | m68k_incpc(6); | |
29189 | fill_prefetch_0 (); | |
29190 | m68k_write_memory_8(dsta,dst); | |
29191 | }}}}return 22; | |
29192 | } | |
29193 | unsigned long CPUFUNC(op_8c0_5)(uint32_t opcode) /* BSET */ | |
29194 | { | |
29195 | uint32_t dstreg = opcode & 7; | |
29196 | OpcodeFamily = 24; CurrentInstrCycles = 12; | |
29197 | {{ int16_t src = get_iword_prefetch(2); | |
29198 | { int32_t dst = m68k_dreg(regs, dstreg); | |
29199 | src &= 31; | |
29200 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
29201 | dst |= (1 << src); | |
29202 | m68k_dreg(regs, dstreg) = (dst); | |
29203 | }}}m68k_incpc(4); | |
29204 | fill_prefetch_0 (); | |
29205 | return 12; | |
29206 | } | |
29207 | unsigned long CPUFUNC(op_8d0_5)(uint32_t opcode) /* BSET */ | |
29208 | { | |
29209 | uint32_t dstreg = opcode & 7; | |
29210 | OpcodeFamily = 24; CurrentInstrCycles = 16; | |
29211 | {{ int16_t src = get_iword_prefetch(2); | |
29212 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
29213 | { int8_t dst = m68k_read_memory_8(dsta); | |
29214 | src &= 7; | |
29215 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
29216 | dst |= (1 << src); | |
29217 | m68k_incpc(4); | |
29218 | fill_prefetch_0 (); | |
29219 | m68k_write_memory_8(dsta,dst); | |
29220 | }}}}return 16; | |
29221 | } | |
29222 | unsigned long CPUFUNC(op_8d8_5)(uint32_t opcode) /* BSET */ | |
29223 | { | |
29224 | uint32_t dstreg = opcode & 7; | |
29225 | OpcodeFamily = 24; CurrentInstrCycles = 16; | |
29226 | {{ int16_t src = get_iword_prefetch(2); | |
29227 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
29228 | { int8_t dst = m68k_read_memory_8(dsta); | |
29229 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
29230 | src &= 7; | |
29231 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
29232 | dst |= (1 << src); | |
29233 | m68k_incpc(4); | |
29234 | fill_prefetch_0 (); | |
29235 | m68k_write_memory_8(dsta,dst); | |
29236 | }}}}return 16; | |
29237 | } | |
29238 | unsigned long CPUFUNC(op_8e0_5)(uint32_t opcode) /* BSET */ | |
29239 | { | |
29240 | uint32_t dstreg = opcode & 7; | |
29241 | OpcodeFamily = 24; CurrentInstrCycles = 18; | |
29242 | {{ int16_t src = get_iword_prefetch(2); | |
29243 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
29244 | { int8_t dst = m68k_read_memory_8(dsta); | |
29245 | m68k_areg (regs, dstreg) = dsta; | |
29246 | src &= 7; | |
29247 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
29248 | dst |= (1 << src); | |
29249 | m68k_incpc(4); | |
29250 | fill_prefetch_0 (); | |
29251 | m68k_write_memory_8(dsta,dst); | |
29252 | }}}}return 18; | |
29253 | } | |
29254 | unsigned long CPUFUNC(op_8e8_5)(uint32_t opcode) /* BSET */ | |
29255 | { | |
29256 | uint32_t dstreg = opcode & 7; | |
29257 | OpcodeFamily = 24; CurrentInstrCycles = 20; | |
29258 | {{ int16_t src = get_iword_prefetch(2); | |
29259 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); | |
29260 | { int8_t dst = m68k_read_memory_8(dsta); | |
29261 | src &= 7; | |
29262 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
29263 | dst |= (1 << src); | |
29264 | m68k_incpc(6); | |
29265 | fill_prefetch_0 (); | |
29266 | m68k_write_memory_8(dsta,dst); | |
29267 | }}}}return 20; | |
29268 | } | |
29269 | unsigned long CPUFUNC(op_8f0_5)(uint32_t opcode) /* BSET */ | |
29270 | { | |
29271 | uint32_t dstreg = opcode & 7; | |
29272 | OpcodeFamily = 24; CurrentInstrCycles = 22; | |
29273 | {{ int16_t src = get_iword_prefetch(2); | |
29274 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); | |
29275 | BusCyclePenalty += 2; | |
29276 | { int8_t dst = m68k_read_memory_8(dsta); | |
29277 | src &= 7; | |
29278 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
29279 | dst |= (1 << src); | |
29280 | m68k_incpc(6); | |
29281 | fill_prefetch_0 (); | |
29282 | m68k_write_memory_8(dsta,dst); | |
29283 | }}}}return 22; | |
29284 | } | |
29285 | unsigned long CPUFUNC(op_8f8_5)(uint32_t opcode) /* BSET */ | |
29286 | { | |
29287 | OpcodeFamily = 24; CurrentInstrCycles = 20; | |
29288 | {{ int16_t src = get_iword_prefetch(2); | |
29289 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); | |
29290 | { int8_t dst = m68k_read_memory_8(dsta); | |
29291 | src &= 7; | |
29292 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
29293 | dst |= (1 << src); | |
29294 | m68k_incpc(6); | |
29295 | fill_prefetch_0 (); | |
29296 | m68k_write_memory_8(dsta,dst); | |
29297 | }}}}return 20; | |
29298 | } | |
29299 | unsigned long CPUFUNC(op_8f9_5)(uint32_t opcode) /* BSET */ | |
29300 | { | |
29301 | OpcodeFamily = 24; CurrentInstrCycles = 24; | |
29302 | {{ int16_t src = get_iword_prefetch(2); | |
29303 | { uint32_t dsta = get_ilong_prefetch(4); | |
29304 | { int8_t dst = m68k_read_memory_8(dsta); | |
29305 | src &= 7; | |
29306 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
29307 | dst |= (1 << src); | |
29308 | m68k_incpc(8); | |
29309 | fill_prefetch_0 (); | |
29310 | m68k_write_memory_8(dsta,dst); | |
29311 | }}}}return 24; | |
29312 | } | |
29313 | unsigned long CPUFUNC(op_8fa_5)(uint32_t opcode) /* BSET */ | |
29314 | { | |
29315 | uint32_t dstreg = 2; | |
29316 | OpcodeFamily = 24; CurrentInstrCycles = 20; | |
29317 | {{ int16_t src = get_iword_prefetch(2); | |
29318 | { uint32_t dsta = m68k_getpc () + 4; | |
29319 | dsta += (int32_t)(int16_t)get_iword_prefetch(4); | |
29320 | { int8_t dst = m68k_read_memory_8(dsta); | |
29321 | src &= 7; | |
29322 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
29323 | dst |= (1 << src); | |
29324 | m68k_incpc(6); | |
29325 | fill_prefetch_0 (); | |
29326 | m68k_write_memory_8(dsta,dst); | |
29327 | }}}}return 20; | |
29328 | } | |
29329 | unsigned long CPUFUNC(op_8fb_5)(uint32_t opcode) /* BSET */ | |
29330 | { | |
29331 | uint32_t dstreg = 3; | |
29332 | OpcodeFamily = 24; CurrentInstrCycles = 22; | |
29333 | {{ int16_t src = get_iword_prefetch(2); | |
29334 | { uint32_t tmppc = m68k_getpc() + 4; | |
29335 | uint32_t dsta = get_disp_ea_000(tmppc, get_iword_prefetch(4)); | |
29336 | BusCyclePenalty += 2; | |
29337 | { int8_t dst = m68k_read_memory_8(dsta); | |
29338 | src &= 7; | |
29339 | SET_ZFLG (1 ^ ((dst >> src) & 1)); | |
29340 | dst |= (1 << src); | |
29341 | m68k_incpc(6); | |
29342 | fill_prefetch_0 (); | |
29343 | m68k_write_memory_8(dsta,dst); | |
29344 | }}}}return 22; | |
29345 | } | |
29346 | unsigned long CPUFUNC(op_a00_5)(uint32_t opcode) /* EOR */ | |
29347 | { | |
29348 | uint32_t dstreg = opcode & 7; | |
29349 | OpcodeFamily = 3; CurrentInstrCycles = 8; | |
29350 | {{ int8_t src = get_ibyte_prefetch(2); | |
29351 | { int8_t dst = m68k_dreg(regs, dstreg); | |
29352 | src ^= dst; | |
29353 | CLEAR_CZNV; | |
29354 | SET_ZFLG (((int8_t)(src)) == 0); | |
29355 | SET_NFLG (((int8_t)(src)) < 0); | |
29356 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
29357 | }}}m68k_incpc(4); | |
29358 | fill_prefetch_0 (); | |
29359 | return 8; | |
29360 | } | |
29361 | unsigned long CPUFUNC(op_a10_5)(uint32_t opcode) /* EOR */ | |
29362 | { | |
29363 | uint32_t dstreg = opcode & 7; | |
29364 | OpcodeFamily = 3; CurrentInstrCycles = 16; | |
29365 | {{ int8_t src = get_ibyte_prefetch(2); | |
29366 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
29367 | { int8_t dst = m68k_read_memory_8(dsta); | |
29368 | src ^= dst; | |
29369 | CLEAR_CZNV; | |
29370 | SET_ZFLG (((int8_t)(src)) == 0); | |
29371 | SET_NFLG (((int8_t)(src)) < 0); | |
29372 | m68k_incpc(4); | |
29373 | fill_prefetch_0 (); | |
29374 | m68k_write_memory_8(dsta,src); | |
29375 | }}}}return 16; | |
29376 | } | |
29377 | unsigned long CPUFUNC(op_a18_5)(uint32_t opcode) /* EOR */ | |
29378 | { | |
29379 | uint32_t dstreg = opcode & 7; | |
29380 | OpcodeFamily = 3; CurrentInstrCycles = 16; | |
29381 | {{ int8_t src = get_ibyte_prefetch(2); | |
29382 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
29383 | { int8_t dst = m68k_read_memory_8(dsta); | |
29384 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
29385 | src ^= dst; | |
29386 | CLEAR_CZNV; | |
29387 | SET_ZFLG (((int8_t)(src)) == 0); | |
29388 | SET_NFLG (((int8_t)(src)) < 0); | |
29389 | m68k_incpc(4); | |
29390 | fill_prefetch_0 (); | |
29391 | m68k_write_memory_8(dsta,src); | |
29392 | }}}}return 16; | |
29393 | } | |
29394 | unsigned long CPUFUNC(op_a20_5)(uint32_t opcode) /* EOR */ | |
29395 | { | |
29396 | uint32_t dstreg = opcode & 7; | |
29397 | OpcodeFamily = 3; CurrentInstrCycles = 18; | |
29398 | {{ int8_t src = get_ibyte_prefetch(2); | |
29399 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
29400 | { int8_t dst = m68k_read_memory_8(dsta); | |
29401 | m68k_areg (regs, dstreg) = dsta; | |
29402 | src ^= dst; | |
29403 | CLEAR_CZNV; | |
29404 | SET_ZFLG (((int8_t)(src)) == 0); | |
29405 | SET_NFLG (((int8_t)(src)) < 0); | |
29406 | m68k_incpc(4); | |
29407 | fill_prefetch_0 (); | |
29408 | m68k_write_memory_8(dsta,src); | |
29409 | }}}}return 18; | |
29410 | } | |
29411 | unsigned long CPUFUNC(op_a28_5)(uint32_t opcode) /* EOR */ | |
29412 | { | |
29413 | uint32_t dstreg = opcode & 7; | |
29414 | OpcodeFamily = 3; CurrentInstrCycles = 20; | |
29415 | {{ int8_t src = get_ibyte_prefetch(2); | |
29416 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); | |
29417 | { int8_t dst = m68k_read_memory_8(dsta); | |
29418 | src ^= dst; | |
29419 | CLEAR_CZNV; | |
29420 | SET_ZFLG (((int8_t)(src)) == 0); | |
29421 | SET_NFLG (((int8_t)(src)) < 0); | |
29422 | m68k_incpc(6); | |
29423 | fill_prefetch_0 (); | |
29424 | m68k_write_memory_8(dsta,src); | |
29425 | }}}}return 20; | |
29426 | } | |
29427 | unsigned long CPUFUNC(op_a30_5)(uint32_t opcode) /* EOR */ | |
29428 | { | |
29429 | uint32_t dstreg = opcode & 7; | |
29430 | OpcodeFamily = 3; CurrentInstrCycles = 22; | |
29431 | {{ int8_t src = get_ibyte_prefetch(2); | |
29432 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); | |
29433 | BusCyclePenalty += 2; | |
29434 | { int8_t dst = m68k_read_memory_8(dsta); | |
29435 | src ^= dst; | |
29436 | CLEAR_CZNV; | |
29437 | SET_ZFLG (((int8_t)(src)) == 0); | |
29438 | SET_NFLG (((int8_t)(src)) < 0); | |
29439 | m68k_incpc(6); | |
29440 | fill_prefetch_0 (); | |
29441 | m68k_write_memory_8(dsta,src); | |
29442 | }}}}return 22; | |
29443 | } | |
29444 | unsigned long CPUFUNC(op_a38_5)(uint32_t opcode) /* EOR */ | |
29445 | { | |
29446 | OpcodeFamily = 3; CurrentInstrCycles = 20; | |
29447 | {{ int8_t src = get_ibyte_prefetch(2); | |
29448 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); | |
29449 | { int8_t dst = m68k_read_memory_8(dsta); | |
29450 | src ^= dst; | |
29451 | CLEAR_CZNV; | |
29452 | SET_ZFLG (((int8_t)(src)) == 0); | |
29453 | SET_NFLG (((int8_t)(src)) < 0); | |
29454 | m68k_incpc(6); | |
29455 | fill_prefetch_0 (); | |
29456 | m68k_write_memory_8(dsta,src); | |
29457 | }}}}return 20; | |
29458 | } | |
29459 | unsigned long CPUFUNC(op_a39_5)(uint32_t opcode) /* EOR */ | |
29460 | { | |
29461 | OpcodeFamily = 3; CurrentInstrCycles = 24; | |
29462 | {{ int8_t src = get_ibyte_prefetch(2); | |
29463 | { uint32_t dsta = get_ilong_prefetch(4); | |
29464 | { int8_t dst = m68k_read_memory_8(dsta); | |
29465 | src ^= dst; | |
29466 | CLEAR_CZNV; | |
29467 | SET_ZFLG (((int8_t)(src)) == 0); | |
29468 | SET_NFLG (((int8_t)(src)) < 0); | |
29469 | m68k_incpc(8); | |
29470 | fill_prefetch_0 (); | |
29471 | m68k_write_memory_8(dsta,src); | |
29472 | }}}}return 24; | |
29473 | } | |
29474 | unsigned long CPUFUNC(op_a3c_5)(uint32_t opcode) /* EORSR */ | |
29475 | { | |
29476 | OpcodeFamily = 6; CurrentInstrCycles = 20; | |
29477 | { MakeSR(); | |
29478 | { int16_t src = get_iword_prefetch(2); | |
29479 | src &= 0xFF; | |
29480 | regs.sr ^= src; | |
29481 | MakeFromSR(); | |
29482 | }}m68k_incpc(4); | |
29483 | fill_prefetch_0 (); | |
29484 | return 20; | |
29485 | } | |
29486 | unsigned long CPUFUNC(op_a40_5)(uint32_t opcode) /* EOR */ | |
29487 | { | |
29488 | uint32_t dstreg = opcode & 7; | |
29489 | OpcodeFamily = 3; CurrentInstrCycles = 8; | |
29490 | {{ int16_t src = get_iword_prefetch(2); | |
29491 | { int16_t dst = m68k_dreg(regs, dstreg); | |
29492 | src ^= dst; | |
29493 | CLEAR_CZNV; | |
29494 | SET_ZFLG (((int16_t)(src)) == 0); | |
29495 | SET_NFLG (((int16_t)(src)) < 0); | |
29496 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
29497 | }}}m68k_incpc(4); | |
29498 | fill_prefetch_0 (); | |
29499 | return 8; | |
29500 | } | |
29501 | unsigned long CPUFUNC(op_a50_5)(uint32_t opcode) /* EOR */ | |
29502 | { | |
29503 | uint32_t dstreg = opcode & 7; | |
29504 | OpcodeFamily = 3; CurrentInstrCycles = 16; | |
29505 | {{ int16_t src = get_iword_prefetch(2); | |
29506 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
29507 | if ((dsta & 1) != 0) { | |
29508 | last_fault_for_exception_3 = dsta; | |
29509 | last_op_for_exception_3 = opcode; | |
29510 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
29511 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
29512 | goto endlabel1777; | |
29513 | } | |
29514 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
29515 | src ^= dst; | |
29516 | CLEAR_CZNV; | |
29517 | SET_ZFLG (((int16_t)(src)) == 0); | |
29518 | SET_NFLG (((int16_t)(src)) < 0); | |
29519 | m68k_incpc(4); | |
29520 | fill_prefetch_0 (); | |
29521 | m68k_write_memory_16(dsta,src); | |
29522 | }}}}}endlabel1777: ; | |
29523 | return 16; | |
29524 | } | |
29525 | unsigned long CPUFUNC(op_a58_5)(uint32_t opcode) /* EOR */ | |
29526 | { | |
29527 | uint32_t dstreg = opcode & 7; | |
29528 | OpcodeFamily = 3; CurrentInstrCycles = 16; | |
29529 | {{ int16_t src = get_iword_prefetch(2); | |
29530 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
29531 | if ((dsta & 1) != 0) { | |
29532 | last_fault_for_exception_3 = dsta; | |
29533 | last_op_for_exception_3 = opcode; | |
29534 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
29535 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
29536 | goto endlabel1778; | |
29537 | } | |
29538 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
29539 | m68k_areg(regs, dstreg) += 2; | |
29540 | src ^= dst; | |
29541 | CLEAR_CZNV; | |
29542 | SET_ZFLG (((int16_t)(src)) == 0); | |
29543 | SET_NFLG (((int16_t)(src)) < 0); | |
29544 | m68k_incpc(4); | |
29545 | fill_prefetch_0 (); | |
29546 | m68k_write_memory_16(dsta,src); | |
29547 | }}}}}endlabel1778: ; | |
29548 | return 16; | |
29549 | } | |
29550 | unsigned long CPUFUNC(op_a60_5)(uint32_t opcode) /* EOR */ | |
29551 | { | |
29552 | uint32_t dstreg = opcode & 7; | |
29553 | OpcodeFamily = 3; CurrentInstrCycles = 18; | |
29554 | {{ int16_t src = get_iword_prefetch(2); | |
29555 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
29556 | if ((dsta & 1) != 0) { | |
29557 | last_fault_for_exception_3 = dsta; | |
29558 | last_op_for_exception_3 = opcode; | |
29559 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
29560 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
29561 | goto endlabel1779; | |
29562 | } | |
29563 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
29564 | m68k_areg (regs, dstreg) = dsta; | |
29565 | src ^= dst; | |
29566 | CLEAR_CZNV; | |
29567 | SET_ZFLG (((int16_t)(src)) == 0); | |
29568 | SET_NFLG (((int16_t)(src)) < 0); | |
29569 | m68k_incpc(4); | |
29570 | fill_prefetch_0 (); | |
29571 | m68k_write_memory_16(dsta,src); | |
29572 | }}}}}endlabel1779: ; | |
29573 | return 18; | |
29574 | } | |
29575 | unsigned long CPUFUNC(op_a68_5)(uint32_t opcode) /* EOR */ | |
29576 | { | |
29577 | uint32_t dstreg = opcode & 7; | |
29578 | OpcodeFamily = 3; CurrentInstrCycles = 20; | |
29579 | {{ int16_t src = get_iword_prefetch(2); | |
29580 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); | |
29581 | if ((dsta & 1) != 0) { | |
29582 | last_fault_for_exception_3 = dsta; | |
29583 | last_op_for_exception_3 = opcode; | |
29584 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
29585 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
29586 | goto endlabel1780; | |
29587 | } | |
29588 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
29589 | src ^= dst; | |
29590 | CLEAR_CZNV; | |
29591 | SET_ZFLG (((int16_t)(src)) == 0); | |
29592 | SET_NFLG (((int16_t)(src)) < 0); | |
29593 | m68k_incpc(6); | |
29594 | fill_prefetch_0 (); | |
29595 | m68k_write_memory_16(dsta,src); | |
29596 | }}}}}endlabel1780: ; | |
29597 | return 20; | |
29598 | } | |
29599 | unsigned long CPUFUNC(op_a70_5)(uint32_t opcode) /* EOR */ | |
29600 | { | |
29601 | uint32_t dstreg = opcode & 7; | |
29602 | OpcodeFamily = 3; CurrentInstrCycles = 22; | |
29603 | {{ int16_t src = get_iword_prefetch(2); | |
29604 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); | |
29605 | BusCyclePenalty += 2; | |
29606 | if ((dsta & 1) != 0) { | |
29607 | last_fault_for_exception_3 = dsta; | |
29608 | last_op_for_exception_3 = opcode; | |
29609 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
29610 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
29611 | goto endlabel1781; | |
29612 | } | |
29613 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
29614 | src ^= dst; | |
29615 | CLEAR_CZNV; | |
29616 | SET_ZFLG (((int16_t)(src)) == 0); | |
29617 | SET_NFLG (((int16_t)(src)) < 0); | |
29618 | m68k_incpc(6); | |
29619 | fill_prefetch_0 (); | |
29620 | m68k_write_memory_16(dsta,src); | |
29621 | }}}}}endlabel1781: ; | |
29622 | return 22; | |
29623 | } | |
29624 | unsigned long CPUFUNC(op_a78_5)(uint32_t opcode) /* EOR */ | |
29625 | { | |
29626 | OpcodeFamily = 3; CurrentInstrCycles = 20; | |
29627 | {{ int16_t src = get_iword_prefetch(2); | |
29628 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); | |
29629 | if ((dsta & 1) != 0) { | |
29630 | last_fault_for_exception_3 = dsta; | |
29631 | last_op_for_exception_3 = opcode; | |
29632 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
29633 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
29634 | goto endlabel1782; | |
29635 | } | |
29636 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
29637 | src ^= dst; | |
29638 | CLEAR_CZNV; | |
29639 | SET_ZFLG (((int16_t)(src)) == 0); | |
29640 | SET_NFLG (((int16_t)(src)) < 0); | |
29641 | m68k_incpc(6); | |
29642 | fill_prefetch_0 (); | |
29643 | m68k_write_memory_16(dsta,src); | |
29644 | }}}}}endlabel1782: ; | |
29645 | return 20; | |
29646 | } | |
29647 | unsigned long CPUFUNC(op_a79_5)(uint32_t opcode) /* EOR */ | |
29648 | { | |
29649 | OpcodeFamily = 3; CurrentInstrCycles = 24; | |
29650 | {{ int16_t src = get_iword_prefetch(2); | |
29651 | { uint32_t dsta = get_ilong_prefetch(4); | |
29652 | if ((dsta & 1) != 0) { | |
29653 | last_fault_for_exception_3 = dsta; | |
29654 | last_op_for_exception_3 = opcode; | |
29655 | last_addr_for_exception_3 = m68k_getpc() + 8; | |
29656 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
29657 | goto endlabel1783; | |
29658 | } | |
29659 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
29660 | src ^= dst; | |
29661 | CLEAR_CZNV; | |
29662 | SET_ZFLG (((int16_t)(src)) == 0); | |
29663 | SET_NFLG (((int16_t)(src)) < 0); | |
29664 | m68k_incpc(8); | |
29665 | fill_prefetch_0 (); | |
29666 | m68k_write_memory_16(dsta,src); | |
29667 | }}}}}endlabel1783: ; | |
29668 | return 24; | |
29669 | } | |
29670 | unsigned long CPUFUNC(op_a7c_5)(uint32_t opcode) /* EORSR */ | |
29671 | { | |
29672 | OpcodeFamily = 6; CurrentInstrCycles = 20; | |
29673 | {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel1784; } | |
29674 | { MakeSR(); | |
29675 | { int16_t src = get_iword_prefetch(2); | |
29676 | regs.sr ^= src; | |
29677 | MakeFromSR(); | |
29678 | }}}m68k_incpc(4); | |
29679 | fill_prefetch_0 (); | |
29680 | endlabel1784: ; | |
29681 | return 20; | |
29682 | } | |
29683 | #endif | |
29684 | ||
29685 | #ifdef PART_2 | |
29686 | unsigned long CPUFUNC(op_a80_5)(uint32_t opcode) /* EOR */ | |
29687 | { | |
29688 | uint32_t dstreg = opcode & 7; | |
29689 | OpcodeFamily = 3; CurrentInstrCycles = 16; | |
29690 | {{ int32_t src = get_ilong_prefetch(2); | |
29691 | { int32_t dst = m68k_dreg(regs, dstreg); | |
29692 | src ^= dst; | |
29693 | CLEAR_CZNV; | |
29694 | SET_ZFLG (((int32_t)(src)) == 0); | |
29695 | SET_NFLG (((int32_t)(src)) < 0); | |
29696 | m68k_dreg(regs, dstreg) = (src); | |
29697 | }}}m68k_incpc(6); | |
29698 | fill_prefetch_0 (); | |
29699 | return 16; | |
29700 | } | |
29701 | unsigned long CPUFUNC(op_a90_5)(uint32_t opcode) /* EOR */ | |
29702 | { | |
29703 | uint32_t dstreg = opcode & 7; | |
29704 | OpcodeFamily = 3; CurrentInstrCycles = 28; | |
29705 | {{ int32_t src = get_ilong_prefetch(2); | |
29706 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
29707 | if ((dsta & 1) != 0) { | |
29708 | last_fault_for_exception_3 = dsta; | |
29709 | last_op_for_exception_3 = opcode; | |
29710 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
29711 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
29712 | goto endlabel1786; | |
29713 | } | |
29714 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
29715 | src ^= dst; | |
29716 | CLEAR_CZNV; | |
29717 | SET_ZFLG (((int32_t)(src)) == 0); | |
29718 | SET_NFLG (((int32_t)(src)) < 0); | |
29719 | m68k_incpc(6); | |
29720 | fill_prefetch_0 (); | |
29721 | m68k_write_memory_32(dsta,src); | |
29722 | }}}}}endlabel1786: ; | |
29723 | return 28; | |
29724 | } | |
29725 | unsigned long CPUFUNC(op_a98_5)(uint32_t opcode) /* EOR */ | |
29726 | { | |
29727 | uint32_t dstreg = opcode & 7; | |
29728 | OpcodeFamily = 3; CurrentInstrCycles = 28; | |
29729 | {{ int32_t src = get_ilong_prefetch(2); | |
29730 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
29731 | if ((dsta & 1) != 0) { | |
29732 | last_fault_for_exception_3 = dsta; | |
29733 | last_op_for_exception_3 = opcode; | |
29734 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
29735 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
29736 | goto endlabel1787; | |
29737 | } | |
29738 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
29739 | m68k_areg(regs, dstreg) += 4; | |
29740 | src ^= dst; | |
29741 | CLEAR_CZNV; | |
29742 | SET_ZFLG (((int32_t)(src)) == 0); | |
29743 | SET_NFLG (((int32_t)(src)) < 0); | |
29744 | m68k_incpc(6); | |
29745 | fill_prefetch_0 (); | |
29746 | m68k_write_memory_32(dsta,src); | |
29747 | }}}}}endlabel1787: ; | |
29748 | return 28; | |
29749 | } | |
29750 | unsigned long CPUFUNC(op_aa0_5)(uint32_t opcode) /* EOR */ | |
29751 | { | |
29752 | uint32_t dstreg = opcode & 7; | |
29753 | OpcodeFamily = 3; CurrentInstrCycles = 30; | |
29754 | {{ int32_t src = get_ilong_prefetch(2); | |
29755 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
29756 | if ((dsta & 1) != 0) { | |
29757 | last_fault_for_exception_3 = dsta; | |
29758 | last_op_for_exception_3 = opcode; | |
29759 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
29760 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
29761 | goto endlabel1788; | |
29762 | } | |
29763 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
29764 | m68k_areg (regs, dstreg) = dsta; | |
29765 | src ^= dst; | |
29766 | CLEAR_CZNV; | |
29767 | SET_ZFLG (((int32_t)(src)) == 0); | |
29768 | SET_NFLG (((int32_t)(src)) < 0); | |
29769 | m68k_incpc(6); | |
29770 | fill_prefetch_0 (); | |
29771 | m68k_write_memory_32(dsta,src); | |
29772 | }}}}}endlabel1788: ; | |
29773 | return 30; | |
29774 | } | |
29775 | unsigned long CPUFUNC(op_aa8_5)(uint32_t opcode) /* EOR */ | |
29776 | { | |
29777 | uint32_t dstreg = opcode & 7; | |
29778 | OpcodeFamily = 3; CurrentInstrCycles = 32; | |
29779 | {{ int32_t src = get_ilong_prefetch(2); | |
29780 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(6); | |
29781 | if ((dsta & 1) != 0) { | |
29782 | last_fault_for_exception_3 = dsta; | |
29783 | last_op_for_exception_3 = opcode; | |
29784 | last_addr_for_exception_3 = m68k_getpc() + 8; | |
29785 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
29786 | goto endlabel1789; | |
29787 | } | |
29788 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
29789 | src ^= dst; | |
29790 | CLEAR_CZNV; | |
29791 | SET_ZFLG (((int32_t)(src)) == 0); | |
29792 | SET_NFLG (((int32_t)(src)) < 0); | |
29793 | m68k_incpc(8); | |
29794 | fill_prefetch_0 (); | |
29795 | m68k_write_memory_32(dsta,src); | |
29796 | }}}}}endlabel1789: ; | |
29797 | return 32; | |
29798 | } | |
29799 | unsigned long CPUFUNC(op_ab0_5)(uint32_t opcode) /* EOR */ | |
29800 | { | |
29801 | uint32_t dstreg = opcode & 7; | |
29802 | OpcodeFamily = 3; CurrentInstrCycles = 34; | |
29803 | {{ int32_t src = get_ilong_prefetch(2); | |
29804 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(6)); | |
29805 | BusCyclePenalty += 2; | |
29806 | if ((dsta & 1) != 0) { | |
29807 | last_fault_for_exception_3 = dsta; | |
29808 | last_op_for_exception_3 = opcode; | |
29809 | last_addr_for_exception_3 = m68k_getpc() + 8; | |
29810 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
29811 | goto endlabel1790; | |
29812 | } | |
29813 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
29814 | src ^= dst; | |
29815 | CLEAR_CZNV; | |
29816 | SET_ZFLG (((int32_t)(src)) == 0); | |
29817 | SET_NFLG (((int32_t)(src)) < 0); | |
29818 | m68k_incpc(8); | |
29819 | fill_prefetch_0 (); | |
29820 | m68k_write_memory_32(dsta,src); | |
29821 | }}}}}endlabel1790: ; | |
29822 | return 34; | |
29823 | } | |
29824 | unsigned long CPUFUNC(op_ab8_5)(uint32_t opcode) /* EOR */ | |
29825 | { | |
29826 | OpcodeFamily = 3; CurrentInstrCycles = 32; | |
29827 | {{ int32_t src = get_ilong_prefetch(2); | |
29828 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(6); | |
29829 | if ((dsta & 1) != 0) { | |
29830 | last_fault_for_exception_3 = dsta; | |
29831 | last_op_for_exception_3 = opcode; | |
29832 | last_addr_for_exception_3 = m68k_getpc() + 8; | |
29833 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
29834 | goto endlabel1791; | |
29835 | } | |
29836 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
29837 | src ^= dst; | |
29838 | CLEAR_CZNV; | |
29839 | SET_ZFLG (((int32_t)(src)) == 0); | |
29840 | SET_NFLG (((int32_t)(src)) < 0); | |
29841 | m68k_incpc(8); | |
29842 | fill_prefetch_0 (); | |
29843 | m68k_write_memory_32(dsta,src); | |
29844 | }}}}}endlabel1791: ; | |
29845 | return 32; | |
29846 | } | |
29847 | unsigned long CPUFUNC(op_ab9_5)(uint32_t opcode) /* EOR */ | |
29848 | { | |
29849 | OpcodeFamily = 3; CurrentInstrCycles = 36; | |
29850 | {{ int32_t src = get_ilong_prefetch(2); | |
29851 | { uint32_t dsta = get_ilong_prefetch(6); | |
29852 | if ((dsta & 1) != 0) { | |
29853 | last_fault_for_exception_3 = dsta; | |
29854 | last_op_for_exception_3 = opcode; | |
29855 | last_addr_for_exception_3 = m68k_getpc() + 10; | |
29856 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
29857 | goto endlabel1792; | |
29858 | } | |
29859 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
29860 | src ^= dst; | |
29861 | CLEAR_CZNV; | |
29862 | SET_ZFLG (((int32_t)(src)) == 0); | |
29863 | SET_NFLG (((int32_t)(src)) < 0); | |
29864 | m68k_incpc(10); | |
29865 | fill_prefetch_0 (); | |
29866 | m68k_write_memory_32(dsta,src); | |
29867 | }}}}}endlabel1792: ; | |
29868 | return 36; | |
29869 | } | |
29870 | unsigned long CPUFUNC(op_c00_5)(uint32_t opcode) /* CMP */ | |
29871 | { | |
29872 | uint32_t dstreg = opcode & 7; | |
29873 | OpcodeFamily = 25; CurrentInstrCycles = 8; | |
29874 | {{ int8_t src = get_ibyte_prefetch(2); | |
29875 | { int8_t dst = m68k_dreg(regs, dstreg); | |
29876 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
29877 | { int flgs = ((int8_t)(src)) < 0; | |
29878 | int flgo = ((int8_t)(dst)) < 0; | |
29879 | int flgn = ((int8_t)(newv)) < 0; | |
29880 | SET_ZFLG (((int8_t)(newv)) == 0); | |
29881 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
29882 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
29883 | SET_NFLG (flgn != 0); | |
29884 | }}}}}}m68k_incpc(4); | |
29885 | fill_prefetch_0 (); | |
29886 | return 8; | |
29887 | } | |
29888 | unsigned long CPUFUNC(op_c10_5)(uint32_t opcode) /* CMP */ | |
29889 | { | |
29890 | uint32_t dstreg = opcode & 7; | |
29891 | OpcodeFamily = 25; CurrentInstrCycles = 12; | |
29892 | {{ int8_t src = get_ibyte_prefetch(2); | |
29893 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
29894 | { int8_t dst = m68k_read_memory_8(dsta); | |
29895 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
29896 | { int flgs = ((int8_t)(src)) < 0; | |
29897 | int flgo = ((int8_t)(dst)) < 0; | |
29898 | int flgn = ((int8_t)(newv)) < 0; | |
29899 | SET_ZFLG (((int8_t)(newv)) == 0); | |
29900 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
29901 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
29902 | SET_NFLG (flgn != 0); | |
29903 | }}}}}}}m68k_incpc(4); | |
29904 | fill_prefetch_0 (); | |
29905 | return 12; | |
29906 | } | |
29907 | unsigned long CPUFUNC(op_c18_5)(uint32_t opcode) /* CMP */ | |
29908 | { | |
29909 | uint32_t dstreg = opcode & 7; | |
29910 | OpcodeFamily = 25; CurrentInstrCycles = 12; | |
29911 | {{ int8_t src = get_ibyte_prefetch(2); | |
29912 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
29913 | { int8_t dst = m68k_read_memory_8(dsta); | |
29914 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
29915 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
29916 | { int flgs = ((int8_t)(src)) < 0; | |
29917 | int flgo = ((int8_t)(dst)) < 0; | |
29918 | int flgn = ((int8_t)(newv)) < 0; | |
29919 | SET_ZFLG (((int8_t)(newv)) == 0); | |
29920 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
29921 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
29922 | SET_NFLG (flgn != 0); | |
29923 | }}}}}}}m68k_incpc(4); | |
29924 | fill_prefetch_0 (); | |
29925 | return 12; | |
29926 | } | |
29927 | unsigned long CPUFUNC(op_c20_5)(uint32_t opcode) /* CMP */ | |
29928 | { | |
29929 | uint32_t dstreg = opcode & 7; | |
29930 | OpcodeFamily = 25; CurrentInstrCycles = 14; | |
29931 | {{ int8_t src = get_ibyte_prefetch(2); | |
29932 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
29933 | { int8_t dst = m68k_read_memory_8(dsta); | |
29934 | m68k_areg (regs, dstreg) = dsta; | |
29935 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
29936 | { int flgs = ((int8_t)(src)) < 0; | |
29937 | int flgo = ((int8_t)(dst)) < 0; | |
29938 | int flgn = ((int8_t)(newv)) < 0; | |
29939 | SET_ZFLG (((int8_t)(newv)) == 0); | |
29940 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
29941 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
29942 | SET_NFLG (flgn != 0); | |
29943 | }}}}}}}m68k_incpc(4); | |
29944 | fill_prefetch_0 (); | |
29945 | return 14; | |
29946 | } | |
29947 | unsigned long CPUFUNC(op_c28_5)(uint32_t opcode) /* CMP */ | |
29948 | { | |
29949 | uint32_t dstreg = opcode & 7; | |
29950 | OpcodeFamily = 25; CurrentInstrCycles = 16; | |
29951 | {{ int8_t src = get_ibyte_prefetch(2); | |
29952 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); | |
29953 | { int8_t dst = m68k_read_memory_8(dsta); | |
29954 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
29955 | { int flgs = ((int8_t)(src)) < 0; | |
29956 | int flgo = ((int8_t)(dst)) < 0; | |
29957 | int flgn = ((int8_t)(newv)) < 0; | |
29958 | SET_ZFLG (((int8_t)(newv)) == 0); | |
29959 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
29960 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
29961 | SET_NFLG (flgn != 0); | |
29962 | }}}}}}}m68k_incpc(6); | |
29963 | fill_prefetch_0 (); | |
29964 | return 16; | |
29965 | } | |
29966 | unsigned long CPUFUNC(op_c30_5)(uint32_t opcode) /* CMP */ | |
29967 | { | |
29968 | uint32_t dstreg = opcode & 7; | |
29969 | OpcodeFamily = 25; CurrentInstrCycles = 18; | |
29970 | {{ int8_t src = get_ibyte_prefetch(2); | |
29971 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); | |
29972 | BusCyclePenalty += 2; | |
29973 | { int8_t dst = m68k_read_memory_8(dsta); | |
29974 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
29975 | { int flgs = ((int8_t)(src)) < 0; | |
29976 | int flgo = ((int8_t)(dst)) < 0; | |
29977 | int flgn = ((int8_t)(newv)) < 0; | |
29978 | SET_ZFLG (((int8_t)(newv)) == 0); | |
29979 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
29980 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
29981 | SET_NFLG (flgn != 0); | |
29982 | }}}}}}}m68k_incpc(6); | |
29983 | fill_prefetch_0 (); | |
29984 | return 18; | |
29985 | } | |
29986 | unsigned long CPUFUNC(op_c38_5)(uint32_t opcode) /* CMP */ | |
29987 | { | |
29988 | OpcodeFamily = 25; CurrentInstrCycles = 16; | |
29989 | {{ int8_t src = get_ibyte_prefetch(2); | |
29990 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); | |
29991 | { int8_t dst = m68k_read_memory_8(dsta); | |
29992 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
29993 | { int flgs = ((int8_t)(src)) < 0; | |
29994 | int flgo = ((int8_t)(dst)) < 0; | |
29995 | int flgn = ((int8_t)(newv)) < 0; | |
29996 | SET_ZFLG (((int8_t)(newv)) == 0); | |
29997 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
29998 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
29999 | SET_NFLG (flgn != 0); | |
30000 | }}}}}}}m68k_incpc(6); | |
30001 | fill_prefetch_0 (); | |
30002 | return 16; | |
30003 | } | |
30004 | unsigned long CPUFUNC(op_c39_5)(uint32_t opcode) /* CMP */ | |
30005 | { | |
30006 | OpcodeFamily = 25; CurrentInstrCycles = 20; | |
30007 | {{ int8_t src = get_ibyte_prefetch(2); | |
30008 | { uint32_t dsta = get_ilong_prefetch(4); | |
30009 | { int8_t dst = m68k_read_memory_8(dsta); | |
30010 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
30011 | { int flgs = ((int8_t)(src)) < 0; | |
30012 | int flgo = ((int8_t)(dst)) < 0; | |
30013 | int flgn = ((int8_t)(newv)) < 0; | |
30014 | SET_ZFLG (((int8_t)(newv)) == 0); | |
30015 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
30016 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
30017 | SET_NFLG (flgn != 0); | |
30018 | }}}}}}}m68k_incpc(8); | |
30019 | fill_prefetch_0 (); | |
30020 | return 20; | |
30021 | } | |
30022 | unsigned long CPUFUNC(op_c3a_5)(uint32_t opcode) /* CMP */ | |
30023 | { | |
30024 | uint32_t dstreg = 2; | |
30025 | OpcodeFamily = 25; CurrentInstrCycles = 16; | |
30026 | {{ int8_t src = get_ibyte_prefetch(2); | |
30027 | { uint32_t dsta = m68k_getpc () + 4; | |
30028 | dsta += (int32_t)(int16_t)get_iword_prefetch(4); | |
30029 | { int8_t dst = m68k_read_memory_8(dsta); | |
30030 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
30031 | { int flgs = ((int8_t)(src)) < 0; | |
30032 | int flgo = ((int8_t)(dst)) < 0; | |
30033 | int flgn = ((int8_t)(newv)) < 0; | |
30034 | SET_ZFLG (((int8_t)(newv)) == 0); | |
30035 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
30036 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
30037 | SET_NFLG (flgn != 0); | |
30038 | }}}}}}}m68k_incpc(6); | |
30039 | fill_prefetch_0 (); | |
30040 | return 16; | |
30041 | } | |
30042 | unsigned long CPUFUNC(op_c3b_5)(uint32_t opcode) /* CMP */ | |
30043 | { | |
30044 | uint32_t dstreg = 3; | |
30045 | OpcodeFamily = 25; CurrentInstrCycles = 18; | |
30046 | {{ int8_t src = get_ibyte_prefetch(2); | |
30047 | { uint32_t tmppc = m68k_getpc() + 4; | |
30048 | uint32_t dsta = get_disp_ea_000(tmppc, get_iword_prefetch(4)); | |
30049 | BusCyclePenalty += 2; | |
30050 | { int8_t dst = m68k_read_memory_8(dsta); | |
30051 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
30052 | { int flgs = ((int8_t)(src)) < 0; | |
30053 | int flgo = ((int8_t)(dst)) < 0; | |
30054 | int flgn = ((int8_t)(newv)) < 0; | |
30055 | SET_ZFLG (((int8_t)(newv)) == 0); | |
30056 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
30057 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
30058 | SET_NFLG (flgn != 0); | |
30059 | }}}}}}}m68k_incpc(6); | |
30060 | fill_prefetch_0 (); | |
30061 | return 18; | |
30062 | } | |
30063 | unsigned long CPUFUNC(op_c40_5)(uint32_t opcode) /* CMP */ | |
30064 | { | |
30065 | uint32_t dstreg = opcode & 7; | |
30066 | OpcodeFamily = 25; CurrentInstrCycles = 8; | |
30067 | {{ int16_t src = get_iword_prefetch(2); | |
30068 | { int16_t dst = m68k_dreg(regs, dstreg); | |
30069 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
30070 | { int flgs = ((int16_t)(src)) < 0; | |
30071 | int flgo = ((int16_t)(dst)) < 0; | |
30072 | int flgn = ((int16_t)(newv)) < 0; | |
30073 | SET_ZFLG (((int16_t)(newv)) == 0); | |
30074 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
30075 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
30076 | SET_NFLG (flgn != 0); | |
30077 | }}}}}}m68k_incpc(4); | |
30078 | fill_prefetch_0 (); | |
30079 | return 8; | |
30080 | } | |
30081 | unsigned long CPUFUNC(op_c50_5)(uint32_t opcode) /* CMP */ | |
30082 | { | |
30083 | uint32_t dstreg = opcode & 7; | |
30084 | OpcodeFamily = 25; CurrentInstrCycles = 12; | |
30085 | {{ int16_t src = get_iword_prefetch(2); | |
30086 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
30087 | if ((dsta & 1) != 0) { | |
30088 | last_fault_for_exception_3 = dsta; | |
30089 | last_op_for_exception_3 = opcode; | |
30090 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
30091 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
30092 | goto endlabel1804; | |
30093 | } | |
30094 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
30095 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
30096 | { int flgs = ((int16_t)(src)) < 0; | |
30097 | int flgo = ((int16_t)(dst)) < 0; | |
30098 | int flgn = ((int16_t)(newv)) < 0; | |
30099 | SET_ZFLG (((int16_t)(newv)) == 0); | |
30100 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
30101 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
30102 | SET_NFLG (flgn != 0); | |
30103 | }}}}}}}}m68k_incpc(4); | |
30104 | fill_prefetch_0 (); | |
30105 | endlabel1804: ; | |
30106 | return 12; | |
30107 | } | |
30108 | unsigned long CPUFUNC(op_c58_5)(uint32_t opcode) /* CMP */ | |
30109 | { | |
30110 | uint32_t dstreg = opcode & 7; | |
30111 | OpcodeFamily = 25; CurrentInstrCycles = 12; | |
30112 | {{ int16_t src = get_iword_prefetch(2); | |
30113 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
30114 | if ((dsta & 1) != 0) { | |
30115 | last_fault_for_exception_3 = dsta; | |
30116 | last_op_for_exception_3 = opcode; | |
30117 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
30118 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
30119 | goto endlabel1805; | |
30120 | } | |
30121 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
30122 | m68k_areg(regs, dstreg) += 2; | |
30123 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
30124 | { int flgs = ((int16_t)(src)) < 0; | |
30125 | int flgo = ((int16_t)(dst)) < 0; | |
30126 | int flgn = ((int16_t)(newv)) < 0; | |
30127 | SET_ZFLG (((int16_t)(newv)) == 0); | |
30128 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
30129 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
30130 | SET_NFLG (flgn != 0); | |
30131 | }}}}}}}}m68k_incpc(4); | |
30132 | fill_prefetch_0 (); | |
30133 | endlabel1805: ; | |
30134 | return 12; | |
30135 | } | |
30136 | unsigned long CPUFUNC(op_c60_5)(uint32_t opcode) /* CMP */ | |
30137 | { | |
30138 | uint32_t dstreg = opcode & 7; | |
30139 | OpcodeFamily = 25; CurrentInstrCycles = 14; | |
30140 | {{ int16_t src = get_iword_prefetch(2); | |
30141 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
30142 | if ((dsta & 1) != 0) { | |
30143 | last_fault_for_exception_3 = dsta; | |
30144 | last_op_for_exception_3 = opcode; | |
30145 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
30146 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
30147 | goto endlabel1806; | |
30148 | } | |
30149 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
30150 | m68k_areg (regs, dstreg) = dsta; | |
30151 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
30152 | { int flgs = ((int16_t)(src)) < 0; | |
30153 | int flgo = ((int16_t)(dst)) < 0; | |
30154 | int flgn = ((int16_t)(newv)) < 0; | |
30155 | SET_ZFLG (((int16_t)(newv)) == 0); | |
30156 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
30157 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
30158 | SET_NFLG (flgn != 0); | |
30159 | }}}}}}}}m68k_incpc(4); | |
30160 | fill_prefetch_0 (); | |
30161 | endlabel1806: ; | |
30162 | return 14; | |
30163 | } | |
30164 | unsigned long CPUFUNC(op_c68_5)(uint32_t opcode) /* CMP */ | |
30165 | { | |
30166 | uint32_t dstreg = opcode & 7; | |
30167 | OpcodeFamily = 25; CurrentInstrCycles = 16; | |
30168 | {{ int16_t src = get_iword_prefetch(2); | |
30169 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); | |
30170 | if ((dsta & 1) != 0) { | |
30171 | last_fault_for_exception_3 = dsta; | |
30172 | last_op_for_exception_3 = opcode; | |
30173 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
30174 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
30175 | goto endlabel1807; | |
30176 | } | |
30177 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
30178 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
30179 | { int flgs = ((int16_t)(src)) < 0; | |
30180 | int flgo = ((int16_t)(dst)) < 0; | |
30181 | int flgn = ((int16_t)(newv)) < 0; | |
30182 | SET_ZFLG (((int16_t)(newv)) == 0); | |
30183 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
30184 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
30185 | SET_NFLG (flgn != 0); | |
30186 | }}}}}}}}m68k_incpc(6); | |
30187 | fill_prefetch_0 (); | |
30188 | endlabel1807: ; | |
30189 | return 16; | |
30190 | } | |
30191 | unsigned long CPUFUNC(op_c70_5)(uint32_t opcode) /* CMP */ | |
30192 | { | |
30193 | uint32_t dstreg = opcode & 7; | |
30194 | OpcodeFamily = 25; CurrentInstrCycles = 18; | |
30195 | {{ int16_t src = get_iword_prefetch(2); | |
30196 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); | |
30197 | BusCyclePenalty += 2; | |
30198 | if ((dsta & 1) != 0) { | |
30199 | last_fault_for_exception_3 = dsta; | |
30200 | last_op_for_exception_3 = opcode; | |
30201 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
30202 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
30203 | goto endlabel1808; | |
30204 | } | |
30205 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
30206 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
30207 | { int flgs = ((int16_t)(src)) < 0; | |
30208 | int flgo = ((int16_t)(dst)) < 0; | |
30209 | int flgn = ((int16_t)(newv)) < 0; | |
30210 | SET_ZFLG (((int16_t)(newv)) == 0); | |
30211 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
30212 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
30213 | SET_NFLG (flgn != 0); | |
30214 | }}}}}}}}m68k_incpc(6); | |
30215 | fill_prefetch_0 (); | |
30216 | endlabel1808: ; | |
30217 | return 18; | |
30218 | } | |
30219 | unsigned long CPUFUNC(op_c78_5)(uint32_t opcode) /* CMP */ | |
30220 | { | |
30221 | OpcodeFamily = 25; CurrentInstrCycles = 16; | |
30222 | {{ int16_t src = get_iword_prefetch(2); | |
30223 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); | |
30224 | if ((dsta & 1) != 0) { | |
30225 | last_fault_for_exception_3 = dsta; | |
30226 | last_op_for_exception_3 = opcode; | |
30227 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
30228 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
30229 | goto endlabel1809; | |
30230 | } | |
30231 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
30232 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
30233 | { int flgs = ((int16_t)(src)) < 0; | |
30234 | int flgo = ((int16_t)(dst)) < 0; | |
30235 | int flgn = ((int16_t)(newv)) < 0; | |
30236 | SET_ZFLG (((int16_t)(newv)) == 0); | |
30237 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
30238 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
30239 | SET_NFLG (flgn != 0); | |
30240 | }}}}}}}}m68k_incpc(6); | |
30241 | fill_prefetch_0 (); | |
30242 | endlabel1809: ; | |
30243 | return 16; | |
30244 | } | |
30245 | unsigned long CPUFUNC(op_c79_5)(uint32_t opcode) /* CMP */ | |
30246 | { | |
30247 | OpcodeFamily = 25; CurrentInstrCycles = 20; | |
30248 | {{ int16_t src = get_iword_prefetch(2); | |
30249 | { uint32_t dsta = get_ilong_prefetch(4); | |
30250 | if ((dsta & 1) != 0) { | |
30251 | last_fault_for_exception_3 = dsta; | |
30252 | last_op_for_exception_3 = opcode; | |
30253 | last_addr_for_exception_3 = m68k_getpc() + 8; | |
30254 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
30255 | goto endlabel1810; | |
30256 | } | |
30257 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
30258 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
30259 | { int flgs = ((int16_t)(src)) < 0; | |
30260 | int flgo = ((int16_t)(dst)) < 0; | |
30261 | int flgn = ((int16_t)(newv)) < 0; | |
30262 | SET_ZFLG (((int16_t)(newv)) == 0); | |
30263 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
30264 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
30265 | SET_NFLG (flgn != 0); | |
30266 | }}}}}}}}m68k_incpc(8); | |
30267 | fill_prefetch_0 (); | |
30268 | endlabel1810: ; | |
30269 | return 20; | |
30270 | } | |
30271 | unsigned long CPUFUNC(op_c7a_5)(uint32_t opcode) /* CMP */ | |
30272 | { | |
30273 | uint32_t dstreg = 2; | |
30274 | OpcodeFamily = 25; CurrentInstrCycles = 16; | |
30275 | {{ int16_t src = get_iword_prefetch(2); | |
30276 | { uint32_t dsta = m68k_getpc () + 4; | |
30277 | dsta += (int32_t)(int16_t)get_iword_prefetch(4); | |
30278 | if ((dsta & 1) != 0) { | |
30279 | last_fault_for_exception_3 = dsta; | |
30280 | last_op_for_exception_3 = opcode; | |
30281 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
30282 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
30283 | goto endlabel1811; | |
30284 | } | |
30285 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
30286 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
30287 | { int flgs = ((int16_t)(src)) < 0; | |
30288 | int flgo = ((int16_t)(dst)) < 0; | |
30289 | int flgn = ((int16_t)(newv)) < 0; | |
30290 | SET_ZFLG (((int16_t)(newv)) == 0); | |
30291 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
30292 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
30293 | SET_NFLG (flgn != 0); | |
30294 | }}}}}}}}m68k_incpc(6); | |
30295 | fill_prefetch_0 (); | |
30296 | endlabel1811: ; | |
30297 | return 16; | |
30298 | } | |
30299 | unsigned long CPUFUNC(op_c7b_5)(uint32_t opcode) /* CMP */ | |
30300 | { | |
30301 | uint32_t dstreg = 3; | |
30302 | OpcodeFamily = 25; CurrentInstrCycles = 18; | |
30303 | {{ int16_t src = get_iword_prefetch(2); | |
30304 | { uint32_t tmppc = m68k_getpc() + 4; | |
30305 | uint32_t dsta = get_disp_ea_000(tmppc, get_iword_prefetch(4)); | |
30306 | BusCyclePenalty += 2; | |
30307 | if ((dsta & 1) != 0) { | |
30308 | last_fault_for_exception_3 = dsta; | |
30309 | last_op_for_exception_3 = opcode; | |
30310 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
30311 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
30312 | goto endlabel1812; | |
30313 | } | |
30314 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
30315 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
30316 | { int flgs = ((int16_t)(src)) < 0; | |
30317 | int flgo = ((int16_t)(dst)) < 0; | |
30318 | int flgn = ((int16_t)(newv)) < 0; | |
30319 | SET_ZFLG (((int16_t)(newv)) == 0); | |
30320 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
30321 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
30322 | SET_NFLG (flgn != 0); | |
30323 | }}}}}}}}m68k_incpc(6); | |
30324 | fill_prefetch_0 (); | |
30325 | endlabel1812: ; | |
30326 | return 18; | |
30327 | } | |
30328 | unsigned long CPUFUNC(op_c80_5)(uint32_t opcode) /* CMP */ | |
30329 | { | |
30330 | uint32_t dstreg = opcode & 7; | |
30331 | OpcodeFamily = 25; CurrentInstrCycles = 14; | |
30332 | {{ int32_t src = get_ilong_prefetch(2); | |
30333 | { int32_t dst = m68k_dreg(regs, dstreg); | |
30334 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
30335 | { int flgs = ((int32_t)(src)) < 0; | |
30336 | int flgo = ((int32_t)(dst)) < 0; | |
30337 | int flgn = ((int32_t)(newv)) < 0; | |
30338 | SET_ZFLG (((int32_t)(newv)) == 0); | |
30339 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
30340 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
30341 | SET_NFLG (flgn != 0); | |
30342 | }}}}}}m68k_incpc(6); | |
30343 | fill_prefetch_0 (); | |
30344 | return 14; | |
30345 | } | |
30346 | unsigned long CPUFUNC(op_c90_5)(uint32_t opcode) /* CMP */ | |
30347 | { | |
30348 | uint32_t dstreg = opcode & 7; | |
30349 | OpcodeFamily = 25; CurrentInstrCycles = 20; | |
30350 | {{ int32_t src = get_ilong_prefetch(2); | |
30351 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
30352 | if ((dsta & 1) != 0) { | |
30353 | last_fault_for_exception_3 = dsta; | |
30354 | last_op_for_exception_3 = opcode; | |
30355 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
30356 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
30357 | goto endlabel1814; | |
30358 | } | |
30359 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
30360 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
30361 | { int flgs = ((int32_t)(src)) < 0; | |
30362 | int flgo = ((int32_t)(dst)) < 0; | |
30363 | int flgn = ((int32_t)(newv)) < 0; | |
30364 | SET_ZFLG (((int32_t)(newv)) == 0); | |
30365 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
30366 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
30367 | SET_NFLG (flgn != 0); | |
30368 | }}}}}}}}m68k_incpc(6); | |
30369 | fill_prefetch_0 (); | |
30370 | endlabel1814: ; | |
30371 | return 20; | |
30372 | } | |
30373 | unsigned long CPUFUNC(op_c98_5)(uint32_t opcode) /* CMP */ | |
30374 | { | |
30375 | uint32_t dstreg = opcode & 7; | |
30376 | OpcodeFamily = 25; CurrentInstrCycles = 20; | |
30377 | {{ int32_t src = get_ilong_prefetch(2); | |
30378 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
30379 | if ((dsta & 1) != 0) { | |
30380 | last_fault_for_exception_3 = dsta; | |
30381 | last_op_for_exception_3 = opcode; | |
30382 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
30383 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
30384 | goto endlabel1815; | |
30385 | } | |
30386 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
30387 | m68k_areg(regs, dstreg) += 4; | |
30388 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
30389 | { int flgs = ((int32_t)(src)) < 0; | |
30390 | int flgo = ((int32_t)(dst)) < 0; | |
30391 | int flgn = ((int32_t)(newv)) < 0; | |
30392 | SET_ZFLG (((int32_t)(newv)) == 0); | |
30393 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
30394 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
30395 | SET_NFLG (flgn != 0); | |
30396 | }}}}}}}}m68k_incpc(6); | |
30397 | fill_prefetch_0 (); | |
30398 | endlabel1815: ; | |
30399 | return 20; | |
30400 | } | |
30401 | unsigned long CPUFUNC(op_ca0_5)(uint32_t opcode) /* CMP */ | |
30402 | { | |
30403 | uint32_t dstreg = opcode & 7; | |
30404 | OpcodeFamily = 25; CurrentInstrCycles = 22; | |
30405 | {{ int32_t src = get_ilong_prefetch(2); | |
30406 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
30407 | if ((dsta & 1) != 0) { | |
30408 | last_fault_for_exception_3 = dsta; | |
30409 | last_op_for_exception_3 = opcode; | |
30410 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
30411 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
30412 | goto endlabel1816; | |
30413 | } | |
30414 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
30415 | m68k_areg (regs, dstreg) = dsta; | |
30416 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
30417 | { int flgs = ((int32_t)(src)) < 0; | |
30418 | int flgo = ((int32_t)(dst)) < 0; | |
30419 | int flgn = ((int32_t)(newv)) < 0; | |
30420 | SET_ZFLG (((int32_t)(newv)) == 0); | |
30421 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
30422 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
30423 | SET_NFLG (flgn != 0); | |
30424 | }}}}}}}}m68k_incpc(6); | |
30425 | fill_prefetch_0 (); | |
30426 | endlabel1816: ; | |
30427 | return 22; | |
30428 | } | |
30429 | unsigned long CPUFUNC(op_ca8_5)(uint32_t opcode) /* CMP */ | |
30430 | { | |
30431 | uint32_t dstreg = opcode & 7; | |
30432 | OpcodeFamily = 25; CurrentInstrCycles = 24; | |
30433 | {{ int32_t src = get_ilong_prefetch(2); | |
30434 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(6); | |
30435 | if ((dsta & 1) != 0) { | |
30436 | last_fault_for_exception_3 = dsta; | |
30437 | last_op_for_exception_3 = opcode; | |
30438 | last_addr_for_exception_3 = m68k_getpc() + 8; | |
30439 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
30440 | goto endlabel1817; | |
30441 | } | |
30442 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
30443 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
30444 | { int flgs = ((int32_t)(src)) < 0; | |
30445 | int flgo = ((int32_t)(dst)) < 0; | |
30446 | int flgn = ((int32_t)(newv)) < 0; | |
30447 | SET_ZFLG (((int32_t)(newv)) == 0); | |
30448 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
30449 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
30450 | SET_NFLG (flgn != 0); | |
30451 | }}}}}}}}m68k_incpc(8); | |
30452 | fill_prefetch_0 (); | |
30453 | endlabel1817: ; | |
30454 | return 24; | |
30455 | } | |
30456 | unsigned long CPUFUNC(op_cb0_5)(uint32_t opcode) /* CMP */ | |
30457 | { | |
30458 | uint32_t dstreg = opcode & 7; | |
30459 | OpcodeFamily = 25; CurrentInstrCycles = 26; | |
30460 | {{ int32_t src = get_ilong_prefetch(2); | |
30461 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(6)); | |
30462 | BusCyclePenalty += 2; | |
30463 | if ((dsta & 1) != 0) { | |
30464 | last_fault_for_exception_3 = dsta; | |
30465 | last_op_for_exception_3 = opcode; | |
30466 | last_addr_for_exception_3 = m68k_getpc() + 8; | |
30467 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
30468 | goto endlabel1818; | |
30469 | } | |
30470 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
30471 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
30472 | { int flgs = ((int32_t)(src)) < 0; | |
30473 | int flgo = ((int32_t)(dst)) < 0; | |
30474 | int flgn = ((int32_t)(newv)) < 0; | |
30475 | SET_ZFLG (((int32_t)(newv)) == 0); | |
30476 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
30477 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
30478 | SET_NFLG (flgn != 0); | |
30479 | }}}}}}}}m68k_incpc(8); | |
30480 | fill_prefetch_0 (); | |
30481 | endlabel1818: ; | |
30482 | return 26; | |
30483 | } | |
30484 | unsigned long CPUFUNC(op_cb8_5)(uint32_t opcode) /* CMP */ | |
30485 | { | |
30486 | OpcodeFamily = 25; CurrentInstrCycles = 24; | |
30487 | {{ int32_t src = get_ilong_prefetch(2); | |
30488 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(6); | |
30489 | if ((dsta & 1) != 0) { | |
30490 | last_fault_for_exception_3 = dsta; | |
30491 | last_op_for_exception_3 = opcode; | |
30492 | last_addr_for_exception_3 = m68k_getpc() + 8; | |
30493 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
30494 | goto endlabel1819; | |
30495 | } | |
30496 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
30497 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
30498 | { int flgs = ((int32_t)(src)) < 0; | |
30499 | int flgo = ((int32_t)(dst)) < 0; | |
30500 | int flgn = ((int32_t)(newv)) < 0; | |
30501 | SET_ZFLG (((int32_t)(newv)) == 0); | |
30502 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
30503 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
30504 | SET_NFLG (flgn != 0); | |
30505 | }}}}}}}}m68k_incpc(8); | |
30506 | fill_prefetch_0 (); | |
30507 | endlabel1819: ; | |
30508 | return 24; | |
30509 | } | |
30510 | unsigned long CPUFUNC(op_cb9_5)(uint32_t opcode) /* CMP */ | |
30511 | { | |
30512 | OpcodeFamily = 25; CurrentInstrCycles = 28; | |
30513 | {{ int32_t src = get_ilong_prefetch(2); | |
30514 | { uint32_t dsta = get_ilong_prefetch(6); | |
30515 | if ((dsta & 1) != 0) { | |
30516 | last_fault_for_exception_3 = dsta; | |
30517 | last_op_for_exception_3 = opcode; | |
30518 | last_addr_for_exception_3 = m68k_getpc() + 10; | |
30519 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
30520 | goto endlabel1820; | |
30521 | } | |
30522 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
30523 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
30524 | { int flgs = ((int32_t)(src)) < 0; | |
30525 | int flgo = ((int32_t)(dst)) < 0; | |
30526 | int flgn = ((int32_t)(newv)) < 0; | |
30527 | SET_ZFLG (((int32_t)(newv)) == 0); | |
30528 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
30529 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
30530 | SET_NFLG (flgn != 0); | |
30531 | }}}}}}}}m68k_incpc(10); | |
30532 | fill_prefetch_0 (); | |
30533 | endlabel1820: ; | |
30534 | return 28; | |
30535 | } | |
30536 | unsigned long CPUFUNC(op_cba_5)(uint32_t opcode) /* CMP */ | |
30537 | { | |
30538 | uint32_t dstreg = 2; | |
30539 | OpcodeFamily = 25; CurrentInstrCycles = 24; | |
30540 | {{ int32_t src = get_ilong_prefetch(2); | |
30541 | { uint32_t dsta = m68k_getpc () + 6; | |
30542 | dsta += (int32_t)(int16_t)get_iword_prefetch(6); | |
30543 | if ((dsta & 1) != 0) { | |
30544 | last_fault_for_exception_3 = dsta; | |
30545 | last_op_for_exception_3 = opcode; | |
30546 | last_addr_for_exception_3 = m68k_getpc() + 8; | |
30547 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
30548 | goto endlabel1821; | |
30549 | } | |
30550 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
30551 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
30552 | { int flgs = ((int32_t)(src)) < 0; | |
30553 | int flgo = ((int32_t)(dst)) < 0; | |
30554 | int flgn = ((int32_t)(newv)) < 0; | |
30555 | SET_ZFLG (((int32_t)(newv)) == 0); | |
30556 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
30557 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
30558 | SET_NFLG (flgn != 0); | |
30559 | }}}}}}}}m68k_incpc(8); | |
30560 | fill_prefetch_0 (); | |
30561 | endlabel1821: ; | |
30562 | return 24; | |
30563 | } | |
30564 | unsigned long CPUFUNC(op_cbb_5)(uint32_t opcode) /* CMP */ | |
30565 | { | |
30566 | uint32_t dstreg = 3; | |
30567 | OpcodeFamily = 25; CurrentInstrCycles = 26; | |
30568 | {{ int32_t src = get_ilong_prefetch(2); | |
30569 | { uint32_t tmppc = m68k_getpc() + 6; | |
30570 | uint32_t dsta = get_disp_ea_000(tmppc, get_iword_prefetch(6)); | |
30571 | BusCyclePenalty += 2; | |
30572 | if ((dsta & 1) != 0) { | |
30573 | last_fault_for_exception_3 = dsta; | |
30574 | last_op_for_exception_3 = opcode; | |
30575 | last_addr_for_exception_3 = m68k_getpc() + 8; | |
30576 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
30577 | goto endlabel1822; | |
30578 | } | |
30579 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
30580 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
30581 | { int flgs = ((int32_t)(src)) < 0; | |
30582 | int flgo = ((int32_t)(dst)) < 0; | |
30583 | int flgn = ((int32_t)(newv)) < 0; | |
30584 | SET_ZFLG (((int32_t)(newv)) == 0); | |
30585 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
30586 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
30587 | SET_NFLG (flgn != 0); | |
30588 | }}}}}}}}m68k_incpc(8); | |
30589 | fill_prefetch_0 (); | |
30590 | endlabel1822: ; | |
30591 | return 26; | |
30592 | } | |
30593 | unsigned long CPUFUNC(op_1000_5)(uint32_t opcode) /* MOVE */ | |
30594 | { | |
30595 | uint32_t srcreg = (opcode & 7); | |
30596 | uint32_t dstreg = (opcode >> 9) & 7; | |
30597 | OpcodeFamily = 30; CurrentInstrCycles = 4; | |
30598 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
30599 | { CLEAR_CZNV; | |
30600 | SET_ZFLG (((int8_t)(src)) == 0); | |
30601 | SET_NFLG (((int8_t)(src)) < 0); | |
30602 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
30603 | }}}m68k_incpc(2); | |
30604 | fill_prefetch_2 (); | |
30605 | return 4; | |
30606 | } | |
30607 | unsigned long CPUFUNC(op_1008_5)(uint32_t opcode) /* MOVE */ | |
30608 | { | |
30609 | uint32_t srcreg = (opcode & 7); | |
30610 | uint32_t dstreg = (opcode >> 9) & 7; | |
30611 | OpcodeFamily = 30; CurrentInstrCycles = 4; | |
30612 | {{ int8_t src = m68k_areg(regs, srcreg); | |
30613 | { CLEAR_CZNV; | |
30614 | SET_ZFLG (((int8_t)(src)) == 0); | |
30615 | SET_NFLG (((int8_t)(src)) < 0); | |
30616 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
30617 | }}}m68k_incpc(2); | |
30618 | fill_prefetch_2 (); | |
30619 | return 4; | |
30620 | } | |
30621 | unsigned long CPUFUNC(op_1010_5)(uint32_t opcode) /* MOVE */ | |
30622 | { | |
30623 | uint32_t srcreg = (opcode & 7); | |
30624 | uint32_t dstreg = (opcode >> 9) & 7; | |
30625 | OpcodeFamily = 30; CurrentInstrCycles = 8; | |
30626 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
30627 | { int8_t src = m68k_read_memory_8(srca); | |
30628 | { CLEAR_CZNV; | |
30629 | SET_ZFLG (((int8_t)(src)) == 0); | |
30630 | SET_NFLG (((int8_t)(src)) < 0); | |
30631 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
30632 | }}}}m68k_incpc(2); | |
30633 | fill_prefetch_2 (); | |
30634 | return 8; | |
30635 | } | |
30636 | unsigned long CPUFUNC(op_1018_5)(uint32_t opcode) /* MOVE */ | |
30637 | { | |
30638 | uint32_t srcreg = (opcode & 7); | |
30639 | uint32_t dstreg = (opcode >> 9) & 7; | |
30640 | OpcodeFamily = 30; CurrentInstrCycles = 8; | |
30641 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
30642 | { int8_t src = m68k_read_memory_8(srca); | |
30643 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
30644 | { CLEAR_CZNV; | |
30645 | SET_ZFLG (((int8_t)(src)) == 0); | |
30646 | SET_NFLG (((int8_t)(src)) < 0); | |
30647 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
30648 | }}}}m68k_incpc(2); | |
30649 | fill_prefetch_2 (); | |
30650 | return 8; | |
30651 | } | |
30652 | unsigned long CPUFUNC(op_1020_5)(uint32_t opcode) /* MOVE */ | |
30653 | { | |
30654 | uint32_t srcreg = (opcode & 7); | |
30655 | uint32_t dstreg = (opcode >> 9) & 7; | |
30656 | OpcodeFamily = 30; CurrentInstrCycles = 10; | |
30657 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
30658 | { int8_t src = m68k_read_memory_8(srca); | |
30659 | m68k_areg (regs, srcreg) = srca; | |
30660 | { CLEAR_CZNV; | |
30661 | SET_ZFLG (((int8_t)(src)) == 0); | |
30662 | SET_NFLG (((int8_t)(src)) < 0); | |
30663 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
30664 | }}}}m68k_incpc(2); | |
30665 | fill_prefetch_2 (); | |
30666 | return 10; | |
30667 | } | |
30668 | unsigned long CPUFUNC(op_1028_5)(uint32_t opcode) /* MOVE */ | |
30669 | { | |
30670 | uint32_t srcreg = (opcode & 7); | |
30671 | uint32_t dstreg = (opcode >> 9) & 7; | |
30672 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
30673 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
30674 | { int8_t src = m68k_read_memory_8(srca); | |
30675 | { CLEAR_CZNV; | |
30676 | SET_ZFLG (((int8_t)(src)) == 0); | |
30677 | SET_NFLG (((int8_t)(src)) < 0); | |
30678 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
30679 | }}}}m68k_incpc(4); | |
30680 | fill_prefetch_0 (); | |
30681 | return 12; | |
30682 | } | |
30683 | unsigned long CPUFUNC(op_1030_5)(uint32_t opcode) /* MOVE */ | |
30684 | { | |
30685 | uint32_t srcreg = (opcode & 7); | |
30686 | uint32_t dstreg = (opcode >> 9) & 7; | |
30687 | OpcodeFamily = 30; CurrentInstrCycles = 14; | |
30688 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
30689 | BusCyclePenalty += 2; | |
30690 | { int8_t src = m68k_read_memory_8(srca); | |
30691 | { CLEAR_CZNV; | |
30692 | SET_ZFLG (((int8_t)(src)) == 0); | |
30693 | SET_NFLG (((int8_t)(src)) < 0); | |
30694 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
30695 | }}}}m68k_incpc(4); | |
30696 | fill_prefetch_0 (); | |
30697 | return 14; | |
30698 | } | |
30699 | unsigned long CPUFUNC(op_1038_5)(uint32_t opcode) /* MOVE */ | |
30700 | { | |
30701 | uint32_t dstreg = (opcode >> 9) & 7; | |
30702 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
30703 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
30704 | { int8_t src = m68k_read_memory_8(srca); | |
30705 | { CLEAR_CZNV; | |
30706 | SET_ZFLG (((int8_t)(src)) == 0); | |
30707 | SET_NFLG (((int8_t)(src)) < 0); | |
30708 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
30709 | }}}}m68k_incpc(4); | |
30710 | fill_prefetch_0 (); | |
30711 | return 12; | |
30712 | } | |
30713 | unsigned long CPUFUNC(op_1039_5)(uint32_t opcode) /* MOVE */ | |
30714 | { | |
30715 | uint32_t dstreg = (opcode >> 9) & 7; | |
30716 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
30717 | {{ uint32_t srca = get_ilong_prefetch(2); | |
30718 | { int8_t src = m68k_read_memory_8(srca); | |
30719 | { CLEAR_CZNV; | |
30720 | SET_ZFLG (((int8_t)(src)) == 0); | |
30721 | SET_NFLG (((int8_t)(src)) < 0); | |
30722 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
30723 | }}}}m68k_incpc(6); | |
30724 | fill_prefetch_0 (); | |
30725 | return 16; | |
30726 | } | |
30727 | unsigned long CPUFUNC(op_103a_5)(uint32_t opcode) /* MOVE */ | |
30728 | { | |
30729 | uint32_t dstreg = (opcode >> 9) & 7; | |
30730 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
30731 | {{ uint32_t srca = m68k_getpc () + 2; | |
30732 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
30733 | { int8_t src = m68k_read_memory_8(srca); | |
30734 | { CLEAR_CZNV; | |
30735 | SET_ZFLG (((int8_t)(src)) == 0); | |
30736 | SET_NFLG (((int8_t)(src)) < 0); | |
30737 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
30738 | }}}}m68k_incpc(4); | |
30739 | fill_prefetch_0 (); | |
30740 | return 12; | |
30741 | } | |
30742 | unsigned long CPUFUNC(op_103b_5)(uint32_t opcode) /* MOVE */ | |
30743 | { | |
30744 | uint32_t dstreg = (opcode >> 9) & 7; | |
30745 | OpcodeFamily = 30; CurrentInstrCycles = 14; | |
30746 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
30747 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
30748 | BusCyclePenalty += 2; | |
30749 | { int8_t src = m68k_read_memory_8(srca); | |
30750 | { CLEAR_CZNV; | |
30751 | SET_ZFLG (((int8_t)(src)) == 0); | |
30752 | SET_NFLG (((int8_t)(src)) < 0); | |
30753 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
30754 | }}}}m68k_incpc(4); | |
30755 | fill_prefetch_0 (); | |
30756 | return 14; | |
30757 | } | |
30758 | unsigned long CPUFUNC(op_103c_5)(uint32_t opcode) /* MOVE */ | |
30759 | { | |
30760 | uint32_t dstreg = (opcode >> 9) & 7; | |
30761 | OpcodeFamily = 30; CurrentInstrCycles = 8; | |
30762 | {{ int8_t src = get_ibyte_prefetch(2); | |
30763 | { CLEAR_CZNV; | |
30764 | SET_ZFLG (((int8_t)(src)) == 0); | |
30765 | SET_NFLG (((int8_t)(src)) < 0); | |
30766 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
30767 | }}}m68k_incpc(4); | |
30768 | fill_prefetch_0 (); | |
30769 | return 8; | |
30770 | } | |
30771 | unsigned long CPUFUNC(op_1080_5)(uint32_t opcode) /* MOVE */ | |
30772 | { | |
30773 | uint32_t srcreg = (opcode & 7); | |
30774 | uint32_t dstreg = (opcode >> 9) & 7; | |
30775 | OpcodeFamily = 30; CurrentInstrCycles = 8; | |
30776 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
30777 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
30778 | CLEAR_CZNV; | |
30779 | SET_ZFLG (((int8_t)(src)) == 0); | |
30780 | SET_NFLG (((int8_t)(src)) < 0); | |
30781 | m68k_incpc(2); | |
30782 | fill_prefetch_2 (); | |
30783 | m68k_write_memory_8(dsta,src); | |
30784 | }}}return 8; | |
30785 | } | |
30786 | unsigned long CPUFUNC(op_1088_5)(uint32_t opcode) /* MOVE */ | |
30787 | { | |
30788 | uint32_t srcreg = (opcode & 7); | |
30789 | uint32_t dstreg = (opcode >> 9) & 7; | |
30790 | OpcodeFamily = 30; CurrentInstrCycles = 8; | |
30791 | {{ int8_t src = m68k_areg(regs, srcreg); | |
30792 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
30793 | CLEAR_CZNV; | |
30794 | SET_ZFLG (((int8_t)(src)) == 0); | |
30795 | SET_NFLG (((int8_t)(src)) < 0); | |
30796 | m68k_incpc(2); | |
30797 | fill_prefetch_2 (); | |
30798 | m68k_write_memory_8(dsta,src); | |
30799 | }}}return 8; | |
30800 | } | |
30801 | unsigned long CPUFUNC(op_1090_5)(uint32_t opcode) /* MOVE */ | |
30802 | { | |
30803 | uint32_t srcreg = (opcode & 7); | |
30804 | uint32_t dstreg = (opcode >> 9) & 7; | |
30805 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
30806 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
30807 | { int8_t src = m68k_read_memory_8(srca); | |
30808 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
30809 | CLEAR_CZNV; | |
30810 | SET_ZFLG (((int8_t)(src)) == 0); | |
30811 | SET_NFLG (((int8_t)(src)) < 0); | |
30812 | m68k_incpc(2); | |
30813 | fill_prefetch_2 (); | |
30814 | m68k_write_memory_8(dsta,src); | |
30815 | }}}}return 12; | |
30816 | } | |
30817 | unsigned long CPUFUNC(op_1098_5)(uint32_t opcode) /* MOVE */ | |
30818 | { | |
30819 | uint32_t srcreg = (opcode & 7); | |
30820 | uint32_t dstreg = (opcode >> 9) & 7; | |
30821 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
30822 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
30823 | { int8_t src = m68k_read_memory_8(srca); | |
30824 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
30825 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
30826 | CLEAR_CZNV; | |
30827 | SET_ZFLG (((int8_t)(src)) == 0); | |
30828 | SET_NFLG (((int8_t)(src)) < 0); | |
30829 | m68k_incpc(2); | |
30830 | fill_prefetch_2 (); | |
30831 | m68k_write_memory_8(dsta,src); | |
30832 | }}}}return 12; | |
30833 | } | |
30834 | unsigned long CPUFUNC(op_10a0_5)(uint32_t opcode) /* MOVE */ | |
30835 | { | |
30836 | uint32_t srcreg = (opcode & 7); | |
30837 | uint32_t dstreg = (opcode >> 9) & 7; | |
30838 | OpcodeFamily = 30; CurrentInstrCycles = 14; | |
30839 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
30840 | { int8_t src = m68k_read_memory_8(srca); | |
30841 | m68k_areg (regs, srcreg) = srca; | |
30842 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
30843 | CLEAR_CZNV; | |
30844 | SET_ZFLG (((int8_t)(src)) == 0); | |
30845 | SET_NFLG (((int8_t)(src)) < 0); | |
30846 | m68k_incpc(2); | |
30847 | fill_prefetch_2 (); | |
30848 | m68k_write_memory_8(dsta,src); | |
30849 | }}}}return 14; | |
30850 | } | |
30851 | unsigned long CPUFUNC(op_10a8_5)(uint32_t opcode) /* MOVE */ | |
30852 | { | |
30853 | uint32_t srcreg = (opcode & 7); | |
30854 | uint32_t dstreg = (opcode >> 9) & 7; | |
30855 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
30856 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
30857 | { int8_t src = m68k_read_memory_8(srca); | |
30858 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
30859 | CLEAR_CZNV; | |
30860 | SET_ZFLG (((int8_t)(src)) == 0); | |
30861 | SET_NFLG (((int8_t)(src)) < 0); | |
30862 | m68k_incpc(4); | |
30863 | fill_prefetch_0 (); | |
30864 | m68k_write_memory_8(dsta,src); | |
30865 | }}}}return 16; | |
30866 | } | |
30867 | unsigned long CPUFUNC(op_10b0_5)(uint32_t opcode) /* MOVE */ | |
30868 | { | |
30869 | uint32_t srcreg = (opcode & 7); | |
30870 | uint32_t dstreg = (opcode >> 9) & 7; | |
30871 | OpcodeFamily = 30; CurrentInstrCycles = 18; | |
30872 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
30873 | BusCyclePenalty += 2; | |
30874 | { int8_t src = m68k_read_memory_8(srca); | |
30875 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
30876 | CLEAR_CZNV; | |
30877 | SET_ZFLG (((int8_t)(src)) == 0); | |
30878 | SET_NFLG (((int8_t)(src)) < 0); | |
30879 | m68k_incpc(4); | |
30880 | fill_prefetch_0 (); | |
30881 | m68k_write_memory_8(dsta,src); | |
30882 | }}}}return 18; | |
30883 | } | |
30884 | unsigned long CPUFUNC(op_10b8_5)(uint32_t opcode) /* MOVE */ | |
30885 | { | |
30886 | uint32_t dstreg = (opcode >> 9) & 7; | |
30887 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
30888 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
30889 | { int8_t src = m68k_read_memory_8(srca); | |
30890 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
30891 | CLEAR_CZNV; | |
30892 | SET_ZFLG (((int8_t)(src)) == 0); | |
30893 | SET_NFLG (((int8_t)(src)) < 0); | |
30894 | m68k_incpc(4); | |
30895 | fill_prefetch_0 (); | |
30896 | m68k_write_memory_8(dsta,src); | |
30897 | }}}}return 16; | |
30898 | } | |
30899 | unsigned long CPUFUNC(op_10b9_5)(uint32_t opcode) /* MOVE */ | |
30900 | { | |
30901 | uint32_t dstreg = (opcode >> 9) & 7; | |
30902 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
30903 | {{ uint32_t srca = get_ilong_prefetch(2); | |
30904 | { int8_t src = m68k_read_memory_8(srca); | |
30905 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
30906 | CLEAR_CZNV; | |
30907 | SET_ZFLG (((int8_t)(src)) == 0); | |
30908 | SET_NFLG (((int8_t)(src)) < 0); | |
30909 | m68k_incpc(6); | |
30910 | fill_prefetch_0 (); | |
30911 | m68k_write_memory_8(dsta,src); | |
30912 | }}}}return 20; | |
30913 | } | |
30914 | unsigned long CPUFUNC(op_10ba_5)(uint32_t opcode) /* MOVE */ | |
30915 | { | |
30916 | uint32_t dstreg = (opcode >> 9) & 7; | |
30917 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
30918 | {{ uint32_t srca = m68k_getpc () + 2; | |
30919 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
30920 | { int8_t src = m68k_read_memory_8(srca); | |
30921 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
30922 | CLEAR_CZNV; | |
30923 | SET_ZFLG (((int8_t)(src)) == 0); | |
30924 | SET_NFLG (((int8_t)(src)) < 0); | |
30925 | m68k_incpc(4); | |
30926 | fill_prefetch_0 (); | |
30927 | m68k_write_memory_8(dsta,src); | |
30928 | }}}}return 16; | |
30929 | } | |
30930 | unsigned long CPUFUNC(op_10bb_5)(uint32_t opcode) /* MOVE */ | |
30931 | { | |
30932 | uint32_t dstreg = (opcode >> 9) & 7; | |
30933 | OpcodeFamily = 30; CurrentInstrCycles = 18; | |
30934 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
30935 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
30936 | BusCyclePenalty += 2; | |
30937 | { int8_t src = m68k_read_memory_8(srca); | |
30938 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
30939 | CLEAR_CZNV; | |
30940 | SET_ZFLG (((int8_t)(src)) == 0); | |
30941 | SET_NFLG (((int8_t)(src)) < 0); | |
30942 | m68k_incpc(4); | |
30943 | fill_prefetch_0 (); | |
30944 | m68k_write_memory_8(dsta,src); | |
30945 | }}}}return 18; | |
30946 | } | |
30947 | unsigned long CPUFUNC(op_10bc_5)(uint32_t opcode) /* MOVE */ | |
30948 | { | |
30949 | uint32_t dstreg = (opcode >> 9) & 7; | |
30950 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
30951 | {{ int8_t src = get_ibyte_prefetch(2); | |
30952 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
30953 | CLEAR_CZNV; | |
30954 | SET_ZFLG (((int8_t)(src)) == 0); | |
30955 | SET_NFLG (((int8_t)(src)) < 0); | |
30956 | m68k_incpc(4); | |
30957 | fill_prefetch_0 (); | |
30958 | m68k_write_memory_8(dsta,src); | |
30959 | }}}return 12; | |
30960 | } | |
30961 | unsigned long CPUFUNC(op_10c0_5)(uint32_t opcode) /* MOVE */ | |
30962 | { | |
30963 | uint32_t srcreg = (opcode & 7); | |
30964 | uint32_t dstreg = (opcode >> 9) & 7; | |
30965 | OpcodeFamily = 30; CurrentInstrCycles = 8; | |
30966 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
30967 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
30968 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
30969 | CLEAR_CZNV; | |
30970 | SET_ZFLG (((int8_t)(src)) == 0); | |
30971 | SET_NFLG (((int8_t)(src)) < 0); | |
30972 | m68k_incpc(2); | |
30973 | fill_prefetch_2 (); | |
30974 | m68k_write_memory_8(dsta,src); | |
30975 | }}}return 8; | |
30976 | } | |
30977 | unsigned long CPUFUNC(op_10c8_5)(uint32_t opcode) /* MOVE */ | |
30978 | { | |
30979 | uint32_t srcreg = (opcode & 7); | |
30980 | uint32_t dstreg = (opcode >> 9) & 7; | |
30981 | OpcodeFamily = 30; CurrentInstrCycles = 8; | |
30982 | {{ int8_t src = m68k_areg(regs, srcreg); | |
30983 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
30984 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
30985 | CLEAR_CZNV; | |
30986 | SET_ZFLG (((int8_t)(src)) == 0); | |
30987 | SET_NFLG (((int8_t)(src)) < 0); | |
30988 | m68k_incpc(2); | |
30989 | fill_prefetch_2 (); | |
30990 | m68k_write_memory_8(dsta,src); | |
30991 | }}}return 8; | |
30992 | } | |
30993 | unsigned long CPUFUNC(op_10d0_5)(uint32_t opcode) /* MOVE */ | |
30994 | { | |
30995 | uint32_t srcreg = (opcode & 7); | |
30996 | uint32_t dstreg = (opcode >> 9) & 7; | |
30997 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
30998 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
30999 | { int8_t src = m68k_read_memory_8(srca); | |
31000 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
31001 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
31002 | CLEAR_CZNV; | |
31003 | SET_ZFLG (((int8_t)(src)) == 0); | |
31004 | SET_NFLG (((int8_t)(src)) < 0); | |
31005 | m68k_incpc(2); | |
31006 | fill_prefetch_2 (); | |
31007 | m68k_write_memory_8(dsta,src); | |
31008 | }}}}return 12; | |
31009 | } | |
31010 | unsigned long CPUFUNC(op_10d8_5)(uint32_t opcode) /* MOVE */ | |
31011 | { | |
31012 | uint32_t srcreg = (opcode & 7); | |
31013 | uint32_t dstreg = (opcode >> 9) & 7; | |
31014 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
31015 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
31016 | { int8_t src = m68k_read_memory_8(srca); | |
31017 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
31018 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
31019 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
31020 | CLEAR_CZNV; | |
31021 | SET_ZFLG (((int8_t)(src)) == 0); | |
31022 | SET_NFLG (((int8_t)(src)) < 0); | |
31023 | m68k_incpc(2); | |
31024 | fill_prefetch_2 (); | |
31025 | m68k_write_memory_8(dsta,src); | |
31026 | }}}}return 12; | |
31027 | } | |
31028 | unsigned long CPUFUNC(op_10e0_5)(uint32_t opcode) /* MOVE */ | |
31029 | { | |
31030 | uint32_t srcreg = (opcode & 7); | |
31031 | uint32_t dstreg = (opcode >> 9) & 7; | |
31032 | OpcodeFamily = 30; CurrentInstrCycles = 14; | |
31033 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
31034 | { int8_t src = m68k_read_memory_8(srca); | |
31035 | m68k_areg (regs, srcreg) = srca; | |
31036 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
31037 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
31038 | CLEAR_CZNV; | |
31039 | SET_ZFLG (((int8_t)(src)) == 0); | |
31040 | SET_NFLG (((int8_t)(src)) < 0); | |
31041 | m68k_incpc(2); | |
31042 | fill_prefetch_2 (); | |
31043 | m68k_write_memory_8(dsta,src); | |
31044 | }}}}return 14; | |
31045 | } | |
31046 | unsigned long CPUFUNC(op_10e8_5)(uint32_t opcode) /* MOVE */ | |
31047 | { | |
31048 | uint32_t srcreg = (opcode & 7); | |
31049 | uint32_t dstreg = (opcode >> 9) & 7; | |
31050 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
31051 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
31052 | { int8_t src = m68k_read_memory_8(srca); | |
31053 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
31054 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
31055 | CLEAR_CZNV; | |
31056 | SET_ZFLG (((int8_t)(src)) == 0); | |
31057 | SET_NFLG (((int8_t)(src)) < 0); | |
31058 | m68k_incpc(4); | |
31059 | fill_prefetch_0 (); | |
31060 | m68k_write_memory_8(dsta,src); | |
31061 | }}}}return 16; | |
31062 | } | |
31063 | unsigned long CPUFUNC(op_10f0_5)(uint32_t opcode) /* MOVE */ | |
31064 | { | |
31065 | uint32_t srcreg = (opcode & 7); | |
31066 | uint32_t dstreg = (opcode >> 9) & 7; | |
31067 | OpcodeFamily = 30; CurrentInstrCycles = 18; | |
31068 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
31069 | BusCyclePenalty += 2; | |
31070 | { int8_t src = m68k_read_memory_8(srca); | |
31071 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
31072 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
31073 | CLEAR_CZNV; | |
31074 | SET_ZFLG (((int8_t)(src)) == 0); | |
31075 | SET_NFLG (((int8_t)(src)) < 0); | |
31076 | m68k_incpc(4); | |
31077 | fill_prefetch_0 (); | |
31078 | m68k_write_memory_8(dsta,src); | |
31079 | }}}}return 18; | |
31080 | } | |
31081 | unsigned long CPUFUNC(op_10f8_5)(uint32_t opcode) /* MOVE */ | |
31082 | { | |
31083 | uint32_t dstreg = (opcode >> 9) & 7; | |
31084 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
31085 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
31086 | { int8_t src = m68k_read_memory_8(srca); | |
31087 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
31088 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
31089 | CLEAR_CZNV; | |
31090 | SET_ZFLG (((int8_t)(src)) == 0); | |
31091 | SET_NFLG (((int8_t)(src)) < 0); | |
31092 | m68k_incpc(4); | |
31093 | fill_prefetch_0 (); | |
31094 | m68k_write_memory_8(dsta,src); | |
31095 | }}}}return 16; | |
31096 | } | |
31097 | unsigned long CPUFUNC(op_10f9_5)(uint32_t opcode) /* MOVE */ | |
31098 | { | |
31099 | uint32_t dstreg = (opcode >> 9) & 7; | |
31100 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
31101 | {{ uint32_t srca = get_ilong_prefetch(2); | |
31102 | { int8_t src = m68k_read_memory_8(srca); | |
31103 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
31104 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
31105 | CLEAR_CZNV; | |
31106 | SET_ZFLG (((int8_t)(src)) == 0); | |
31107 | SET_NFLG (((int8_t)(src)) < 0); | |
31108 | m68k_incpc(6); | |
31109 | fill_prefetch_0 (); | |
31110 | m68k_write_memory_8(dsta,src); | |
31111 | }}}}return 20; | |
31112 | } | |
31113 | unsigned long CPUFUNC(op_10fa_5)(uint32_t opcode) /* MOVE */ | |
31114 | { | |
31115 | uint32_t dstreg = (opcode >> 9) & 7; | |
31116 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
31117 | {{ uint32_t srca = m68k_getpc () + 2; | |
31118 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
31119 | { int8_t src = m68k_read_memory_8(srca); | |
31120 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
31121 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
31122 | CLEAR_CZNV; | |
31123 | SET_ZFLG (((int8_t)(src)) == 0); | |
31124 | SET_NFLG (((int8_t)(src)) < 0); | |
31125 | m68k_incpc(4); | |
31126 | fill_prefetch_0 (); | |
31127 | m68k_write_memory_8(dsta,src); | |
31128 | }}}}return 16; | |
31129 | } | |
31130 | unsigned long CPUFUNC(op_10fb_5)(uint32_t opcode) /* MOVE */ | |
31131 | { | |
31132 | uint32_t dstreg = (opcode >> 9) & 7; | |
31133 | OpcodeFamily = 30; CurrentInstrCycles = 18; | |
31134 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
31135 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
31136 | BusCyclePenalty += 2; | |
31137 | { int8_t src = m68k_read_memory_8(srca); | |
31138 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
31139 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
31140 | CLEAR_CZNV; | |
31141 | SET_ZFLG (((int8_t)(src)) == 0); | |
31142 | SET_NFLG (((int8_t)(src)) < 0); | |
31143 | m68k_incpc(4); | |
31144 | fill_prefetch_0 (); | |
31145 | m68k_write_memory_8(dsta,src); | |
31146 | }}}}return 18; | |
31147 | } | |
31148 | unsigned long CPUFUNC(op_10fc_5)(uint32_t opcode) /* MOVE */ | |
31149 | { | |
31150 | uint32_t dstreg = (opcode >> 9) & 7; | |
31151 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
31152 | {{ int8_t src = get_ibyte_prefetch(2); | |
31153 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
31154 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
31155 | CLEAR_CZNV; | |
31156 | SET_ZFLG (((int8_t)(src)) == 0); | |
31157 | SET_NFLG (((int8_t)(src)) < 0); | |
31158 | m68k_incpc(4); | |
31159 | fill_prefetch_0 (); | |
31160 | m68k_write_memory_8(dsta,src); | |
31161 | }}}return 12; | |
31162 | } | |
31163 | unsigned long CPUFUNC(op_1100_5)(uint32_t opcode) /* MOVE */ | |
31164 | { | |
31165 | uint32_t srcreg = (opcode & 7); | |
31166 | uint32_t dstreg = (opcode >> 9) & 7; | |
31167 | OpcodeFamily = 30; CurrentInstrCycles = 8; | |
31168 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
31169 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
31170 | m68k_areg (regs, dstreg) = dsta; | |
31171 | CLEAR_CZNV; | |
31172 | SET_ZFLG (((int8_t)(src)) == 0); | |
31173 | SET_NFLG (((int8_t)(src)) < 0); | |
31174 | m68k_incpc(2); | |
31175 | fill_prefetch_2 (); | |
31176 | m68k_write_memory_8(dsta,src); | |
31177 | }}}return 8; | |
31178 | } | |
31179 | unsigned long CPUFUNC(op_1108_5)(uint32_t opcode) /* MOVE */ | |
31180 | { | |
31181 | uint32_t srcreg = (opcode & 7); | |
31182 | uint32_t dstreg = (opcode >> 9) & 7; | |
31183 | OpcodeFamily = 30; CurrentInstrCycles = 8; | |
31184 | {{ int8_t src = m68k_areg(regs, srcreg); | |
31185 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
31186 | m68k_areg (regs, dstreg) = dsta; | |
31187 | CLEAR_CZNV; | |
31188 | SET_ZFLG (((int8_t)(src)) == 0); | |
31189 | SET_NFLG (((int8_t)(src)) < 0); | |
31190 | m68k_incpc(2); | |
31191 | fill_prefetch_2 (); | |
31192 | m68k_write_memory_8(dsta,src); | |
31193 | }}}return 8; | |
31194 | } | |
31195 | unsigned long CPUFUNC(op_1110_5)(uint32_t opcode) /* MOVE */ | |
31196 | { | |
31197 | uint32_t srcreg = (opcode & 7); | |
31198 | uint32_t dstreg = (opcode >> 9) & 7; | |
31199 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
31200 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
31201 | { int8_t src = m68k_read_memory_8(srca); | |
31202 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
31203 | m68k_areg (regs, dstreg) = dsta; | |
31204 | CLEAR_CZNV; | |
31205 | SET_ZFLG (((int8_t)(src)) == 0); | |
31206 | SET_NFLG (((int8_t)(src)) < 0); | |
31207 | m68k_incpc(2); | |
31208 | fill_prefetch_2 (); | |
31209 | m68k_write_memory_8(dsta,src); | |
31210 | }}}}return 12; | |
31211 | } | |
31212 | unsigned long CPUFUNC(op_1118_5)(uint32_t opcode) /* MOVE */ | |
31213 | { | |
31214 | uint32_t srcreg = (opcode & 7); | |
31215 | uint32_t dstreg = (opcode >> 9) & 7; | |
31216 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
31217 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
31218 | { int8_t src = m68k_read_memory_8(srca); | |
31219 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
31220 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
31221 | m68k_areg (regs, dstreg) = dsta; | |
31222 | CLEAR_CZNV; | |
31223 | SET_ZFLG (((int8_t)(src)) == 0); | |
31224 | SET_NFLG (((int8_t)(src)) < 0); | |
31225 | m68k_incpc(2); | |
31226 | fill_prefetch_2 (); | |
31227 | m68k_write_memory_8(dsta,src); | |
31228 | }}}}return 12; | |
31229 | } | |
31230 | unsigned long CPUFUNC(op_1120_5)(uint32_t opcode) /* MOVE */ | |
31231 | { | |
31232 | uint32_t srcreg = (opcode & 7); | |
31233 | uint32_t dstreg = (opcode >> 9) & 7; | |
31234 | OpcodeFamily = 30; CurrentInstrCycles = 14; | |
31235 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
31236 | { int8_t src = m68k_read_memory_8(srca); | |
31237 | m68k_areg (regs, srcreg) = srca; | |
31238 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
31239 | m68k_areg (regs, dstreg) = dsta; | |
31240 | CLEAR_CZNV; | |
31241 | SET_ZFLG (((int8_t)(src)) == 0); | |
31242 | SET_NFLG (((int8_t)(src)) < 0); | |
31243 | m68k_incpc(2); | |
31244 | fill_prefetch_2 (); | |
31245 | m68k_write_memory_8(dsta,src); | |
31246 | }}}}return 14; | |
31247 | } | |
31248 | unsigned long CPUFUNC(op_1128_5)(uint32_t opcode) /* MOVE */ | |
31249 | { | |
31250 | uint32_t srcreg = (opcode & 7); | |
31251 | uint32_t dstreg = (opcode >> 9) & 7; | |
31252 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
31253 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
31254 | { int8_t src = m68k_read_memory_8(srca); | |
31255 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
31256 | m68k_areg (regs, dstreg) = dsta; | |
31257 | CLEAR_CZNV; | |
31258 | SET_ZFLG (((int8_t)(src)) == 0); | |
31259 | SET_NFLG (((int8_t)(src)) < 0); | |
31260 | m68k_incpc(4); | |
31261 | fill_prefetch_0 (); | |
31262 | m68k_write_memory_8(dsta,src); | |
31263 | }}}}return 16; | |
31264 | } | |
31265 | unsigned long CPUFUNC(op_1130_5)(uint32_t opcode) /* MOVE */ | |
31266 | { | |
31267 | uint32_t srcreg = (opcode & 7); | |
31268 | uint32_t dstreg = (opcode >> 9) & 7; | |
31269 | OpcodeFamily = 30; CurrentInstrCycles = 18; | |
31270 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
31271 | BusCyclePenalty += 2; | |
31272 | { int8_t src = m68k_read_memory_8(srca); | |
31273 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
31274 | m68k_areg (regs, dstreg) = dsta; | |
31275 | CLEAR_CZNV; | |
31276 | SET_ZFLG (((int8_t)(src)) == 0); | |
31277 | SET_NFLG (((int8_t)(src)) < 0); | |
31278 | m68k_incpc(4); | |
31279 | fill_prefetch_0 (); | |
31280 | m68k_write_memory_8(dsta,src); | |
31281 | }}}}return 18; | |
31282 | } | |
31283 | unsigned long CPUFUNC(op_1138_5)(uint32_t opcode) /* MOVE */ | |
31284 | { | |
31285 | uint32_t dstreg = (opcode >> 9) & 7; | |
31286 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
31287 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
31288 | { int8_t src = m68k_read_memory_8(srca); | |
31289 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
31290 | m68k_areg (regs, dstreg) = dsta; | |
31291 | CLEAR_CZNV; | |
31292 | SET_ZFLG (((int8_t)(src)) == 0); | |
31293 | SET_NFLG (((int8_t)(src)) < 0); | |
31294 | m68k_incpc(4); | |
31295 | fill_prefetch_0 (); | |
31296 | m68k_write_memory_8(dsta,src); | |
31297 | }}}}return 16; | |
31298 | } | |
31299 | unsigned long CPUFUNC(op_1139_5)(uint32_t opcode) /* MOVE */ | |
31300 | { | |
31301 | uint32_t dstreg = (opcode >> 9) & 7; | |
31302 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
31303 | {{ uint32_t srca = get_ilong_prefetch(2); | |
31304 | { int8_t src = m68k_read_memory_8(srca); | |
31305 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
31306 | m68k_areg (regs, dstreg) = dsta; | |
31307 | CLEAR_CZNV; | |
31308 | SET_ZFLG (((int8_t)(src)) == 0); | |
31309 | SET_NFLG (((int8_t)(src)) < 0); | |
31310 | m68k_incpc(6); | |
31311 | fill_prefetch_0 (); | |
31312 | m68k_write_memory_8(dsta,src); | |
31313 | }}}}return 20; | |
31314 | } | |
31315 | unsigned long CPUFUNC(op_113a_5)(uint32_t opcode) /* MOVE */ | |
31316 | { | |
31317 | uint32_t dstreg = (opcode >> 9) & 7; | |
31318 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
31319 | {{ uint32_t srca = m68k_getpc () + 2; | |
31320 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
31321 | { int8_t src = m68k_read_memory_8(srca); | |
31322 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
31323 | m68k_areg (regs, dstreg) = dsta; | |
31324 | CLEAR_CZNV; | |
31325 | SET_ZFLG (((int8_t)(src)) == 0); | |
31326 | SET_NFLG (((int8_t)(src)) < 0); | |
31327 | m68k_incpc(4); | |
31328 | fill_prefetch_0 (); | |
31329 | m68k_write_memory_8(dsta,src); | |
31330 | }}}}return 16; | |
31331 | } | |
31332 | unsigned long CPUFUNC(op_113b_5)(uint32_t opcode) /* MOVE */ | |
31333 | { | |
31334 | uint32_t dstreg = (opcode >> 9) & 7; | |
31335 | OpcodeFamily = 30; CurrentInstrCycles = 18; | |
31336 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
31337 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
31338 | BusCyclePenalty += 2; | |
31339 | { int8_t src = m68k_read_memory_8(srca); | |
31340 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
31341 | m68k_areg (regs, dstreg) = dsta; | |
31342 | CLEAR_CZNV; | |
31343 | SET_ZFLG (((int8_t)(src)) == 0); | |
31344 | SET_NFLG (((int8_t)(src)) < 0); | |
31345 | m68k_incpc(4); | |
31346 | fill_prefetch_0 (); | |
31347 | m68k_write_memory_8(dsta,src); | |
31348 | }}}}return 18; | |
31349 | } | |
31350 | unsigned long CPUFUNC(op_113c_5)(uint32_t opcode) /* MOVE */ | |
31351 | { | |
31352 | uint32_t dstreg = (opcode >> 9) & 7; | |
31353 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
31354 | {{ int8_t src = get_ibyte_prefetch(2); | |
31355 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
31356 | m68k_areg (regs, dstreg) = dsta; | |
31357 | CLEAR_CZNV; | |
31358 | SET_ZFLG (((int8_t)(src)) == 0); | |
31359 | SET_NFLG (((int8_t)(src)) < 0); | |
31360 | m68k_incpc(4); | |
31361 | fill_prefetch_0 (); | |
31362 | m68k_write_memory_8(dsta,src); | |
31363 | }}}return 12; | |
31364 | } | |
31365 | unsigned long CPUFUNC(op_1140_5)(uint32_t opcode) /* MOVE */ | |
31366 | { | |
31367 | uint32_t srcreg = (opcode & 7); | |
31368 | uint32_t dstreg = (opcode >> 9) & 7; | |
31369 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
31370 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
31371 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
31372 | CLEAR_CZNV; | |
31373 | SET_ZFLG (((int8_t)(src)) == 0); | |
31374 | SET_NFLG (((int8_t)(src)) < 0); | |
31375 | m68k_incpc(4); | |
31376 | fill_prefetch_0 (); | |
31377 | m68k_write_memory_8(dsta,src); | |
31378 | }}}return 12; | |
31379 | } | |
31380 | unsigned long CPUFUNC(op_1148_5)(uint32_t opcode) /* MOVE */ | |
31381 | { | |
31382 | uint32_t srcreg = (opcode & 7); | |
31383 | uint32_t dstreg = (opcode >> 9) & 7; | |
31384 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
31385 | {{ int8_t src = m68k_areg(regs, srcreg); | |
31386 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
31387 | CLEAR_CZNV; | |
31388 | SET_ZFLG (((int8_t)(src)) == 0); | |
31389 | SET_NFLG (((int8_t)(src)) < 0); | |
31390 | m68k_incpc(4); | |
31391 | fill_prefetch_0 (); | |
31392 | m68k_write_memory_8(dsta,src); | |
31393 | }}}return 12; | |
31394 | } | |
31395 | unsigned long CPUFUNC(op_1150_5)(uint32_t opcode) /* MOVE */ | |
31396 | { | |
31397 | uint32_t srcreg = (opcode & 7); | |
31398 | uint32_t dstreg = (opcode >> 9) & 7; | |
31399 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
31400 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
31401 | { int8_t src = m68k_read_memory_8(srca); | |
31402 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
31403 | CLEAR_CZNV; | |
31404 | SET_ZFLG (((int8_t)(src)) == 0); | |
31405 | SET_NFLG (((int8_t)(src)) < 0); | |
31406 | m68k_incpc(4); | |
31407 | fill_prefetch_0 (); | |
31408 | m68k_write_memory_8(dsta,src); | |
31409 | }}}}return 16; | |
31410 | } | |
31411 | unsigned long CPUFUNC(op_1158_5)(uint32_t opcode) /* MOVE */ | |
31412 | { | |
31413 | uint32_t srcreg = (opcode & 7); | |
31414 | uint32_t dstreg = (opcode >> 9) & 7; | |
31415 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
31416 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
31417 | { int8_t src = m68k_read_memory_8(srca); | |
31418 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
31419 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
31420 | CLEAR_CZNV; | |
31421 | SET_ZFLG (((int8_t)(src)) == 0); | |
31422 | SET_NFLG (((int8_t)(src)) < 0); | |
31423 | m68k_incpc(4); | |
31424 | fill_prefetch_0 (); | |
31425 | m68k_write_memory_8(dsta,src); | |
31426 | }}}}return 16; | |
31427 | } | |
31428 | unsigned long CPUFUNC(op_1160_5)(uint32_t opcode) /* MOVE */ | |
31429 | { | |
31430 | uint32_t srcreg = (opcode & 7); | |
31431 | uint32_t dstreg = (opcode >> 9) & 7; | |
31432 | OpcodeFamily = 30; CurrentInstrCycles = 18; | |
31433 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
31434 | { int8_t src = m68k_read_memory_8(srca); | |
31435 | m68k_areg (regs, srcreg) = srca; | |
31436 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
31437 | CLEAR_CZNV; | |
31438 | SET_ZFLG (((int8_t)(src)) == 0); | |
31439 | SET_NFLG (((int8_t)(src)) < 0); | |
31440 | m68k_incpc(4); | |
31441 | fill_prefetch_0 (); | |
31442 | m68k_write_memory_8(dsta,src); | |
31443 | }}}}return 18; | |
31444 | } | |
31445 | unsigned long CPUFUNC(op_1168_5)(uint32_t opcode) /* MOVE */ | |
31446 | { | |
31447 | uint32_t srcreg = (opcode & 7); | |
31448 | uint32_t dstreg = (opcode >> 9) & 7; | |
31449 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
31450 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
31451 | { int8_t src = m68k_read_memory_8(srca); | |
31452 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); | |
31453 | CLEAR_CZNV; | |
31454 | SET_ZFLG (((int8_t)(src)) == 0); | |
31455 | SET_NFLG (((int8_t)(src)) < 0); | |
31456 | m68k_incpc(6); | |
31457 | fill_prefetch_0 (); | |
31458 | m68k_write_memory_8(dsta,src); | |
31459 | }}}}return 20; | |
31460 | } | |
31461 | unsigned long CPUFUNC(op_1170_5)(uint32_t opcode) /* MOVE */ | |
31462 | { | |
31463 | uint32_t srcreg = (opcode & 7); | |
31464 | uint32_t dstreg = (opcode >> 9) & 7; | |
31465 | OpcodeFamily = 30; CurrentInstrCycles = 22; | |
31466 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
31467 | BusCyclePenalty += 2; | |
31468 | { int8_t src = m68k_read_memory_8(srca); | |
31469 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); | |
31470 | CLEAR_CZNV; | |
31471 | SET_ZFLG (((int8_t)(src)) == 0); | |
31472 | SET_NFLG (((int8_t)(src)) < 0); | |
31473 | m68k_incpc(6); | |
31474 | fill_prefetch_0 (); | |
31475 | m68k_write_memory_8(dsta,src); | |
31476 | }}}}return 22; | |
31477 | } | |
31478 | unsigned long CPUFUNC(op_1178_5)(uint32_t opcode) /* MOVE */ | |
31479 | { | |
31480 | uint32_t dstreg = (opcode >> 9) & 7; | |
31481 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
31482 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
31483 | { int8_t src = m68k_read_memory_8(srca); | |
31484 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); | |
31485 | CLEAR_CZNV; | |
31486 | SET_ZFLG (((int8_t)(src)) == 0); | |
31487 | SET_NFLG (((int8_t)(src)) < 0); | |
31488 | m68k_incpc(6); | |
31489 | fill_prefetch_0 (); | |
31490 | m68k_write_memory_8(dsta,src); | |
31491 | }}}}return 20; | |
31492 | } | |
31493 | unsigned long CPUFUNC(op_1179_5)(uint32_t opcode) /* MOVE */ | |
31494 | { | |
31495 | uint32_t dstreg = (opcode >> 9) & 7; | |
31496 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
31497 | {{ uint32_t srca = get_ilong_prefetch(2); | |
31498 | { int8_t src = m68k_read_memory_8(srca); | |
31499 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(6); | |
31500 | CLEAR_CZNV; | |
31501 | SET_ZFLG (((int8_t)(src)) == 0); | |
31502 | SET_NFLG (((int8_t)(src)) < 0); | |
31503 | m68k_incpc(8); | |
31504 | fill_prefetch_0 (); | |
31505 | m68k_write_memory_8(dsta,src); | |
31506 | }}}}return 24; | |
31507 | } | |
31508 | unsigned long CPUFUNC(op_117a_5)(uint32_t opcode) /* MOVE */ | |
31509 | { | |
31510 | uint32_t dstreg = (opcode >> 9) & 7; | |
31511 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
31512 | {{ uint32_t srca = m68k_getpc () + 2; | |
31513 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
31514 | { int8_t src = m68k_read_memory_8(srca); | |
31515 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); | |
31516 | CLEAR_CZNV; | |
31517 | SET_ZFLG (((int8_t)(src)) == 0); | |
31518 | SET_NFLG (((int8_t)(src)) < 0); | |
31519 | m68k_incpc(6); | |
31520 | fill_prefetch_0 (); | |
31521 | m68k_write_memory_8(dsta,src); | |
31522 | }}}}return 20; | |
31523 | } | |
31524 | unsigned long CPUFUNC(op_117b_5)(uint32_t opcode) /* MOVE */ | |
31525 | { | |
31526 | uint32_t dstreg = (opcode >> 9) & 7; | |
31527 | OpcodeFamily = 30; CurrentInstrCycles = 22; | |
31528 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
31529 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
31530 | BusCyclePenalty += 2; | |
31531 | { int8_t src = m68k_read_memory_8(srca); | |
31532 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); | |
31533 | CLEAR_CZNV; | |
31534 | SET_ZFLG (((int8_t)(src)) == 0); | |
31535 | SET_NFLG (((int8_t)(src)) < 0); | |
31536 | m68k_incpc(6); | |
31537 | fill_prefetch_0 (); | |
31538 | m68k_write_memory_8(dsta,src); | |
31539 | }}}}return 22; | |
31540 | } | |
31541 | unsigned long CPUFUNC(op_117c_5)(uint32_t opcode) /* MOVE */ | |
31542 | { | |
31543 | uint32_t dstreg = (opcode >> 9) & 7; | |
31544 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
31545 | {{ int8_t src = get_ibyte_prefetch(2); | |
31546 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); | |
31547 | CLEAR_CZNV; | |
31548 | SET_ZFLG (((int8_t)(src)) == 0); | |
31549 | SET_NFLG (((int8_t)(src)) < 0); | |
31550 | m68k_incpc(6); | |
31551 | fill_prefetch_0 (); | |
31552 | m68k_write_memory_8(dsta,src); | |
31553 | }}}return 16; | |
31554 | } | |
31555 | unsigned long CPUFUNC(op_1180_5)(uint32_t opcode) /* MOVE */ | |
31556 | { | |
31557 | uint32_t srcreg = (opcode & 7); | |
31558 | uint32_t dstreg = (opcode >> 9) & 7; | |
31559 | OpcodeFamily = 30; CurrentInstrCycles = 14; | |
31560 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
31561 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); | |
31562 | BusCyclePenalty += 2; | |
31563 | CLEAR_CZNV; | |
31564 | SET_ZFLG (((int8_t)(src)) == 0); | |
31565 | SET_NFLG (((int8_t)(src)) < 0); | |
31566 | m68k_incpc(4); | |
31567 | fill_prefetch_0 (); | |
31568 | m68k_write_memory_8(dsta,src); | |
31569 | }}}return 14; | |
31570 | } | |
31571 | unsigned long CPUFUNC(op_1188_5)(uint32_t opcode) /* MOVE */ | |
31572 | { | |
31573 | uint32_t srcreg = (opcode & 7); | |
31574 | uint32_t dstreg = (opcode >> 9) & 7; | |
31575 | OpcodeFamily = 30; CurrentInstrCycles = 14; | |
31576 | {{ int8_t src = m68k_areg(regs, srcreg); | |
31577 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); | |
31578 | BusCyclePenalty += 2; | |
31579 | CLEAR_CZNV; | |
31580 | SET_ZFLG (((int8_t)(src)) == 0); | |
31581 | SET_NFLG (((int8_t)(src)) < 0); | |
31582 | m68k_incpc(4); | |
31583 | fill_prefetch_0 (); | |
31584 | m68k_write_memory_8(dsta,src); | |
31585 | }}}return 14; | |
31586 | } | |
31587 | unsigned long CPUFUNC(op_1190_5)(uint32_t opcode) /* MOVE */ | |
31588 | { | |
31589 | uint32_t srcreg = (opcode & 7); | |
31590 | uint32_t dstreg = (opcode >> 9) & 7; | |
31591 | OpcodeFamily = 30; CurrentInstrCycles = 18; | |
31592 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
31593 | { int8_t src = m68k_read_memory_8(srca); | |
31594 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); | |
31595 | BusCyclePenalty += 2; | |
31596 | CLEAR_CZNV; | |
31597 | SET_ZFLG (((int8_t)(src)) == 0); | |
31598 | SET_NFLG (((int8_t)(src)) < 0); | |
31599 | m68k_incpc(4); | |
31600 | fill_prefetch_0 (); | |
31601 | m68k_write_memory_8(dsta,src); | |
31602 | }}}}return 18; | |
31603 | } | |
31604 | unsigned long CPUFUNC(op_1198_5)(uint32_t opcode) /* MOVE */ | |
31605 | { | |
31606 | uint32_t srcreg = (opcode & 7); | |
31607 | uint32_t dstreg = (opcode >> 9) & 7; | |
31608 | OpcodeFamily = 30; CurrentInstrCycles = 18; | |
31609 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
31610 | { int8_t src = m68k_read_memory_8(srca); | |
31611 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
31612 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); | |
31613 | BusCyclePenalty += 2; | |
31614 | CLEAR_CZNV; | |
31615 | SET_ZFLG (((int8_t)(src)) == 0); | |
31616 | SET_NFLG (((int8_t)(src)) < 0); | |
31617 | m68k_incpc(4); | |
31618 | fill_prefetch_0 (); | |
31619 | m68k_write_memory_8(dsta,src); | |
31620 | }}}}return 18; | |
31621 | } | |
31622 | unsigned long CPUFUNC(op_11a0_5)(uint32_t opcode) /* MOVE */ | |
31623 | { | |
31624 | uint32_t srcreg = (opcode & 7); | |
31625 | uint32_t dstreg = (opcode >> 9) & 7; | |
31626 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
31627 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
31628 | { int8_t src = m68k_read_memory_8(srca); | |
31629 | m68k_areg (regs, srcreg) = srca; | |
31630 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); | |
31631 | BusCyclePenalty += 2; | |
31632 | CLEAR_CZNV; | |
31633 | SET_ZFLG (((int8_t)(src)) == 0); | |
31634 | SET_NFLG (((int8_t)(src)) < 0); | |
31635 | m68k_incpc(4); | |
31636 | fill_prefetch_0 (); | |
31637 | m68k_write_memory_8(dsta,src); | |
31638 | }}}}return 20; | |
31639 | } | |
31640 | unsigned long CPUFUNC(op_11a8_5)(uint32_t opcode) /* MOVE */ | |
31641 | { | |
31642 | uint32_t srcreg = (opcode & 7); | |
31643 | uint32_t dstreg = (opcode >> 9) & 7; | |
31644 | OpcodeFamily = 30; CurrentInstrCycles = 22; | |
31645 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
31646 | { int8_t src = m68k_read_memory_8(srca); | |
31647 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); | |
31648 | BusCyclePenalty += 2; | |
31649 | CLEAR_CZNV; | |
31650 | SET_ZFLG (((int8_t)(src)) == 0); | |
31651 | SET_NFLG (((int8_t)(src)) < 0); | |
31652 | m68k_incpc(6); | |
31653 | fill_prefetch_0 (); | |
31654 | m68k_write_memory_8(dsta,src); | |
31655 | }}}}return 22; | |
31656 | } | |
31657 | unsigned long CPUFUNC(op_11b0_5)(uint32_t opcode) /* MOVE */ | |
31658 | { | |
31659 | uint32_t srcreg = (opcode & 7); | |
31660 | uint32_t dstreg = (opcode >> 9) & 7; | |
31661 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
31662 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
31663 | BusCyclePenalty += 2; | |
31664 | { int8_t src = m68k_read_memory_8(srca); | |
31665 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); | |
31666 | BusCyclePenalty += 2; | |
31667 | CLEAR_CZNV; | |
31668 | SET_ZFLG (((int8_t)(src)) == 0); | |
31669 | SET_NFLG (((int8_t)(src)) < 0); | |
31670 | m68k_incpc(6); | |
31671 | fill_prefetch_0 (); | |
31672 | m68k_write_memory_8(dsta,src); | |
31673 | }}}}return 24; | |
31674 | } | |
31675 | unsigned long CPUFUNC(op_11b8_5)(uint32_t opcode) /* MOVE */ | |
31676 | { | |
31677 | uint32_t dstreg = (opcode >> 9) & 7; | |
31678 | OpcodeFamily = 30; CurrentInstrCycles = 22; | |
31679 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
31680 | { int8_t src = m68k_read_memory_8(srca); | |
31681 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); | |
31682 | BusCyclePenalty += 2; | |
31683 | CLEAR_CZNV; | |
31684 | SET_ZFLG (((int8_t)(src)) == 0); | |
31685 | SET_NFLG (((int8_t)(src)) < 0); | |
31686 | m68k_incpc(6); | |
31687 | fill_prefetch_0 (); | |
31688 | m68k_write_memory_8(dsta,src); | |
31689 | }}}}return 22; | |
31690 | } | |
31691 | unsigned long CPUFUNC(op_11b9_5)(uint32_t opcode) /* MOVE */ | |
31692 | { | |
31693 | uint32_t dstreg = (opcode >> 9) & 7; | |
31694 | OpcodeFamily = 30; CurrentInstrCycles = 26; | |
31695 | {{ uint32_t srca = get_ilong_prefetch(2); | |
31696 | { int8_t src = m68k_read_memory_8(srca); | |
31697 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(6)); | |
31698 | BusCyclePenalty += 2; | |
31699 | CLEAR_CZNV; | |
31700 | SET_ZFLG (((int8_t)(src)) == 0); | |
31701 | SET_NFLG (((int8_t)(src)) < 0); | |
31702 | m68k_incpc(8); | |
31703 | fill_prefetch_0 (); | |
31704 | m68k_write_memory_8(dsta,src); | |
31705 | }}}}return 26; | |
31706 | } | |
31707 | unsigned long CPUFUNC(op_11ba_5)(uint32_t opcode) /* MOVE */ | |
31708 | { | |
31709 | uint32_t dstreg = (opcode >> 9) & 7; | |
31710 | OpcodeFamily = 30; CurrentInstrCycles = 22; | |
31711 | {{ uint32_t srca = m68k_getpc () + 2; | |
31712 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
31713 | { int8_t src = m68k_read_memory_8(srca); | |
31714 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); | |
31715 | BusCyclePenalty += 2; | |
31716 | CLEAR_CZNV; | |
31717 | SET_ZFLG (((int8_t)(src)) == 0); | |
31718 | SET_NFLG (((int8_t)(src)) < 0); | |
31719 | m68k_incpc(6); | |
31720 | fill_prefetch_0 (); | |
31721 | m68k_write_memory_8(dsta,src); | |
31722 | }}}}return 22; | |
31723 | } | |
31724 | unsigned long CPUFUNC(op_11bb_5)(uint32_t opcode) /* MOVE */ | |
31725 | { | |
31726 | uint32_t dstreg = (opcode >> 9) & 7; | |
31727 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
31728 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
31729 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
31730 | BusCyclePenalty += 2; | |
31731 | { int8_t src = m68k_read_memory_8(srca); | |
31732 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); | |
31733 | BusCyclePenalty += 2; | |
31734 | CLEAR_CZNV; | |
31735 | SET_ZFLG (((int8_t)(src)) == 0); | |
31736 | SET_NFLG (((int8_t)(src)) < 0); | |
31737 | m68k_incpc(6); | |
31738 | fill_prefetch_0 (); | |
31739 | m68k_write_memory_8(dsta,src); | |
31740 | }}}}return 24; | |
31741 | } | |
31742 | unsigned long CPUFUNC(op_11bc_5)(uint32_t opcode) /* MOVE */ | |
31743 | { | |
31744 | uint32_t dstreg = (opcode >> 9) & 7; | |
31745 | OpcodeFamily = 30; CurrentInstrCycles = 18; | |
31746 | {{ int8_t src = get_ibyte_prefetch(2); | |
31747 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); | |
31748 | BusCyclePenalty += 2; | |
31749 | CLEAR_CZNV; | |
31750 | SET_ZFLG (((int8_t)(src)) == 0); | |
31751 | SET_NFLG (((int8_t)(src)) < 0); | |
31752 | m68k_incpc(6); | |
31753 | fill_prefetch_0 (); | |
31754 | m68k_write_memory_8(dsta,src); | |
31755 | }}}return 18; | |
31756 | } | |
31757 | unsigned long CPUFUNC(op_11c0_5)(uint32_t opcode) /* MOVE */ | |
31758 | { | |
31759 | uint32_t srcreg = (opcode & 7); | |
31760 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
31761 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
31762 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); | |
31763 | CLEAR_CZNV; | |
31764 | SET_ZFLG (((int8_t)(src)) == 0); | |
31765 | SET_NFLG (((int8_t)(src)) < 0); | |
31766 | m68k_incpc(4); | |
31767 | fill_prefetch_0 (); | |
31768 | m68k_write_memory_8(dsta,src); | |
31769 | }}}return 12; | |
31770 | } | |
31771 | unsigned long CPUFUNC(op_11c8_5)(uint32_t opcode) /* MOVE */ | |
31772 | { | |
31773 | uint32_t srcreg = (opcode & 7); | |
31774 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
31775 | {{ int8_t src = m68k_areg(regs, srcreg); | |
31776 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); | |
31777 | CLEAR_CZNV; | |
31778 | SET_ZFLG (((int8_t)(src)) == 0); | |
31779 | SET_NFLG (((int8_t)(src)) < 0); | |
31780 | m68k_incpc(4); | |
31781 | fill_prefetch_0 (); | |
31782 | m68k_write_memory_8(dsta,src); | |
31783 | }}}return 12; | |
31784 | } | |
31785 | unsigned long CPUFUNC(op_11d0_5)(uint32_t opcode) /* MOVE */ | |
31786 | { | |
31787 | uint32_t srcreg = (opcode & 7); | |
31788 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
31789 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
31790 | { int8_t src = m68k_read_memory_8(srca); | |
31791 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); | |
31792 | CLEAR_CZNV; | |
31793 | SET_ZFLG (((int8_t)(src)) == 0); | |
31794 | SET_NFLG (((int8_t)(src)) < 0); | |
31795 | m68k_incpc(4); | |
31796 | fill_prefetch_0 (); | |
31797 | m68k_write_memory_8(dsta,src); | |
31798 | }}}}return 16; | |
31799 | } | |
31800 | unsigned long CPUFUNC(op_11d8_5)(uint32_t opcode) /* MOVE */ | |
31801 | { | |
31802 | uint32_t srcreg = (opcode & 7); | |
31803 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
31804 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
31805 | { int8_t src = m68k_read_memory_8(srca); | |
31806 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
31807 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); | |
31808 | CLEAR_CZNV; | |
31809 | SET_ZFLG (((int8_t)(src)) == 0); | |
31810 | SET_NFLG (((int8_t)(src)) < 0); | |
31811 | m68k_incpc(4); | |
31812 | fill_prefetch_0 (); | |
31813 | m68k_write_memory_8(dsta,src); | |
31814 | }}}}return 16; | |
31815 | } | |
31816 | unsigned long CPUFUNC(op_11e0_5)(uint32_t opcode) /* MOVE */ | |
31817 | { | |
31818 | uint32_t srcreg = (opcode & 7); | |
31819 | OpcodeFamily = 30; CurrentInstrCycles = 18; | |
31820 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
31821 | { int8_t src = m68k_read_memory_8(srca); | |
31822 | m68k_areg (regs, srcreg) = srca; | |
31823 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); | |
31824 | CLEAR_CZNV; | |
31825 | SET_ZFLG (((int8_t)(src)) == 0); | |
31826 | SET_NFLG (((int8_t)(src)) < 0); | |
31827 | m68k_incpc(4); | |
31828 | fill_prefetch_0 (); | |
31829 | m68k_write_memory_8(dsta,src); | |
31830 | }}}}return 18; | |
31831 | } | |
31832 | unsigned long CPUFUNC(op_11e8_5)(uint32_t opcode) /* MOVE */ | |
31833 | { | |
31834 | uint32_t srcreg = (opcode & 7); | |
31835 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
31836 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
31837 | { int8_t src = m68k_read_memory_8(srca); | |
31838 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); | |
31839 | CLEAR_CZNV; | |
31840 | SET_ZFLG (((int8_t)(src)) == 0); | |
31841 | SET_NFLG (((int8_t)(src)) < 0); | |
31842 | m68k_incpc(6); | |
31843 | fill_prefetch_0 (); | |
31844 | m68k_write_memory_8(dsta,src); | |
31845 | }}}}return 20; | |
31846 | } | |
31847 | unsigned long CPUFUNC(op_11f0_5)(uint32_t opcode) /* MOVE */ | |
31848 | { | |
31849 | uint32_t srcreg = (opcode & 7); | |
31850 | OpcodeFamily = 30; CurrentInstrCycles = 22; | |
31851 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
31852 | BusCyclePenalty += 2; | |
31853 | { int8_t src = m68k_read_memory_8(srca); | |
31854 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); | |
31855 | CLEAR_CZNV; | |
31856 | SET_ZFLG (((int8_t)(src)) == 0); | |
31857 | SET_NFLG (((int8_t)(src)) < 0); | |
31858 | m68k_incpc(6); | |
31859 | fill_prefetch_0 (); | |
31860 | m68k_write_memory_8(dsta,src); | |
31861 | }}}}return 22; | |
31862 | } | |
31863 | unsigned long CPUFUNC(op_11f8_5)(uint32_t opcode) /* MOVE */ | |
31864 | { | |
31865 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
31866 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
31867 | { int8_t src = m68k_read_memory_8(srca); | |
31868 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); | |
31869 | CLEAR_CZNV; | |
31870 | SET_ZFLG (((int8_t)(src)) == 0); | |
31871 | SET_NFLG (((int8_t)(src)) < 0); | |
31872 | m68k_incpc(6); | |
31873 | fill_prefetch_0 (); | |
31874 | m68k_write_memory_8(dsta,src); | |
31875 | }}}}return 20; | |
31876 | } | |
31877 | unsigned long CPUFUNC(op_11f9_5)(uint32_t opcode) /* MOVE */ | |
31878 | { | |
31879 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
31880 | {{ uint32_t srca = get_ilong_prefetch(2); | |
31881 | { int8_t src = m68k_read_memory_8(srca); | |
31882 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(6); | |
31883 | CLEAR_CZNV; | |
31884 | SET_ZFLG (((int8_t)(src)) == 0); | |
31885 | SET_NFLG (((int8_t)(src)) < 0); | |
31886 | m68k_incpc(8); | |
31887 | fill_prefetch_0 (); | |
31888 | m68k_write_memory_8(dsta,src); | |
31889 | }}}}return 24; | |
31890 | } | |
31891 | unsigned long CPUFUNC(op_11fa_5)(uint32_t opcode) /* MOVE */ | |
31892 | { | |
31893 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
31894 | {{ uint32_t srca = m68k_getpc () + 2; | |
31895 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
31896 | { int8_t src = m68k_read_memory_8(srca); | |
31897 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); | |
31898 | CLEAR_CZNV; | |
31899 | SET_ZFLG (((int8_t)(src)) == 0); | |
31900 | SET_NFLG (((int8_t)(src)) < 0); | |
31901 | m68k_incpc(6); | |
31902 | fill_prefetch_0 (); | |
31903 | m68k_write_memory_8(dsta,src); | |
31904 | }}}}return 20; | |
31905 | } | |
31906 | unsigned long CPUFUNC(op_11fb_5)(uint32_t opcode) /* MOVE */ | |
31907 | { | |
31908 | OpcodeFamily = 30; CurrentInstrCycles = 22; | |
31909 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
31910 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
31911 | BusCyclePenalty += 2; | |
31912 | { int8_t src = m68k_read_memory_8(srca); | |
31913 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); | |
31914 | CLEAR_CZNV; | |
31915 | SET_ZFLG (((int8_t)(src)) == 0); | |
31916 | SET_NFLG (((int8_t)(src)) < 0); | |
31917 | m68k_incpc(6); | |
31918 | fill_prefetch_0 (); | |
31919 | m68k_write_memory_8(dsta,src); | |
31920 | }}}}return 22; | |
31921 | } | |
31922 | unsigned long CPUFUNC(op_11fc_5)(uint32_t opcode) /* MOVE */ | |
31923 | { | |
31924 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
31925 | {{ int8_t src = get_ibyte_prefetch(2); | |
31926 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); | |
31927 | CLEAR_CZNV; | |
31928 | SET_ZFLG (((int8_t)(src)) == 0); | |
31929 | SET_NFLG (((int8_t)(src)) < 0); | |
31930 | m68k_incpc(6); | |
31931 | fill_prefetch_0 (); | |
31932 | m68k_write_memory_8(dsta,src); | |
31933 | }}}return 16; | |
31934 | } | |
31935 | unsigned long CPUFUNC(op_13c0_5)(uint32_t opcode) /* MOVE */ | |
31936 | { | |
31937 | uint32_t srcreg = (opcode & 7); | |
31938 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
31939 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
31940 | { uint32_t dsta = get_ilong_prefetch(2); | |
31941 | CLEAR_CZNV; | |
31942 | SET_ZFLG (((int8_t)(src)) == 0); | |
31943 | SET_NFLG (((int8_t)(src)) < 0); | |
31944 | m68k_incpc(6); | |
31945 | fill_prefetch_0 (); | |
31946 | m68k_write_memory_8(dsta,src); | |
31947 | }}}return 16; | |
31948 | } | |
31949 | unsigned long CPUFUNC(op_13c8_5)(uint32_t opcode) /* MOVE */ | |
31950 | { | |
31951 | uint32_t srcreg = (opcode & 7); | |
31952 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
31953 | {{ int8_t src = m68k_areg(regs, srcreg); | |
31954 | { uint32_t dsta = get_ilong_prefetch(2); | |
31955 | CLEAR_CZNV; | |
31956 | SET_ZFLG (((int8_t)(src)) == 0); | |
31957 | SET_NFLG (((int8_t)(src)) < 0); | |
31958 | m68k_incpc(6); | |
31959 | fill_prefetch_0 (); | |
31960 | m68k_write_memory_8(dsta,src); | |
31961 | }}}return 16; | |
31962 | } | |
31963 | unsigned long CPUFUNC(op_13d0_5)(uint32_t opcode) /* MOVE */ | |
31964 | { | |
31965 | uint32_t srcreg = (opcode & 7); | |
31966 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
31967 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
31968 | { int8_t src = m68k_read_memory_8(srca); | |
31969 | { uint32_t dsta = get_ilong_prefetch(2); | |
31970 | CLEAR_CZNV; | |
31971 | SET_ZFLG (((int8_t)(src)) == 0); | |
31972 | SET_NFLG (((int8_t)(src)) < 0); | |
31973 | m68k_incpc(6); | |
31974 | fill_prefetch_0 (); | |
31975 | m68k_write_memory_8(dsta,src); | |
31976 | }}}}return 20; | |
31977 | } | |
31978 | unsigned long CPUFUNC(op_13d8_5)(uint32_t opcode) /* MOVE */ | |
31979 | { | |
31980 | uint32_t srcreg = (opcode & 7); | |
31981 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
31982 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
31983 | { int8_t src = m68k_read_memory_8(srca); | |
31984 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
31985 | { uint32_t dsta = get_ilong_prefetch(2); | |
31986 | CLEAR_CZNV; | |
31987 | SET_ZFLG (((int8_t)(src)) == 0); | |
31988 | SET_NFLG (((int8_t)(src)) < 0); | |
31989 | m68k_incpc(6); | |
31990 | fill_prefetch_0 (); | |
31991 | m68k_write_memory_8(dsta,src); | |
31992 | }}}}return 20; | |
31993 | } | |
31994 | unsigned long CPUFUNC(op_13e0_5)(uint32_t opcode) /* MOVE */ | |
31995 | { | |
31996 | uint32_t srcreg = (opcode & 7); | |
31997 | OpcodeFamily = 30; CurrentInstrCycles = 22; | |
31998 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
31999 | { int8_t src = m68k_read_memory_8(srca); | |
32000 | m68k_areg (regs, srcreg) = srca; | |
32001 | { uint32_t dsta = get_ilong_prefetch(2); | |
32002 | CLEAR_CZNV; | |
32003 | SET_ZFLG (((int8_t)(src)) == 0); | |
32004 | SET_NFLG (((int8_t)(src)) < 0); | |
32005 | m68k_incpc(6); | |
32006 | fill_prefetch_0 (); | |
32007 | m68k_write_memory_8(dsta,src); | |
32008 | }}}}return 22; | |
32009 | } | |
32010 | unsigned long CPUFUNC(op_13e8_5)(uint32_t opcode) /* MOVE */ | |
32011 | { | |
32012 | uint32_t srcreg = (opcode & 7); | |
32013 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
32014 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
32015 | { int8_t src = m68k_read_memory_8(srca); | |
32016 | { uint32_t dsta = get_ilong_prefetch(4); | |
32017 | CLEAR_CZNV; | |
32018 | SET_ZFLG (((int8_t)(src)) == 0); | |
32019 | SET_NFLG (((int8_t)(src)) < 0); | |
32020 | m68k_incpc(8); | |
32021 | fill_prefetch_0 (); | |
32022 | m68k_write_memory_8(dsta,src); | |
32023 | }}}}return 24; | |
32024 | } | |
32025 | unsigned long CPUFUNC(op_13f0_5)(uint32_t opcode) /* MOVE */ | |
32026 | { | |
32027 | uint32_t srcreg = (opcode & 7); | |
32028 | OpcodeFamily = 30; CurrentInstrCycles = 26; | |
32029 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
32030 | BusCyclePenalty += 2; | |
32031 | { int8_t src = m68k_read_memory_8(srca); | |
32032 | { uint32_t dsta = get_ilong_prefetch(4); | |
32033 | CLEAR_CZNV; | |
32034 | SET_ZFLG (((int8_t)(src)) == 0); | |
32035 | SET_NFLG (((int8_t)(src)) < 0); | |
32036 | m68k_incpc(8); | |
32037 | fill_prefetch_0 (); | |
32038 | m68k_write_memory_8(dsta,src); | |
32039 | }}}}return 26; | |
32040 | } | |
32041 | unsigned long CPUFUNC(op_13f8_5)(uint32_t opcode) /* MOVE */ | |
32042 | { | |
32043 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
32044 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
32045 | { int8_t src = m68k_read_memory_8(srca); | |
32046 | { uint32_t dsta = get_ilong_prefetch(4); | |
32047 | CLEAR_CZNV; | |
32048 | SET_ZFLG (((int8_t)(src)) == 0); | |
32049 | SET_NFLG (((int8_t)(src)) < 0); | |
32050 | m68k_incpc(8); | |
32051 | fill_prefetch_0 (); | |
32052 | m68k_write_memory_8(dsta,src); | |
32053 | }}}}return 24; | |
32054 | } | |
32055 | unsigned long CPUFUNC(op_13f9_5)(uint32_t opcode) /* MOVE */ | |
32056 | { | |
32057 | OpcodeFamily = 30; CurrentInstrCycles = 28; | |
32058 | {{ uint32_t srca = get_ilong_prefetch(2); | |
32059 | { int8_t src = m68k_read_memory_8(srca); | |
32060 | { uint32_t dsta = get_ilong_prefetch(6); | |
32061 | CLEAR_CZNV; | |
32062 | SET_ZFLG (((int8_t)(src)) == 0); | |
32063 | SET_NFLG (((int8_t)(src)) < 0); | |
32064 | m68k_incpc(10); | |
32065 | fill_prefetch_0 (); | |
32066 | m68k_write_memory_8(dsta,src); | |
32067 | }}}}return 28; | |
32068 | } | |
32069 | unsigned long CPUFUNC(op_13fa_5)(uint32_t opcode) /* MOVE */ | |
32070 | { | |
32071 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
32072 | {{ uint32_t srca = m68k_getpc () + 2; | |
32073 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
32074 | { int8_t src = m68k_read_memory_8(srca); | |
32075 | { uint32_t dsta = get_ilong_prefetch(4); | |
32076 | CLEAR_CZNV; | |
32077 | SET_ZFLG (((int8_t)(src)) == 0); | |
32078 | SET_NFLG (((int8_t)(src)) < 0); | |
32079 | m68k_incpc(8); | |
32080 | fill_prefetch_0 (); | |
32081 | m68k_write_memory_8(dsta,src); | |
32082 | }}}}return 24; | |
32083 | } | |
32084 | unsigned long CPUFUNC(op_13fb_5)(uint32_t opcode) /* MOVE */ | |
32085 | { | |
32086 | OpcodeFamily = 30; CurrentInstrCycles = 26; | |
32087 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
32088 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
32089 | BusCyclePenalty += 2; | |
32090 | { int8_t src = m68k_read_memory_8(srca); | |
32091 | { uint32_t dsta = get_ilong_prefetch(4); | |
32092 | CLEAR_CZNV; | |
32093 | SET_ZFLG (((int8_t)(src)) == 0); | |
32094 | SET_NFLG (((int8_t)(src)) < 0); | |
32095 | m68k_incpc(8); | |
32096 | fill_prefetch_0 (); | |
32097 | m68k_write_memory_8(dsta,src); | |
32098 | }}}}return 26; | |
32099 | } | |
32100 | unsigned long CPUFUNC(op_13fc_5)(uint32_t opcode) /* MOVE */ | |
32101 | { | |
32102 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
32103 | {{ int8_t src = get_ibyte_prefetch(2); | |
32104 | { uint32_t dsta = get_ilong_prefetch(4); | |
32105 | CLEAR_CZNV; | |
32106 | SET_ZFLG (((int8_t)(src)) == 0); | |
32107 | SET_NFLG (((int8_t)(src)) < 0); | |
32108 | m68k_incpc(8); | |
32109 | fill_prefetch_0 (); | |
32110 | m68k_write_memory_8(dsta,src); | |
32111 | }}}return 20; | |
32112 | } | |
32113 | unsigned long CPUFUNC(op_2000_5)(uint32_t opcode) /* MOVE */ | |
32114 | { | |
32115 | uint32_t srcreg = (opcode & 7); | |
32116 | uint32_t dstreg = (opcode >> 9) & 7; | |
32117 | OpcodeFamily = 30; CurrentInstrCycles = 4; | |
32118 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
32119 | { CLEAR_CZNV; | |
32120 | SET_ZFLG (((int32_t)(src)) == 0); | |
32121 | SET_NFLG (((int32_t)(src)) < 0); | |
32122 | m68k_dreg(regs, dstreg) = (src); | |
32123 | }}}m68k_incpc(2); | |
32124 | fill_prefetch_2 (); | |
32125 | return 4; | |
32126 | } | |
32127 | unsigned long CPUFUNC(op_2008_5)(uint32_t opcode) /* MOVE */ | |
32128 | { | |
32129 | uint32_t srcreg = (opcode & 7); | |
32130 | uint32_t dstreg = (opcode >> 9) & 7; | |
32131 | OpcodeFamily = 30; CurrentInstrCycles = 4; | |
32132 | {{ int32_t src = m68k_areg(regs, srcreg); | |
32133 | { CLEAR_CZNV; | |
32134 | SET_ZFLG (((int32_t)(src)) == 0); | |
32135 | SET_NFLG (((int32_t)(src)) < 0); | |
32136 | m68k_dreg(regs, dstreg) = (src); | |
32137 | }}}m68k_incpc(2); | |
32138 | fill_prefetch_2 (); | |
32139 | return 4; | |
32140 | } | |
32141 | unsigned long CPUFUNC(op_2010_5)(uint32_t opcode) /* MOVE */ | |
32142 | { | |
32143 | uint32_t srcreg = (opcode & 7); | |
32144 | uint32_t dstreg = (opcode >> 9) & 7; | |
32145 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
32146 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
32147 | if ((srca & 1) != 0) { | |
32148 | last_fault_for_exception_3 = srca; | |
32149 | last_op_for_exception_3 = opcode; | |
32150 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
32151 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
32152 | goto endlabel1921; | |
32153 | } | |
32154 | {{ int32_t src = m68k_read_memory_32(srca); | |
32155 | { CLEAR_CZNV; | |
32156 | SET_ZFLG (((int32_t)(src)) == 0); | |
32157 | SET_NFLG (((int32_t)(src)) < 0); | |
32158 | m68k_dreg(regs, dstreg) = (src); | |
32159 | }}}}}m68k_incpc(2); | |
32160 | fill_prefetch_2 (); | |
32161 | endlabel1921: ; | |
32162 | return 12; | |
32163 | } | |
32164 | unsigned long CPUFUNC(op_2018_5)(uint32_t opcode) /* MOVE */ | |
32165 | { | |
32166 | uint32_t srcreg = (opcode & 7); | |
32167 | uint32_t dstreg = (opcode >> 9) & 7; | |
32168 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
32169 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
32170 | if ((srca & 1) != 0) { | |
32171 | last_fault_for_exception_3 = srca; | |
32172 | last_op_for_exception_3 = opcode; | |
32173 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
32174 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
32175 | goto endlabel1922; | |
32176 | } | |
32177 | {{ int32_t src = m68k_read_memory_32(srca); | |
32178 | m68k_areg(regs, srcreg) += 4; | |
32179 | { CLEAR_CZNV; | |
32180 | SET_ZFLG (((int32_t)(src)) == 0); | |
32181 | SET_NFLG (((int32_t)(src)) < 0); | |
32182 | m68k_dreg(regs, dstreg) = (src); | |
32183 | }}}}}m68k_incpc(2); | |
32184 | fill_prefetch_2 (); | |
32185 | endlabel1922: ; | |
32186 | return 12; | |
32187 | } | |
32188 | unsigned long CPUFUNC(op_2020_5)(uint32_t opcode) /* MOVE */ | |
32189 | { | |
32190 | uint32_t srcreg = (opcode & 7); | |
32191 | uint32_t dstreg = (opcode >> 9) & 7; | |
32192 | OpcodeFamily = 30; CurrentInstrCycles = 14; | |
32193 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 4; | |
32194 | if ((srca & 1) != 0) { | |
32195 | last_fault_for_exception_3 = srca; | |
32196 | last_op_for_exception_3 = opcode; | |
32197 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
32198 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
32199 | goto endlabel1923; | |
32200 | } | |
32201 | {{ int32_t src = m68k_read_memory_32(srca); | |
32202 | m68k_areg (regs, srcreg) = srca; | |
32203 | { CLEAR_CZNV; | |
32204 | SET_ZFLG (((int32_t)(src)) == 0); | |
32205 | SET_NFLG (((int32_t)(src)) < 0); | |
32206 | m68k_dreg(regs, dstreg) = (src); | |
32207 | }}}}}m68k_incpc(2); | |
32208 | fill_prefetch_2 (); | |
32209 | endlabel1923: ; | |
32210 | return 14; | |
32211 | } | |
32212 | unsigned long CPUFUNC(op_2028_5)(uint32_t opcode) /* MOVE */ | |
32213 | { | |
32214 | uint32_t srcreg = (opcode & 7); | |
32215 | uint32_t dstreg = (opcode >> 9) & 7; | |
32216 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
32217 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
32218 | if ((srca & 1) != 0) { | |
32219 | last_fault_for_exception_3 = srca; | |
32220 | last_op_for_exception_3 = opcode; | |
32221 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
32222 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
32223 | goto endlabel1924; | |
32224 | } | |
32225 | {{ int32_t src = m68k_read_memory_32(srca); | |
32226 | { CLEAR_CZNV; | |
32227 | SET_ZFLG (((int32_t)(src)) == 0); | |
32228 | SET_NFLG (((int32_t)(src)) < 0); | |
32229 | m68k_dreg(regs, dstreg) = (src); | |
32230 | }}}}}m68k_incpc(4); | |
32231 | fill_prefetch_0 (); | |
32232 | endlabel1924: ; | |
32233 | return 16; | |
32234 | } | |
32235 | unsigned long CPUFUNC(op_2030_5)(uint32_t opcode) /* MOVE */ | |
32236 | { | |
32237 | uint32_t srcreg = (opcode & 7); | |
32238 | uint32_t dstreg = (opcode >> 9) & 7; | |
32239 | OpcodeFamily = 30; CurrentInstrCycles = 18; | |
32240 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
32241 | BusCyclePenalty += 2; | |
32242 | if ((srca & 1) != 0) { | |
32243 | last_fault_for_exception_3 = srca; | |
32244 | last_op_for_exception_3 = opcode; | |
32245 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
32246 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
32247 | goto endlabel1925; | |
32248 | } | |
32249 | {{ int32_t src = m68k_read_memory_32(srca); | |
32250 | { CLEAR_CZNV; | |
32251 | SET_ZFLG (((int32_t)(src)) == 0); | |
32252 | SET_NFLG (((int32_t)(src)) < 0); | |
32253 | m68k_dreg(regs, dstreg) = (src); | |
32254 | }}}}}m68k_incpc(4); | |
32255 | fill_prefetch_0 (); | |
32256 | endlabel1925: ; | |
32257 | return 18; | |
32258 | } | |
32259 | unsigned long CPUFUNC(op_2038_5)(uint32_t opcode) /* MOVE */ | |
32260 | { | |
32261 | uint32_t dstreg = (opcode >> 9) & 7; | |
32262 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
32263 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
32264 | if ((srca & 1) != 0) { | |
32265 | last_fault_for_exception_3 = srca; | |
32266 | last_op_for_exception_3 = opcode; | |
32267 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
32268 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
32269 | goto endlabel1926; | |
32270 | } | |
32271 | {{ int32_t src = m68k_read_memory_32(srca); | |
32272 | { CLEAR_CZNV; | |
32273 | SET_ZFLG (((int32_t)(src)) == 0); | |
32274 | SET_NFLG (((int32_t)(src)) < 0); | |
32275 | m68k_dreg(regs, dstreg) = (src); | |
32276 | }}}}}m68k_incpc(4); | |
32277 | fill_prefetch_0 (); | |
32278 | endlabel1926: ; | |
32279 | return 16; | |
32280 | } | |
32281 | unsigned long CPUFUNC(op_2039_5)(uint32_t opcode) /* MOVE */ | |
32282 | { | |
32283 | uint32_t dstreg = (opcode >> 9) & 7; | |
32284 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
32285 | {{ uint32_t srca = get_ilong_prefetch(2); | |
32286 | if ((srca & 1) != 0) { | |
32287 | last_fault_for_exception_3 = srca; | |
32288 | last_op_for_exception_3 = opcode; | |
32289 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
32290 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
32291 | goto endlabel1927; | |
32292 | } | |
32293 | {{ int32_t src = m68k_read_memory_32(srca); | |
32294 | { CLEAR_CZNV; | |
32295 | SET_ZFLG (((int32_t)(src)) == 0); | |
32296 | SET_NFLG (((int32_t)(src)) < 0); | |
32297 | m68k_dreg(regs, dstreg) = (src); | |
32298 | }}}}}m68k_incpc(6); | |
32299 | fill_prefetch_0 (); | |
32300 | endlabel1927: ; | |
32301 | return 20; | |
32302 | } | |
32303 | unsigned long CPUFUNC(op_203a_5)(uint32_t opcode) /* MOVE */ | |
32304 | { | |
32305 | uint32_t dstreg = (opcode >> 9) & 7; | |
32306 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
32307 | {{ uint32_t srca = m68k_getpc () + 2; | |
32308 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
32309 | if ((srca & 1) != 0) { | |
32310 | last_fault_for_exception_3 = srca; | |
32311 | last_op_for_exception_3 = opcode; | |
32312 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
32313 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
32314 | goto endlabel1928; | |
32315 | } | |
32316 | {{ int32_t src = m68k_read_memory_32(srca); | |
32317 | { CLEAR_CZNV; | |
32318 | SET_ZFLG (((int32_t)(src)) == 0); | |
32319 | SET_NFLG (((int32_t)(src)) < 0); | |
32320 | m68k_dreg(regs, dstreg) = (src); | |
32321 | }}}}}m68k_incpc(4); | |
32322 | fill_prefetch_0 (); | |
32323 | endlabel1928: ; | |
32324 | return 16; | |
32325 | } | |
32326 | unsigned long CPUFUNC(op_203b_5)(uint32_t opcode) /* MOVE */ | |
32327 | { | |
32328 | uint32_t dstreg = (opcode >> 9) & 7; | |
32329 | OpcodeFamily = 30; CurrentInstrCycles = 18; | |
32330 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
32331 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
32332 | BusCyclePenalty += 2; | |
32333 | if ((srca & 1) != 0) { | |
32334 | last_fault_for_exception_3 = srca; | |
32335 | last_op_for_exception_3 = opcode; | |
32336 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
32337 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
32338 | goto endlabel1929; | |
32339 | } | |
32340 | {{ int32_t src = m68k_read_memory_32(srca); | |
32341 | { CLEAR_CZNV; | |
32342 | SET_ZFLG (((int32_t)(src)) == 0); | |
32343 | SET_NFLG (((int32_t)(src)) < 0); | |
32344 | m68k_dreg(regs, dstreg) = (src); | |
32345 | }}}}}m68k_incpc(4); | |
32346 | fill_prefetch_0 (); | |
32347 | endlabel1929: ; | |
32348 | return 18; | |
32349 | } | |
32350 | unsigned long CPUFUNC(op_203c_5)(uint32_t opcode) /* MOVE */ | |
32351 | { | |
32352 | uint32_t dstreg = (opcode >> 9) & 7; | |
32353 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
32354 | {{ int32_t src = get_ilong_prefetch(2); | |
32355 | { CLEAR_CZNV; | |
32356 | SET_ZFLG (((int32_t)(src)) == 0); | |
32357 | SET_NFLG (((int32_t)(src)) < 0); | |
32358 | m68k_dreg(regs, dstreg) = (src); | |
32359 | }}}m68k_incpc(6); | |
32360 | fill_prefetch_0 (); | |
32361 | return 12; | |
32362 | } | |
32363 | unsigned long CPUFUNC(op_2040_5)(uint32_t opcode) /* MOVEA */ | |
32364 | { | |
32365 | uint32_t srcreg = (opcode & 7); | |
32366 | uint32_t dstreg = (opcode >> 9) & 7; | |
32367 | OpcodeFamily = 31; CurrentInstrCycles = 4; | |
32368 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
32369 | { uint32_t val = src; | |
32370 | m68k_areg(regs, dstreg) = (val); | |
32371 | }}}m68k_incpc(2); | |
32372 | fill_prefetch_2 (); | |
32373 | return 4; | |
32374 | } | |
32375 | unsigned long CPUFUNC(op_2048_5)(uint32_t opcode) /* MOVEA */ | |
32376 | { | |
32377 | uint32_t srcreg = (opcode & 7); | |
32378 | uint32_t dstreg = (opcode >> 9) & 7; | |
32379 | OpcodeFamily = 31; CurrentInstrCycles = 4; | |
32380 | {{ int32_t src = m68k_areg(regs, srcreg); | |
32381 | { uint32_t val = src; | |
32382 | m68k_areg(regs, dstreg) = (val); | |
32383 | }}}m68k_incpc(2); | |
32384 | fill_prefetch_2 (); | |
32385 | return 4; | |
32386 | } | |
32387 | unsigned long CPUFUNC(op_2050_5)(uint32_t opcode) /* MOVEA */ | |
32388 | { | |
32389 | uint32_t srcreg = (opcode & 7); | |
32390 | uint32_t dstreg = (opcode >> 9) & 7; | |
32391 | OpcodeFamily = 31; CurrentInstrCycles = 12; | |
32392 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
32393 | if ((srca & 1) != 0) { | |
32394 | last_fault_for_exception_3 = srca; | |
32395 | last_op_for_exception_3 = opcode; | |
32396 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
32397 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
32398 | goto endlabel1933; | |
32399 | } | |
32400 | {{ int32_t src = m68k_read_memory_32(srca); | |
32401 | { uint32_t val = src; | |
32402 | m68k_areg(regs, dstreg) = (val); | |
32403 | }}}}}m68k_incpc(2); | |
32404 | fill_prefetch_2 (); | |
32405 | endlabel1933: ; | |
32406 | return 12; | |
32407 | } | |
32408 | unsigned long CPUFUNC(op_2058_5)(uint32_t opcode) /* MOVEA */ | |
32409 | { | |
32410 | uint32_t srcreg = (opcode & 7); | |
32411 | uint32_t dstreg = (opcode >> 9) & 7; | |
32412 | OpcodeFamily = 31; CurrentInstrCycles = 12; | |
32413 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
32414 | if ((srca & 1) != 0) { | |
32415 | last_fault_for_exception_3 = srca; | |
32416 | last_op_for_exception_3 = opcode; | |
32417 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
32418 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
32419 | goto endlabel1934; | |
32420 | } | |
32421 | {{ int32_t src = m68k_read_memory_32(srca); | |
32422 | m68k_areg(regs, srcreg) += 4; | |
32423 | { uint32_t val = src; | |
32424 | m68k_areg(regs, dstreg) = (val); | |
32425 | }}}}}m68k_incpc(2); | |
32426 | fill_prefetch_2 (); | |
32427 | endlabel1934: ; | |
32428 | return 12; | |
32429 | } | |
32430 | unsigned long CPUFUNC(op_2060_5)(uint32_t opcode) /* MOVEA */ | |
32431 | { | |
32432 | uint32_t srcreg = (opcode & 7); | |
32433 | uint32_t dstreg = (opcode >> 9) & 7; | |
32434 | OpcodeFamily = 31; CurrentInstrCycles = 14; | |
32435 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 4; | |
32436 | if ((srca & 1) != 0) { | |
32437 | last_fault_for_exception_3 = srca; | |
32438 | last_op_for_exception_3 = opcode; | |
32439 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
32440 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
32441 | goto endlabel1935; | |
32442 | } | |
32443 | {{ int32_t src = m68k_read_memory_32(srca); | |
32444 | m68k_areg (regs, srcreg) = srca; | |
32445 | { uint32_t val = src; | |
32446 | m68k_areg(regs, dstreg) = (val); | |
32447 | }}}}}m68k_incpc(2); | |
32448 | fill_prefetch_2 (); | |
32449 | endlabel1935: ; | |
32450 | return 14; | |
32451 | } | |
32452 | unsigned long CPUFUNC(op_2068_5)(uint32_t opcode) /* MOVEA */ | |
32453 | { | |
32454 | uint32_t srcreg = (opcode & 7); | |
32455 | uint32_t dstreg = (opcode >> 9) & 7; | |
32456 | OpcodeFamily = 31; CurrentInstrCycles = 16; | |
32457 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
32458 | if ((srca & 1) != 0) { | |
32459 | last_fault_for_exception_3 = srca; | |
32460 | last_op_for_exception_3 = opcode; | |
32461 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
32462 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
32463 | goto endlabel1936; | |
32464 | } | |
32465 | {{ int32_t src = m68k_read_memory_32(srca); | |
32466 | { uint32_t val = src; | |
32467 | m68k_areg(regs, dstreg) = (val); | |
32468 | }}}}}m68k_incpc(4); | |
32469 | fill_prefetch_0 (); | |
32470 | endlabel1936: ; | |
32471 | return 16; | |
32472 | } | |
32473 | unsigned long CPUFUNC(op_2070_5)(uint32_t opcode) /* MOVEA */ | |
32474 | { | |
32475 | uint32_t srcreg = (opcode & 7); | |
32476 | uint32_t dstreg = (opcode >> 9) & 7; | |
32477 | OpcodeFamily = 31; CurrentInstrCycles = 18; | |
32478 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
32479 | BusCyclePenalty += 2; | |
32480 | if ((srca & 1) != 0) { | |
32481 | last_fault_for_exception_3 = srca; | |
32482 | last_op_for_exception_3 = opcode; | |
32483 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
32484 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
32485 | goto endlabel1937; | |
32486 | } | |
32487 | {{ int32_t src = m68k_read_memory_32(srca); | |
32488 | { uint32_t val = src; | |
32489 | m68k_areg(regs, dstreg) = (val); | |
32490 | }}}}}m68k_incpc(4); | |
32491 | fill_prefetch_0 (); | |
32492 | endlabel1937: ; | |
32493 | return 18; | |
32494 | } | |
32495 | unsigned long CPUFUNC(op_2078_5)(uint32_t opcode) /* MOVEA */ | |
32496 | { | |
32497 | uint32_t dstreg = (opcode >> 9) & 7; | |
32498 | OpcodeFamily = 31; CurrentInstrCycles = 16; | |
32499 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
32500 | if ((srca & 1) != 0) { | |
32501 | last_fault_for_exception_3 = srca; | |
32502 | last_op_for_exception_3 = opcode; | |
32503 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
32504 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
32505 | goto endlabel1938; | |
32506 | } | |
32507 | {{ int32_t src = m68k_read_memory_32(srca); | |
32508 | { uint32_t val = src; | |
32509 | m68k_areg(regs, dstreg) = (val); | |
32510 | }}}}}m68k_incpc(4); | |
32511 | fill_prefetch_0 (); | |
32512 | endlabel1938: ; | |
32513 | return 16; | |
32514 | } | |
32515 | unsigned long CPUFUNC(op_2079_5)(uint32_t opcode) /* MOVEA */ | |
32516 | { | |
32517 | uint32_t dstreg = (opcode >> 9) & 7; | |
32518 | OpcodeFamily = 31; CurrentInstrCycles = 20; | |
32519 | {{ uint32_t srca = get_ilong_prefetch(2); | |
32520 | if ((srca & 1) != 0) { | |
32521 | last_fault_for_exception_3 = srca; | |
32522 | last_op_for_exception_3 = opcode; | |
32523 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
32524 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
32525 | goto endlabel1939; | |
32526 | } | |
32527 | {{ int32_t src = m68k_read_memory_32(srca); | |
32528 | { uint32_t val = src; | |
32529 | m68k_areg(regs, dstreg) = (val); | |
32530 | }}}}}m68k_incpc(6); | |
32531 | fill_prefetch_0 (); | |
32532 | endlabel1939: ; | |
32533 | return 20; | |
32534 | } | |
32535 | unsigned long CPUFUNC(op_207a_5)(uint32_t opcode) /* MOVEA */ | |
32536 | { | |
32537 | uint32_t dstreg = (opcode >> 9) & 7; | |
32538 | OpcodeFamily = 31; CurrentInstrCycles = 16; | |
32539 | {{ uint32_t srca = m68k_getpc () + 2; | |
32540 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
32541 | if ((srca & 1) != 0) { | |
32542 | last_fault_for_exception_3 = srca; | |
32543 | last_op_for_exception_3 = opcode; | |
32544 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
32545 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
32546 | goto endlabel1940; | |
32547 | } | |
32548 | {{ int32_t src = m68k_read_memory_32(srca); | |
32549 | { uint32_t val = src; | |
32550 | m68k_areg(regs, dstreg) = (val); | |
32551 | }}}}}m68k_incpc(4); | |
32552 | fill_prefetch_0 (); | |
32553 | endlabel1940: ; | |
32554 | return 16; | |
32555 | } | |
32556 | unsigned long CPUFUNC(op_207b_5)(uint32_t opcode) /* MOVEA */ | |
32557 | { | |
32558 | uint32_t dstreg = (opcode >> 9) & 7; | |
32559 | OpcodeFamily = 31; CurrentInstrCycles = 18; | |
32560 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
32561 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
32562 | BusCyclePenalty += 2; | |
32563 | if ((srca & 1) != 0) { | |
32564 | last_fault_for_exception_3 = srca; | |
32565 | last_op_for_exception_3 = opcode; | |
32566 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
32567 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
32568 | goto endlabel1941; | |
32569 | } | |
32570 | {{ int32_t src = m68k_read_memory_32(srca); | |
32571 | { uint32_t val = src; | |
32572 | m68k_areg(regs, dstreg) = (val); | |
32573 | }}}}}m68k_incpc(4); | |
32574 | fill_prefetch_0 (); | |
32575 | endlabel1941: ; | |
32576 | return 18; | |
32577 | } | |
32578 | unsigned long CPUFUNC(op_207c_5)(uint32_t opcode) /* MOVEA */ | |
32579 | { | |
32580 | uint32_t dstreg = (opcode >> 9) & 7; | |
32581 | OpcodeFamily = 31; CurrentInstrCycles = 12; | |
32582 | {{ int32_t src = get_ilong_prefetch(2); | |
32583 | { uint32_t val = src; | |
32584 | m68k_areg(regs, dstreg) = (val); | |
32585 | }}}m68k_incpc(6); | |
32586 | fill_prefetch_0 (); | |
32587 | return 12; | |
32588 | } | |
32589 | unsigned long CPUFUNC(op_2080_5)(uint32_t opcode) /* MOVE */ | |
32590 | { | |
32591 | uint32_t srcreg = (opcode & 7); | |
32592 | uint32_t dstreg = (opcode >> 9) & 7; | |
32593 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
32594 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
32595 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
32596 | if ((dsta & 1) != 0) { | |
32597 | last_fault_for_exception_3 = dsta; | |
32598 | last_op_for_exception_3 = opcode; | |
32599 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
32600 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
32601 | goto endlabel1943; | |
32602 | } | |
32603 | { CLEAR_CZNV; | |
32604 | SET_ZFLG (((int32_t)(src)) == 0); | |
32605 | SET_NFLG (((int32_t)(src)) < 0); | |
32606 | m68k_incpc(2); | |
32607 | fill_prefetch_2 (); | |
32608 | m68k_write_memory_32(dsta,src); | |
32609 | }}}}endlabel1943: ; | |
32610 | return 12; | |
32611 | } | |
32612 | unsigned long CPUFUNC(op_2088_5)(uint32_t opcode) /* MOVE */ | |
32613 | { | |
32614 | uint32_t srcreg = (opcode & 7); | |
32615 | uint32_t dstreg = (opcode >> 9) & 7; | |
32616 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
32617 | {{ int32_t src = m68k_areg(regs, srcreg); | |
32618 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
32619 | if ((dsta & 1) != 0) { | |
32620 | last_fault_for_exception_3 = dsta; | |
32621 | last_op_for_exception_3 = opcode; | |
32622 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
32623 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
32624 | goto endlabel1944; | |
32625 | } | |
32626 | { CLEAR_CZNV; | |
32627 | SET_ZFLG (((int32_t)(src)) == 0); | |
32628 | SET_NFLG (((int32_t)(src)) < 0); | |
32629 | m68k_incpc(2); | |
32630 | fill_prefetch_2 (); | |
32631 | m68k_write_memory_32(dsta,src); | |
32632 | }}}}endlabel1944: ; | |
32633 | return 12; | |
32634 | } | |
32635 | unsigned long CPUFUNC(op_2090_5)(uint32_t opcode) /* MOVE */ | |
32636 | { | |
32637 | uint32_t srcreg = (opcode & 7); | |
32638 | uint32_t dstreg = (opcode >> 9) & 7; | |
32639 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
32640 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
32641 | if ((srca & 1) != 0) { | |
32642 | last_fault_for_exception_3 = srca; | |
32643 | last_op_for_exception_3 = opcode; | |
32644 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
32645 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
32646 | goto endlabel1945; | |
32647 | } | |
32648 | {{ int32_t src = m68k_read_memory_32(srca); | |
32649 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
32650 | if ((dsta & 1) != 0) { | |
32651 | last_fault_for_exception_3 = dsta; | |
32652 | last_op_for_exception_3 = opcode; | |
32653 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
32654 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
32655 | goto endlabel1945; | |
32656 | } | |
32657 | { CLEAR_CZNV; | |
32658 | SET_ZFLG (((int32_t)(src)) == 0); | |
32659 | SET_NFLG (((int32_t)(src)) < 0); | |
32660 | m68k_incpc(2); | |
32661 | fill_prefetch_2 (); | |
32662 | m68k_write_memory_32(dsta,src); | |
32663 | }}}}}}endlabel1945: ; | |
32664 | return 20; | |
32665 | } | |
32666 | unsigned long CPUFUNC(op_2098_5)(uint32_t opcode) /* MOVE */ | |
32667 | { | |
32668 | uint32_t srcreg = (opcode & 7); | |
32669 | uint32_t dstreg = (opcode >> 9) & 7; | |
32670 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
32671 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
32672 | if ((srca & 1) != 0) { | |
32673 | last_fault_for_exception_3 = srca; | |
32674 | last_op_for_exception_3 = opcode; | |
32675 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
32676 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
32677 | goto endlabel1946; | |
32678 | } | |
32679 | {{ int32_t src = m68k_read_memory_32(srca); | |
32680 | m68k_areg(regs, srcreg) += 4; | |
32681 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
32682 | if ((dsta & 1) != 0) { | |
32683 | last_fault_for_exception_3 = dsta; | |
32684 | last_op_for_exception_3 = opcode; | |
32685 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
32686 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
32687 | goto endlabel1946; | |
32688 | } | |
32689 | { CLEAR_CZNV; | |
32690 | SET_ZFLG (((int32_t)(src)) == 0); | |
32691 | SET_NFLG (((int32_t)(src)) < 0); | |
32692 | m68k_incpc(2); | |
32693 | fill_prefetch_2 (); | |
32694 | m68k_write_memory_32(dsta,src); | |
32695 | }}}}}}endlabel1946: ; | |
32696 | return 20; | |
32697 | } | |
32698 | unsigned long CPUFUNC(op_20a0_5)(uint32_t opcode) /* MOVE */ | |
32699 | { | |
32700 | uint32_t srcreg = (opcode & 7); | |
32701 | uint32_t dstreg = (opcode >> 9) & 7; | |
32702 | OpcodeFamily = 30; CurrentInstrCycles = 22; | |
32703 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 4; | |
32704 | if ((srca & 1) != 0) { | |
32705 | last_fault_for_exception_3 = srca; | |
32706 | last_op_for_exception_3 = opcode; | |
32707 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
32708 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
32709 | goto endlabel1947; | |
32710 | } | |
32711 | {{ int32_t src = m68k_read_memory_32(srca); | |
32712 | m68k_areg (regs, srcreg) = srca; | |
32713 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
32714 | if ((dsta & 1) != 0) { | |
32715 | last_fault_for_exception_3 = dsta; | |
32716 | last_op_for_exception_3 = opcode; | |
32717 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
32718 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
32719 | goto endlabel1947; | |
32720 | } | |
32721 | { CLEAR_CZNV; | |
32722 | SET_ZFLG (((int32_t)(src)) == 0); | |
32723 | SET_NFLG (((int32_t)(src)) < 0); | |
32724 | m68k_incpc(2); | |
32725 | fill_prefetch_2 (); | |
32726 | m68k_write_memory_32(dsta,src); | |
32727 | }}}}}}endlabel1947: ; | |
32728 | return 22; | |
32729 | } | |
32730 | unsigned long CPUFUNC(op_20a8_5)(uint32_t opcode) /* MOVE */ | |
32731 | { | |
32732 | uint32_t srcreg = (opcode & 7); | |
32733 | uint32_t dstreg = (opcode >> 9) & 7; | |
32734 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
32735 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
32736 | if ((srca & 1) != 0) { | |
32737 | last_fault_for_exception_3 = srca; | |
32738 | last_op_for_exception_3 = opcode; | |
32739 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
32740 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
32741 | goto endlabel1948; | |
32742 | } | |
32743 | {{ int32_t src = m68k_read_memory_32(srca); | |
32744 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
32745 | if ((dsta & 1) != 0) { | |
32746 | last_fault_for_exception_3 = dsta; | |
32747 | last_op_for_exception_3 = opcode; | |
32748 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
32749 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
32750 | goto endlabel1948; | |
32751 | } | |
32752 | { CLEAR_CZNV; | |
32753 | SET_ZFLG (((int32_t)(src)) == 0); | |
32754 | SET_NFLG (((int32_t)(src)) < 0); | |
32755 | m68k_incpc(4); | |
32756 | fill_prefetch_0 (); | |
32757 | m68k_write_memory_32(dsta,src); | |
32758 | }}}}}}endlabel1948: ; | |
32759 | return 24; | |
32760 | } | |
32761 | unsigned long CPUFUNC(op_20b0_5)(uint32_t opcode) /* MOVE */ | |
32762 | { | |
32763 | uint32_t srcreg = (opcode & 7); | |
32764 | uint32_t dstreg = (opcode >> 9) & 7; | |
32765 | OpcodeFamily = 30; CurrentInstrCycles = 26; | |
32766 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
32767 | BusCyclePenalty += 2; | |
32768 | if ((srca & 1) != 0) { | |
32769 | last_fault_for_exception_3 = srca; | |
32770 | last_op_for_exception_3 = opcode; | |
32771 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
32772 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
32773 | goto endlabel1949; | |
32774 | } | |
32775 | {{ int32_t src = m68k_read_memory_32(srca); | |
32776 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
32777 | if ((dsta & 1) != 0) { | |
32778 | last_fault_for_exception_3 = dsta; | |
32779 | last_op_for_exception_3 = opcode; | |
32780 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
32781 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
32782 | goto endlabel1949; | |
32783 | } | |
32784 | { CLEAR_CZNV; | |
32785 | SET_ZFLG (((int32_t)(src)) == 0); | |
32786 | SET_NFLG (((int32_t)(src)) < 0); | |
32787 | m68k_incpc(4); | |
32788 | fill_prefetch_0 (); | |
32789 | m68k_write_memory_32(dsta,src); | |
32790 | }}}}}}endlabel1949: ; | |
32791 | return 26; | |
32792 | } | |
32793 | unsigned long CPUFUNC(op_20b8_5)(uint32_t opcode) /* MOVE */ | |
32794 | { | |
32795 | uint32_t dstreg = (opcode >> 9) & 7; | |
32796 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
32797 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
32798 | if ((srca & 1) != 0) { | |
32799 | last_fault_for_exception_3 = srca; | |
32800 | last_op_for_exception_3 = opcode; | |
32801 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
32802 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
32803 | goto endlabel1950; | |
32804 | } | |
32805 | {{ int32_t src = m68k_read_memory_32(srca); | |
32806 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
32807 | if ((dsta & 1) != 0) { | |
32808 | last_fault_for_exception_3 = dsta; | |
32809 | last_op_for_exception_3 = opcode; | |
32810 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
32811 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
32812 | goto endlabel1950; | |
32813 | } | |
32814 | { CLEAR_CZNV; | |
32815 | SET_ZFLG (((int32_t)(src)) == 0); | |
32816 | SET_NFLG (((int32_t)(src)) < 0); | |
32817 | m68k_incpc(4); | |
32818 | fill_prefetch_0 (); | |
32819 | m68k_write_memory_32(dsta,src); | |
32820 | }}}}}}endlabel1950: ; | |
32821 | return 24; | |
32822 | } | |
32823 | unsigned long CPUFUNC(op_20b9_5)(uint32_t opcode) /* MOVE */ | |
32824 | { | |
32825 | uint32_t dstreg = (opcode >> 9) & 7; | |
32826 | OpcodeFamily = 30; CurrentInstrCycles = 28; | |
32827 | {{ uint32_t srca = get_ilong_prefetch(2); | |
32828 | if ((srca & 1) != 0) { | |
32829 | last_fault_for_exception_3 = srca; | |
32830 | last_op_for_exception_3 = opcode; | |
32831 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
32832 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
32833 | goto endlabel1951; | |
32834 | } | |
32835 | {{ int32_t src = m68k_read_memory_32(srca); | |
32836 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
32837 | if ((dsta & 1) != 0) { | |
32838 | last_fault_for_exception_3 = dsta; | |
32839 | last_op_for_exception_3 = opcode; | |
32840 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
32841 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
32842 | goto endlabel1951; | |
32843 | } | |
32844 | { CLEAR_CZNV; | |
32845 | SET_ZFLG (((int32_t)(src)) == 0); | |
32846 | SET_NFLG (((int32_t)(src)) < 0); | |
32847 | m68k_incpc(6); | |
32848 | fill_prefetch_0 (); | |
32849 | m68k_write_memory_32(dsta,src); | |
32850 | }}}}}}endlabel1951: ; | |
32851 | return 28; | |
32852 | } | |
32853 | unsigned long CPUFUNC(op_20ba_5)(uint32_t opcode) /* MOVE */ | |
32854 | { | |
32855 | uint32_t dstreg = (opcode >> 9) & 7; | |
32856 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
32857 | {{ uint32_t srca = m68k_getpc () + 2; | |
32858 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
32859 | if ((srca & 1) != 0) { | |
32860 | last_fault_for_exception_3 = srca; | |
32861 | last_op_for_exception_3 = opcode; | |
32862 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
32863 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
32864 | goto endlabel1952; | |
32865 | } | |
32866 | {{ int32_t src = m68k_read_memory_32(srca); | |
32867 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
32868 | if ((dsta & 1) != 0) { | |
32869 | last_fault_for_exception_3 = dsta; | |
32870 | last_op_for_exception_3 = opcode; | |
32871 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
32872 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
32873 | goto endlabel1952; | |
32874 | } | |
32875 | { CLEAR_CZNV; | |
32876 | SET_ZFLG (((int32_t)(src)) == 0); | |
32877 | SET_NFLG (((int32_t)(src)) < 0); | |
32878 | m68k_incpc(4); | |
32879 | fill_prefetch_0 (); | |
32880 | m68k_write_memory_32(dsta,src); | |
32881 | }}}}}}endlabel1952: ; | |
32882 | return 24; | |
32883 | } | |
32884 | unsigned long CPUFUNC(op_20bb_5)(uint32_t opcode) /* MOVE */ | |
32885 | { | |
32886 | uint32_t dstreg = (opcode >> 9) & 7; | |
32887 | OpcodeFamily = 30; CurrentInstrCycles = 26; | |
32888 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
32889 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
32890 | BusCyclePenalty += 2; | |
32891 | if ((srca & 1) != 0) { | |
32892 | last_fault_for_exception_3 = srca; | |
32893 | last_op_for_exception_3 = opcode; | |
32894 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
32895 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
32896 | goto endlabel1953; | |
32897 | } | |
32898 | {{ int32_t src = m68k_read_memory_32(srca); | |
32899 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
32900 | if ((dsta & 1) != 0) { | |
32901 | last_fault_for_exception_3 = dsta; | |
32902 | last_op_for_exception_3 = opcode; | |
32903 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
32904 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
32905 | goto endlabel1953; | |
32906 | } | |
32907 | { CLEAR_CZNV; | |
32908 | SET_ZFLG (((int32_t)(src)) == 0); | |
32909 | SET_NFLG (((int32_t)(src)) < 0); | |
32910 | m68k_incpc(4); | |
32911 | fill_prefetch_0 (); | |
32912 | m68k_write_memory_32(dsta,src); | |
32913 | }}}}}}endlabel1953: ; | |
32914 | return 26; | |
32915 | } | |
32916 | unsigned long CPUFUNC(op_20bc_5)(uint32_t opcode) /* MOVE */ | |
32917 | { | |
32918 | uint32_t dstreg = (opcode >> 9) & 7; | |
32919 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
32920 | {{ int32_t src = get_ilong_prefetch(2); | |
32921 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
32922 | if ((dsta & 1) != 0) { | |
32923 | last_fault_for_exception_3 = dsta; | |
32924 | last_op_for_exception_3 = opcode; | |
32925 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
32926 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
32927 | goto endlabel1954; | |
32928 | } | |
32929 | { CLEAR_CZNV; | |
32930 | SET_ZFLG (((int32_t)(src)) == 0); | |
32931 | SET_NFLG (((int32_t)(src)) < 0); | |
32932 | m68k_incpc(6); | |
32933 | fill_prefetch_0 (); | |
32934 | m68k_write_memory_32(dsta,src); | |
32935 | }}}}endlabel1954: ; | |
32936 | return 20; | |
32937 | } | |
32938 | unsigned long CPUFUNC(op_20c0_5)(uint32_t opcode) /* MOVE */ | |
32939 | { | |
32940 | uint32_t srcreg = (opcode & 7); | |
32941 | uint32_t dstreg = (opcode >> 9) & 7; | |
32942 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
32943 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
32944 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
32945 | if ((dsta & 1) != 0) { | |
32946 | last_fault_for_exception_3 = dsta; | |
32947 | last_op_for_exception_3 = opcode; | |
32948 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
32949 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
32950 | goto endlabel1955; | |
32951 | } | |
32952 | { m68k_areg(regs, dstreg) += 4; | |
32953 | CLEAR_CZNV; | |
32954 | SET_ZFLG (((int32_t)(src)) == 0); | |
32955 | SET_NFLG (((int32_t)(src)) < 0); | |
32956 | m68k_incpc(2); | |
32957 | fill_prefetch_2 (); | |
32958 | m68k_write_memory_32(dsta,src); | |
32959 | }}}}endlabel1955: ; | |
32960 | return 12; | |
32961 | } | |
32962 | unsigned long CPUFUNC(op_20c8_5)(uint32_t opcode) /* MOVE */ | |
32963 | { | |
32964 | uint32_t srcreg = (opcode & 7); | |
32965 | uint32_t dstreg = (opcode >> 9) & 7; | |
32966 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
32967 | {{ int32_t src = m68k_areg(regs, srcreg); | |
32968 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
32969 | if ((dsta & 1) != 0) { | |
32970 | last_fault_for_exception_3 = dsta; | |
32971 | last_op_for_exception_3 = opcode; | |
32972 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
32973 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
32974 | goto endlabel1956; | |
32975 | } | |
32976 | { m68k_areg(regs, dstreg) += 4; | |
32977 | CLEAR_CZNV; | |
32978 | SET_ZFLG (((int32_t)(src)) == 0); | |
32979 | SET_NFLG (((int32_t)(src)) < 0); | |
32980 | m68k_incpc(2); | |
32981 | fill_prefetch_2 (); | |
32982 | m68k_write_memory_32(dsta,src); | |
32983 | }}}}endlabel1956: ; | |
32984 | return 12; | |
32985 | } | |
32986 | unsigned long CPUFUNC(op_20d0_5)(uint32_t opcode) /* MOVE */ | |
32987 | { | |
32988 | uint32_t srcreg = (opcode & 7); | |
32989 | uint32_t dstreg = (opcode >> 9) & 7; | |
32990 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
32991 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
32992 | if ((srca & 1) != 0) { | |
32993 | last_fault_for_exception_3 = srca; | |
32994 | last_op_for_exception_3 = opcode; | |
32995 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
32996 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
32997 | goto endlabel1957; | |
32998 | } | |
32999 | {{ int32_t src = m68k_read_memory_32(srca); | |
33000 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
33001 | if ((dsta & 1) != 0) { | |
33002 | last_fault_for_exception_3 = dsta; | |
33003 | last_op_for_exception_3 = opcode; | |
33004 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
33005 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33006 | goto endlabel1957; | |
33007 | } | |
33008 | { m68k_areg(regs, dstreg) += 4; | |
33009 | CLEAR_CZNV; | |
33010 | SET_ZFLG (((int32_t)(src)) == 0); | |
33011 | SET_NFLG (((int32_t)(src)) < 0); | |
33012 | m68k_incpc(2); | |
33013 | fill_prefetch_2 (); | |
33014 | m68k_write_memory_32(dsta,src); | |
33015 | }}}}}}endlabel1957: ; | |
33016 | return 20; | |
33017 | } | |
33018 | unsigned long CPUFUNC(op_20d8_5)(uint32_t opcode) /* MOVE */ | |
33019 | { | |
33020 | uint32_t srcreg = (opcode & 7); | |
33021 | uint32_t dstreg = (opcode >> 9) & 7; | |
33022 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
33023 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
33024 | if ((srca & 1) != 0) { | |
33025 | last_fault_for_exception_3 = srca; | |
33026 | last_op_for_exception_3 = opcode; | |
33027 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
33028 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33029 | goto endlabel1958; | |
33030 | } | |
33031 | {{ int32_t src = m68k_read_memory_32(srca); | |
33032 | m68k_areg(regs, srcreg) += 4; | |
33033 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
33034 | if ((dsta & 1) != 0) { | |
33035 | last_fault_for_exception_3 = dsta; | |
33036 | last_op_for_exception_3 = opcode; | |
33037 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
33038 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33039 | goto endlabel1958; | |
33040 | } | |
33041 | { m68k_areg(regs, dstreg) += 4; | |
33042 | CLEAR_CZNV; | |
33043 | SET_ZFLG (((int32_t)(src)) == 0); | |
33044 | SET_NFLG (((int32_t)(src)) < 0); | |
33045 | m68k_incpc(2); | |
33046 | fill_prefetch_2 (); | |
33047 | m68k_write_memory_32(dsta,src); | |
33048 | }}}}}}endlabel1958: ; | |
33049 | return 20; | |
33050 | } | |
33051 | unsigned long CPUFUNC(op_20e0_5)(uint32_t opcode) /* MOVE */ | |
33052 | { | |
33053 | uint32_t srcreg = (opcode & 7); | |
33054 | uint32_t dstreg = (opcode >> 9) & 7; | |
33055 | OpcodeFamily = 30; CurrentInstrCycles = 22; | |
33056 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 4; | |
33057 | if ((srca & 1) != 0) { | |
33058 | last_fault_for_exception_3 = srca; | |
33059 | last_op_for_exception_3 = opcode; | |
33060 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
33061 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33062 | goto endlabel1959; | |
33063 | } | |
33064 | {{ int32_t src = m68k_read_memory_32(srca); | |
33065 | m68k_areg (regs, srcreg) = srca; | |
33066 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
33067 | if ((dsta & 1) != 0) { | |
33068 | last_fault_for_exception_3 = dsta; | |
33069 | last_op_for_exception_3 = opcode; | |
33070 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
33071 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33072 | goto endlabel1959; | |
33073 | } | |
33074 | { m68k_areg(regs, dstreg) += 4; | |
33075 | CLEAR_CZNV; | |
33076 | SET_ZFLG (((int32_t)(src)) == 0); | |
33077 | SET_NFLG (((int32_t)(src)) < 0); | |
33078 | m68k_incpc(2); | |
33079 | fill_prefetch_2 (); | |
33080 | m68k_write_memory_32(dsta,src); | |
33081 | }}}}}}endlabel1959: ; | |
33082 | return 22; | |
33083 | } | |
33084 | unsigned long CPUFUNC(op_20e8_5)(uint32_t opcode) /* MOVE */ | |
33085 | { | |
33086 | uint32_t srcreg = (opcode & 7); | |
33087 | uint32_t dstreg = (opcode >> 9) & 7; | |
33088 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
33089 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
33090 | if ((srca & 1) != 0) { | |
33091 | last_fault_for_exception_3 = srca; | |
33092 | last_op_for_exception_3 = opcode; | |
33093 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
33094 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33095 | goto endlabel1960; | |
33096 | } | |
33097 | {{ int32_t src = m68k_read_memory_32(srca); | |
33098 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
33099 | if ((dsta & 1) != 0) { | |
33100 | last_fault_for_exception_3 = dsta; | |
33101 | last_op_for_exception_3 = opcode; | |
33102 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
33103 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33104 | goto endlabel1960; | |
33105 | } | |
33106 | { m68k_areg(regs, dstreg) += 4; | |
33107 | CLEAR_CZNV; | |
33108 | SET_ZFLG (((int32_t)(src)) == 0); | |
33109 | SET_NFLG (((int32_t)(src)) < 0); | |
33110 | m68k_incpc(4); | |
33111 | fill_prefetch_0 (); | |
33112 | m68k_write_memory_32(dsta,src); | |
33113 | }}}}}}endlabel1960: ; | |
33114 | return 24; | |
33115 | } | |
33116 | unsigned long CPUFUNC(op_20f0_5)(uint32_t opcode) /* MOVE */ | |
33117 | { | |
33118 | uint32_t srcreg = (opcode & 7); | |
33119 | uint32_t dstreg = (opcode >> 9) & 7; | |
33120 | OpcodeFamily = 30; CurrentInstrCycles = 26; | |
33121 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
33122 | BusCyclePenalty += 2; | |
33123 | if ((srca & 1) != 0) { | |
33124 | last_fault_for_exception_3 = srca; | |
33125 | last_op_for_exception_3 = opcode; | |
33126 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
33127 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33128 | goto endlabel1961; | |
33129 | } | |
33130 | {{ int32_t src = m68k_read_memory_32(srca); | |
33131 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
33132 | if ((dsta & 1) != 0) { | |
33133 | last_fault_for_exception_3 = dsta; | |
33134 | last_op_for_exception_3 = opcode; | |
33135 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
33136 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33137 | goto endlabel1961; | |
33138 | } | |
33139 | { m68k_areg(regs, dstreg) += 4; | |
33140 | CLEAR_CZNV; | |
33141 | SET_ZFLG (((int32_t)(src)) == 0); | |
33142 | SET_NFLG (((int32_t)(src)) < 0); | |
33143 | m68k_incpc(4); | |
33144 | fill_prefetch_0 (); | |
33145 | m68k_write_memory_32(dsta,src); | |
33146 | }}}}}}endlabel1961: ; | |
33147 | return 26; | |
33148 | } | |
33149 | unsigned long CPUFUNC(op_20f8_5)(uint32_t opcode) /* MOVE */ | |
33150 | { | |
33151 | uint32_t dstreg = (opcode >> 9) & 7; | |
33152 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
33153 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
33154 | if ((srca & 1) != 0) { | |
33155 | last_fault_for_exception_3 = srca; | |
33156 | last_op_for_exception_3 = opcode; | |
33157 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
33158 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33159 | goto endlabel1962; | |
33160 | } | |
33161 | {{ int32_t src = m68k_read_memory_32(srca); | |
33162 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
33163 | if ((dsta & 1) != 0) { | |
33164 | last_fault_for_exception_3 = dsta; | |
33165 | last_op_for_exception_3 = opcode; | |
33166 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
33167 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33168 | goto endlabel1962; | |
33169 | } | |
33170 | { m68k_areg(regs, dstreg) += 4; | |
33171 | CLEAR_CZNV; | |
33172 | SET_ZFLG (((int32_t)(src)) == 0); | |
33173 | SET_NFLG (((int32_t)(src)) < 0); | |
33174 | m68k_incpc(4); | |
33175 | fill_prefetch_0 (); | |
33176 | m68k_write_memory_32(dsta,src); | |
33177 | }}}}}}endlabel1962: ; | |
33178 | return 24; | |
33179 | } | |
33180 | unsigned long CPUFUNC(op_20f9_5)(uint32_t opcode) /* MOVE */ | |
33181 | { | |
33182 | uint32_t dstreg = (opcode >> 9) & 7; | |
33183 | OpcodeFamily = 30; CurrentInstrCycles = 28; | |
33184 | {{ uint32_t srca = get_ilong_prefetch(2); | |
33185 | if ((srca & 1) != 0) { | |
33186 | last_fault_for_exception_3 = srca; | |
33187 | last_op_for_exception_3 = opcode; | |
33188 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
33189 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33190 | goto endlabel1963; | |
33191 | } | |
33192 | {{ int32_t src = m68k_read_memory_32(srca); | |
33193 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
33194 | if ((dsta & 1) != 0) { | |
33195 | last_fault_for_exception_3 = dsta; | |
33196 | last_op_for_exception_3 = opcode; | |
33197 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
33198 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33199 | goto endlabel1963; | |
33200 | } | |
33201 | { m68k_areg(regs, dstreg) += 4; | |
33202 | CLEAR_CZNV; | |
33203 | SET_ZFLG (((int32_t)(src)) == 0); | |
33204 | SET_NFLG (((int32_t)(src)) < 0); | |
33205 | m68k_incpc(6); | |
33206 | fill_prefetch_0 (); | |
33207 | m68k_write_memory_32(dsta,src); | |
33208 | }}}}}}endlabel1963: ; | |
33209 | return 28; | |
33210 | } | |
33211 | unsigned long CPUFUNC(op_20fa_5)(uint32_t opcode) /* MOVE */ | |
33212 | { | |
33213 | uint32_t dstreg = (opcode >> 9) & 7; | |
33214 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
33215 | {{ uint32_t srca = m68k_getpc () + 2; | |
33216 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
33217 | if ((srca & 1) != 0) { | |
33218 | last_fault_for_exception_3 = srca; | |
33219 | last_op_for_exception_3 = opcode; | |
33220 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
33221 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33222 | goto endlabel1964; | |
33223 | } | |
33224 | {{ int32_t src = m68k_read_memory_32(srca); | |
33225 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
33226 | if ((dsta & 1) != 0) { | |
33227 | last_fault_for_exception_3 = dsta; | |
33228 | last_op_for_exception_3 = opcode; | |
33229 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
33230 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33231 | goto endlabel1964; | |
33232 | } | |
33233 | { m68k_areg(regs, dstreg) += 4; | |
33234 | CLEAR_CZNV; | |
33235 | SET_ZFLG (((int32_t)(src)) == 0); | |
33236 | SET_NFLG (((int32_t)(src)) < 0); | |
33237 | m68k_incpc(4); | |
33238 | fill_prefetch_0 (); | |
33239 | m68k_write_memory_32(dsta,src); | |
33240 | }}}}}}endlabel1964: ; | |
33241 | return 24; | |
33242 | } | |
33243 | unsigned long CPUFUNC(op_20fb_5)(uint32_t opcode) /* MOVE */ | |
33244 | { | |
33245 | uint32_t dstreg = (opcode >> 9) & 7; | |
33246 | OpcodeFamily = 30; CurrentInstrCycles = 26; | |
33247 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
33248 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
33249 | BusCyclePenalty += 2; | |
33250 | if ((srca & 1) != 0) { | |
33251 | last_fault_for_exception_3 = srca; | |
33252 | last_op_for_exception_3 = opcode; | |
33253 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
33254 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33255 | goto endlabel1965; | |
33256 | } | |
33257 | {{ int32_t src = m68k_read_memory_32(srca); | |
33258 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
33259 | if ((dsta & 1) != 0) { | |
33260 | last_fault_for_exception_3 = dsta; | |
33261 | last_op_for_exception_3 = opcode; | |
33262 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
33263 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33264 | goto endlabel1965; | |
33265 | } | |
33266 | { m68k_areg(regs, dstreg) += 4; | |
33267 | CLEAR_CZNV; | |
33268 | SET_ZFLG (((int32_t)(src)) == 0); | |
33269 | SET_NFLG (((int32_t)(src)) < 0); | |
33270 | m68k_incpc(4); | |
33271 | fill_prefetch_0 (); | |
33272 | m68k_write_memory_32(dsta,src); | |
33273 | }}}}}}endlabel1965: ; | |
33274 | return 26; | |
33275 | } | |
33276 | unsigned long CPUFUNC(op_20fc_5)(uint32_t opcode) /* MOVE */ | |
33277 | { | |
33278 | uint32_t dstreg = (opcode >> 9) & 7; | |
33279 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
33280 | {{ int32_t src = get_ilong_prefetch(2); | |
33281 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
33282 | if ((dsta & 1) != 0) { | |
33283 | last_fault_for_exception_3 = dsta; | |
33284 | last_op_for_exception_3 = opcode; | |
33285 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
33286 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33287 | goto endlabel1966; | |
33288 | } | |
33289 | { m68k_areg(regs, dstreg) += 4; | |
33290 | CLEAR_CZNV; | |
33291 | SET_ZFLG (((int32_t)(src)) == 0); | |
33292 | SET_NFLG (((int32_t)(src)) < 0); | |
33293 | m68k_incpc(6); | |
33294 | fill_prefetch_0 (); | |
33295 | m68k_write_memory_32(dsta,src); | |
33296 | }}}}endlabel1966: ; | |
33297 | return 20; | |
33298 | } | |
33299 | unsigned long CPUFUNC(op_2100_5)(uint32_t opcode) /* MOVE */ | |
33300 | { | |
33301 | uint32_t srcreg = (opcode & 7); | |
33302 | uint32_t dstreg = (opcode >> 9) & 7; | |
33303 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
33304 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
33305 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
33306 | if ((dsta & 1) != 0) { | |
33307 | last_fault_for_exception_3 = dsta; | |
33308 | last_op_for_exception_3 = opcode; | |
33309 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
33310 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33311 | goto endlabel1967; | |
33312 | } | |
33313 | { m68k_areg (regs, dstreg) = dsta; | |
33314 | CLEAR_CZNV; | |
33315 | SET_ZFLG (((int32_t)(src)) == 0); | |
33316 | SET_NFLG (((int32_t)(src)) < 0); | |
33317 | m68k_incpc(2); | |
33318 | fill_prefetch_2 (); | |
33319 | m68k_write_memory_32(dsta,src); | |
33320 | }}}}endlabel1967: ; | |
33321 | return 12; | |
33322 | } | |
33323 | unsigned long CPUFUNC(op_2108_5)(uint32_t opcode) /* MOVE */ | |
33324 | { | |
33325 | uint32_t srcreg = (opcode & 7); | |
33326 | uint32_t dstreg = (opcode >> 9) & 7; | |
33327 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
33328 | {{ int32_t src = m68k_areg(regs, srcreg); | |
33329 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
33330 | if ((dsta & 1) != 0) { | |
33331 | last_fault_for_exception_3 = dsta; | |
33332 | last_op_for_exception_3 = opcode; | |
33333 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
33334 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33335 | goto endlabel1968; | |
33336 | } | |
33337 | { m68k_areg (regs, dstreg) = dsta; | |
33338 | CLEAR_CZNV; | |
33339 | SET_ZFLG (((int32_t)(src)) == 0); | |
33340 | SET_NFLG (((int32_t)(src)) < 0); | |
33341 | m68k_incpc(2); | |
33342 | fill_prefetch_2 (); | |
33343 | m68k_write_memory_32(dsta,src); | |
33344 | }}}}endlabel1968: ; | |
33345 | return 12; | |
33346 | } | |
33347 | unsigned long CPUFUNC(op_2110_5)(uint32_t opcode) /* MOVE */ | |
33348 | { | |
33349 | uint32_t srcreg = (opcode & 7); | |
33350 | uint32_t dstreg = (opcode >> 9) & 7; | |
33351 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
33352 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
33353 | if ((srca & 1) != 0) { | |
33354 | last_fault_for_exception_3 = srca; | |
33355 | last_op_for_exception_3 = opcode; | |
33356 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
33357 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33358 | goto endlabel1969; | |
33359 | } | |
33360 | {{ int32_t src = m68k_read_memory_32(srca); | |
33361 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
33362 | if ((dsta & 1) != 0) { | |
33363 | last_fault_for_exception_3 = dsta; | |
33364 | last_op_for_exception_3 = opcode; | |
33365 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
33366 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33367 | goto endlabel1969; | |
33368 | } | |
33369 | { m68k_areg (regs, dstreg) = dsta; | |
33370 | CLEAR_CZNV; | |
33371 | SET_ZFLG (((int32_t)(src)) == 0); | |
33372 | SET_NFLG (((int32_t)(src)) < 0); | |
33373 | m68k_incpc(2); | |
33374 | fill_prefetch_2 (); | |
33375 | m68k_write_memory_32(dsta,src); | |
33376 | }}}}}}endlabel1969: ; | |
33377 | return 20; | |
33378 | } | |
33379 | unsigned long CPUFUNC(op_2118_5)(uint32_t opcode) /* MOVE */ | |
33380 | { | |
33381 | uint32_t srcreg = (opcode & 7); | |
33382 | uint32_t dstreg = (opcode >> 9) & 7; | |
33383 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
33384 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
33385 | if ((srca & 1) != 0) { | |
33386 | last_fault_for_exception_3 = srca; | |
33387 | last_op_for_exception_3 = opcode; | |
33388 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
33389 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33390 | goto endlabel1970; | |
33391 | } | |
33392 | {{ int32_t src = m68k_read_memory_32(srca); | |
33393 | m68k_areg(regs, srcreg) += 4; | |
33394 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
33395 | if ((dsta & 1) != 0) { | |
33396 | last_fault_for_exception_3 = dsta; | |
33397 | last_op_for_exception_3 = opcode; | |
33398 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
33399 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33400 | goto endlabel1970; | |
33401 | } | |
33402 | { m68k_areg (regs, dstreg) = dsta; | |
33403 | CLEAR_CZNV; | |
33404 | SET_ZFLG (((int32_t)(src)) == 0); | |
33405 | SET_NFLG (((int32_t)(src)) < 0); | |
33406 | m68k_incpc(2); | |
33407 | fill_prefetch_2 (); | |
33408 | m68k_write_memory_32(dsta,src); | |
33409 | }}}}}}endlabel1970: ; | |
33410 | return 20; | |
33411 | } | |
33412 | unsigned long CPUFUNC(op_2120_5)(uint32_t opcode) /* MOVE */ | |
33413 | { | |
33414 | uint32_t srcreg = (opcode & 7); | |
33415 | uint32_t dstreg = (opcode >> 9) & 7; | |
33416 | OpcodeFamily = 30; CurrentInstrCycles = 22; | |
33417 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 4; | |
33418 | if ((srca & 1) != 0) { | |
33419 | last_fault_for_exception_3 = srca; | |
33420 | last_op_for_exception_3 = opcode; | |
33421 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
33422 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33423 | goto endlabel1971; | |
33424 | } | |
33425 | {{ int32_t src = m68k_read_memory_32(srca); | |
33426 | m68k_areg (regs, srcreg) = srca; | |
33427 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
33428 | if ((dsta & 1) != 0) { | |
33429 | last_fault_for_exception_3 = dsta; | |
33430 | last_op_for_exception_3 = opcode; | |
33431 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
33432 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33433 | goto endlabel1971; | |
33434 | } | |
33435 | { m68k_areg (regs, dstreg) = dsta; | |
33436 | CLEAR_CZNV; | |
33437 | SET_ZFLG (((int32_t)(src)) == 0); | |
33438 | SET_NFLG (((int32_t)(src)) < 0); | |
33439 | m68k_incpc(2); | |
33440 | fill_prefetch_2 (); | |
33441 | m68k_write_memory_32(dsta,src); | |
33442 | }}}}}}endlabel1971: ; | |
33443 | return 22; | |
33444 | } | |
33445 | unsigned long CPUFUNC(op_2128_5)(uint32_t opcode) /* MOVE */ | |
33446 | { | |
33447 | uint32_t srcreg = (opcode & 7); | |
33448 | uint32_t dstreg = (opcode >> 9) & 7; | |
33449 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
33450 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
33451 | if ((srca & 1) != 0) { | |
33452 | last_fault_for_exception_3 = srca; | |
33453 | last_op_for_exception_3 = opcode; | |
33454 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
33455 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33456 | goto endlabel1972; | |
33457 | } | |
33458 | {{ int32_t src = m68k_read_memory_32(srca); | |
33459 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
33460 | if ((dsta & 1) != 0) { | |
33461 | last_fault_for_exception_3 = dsta; | |
33462 | last_op_for_exception_3 = opcode; | |
33463 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
33464 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33465 | goto endlabel1972; | |
33466 | } | |
33467 | { m68k_areg (regs, dstreg) = dsta; | |
33468 | CLEAR_CZNV; | |
33469 | SET_ZFLG (((int32_t)(src)) == 0); | |
33470 | SET_NFLG (((int32_t)(src)) < 0); | |
33471 | m68k_incpc(4); | |
33472 | fill_prefetch_0 (); | |
33473 | m68k_write_memory_32(dsta,src); | |
33474 | }}}}}}endlabel1972: ; | |
33475 | return 24; | |
33476 | } | |
33477 | unsigned long CPUFUNC(op_2130_5)(uint32_t opcode) /* MOVE */ | |
33478 | { | |
33479 | uint32_t srcreg = (opcode & 7); | |
33480 | uint32_t dstreg = (opcode >> 9) & 7; | |
33481 | OpcodeFamily = 30; CurrentInstrCycles = 26; | |
33482 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
33483 | BusCyclePenalty += 2; | |
33484 | if ((srca & 1) != 0) { | |
33485 | last_fault_for_exception_3 = srca; | |
33486 | last_op_for_exception_3 = opcode; | |
33487 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
33488 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33489 | goto endlabel1973; | |
33490 | } | |
33491 | {{ int32_t src = m68k_read_memory_32(srca); | |
33492 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
33493 | if ((dsta & 1) != 0) { | |
33494 | last_fault_for_exception_3 = dsta; | |
33495 | last_op_for_exception_3 = opcode; | |
33496 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
33497 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33498 | goto endlabel1973; | |
33499 | } | |
33500 | { m68k_areg (regs, dstreg) = dsta; | |
33501 | CLEAR_CZNV; | |
33502 | SET_ZFLG (((int32_t)(src)) == 0); | |
33503 | SET_NFLG (((int32_t)(src)) < 0); | |
33504 | m68k_incpc(4); | |
33505 | fill_prefetch_0 (); | |
33506 | m68k_write_memory_32(dsta,src); | |
33507 | }}}}}}endlabel1973: ; | |
33508 | return 26; | |
33509 | } | |
33510 | unsigned long CPUFUNC(op_2138_5)(uint32_t opcode) /* MOVE */ | |
33511 | { | |
33512 | uint32_t dstreg = (opcode >> 9) & 7; | |
33513 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
33514 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
33515 | if ((srca & 1) != 0) { | |
33516 | last_fault_for_exception_3 = srca; | |
33517 | last_op_for_exception_3 = opcode; | |
33518 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
33519 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33520 | goto endlabel1974; | |
33521 | } | |
33522 | {{ int32_t src = m68k_read_memory_32(srca); | |
33523 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
33524 | if ((dsta & 1) != 0) { | |
33525 | last_fault_for_exception_3 = dsta; | |
33526 | last_op_for_exception_3 = opcode; | |
33527 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
33528 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33529 | goto endlabel1974; | |
33530 | } | |
33531 | { m68k_areg (regs, dstreg) = dsta; | |
33532 | CLEAR_CZNV; | |
33533 | SET_ZFLG (((int32_t)(src)) == 0); | |
33534 | SET_NFLG (((int32_t)(src)) < 0); | |
33535 | m68k_incpc(4); | |
33536 | fill_prefetch_0 (); | |
33537 | m68k_write_memory_32(dsta,src); | |
33538 | }}}}}}endlabel1974: ; | |
33539 | return 24; | |
33540 | } | |
33541 | #endif | |
33542 | ||
33543 | #ifdef PART_3 | |
33544 | unsigned long CPUFUNC(op_2139_5)(uint32_t opcode) /* MOVE */ | |
33545 | { | |
33546 | uint32_t dstreg = (opcode >> 9) & 7; | |
33547 | OpcodeFamily = 30; CurrentInstrCycles = 28; | |
33548 | {{ uint32_t srca = get_ilong_prefetch(2); | |
33549 | if ((srca & 1) != 0) { | |
33550 | last_fault_for_exception_3 = srca; | |
33551 | last_op_for_exception_3 = opcode; | |
33552 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
33553 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33554 | goto endlabel1975; | |
33555 | } | |
33556 | {{ int32_t src = m68k_read_memory_32(srca); | |
33557 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
33558 | if ((dsta & 1) != 0) { | |
33559 | last_fault_for_exception_3 = dsta; | |
33560 | last_op_for_exception_3 = opcode; | |
33561 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
33562 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33563 | goto endlabel1975; | |
33564 | } | |
33565 | { m68k_areg (regs, dstreg) = dsta; | |
33566 | CLEAR_CZNV; | |
33567 | SET_ZFLG (((int32_t)(src)) == 0); | |
33568 | SET_NFLG (((int32_t)(src)) < 0); | |
33569 | m68k_incpc(6); | |
33570 | fill_prefetch_0 (); | |
33571 | m68k_write_memory_32(dsta,src); | |
33572 | }}}}}}endlabel1975: ; | |
33573 | return 28; | |
33574 | } | |
33575 | unsigned long CPUFUNC(op_213a_5)(uint32_t opcode) /* MOVE */ | |
33576 | { | |
33577 | uint32_t dstreg = (opcode >> 9) & 7; | |
33578 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
33579 | {{ uint32_t srca = m68k_getpc () + 2; | |
33580 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
33581 | if ((srca & 1) != 0) { | |
33582 | last_fault_for_exception_3 = srca; | |
33583 | last_op_for_exception_3 = opcode; | |
33584 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
33585 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33586 | goto endlabel1976; | |
33587 | } | |
33588 | {{ int32_t src = m68k_read_memory_32(srca); | |
33589 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
33590 | if ((dsta & 1) != 0) { | |
33591 | last_fault_for_exception_3 = dsta; | |
33592 | last_op_for_exception_3 = opcode; | |
33593 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
33594 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33595 | goto endlabel1976; | |
33596 | } | |
33597 | { m68k_areg (regs, dstreg) = dsta; | |
33598 | CLEAR_CZNV; | |
33599 | SET_ZFLG (((int32_t)(src)) == 0); | |
33600 | SET_NFLG (((int32_t)(src)) < 0); | |
33601 | m68k_incpc(4); | |
33602 | fill_prefetch_0 (); | |
33603 | m68k_write_memory_32(dsta,src); | |
33604 | }}}}}}endlabel1976: ; | |
33605 | return 24; | |
33606 | } | |
33607 | unsigned long CPUFUNC(op_213b_5)(uint32_t opcode) /* MOVE */ | |
33608 | { | |
33609 | uint32_t dstreg = (opcode >> 9) & 7; | |
33610 | OpcodeFamily = 30; CurrentInstrCycles = 26; | |
33611 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
33612 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
33613 | BusCyclePenalty += 2; | |
33614 | if ((srca & 1) != 0) { | |
33615 | last_fault_for_exception_3 = srca; | |
33616 | last_op_for_exception_3 = opcode; | |
33617 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
33618 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33619 | goto endlabel1977; | |
33620 | } | |
33621 | {{ int32_t src = m68k_read_memory_32(srca); | |
33622 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
33623 | if ((dsta & 1) != 0) { | |
33624 | last_fault_for_exception_3 = dsta; | |
33625 | last_op_for_exception_3 = opcode; | |
33626 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
33627 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33628 | goto endlabel1977; | |
33629 | } | |
33630 | { m68k_areg (regs, dstreg) = dsta; | |
33631 | CLEAR_CZNV; | |
33632 | SET_ZFLG (((int32_t)(src)) == 0); | |
33633 | SET_NFLG (((int32_t)(src)) < 0); | |
33634 | m68k_incpc(4); | |
33635 | fill_prefetch_0 (); | |
33636 | m68k_write_memory_32(dsta,src); | |
33637 | }}}}}}endlabel1977: ; | |
33638 | return 26; | |
33639 | } | |
33640 | unsigned long CPUFUNC(op_213c_5)(uint32_t opcode) /* MOVE */ | |
33641 | { | |
33642 | uint32_t dstreg = (opcode >> 9) & 7; | |
33643 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
33644 | {{ int32_t src = get_ilong_prefetch(2); | |
33645 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
33646 | if ((dsta & 1) != 0) { | |
33647 | last_fault_for_exception_3 = dsta; | |
33648 | last_op_for_exception_3 = opcode; | |
33649 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
33650 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33651 | goto endlabel1978; | |
33652 | } | |
33653 | { m68k_areg (regs, dstreg) = dsta; | |
33654 | CLEAR_CZNV; | |
33655 | SET_ZFLG (((int32_t)(src)) == 0); | |
33656 | SET_NFLG (((int32_t)(src)) < 0); | |
33657 | m68k_incpc(6); | |
33658 | fill_prefetch_0 (); | |
33659 | m68k_write_memory_32(dsta,src); | |
33660 | }}}}endlabel1978: ; | |
33661 | return 20; | |
33662 | } | |
33663 | unsigned long CPUFUNC(op_2140_5)(uint32_t opcode) /* MOVE */ | |
33664 | { | |
33665 | uint32_t srcreg = (opcode & 7); | |
33666 | uint32_t dstreg = (opcode >> 9) & 7; | |
33667 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
33668 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
33669 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
33670 | if ((dsta & 1) != 0) { | |
33671 | last_fault_for_exception_3 = dsta; | |
33672 | last_op_for_exception_3 = opcode; | |
33673 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
33674 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33675 | goto endlabel1979; | |
33676 | } | |
33677 | { CLEAR_CZNV; | |
33678 | SET_ZFLG (((int32_t)(src)) == 0); | |
33679 | SET_NFLG (((int32_t)(src)) < 0); | |
33680 | m68k_incpc(4); | |
33681 | fill_prefetch_0 (); | |
33682 | m68k_write_memory_32(dsta,src); | |
33683 | }}}}endlabel1979: ; | |
33684 | return 16; | |
33685 | } | |
33686 | unsigned long CPUFUNC(op_2148_5)(uint32_t opcode) /* MOVE */ | |
33687 | { | |
33688 | uint32_t srcreg = (opcode & 7); | |
33689 | uint32_t dstreg = (opcode >> 9) & 7; | |
33690 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
33691 | {{ int32_t src = m68k_areg(regs, srcreg); | |
33692 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
33693 | if ((dsta & 1) != 0) { | |
33694 | last_fault_for_exception_3 = dsta; | |
33695 | last_op_for_exception_3 = opcode; | |
33696 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
33697 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33698 | goto endlabel1980; | |
33699 | } | |
33700 | { CLEAR_CZNV; | |
33701 | SET_ZFLG (((int32_t)(src)) == 0); | |
33702 | SET_NFLG (((int32_t)(src)) < 0); | |
33703 | m68k_incpc(4); | |
33704 | fill_prefetch_0 (); | |
33705 | m68k_write_memory_32(dsta,src); | |
33706 | }}}}endlabel1980: ; | |
33707 | return 16; | |
33708 | } | |
33709 | unsigned long CPUFUNC(op_2150_5)(uint32_t opcode) /* MOVE */ | |
33710 | { | |
33711 | uint32_t srcreg = (opcode & 7); | |
33712 | uint32_t dstreg = (opcode >> 9) & 7; | |
33713 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
33714 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
33715 | if ((srca & 1) != 0) { | |
33716 | last_fault_for_exception_3 = srca; | |
33717 | last_op_for_exception_3 = opcode; | |
33718 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
33719 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33720 | goto endlabel1981; | |
33721 | } | |
33722 | {{ int32_t src = m68k_read_memory_32(srca); | |
33723 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
33724 | if ((dsta & 1) != 0) { | |
33725 | last_fault_for_exception_3 = dsta; | |
33726 | last_op_for_exception_3 = opcode; | |
33727 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
33728 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33729 | goto endlabel1981; | |
33730 | } | |
33731 | { CLEAR_CZNV; | |
33732 | SET_ZFLG (((int32_t)(src)) == 0); | |
33733 | SET_NFLG (((int32_t)(src)) < 0); | |
33734 | m68k_incpc(4); | |
33735 | fill_prefetch_0 (); | |
33736 | m68k_write_memory_32(dsta,src); | |
33737 | }}}}}}endlabel1981: ; | |
33738 | return 24; | |
33739 | } | |
33740 | unsigned long CPUFUNC(op_2158_5)(uint32_t opcode) /* MOVE */ | |
33741 | { | |
33742 | uint32_t srcreg = (opcode & 7); | |
33743 | uint32_t dstreg = (opcode >> 9) & 7; | |
33744 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
33745 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
33746 | if ((srca & 1) != 0) { | |
33747 | last_fault_for_exception_3 = srca; | |
33748 | last_op_for_exception_3 = opcode; | |
33749 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
33750 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33751 | goto endlabel1982; | |
33752 | } | |
33753 | {{ int32_t src = m68k_read_memory_32(srca); | |
33754 | m68k_areg(regs, srcreg) += 4; | |
33755 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
33756 | if ((dsta & 1) != 0) { | |
33757 | last_fault_for_exception_3 = dsta; | |
33758 | last_op_for_exception_3 = opcode; | |
33759 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
33760 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33761 | goto endlabel1982; | |
33762 | } | |
33763 | { CLEAR_CZNV; | |
33764 | SET_ZFLG (((int32_t)(src)) == 0); | |
33765 | SET_NFLG (((int32_t)(src)) < 0); | |
33766 | m68k_incpc(4); | |
33767 | fill_prefetch_0 (); | |
33768 | m68k_write_memory_32(dsta,src); | |
33769 | }}}}}}endlabel1982: ; | |
33770 | return 24; | |
33771 | } | |
33772 | unsigned long CPUFUNC(op_2160_5)(uint32_t opcode) /* MOVE */ | |
33773 | { | |
33774 | uint32_t srcreg = (opcode & 7); | |
33775 | uint32_t dstreg = (opcode >> 9) & 7; | |
33776 | OpcodeFamily = 30; CurrentInstrCycles = 26; | |
33777 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 4; | |
33778 | if ((srca & 1) != 0) { | |
33779 | last_fault_for_exception_3 = srca; | |
33780 | last_op_for_exception_3 = opcode; | |
33781 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
33782 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33783 | goto endlabel1983; | |
33784 | } | |
33785 | {{ int32_t src = m68k_read_memory_32(srca); | |
33786 | m68k_areg (regs, srcreg) = srca; | |
33787 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
33788 | if ((dsta & 1) != 0) { | |
33789 | last_fault_for_exception_3 = dsta; | |
33790 | last_op_for_exception_3 = opcode; | |
33791 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
33792 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33793 | goto endlabel1983; | |
33794 | } | |
33795 | { CLEAR_CZNV; | |
33796 | SET_ZFLG (((int32_t)(src)) == 0); | |
33797 | SET_NFLG (((int32_t)(src)) < 0); | |
33798 | m68k_incpc(4); | |
33799 | fill_prefetch_0 (); | |
33800 | m68k_write_memory_32(dsta,src); | |
33801 | }}}}}}endlabel1983: ; | |
33802 | return 26; | |
33803 | } | |
33804 | unsigned long CPUFUNC(op_2168_5)(uint32_t opcode) /* MOVE */ | |
33805 | { | |
33806 | uint32_t srcreg = (opcode & 7); | |
33807 | uint32_t dstreg = (opcode >> 9) & 7; | |
33808 | OpcodeFamily = 30; CurrentInstrCycles = 28; | |
33809 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
33810 | if ((srca & 1) != 0) { | |
33811 | last_fault_for_exception_3 = srca; | |
33812 | last_op_for_exception_3 = opcode; | |
33813 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
33814 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33815 | goto endlabel1984; | |
33816 | } | |
33817 | {{ int32_t src = m68k_read_memory_32(srca); | |
33818 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); | |
33819 | if ((dsta & 1) != 0) { | |
33820 | last_fault_for_exception_3 = dsta; | |
33821 | last_op_for_exception_3 = opcode; | |
33822 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
33823 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33824 | goto endlabel1984; | |
33825 | } | |
33826 | { CLEAR_CZNV; | |
33827 | SET_ZFLG (((int32_t)(src)) == 0); | |
33828 | SET_NFLG (((int32_t)(src)) < 0); | |
33829 | m68k_incpc(6); | |
33830 | fill_prefetch_0 (); | |
33831 | m68k_write_memory_32(dsta,src); | |
33832 | }}}}}}endlabel1984: ; | |
33833 | return 28; | |
33834 | } | |
33835 | unsigned long CPUFUNC(op_2170_5)(uint32_t opcode) /* MOVE */ | |
33836 | { | |
33837 | uint32_t srcreg = (opcode & 7); | |
33838 | uint32_t dstreg = (opcode >> 9) & 7; | |
33839 | OpcodeFamily = 30; CurrentInstrCycles = 30; | |
33840 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
33841 | BusCyclePenalty += 2; | |
33842 | if ((srca & 1) != 0) { | |
33843 | last_fault_for_exception_3 = srca; | |
33844 | last_op_for_exception_3 = opcode; | |
33845 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
33846 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33847 | goto endlabel1985; | |
33848 | } | |
33849 | {{ int32_t src = m68k_read_memory_32(srca); | |
33850 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); | |
33851 | if ((dsta & 1) != 0) { | |
33852 | last_fault_for_exception_3 = dsta; | |
33853 | last_op_for_exception_3 = opcode; | |
33854 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
33855 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33856 | goto endlabel1985; | |
33857 | } | |
33858 | { CLEAR_CZNV; | |
33859 | SET_ZFLG (((int32_t)(src)) == 0); | |
33860 | SET_NFLG (((int32_t)(src)) < 0); | |
33861 | m68k_incpc(6); | |
33862 | fill_prefetch_0 (); | |
33863 | m68k_write_memory_32(dsta,src); | |
33864 | }}}}}}endlabel1985: ; | |
33865 | return 30; | |
33866 | } | |
33867 | unsigned long CPUFUNC(op_2178_5)(uint32_t opcode) /* MOVE */ | |
33868 | { | |
33869 | uint32_t dstreg = (opcode >> 9) & 7; | |
33870 | OpcodeFamily = 30; CurrentInstrCycles = 28; | |
33871 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
33872 | if ((srca & 1) != 0) { | |
33873 | last_fault_for_exception_3 = srca; | |
33874 | last_op_for_exception_3 = opcode; | |
33875 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
33876 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33877 | goto endlabel1986; | |
33878 | } | |
33879 | {{ int32_t src = m68k_read_memory_32(srca); | |
33880 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); | |
33881 | if ((dsta & 1) != 0) { | |
33882 | last_fault_for_exception_3 = dsta; | |
33883 | last_op_for_exception_3 = opcode; | |
33884 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
33885 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33886 | goto endlabel1986; | |
33887 | } | |
33888 | { CLEAR_CZNV; | |
33889 | SET_ZFLG (((int32_t)(src)) == 0); | |
33890 | SET_NFLG (((int32_t)(src)) < 0); | |
33891 | m68k_incpc(6); | |
33892 | fill_prefetch_0 (); | |
33893 | m68k_write_memory_32(dsta,src); | |
33894 | }}}}}}endlabel1986: ; | |
33895 | return 28; | |
33896 | } | |
33897 | unsigned long CPUFUNC(op_2179_5)(uint32_t opcode) /* MOVE */ | |
33898 | { | |
33899 | uint32_t dstreg = (opcode >> 9) & 7; | |
33900 | OpcodeFamily = 30; CurrentInstrCycles = 32; | |
33901 | {{ uint32_t srca = get_ilong_prefetch(2); | |
33902 | if ((srca & 1) != 0) { | |
33903 | last_fault_for_exception_3 = srca; | |
33904 | last_op_for_exception_3 = opcode; | |
33905 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
33906 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33907 | goto endlabel1987; | |
33908 | } | |
33909 | {{ int32_t src = m68k_read_memory_32(srca); | |
33910 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(6); | |
33911 | if ((dsta & 1) != 0) { | |
33912 | last_fault_for_exception_3 = dsta; | |
33913 | last_op_for_exception_3 = opcode; | |
33914 | last_addr_for_exception_3 = m68k_getpc() + 8; | |
33915 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33916 | goto endlabel1987; | |
33917 | } | |
33918 | { CLEAR_CZNV; | |
33919 | SET_ZFLG (((int32_t)(src)) == 0); | |
33920 | SET_NFLG (((int32_t)(src)) < 0); | |
33921 | m68k_incpc(8); | |
33922 | fill_prefetch_0 (); | |
33923 | m68k_write_memory_32(dsta,src); | |
33924 | }}}}}}endlabel1987: ; | |
33925 | return 32; | |
33926 | } | |
33927 | unsigned long CPUFUNC(op_217a_5)(uint32_t opcode) /* MOVE */ | |
33928 | { | |
33929 | uint32_t dstreg = (opcode >> 9) & 7; | |
33930 | OpcodeFamily = 30; CurrentInstrCycles = 28; | |
33931 | {{ uint32_t srca = m68k_getpc () + 2; | |
33932 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
33933 | if ((srca & 1) != 0) { | |
33934 | last_fault_for_exception_3 = srca; | |
33935 | last_op_for_exception_3 = opcode; | |
33936 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
33937 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33938 | goto endlabel1988; | |
33939 | } | |
33940 | {{ int32_t src = m68k_read_memory_32(srca); | |
33941 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); | |
33942 | if ((dsta & 1) != 0) { | |
33943 | last_fault_for_exception_3 = dsta; | |
33944 | last_op_for_exception_3 = opcode; | |
33945 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
33946 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33947 | goto endlabel1988; | |
33948 | } | |
33949 | { CLEAR_CZNV; | |
33950 | SET_ZFLG (((int32_t)(src)) == 0); | |
33951 | SET_NFLG (((int32_t)(src)) < 0); | |
33952 | m68k_incpc(6); | |
33953 | fill_prefetch_0 (); | |
33954 | m68k_write_memory_32(dsta,src); | |
33955 | }}}}}}endlabel1988: ; | |
33956 | return 28; | |
33957 | } | |
33958 | unsigned long CPUFUNC(op_217b_5)(uint32_t opcode) /* MOVE */ | |
33959 | { | |
33960 | uint32_t dstreg = (opcode >> 9) & 7; | |
33961 | OpcodeFamily = 30; CurrentInstrCycles = 30; | |
33962 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
33963 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
33964 | BusCyclePenalty += 2; | |
33965 | if ((srca & 1) != 0) { | |
33966 | last_fault_for_exception_3 = srca; | |
33967 | last_op_for_exception_3 = opcode; | |
33968 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
33969 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33970 | goto endlabel1989; | |
33971 | } | |
33972 | {{ int32_t src = m68k_read_memory_32(srca); | |
33973 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); | |
33974 | if ((dsta & 1) != 0) { | |
33975 | last_fault_for_exception_3 = dsta; | |
33976 | last_op_for_exception_3 = opcode; | |
33977 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
33978 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
33979 | goto endlabel1989; | |
33980 | } | |
33981 | { CLEAR_CZNV; | |
33982 | SET_ZFLG (((int32_t)(src)) == 0); | |
33983 | SET_NFLG (((int32_t)(src)) < 0); | |
33984 | m68k_incpc(6); | |
33985 | fill_prefetch_0 (); | |
33986 | m68k_write_memory_32(dsta,src); | |
33987 | }}}}}}endlabel1989: ; | |
33988 | return 30; | |
33989 | } | |
33990 | unsigned long CPUFUNC(op_217c_5)(uint32_t opcode) /* MOVE */ | |
33991 | { | |
33992 | uint32_t dstreg = (opcode >> 9) & 7; | |
33993 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
33994 | {{ int32_t src = get_ilong_prefetch(2); | |
33995 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(6); | |
33996 | if ((dsta & 1) != 0) { | |
33997 | last_fault_for_exception_3 = dsta; | |
33998 | last_op_for_exception_3 = opcode; | |
33999 | last_addr_for_exception_3 = m68k_getpc() + 8; | |
34000 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34001 | goto endlabel1990; | |
34002 | } | |
34003 | { CLEAR_CZNV; | |
34004 | SET_ZFLG (((int32_t)(src)) == 0); | |
34005 | SET_NFLG (((int32_t)(src)) < 0); | |
34006 | m68k_incpc(8); | |
34007 | fill_prefetch_0 (); | |
34008 | m68k_write_memory_32(dsta,src); | |
34009 | }}}}endlabel1990: ; | |
34010 | return 24; | |
34011 | } | |
34012 | unsigned long CPUFUNC(op_2180_5)(uint32_t opcode) /* MOVE */ | |
34013 | { | |
34014 | uint32_t srcreg = (opcode & 7); | |
34015 | uint32_t dstreg = (opcode >> 9) & 7; | |
34016 | OpcodeFamily = 30; CurrentInstrCycles = 18; | |
34017 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
34018 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); | |
34019 | BusCyclePenalty += 2; | |
34020 | if ((dsta & 1) != 0) { | |
34021 | last_fault_for_exception_3 = dsta; | |
34022 | last_op_for_exception_3 = opcode; | |
34023 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
34024 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34025 | goto endlabel1991; | |
34026 | } | |
34027 | { CLEAR_CZNV; | |
34028 | SET_ZFLG (((int32_t)(src)) == 0); | |
34029 | SET_NFLG (((int32_t)(src)) < 0); | |
34030 | m68k_incpc(4); | |
34031 | fill_prefetch_0 (); | |
34032 | m68k_write_memory_32(dsta,src); | |
34033 | }}}}endlabel1991: ; | |
34034 | return 18; | |
34035 | } | |
34036 | unsigned long CPUFUNC(op_2188_5)(uint32_t opcode) /* MOVE */ | |
34037 | { | |
34038 | uint32_t srcreg = (opcode & 7); | |
34039 | uint32_t dstreg = (opcode >> 9) & 7; | |
34040 | OpcodeFamily = 30; CurrentInstrCycles = 18; | |
34041 | {{ int32_t src = m68k_areg(regs, srcreg); | |
34042 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); | |
34043 | BusCyclePenalty += 2; | |
34044 | if ((dsta & 1) != 0) { | |
34045 | last_fault_for_exception_3 = dsta; | |
34046 | last_op_for_exception_3 = opcode; | |
34047 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
34048 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34049 | goto endlabel1992; | |
34050 | } | |
34051 | { CLEAR_CZNV; | |
34052 | SET_ZFLG (((int32_t)(src)) == 0); | |
34053 | SET_NFLG (((int32_t)(src)) < 0); | |
34054 | m68k_incpc(4); | |
34055 | fill_prefetch_0 (); | |
34056 | m68k_write_memory_32(dsta,src); | |
34057 | }}}}endlabel1992: ; | |
34058 | return 18; | |
34059 | } | |
34060 | unsigned long CPUFUNC(op_2190_5)(uint32_t opcode) /* MOVE */ | |
34061 | { | |
34062 | uint32_t srcreg = (opcode & 7); | |
34063 | uint32_t dstreg = (opcode >> 9) & 7; | |
34064 | OpcodeFamily = 30; CurrentInstrCycles = 26; | |
34065 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
34066 | if ((srca & 1) != 0) { | |
34067 | last_fault_for_exception_3 = srca; | |
34068 | last_op_for_exception_3 = opcode; | |
34069 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
34070 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34071 | goto endlabel1993; | |
34072 | } | |
34073 | {{ int32_t src = m68k_read_memory_32(srca); | |
34074 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); | |
34075 | BusCyclePenalty += 2; | |
34076 | if ((dsta & 1) != 0) { | |
34077 | last_fault_for_exception_3 = dsta; | |
34078 | last_op_for_exception_3 = opcode; | |
34079 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
34080 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34081 | goto endlabel1993; | |
34082 | } | |
34083 | { CLEAR_CZNV; | |
34084 | SET_ZFLG (((int32_t)(src)) == 0); | |
34085 | SET_NFLG (((int32_t)(src)) < 0); | |
34086 | m68k_incpc(4); | |
34087 | fill_prefetch_0 (); | |
34088 | m68k_write_memory_32(dsta,src); | |
34089 | }}}}}}endlabel1993: ; | |
34090 | return 26; | |
34091 | } | |
34092 | unsigned long CPUFUNC(op_2198_5)(uint32_t opcode) /* MOVE */ | |
34093 | { | |
34094 | uint32_t srcreg = (opcode & 7); | |
34095 | uint32_t dstreg = (opcode >> 9) & 7; | |
34096 | OpcodeFamily = 30; CurrentInstrCycles = 26; | |
34097 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
34098 | if ((srca & 1) != 0) { | |
34099 | last_fault_for_exception_3 = srca; | |
34100 | last_op_for_exception_3 = opcode; | |
34101 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
34102 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34103 | goto endlabel1994; | |
34104 | } | |
34105 | {{ int32_t src = m68k_read_memory_32(srca); | |
34106 | m68k_areg(regs, srcreg) += 4; | |
34107 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); | |
34108 | BusCyclePenalty += 2; | |
34109 | if ((dsta & 1) != 0) { | |
34110 | last_fault_for_exception_3 = dsta; | |
34111 | last_op_for_exception_3 = opcode; | |
34112 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
34113 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34114 | goto endlabel1994; | |
34115 | } | |
34116 | { CLEAR_CZNV; | |
34117 | SET_ZFLG (((int32_t)(src)) == 0); | |
34118 | SET_NFLG (((int32_t)(src)) < 0); | |
34119 | m68k_incpc(4); | |
34120 | fill_prefetch_0 (); | |
34121 | m68k_write_memory_32(dsta,src); | |
34122 | }}}}}}endlabel1994: ; | |
34123 | return 26; | |
34124 | } | |
34125 | unsigned long CPUFUNC(op_21a0_5)(uint32_t opcode) /* MOVE */ | |
34126 | { | |
34127 | uint32_t srcreg = (opcode & 7); | |
34128 | uint32_t dstreg = (opcode >> 9) & 7; | |
34129 | OpcodeFamily = 30; CurrentInstrCycles = 28; | |
34130 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 4; | |
34131 | if ((srca & 1) != 0) { | |
34132 | last_fault_for_exception_3 = srca; | |
34133 | last_op_for_exception_3 = opcode; | |
34134 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
34135 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34136 | goto endlabel1995; | |
34137 | } | |
34138 | {{ int32_t src = m68k_read_memory_32(srca); | |
34139 | m68k_areg (regs, srcreg) = srca; | |
34140 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); | |
34141 | BusCyclePenalty += 2; | |
34142 | if ((dsta & 1) != 0) { | |
34143 | last_fault_for_exception_3 = dsta; | |
34144 | last_op_for_exception_3 = opcode; | |
34145 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
34146 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34147 | goto endlabel1995; | |
34148 | } | |
34149 | { CLEAR_CZNV; | |
34150 | SET_ZFLG (((int32_t)(src)) == 0); | |
34151 | SET_NFLG (((int32_t)(src)) < 0); | |
34152 | m68k_incpc(4); | |
34153 | fill_prefetch_0 (); | |
34154 | m68k_write_memory_32(dsta,src); | |
34155 | }}}}}}endlabel1995: ; | |
34156 | return 28; | |
34157 | } | |
34158 | unsigned long CPUFUNC(op_21a8_5)(uint32_t opcode) /* MOVE */ | |
34159 | { | |
34160 | uint32_t srcreg = (opcode & 7); | |
34161 | uint32_t dstreg = (opcode >> 9) & 7; | |
34162 | OpcodeFamily = 30; CurrentInstrCycles = 30; | |
34163 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
34164 | if ((srca & 1) != 0) { | |
34165 | last_fault_for_exception_3 = srca; | |
34166 | last_op_for_exception_3 = opcode; | |
34167 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
34168 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34169 | goto endlabel1996; | |
34170 | } | |
34171 | {{ int32_t src = m68k_read_memory_32(srca); | |
34172 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); | |
34173 | BusCyclePenalty += 2; | |
34174 | if ((dsta & 1) != 0) { | |
34175 | last_fault_for_exception_3 = dsta; | |
34176 | last_op_for_exception_3 = opcode; | |
34177 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
34178 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34179 | goto endlabel1996; | |
34180 | } | |
34181 | { CLEAR_CZNV; | |
34182 | SET_ZFLG (((int32_t)(src)) == 0); | |
34183 | SET_NFLG (((int32_t)(src)) < 0); | |
34184 | m68k_incpc(6); | |
34185 | fill_prefetch_0 (); | |
34186 | m68k_write_memory_32(dsta,src); | |
34187 | }}}}}}endlabel1996: ; | |
34188 | return 30; | |
34189 | } | |
34190 | unsigned long CPUFUNC(op_21b0_5)(uint32_t opcode) /* MOVE */ | |
34191 | { | |
34192 | uint32_t srcreg = (opcode & 7); | |
34193 | uint32_t dstreg = (opcode >> 9) & 7; | |
34194 | OpcodeFamily = 30; CurrentInstrCycles = 32; | |
34195 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
34196 | BusCyclePenalty += 2; | |
34197 | if ((srca & 1) != 0) { | |
34198 | last_fault_for_exception_3 = srca; | |
34199 | last_op_for_exception_3 = opcode; | |
34200 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
34201 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34202 | goto endlabel1997; | |
34203 | } | |
34204 | {{ int32_t src = m68k_read_memory_32(srca); | |
34205 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); | |
34206 | BusCyclePenalty += 2; | |
34207 | if ((dsta & 1) != 0) { | |
34208 | last_fault_for_exception_3 = dsta; | |
34209 | last_op_for_exception_3 = opcode; | |
34210 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
34211 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34212 | goto endlabel1997; | |
34213 | } | |
34214 | { CLEAR_CZNV; | |
34215 | SET_ZFLG (((int32_t)(src)) == 0); | |
34216 | SET_NFLG (((int32_t)(src)) < 0); | |
34217 | m68k_incpc(6); | |
34218 | fill_prefetch_0 (); | |
34219 | m68k_write_memory_32(dsta,src); | |
34220 | }}}}}}endlabel1997: ; | |
34221 | return 32; | |
34222 | } | |
34223 | unsigned long CPUFUNC(op_21b8_5)(uint32_t opcode) /* MOVE */ | |
34224 | { | |
34225 | uint32_t dstreg = (opcode >> 9) & 7; | |
34226 | OpcodeFamily = 30; CurrentInstrCycles = 30; | |
34227 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
34228 | if ((srca & 1) != 0) { | |
34229 | last_fault_for_exception_3 = srca; | |
34230 | last_op_for_exception_3 = opcode; | |
34231 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
34232 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34233 | goto endlabel1998; | |
34234 | } | |
34235 | {{ int32_t src = m68k_read_memory_32(srca); | |
34236 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); | |
34237 | BusCyclePenalty += 2; | |
34238 | if ((dsta & 1) != 0) { | |
34239 | last_fault_for_exception_3 = dsta; | |
34240 | last_op_for_exception_3 = opcode; | |
34241 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
34242 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34243 | goto endlabel1998; | |
34244 | } | |
34245 | { CLEAR_CZNV; | |
34246 | SET_ZFLG (((int32_t)(src)) == 0); | |
34247 | SET_NFLG (((int32_t)(src)) < 0); | |
34248 | m68k_incpc(6); | |
34249 | fill_prefetch_0 (); | |
34250 | m68k_write_memory_32(dsta,src); | |
34251 | }}}}}}endlabel1998: ; | |
34252 | return 30; | |
34253 | } | |
34254 | unsigned long CPUFUNC(op_21b9_5)(uint32_t opcode) /* MOVE */ | |
34255 | { | |
34256 | uint32_t dstreg = (opcode >> 9) & 7; | |
34257 | OpcodeFamily = 30; CurrentInstrCycles = 34; | |
34258 | {{ uint32_t srca = get_ilong_prefetch(2); | |
34259 | if ((srca & 1) != 0) { | |
34260 | last_fault_for_exception_3 = srca; | |
34261 | last_op_for_exception_3 = opcode; | |
34262 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
34263 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34264 | goto endlabel1999; | |
34265 | } | |
34266 | {{ int32_t src = m68k_read_memory_32(srca); | |
34267 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(6)); | |
34268 | BusCyclePenalty += 2; | |
34269 | if ((dsta & 1) != 0) { | |
34270 | last_fault_for_exception_3 = dsta; | |
34271 | last_op_for_exception_3 = opcode; | |
34272 | last_addr_for_exception_3 = m68k_getpc() + 8; | |
34273 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34274 | goto endlabel1999; | |
34275 | } | |
34276 | { CLEAR_CZNV; | |
34277 | SET_ZFLG (((int32_t)(src)) == 0); | |
34278 | SET_NFLG (((int32_t)(src)) < 0); | |
34279 | m68k_incpc(8); | |
34280 | fill_prefetch_0 (); | |
34281 | m68k_write_memory_32(dsta,src); | |
34282 | }}}}}}endlabel1999: ; | |
34283 | return 34; | |
34284 | } | |
34285 | unsigned long CPUFUNC(op_21ba_5)(uint32_t opcode) /* MOVE */ | |
34286 | { | |
34287 | uint32_t dstreg = (opcode >> 9) & 7; | |
34288 | OpcodeFamily = 30; CurrentInstrCycles = 30; | |
34289 | {{ uint32_t srca = m68k_getpc () + 2; | |
34290 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
34291 | if ((srca & 1) != 0) { | |
34292 | last_fault_for_exception_3 = srca; | |
34293 | last_op_for_exception_3 = opcode; | |
34294 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
34295 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34296 | goto endlabel2000; | |
34297 | } | |
34298 | {{ int32_t src = m68k_read_memory_32(srca); | |
34299 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); | |
34300 | BusCyclePenalty += 2; | |
34301 | if ((dsta & 1) != 0) { | |
34302 | last_fault_for_exception_3 = dsta; | |
34303 | last_op_for_exception_3 = opcode; | |
34304 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
34305 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34306 | goto endlabel2000; | |
34307 | } | |
34308 | { CLEAR_CZNV; | |
34309 | SET_ZFLG (((int32_t)(src)) == 0); | |
34310 | SET_NFLG (((int32_t)(src)) < 0); | |
34311 | m68k_incpc(6); | |
34312 | fill_prefetch_0 (); | |
34313 | m68k_write_memory_32(dsta,src); | |
34314 | }}}}}}endlabel2000: ; | |
34315 | return 30; | |
34316 | } | |
34317 | unsigned long CPUFUNC(op_21bb_5)(uint32_t opcode) /* MOVE */ | |
34318 | { | |
34319 | uint32_t dstreg = (opcode >> 9) & 7; | |
34320 | OpcodeFamily = 30; CurrentInstrCycles = 32; | |
34321 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
34322 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
34323 | BusCyclePenalty += 2; | |
34324 | if ((srca & 1) != 0) { | |
34325 | last_fault_for_exception_3 = srca; | |
34326 | last_op_for_exception_3 = opcode; | |
34327 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
34328 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34329 | goto endlabel2001; | |
34330 | } | |
34331 | {{ int32_t src = m68k_read_memory_32(srca); | |
34332 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); | |
34333 | BusCyclePenalty += 2; | |
34334 | if ((dsta & 1) != 0) { | |
34335 | last_fault_for_exception_3 = dsta; | |
34336 | last_op_for_exception_3 = opcode; | |
34337 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
34338 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34339 | goto endlabel2001; | |
34340 | } | |
34341 | { CLEAR_CZNV; | |
34342 | SET_ZFLG (((int32_t)(src)) == 0); | |
34343 | SET_NFLG (((int32_t)(src)) < 0); | |
34344 | m68k_incpc(6); | |
34345 | fill_prefetch_0 (); | |
34346 | m68k_write_memory_32(dsta,src); | |
34347 | }}}}}}endlabel2001: ; | |
34348 | return 32; | |
34349 | } | |
34350 | unsigned long CPUFUNC(op_21bc_5)(uint32_t opcode) /* MOVE */ | |
34351 | { | |
34352 | uint32_t dstreg = (opcode >> 9) & 7; | |
34353 | OpcodeFamily = 30; CurrentInstrCycles = 26; | |
34354 | {{ int32_t src = get_ilong_prefetch(2); | |
34355 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(6)); | |
34356 | BusCyclePenalty += 2; | |
34357 | if ((dsta & 1) != 0) { | |
34358 | last_fault_for_exception_3 = dsta; | |
34359 | last_op_for_exception_3 = opcode; | |
34360 | last_addr_for_exception_3 = m68k_getpc() + 8; | |
34361 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34362 | goto endlabel2002; | |
34363 | } | |
34364 | { CLEAR_CZNV; | |
34365 | SET_ZFLG (((int32_t)(src)) == 0); | |
34366 | SET_NFLG (((int32_t)(src)) < 0); | |
34367 | m68k_incpc(8); | |
34368 | fill_prefetch_0 (); | |
34369 | m68k_write_memory_32(dsta,src); | |
34370 | }}}}endlabel2002: ; | |
34371 | return 26; | |
34372 | } | |
34373 | unsigned long CPUFUNC(op_21c0_5)(uint32_t opcode) /* MOVE */ | |
34374 | { | |
34375 | uint32_t srcreg = (opcode & 7); | |
34376 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
34377 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
34378 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); | |
34379 | if ((dsta & 1) != 0) { | |
34380 | last_fault_for_exception_3 = dsta; | |
34381 | last_op_for_exception_3 = opcode; | |
34382 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
34383 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34384 | goto endlabel2003; | |
34385 | } | |
34386 | { CLEAR_CZNV; | |
34387 | SET_ZFLG (((int32_t)(src)) == 0); | |
34388 | SET_NFLG (((int32_t)(src)) < 0); | |
34389 | m68k_incpc(4); | |
34390 | fill_prefetch_0 (); | |
34391 | m68k_write_memory_32(dsta,src); | |
34392 | }}}}endlabel2003: ; | |
34393 | return 16; | |
34394 | } | |
34395 | unsigned long CPUFUNC(op_21c8_5)(uint32_t opcode) /* MOVE */ | |
34396 | { | |
34397 | uint32_t srcreg = (opcode & 7); | |
34398 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
34399 | {{ int32_t src = m68k_areg(regs, srcreg); | |
34400 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); | |
34401 | if ((dsta & 1) != 0) { | |
34402 | last_fault_for_exception_3 = dsta; | |
34403 | last_op_for_exception_3 = opcode; | |
34404 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
34405 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34406 | goto endlabel2004; | |
34407 | } | |
34408 | { CLEAR_CZNV; | |
34409 | SET_ZFLG (((int32_t)(src)) == 0); | |
34410 | SET_NFLG (((int32_t)(src)) < 0); | |
34411 | m68k_incpc(4); | |
34412 | fill_prefetch_0 (); | |
34413 | m68k_write_memory_32(dsta,src); | |
34414 | }}}}endlabel2004: ; | |
34415 | return 16; | |
34416 | } | |
34417 | unsigned long CPUFUNC(op_21d0_5)(uint32_t opcode) /* MOVE */ | |
34418 | { | |
34419 | uint32_t srcreg = (opcode & 7); | |
34420 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
34421 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
34422 | if ((srca & 1) != 0) { | |
34423 | last_fault_for_exception_3 = srca; | |
34424 | last_op_for_exception_3 = opcode; | |
34425 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
34426 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34427 | goto endlabel2005; | |
34428 | } | |
34429 | {{ int32_t src = m68k_read_memory_32(srca); | |
34430 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); | |
34431 | if ((dsta & 1) != 0) { | |
34432 | last_fault_for_exception_3 = dsta; | |
34433 | last_op_for_exception_3 = opcode; | |
34434 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
34435 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34436 | goto endlabel2005; | |
34437 | } | |
34438 | { CLEAR_CZNV; | |
34439 | SET_ZFLG (((int32_t)(src)) == 0); | |
34440 | SET_NFLG (((int32_t)(src)) < 0); | |
34441 | m68k_incpc(4); | |
34442 | fill_prefetch_0 (); | |
34443 | m68k_write_memory_32(dsta,src); | |
34444 | }}}}}}endlabel2005: ; | |
34445 | return 24; | |
34446 | } | |
34447 | unsigned long CPUFUNC(op_21d8_5)(uint32_t opcode) /* MOVE */ | |
34448 | { | |
34449 | uint32_t srcreg = (opcode & 7); | |
34450 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
34451 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
34452 | if ((srca & 1) != 0) { | |
34453 | last_fault_for_exception_3 = srca; | |
34454 | last_op_for_exception_3 = opcode; | |
34455 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
34456 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34457 | goto endlabel2006; | |
34458 | } | |
34459 | {{ int32_t src = m68k_read_memory_32(srca); | |
34460 | m68k_areg(regs, srcreg) += 4; | |
34461 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); | |
34462 | if ((dsta & 1) != 0) { | |
34463 | last_fault_for_exception_3 = dsta; | |
34464 | last_op_for_exception_3 = opcode; | |
34465 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
34466 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34467 | goto endlabel2006; | |
34468 | } | |
34469 | { CLEAR_CZNV; | |
34470 | SET_ZFLG (((int32_t)(src)) == 0); | |
34471 | SET_NFLG (((int32_t)(src)) < 0); | |
34472 | m68k_incpc(4); | |
34473 | fill_prefetch_0 (); | |
34474 | m68k_write_memory_32(dsta,src); | |
34475 | }}}}}}endlabel2006: ; | |
34476 | return 24; | |
34477 | } | |
34478 | unsigned long CPUFUNC(op_21e0_5)(uint32_t opcode) /* MOVE */ | |
34479 | { | |
34480 | uint32_t srcreg = (opcode & 7); | |
34481 | OpcodeFamily = 30; CurrentInstrCycles = 26; | |
34482 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 4; | |
34483 | if ((srca & 1) != 0) { | |
34484 | last_fault_for_exception_3 = srca; | |
34485 | last_op_for_exception_3 = opcode; | |
34486 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
34487 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34488 | goto endlabel2007; | |
34489 | } | |
34490 | {{ int32_t src = m68k_read_memory_32(srca); | |
34491 | m68k_areg (regs, srcreg) = srca; | |
34492 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); | |
34493 | if ((dsta & 1) != 0) { | |
34494 | last_fault_for_exception_3 = dsta; | |
34495 | last_op_for_exception_3 = opcode; | |
34496 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
34497 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34498 | goto endlabel2007; | |
34499 | } | |
34500 | { CLEAR_CZNV; | |
34501 | SET_ZFLG (((int32_t)(src)) == 0); | |
34502 | SET_NFLG (((int32_t)(src)) < 0); | |
34503 | m68k_incpc(4); | |
34504 | fill_prefetch_0 (); | |
34505 | m68k_write_memory_32(dsta,src); | |
34506 | }}}}}}endlabel2007: ; | |
34507 | return 26; | |
34508 | } | |
34509 | unsigned long CPUFUNC(op_21e8_5)(uint32_t opcode) /* MOVE */ | |
34510 | { | |
34511 | uint32_t srcreg = (opcode & 7); | |
34512 | OpcodeFamily = 30; CurrentInstrCycles = 28; | |
34513 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
34514 | if ((srca & 1) != 0) { | |
34515 | last_fault_for_exception_3 = srca; | |
34516 | last_op_for_exception_3 = opcode; | |
34517 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
34518 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34519 | goto endlabel2008; | |
34520 | } | |
34521 | {{ int32_t src = m68k_read_memory_32(srca); | |
34522 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); | |
34523 | if ((dsta & 1) != 0) { | |
34524 | last_fault_for_exception_3 = dsta; | |
34525 | last_op_for_exception_3 = opcode; | |
34526 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
34527 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34528 | goto endlabel2008; | |
34529 | } | |
34530 | { CLEAR_CZNV; | |
34531 | SET_ZFLG (((int32_t)(src)) == 0); | |
34532 | SET_NFLG (((int32_t)(src)) < 0); | |
34533 | m68k_incpc(6); | |
34534 | fill_prefetch_0 (); | |
34535 | m68k_write_memory_32(dsta,src); | |
34536 | }}}}}}endlabel2008: ; | |
34537 | return 28; | |
34538 | } | |
34539 | unsigned long CPUFUNC(op_21f0_5)(uint32_t opcode) /* MOVE */ | |
34540 | { | |
34541 | uint32_t srcreg = (opcode & 7); | |
34542 | OpcodeFamily = 30; CurrentInstrCycles = 30; | |
34543 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
34544 | BusCyclePenalty += 2; | |
34545 | if ((srca & 1) != 0) { | |
34546 | last_fault_for_exception_3 = srca; | |
34547 | last_op_for_exception_3 = opcode; | |
34548 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
34549 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34550 | goto endlabel2009; | |
34551 | } | |
34552 | {{ int32_t src = m68k_read_memory_32(srca); | |
34553 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); | |
34554 | if ((dsta & 1) != 0) { | |
34555 | last_fault_for_exception_3 = dsta; | |
34556 | last_op_for_exception_3 = opcode; | |
34557 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
34558 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34559 | goto endlabel2009; | |
34560 | } | |
34561 | { CLEAR_CZNV; | |
34562 | SET_ZFLG (((int32_t)(src)) == 0); | |
34563 | SET_NFLG (((int32_t)(src)) < 0); | |
34564 | m68k_incpc(6); | |
34565 | fill_prefetch_0 (); | |
34566 | m68k_write_memory_32(dsta,src); | |
34567 | }}}}}}endlabel2009: ; | |
34568 | return 30; | |
34569 | } | |
34570 | unsigned long CPUFUNC(op_21f8_5)(uint32_t opcode) /* MOVE */ | |
34571 | { | |
34572 | OpcodeFamily = 30; CurrentInstrCycles = 28; | |
34573 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
34574 | if ((srca & 1) != 0) { | |
34575 | last_fault_for_exception_3 = srca; | |
34576 | last_op_for_exception_3 = opcode; | |
34577 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
34578 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34579 | goto endlabel2010; | |
34580 | } | |
34581 | {{ int32_t src = m68k_read_memory_32(srca); | |
34582 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); | |
34583 | if ((dsta & 1) != 0) { | |
34584 | last_fault_for_exception_3 = dsta; | |
34585 | last_op_for_exception_3 = opcode; | |
34586 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
34587 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34588 | goto endlabel2010; | |
34589 | } | |
34590 | { CLEAR_CZNV; | |
34591 | SET_ZFLG (((int32_t)(src)) == 0); | |
34592 | SET_NFLG (((int32_t)(src)) < 0); | |
34593 | m68k_incpc(6); | |
34594 | fill_prefetch_0 (); | |
34595 | m68k_write_memory_32(dsta,src); | |
34596 | }}}}}}endlabel2010: ; | |
34597 | return 28; | |
34598 | } | |
34599 | unsigned long CPUFUNC(op_21f9_5)(uint32_t opcode) /* MOVE */ | |
34600 | { | |
34601 | OpcodeFamily = 30; CurrentInstrCycles = 32; | |
34602 | {{ uint32_t srca = get_ilong_prefetch(2); | |
34603 | if ((srca & 1) != 0) { | |
34604 | last_fault_for_exception_3 = srca; | |
34605 | last_op_for_exception_3 = opcode; | |
34606 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
34607 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34608 | goto endlabel2011; | |
34609 | } | |
34610 | {{ int32_t src = m68k_read_memory_32(srca); | |
34611 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(6); | |
34612 | if ((dsta & 1) != 0) { | |
34613 | last_fault_for_exception_3 = dsta; | |
34614 | last_op_for_exception_3 = opcode; | |
34615 | last_addr_for_exception_3 = m68k_getpc() + 8; | |
34616 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34617 | goto endlabel2011; | |
34618 | } | |
34619 | { CLEAR_CZNV; | |
34620 | SET_ZFLG (((int32_t)(src)) == 0); | |
34621 | SET_NFLG (((int32_t)(src)) < 0); | |
34622 | m68k_incpc(8); | |
34623 | fill_prefetch_0 (); | |
34624 | m68k_write_memory_32(dsta,src); | |
34625 | }}}}}}endlabel2011: ; | |
34626 | return 32; | |
34627 | } | |
34628 | unsigned long CPUFUNC(op_21fa_5)(uint32_t opcode) /* MOVE */ | |
34629 | { | |
34630 | OpcodeFamily = 30; CurrentInstrCycles = 28; | |
34631 | {{ uint32_t srca = m68k_getpc () + 2; | |
34632 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
34633 | if ((srca & 1) != 0) { | |
34634 | last_fault_for_exception_3 = srca; | |
34635 | last_op_for_exception_3 = opcode; | |
34636 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
34637 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34638 | goto endlabel2012; | |
34639 | } | |
34640 | {{ int32_t src = m68k_read_memory_32(srca); | |
34641 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); | |
34642 | if ((dsta & 1) != 0) { | |
34643 | last_fault_for_exception_3 = dsta; | |
34644 | last_op_for_exception_3 = opcode; | |
34645 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
34646 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34647 | goto endlabel2012; | |
34648 | } | |
34649 | { CLEAR_CZNV; | |
34650 | SET_ZFLG (((int32_t)(src)) == 0); | |
34651 | SET_NFLG (((int32_t)(src)) < 0); | |
34652 | m68k_incpc(6); | |
34653 | fill_prefetch_0 (); | |
34654 | m68k_write_memory_32(dsta,src); | |
34655 | }}}}}}endlabel2012: ; | |
34656 | return 28; | |
34657 | } | |
34658 | unsigned long CPUFUNC(op_21fb_5)(uint32_t opcode) /* MOVE */ | |
34659 | { | |
34660 | OpcodeFamily = 30; CurrentInstrCycles = 30; | |
34661 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
34662 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
34663 | BusCyclePenalty += 2; | |
34664 | if ((srca & 1) != 0) { | |
34665 | last_fault_for_exception_3 = srca; | |
34666 | last_op_for_exception_3 = opcode; | |
34667 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
34668 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34669 | goto endlabel2013; | |
34670 | } | |
34671 | {{ int32_t src = m68k_read_memory_32(srca); | |
34672 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); | |
34673 | if ((dsta & 1) != 0) { | |
34674 | last_fault_for_exception_3 = dsta; | |
34675 | last_op_for_exception_3 = opcode; | |
34676 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
34677 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34678 | goto endlabel2013; | |
34679 | } | |
34680 | { CLEAR_CZNV; | |
34681 | SET_ZFLG (((int32_t)(src)) == 0); | |
34682 | SET_NFLG (((int32_t)(src)) < 0); | |
34683 | m68k_incpc(6); | |
34684 | fill_prefetch_0 (); | |
34685 | m68k_write_memory_32(dsta,src); | |
34686 | }}}}}}endlabel2013: ; | |
34687 | return 30; | |
34688 | } | |
34689 | unsigned long CPUFUNC(op_21fc_5)(uint32_t opcode) /* MOVE */ | |
34690 | { | |
34691 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
34692 | {{ int32_t src = get_ilong_prefetch(2); | |
34693 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(6); | |
34694 | if ((dsta & 1) != 0) { | |
34695 | last_fault_for_exception_3 = dsta; | |
34696 | last_op_for_exception_3 = opcode; | |
34697 | last_addr_for_exception_3 = m68k_getpc() + 8; | |
34698 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34699 | goto endlabel2014; | |
34700 | } | |
34701 | { CLEAR_CZNV; | |
34702 | SET_ZFLG (((int32_t)(src)) == 0); | |
34703 | SET_NFLG (((int32_t)(src)) < 0); | |
34704 | m68k_incpc(8); | |
34705 | fill_prefetch_0 (); | |
34706 | m68k_write_memory_32(dsta,src); | |
34707 | }}}}endlabel2014: ; | |
34708 | return 24; | |
34709 | } | |
34710 | unsigned long CPUFUNC(op_23c0_5)(uint32_t opcode) /* MOVE */ | |
34711 | { | |
34712 | uint32_t srcreg = (opcode & 7); | |
34713 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
34714 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
34715 | { uint32_t dsta = get_ilong_prefetch(2); | |
34716 | if ((dsta & 1) != 0) { | |
34717 | last_fault_for_exception_3 = dsta; | |
34718 | last_op_for_exception_3 = opcode; | |
34719 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
34720 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34721 | goto endlabel2015; | |
34722 | } | |
34723 | { CLEAR_CZNV; | |
34724 | SET_ZFLG (((int32_t)(src)) == 0); | |
34725 | SET_NFLG (((int32_t)(src)) < 0); | |
34726 | m68k_incpc(6); | |
34727 | fill_prefetch_0 (); | |
34728 | m68k_write_memory_32(dsta,src); | |
34729 | }}}}endlabel2015: ; | |
34730 | return 20; | |
34731 | } | |
34732 | unsigned long CPUFUNC(op_23c8_5)(uint32_t opcode) /* MOVE */ | |
34733 | { | |
34734 | uint32_t srcreg = (opcode & 7); | |
34735 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
34736 | {{ int32_t src = m68k_areg(regs, srcreg); | |
34737 | { uint32_t dsta = get_ilong_prefetch(2); | |
34738 | if ((dsta & 1) != 0) { | |
34739 | last_fault_for_exception_3 = dsta; | |
34740 | last_op_for_exception_3 = opcode; | |
34741 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
34742 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34743 | goto endlabel2016; | |
34744 | } | |
34745 | { CLEAR_CZNV; | |
34746 | SET_ZFLG (((int32_t)(src)) == 0); | |
34747 | SET_NFLG (((int32_t)(src)) < 0); | |
34748 | m68k_incpc(6); | |
34749 | fill_prefetch_0 (); | |
34750 | m68k_write_memory_32(dsta,src); | |
34751 | }}}}endlabel2016: ; | |
34752 | return 20; | |
34753 | } | |
34754 | unsigned long CPUFUNC(op_23d0_5)(uint32_t opcode) /* MOVE */ | |
34755 | { | |
34756 | uint32_t srcreg = (opcode & 7); | |
34757 | OpcodeFamily = 30; CurrentInstrCycles = 28; | |
34758 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
34759 | if ((srca & 1) != 0) { | |
34760 | last_fault_for_exception_3 = srca; | |
34761 | last_op_for_exception_3 = opcode; | |
34762 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
34763 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34764 | goto endlabel2017; | |
34765 | } | |
34766 | {{ int32_t src = m68k_read_memory_32(srca); | |
34767 | { uint32_t dsta = get_ilong_prefetch(2); | |
34768 | if ((dsta & 1) != 0) { | |
34769 | last_fault_for_exception_3 = dsta; | |
34770 | last_op_for_exception_3 = opcode; | |
34771 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
34772 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34773 | goto endlabel2017; | |
34774 | } | |
34775 | { CLEAR_CZNV; | |
34776 | SET_ZFLG (((int32_t)(src)) == 0); | |
34777 | SET_NFLG (((int32_t)(src)) < 0); | |
34778 | m68k_incpc(6); | |
34779 | fill_prefetch_0 (); | |
34780 | m68k_write_memory_32(dsta,src); | |
34781 | }}}}}}endlabel2017: ; | |
34782 | return 28; | |
34783 | } | |
34784 | unsigned long CPUFUNC(op_23d8_5)(uint32_t opcode) /* MOVE */ | |
34785 | { | |
34786 | uint32_t srcreg = (opcode & 7); | |
34787 | OpcodeFamily = 30; CurrentInstrCycles = 28; | |
34788 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
34789 | if ((srca & 1) != 0) { | |
34790 | last_fault_for_exception_3 = srca; | |
34791 | last_op_for_exception_3 = opcode; | |
34792 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
34793 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34794 | goto endlabel2018; | |
34795 | } | |
34796 | {{ int32_t src = m68k_read_memory_32(srca); | |
34797 | m68k_areg(regs, srcreg) += 4; | |
34798 | { uint32_t dsta = get_ilong_prefetch(2); | |
34799 | if ((dsta & 1) != 0) { | |
34800 | last_fault_for_exception_3 = dsta; | |
34801 | last_op_for_exception_3 = opcode; | |
34802 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
34803 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34804 | goto endlabel2018; | |
34805 | } | |
34806 | { CLEAR_CZNV; | |
34807 | SET_ZFLG (((int32_t)(src)) == 0); | |
34808 | SET_NFLG (((int32_t)(src)) < 0); | |
34809 | m68k_incpc(6); | |
34810 | fill_prefetch_0 (); | |
34811 | m68k_write_memory_32(dsta,src); | |
34812 | }}}}}}endlabel2018: ; | |
34813 | return 28; | |
34814 | } | |
34815 | unsigned long CPUFUNC(op_23e0_5)(uint32_t opcode) /* MOVE */ | |
34816 | { | |
34817 | uint32_t srcreg = (opcode & 7); | |
34818 | OpcodeFamily = 30; CurrentInstrCycles = 30; | |
34819 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 4; | |
34820 | if ((srca & 1) != 0) { | |
34821 | last_fault_for_exception_3 = srca; | |
34822 | last_op_for_exception_3 = opcode; | |
34823 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
34824 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34825 | goto endlabel2019; | |
34826 | } | |
34827 | {{ int32_t src = m68k_read_memory_32(srca); | |
34828 | m68k_areg (regs, srcreg) = srca; | |
34829 | { uint32_t dsta = get_ilong_prefetch(2); | |
34830 | if ((dsta & 1) != 0) { | |
34831 | last_fault_for_exception_3 = dsta; | |
34832 | last_op_for_exception_3 = opcode; | |
34833 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
34834 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34835 | goto endlabel2019; | |
34836 | } | |
34837 | { CLEAR_CZNV; | |
34838 | SET_ZFLG (((int32_t)(src)) == 0); | |
34839 | SET_NFLG (((int32_t)(src)) < 0); | |
34840 | m68k_incpc(6); | |
34841 | fill_prefetch_0 (); | |
34842 | m68k_write_memory_32(dsta,src); | |
34843 | }}}}}}endlabel2019: ; | |
34844 | return 30; | |
34845 | } | |
34846 | unsigned long CPUFUNC(op_23e8_5)(uint32_t opcode) /* MOVE */ | |
34847 | { | |
34848 | uint32_t srcreg = (opcode & 7); | |
34849 | OpcodeFamily = 30; CurrentInstrCycles = 32; | |
34850 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
34851 | if ((srca & 1) != 0) { | |
34852 | last_fault_for_exception_3 = srca; | |
34853 | last_op_for_exception_3 = opcode; | |
34854 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
34855 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34856 | goto endlabel2020; | |
34857 | } | |
34858 | {{ int32_t src = m68k_read_memory_32(srca); | |
34859 | { uint32_t dsta = get_ilong_prefetch(4); | |
34860 | if ((dsta & 1) != 0) { | |
34861 | last_fault_for_exception_3 = dsta; | |
34862 | last_op_for_exception_3 = opcode; | |
34863 | last_addr_for_exception_3 = m68k_getpc() + 8; | |
34864 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34865 | goto endlabel2020; | |
34866 | } | |
34867 | { CLEAR_CZNV; | |
34868 | SET_ZFLG (((int32_t)(src)) == 0); | |
34869 | SET_NFLG (((int32_t)(src)) < 0); | |
34870 | m68k_incpc(8); | |
34871 | fill_prefetch_0 (); | |
34872 | m68k_write_memory_32(dsta,src); | |
34873 | }}}}}}endlabel2020: ; | |
34874 | return 32; | |
34875 | } | |
34876 | unsigned long CPUFUNC(op_23f0_5)(uint32_t opcode) /* MOVE */ | |
34877 | { | |
34878 | uint32_t srcreg = (opcode & 7); | |
34879 | OpcodeFamily = 30; CurrentInstrCycles = 34; | |
34880 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
34881 | BusCyclePenalty += 2; | |
34882 | if ((srca & 1) != 0) { | |
34883 | last_fault_for_exception_3 = srca; | |
34884 | last_op_for_exception_3 = opcode; | |
34885 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
34886 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34887 | goto endlabel2021; | |
34888 | } | |
34889 | {{ int32_t src = m68k_read_memory_32(srca); | |
34890 | { uint32_t dsta = get_ilong_prefetch(4); | |
34891 | if ((dsta & 1) != 0) { | |
34892 | last_fault_for_exception_3 = dsta; | |
34893 | last_op_for_exception_3 = opcode; | |
34894 | last_addr_for_exception_3 = m68k_getpc() + 8; | |
34895 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34896 | goto endlabel2021; | |
34897 | } | |
34898 | { CLEAR_CZNV; | |
34899 | SET_ZFLG (((int32_t)(src)) == 0); | |
34900 | SET_NFLG (((int32_t)(src)) < 0); | |
34901 | m68k_incpc(8); | |
34902 | fill_prefetch_0 (); | |
34903 | m68k_write_memory_32(dsta,src); | |
34904 | }}}}}}endlabel2021: ; | |
34905 | return 34; | |
34906 | } | |
34907 | unsigned long CPUFUNC(op_23f8_5)(uint32_t opcode) /* MOVE */ | |
34908 | { | |
34909 | OpcodeFamily = 30; CurrentInstrCycles = 32; | |
34910 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
34911 | if ((srca & 1) != 0) { | |
34912 | last_fault_for_exception_3 = srca; | |
34913 | last_op_for_exception_3 = opcode; | |
34914 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
34915 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34916 | goto endlabel2022; | |
34917 | } | |
34918 | {{ int32_t src = m68k_read_memory_32(srca); | |
34919 | { uint32_t dsta = get_ilong_prefetch(4); | |
34920 | if ((dsta & 1) != 0) { | |
34921 | last_fault_for_exception_3 = dsta; | |
34922 | last_op_for_exception_3 = opcode; | |
34923 | last_addr_for_exception_3 = m68k_getpc() + 8; | |
34924 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34925 | goto endlabel2022; | |
34926 | } | |
34927 | { CLEAR_CZNV; | |
34928 | SET_ZFLG (((int32_t)(src)) == 0); | |
34929 | SET_NFLG (((int32_t)(src)) < 0); | |
34930 | m68k_incpc(8); | |
34931 | fill_prefetch_0 (); | |
34932 | m68k_write_memory_32(dsta,src); | |
34933 | }}}}}}endlabel2022: ; | |
34934 | return 32; | |
34935 | } | |
34936 | unsigned long CPUFUNC(op_23f9_5)(uint32_t opcode) /* MOVE */ | |
34937 | { | |
34938 | OpcodeFamily = 30; CurrentInstrCycles = 36; | |
34939 | {{ uint32_t srca = get_ilong_prefetch(2); | |
34940 | if ((srca & 1) != 0) { | |
34941 | last_fault_for_exception_3 = srca; | |
34942 | last_op_for_exception_3 = opcode; | |
34943 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
34944 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34945 | goto endlabel2023; | |
34946 | } | |
34947 | {{ int32_t src = m68k_read_memory_32(srca); | |
34948 | { uint32_t dsta = get_ilong_prefetch(6); | |
34949 | if ((dsta & 1) != 0) { | |
34950 | last_fault_for_exception_3 = dsta; | |
34951 | last_op_for_exception_3 = opcode; | |
34952 | last_addr_for_exception_3 = m68k_getpc() + 10; | |
34953 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34954 | goto endlabel2023; | |
34955 | } | |
34956 | { CLEAR_CZNV; | |
34957 | SET_ZFLG (((int32_t)(src)) == 0); | |
34958 | SET_NFLG (((int32_t)(src)) < 0); | |
34959 | m68k_incpc(10); | |
34960 | fill_prefetch_0 (); | |
34961 | m68k_write_memory_32(dsta,src); | |
34962 | }}}}}}endlabel2023: ; | |
34963 | return 36; | |
34964 | } | |
34965 | unsigned long CPUFUNC(op_23fa_5)(uint32_t opcode) /* MOVE */ | |
34966 | { | |
34967 | OpcodeFamily = 30; CurrentInstrCycles = 32; | |
34968 | {{ uint32_t srca = m68k_getpc () + 2; | |
34969 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
34970 | if ((srca & 1) != 0) { | |
34971 | last_fault_for_exception_3 = srca; | |
34972 | last_op_for_exception_3 = opcode; | |
34973 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
34974 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34975 | goto endlabel2024; | |
34976 | } | |
34977 | {{ int32_t src = m68k_read_memory_32(srca); | |
34978 | { uint32_t dsta = get_ilong_prefetch(4); | |
34979 | if ((dsta & 1) != 0) { | |
34980 | last_fault_for_exception_3 = dsta; | |
34981 | last_op_for_exception_3 = opcode; | |
34982 | last_addr_for_exception_3 = m68k_getpc() + 8; | |
34983 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
34984 | goto endlabel2024; | |
34985 | } | |
34986 | { CLEAR_CZNV; | |
34987 | SET_ZFLG (((int32_t)(src)) == 0); | |
34988 | SET_NFLG (((int32_t)(src)) < 0); | |
34989 | m68k_incpc(8); | |
34990 | fill_prefetch_0 (); | |
34991 | m68k_write_memory_32(dsta,src); | |
34992 | }}}}}}endlabel2024: ; | |
34993 | return 32; | |
34994 | } | |
34995 | unsigned long CPUFUNC(op_23fb_5)(uint32_t opcode) /* MOVE */ | |
34996 | { | |
34997 | OpcodeFamily = 30; CurrentInstrCycles = 34; | |
34998 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
34999 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
35000 | BusCyclePenalty += 2; | |
35001 | if ((srca & 1) != 0) { | |
35002 | last_fault_for_exception_3 = srca; | |
35003 | last_op_for_exception_3 = opcode; | |
35004 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
35005 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
35006 | goto endlabel2025; | |
35007 | } | |
35008 | {{ int32_t src = m68k_read_memory_32(srca); | |
35009 | { uint32_t dsta = get_ilong_prefetch(4); | |
35010 | if ((dsta & 1) != 0) { | |
35011 | last_fault_for_exception_3 = dsta; | |
35012 | last_op_for_exception_3 = opcode; | |
35013 | last_addr_for_exception_3 = m68k_getpc() + 8; | |
35014 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
35015 | goto endlabel2025; | |
35016 | } | |
35017 | { CLEAR_CZNV; | |
35018 | SET_ZFLG (((int32_t)(src)) == 0); | |
35019 | SET_NFLG (((int32_t)(src)) < 0); | |
35020 | m68k_incpc(8); | |
35021 | fill_prefetch_0 (); | |
35022 | m68k_write_memory_32(dsta,src); | |
35023 | }}}}}}endlabel2025: ; | |
35024 | return 34; | |
35025 | } | |
35026 | unsigned long CPUFUNC(op_23fc_5)(uint32_t opcode) /* MOVE */ | |
35027 | { | |
35028 | OpcodeFamily = 30; CurrentInstrCycles = 28; | |
35029 | {{ int32_t src = get_ilong_prefetch(2); | |
35030 | { uint32_t dsta = get_ilong_prefetch(6); | |
35031 | if ((dsta & 1) != 0) { | |
35032 | last_fault_for_exception_3 = dsta; | |
35033 | last_op_for_exception_3 = opcode; | |
35034 | last_addr_for_exception_3 = m68k_getpc() + 10; | |
35035 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
35036 | goto endlabel2026; | |
35037 | } | |
35038 | { CLEAR_CZNV; | |
35039 | SET_ZFLG (((int32_t)(src)) == 0); | |
35040 | SET_NFLG (((int32_t)(src)) < 0); | |
35041 | m68k_incpc(10); | |
35042 | fill_prefetch_0 (); | |
35043 | m68k_write_memory_32(dsta,src); | |
35044 | }}}}endlabel2026: ; | |
35045 | return 28; | |
35046 | } | |
35047 | unsigned long CPUFUNC(op_3000_5)(uint32_t opcode) /* MOVE */ | |
35048 | { | |
35049 | uint32_t srcreg = (opcode & 7); | |
35050 | uint32_t dstreg = (opcode >> 9) & 7; | |
35051 | OpcodeFamily = 30; CurrentInstrCycles = 4; | |
35052 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
35053 | { CLEAR_CZNV; | |
35054 | SET_ZFLG (((int16_t)(src)) == 0); | |
35055 | SET_NFLG (((int16_t)(src)) < 0); | |
35056 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
35057 | }}}m68k_incpc(2); | |
35058 | fill_prefetch_2 (); | |
35059 | return 4; | |
35060 | } | |
35061 | unsigned long CPUFUNC(op_3008_5)(uint32_t opcode) /* MOVE */ | |
35062 | { | |
35063 | uint32_t srcreg = (opcode & 7); | |
35064 | uint32_t dstreg = (opcode >> 9) & 7; | |
35065 | OpcodeFamily = 30; CurrentInstrCycles = 4; | |
35066 | {{ int16_t src = m68k_areg(regs, srcreg); | |
35067 | { CLEAR_CZNV; | |
35068 | SET_ZFLG (((int16_t)(src)) == 0); | |
35069 | SET_NFLG (((int16_t)(src)) < 0); | |
35070 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
35071 | }}}m68k_incpc(2); | |
35072 | fill_prefetch_2 (); | |
35073 | return 4; | |
35074 | } | |
35075 | unsigned long CPUFUNC(op_3010_5)(uint32_t opcode) /* MOVE */ | |
35076 | { | |
35077 | uint32_t srcreg = (opcode & 7); | |
35078 | uint32_t dstreg = (opcode >> 9) & 7; | |
35079 | OpcodeFamily = 30; CurrentInstrCycles = 8; | |
35080 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
35081 | if ((srca & 1) != 0) { | |
35082 | last_fault_for_exception_3 = srca; | |
35083 | last_op_for_exception_3 = opcode; | |
35084 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
35085 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
35086 | goto endlabel2029; | |
35087 | } | |
35088 | {{ int16_t src = m68k_read_memory_16(srca); | |
35089 | { CLEAR_CZNV; | |
35090 | SET_ZFLG (((int16_t)(src)) == 0); | |
35091 | SET_NFLG (((int16_t)(src)) < 0); | |
35092 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
35093 | }}}}}m68k_incpc(2); | |
35094 | fill_prefetch_2 (); | |
35095 | endlabel2029: ; | |
35096 | return 8; | |
35097 | } | |
35098 | unsigned long CPUFUNC(op_3018_5)(uint32_t opcode) /* MOVE */ | |
35099 | { | |
35100 | uint32_t srcreg = (opcode & 7); | |
35101 | uint32_t dstreg = (opcode >> 9) & 7; | |
35102 | OpcodeFamily = 30; CurrentInstrCycles = 8; | |
35103 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
35104 | if ((srca & 1) != 0) { | |
35105 | last_fault_for_exception_3 = srca; | |
35106 | last_op_for_exception_3 = opcode; | |
35107 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
35108 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
35109 | goto endlabel2030; | |
35110 | } | |
35111 | {{ int16_t src = m68k_read_memory_16(srca); | |
35112 | m68k_areg(regs, srcreg) += 2; | |
35113 | { CLEAR_CZNV; | |
35114 | SET_ZFLG (((int16_t)(src)) == 0); | |
35115 | SET_NFLG (((int16_t)(src)) < 0); | |
35116 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
35117 | }}}}}m68k_incpc(2); | |
35118 | fill_prefetch_2 (); | |
35119 | endlabel2030: ; | |
35120 | return 8; | |
35121 | } | |
35122 | unsigned long CPUFUNC(op_3020_5)(uint32_t opcode) /* MOVE */ | |
35123 | { | |
35124 | uint32_t srcreg = (opcode & 7); | |
35125 | uint32_t dstreg = (opcode >> 9) & 7; | |
35126 | OpcodeFamily = 30; CurrentInstrCycles = 10; | |
35127 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
35128 | if ((srca & 1) != 0) { | |
35129 | last_fault_for_exception_3 = srca; | |
35130 | last_op_for_exception_3 = opcode; | |
35131 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
35132 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
35133 | goto endlabel2031; | |
35134 | } | |
35135 | {{ int16_t src = m68k_read_memory_16(srca); | |
35136 | m68k_areg (regs, srcreg) = srca; | |
35137 | { CLEAR_CZNV; | |
35138 | SET_ZFLG (((int16_t)(src)) == 0); | |
35139 | SET_NFLG (((int16_t)(src)) < 0); | |
35140 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
35141 | }}}}}m68k_incpc(2); | |
35142 | fill_prefetch_2 (); | |
35143 | endlabel2031: ; | |
35144 | return 10; | |
35145 | } | |
35146 | unsigned long CPUFUNC(op_3028_5)(uint32_t opcode) /* MOVE */ | |
35147 | { | |
35148 | uint32_t srcreg = (opcode & 7); | |
35149 | uint32_t dstreg = (opcode >> 9) & 7; | |
35150 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
35151 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
35152 | if ((srca & 1) != 0) { | |
35153 | last_fault_for_exception_3 = srca; | |
35154 | last_op_for_exception_3 = opcode; | |
35155 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
35156 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
35157 | goto endlabel2032; | |
35158 | } | |
35159 | {{ int16_t src = m68k_read_memory_16(srca); | |
35160 | { CLEAR_CZNV; | |
35161 | SET_ZFLG (((int16_t)(src)) == 0); | |
35162 | SET_NFLG (((int16_t)(src)) < 0); | |
35163 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
35164 | }}}}}m68k_incpc(4); | |
35165 | fill_prefetch_0 (); | |
35166 | endlabel2032: ; | |
35167 | return 12; | |
35168 | } | |
35169 | unsigned long CPUFUNC(op_3030_5)(uint32_t opcode) /* MOVE */ | |
35170 | { | |
35171 | uint32_t srcreg = (opcode & 7); | |
35172 | uint32_t dstreg = (opcode >> 9) & 7; | |
35173 | OpcodeFamily = 30; CurrentInstrCycles = 14; | |
35174 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
35175 | BusCyclePenalty += 2; | |
35176 | if ((srca & 1) != 0) { | |
35177 | last_fault_for_exception_3 = srca; | |
35178 | last_op_for_exception_3 = opcode; | |
35179 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
35180 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
35181 | goto endlabel2033; | |
35182 | } | |
35183 | {{ int16_t src = m68k_read_memory_16(srca); | |
35184 | { CLEAR_CZNV; | |
35185 | SET_ZFLG (((int16_t)(src)) == 0); | |
35186 | SET_NFLG (((int16_t)(src)) < 0); | |
35187 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
35188 | }}}}}m68k_incpc(4); | |
35189 | fill_prefetch_0 (); | |
35190 | endlabel2033: ; | |
35191 | return 14; | |
35192 | } | |
35193 | unsigned long CPUFUNC(op_3038_5)(uint32_t opcode) /* MOVE */ | |
35194 | { | |
35195 | uint32_t dstreg = (opcode >> 9) & 7; | |
35196 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
35197 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
35198 | if ((srca & 1) != 0) { | |
35199 | last_fault_for_exception_3 = srca; | |
35200 | last_op_for_exception_3 = opcode; | |
35201 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
35202 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
35203 | goto endlabel2034; | |
35204 | } | |
35205 | {{ int16_t src = m68k_read_memory_16(srca); | |
35206 | { CLEAR_CZNV; | |
35207 | SET_ZFLG (((int16_t)(src)) == 0); | |
35208 | SET_NFLG (((int16_t)(src)) < 0); | |
35209 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
35210 | }}}}}m68k_incpc(4); | |
35211 | fill_prefetch_0 (); | |
35212 | endlabel2034: ; | |
35213 | return 12; | |
35214 | } | |
35215 | unsigned long CPUFUNC(op_3039_5)(uint32_t opcode) /* MOVE */ | |
35216 | { | |
35217 | uint32_t dstreg = (opcode >> 9) & 7; | |
35218 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
35219 | {{ uint32_t srca = get_ilong_prefetch(2); | |
35220 | if ((srca & 1) != 0) { | |
35221 | last_fault_for_exception_3 = srca; | |
35222 | last_op_for_exception_3 = opcode; | |
35223 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
35224 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
35225 | goto endlabel2035; | |
35226 | } | |
35227 | {{ int16_t src = m68k_read_memory_16(srca); | |
35228 | { CLEAR_CZNV; | |
35229 | SET_ZFLG (((int16_t)(src)) == 0); | |
35230 | SET_NFLG (((int16_t)(src)) < 0); | |
35231 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
35232 | }}}}}m68k_incpc(6); | |
35233 | fill_prefetch_0 (); | |
35234 | endlabel2035: ; | |
35235 | return 16; | |
35236 | } | |
35237 | unsigned long CPUFUNC(op_303a_5)(uint32_t opcode) /* MOVE */ | |
35238 | { | |
35239 | uint32_t dstreg = (opcode >> 9) & 7; | |
35240 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
35241 | {{ uint32_t srca = m68k_getpc () + 2; | |
35242 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
35243 | if ((srca & 1) != 0) { | |
35244 | last_fault_for_exception_3 = srca; | |
35245 | last_op_for_exception_3 = opcode; | |
35246 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
35247 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
35248 | goto endlabel2036; | |
35249 | } | |
35250 | {{ int16_t src = m68k_read_memory_16(srca); | |
35251 | { CLEAR_CZNV; | |
35252 | SET_ZFLG (((int16_t)(src)) == 0); | |
35253 | SET_NFLG (((int16_t)(src)) < 0); | |
35254 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
35255 | }}}}}m68k_incpc(4); | |
35256 | fill_prefetch_0 (); | |
35257 | endlabel2036: ; | |
35258 | return 12; | |
35259 | } | |
35260 | unsigned long CPUFUNC(op_303b_5)(uint32_t opcode) /* MOVE */ | |
35261 | { | |
35262 | uint32_t dstreg = (opcode >> 9) & 7; | |
35263 | OpcodeFamily = 30; CurrentInstrCycles = 14; | |
35264 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
35265 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
35266 | BusCyclePenalty += 2; | |
35267 | if ((srca & 1) != 0) { | |
35268 | last_fault_for_exception_3 = srca; | |
35269 | last_op_for_exception_3 = opcode; | |
35270 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
35271 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
35272 | goto endlabel2037; | |
35273 | } | |
35274 | {{ int16_t src = m68k_read_memory_16(srca); | |
35275 | { CLEAR_CZNV; | |
35276 | SET_ZFLG (((int16_t)(src)) == 0); | |
35277 | SET_NFLG (((int16_t)(src)) < 0); | |
35278 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
35279 | }}}}}m68k_incpc(4); | |
35280 | fill_prefetch_0 (); | |
35281 | endlabel2037: ; | |
35282 | return 14; | |
35283 | } | |
35284 | unsigned long CPUFUNC(op_303c_5)(uint32_t opcode) /* MOVE */ | |
35285 | { | |
35286 | uint32_t dstreg = (opcode >> 9) & 7; | |
35287 | OpcodeFamily = 30; CurrentInstrCycles = 8; | |
35288 | {{ int16_t src = get_iword_prefetch(2); | |
35289 | { CLEAR_CZNV; | |
35290 | SET_ZFLG (((int16_t)(src)) == 0); | |
35291 | SET_NFLG (((int16_t)(src)) < 0); | |
35292 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
35293 | }}}m68k_incpc(4); | |
35294 | fill_prefetch_0 (); | |
35295 | return 8; | |
35296 | } | |
35297 | unsigned long CPUFUNC(op_3040_5)(uint32_t opcode) /* MOVEA */ | |
35298 | { | |
35299 | uint32_t srcreg = (opcode & 7); | |
35300 | uint32_t dstreg = (opcode >> 9) & 7; | |
35301 | OpcodeFamily = 31; CurrentInstrCycles = 4; | |
35302 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
35303 | { uint32_t val = (int32_t)(int16_t)src; | |
35304 | m68k_areg(regs, dstreg) = (val); | |
35305 | }}}m68k_incpc(2); | |
35306 | fill_prefetch_2 (); | |
35307 | return 4; | |
35308 | } | |
35309 | unsigned long CPUFUNC(op_3048_5)(uint32_t opcode) /* MOVEA */ | |
35310 | { | |
35311 | uint32_t srcreg = (opcode & 7); | |
35312 | uint32_t dstreg = (opcode >> 9) & 7; | |
35313 | OpcodeFamily = 31; CurrentInstrCycles = 4; | |
35314 | {{ int16_t src = m68k_areg(regs, srcreg); | |
35315 | { uint32_t val = (int32_t)(int16_t)src; | |
35316 | m68k_areg(regs, dstreg) = (val); | |
35317 | }}}m68k_incpc(2); | |
35318 | fill_prefetch_2 (); | |
35319 | return 4; | |
35320 | } | |
35321 | unsigned long CPUFUNC(op_3050_5)(uint32_t opcode) /* MOVEA */ | |
35322 | { | |
35323 | uint32_t srcreg = (opcode & 7); | |
35324 | uint32_t dstreg = (opcode >> 9) & 7; | |
35325 | OpcodeFamily = 31; CurrentInstrCycles = 8; | |
35326 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
35327 | if ((srca & 1) != 0) { | |
35328 | last_fault_for_exception_3 = srca; | |
35329 | last_op_for_exception_3 = opcode; | |
35330 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
35331 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
35332 | goto endlabel2041; | |
35333 | } | |
35334 | {{ int16_t src = m68k_read_memory_16(srca); | |
35335 | { uint32_t val = (int32_t)(int16_t)src; | |
35336 | m68k_areg(regs, dstreg) = (val); | |
35337 | }}}}}m68k_incpc(2); | |
35338 | fill_prefetch_2 (); | |
35339 | endlabel2041: ; | |
35340 | return 8; | |
35341 | } | |
35342 | unsigned long CPUFUNC(op_3058_5)(uint32_t opcode) /* MOVEA */ | |
35343 | { | |
35344 | uint32_t srcreg = (opcode & 7); | |
35345 | uint32_t dstreg = (opcode >> 9) & 7; | |
35346 | OpcodeFamily = 31; CurrentInstrCycles = 8; | |
35347 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
35348 | if ((srca & 1) != 0) { | |
35349 | last_fault_for_exception_3 = srca; | |
35350 | last_op_for_exception_3 = opcode; | |
35351 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
35352 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
35353 | goto endlabel2042; | |
35354 | } | |
35355 | {{ int16_t src = m68k_read_memory_16(srca); | |
35356 | m68k_areg(regs, srcreg) += 2; | |
35357 | { uint32_t val = (int32_t)(int16_t)src; | |
35358 | m68k_areg(regs, dstreg) = (val); | |
35359 | }}}}}m68k_incpc(2); | |
35360 | fill_prefetch_2 (); | |
35361 | endlabel2042: ; | |
35362 | return 8; | |
35363 | } | |
35364 | unsigned long CPUFUNC(op_3060_5)(uint32_t opcode) /* MOVEA */ | |
35365 | { | |
35366 | uint32_t srcreg = (opcode & 7); | |
35367 | uint32_t dstreg = (opcode >> 9) & 7; | |
35368 | OpcodeFamily = 31; CurrentInstrCycles = 10; | |
35369 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
35370 | if ((srca & 1) != 0) { | |
35371 | last_fault_for_exception_3 = srca; | |
35372 | last_op_for_exception_3 = opcode; | |
35373 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
35374 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
35375 | goto endlabel2043; | |
35376 | } | |
35377 | {{ int16_t src = m68k_read_memory_16(srca); | |
35378 | m68k_areg (regs, srcreg) = srca; | |
35379 | { uint32_t val = (int32_t)(int16_t)src; | |
35380 | m68k_areg(regs, dstreg) = (val); | |
35381 | }}}}}m68k_incpc(2); | |
35382 | fill_prefetch_2 (); | |
35383 | endlabel2043: ; | |
35384 | return 10; | |
35385 | } | |
35386 | unsigned long CPUFUNC(op_3068_5)(uint32_t opcode) /* MOVEA */ | |
35387 | { | |
35388 | uint32_t srcreg = (opcode & 7); | |
35389 | uint32_t dstreg = (opcode >> 9) & 7; | |
35390 | OpcodeFamily = 31; CurrentInstrCycles = 12; | |
35391 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
35392 | if ((srca & 1) != 0) { | |
35393 | last_fault_for_exception_3 = srca; | |
35394 | last_op_for_exception_3 = opcode; | |
35395 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
35396 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
35397 | goto endlabel2044; | |
35398 | } | |
35399 | {{ int16_t src = m68k_read_memory_16(srca); | |
35400 | { uint32_t val = (int32_t)(int16_t)src; | |
35401 | m68k_areg(regs, dstreg) = (val); | |
35402 | }}}}}m68k_incpc(4); | |
35403 | fill_prefetch_0 (); | |
35404 | endlabel2044: ; | |
35405 | return 12; | |
35406 | } | |
35407 | unsigned long CPUFUNC(op_3070_5)(uint32_t opcode) /* MOVEA */ | |
35408 | { | |
35409 | uint32_t srcreg = (opcode & 7); | |
35410 | uint32_t dstreg = (opcode >> 9) & 7; | |
35411 | OpcodeFamily = 31; CurrentInstrCycles = 14; | |
35412 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
35413 | BusCyclePenalty += 2; | |
35414 | if ((srca & 1) != 0) { | |
35415 | last_fault_for_exception_3 = srca; | |
35416 | last_op_for_exception_3 = opcode; | |
35417 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
35418 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
35419 | goto endlabel2045; | |
35420 | } | |
35421 | {{ int16_t src = m68k_read_memory_16(srca); | |
35422 | { uint32_t val = (int32_t)(int16_t)src; | |
35423 | m68k_areg(regs, dstreg) = (val); | |
35424 | }}}}}m68k_incpc(4); | |
35425 | fill_prefetch_0 (); | |
35426 | endlabel2045: ; | |
35427 | return 14; | |
35428 | } | |
35429 | unsigned long CPUFUNC(op_3078_5)(uint32_t opcode) /* MOVEA */ | |
35430 | { | |
35431 | uint32_t dstreg = (opcode >> 9) & 7; | |
35432 | OpcodeFamily = 31; CurrentInstrCycles = 12; | |
35433 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
35434 | if ((srca & 1) != 0) { | |
35435 | last_fault_for_exception_3 = srca; | |
35436 | last_op_for_exception_3 = opcode; | |
35437 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
35438 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
35439 | goto endlabel2046; | |
35440 | } | |
35441 | {{ int16_t src = m68k_read_memory_16(srca); | |
35442 | { uint32_t val = (int32_t)(int16_t)src; | |
35443 | m68k_areg(regs, dstreg) = (val); | |
35444 | }}}}}m68k_incpc(4); | |
35445 | fill_prefetch_0 (); | |
35446 | endlabel2046: ; | |
35447 | return 12; | |
35448 | } | |
35449 | unsigned long CPUFUNC(op_3079_5)(uint32_t opcode) /* MOVEA */ | |
35450 | { | |
35451 | uint32_t dstreg = (opcode >> 9) & 7; | |
35452 | OpcodeFamily = 31; CurrentInstrCycles = 16; | |
35453 | {{ uint32_t srca = get_ilong_prefetch(2); | |
35454 | if ((srca & 1) != 0) { | |
35455 | last_fault_for_exception_3 = srca; | |
35456 | last_op_for_exception_3 = opcode; | |
35457 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
35458 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
35459 | goto endlabel2047; | |
35460 | } | |
35461 | {{ int16_t src = m68k_read_memory_16(srca); | |
35462 | { uint32_t val = (int32_t)(int16_t)src; | |
35463 | m68k_areg(regs, dstreg) = (val); | |
35464 | }}}}}m68k_incpc(6); | |
35465 | fill_prefetch_0 (); | |
35466 | endlabel2047: ; | |
35467 | return 16; | |
35468 | } | |
35469 | unsigned long CPUFUNC(op_307a_5)(uint32_t opcode) /* MOVEA */ | |
35470 | { | |
35471 | uint32_t dstreg = (opcode >> 9) & 7; | |
35472 | OpcodeFamily = 31; CurrentInstrCycles = 12; | |
35473 | {{ uint32_t srca = m68k_getpc () + 2; | |
35474 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
35475 | if ((srca & 1) != 0) { | |
35476 | last_fault_for_exception_3 = srca; | |
35477 | last_op_for_exception_3 = opcode; | |
35478 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
35479 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
35480 | goto endlabel2048; | |
35481 | } | |
35482 | {{ int16_t src = m68k_read_memory_16(srca); | |
35483 | { uint32_t val = (int32_t)(int16_t)src; | |
35484 | m68k_areg(regs, dstreg) = (val); | |
35485 | }}}}}m68k_incpc(4); | |
35486 | fill_prefetch_0 (); | |
35487 | endlabel2048: ; | |
35488 | return 12; | |
35489 | } | |
35490 | unsigned long CPUFUNC(op_307b_5)(uint32_t opcode) /* MOVEA */ | |
35491 | { | |
35492 | uint32_t dstreg = (opcode >> 9) & 7; | |
35493 | OpcodeFamily = 31; CurrentInstrCycles = 14; | |
35494 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
35495 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
35496 | BusCyclePenalty += 2; | |
35497 | if ((srca & 1) != 0) { | |
35498 | last_fault_for_exception_3 = srca; | |
35499 | last_op_for_exception_3 = opcode; | |
35500 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
35501 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
35502 | goto endlabel2049; | |
35503 | } | |
35504 | {{ int16_t src = m68k_read_memory_16(srca); | |
35505 | { uint32_t val = (int32_t)(int16_t)src; | |
35506 | m68k_areg(regs, dstreg) = (val); | |
35507 | }}}}}m68k_incpc(4); | |
35508 | fill_prefetch_0 (); | |
35509 | endlabel2049: ; | |
35510 | return 14; | |
35511 | } | |
35512 | unsigned long CPUFUNC(op_307c_5)(uint32_t opcode) /* MOVEA */ | |
35513 | { | |
35514 | uint32_t dstreg = (opcode >> 9) & 7; | |
35515 | OpcodeFamily = 31; CurrentInstrCycles = 8; | |
35516 | {{ int16_t src = get_iword_prefetch(2); | |
35517 | { uint32_t val = (int32_t)(int16_t)src; | |
35518 | m68k_areg(regs, dstreg) = (val); | |
35519 | }}}m68k_incpc(4); | |
35520 | fill_prefetch_0 (); | |
35521 | return 8; | |
35522 | } | |
35523 | unsigned long CPUFUNC(op_3080_5)(uint32_t opcode) /* MOVE */ | |
35524 | { | |
35525 | uint32_t srcreg = (opcode & 7); | |
35526 | uint32_t dstreg = (opcode >> 9) & 7; | |
35527 | OpcodeFamily = 30; CurrentInstrCycles = 8; | |
35528 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
35529 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
35530 | if ((dsta & 1) != 0) { | |
35531 | last_fault_for_exception_3 = dsta; | |
35532 | last_op_for_exception_3 = opcode; | |
35533 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
35534 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
35535 | goto endlabel2051; | |
35536 | } | |
35537 | { CLEAR_CZNV; | |
35538 | SET_ZFLG (((int16_t)(src)) == 0); | |
35539 | SET_NFLG (((int16_t)(src)) < 0); | |
35540 | m68k_incpc(2); | |
35541 | fill_prefetch_2 (); | |
35542 | m68k_write_memory_16(dsta,src); | |
35543 | }}}}endlabel2051: ; | |
35544 | return 8; | |
35545 | } | |
35546 | unsigned long CPUFUNC(op_3088_5)(uint32_t opcode) /* MOVE */ | |
35547 | { | |
35548 | uint32_t srcreg = (opcode & 7); | |
35549 | uint32_t dstreg = (opcode >> 9) & 7; | |
35550 | OpcodeFamily = 30; CurrentInstrCycles = 8; | |
35551 | {{ int16_t src = m68k_areg(regs, srcreg); | |
35552 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
35553 | if ((dsta & 1) != 0) { | |
35554 | last_fault_for_exception_3 = dsta; | |
35555 | last_op_for_exception_3 = opcode; | |
35556 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
35557 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
35558 | goto endlabel2052; | |
35559 | } | |
35560 | { CLEAR_CZNV; | |
35561 | SET_ZFLG (((int16_t)(src)) == 0); | |
35562 | SET_NFLG (((int16_t)(src)) < 0); | |
35563 | m68k_incpc(2); | |
35564 | fill_prefetch_2 (); | |
35565 | m68k_write_memory_16(dsta,src); | |
35566 | }}}}endlabel2052: ; | |
35567 | return 8; | |
35568 | } | |
35569 | unsigned long CPUFUNC(op_3090_5)(uint32_t opcode) /* MOVE */ | |
35570 | { | |
35571 | uint32_t srcreg = (opcode & 7); | |
35572 | uint32_t dstreg = (opcode >> 9) & 7; | |
35573 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
35574 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
35575 | if ((srca & 1) != 0) { | |
35576 | last_fault_for_exception_3 = srca; | |
35577 | last_op_for_exception_3 = opcode; | |
35578 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
35579 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
35580 | goto endlabel2053; | |
35581 | } | |
35582 | {{ int16_t src = m68k_read_memory_16(srca); | |
35583 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
35584 | if ((dsta & 1) != 0) { | |
35585 | last_fault_for_exception_3 = dsta; | |
35586 | last_op_for_exception_3 = opcode; | |
35587 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
35588 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
35589 | goto endlabel2053; | |
35590 | } | |
35591 | { CLEAR_CZNV; | |
35592 | SET_ZFLG (((int16_t)(src)) == 0); | |
35593 | SET_NFLG (((int16_t)(src)) < 0); | |
35594 | m68k_incpc(2); | |
35595 | fill_prefetch_2 (); | |
35596 | m68k_write_memory_16(dsta,src); | |
35597 | }}}}}}endlabel2053: ; | |
35598 | return 12; | |
35599 | } | |
35600 | unsigned long CPUFUNC(op_3098_5)(uint32_t opcode) /* MOVE */ | |
35601 | { | |
35602 | uint32_t srcreg = (opcode & 7); | |
35603 | uint32_t dstreg = (opcode >> 9) & 7; | |
35604 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
35605 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
35606 | if ((srca & 1) != 0) { | |
35607 | last_fault_for_exception_3 = srca; | |
35608 | last_op_for_exception_3 = opcode; | |
35609 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
35610 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
35611 | goto endlabel2054; | |
35612 | } | |
35613 | {{ int16_t src = m68k_read_memory_16(srca); | |
35614 | m68k_areg(regs, srcreg) += 2; | |
35615 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
35616 | if ((dsta & 1) != 0) { | |
35617 | last_fault_for_exception_3 = dsta; | |
35618 | last_op_for_exception_3 = opcode; | |
35619 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
35620 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
35621 | goto endlabel2054; | |
35622 | } | |
35623 | { CLEAR_CZNV; | |
35624 | SET_ZFLG (((int16_t)(src)) == 0); | |
35625 | SET_NFLG (((int16_t)(src)) < 0); | |
35626 | m68k_incpc(2); | |
35627 | fill_prefetch_2 (); | |
35628 | m68k_write_memory_16(dsta,src); | |
35629 | }}}}}}endlabel2054: ; | |
35630 | return 12; | |
35631 | } | |
35632 | unsigned long CPUFUNC(op_30a0_5)(uint32_t opcode) /* MOVE */ | |
35633 | { | |
35634 | uint32_t srcreg = (opcode & 7); | |
35635 | uint32_t dstreg = (opcode >> 9) & 7; | |
35636 | OpcodeFamily = 30; CurrentInstrCycles = 14; | |
35637 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
35638 | if ((srca & 1) != 0) { | |
35639 | last_fault_for_exception_3 = srca; | |
35640 | last_op_for_exception_3 = opcode; | |
35641 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
35642 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
35643 | goto endlabel2055; | |
35644 | } | |
35645 | {{ int16_t src = m68k_read_memory_16(srca); | |
35646 | m68k_areg (regs, srcreg) = srca; | |
35647 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
35648 | if ((dsta & 1) != 0) { | |
35649 | last_fault_for_exception_3 = dsta; | |
35650 | last_op_for_exception_3 = opcode; | |
35651 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
35652 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
35653 | goto endlabel2055; | |
35654 | } | |
35655 | { CLEAR_CZNV; | |
35656 | SET_ZFLG (((int16_t)(src)) == 0); | |
35657 | SET_NFLG (((int16_t)(src)) < 0); | |
35658 | m68k_incpc(2); | |
35659 | fill_prefetch_2 (); | |
35660 | m68k_write_memory_16(dsta,src); | |
35661 | }}}}}}endlabel2055: ; | |
35662 | return 14; | |
35663 | } | |
35664 | unsigned long CPUFUNC(op_30a8_5)(uint32_t opcode) /* MOVE */ | |
35665 | { | |
35666 | uint32_t srcreg = (opcode & 7); | |
35667 | uint32_t dstreg = (opcode >> 9) & 7; | |
35668 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
35669 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
35670 | if ((srca & 1) != 0) { | |
35671 | last_fault_for_exception_3 = srca; | |
35672 | last_op_for_exception_3 = opcode; | |
35673 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
35674 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
35675 | goto endlabel2056; | |
35676 | } | |
35677 | {{ int16_t src = m68k_read_memory_16(srca); | |
35678 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
35679 | if ((dsta & 1) != 0) { | |
35680 | last_fault_for_exception_3 = dsta; | |
35681 | last_op_for_exception_3 = opcode; | |
35682 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
35683 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
35684 | goto endlabel2056; | |
35685 | } | |
35686 | { CLEAR_CZNV; | |
35687 | SET_ZFLG (((int16_t)(src)) == 0); | |
35688 | SET_NFLG (((int16_t)(src)) < 0); | |
35689 | m68k_incpc(4); | |
35690 | fill_prefetch_0 (); | |
35691 | m68k_write_memory_16(dsta,src); | |
35692 | }}}}}}endlabel2056: ; | |
35693 | return 16; | |
35694 | } | |
35695 | unsigned long CPUFUNC(op_30b0_5)(uint32_t opcode) /* MOVE */ | |
35696 | { | |
35697 | uint32_t srcreg = (opcode & 7); | |
35698 | uint32_t dstreg = (opcode >> 9) & 7; | |
35699 | OpcodeFamily = 30; CurrentInstrCycles = 18; | |
35700 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
35701 | BusCyclePenalty += 2; | |
35702 | if ((srca & 1) != 0) { | |
35703 | last_fault_for_exception_3 = srca; | |
35704 | last_op_for_exception_3 = opcode; | |
35705 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
35706 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
35707 | goto endlabel2057; | |
35708 | } | |
35709 | {{ int16_t src = m68k_read_memory_16(srca); | |
35710 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
35711 | if ((dsta & 1) != 0) { | |
35712 | last_fault_for_exception_3 = dsta; | |
35713 | last_op_for_exception_3 = opcode; | |
35714 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
35715 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
35716 | goto endlabel2057; | |
35717 | } | |
35718 | { CLEAR_CZNV; | |
35719 | SET_ZFLG (((int16_t)(src)) == 0); | |
35720 | SET_NFLG (((int16_t)(src)) < 0); | |
35721 | m68k_incpc(4); | |
35722 | fill_prefetch_0 (); | |
35723 | m68k_write_memory_16(dsta,src); | |
35724 | }}}}}}endlabel2057: ; | |
35725 | return 18; | |
35726 | } | |
35727 | unsigned long CPUFUNC(op_30b8_5)(uint32_t opcode) /* MOVE */ | |
35728 | { | |
35729 | uint32_t dstreg = (opcode >> 9) & 7; | |
35730 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
35731 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
35732 | if ((srca & 1) != 0) { | |
35733 | last_fault_for_exception_3 = srca; | |
35734 | last_op_for_exception_3 = opcode; | |
35735 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
35736 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
35737 | goto endlabel2058; | |
35738 | } | |
35739 | {{ int16_t src = m68k_read_memory_16(srca); | |
35740 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
35741 | if ((dsta & 1) != 0) { | |
35742 | last_fault_for_exception_3 = dsta; | |
35743 | last_op_for_exception_3 = opcode; | |
35744 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
35745 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
35746 | goto endlabel2058; | |
35747 | } | |
35748 | { CLEAR_CZNV; | |
35749 | SET_ZFLG (((int16_t)(src)) == 0); | |
35750 | SET_NFLG (((int16_t)(src)) < 0); | |
35751 | m68k_incpc(4); | |
35752 | fill_prefetch_0 (); | |
35753 | m68k_write_memory_16(dsta,src); | |
35754 | }}}}}}endlabel2058: ; | |
35755 | return 16; | |
35756 | } | |
35757 | unsigned long CPUFUNC(op_30b9_5)(uint32_t opcode) /* MOVE */ | |
35758 | { | |
35759 | uint32_t dstreg = (opcode >> 9) & 7; | |
35760 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
35761 | {{ uint32_t srca = get_ilong_prefetch(2); | |
35762 | if ((srca & 1) != 0) { | |
35763 | last_fault_for_exception_3 = srca; | |
35764 | last_op_for_exception_3 = opcode; | |
35765 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
35766 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
35767 | goto endlabel2059; | |
35768 | } | |
35769 | {{ int16_t src = m68k_read_memory_16(srca); | |
35770 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
35771 | if ((dsta & 1) != 0) { | |
35772 | last_fault_for_exception_3 = dsta; | |
35773 | last_op_for_exception_3 = opcode; | |
35774 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
35775 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
35776 | goto endlabel2059; | |
35777 | } | |
35778 | { CLEAR_CZNV; | |
35779 | SET_ZFLG (((int16_t)(src)) == 0); | |
35780 | SET_NFLG (((int16_t)(src)) < 0); | |
35781 | m68k_incpc(6); | |
35782 | fill_prefetch_0 (); | |
35783 | m68k_write_memory_16(dsta,src); | |
35784 | }}}}}}endlabel2059: ; | |
35785 | return 20; | |
35786 | } | |
35787 | unsigned long CPUFUNC(op_30ba_5)(uint32_t opcode) /* MOVE */ | |
35788 | { | |
35789 | uint32_t dstreg = (opcode >> 9) & 7; | |
35790 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
35791 | {{ uint32_t srca = m68k_getpc () + 2; | |
35792 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
35793 | if ((srca & 1) != 0) { | |
35794 | last_fault_for_exception_3 = srca; | |
35795 | last_op_for_exception_3 = opcode; | |
35796 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
35797 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
35798 | goto endlabel2060; | |
35799 | } | |
35800 | {{ int16_t src = m68k_read_memory_16(srca); | |
35801 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
35802 | if ((dsta & 1) != 0) { | |
35803 | last_fault_for_exception_3 = dsta; | |
35804 | last_op_for_exception_3 = opcode; | |
35805 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
35806 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
35807 | goto endlabel2060; | |
35808 | } | |
35809 | { CLEAR_CZNV; | |
35810 | SET_ZFLG (((int16_t)(src)) == 0); | |
35811 | SET_NFLG (((int16_t)(src)) < 0); | |
35812 | m68k_incpc(4); | |
35813 | fill_prefetch_0 (); | |
35814 | m68k_write_memory_16(dsta,src); | |
35815 | }}}}}}endlabel2060: ; | |
35816 | return 16; | |
35817 | } | |
35818 | unsigned long CPUFUNC(op_30bb_5)(uint32_t opcode) /* MOVE */ | |
35819 | { | |
35820 | uint32_t dstreg = (opcode >> 9) & 7; | |
35821 | OpcodeFamily = 30; CurrentInstrCycles = 18; | |
35822 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
35823 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
35824 | BusCyclePenalty += 2; | |
35825 | if ((srca & 1) != 0) { | |
35826 | last_fault_for_exception_3 = srca; | |
35827 | last_op_for_exception_3 = opcode; | |
35828 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
35829 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
35830 | goto endlabel2061; | |
35831 | } | |
35832 | {{ int16_t src = m68k_read_memory_16(srca); | |
35833 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
35834 | if ((dsta & 1) != 0) { | |
35835 | last_fault_for_exception_3 = dsta; | |
35836 | last_op_for_exception_3 = opcode; | |
35837 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
35838 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
35839 | goto endlabel2061; | |
35840 | } | |
35841 | { CLEAR_CZNV; | |
35842 | SET_ZFLG (((int16_t)(src)) == 0); | |
35843 | SET_NFLG (((int16_t)(src)) < 0); | |
35844 | m68k_incpc(4); | |
35845 | fill_prefetch_0 (); | |
35846 | m68k_write_memory_16(dsta,src); | |
35847 | }}}}}}endlabel2061: ; | |
35848 | return 18; | |
35849 | } | |
35850 | unsigned long CPUFUNC(op_30bc_5)(uint32_t opcode) /* MOVE */ | |
35851 | { | |
35852 | uint32_t dstreg = (opcode >> 9) & 7; | |
35853 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
35854 | {{ int16_t src = get_iword_prefetch(2); | |
35855 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
35856 | if ((dsta & 1) != 0) { | |
35857 | last_fault_for_exception_3 = dsta; | |
35858 | last_op_for_exception_3 = opcode; | |
35859 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
35860 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
35861 | goto endlabel2062; | |
35862 | } | |
35863 | { CLEAR_CZNV; | |
35864 | SET_ZFLG (((int16_t)(src)) == 0); | |
35865 | SET_NFLG (((int16_t)(src)) < 0); | |
35866 | m68k_incpc(4); | |
35867 | fill_prefetch_0 (); | |
35868 | m68k_write_memory_16(dsta,src); | |
35869 | }}}}endlabel2062: ; | |
35870 | return 12; | |
35871 | } | |
35872 | unsigned long CPUFUNC(op_30c0_5)(uint32_t opcode) /* MOVE */ | |
35873 | { | |
35874 | uint32_t srcreg = (opcode & 7); | |
35875 | uint32_t dstreg = (opcode >> 9) & 7; | |
35876 | OpcodeFamily = 30; CurrentInstrCycles = 8; | |
35877 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
35878 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
35879 | if ((dsta & 1) != 0) { | |
35880 | last_fault_for_exception_3 = dsta; | |
35881 | last_op_for_exception_3 = opcode; | |
35882 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
35883 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
35884 | goto endlabel2063; | |
35885 | } | |
35886 | { m68k_areg(regs, dstreg) += 2; | |
35887 | CLEAR_CZNV; | |
35888 | SET_ZFLG (((int16_t)(src)) == 0); | |
35889 | SET_NFLG (((int16_t)(src)) < 0); | |
35890 | m68k_incpc(2); | |
35891 | fill_prefetch_2 (); | |
35892 | m68k_write_memory_16(dsta,src); | |
35893 | }}}}endlabel2063: ; | |
35894 | return 8; | |
35895 | } | |
35896 | unsigned long CPUFUNC(op_30c8_5)(uint32_t opcode) /* MOVE */ | |
35897 | { | |
35898 | uint32_t srcreg = (opcode & 7); | |
35899 | uint32_t dstreg = (opcode >> 9) & 7; | |
35900 | OpcodeFamily = 30; CurrentInstrCycles = 8; | |
35901 | {{ int16_t src = m68k_areg(regs, srcreg); | |
35902 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
35903 | if ((dsta & 1) != 0) { | |
35904 | last_fault_for_exception_3 = dsta; | |
35905 | last_op_for_exception_3 = opcode; | |
35906 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
35907 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
35908 | goto endlabel2064; | |
35909 | } | |
35910 | { m68k_areg(regs, dstreg) += 2; | |
35911 | CLEAR_CZNV; | |
35912 | SET_ZFLG (((int16_t)(src)) == 0); | |
35913 | SET_NFLG (((int16_t)(src)) < 0); | |
35914 | m68k_incpc(2); | |
35915 | fill_prefetch_2 (); | |
35916 | m68k_write_memory_16(dsta,src); | |
35917 | }}}}endlabel2064: ; | |
35918 | return 8; | |
35919 | } | |
35920 | unsigned long CPUFUNC(op_30d0_5)(uint32_t opcode) /* MOVE */ | |
35921 | { | |
35922 | uint32_t srcreg = (opcode & 7); | |
35923 | uint32_t dstreg = (opcode >> 9) & 7; | |
35924 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
35925 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
35926 | if ((srca & 1) != 0) { | |
35927 | last_fault_for_exception_3 = srca; | |
35928 | last_op_for_exception_3 = opcode; | |
35929 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
35930 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
35931 | goto endlabel2065; | |
35932 | } | |
35933 | {{ int16_t src = m68k_read_memory_16(srca); | |
35934 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
35935 | if ((dsta & 1) != 0) { | |
35936 | last_fault_for_exception_3 = dsta; | |
35937 | last_op_for_exception_3 = opcode; | |
35938 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
35939 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
35940 | goto endlabel2065; | |
35941 | } | |
35942 | { m68k_areg(regs, dstreg) += 2; | |
35943 | CLEAR_CZNV; | |
35944 | SET_ZFLG (((int16_t)(src)) == 0); | |
35945 | SET_NFLG (((int16_t)(src)) < 0); | |
35946 | m68k_incpc(2); | |
35947 | fill_prefetch_2 (); | |
35948 | m68k_write_memory_16(dsta,src); | |
35949 | }}}}}}endlabel2065: ; | |
35950 | return 12; | |
35951 | } | |
35952 | unsigned long CPUFUNC(op_30d8_5)(uint32_t opcode) /* MOVE */ | |
35953 | { | |
35954 | uint32_t srcreg = (opcode & 7); | |
35955 | uint32_t dstreg = (opcode >> 9) & 7; | |
35956 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
35957 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
35958 | if ((srca & 1) != 0) { | |
35959 | last_fault_for_exception_3 = srca; | |
35960 | last_op_for_exception_3 = opcode; | |
35961 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
35962 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
35963 | goto endlabel2066; | |
35964 | } | |
35965 | {{ int16_t src = m68k_read_memory_16(srca); | |
35966 | m68k_areg(regs, srcreg) += 2; | |
35967 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
35968 | if ((dsta & 1) != 0) { | |
35969 | last_fault_for_exception_3 = dsta; | |
35970 | last_op_for_exception_3 = opcode; | |
35971 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
35972 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
35973 | goto endlabel2066; | |
35974 | } | |
35975 | { m68k_areg(regs, dstreg) += 2; | |
35976 | CLEAR_CZNV; | |
35977 | SET_ZFLG (((int16_t)(src)) == 0); | |
35978 | SET_NFLG (((int16_t)(src)) < 0); | |
35979 | m68k_incpc(2); | |
35980 | fill_prefetch_2 (); | |
35981 | m68k_write_memory_16(dsta,src); | |
35982 | }}}}}}endlabel2066: ; | |
35983 | return 12; | |
35984 | } | |
35985 | unsigned long CPUFUNC(op_30e0_5)(uint32_t opcode) /* MOVE */ | |
35986 | { | |
35987 | uint32_t srcreg = (opcode & 7); | |
35988 | uint32_t dstreg = (opcode >> 9) & 7; | |
35989 | OpcodeFamily = 30; CurrentInstrCycles = 14; | |
35990 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
35991 | if ((srca & 1) != 0) { | |
35992 | last_fault_for_exception_3 = srca; | |
35993 | last_op_for_exception_3 = opcode; | |
35994 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
35995 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
35996 | goto endlabel2067; | |
35997 | } | |
35998 | {{ int16_t src = m68k_read_memory_16(srca); | |
35999 | m68k_areg (regs, srcreg) = srca; | |
36000 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
36001 | if ((dsta & 1) != 0) { | |
36002 | last_fault_for_exception_3 = dsta; | |
36003 | last_op_for_exception_3 = opcode; | |
36004 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
36005 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36006 | goto endlabel2067; | |
36007 | } | |
36008 | { m68k_areg(regs, dstreg) += 2; | |
36009 | CLEAR_CZNV; | |
36010 | SET_ZFLG (((int16_t)(src)) == 0); | |
36011 | SET_NFLG (((int16_t)(src)) < 0); | |
36012 | m68k_incpc(2); | |
36013 | fill_prefetch_2 (); | |
36014 | m68k_write_memory_16(dsta,src); | |
36015 | }}}}}}endlabel2067: ; | |
36016 | return 14; | |
36017 | } | |
36018 | unsigned long CPUFUNC(op_30e8_5)(uint32_t opcode) /* MOVE */ | |
36019 | { | |
36020 | uint32_t srcreg = (opcode & 7); | |
36021 | uint32_t dstreg = (opcode >> 9) & 7; | |
36022 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
36023 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
36024 | if ((srca & 1) != 0) { | |
36025 | last_fault_for_exception_3 = srca; | |
36026 | last_op_for_exception_3 = opcode; | |
36027 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
36028 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36029 | goto endlabel2068; | |
36030 | } | |
36031 | {{ int16_t src = m68k_read_memory_16(srca); | |
36032 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
36033 | if ((dsta & 1) != 0) { | |
36034 | last_fault_for_exception_3 = dsta; | |
36035 | last_op_for_exception_3 = opcode; | |
36036 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
36037 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36038 | goto endlabel2068; | |
36039 | } | |
36040 | { m68k_areg(regs, dstreg) += 2; | |
36041 | CLEAR_CZNV; | |
36042 | SET_ZFLG (((int16_t)(src)) == 0); | |
36043 | SET_NFLG (((int16_t)(src)) < 0); | |
36044 | m68k_incpc(4); | |
36045 | fill_prefetch_0 (); | |
36046 | m68k_write_memory_16(dsta,src); | |
36047 | }}}}}}endlabel2068: ; | |
36048 | return 16; | |
36049 | } | |
36050 | unsigned long CPUFUNC(op_30f0_5)(uint32_t opcode) /* MOVE */ | |
36051 | { | |
36052 | uint32_t srcreg = (opcode & 7); | |
36053 | uint32_t dstreg = (opcode >> 9) & 7; | |
36054 | OpcodeFamily = 30; CurrentInstrCycles = 18; | |
36055 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
36056 | BusCyclePenalty += 2; | |
36057 | if ((srca & 1) != 0) { | |
36058 | last_fault_for_exception_3 = srca; | |
36059 | last_op_for_exception_3 = opcode; | |
36060 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
36061 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36062 | goto endlabel2069; | |
36063 | } | |
36064 | {{ int16_t src = m68k_read_memory_16(srca); | |
36065 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
36066 | if ((dsta & 1) != 0) { | |
36067 | last_fault_for_exception_3 = dsta; | |
36068 | last_op_for_exception_3 = opcode; | |
36069 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
36070 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36071 | goto endlabel2069; | |
36072 | } | |
36073 | { m68k_areg(regs, dstreg) += 2; | |
36074 | CLEAR_CZNV; | |
36075 | SET_ZFLG (((int16_t)(src)) == 0); | |
36076 | SET_NFLG (((int16_t)(src)) < 0); | |
36077 | m68k_incpc(4); | |
36078 | fill_prefetch_0 (); | |
36079 | m68k_write_memory_16(dsta,src); | |
36080 | }}}}}}endlabel2069: ; | |
36081 | return 18; | |
36082 | } | |
36083 | unsigned long CPUFUNC(op_30f8_5)(uint32_t opcode) /* MOVE */ | |
36084 | { | |
36085 | uint32_t dstreg = (opcode >> 9) & 7; | |
36086 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
36087 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
36088 | if ((srca & 1) != 0) { | |
36089 | last_fault_for_exception_3 = srca; | |
36090 | last_op_for_exception_3 = opcode; | |
36091 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
36092 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36093 | goto endlabel2070; | |
36094 | } | |
36095 | {{ int16_t src = m68k_read_memory_16(srca); | |
36096 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
36097 | if ((dsta & 1) != 0) { | |
36098 | last_fault_for_exception_3 = dsta; | |
36099 | last_op_for_exception_3 = opcode; | |
36100 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
36101 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36102 | goto endlabel2070; | |
36103 | } | |
36104 | { m68k_areg(regs, dstreg) += 2; | |
36105 | CLEAR_CZNV; | |
36106 | SET_ZFLG (((int16_t)(src)) == 0); | |
36107 | SET_NFLG (((int16_t)(src)) < 0); | |
36108 | m68k_incpc(4); | |
36109 | fill_prefetch_0 (); | |
36110 | m68k_write_memory_16(dsta,src); | |
36111 | }}}}}}endlabel2070: ; | |
36112 | return 16; | |
36113 | } | |
36114 | unsigned long CPUFUNC(op_30f9_5)(uint32_t opcode) /* MOVE */ | |
36115 | { | |
36116 | uint32_t dstreg = (opcode >> 9) & 7; | |
36117 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
36118 | {{ uint32_t srca = get_ilong_prefetch(2); | |
36119 | if ((srca & 1) != 0) { | |
36120 | last_fault_for_exception_3 = srca; | |
36121 | last_op_for_exception_3 = opcode; | |
36122 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
36123 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36124 | goto endlabel2071; | |
36125 | } | |
36126 | {{ int16_t src = m68k_read_memory_16(srca); | |
36127 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
36128 | if ((dsta & 1) != 0) { | |
36129 | last_fault_for_exception_3 = dsta; | |
36130 | last_op_for_exception_3 = opcode; | |
36131 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
36132 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36133 | goto endlabel2071; | |
36134 | } | |
36135 | { m68k_areg(regs, dstreg) += 2; | |
36136 | CLEAR_CZNV; | |
36137 | SET_ZFLG (((int16_t)(src)) == 0); | |
36138 | SET_NFLG (((int16_t)(src)) < 0); | |
36139 | m68k_incpc(6); | |
36140 | fill_prefetch_0 (); | |
36141 | m68k_write_memory_16(dsta,src); | |
36142 | }}}}}}endlabel2071: ; | |
36143 | return 20; | |
36144 | } | |
36145 | unsigned long CPUFUNC(op_30fa_5)(uint32_t opcode) /* MOVE */ | |
36146 | { | |
36147 | uint32_t dstreg = (opcode >> 9) & 7; | |
36148 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
36149 | {{ uint32_t srca = m68k_getpc () + 2; | |
36150 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
36151 | if ((srca & 1) != 0) { | |
36152 | last_fault_for_exception_3 = srca; | |
36153 | last_op_for_exception_3 = opcode; | |
36154 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
36155 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36156 | goto endlabel2072; | |
36157 | } | |
36158 | {{ int16_t src = m68k_read_memory_16(srca); | |
36159 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
36160 | if ((dsta & 1) != 0) { | |
36161 | last_fault_for_exception_3 = dsta; | |
36162 | last_op_for_exception_3 = opcode; | |
36163 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
36164 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36165 | goto endlabel2072; | |
36166 | } | |
36167 | { m68k_areg(regs, dstreg) += 2; | |
36168 | CLEAR_CZNV; | |
36169 | SET_ZFLG (((int16_t)(src)) == 0); | |
36170 | SET_NFLG (((int16_t)(src)) < 0); | |
36171 | m68k_incpc(4); | |
36172 | fill_prefetch_0 (); | |
36173 | m68k_write_memory_16(dsta,src); | |
36174 | }}}}}}endlabel2072: ; | |
36175 | return 16; | |
36176 | } | |
36177 | unsigned long CPUFUNC(op_30fb_5)(uint32_t opcode) /* MOVE */ | |
36178 | { | |
36179 | uint32_t dstreg = (opcode >> 9) & 7; | |
36180 | OpcodeFamily = 30; CurrentInstrCycles = 18; | |
36181 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
36182 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
36183 | BusCyclePenalty += 2; | |
36184 | if ((srca & 1) != 0) { | |
36185 | last_fault_for_exception_3 = srca; | |
36186 | last_op_for_exception_3 = opcode; | |
36187 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
36188 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36189 | goto endlabel2073; | |
36190 | } | |
36191 | {{ int16_t src = m68k_read_memory_16(srca); | |
36192 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
36193 | if ((dsta & 1) != 0) { | |
36194 | last_fault_for_exception_3 = dsta; | |
36195 | last_op_for_exception_3 = opcode; | |
36196 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
36197 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36198 | goto endlabel2073; | |
36199 | } | |
36200 | { m68k_areg(regs, dstreg) += 2; | |
36201 | CLEAR_CZNV; | |
36202 | SET_ZFLG (((int16_t)(src)) == 0); | |
36203 | SET_NFLG (((int16_t)(src)) < 0); | |
36204 | m68k_incpc(4); | |
36205 | fill_prefetch_0 (); | |
36206 | m68k_write_memory_16(dsta,src); | |
36207 | }}}}}}endlabel2073: ; | |
36208 | return 18; | |
36209 | } | |
36210 | unsigned long CPUFUNC(op_30fc_5)(uint32_t opcode) /* MOVE */ | |
36211 | { | |
36212 | uint32_t dstreg = (opcode >> 9) & 7; | |
36213 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
36214 | {{ int16_t src = get_iword_prefetch(2); | |
36215 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
36216 | if ((dsta & 1) != 0) { | |
36217 | last_fault_for_exception_3 = dsta; | |
36218 | last_op_for_exception_3 = opcode; | |
36219 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
36220 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36221 | goto endlabel2074; | |
36222 | } | |
36223 | { m68k_areg(regs, dstreg) += 2; | |
36224 | CLEAR_CZNV; | |
36225 | SET_ZFLG (((int16_t)(src)) == 0); | |
36226 | SET_NFLG (((int16_t)(src)) < 0); | |
36227 | m68k_incpc(4); | |
36228 | fill_prefetch_0 (); | |
36229 | m68k_write_memory_16(dsta,src); | |
36230 | }}}}endlabel2074: ; | |
36231 | return 12; | |
36232 | } | |
36233 | unsigned long CPUFUNC(op_3100_5)(uint32_t opcode) /* MOVE */ | |
36234 | { | |
36235 | uint32_t srcreg = (opcode & 7); | |
36236 | uint32_t dstreg = (opcode >> 9) & 7; | |
36237 | OpcodeFamily = 30; CurrentInstrCycles = 8; | |
36238 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
36239 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
36240 | if ((dsta & 1) != 0) { | |
36241 | last_fault_for_exception_3 = dsta; | |
36242 | last_op_for_exception_3 = opcode; | |
36243 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
36244 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36245 | goto endlabel2075; | |
36246 | } | |
36247 | { m68k_areg (regs, dstreg) = dsta; | |
36248 | CLEAR_CZNV; | |
36249 | SET_ZFLG (((int16_t)(src)) == 0); | |
36250 | SET_NFLG (((int16_t)(src)) < 0); | |
36251 | m68k_incpc(2); | |
36252 | fill_prefetch_2 (); | |
36253 | m68k_write_memory_16(dsta,src); | |
36254 | }}}}endlabel2075: ; | |
36255 | return 8; | |
36256 | } | |
36257 | unsigned long CPUFUNC(op_3108_5)(uint32_t opcode) /* MOVE */ | |
36258 | { | |
36259 | uint32_t srcreg = (opcode & 7); | |
36260 | uint32_t dstreg = (opcode >> 9) & 7; | |
36261 | OpcodeFamily = 30; CurrentInstrCycles = 8; | |
36262 | {{ int16_t src = m68k_areg(regs, srcreg); | |
36263 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
36264 | if ((dsta & 1) != 0) { | |
36265 | last_fault_for_exception_3 = dsta; | |
36266 | last_op_for_exception_3 = opcode; | |
36267 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
36268 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36269 | goto endlabel2076; | |
36270 | } | |
36271 | { m68k_areg (regs, dstreg) = dsta; | |
36272 | CLEAR_CZNV; | |
36273 | SET_ZFLG (((int16_t)(src)) == 0); | |
36274 | SET_NFLG (((int16_t)(src)) < 0); | |
36275 | m68k_incpc(2); | |
36276 | fill_prefetch_2 (); | |
36277 | m68k_write_memory_16(dsta,src); | |
36278 | }}}}endlabel2076: ; | |
36279 | return 8; | |
36280 | } | |
36281 | unsigned long CPUFUNC(op_3110_5)(uint32_t opcode) /* MOVE */ | |
36282 | { | |
36283 | uint32_t srcreg = (opcode & 7); | |
36284 | uint32_t dstreg = (opcode >> 9) & 7; | |
36285 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
36286 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
36287 | if ((srca & 1) != 0) { | |
36288 | last_fault_for_exception_3 = srca; | |
36289 | last_op_for_exception_3 = opcode; | |
36290 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
36291 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36292 | goto endlabel2077; | |
36293 | } | |
36294 | {{ int16_t src = m68k_read_memory_16(srca); | |
36295 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
36296 | if ((dsta & 1) != 0) { | |
36297 | last_fault_for_exception_3 = dsta; | |
36298 | last_op_for_exception_3 = opcode; | |
36299 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
36300 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36301 | goto endlabel2077; | |
36302 | } | |
36303 | { m68k_areg (regs, dstreg) = dsta; | |
36304 | CLEAR_CZNV; | |
36305 | SET_ZFLG (((int16_t)(src)) == 0); | |
36306 | SET_NFLG (((int16_t)(src)) < 0); | |
36307 | m68k_incpc(2); | |
36308 | fill_prefetch_2 (); | |
36309 | m68k_write_memory_16(dsta,src); | |
36310 | }}}}}}endlabel2077: ; | |
36311 | return 12; | |
36312 | } | |
36313 | unsigned long CPUFUNC(op_3118_5)(uint32_t opcode) /* MOVE */ | |
36314 | { | |
36315 | uint32_t srcreg = (opcode & 7); | |
36316 | uint32_t dstreg = (opcode >> 9) & 7; | |
36317 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
36318 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
36319 | if ((srca & 1) != 0) { | |
36320 | last_fault_for_exception_3 = srca; | |
36321 | last_op_for_exception_3 = opcode; | |
36322 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
36323 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36324 | goto endlabel2078; | |
36325 | } | |
36326 | {{ int16_t src = m68k_read_memory_16(srca); | |
36327 | m68k_areg(regs, srcreg) += 2; | |
36328 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
36329 | if ((dsta & 1) != 0) { | |
36330 | last_fault_for_exception_3 = dsta; | |
36331 | last_op_for_exception_3 = opcode; | |
36332 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
36333 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36334 | goto endlabel2078; | |
36335 | } | |
36336 | { m68k_areg (regs, dstreg) = dsta; | |
36337 | CLEAR_CZNV; | |
36338 | SET_ZFLG (((int16_t)(src)) == 0); | |
36339 | SET_NFLG (((int16_t)(src)) < 0); | |
36340 | m68k_incpc(2); | |
36341 | fill_prefetch_2 (); | |
36342 | m68k_write_memory_16(dsta,src); | |
36343 | }}}}}}endlabel2078: ; | |
36344 | return 12; | |
36345 | } | |
36346 | unsigned long CPUFUNC(op_3120_5)(uint32_t opcode) /* MOVE */ | |
36347 | { | |
36348 | uint32_t srcreg = (opcode & 7); | |
36349 | uint32_t dstreg = (opcode >> 9) & 7; | |
36350 | OpcodeFamily = 30; CurrentInstrCycles = 14; | |
36351 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
36352 | if ((srca & 1) != 0) { | |
36353 | last_fault_for_exception_3 = srca; | |
36354 | last_op_for_exception_3 = opcode; | |
36355 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
36356 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36357 | goto endlabel2079; | |
36358 | } | |
36359 | {{ int16_t src = m68k_read_memory_16(srca); | |
36360 | m68k_areg (regs, srcreg) = srca; | |
36361 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
36362 | if ((dsta & 1) != 0) { | |
36363 | last_fault_for_exception_3 = dsta; | |
36364 | last_op_for_exception_3 = opcode; | |
36365 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
36366 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36367 | goto endlabel2079; | |
36368 | } | |
36369 | { m68k_areg (regs, dstreg) = dsta; | |
36370 | CLEAR_CZNV; | |
36371 | SET_ZFLG (((int16_t)(src)) == 0); | |
36372 | SET_NFLG (((int16_t)(src)) < 0); | |
36373 | m68k_incpc(2); | |
36374 | fill_prefetch_2 (); | |
36375 | m68k_write_memory_16(dsta,src); | |
36376 | }}}}}}endlabel2079: ; | |
36377 | return 14; | |
36378 | } | |
36379 | unsigned long CPUFUNC(op_3128_5)(uint32_t opcode) /* MOVE */ | |
36380 | { | |
36381 | uint32_t srcreg = (opcode & 7); | |
36382 | uint32_t dstreg = (opcode >> 9) & 7; | |
36383 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
36384 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
36385 | if ((srca & 1) != 0) { | |
36386 | last_fault_for_exception_3 = srca; | |
36387 | last_op_for_exception_3 = opcode; | |
36388 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
36389 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36390 | goto endlabel2080; | |
36391 | } | |
36392 | {{ int16_t src = m68k_read_memory_16(srca); | |
36393 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
36394 | if ((dsta & 1) != 0) { | |
36395 | last_fault_for_exception_3 = dsta; | |
36396 | last_op_for_exception_3 = opcode; | |
36397 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
36398 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36399 | goto endlabel2080; | |
36400 | } | |
36401 | { m68k_areg (regs, dstreg) = dsta; | |
36402 | CLEAR_CZNV; | |
36403 | SET_ZFLG (((int16_t)(src)) == 0); | |
36404 | SET_NFLG (((int16_t)(src)) < 0); | |
36405 | m68k_incpc(4); | |
36406 | fill_prefetch_0 (); | |
36407 | m68k_write_memory_16(dsta,src); | |
36408 | }}}}}}endlabel2080: ; | |
36409 | return 16; | |
36410 | } | |
36411 | unsigned long CPUFUNC(op_3130_5)(uint32_t opcode) /* MOVE */ | |
36412 | { | |
36413 | uint32_t srcreg = (opcode & 7); | |
36414 | uint32_t dstreg = (opcode >> 9) & 7; | |
36415 | OpcodeFamily = 30; CurrentInstrCycles = 18; | |
36416 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
36417 | BusCyclePenalty += 2; | |
36418 | if ((srca & 1) != 0) { | |
36419 | last_fault_for_exception_3 = srca; | |
36420 | last_op_for_exception_3 = opcode; | |
36421 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
36422 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36423 | goto endlabel2081; | |
36424 | } | |
36425 | {{ int16_t src = m68k_read_memory_16(srca); | |
36426 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
36427 | if ((dsta & 1) != 0) { | |
36428 | last_fault_for_exception_3 = dsta; | |
36429 | last_op_for_exception_3 = opcode; | |
36430 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
36431 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36432 | goto endlabel2081; | |
36433 | } | |
36434 | { m68k_areg (regs, dstreg) = dsta; | |
36435 | CLEAR_CZNV; | |
36436 | SET_ZFLG (((int16_t)(src)) == 0); | |
36437 | SET_NFLG (((int16_t)(src)) < 0); | |
36438 | m68k_incpc(4); | |
36439 | fill_prefetch_0 (); | |
36440 | m68k_write_memory_16(dsta,src); | |
36441 | }}}}}}endlabel2081: ; | |
36442 | return 18; | |
36443 | } | |
36444 | unsigned long CPUFUNC(op_3138_5)(uint32_t opcode) /* MOVE */ | |
36445 | { | |
36446 | uint32_t dstreg = (opcode >> 9) & 7; | |
36447 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
36448 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
36449 | if ((srca & 1) != 0) { | |
36450 | last_fault_for_exception_3 = srca; | |
36451 | last_op_for_exception_3 = opcode; | |
36452 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
36453 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36454 | goto endlabel2082; | |
36455 | } | |
36456 | {{ int16_t src = m68k_read_memory_16(srca); | |
36457 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
36458 | if ((dsta & 1) != 0) { | |
36459 | last_fault_for_exception_3 = dsta; | |
36460 | last_op_for_exception_3 = opcode; | |
36461 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
36462 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36463 | goto endlabel2082; | |
36464 | } | |
36465 | { m68k_areg (regs, dstreg) = dsta; | |
36466 | CLEAR_CZNV; | |
36467 | SET_ZFLG (((int16_t)(src)) == 0); | |
36468 | SET_NFLG (((int16_t)(src)) < 0); | |
36469 | m68k_incpc(4); | |
36470 | fill_prefetch_0 (); | |
36471 | m68k_write_memory_16(dsta,src); | |
36472 | }}}}}}endlabel2082: ; | |
36473 | return 16; | |
36474 | } | |
36475 | unsigned long CPUFUNC(op_3139_5)(uint32_t opcode) /* MOVE */ | |
36476 | { | |
36477 | uint32_t dstreg = (opcode >> 9) & 7; | |
36478 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
36479 | {{ uint32_t srca = get_ilong_prefetch(2); | |
36480 | if ((srca & 1) != 0) { | |
36481 | last_fault_for_exception_3 = srca; | |
36482 | last_op_for_exception_3 = opcode; | |
36483 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
36484 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36485 | goto endlabel2083; | |
36486 | } | |
36487 | {{ int16_t src = m68k_read_memory_16(srca); | |
36488 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
36489 | if ((dsta & 1) != 0) { | |
36490 | last_fault_for_exception_3 = dsta; | |
36491 | last_op_for_exception_3 = opcode; | |
36492 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
36493 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36494 | goto endlabel2083; | |
36495 | } | |
36496 | { m68k_areg (regs, dstreg) = dsta; | |
36497 | CLEAR_CZNV; | |
36498 | SET_ZFLG (((int16_t)(src)) == 0); | |
36499 | SET_NFLG (((int16_t)(src)) < 0); | |
36500 | m68k_incpc(6); | |
36501 | fill_prefetch_0 (); | |
36502 | m68k_write_memory_16(dsta,src); | |
36503 | }}}}}}endlabel2083: ; | |
36504 | return 20; | |
36505 | } | |
36506 | unsigned long CPUFUNC(op_313a_5)(uint32_t opcode) /* MOVE */ | |
36507 | { | |
36508 | uint32_t dstreg = (opcode >> 9) & 7; | |
36509 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
36510 | {{ uint32_t srca = m68k_getpc () + 2; | |
36511 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
36512 | if ((srca & 1) != 0) { | |
36513 | last_fault_for_exception_3 = srca; | |
36514 | last_op_for_exception_3 = opcode; | |
36515 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
36516 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36517 | goto endlabel2084; | |
36518 | } | |
36519 | {{ int16_t src = m68k_read_memory_16(srca); | |
36520 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
36521 | if ((dsta & 1) != 0) { | |
36522 | last_fault_for_exception_3 = dsta; | |
36523 | last_op_for_exception_3 = opcode; | |
36524 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
36525 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36526 | goto endlabel2084; | |
36527 | } | |
36528 | { m68k_areg (regs, dstreg) = dsta; | |
36529 | CLEAR_CZNV; | |
36530 | SET_ZFLG (((int16_t)(src)) == 0); | |
36531 | SET_NFLG (((int16_t)(src)) < 0); | |
36532 | m68k_incpc(4); | |
36533 | fill_prefetch_0 (); | |
36534 | m68k_write_memory_16(dsta,src); | |
36535 | }}}}}}endlabel2084: ; | |
36536 | return 16; | |
36537 | } | |
36538 | unsigned long CPUFUNC(op_313b_5)(uint32_t opcode) /* MOVE */ | |
36539 | { | |
36540 | uint32_t dstreg = (opcode >> 9) & 7; | |
36541 | OpcodeFamily = 30; CurrentInstrCycles = 18; | |
36542 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
36543 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
36544 | BusCyclePenalty += 2; | |
36545 | if ((srca & 1) != 0) { | |
36546 | last_fault_for_exception_3 = srca; | |
36547 | last_op_for_exception_3 = opcode; | |
36548 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
36549 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36550 | goto endlabel2085; | |
36551 | } | |
36552 | {{ int16_t src = m68k_read_memory_16(srca); | |
36553 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
36554 | if ((dsta & 1) != 0) { | |
36555 | last_fault_for_exception_3 = dsta; | |
36556 | last_op_for_exception_3 = opcode; | |
36557 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
36558 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36559 | goto endlabel2085; | |
36560 | } | |
36561 | { m68k_areg (regs, dstreg) = dsta; | |
36562 | CLEAR_CZNV; | |
36563 | SET_ZFLG (((int16_t)(src)) == 0); | |
36564 | SET_NFLG (((int16_t)(src)) < 0); | |
36565 | m68k_incpc(4); | |
36566 | fill_prefetch_0 (); | |
36567 | m68k_write_memory_16(dsta,src); | |
36568 | }}}}}}endlabel2085: ; | |
36569 | return 18; | |
36570 | } | |
36571 | unsigned long CPUFUNC(op_313c_5)(uint32_t opcode) /* MOVE */ | |
36572 | { | |
36573 | uint32_t dstreg = (opcode >> 9) & 7; | |
36574 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
36575 | {{ int16_t src = get_iword_prefetch(2); | |
36576 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
36577 | if ((dsta & 1) != 0) { | |
36578 | last_fault_for_exception_3 = dsta; | |
36579 | last_op_for_exception_3 = opcode; | |
36580 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
36581 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36582 | goto endlabel2086; | |
36583 | } | |
36584 | { m68k_areg (regs, dstreg) = dsta; | |
36585 | CLEAR_CZNV; | |
36586 | SET_ZFLG (((int16_t)(src)) == 0); | |
36587 | SET_NFLG (((int16_t)(src)) < 0); | |
36588 | m68k_incpc(4); | |
36589 | fill_prefetch_0 (); | |
36590 | m68k_write_memory_16(dsta,src); | |
36591 | }}}}endlabel2086: ; | |
36592 | return 12; | |
36593 | } | |
36594 | unsigned long CPUFUNC(op_3140_5)(uint32_t opcode) /* MOVE */ | |
36595 | { | |
36596 | uint32_t srcreg = (opcode & 7); | |
36597 | uint32_t dstreg = (opcode >> 9) & 7; | |
36598 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
36599 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
36600 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
36601 | if ((dsta & 1) != 0) { | |
36602 | last_fault_for_exception_3 = dsta; | |
36603 | last_op_for_exception_3 = opcode; | |
36604 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
36605 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36606 | goto endlabel2087; | |
36607 | } | |
36608 | { CLEAR_CZNV; | |
36609 | SET_ZFLG (((int16_t)(src)) == 0); | |
36610 | SET_NFLG (((int16_t)(src)) < 0); | |
36611 | m68k_incpc(4); | |
36612 | fill_prefetch_0 (); | |
36613 | m68k_write_memory_16(dsta,src); | |
36614 | }}}}endlabel2087: ; | |
36615 | return 12; | |
36616 | } | |
36617 | unsigned long CPUFUNC(op_3148_5)(uint32_t opcode) /* MOVE */ | |
36618 | { | |
36619 | uint32_t srcreg = (opcode & 7); | |
36620 | uint32_t dstreg = (opcode >> 9) & 7; | |
36621 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
36622 | {{ int16_t src = m68k_areg(regs, srcreg); | |
36623 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
36624 | if ((dsta & 1) != 0) { | |
36625 | last_fault_for_exception_3 = dsta; | |
36626 | last_op_for_exception_3 = opcode; | |
36627 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
36628 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36629 | goto endlabel2088; | |
36630 | } | |
36631 | { CLEAR_CZNV; | |
36632 | SET_ZFLG (((int16_t)(src)) == 0); | |
36633 | SET_NFLG (((int16_t)(src)) < 0); | |
36634 | m68k_incpc(4); | |
36635 | fill_prefetch_0 (); | |
36636 | m68k_write_memory_16(dsta,src); | |
36637 | }}}}endlabel2088: ; | |
36638 | return 12; | |
36639 | } | |
36640 | unsigned long CPUFUNC(op_3150_5)(uint32_t opcode) /* MOVE */ | |
36641 | { | |
36642 | uint32_t srcreg = (opcode & 7); | |
36643 | uint32_t dstreg = (opcode >> 9) & 7; | |
36644 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
36645 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
36646 | if ((srca & 1) != 0) { | |
36647 | last_fault_for_exception_3 = srca; | |
36648 | last_op_for_exception_3 = opcode; | |
36649 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
36650 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36651 | goto endlabel2089; | |
36652 | } | |
36653 | {{ int16_t src = m68k_read_memory_16(srca); | |
36654 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
36655 | if ((dsta & 1) != 0) { | |
36656 | last_fault_for_exception_3 = dsta; | |
36657 | last_op_for_exception_3 = opcode; | |
36658 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
36659 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36660 | goto endlabel2089; | |
36661 | } | |
36662 | { CLEAR_CZNV; | |
36663 | SET_ZFLG (((int16_t)(src)) == 0); | |
36664 | SET_NFLG (((int16_t)(src)) < 0); | |
36665 | m68k_incpc(4); | |
36666 | fill_prefetch_0 (); | |
36667 | m68k_write_memory_16(dsta,src); | |
36668 | }}}}}}endlabel2089: ; | |
36669 | return 16; | |
36670 | } | |
36671 | unsigned long CPUFUNC(op_3158_5)(uint32_t opcode) /* MOVE */ | |
36672 | { | |
36673 | uint32_t srcreg = (opcode & 7); | |
36674 | uint32_t dstreg = (opcode >> 9) & 7; | |
36675 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
36676 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
36677 | if ((srca & 1) != 0) { | |
36678 | last_fault_for_exception_3 = srca; | |
36679 | last_op_for_exception_3 = opcode; | |
36680 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
36681 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36682 | goto endlabel2090; | |
36683 | } | |
36684 | {{ int16_t src = m68k_read_memory_16(srca); | |
36685 | m68k_areg(regs, srcreg) += 2; | |
36686 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
36687 | if ((dsta & 1) != 0) { | |
36688 | last_fault_for_exception_3 = dsta; | |
36689 | last_op_for_exception_3 = opcode; | |
36690 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
36691 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36692 | goto endlabel2090; | |
36693 | } | |
36694 | { CLEAR_CZNV; | |
36695 | SET_ZFLG (((int16_t)(src)) == 0); | |
36696 | SET_NFLG (((int16_t)(src)) < 0); | |
36697 | m68k_incpc(4); | |
36698 | fill_prefetch_0 (); | |
36699 | m68k_write_memory_16(dsta,src); | |
36700 | }}}}}}endlabel2090: ; | |
36701 | return 16; | |
36702 | } | |
36703 | unsigned long CPUFUNC(op_3160_5)(uint32_t opcode) /* MOVE */ | |
36704 | { | |
36705 | uint32_t srcreg = (opcode & 7); | |
36706 | uint32_t dstreg = (opcode >> 9) & 7; | |
36707 | OpcodeFamily = 30; CurrentInstrCycles = 18; | |
36708 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
36709 | if ((srca & 1) != 0) { | |
36710 | last_fault_for_exception_3 = srca; | |
36711 | last_op_for_exception_3 = opcode; | |
36712 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
36713 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36714 | goto endlabel2091; | |
36715 | } | |
36716 | {{ int16_t src = m68k_read_memory_16(srca); | |
36717 | m68k_areg (regs, srcreg) = srca; | |
36718 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
36719 | if ((dsta & 1) != 0) { | |
36720 | last_fault_for_exception_3 = dsta; | |
36721 | last_op_for_exception_3 = opcode; | |
36722 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
36723 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36724 | goto endlabel2091; | |
36725 | } | |
36726 | { CLEAR_CZNV; | |
36727 | SET_ZFLG (((int16_t)(src)) == 0); | |
36728 | SET_NFLG (((int16_t)(src)) < 0); | |
36729 | m68k_incpc(4); | |
36730 | fill_prefetch_0 (); | |
36731 | m68k_write_memory_16(dsta,src); | |
36732 | }}}}}}endlabel2091: ; | |
36733 | return 18; | |
36734 | } | |
36735 | unsigned long CPUFUNC(op_3168_5)(uint32_t opcode) /* MOVE */ | |
36736 | { | |
36737 | uint32_t srcreg = (opcode & 7); | |
36738 | uint32_t dstreg = (opcode >> 9) & 7; | |
36739 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
36740 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
36741 | if ((srca & 1) != 0) { | |
36742 | last_fault_for_exception_3 = srca; | |
36743 | last_op_for_exception_3 = opcode; | |
36744 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
36745 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36746 | goto endlabel2092; | |
36747 | } | |
36748 | {{ int16_t src = m68k_read_memory_16(srca); | |
36749 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); | |
36750 | if ((dsta & 1) != 0) { | |
36751 | last_fault_for_exception_3 = dsta; | |
36752 | last_op_for_exception_3 = opcode; | |
36753 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
36754 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36755 | goto endlabel2092; | |
36756 | } | |
36757 | { CLEAR_CZNV; | |
36758 | SET_ZFLG (((int16_t)(src)) == 0); | |
36759 | SET_NFLG (((int16_t)(src)) < 0); | |
36760 | m68k_incpc(6); | |
36761 | fill_prefetch_0 (); | |
36762 | m68k_write_memory_16(dsta,src); | |
36763 | }}}}}}endlabel2092: ; | |
36764 | return 20; | |
36765 | } | |
36766 | unsigned long CPUFUNC(op_3170_5)(uint32_t opcode) /* MOVE */ | |
36767 | { | |
36768 | uint32_t srcreg = (opcode & 7); | |
36769 | uint32_t dstreg = (opcode >> 9) & 7; | |
36770 | OpcodeFamily = 30; CurrentInstrCycles = 22; | |
36771 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
36772 | BusCyclePenalty += 2; | |
36773 | if ((srca & 1) != 0) { | |
36774 | last_fault_for_exception_3 = srca; | |
36775 | last_op_for_exception_3 = opcode; | |
36776 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
36777 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36778 | goto endlabel2093; | |
36779 | } | |
36780 | {{ int16_t src = m68k_read_memory_16(srca); | |
36781 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); | |
36782 | if ((dsta & 1) != 0) { | |
36783 | last_fault_for_exception_3 = dsta; | |
36784 | last_op_for_exception_3 = opcode; | |
36785 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
36786 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36787 | goto endlabel2093; | |
36788 | } | |
36789 | { CLEAR_CZNV; | |
36790 | SET_ZFLG (((int16_t)(src)) == 0); | |
36791 | SET_NFLG (((int16_t)(src)) < 0); | |
36792 | m68k_incpc(6); | |
36793 | fill_prefetch_0 (); | |
36794 | m68k_write_memory_16(dsta,src); | |
36795 | }}}}}}endlabel2093: ; | |
36796 | return 22; | |
36797 | } | |
36798 | unsigned long CPUFUNC(op_3178_5)(uint32_t opcode) /* MOVE */ | |
36799 | { | |
36800 | uint32_t dstreg = (opcode >> 9) & 7; | |
36801 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
36802 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
36803 | if ((srca & 1) != 0) { | |
36804 | last_fault_for_exception_3 = srca; | |
36805 | last_op_for_exception_3 = opcode; | |
36806 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
36807 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36808 | goto endlabel2094; | |
36809 | } | |
36810 | {{ int16_t src = m68k_read_memory_16(srca); | |
36811 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); | |
36812 | if ((dsta & 1) != 0) { | |
36813 | last_fault_for_exception_3 = dsta; | |
36814 | last_op_for_exception_3 = opcode; | |
36815 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
36816 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36817 | goto endlabel2094; | |
36818 | } | |
36819 | { CLEAR_CZNV; | |
36820 | SET_ZFLG (((int16_t)(src)) == 0); | |
36821 | SET_NFLG (((int16_t)(src)) < 0); | |
36822 | m68k_incpc(6); | |
36823 | fill_prefetch_0 (); | |
36824 | m68k_write_memory_16(dsta,src); | |
36825 | }}}}}}endlabel2094: ; | |
36826 | return 20; | |
36827 | } | |
36828 | unsigned long CPUFUNC(op_3179_5)(uint32_t opcode) /* MOVE */ | |
36829 | { | |
36830 | uint32_t dstreg = (opcode >> 9) & 7; | |
36831 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
36832 | {{ uint32_t srca = get_ilong_prefetch(2); | |
36833 | if ((srca & 1) != 0) { | |
36834 | last_fault_for_exception_3 = srca; | |
36835 | last_op_for_exception_3 = opcode; | |
36836 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
36837 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36838 | goto endlabel2095; | |
36839 | } | |
36840 | {{ int16_t src = m68k_read_memory_16(srca); | |
36841 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(6); | |
36842 | if ((dsta & 1) != 0) { | |
36843 | last_fault_for_exception_3 = dsta; | |
36844 | last_op_for_exception_3 = opcode; | |
36845 | last_addr_for_exception_3 = m68k_getpc() + 8; | |
36846 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36847 | goto endlabel2095; | |
36848 | } | |
36849 | { CLEAR_CZNV; | |
36850 | SET_ZFLG (((int16_t)(src)) == 0); | |
36851 | SET_NFLG (((int16_t)(src)) < 0); | |
36852 | m68k_incpc(8); | |
36853 | fill_prefetch_0 (); | |
36854 | m68k_write_memory_16(dsta,src); | |
36855 | }}}}}}endlabel2095: ; | |
36856 | return 24; | |
36857 | } | |
36858 | unsigned long CPUFUNC(op_317a_5)(uint32_t opcode) /* MOVE */ | |
36859 | { | |
36860 | uint32_t dstreg = (opcode >> 9) & 7; | |
36861 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
36862 | {{ uint32_t srca = m68k_getpc () + 2; | |
36863 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
36864 | if ((srca & 1) != 0) { | |
36865 | last_fault_for_exception_3 = srca; | |
36866 | last_op_for_exception_3 = opcode; | |
36867 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
36868 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36869 | goto endlabel2096; | |
36870 | } | |
36871 | {{ int16_t src = m68k_read_memory_16(srca); | |
36872 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); | |
36873 | if ((dsta & 1) != 0) { | |
36874 | last_fault_for_exception_3 = dsta; | |
36875 | last_op_for_exception_3 = opcode; | |
36876 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
36877 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36878 | goto endlabel2096; | |
36879 | } | |
36880 | { CLEAR_CZNV; | |
36881 | SET_ZFLG (((int16_t)(src)) == 0); | |
36882 | SET_NFLG (((int16_t)(src)) < 0); | |
36883 | m68k_incpc(6); | |
36884 | fill_prefetch_0 (); | |
36885 | m68k_write_memory_16(dsta,src); | |
36886 | }}}}}}endlabel2096: ; | |
36887 | return 20; | |
36888 | } | |
36889 | unsigned long CPUFUNC(op_317b_5)(uint32_t opcode) /* MOVE */ | |
36890 | { | |
36891 | uint32_t dstreg = (opcode >> 9) & 7; | |
36892 | OpcodeFamily = 30; CurrentInstrCycles = 22; | |
36893 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
36894 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
36895 | BusCyclePenalty += 2; | |
36896 | if ((srca & 1) != 0) { | |
36897 | last_fault_for_exception_3 = srca; | |
36898 | last_op_for_exception_3 = opcode; | |
36899 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
36900 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36901 | goto endlabel2097; | |
36902 | } | |
36903 | {{ int16_t src = m68k_read_memory_16(srca); | |
36904 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); | |
36905 | if ((dsta & 1) != 0) { | |
36906 | last_fault_for_exception_3 = dsta; | |
36907 | last_op_for_exception_3 = opcode; | |
36908 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
36909 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36910 | goto endlabel2097; | |
36911 | } | |
36912 | { CLEAR_CZNV; | |
36913 | SET_ZFLG (((int16_t)(src)) == 0); | |
36914 | SET_NFLG (((int16_t)(src)) < 0); | |
36915 | m68k_incpc(6); | |
36916 | fill_prefetch_0 (); | |
36917 | m68k_write_memory_16(dsta,src); | |
36918 | }}}}}}endlabel2097: ; | |
36919 | return 22; | |
36920 | } | |
36921 | unsigned long CPUFUNC(op_317c_5)(uint32_t opcode) /* MOVE */ | |
36922 | { | |
36923 | uint32_t dstreg = (opcode >> 9) & 7; | |
36924 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
36925 | {{ int16_t src = get_iword_prefetch(2); | |
36926 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); | |
36927 | if ((dsta & 1) != 0) { | |
36928 | last_fault_for_exception_3 = dsta; | |
36929 | last_op_for_exception_3 = opcode; | |
36930 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
36931 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36932 | goto endlabel2098; | |
36933 | } | |
36934 | { CLEAR_CZNV; | |
36935 | SET_ZFLG (((int16_t)(src)) == 0); | |
36936 | SET_NFLG (((int16_t)(src)) < 0); | |
36937 | m68k_incpc(6); | |
36938 | fill_prefetch_0 (); | |
36939 | m68k_write_memory_16(dsta,src); | |
36940 | }}}}endlabel2098: ; | |
36941 | return 16; | |
36942 | } | |
36943 | unsigned long CPUFUNC(op_3180_5)(uint32_t opcode) /* MOVE */ | |
36944 | { | |
36945 | uint32_t srcreg = (opcode & 7); | |
36946 | uint32_t dstreg = (opcode >> 9) & 7; | |
36947 | OpcodeFamily = 30; CurrentInstrCycles = 14; | |
36948 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
36949 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); | |
36950 | BusCyclePenalty += 2; | |
36951 | if ((dsta & 1) != 0) { | |
36952 | last_fault_for_exception_3 = dsta; | |
36953 | last_op_for_exception_3 = opcode; | |
36954 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
36955 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36956 | goto endlabel2099; | |
36957 | } | |
36958 | { CLEAR_CZNV; | |
36959 | SET_ZFLG (((int16_t)(src)) == 0); | |
36960 | SET_NFLG (((int16_t)(src)) < 0); | |
36961 | m68k_incpc(4); | |
36962 | fill_prefetch_0 (); | |
36963 | m68k_write_memory_16(dsta,src); | |
36964 | }}}}endlabel2099: ; | |
36965 | return 14; | |
36966 | } | |
36967 | unsigned long CPUFUNC(op_3188_5)(uint32_t opcode) /* MOVE */ | |
36968 | { | |
36969 | uint32_t srcreg = (opcode & 7); | |
36970 | uint32_t dstreg = (opcode >> 9) & 7; | |
36971 | OpcodeFamily = 30; CurrentInstrCycles = 14; | |
36972 | {{ int16_t src = m68k_areg(regs, srcreg); | |
36973 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); | |
36974 | BusCyclePenalty += 2; | |
36975 | if ((dsta & 1) != 0) { | |
36976 | last_fault_for_exception_3 = dsta; | |
36977 | last_op_for_exception_3 = opcode; | |
36978 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
36979 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
36980 | goto endlabel2100; | |
36981 | } | |
36982 | { CLEAR_CZNV; | |
36983 | SET_ZFLG (((int16_t)(src)) == 0); | |
36984 | SET_NFLG (((int16_t)(src)) < 0); | |
36985 | m68k_incpc(4); | |
36986 | fill_prefetch_0 (); | |
36987 | m68k_write_memory_16(dsta,src); | |
36988 | }}}}endlabel2100: ; | |
36989 | return 14; | |
36990 | } | |
36991 | unsigned long CPUFUNC(op_3190_5)(uint32_t opcode) /* MOVE */ | |
36992 | { | |
36993 | uint32_t srcreg = (opcode & 7); | |
36994 | uint32_t dstreg = (opcode >> 9) & 7; | |
36995 | OpcodeFamily = 30; CurrentInstrCycles = 18; | |
36996 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
36997 | if ((srca & 1) != 0) { | |
36998 | last_fault_for_exception_3 = srca; | |
36999 | last_op_for_exception_3 = opcode; | |
37000 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
37001 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37002 | goto endlabel2101; | |
37003 | } | |
37004 | {{ int16_t src = m68k_read_memory_16(srca); | |
37005 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); | |
37006 | BusCyclePenalty += 2; | |
37007 | if ((dsta & 1) != 0) { | |
37008 | last_fault_for_exception_3 = dsta; | |
37009 | last_op_for_exception_3 = opcode; | |
37010 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
37011 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37012 | goto endlabel2101; | |
37013 | } | |
37014 | { CLEAR_CZNV; | |
37015 | SET_ZFLG (((int16_t)(src)) == 0); | |
37016 | SET_NFLG (((int16_t)(src)) < 0); | |
37017 | m68k_incpc(4); | |
37018 | fill_prefetch_0 (); | |
37019 | m68k_write_memory_16(dsta,src); | |
37020 | }}}}}}endlabel2101: ; | |
37021 | return 18; | |
37022 | } | |
37023 | unsigned long CPUFUNC(op_3198_5)(uint32_t opcode) /* MOVE */ | |
37024 | { | |
37025 | uint32_t srcreg = (opcode & 7); | |
37026 | uint32_t dstreg = (opcode >> 9) & 7; | |
37027 | OpcodeFamily = 30; CurrentInstrCycles = 18; | |
37028 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
37029 | if ((srca & 1) != 0) { | |
37030 | last_fault_for_exception_3 = srca; | |
37031 | last_op_for_exception_3 = opcode; | |
37032 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
37033 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37034 | goto endlabel2102; | |
37035 | } | |
37036 | {{ int16_t src = m68k_read_memory_16(srca); | |
37037 | m68k_areg(regs, srcreg) += 2; | |
37038 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); | |
37039 | BusCyclePenalty += 2; | |
37040 | if ((dsta & 1) != 0) { | |
37041 | last_fault_for_exception_3 = dsta; | |
37042 | last_op_for_exception_3 = opcode; | |
37043 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
37044 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37045 | goto endlabel2102; | |
37046 | } | |
37047 | { CLEAR_CZNV; | |
37048 | SET_ZFLG (((int16_t)(src)) == 0); | |
37049 | SET_NFLG (((int16_t)(src)) < 0); | |
37050 | m68k_incpc(4); | |
37051 | fill_prefetch_0 (); | |
37052 | m68k_write_memory_16(dsta,src); | |
37053 | }}}}}}endlabel2102: ; | |
37054 | return 18; | |
37055 | } | |
37056 | unsigned long CPUFUNC(op_31a0_5)(uint32_t opcode) /* MOVE */ | |
37057 | { | |
37058 | uint32_t srcreg = (opcode & 7); | |
37059 | uint32_t dstreg = (opcode >> 9) & 7; | |
37060 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
37061 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
37062 | if ((srca & 1) != 0) { | |
37063 | last_fault_for_exception_3 = srca; | |
37064 | last_op_for_exception_3 = opcode; | |
37065 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
37066 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37067 | goto endlabel2103; | |
37068 | } | |
37069 | {{ int16_t src = m68k_read_memory_16(srca); | |
37070 | m68k_areg (regs, srcreg) = srca; | |
37071 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); | |
37072 | BusCyclePenalty += 2; | |
37073 | if ((dsta & 1) != 0) { | |
37074 | last_fault_for_exception_3 = dsta; | |
37075 | last_op_for_exception_3 = opcode; | |
37076 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
37077 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37078 | goto endlabel2103; | |
37079 | } | |
37080 | { CLEAR_CZNV; | |
37081 | SET_ZFLG (((int16_t)(src)) == 0); | |
37082 | SET_NFLG (((int16_t)(src)) < 0); | |
37083 | m68k_incpc(4); | |
37084 | fill_prefetch_0 (); | |
37085 | m68k_write_memory_16(dsta,src); | |
37086 | }}}}}}endlabel2103: ; | |
37087 | return 20; | |
37088 | } | |
37089 | unsigned long CPUFUNC(op_31a8_5)(uint32_t opcode) /* MOVE */ | |
37090 | { | |
37091 | uint32_t srcreg = (opcode & 7); | |
37092 | uint32_t dstreg = (opcode >> 9) & 7; | |
37093 | OpcodeFamily = 30; CurrentInstrCycles = 22; | |
37094 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
37095 | if ((srca & 1) != 0) { | |
37096 | last_fault_for_exception_3 = srca; | |
37097 | last_op_for_exception_3 = opcode; | |
37098 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
37099 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37100 | goto endlabel2104; | |
37101 | } | |
37102 | {{ int16_t src = m68k_read_memory_16(srca); | |
37103 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); | |
37104 | BusCyclePenalty += 2; | |
37105 | if ((dsta & 1) != 0) { | |
37106 | last_fault_for_exception_3 = dsta; | |
37107 | last_op_for_exception_3 = opcode; | |
37108 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
37109 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37110 | goto endlabel2104; | |
37111 | } | |
37112 | { CLEAR_CZNV; | |
37113 | SET_ZFLG (((int16_t)(src)) == 0); | |
37114 | SET_NFLG (((int16_t)(src)) < 0); | |
37115 | m68k_incpc(6); | |
37116 | fill_prefetch_0 (); | |
37117 | m68k_write_memory_16(dsta,src); | |
37118 | }}}}}}endlabel2104: ; | |
37119 | return 22; | |
37120 | } | |
37121 | unsigned long CPUFUNC(op_31b0_5)(uint32_t opcode) /* MOVE */ | |
37122 | { | |
37123 | uint32_t srcreg = (opcode & 7); | |
37124 | uint32_t dstreg = (opcode >> 9) & 7; | |
37125 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
37126 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
37127 | BusCyclePenalty += 2; | |
37128 | if ((srca & 1) != 0) { | |
37129 | last_fault_for_exception_3 = srca; | |
37130 | last_op_for_exception_3 = opcode; | |
37131 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
37132 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37133 | goto endlabel2105; | |
37134 | } | |
37135 | {{ int16_t src = m68k_read_memory_16(srca); | |
37136 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); | |
37137 | BusCyclePenalty += 2; | |
37138 | if ((dsta & 1) != 0) { | |
37139 | last_fault_for_exception_3 = dsta; | |
37140 | last_op_for_exception_3 = opcode; | |
37141 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
37142 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37143 | goto endlabel2105; | |
37144 | } | |
37145 | { CLEAR_CZNV; | |
37146 | SET_ZFLG (((int16_t)(src)) == 0); | |
37147 | SET_NFLG (((int16_t)(src)) < 0); | |
37148 | m68k_incpc(6); | |
37149 | fill_prefetch_0 (); | |
37150 | m68k_write_memory_16(dsta,src); | |
37151 | }}}}}}endlabel2105: ; | |
37152 | return 24; | |
37153 | } | |
37154 | unsigned long CPUFUNC(op_31b8_5)(uint32_t opcode) /* MOVE */ | |
37155 | { | |
37156 | uint32_t dstreg = (opcode >> 9) & 7; | |
37157 | OpcodeFamily = 30; CurrentInstrCycles = 22; | |
37158 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
37159 | if ((srca & 1) != 0) { | |
37160 | last_fault_for_exception_3 = srca; | |
37161 | last_op_for_exception_3 = opcode; | |
37162 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
37163 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37164 | goto endlabel2106; | |
37165 | } | |
37166 | {{ int16_t src = m68k_read_memory_16(srca); | |
37167 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); | |
37168 | BusCyclePenalty += 2; | |
37169 | if ((dsta & 1) != 0) { | |
37170 | last_fault_for_exception_3 = dsta; | |
37171 | last_op_for_exception_3 = opcode; | |
37172 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
37173 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37174 | goto endlabel2106; | |
37175 | } | |
37176 | { CLEAR_CZNV; | |
37177 | SET_ZFLG (((int16_t)(src)) == 0); | |
37178 | SET_NFLG (((int16_t)(src)) < 0); | |
37179 | m68k_incpc(6); | |
37180 | fill_prefetch_0 (); | |
37181 | m68k_write_memory_16(dsta,src); | |
37182 | }}}}}}endlabel2106: ; | |
37183 | return 22; | |
37184 | } | |
37185 | unsigned long CPUFUNC(op_31b9_5)(uint32_t opcode) /* MOVE */ | |
37186 | { | |
37187 | uint32_t dstreg = (opcode >> 9) & 7; | |
37188 | OpcodeFamily = 30; CurrentInstrCycles = 26; | |
37189 | {{ uint32_t srca = get_ilong_prefetch(2); | |
37190 | if ((srca & 1) != 0) { | |
37191 | last_fault_for_exception_3 = srca; | |
37192 | last_op_for_exception_3 = opcode; | |
37193 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
37194 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37195 | goto endlabel2107; | |
37196 | } | |
37197 | {{ int16_t src = m68k_read_memory_16(srca); | |
37198 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(6)); | |
37199 | BusCyclePenalty += 2; | |
37200 | if ((dsta & 1) != 0) { | |
37201 | last_fault_for_exception_3 = dsta; | |
37202 | last_op_for_exception_3 = opcode; | |
37203 | last_addr_for_exception_3 = m68k_getpc() + 8; | |
37204 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37205 | goto endlabel2107; | |
37206 | } | |
37207 | { CLEAR_CZNV; | |
37208 | SET_ZFLG (((int16_t)(src)) == 0); | |
37209 | SET_NFLG (((int16_t)(src)) < 0); | |
37210 | m68k_incpc(8); | |
37211 | fill_prefetch_0 (); | |
37212 | m68k_write_memory_16(dsta,src); | |
37213 | }}}}}}endlabel2107: ; | |
37214 | return 26; | |
37215 | } | |
37216 | unsigned long CPUFUNC(op_31ba_5)(uint32_t opcode) /* MOVE */ | |
37217 | { | |
37218 | uint32_t dstreg = (opcode >> 9) & 7; | |
37219 | OpcodeFamily = 30; CurrentInstrCycles = 22; | |
37220 | {{ uint32_t srca = m68k_getpc () + 2; | |
37221 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
37222 | if ((srca & 1) != 0) { | |
37223 | last_fault_for_exception_3 = srca; | |
37224 | last_op_for_exception_3 = opcode; | |
37225 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
37226 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37227 | goto endlabel2108; | |
37228 | } | |
37229 | {{ int16_t src = m68k_read_memory_16(srca); | |
37230 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); | |
37231 | BusCyclePenalty += 2; | |
37232 | if ((dsta & 1) != 0) { | |
37233 | last_fault_for_exception_3 = dsta; | |
37234 | last_op_for_exception_3 = opcode; | |
37235 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
37236 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37237 | goto endlabel2108; | |
37238 | } | |
37239 | { CLEAR_CZNV; | |
37240 | SET_ZFLG (((int16_t)(src)) == 0); | |
37241 | SET_NFLG (((int16_t)(src)) < 0); | |
37242 | m68k_incpc(6); | |
37243 | fill_prefetch_0 (); | |
37244 | m68k_write_memory_16(dsta,src); | |
37245 | }}}}}}endlabel2108: ; | |
37246 | return 22; | |
37247 | } | |
37248 | unsigned long CPUFUNC(op_31bb_5)(uint32_t opcode) /* MOVE */ | |
37249 | { | |
37250 | uint32_t dstreg = (opcode >> 9) & 7; | |
37251 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
37252 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
37253 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
37254 | BusCyclePenalty += 2; | |
37255 | if ((srca & 1) != 0) { | |
37256 | last_fault_for_exception_3 = srca; | |
37257 | last_op_for_exception_3 = opcode; | |
37258 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
37259 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37260 | goto endlabel2109; | |
37261 | } | |
37262 | {{ int16_t src = m68k_read_memory_16(srca); | |
37263 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); | |
37264 | BusCyclePenalty += 2; | |
37265 | if ((dsta & 1) != 0) { | |
37266 | last_fault_for_exception_3 = dsta; | |
37267 | last_op_for_exception_3 = opcode; | |
37268 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
37269 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37270 | goto endlabel2109; | |
37271 | } | |
37272 | { CLEAR_CZNV; | |
37273 | SET_ZFLG (((int16_t)(src)) == 0); | |
37274 | SET_NFLG (((int16_t)(src)) < 0); | |
37275 | m68k_incpc(6); | |
37276 | fill_prefetch_0 (); | |
37277 | m68k_write_memory_16(dsta,src); | |
37278 | }}}}}}endlabel2109: ; | |
37279 | return 24; | |
37280 | } | |
37281 | unsigned long CPUFUNC(op_31bc_5)(uint32_t opcode) /* MOVE */ | |
37282 | { | |
37283 | uint32_t dstreg = (opcode >> 9) & 7; | |
37284 | OpcodeFamily = 30; CurrentInstrCycles = 18; | |
37285 | {{ int16_t src = get_iword_prefetch(2); | |
37286 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); | |
37287 | BusCyclePenalty += 2; | |
37288 | if ((dsta & 1) != 0) { | |
37289 | last_fault_for_exception_3 = dsta; | |
37290 | last_op_for_exception_3 = opcode; | |
37291 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
37292 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37293 | goto endlabel2110; | |
37294 | } | |
37295 | { CLEAR_CZNV; | |
37296 | SET_ZFLG (((int16_t)(src)) == 0); | |
37297 | SET_NFLG (((int16_t)(src)) < 0); | |
37298 | m68k_incpc(6); | |
37299 | fill_prefetch_0 (); | |
37300 | m68k_write_memory_16(dsta,src); | |
37301 | }}}}endlabel2110: ; | |
37302 | return 18; | |
37303 | } | |
37304 | unsigned long CPUFUNC(op_31c0_5)(uint32_t opcode) /* MOVE */ | |
37305 | { | |
37306 | uint32_t srcreg = (opcode & 7); | |
37307 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
37308 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
37309 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); | |
37310 | if ((dsta & 1) != 0) { | |
37311 | last_fault_for_exception_3 = dsta; | |
37312 | last_op_for_exception_3 = opcode; | |
37313 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
37314 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37315 | goto endlabel2111; | |
37316 | } | |
37317 | { CLEAR_CZNV; | |
37318 | SET_ZFLG (((int16_t)(src)) == 0); | |
37319 | SET_NFLG (((int16_t)(src)) < 0); | |
37320 | m68k_incpc(4); | |
37321 | fill_prefetch_0 (); | |
37322 | m68k_write_memory_16(dsta,src); | |
37323 | }}}}endlabel2111: ; | |
37324 | return 12; | |
37325 | } | |
37326 | unsigned long CPUFUNC(op_31c8_5)(uint32_t opcode) /* MOVE */ | |
37327 | { | |
37328 | uint32_t srcreg = (opcode & 7); | |
37329 | OpcodeFamily = 30; CurrentInstrCycles = 12; | |
37330 | {{ int16_t src = m68k_areg(regs, srcreg); | |
37331 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); | |
37332 | if ((dsta & 1) != 0) { | |
37333 | last_fault_for_exception_3 = dsta; | |
37334 | last_op_for_exception_3 = opcode; | |
37335 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
37336 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37337 | goto endlabel2112; | |
37338 | } | |
37339 | { CLEAR_CZNV; | |
37340 | SET_ZFLG (((int16_t)(src)) == 0); | |
37341 | SET_NFLG (((int16_t)(src)) < 0); | |
37342 | m68k_incpc(4); | |
37343 | fill_prefetch_0 (); | |
37344 | m68k_write_memory_16(dsta,src); | |
37345 | }}}}endlabel2112: ; | |
37346 | return 12; | |
37347 | } | |
37348 | unsigned long CPUFUNC(op_31d0_5)(uint32_t opcode) /* MOVE */ | |
37349 | { | |
37350 | uint32_t srcreg = (opcode & 7); | |
37351 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
37352 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
37353 | if ((srca & 1) != 0) { | |
37354 | last_fault_for_exception_3 = srca; | |
37355 | last_op_for_exception_3 = opcode; | |
37356 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
37357 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37358 | goto endlabel2113; | |
37359 | } | |
37360 | {{ int16_t src = m68k_read_memory_16(srca); | |
37361 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); | |
37362 | if ((dsta & 1) != 0) { | |
37363 | last_fault_for_exception_3 = dsta; | |
37364 | last_op_for_exception_3 = opcode; | |
37365 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
37366 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37367 | goto endlabel2113; | |
37368 | } | |
37369 | { CLEAR_CZNV; | |
37370 | SET_ZFLG (((int16_t)(src)) == 0); | |
37371 | SET_NFLG (((int16_t)(src)) < 0); | |
37372 | m68k_incpc(4); | |
37373 | fill_prefetch_0 (); | |
37374 | m68k_write_memory_16(dsta,src); | |
37375 | }}}}}}endlabel2113: ; | |
37376 | return 16; | |
37377 | } | |
37378 | unsigned long CPUFUNC(op_31d8_5)(uint32_t opcode) /* MOVE */ | |
37379 | { | |
37380 | uint32_t srcreg = (opcode & 7); | |
37381 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
37382 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
37383 | if ((srca & 1) != 0) { | |
37384 | last_fault_for_exception_3 = srca; | |
37385 | last_op_for_exception_3 = opcode; | |
37386 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
37387 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37388 | goto endlabel2114; | |
37389 | } | |
37390 | {{ int16_t src = m68k_read_memory_16(srca); | |
37391 | m68k_areg(regs, srcreg) += 2; | |
37392 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); | |
37393 | if ((dsta & 1) != 0) { | |
37394 | last_fault_for_exception_3 = dsta; | |
37395 | last_op_for_exception_3 = opcode; | |
37396 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
37397 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37398 | goto endlabel2114; | |
37399 | } | |
37400 | { CLEAR_CZNV; | |
37401 | SET_ZFLG (((int16_t)(src)) == 0); | |
37402 | SET_NFLG (((int16_t)(src)) < 0); | |
37403 | m68k_incpc(4); | |
37404 | fill_prefetch_0 (); | |
37405 | m68k_write_memory_16(dsta,src); | |
37406 | }}}}}}endlabel2114: ; | |
37407 | return 16; | |
37408 | } | |
37409 | unsigned long CPUFUNC(op_31e0_5)(uint32_t opcode) /* MOVE */ | |
37410 | { | |
37411 | uint32_t srcreg = (opcode & 7); | |
37412 | OpcodeFamily = 30; CurrentInstrCycles = 18; | |
37413 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
37414 | if ((srca & 1) != 0) { | |
37415 | last_fault_for_exception_3 = srca; | |
37416 | last_op_for_exception_3 = opcode; | |
37417 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
37418 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37419 | goto endlabel2115; | |
37420 | } | |
37421 | {{ int16_t src = m68k_read_memory_16(srca); | |
37422 | m68k_areg (regs, srcreg) = srca; | |
37423 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); | |
37424 | if ((dsta & 1) != 0) { | |
37425 | last_fault_for_exception_3 = dsta; | |
37426 | last_op_for_exception_3 = opcode; | |
37427 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
37428 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37429 | goto endlabel2115; | |
37430 | } | |
37431 | { CLEAR_CZNV; | |
37432 | SET_ZFLG (((int16_t)(src)) == 0); | |
37433 | SET_NFLG (((int16_t)(src)) < 0); | |
37434 | m68k_incpc(4); | |
37435 | fill_prefetch_0 (); | |
37436 | m68k_write_memory_16(dsta,src); | |
37437 | }}}}}}endlabel2115: ; | |
37438 | return 18; | |
37439 | } | |
37440 | unsigned long CPUFUNC(op_31e8_5)(uint32_t opcode) /* MOVE */ | |
37441 | { | |
37442 | uint32_t srcreg = (opcode & 7); | |
37443 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
37444 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
37445 | if ((srca & 1) != 0) { | |
37446 | last_fault_for_exception_3 = srca; | |
37447 | last_op_for_exception_3 = opcode; | |
37448 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
37449 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37450 | goto endlabel2116; | |
37451 | } | |
37452 | {{ int16_t src = m68k_read_memory_16(srca); | |
37453 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); | |
37454 | if ((dsta & 1) != 0) { | |
37455 | last_fault_for_exception_3 = dsta; | |
37456 | last_op_for_exception_3 = opcode; | |
37457 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
37458 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37459 | goto endlabel2116; | |
37460 | } | |
37461 | { CLEAR_CZNV; | |
37462 | SET_ZFLG (((int16_t)(src)) == 0); | |
37463 | SET_NFLG (((int16_t)(src)) < 0); | |
37464 | m68k_incpc(6); | |
37465 | fill_prefetch_0 (); | |
37466 | m68k_write_memory_16(dsta,src); | |
37467 | }}}}}}endlabel2116: ; | |
37468 | return 20; | |
37469 | } | |
37470 | unsigned long CPUFUNC(op_31f0_5)(uint32_t opcode) /* MOVE */ | |
37471 | { | |
37472 | uint32_t srcreg = (opcode & 7); | |
37473 | OpcodeFamily = 30; CurrentInstrCycles = 22; | |
37474 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
37475 | BusCyclePenalty += 2; | |
37476 | if ((srca & 1) != 0) { | |
37477 | last_fault_for_exception_3 = srca; | |
37478 | last_op_for_exception_3 = opcode; | |
37479 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
37480 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37481 | goto endlabel2117; | |
37482 | } | |
37483 | {{ int16_t src = m68k_read_memory_16(srca); | |
37484 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); | |
37485 | if ((dsta & 1) != 0) { | |
37486 | last_fault_for_exception_3 = dsta; | |
37487 | last_op_for_exception_3 = opcode; | |
37488 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
37489 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37490 | goto endlabel2117; | |
37491 | } | |
37492 | { CLEAR_CZNV; | |
37493 | SET_ZFLG (((int16_t)(src)) == 0); | |
37494 | SET_NFLG (((int16_t)(src)) < 0); | |
37495 | m68k_incpc(6); | |
37496 | fill_prefetch_0 (); | |
37497 | m68k_write_memory_16(dsta,src); | |
37498 | }}}}}}endlabel2117: ; | |
37499 | return 22; | |
37500 | } | |
37501 | unsigned long CPUFUNC(op_31f8_5)(uint32_t opcode) /* MOVE */ | |
37502 | { | |
37503 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
37504 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
37505 | if ((srca & 1) != 0) { | |
37506 | last_fault_for_exception_3 = srca; | |
37507 | last_op_for_exception_3 = opcode; | |
37508 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
37509 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37510 | goto endlabel2118; | |
37511 | } | |
37512 | {{ int16_t src = m68k_read_memory_16(srca); | |
37513 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); | |
37514 | if ((dsta & 1) != 0) { | |
37515 | last_fault_for_exception_3 = dsta; | |
37516 | last_op_for_exception_3 = opcode; | |
37517 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
37518 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37519 | goto endlabel2118; | |
37520 | } | |
37521 | { CLEAR_CZNV; | |
37522 | SET_ZFLG (((int16_t)(src)) == 0); | |
37523 | SET_NFLG (((int16_t)(src)) < 0); | |
37524 | m68k_incpc(6); | |
37525 | fill_prefetch_0 (); | |
37526 | m68k_write_memory_16(dsta,src); | |
37527 | }}}}}}endlabel2118: ; | |
37528 | return 20; | |
37529 | } | |
37530 | unsigned long CPUFUNC(op_31f9_5)(uint32_t opcode) /* MOVE */ | |
37531 | { | |
37532 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
37533 | {{ uint32_t srca = get_ilong_prefetch(2); | |
37534 | if ((srca & 1) != 0) { | |
37535 | last_fault_for_exception_3 = srca; | |
37536 | last_op_for_exception_3 = opcode; | |
37537 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
37538 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37539 | goto endlabel2119; | |
37540 | } | |
37541 | {{ int16_t src = m68k_read_memory_16(srca); | |
37542 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(6); | |
37543 | if ((dsta & 1) != 0) { | |
37544 | last_fault_for_exception_3 = dsta; | |
37545 | last_op_for_exception_3 = opcode; | |
37546 | last_addr_for_exception_3 = m68k_getpc() + 8; | |
37547 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37548 | goto endlabel2119; | |
37549 | } | |
37550 | { CLEAR_CZNV; | |
37551 | SET_ZFLG (((int16_t)(src)) == 0); | |
37552 | SET_NFLG (((int16_t)(src)) < 0); | |
37553 | m68k_incpc(8); | |
37554 | fill_prefetch_0 (); | |
37555 | m68k_write_memory_16(dsta,src); | |
37556 | }}}}}}endlabel2119: ; | |
37557 | return 24; | |
37558 | } | |
37559 | unsigned long CPUFUNC(op_31fa_5)(uint32_t opcode) /* MOVE */ | |
37560 | { | |
37561 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
37562 | {{ uint32_t srca = m68k_getpc () + 2; | |
37563 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
37564 | if ((srca & 1) != 0) { | |
37565 | last_fault_for_exception_3 = srca; | |
37566 | last_op_for_exception_3 = opcode; | |
37567 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
37568 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37569 | goto endlabel2120; | |
37570 | } | |
37571 | {{ int16_t src = m68k_read_memory_16(srca); | |
37572 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); | |
37573 | if ((dsta & 1) != 0) { | |
37574 | last_fault_for_exception_3 = dsta; | |
37575 | last_op_for_exception_3 = opcode; | |
37576 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
37577 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37578 | goto endlabel2120; | |
37579 | } | |
37580 | { CLEAR_CZNV; | |
37581 | SET_ZFLG (((int16_t)(src)) == 0); | |
37582 | SET_NFLG (((int16_t)(src)) < 0); | |
37583 | m68k_incpc(6); | |
37584 | fill_prefetch_0 (); | |
37585 | m68k_write_memory_16(dsta,src); | |
37586 | }}}}}}endlabel2120: ; | |
37587 | return 20; | |
37588 | } | |
37589 | unsigned long CPUFUNC(op_31fb_5)(uint32_t opcode) /* MOVE */ | |
37590 | { | |
37591 | OpcodeFamily = 30; CurrentInstrCycles = 22; | |
37592 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
37593 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
37594 | BusCyclePenalty += 2; | |
37595 | if ((srca & 1) != 0) { | |
37596 | last_fault_for_exception_3 = srca; | |
37597 | last_op_for_exception_3 = opcode; | |
37598 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
37599 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37600 | goto endlabel2121; | |
37601 | } | |
37602 | {{ int16_t src = m68k_read_memory_16(srca); | |
37603 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); | |
37604 | if ((dsta & 1) != 0) { | |
37605 | last_fault_for_exception_3 = dsta; | |
37606 | last_op_for_exception_3 = opcode; | |
37607 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
37608 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37609 | goto endlabel2121; | |
37610 | } | |
37611 | { CLEAR_CZNV; | |
37612 | SET_ZFLG (((int16_t)(src)) == 0); | |
37613 | SET_NFLG (((int16_t)(src)) < 0); | |
37614 | m68k_incpc(6); | |
37615 | fill_prefetch_0 (); | |
37616 | m68k_write_memory_16(dsta,src); | |
37617 | }}}}}}endlabel2121: ; | |
37618 | return 22; | |
37619 | } | |
37620 | unsigned long CPUFUNC(op_31fc_5)(uint32_t opcode) /* MOVE */ | |
37621 | { | |
37622 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
37623 | {{ int16_t src = get_iword_prefetch(2); | |
37624 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(4); | |
37625 | if ((dsta & 1) != 0) { | |
37626 | last_fault_for_exception_3 = dsta; | |
37627 | last_op_for_exception_3 = opcode; | |
37628 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
37629 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37630 | goto endlabel2122; | |
37631 | } | |
37632 | { CLEAR_CZNV; | |
37633 | SET_ZFLG (((int16_t)(src)) == 0); | |
37634 | SET_NFLG (((int16_t)(src)) < 0); | |
37635 | m68k_incpc(6); | |
37636 | fill_prefetch_0 (); | |
37637 | m68k_write_memory_16(dsta,src); | |
37638 | }}}}endlabel2122: ; | |
37639 | return 16; | |
37640 | } | |
37641 | unsigned long CPUFUNC(op_33c0_5)(uint32_t opcode) /* MOVE */ | |
37642 | { | |
37643 | uint32_t srcreg = (opcode & 7); | |
37644 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
37645 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
37646 | { uint32_t dsta = get_ilong_prefetch(2); | |
37647 | if ((dsta & 1) != 0) { | |
37648 | last_fault_for_exception_3 = dsta; | |
37649 | last_op_for_exception_3 = opcode; | |
37650 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
37651 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37652 | goto endlabel2123; | |
37653 | } | |
37654 | { CLEAR_CZNV; | |
37655 | SET_ZFLG (((int16_t)(src)) == 0); | |
37656 | SET_NFLG (((int16_t)(src)) < 0); | |
37657 | m68k_incpc(6); | |
37658 | fill_prefetch_0 (); | |
37659 | m68k_write_memory_16(dsta,src); | |
37660 | }}}}endlabel2123: ; | |
37661 | return 16; | |
37662 | } | |
37663 | unsigned long CPUFUNC(op_33c8_5)(uint32_t opcode) /* MOVE */ | |
37664 | { | |
37665 | uint32_t srcreg = (opcode & 7); | |
37666 | OpcodeFamily = 30; CurrentInstrCycles = 16; | |
37667 | {{ int16_t src = m68k_areg(regs, srcreg); | |
37668 | { uint32_t dsta = get_ilong_prefetch(2); | |
37669 | if ((dsta & 1) != 0) { | |
37670 | last_fault_for_exception_3 = dsta; | |
37671 | last_op_for_exception_3 = opcode; | |
37672 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
37673 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37674 | goto endlabel2124; | |
37675 | } | |
37676 | { CLEAR_CZNV; | |
37677 | SET_ZFLG (((int16_t)(src)) == 0); | |
37678 | SET_NFLG (((int16_t)(src)) < 0); | |
37679 | m68k_incpc(6); | |
37680 | fill_prefetch_0 (); | |
37681 | m68k_write_memory_16(dsta,src); | |
37682 | }}}}endlabel2124: ; | |
37683 | return 16; | |
37684 | } | |
37685 | unsigned long CPUFUNC(op_33d0_5)(uint32_t opcode) /* MOVE */ | |
37686 | { | |
37687 | uint32_t srcreg = (opcode & 7); | |
37688 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
37689 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
37690 | if ((srca & 1) != 0) { | |
37691 | last_fault_for_exception_3 = srca; | |
37692 | last_op_for_exception_3 = opcode; | |
37693 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
37694 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37695 | goto endlabel2125; | |
37696 | } | |
37697 | {{ int16_t src = m68k_read_memory_16(srca); | |
37698 | { uint32_t dsta = get_ilong_prefetch(2); | |
37699 | if ((dsta & 1) != 0) { | |
37700 | last_fault_for_exception_3 = dsta; | |
37701 | last_op_for_exception_3 = opcode; | |
37702 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
37703 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37704 | goto endlabel2125; | |
37705 | } | |
37706 | { CLEAR_CZNV; | |
37707 | SET_ZFLG (((int16_t)(src)) == 0); | |
37708 | SET_NFLG (((int16_t)(src)) < 0); | |
37709 | m68k_incpc(6); | |
37710 | fill_prefetch_0 (); | |
37711 | m68k_write_memory_16(dsta,src); | |
37712 | }}}}}}endlabel2125: ; | |
37713 | return 20; | |
37714 | } | |
37715 | unsigned long CPUFUNC(op_33d8_5)(uint32_t opcode) /* MOVE */ | |
37716 | { | |
37717 | uint32_t srcreg = (opcode & 7); | |
37718 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
37719 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
37720 | if ((srca & 1) != 0) { | |
37721 | last_fault_for_exception_3 = srca; | |
37722 | last_op_for_exception_3 = opcode; | |
37723 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
37724 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37725 | goto endlabel2126; | |
37726 | } | |
37727 | {{ int16_t src = m68k_read_memory_16(srca); | |
37728 | m68k_areg(regs, srcreg) += 2; | |
37729 | { uint32_t dsta = get_ilong_prefetch(2); | |
37730 | if ((dsta & 1) != 0) { | |
37731 | last_fault_for_exception_3 = dsta; | |
37732 | last_op_for_exception_3 = opcode; | |
37733 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
37734 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37735 | goto endlabel2126; | |
37736 | } | |
37737 | { CLEAR_CZNV; | |
37738 | SET_ZFLG (((int16_t)(src)) == 0); | |
37739 | SET_NFLG (((int16_t)(src)) < 0); | |
37740 | m68k_incpc(6); | |
37741 | fill_prefetch_0 (); | |
37742 | m68k_write_memory_16(dsta,src); | |
37743 | }}}}}}endlabel2126: ; | |
37744 | return 20; | |
37745 | } | |
37746 | unsigned long CPUFUNC(op_33e0_5)(uint32_t opcode) /* MOVE */ | |
37747 | { | |
37748 | uint32_t srcreg = (opcode & 7); | |
37749 | OpcodeFamily = 30; CurrentInstrCycles = 22; | |
37750 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
37751 | if ((srca & 1) != 0) { | |
37752 | last_fault_for_exception_3 = srca; | |
37753 | last_op_for_exception_3 = opcode; | |
37754 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
37755 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37756 | goto endlabel2127; | |
37757 | } | |
37758 | {{ int16_t src = m68k_read_memory_16(srca); | |
37759 | m68k_areg (regs, srcreg) = srca; | |
37760 | { uint32_t dsta = get_ilong_prefetch(2); | |
37761 | if ((dsta & 1) != 0) { | |
37762 | last_fault_for_exception_3 = dsta; | |
37763 | last_op_for_exception_3 = opcode; | |
37764 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
37765 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37766 | goto endlabel2127; | |
37767 | } | |
37768 | { CLEAR_CZNV; | |
37769 | SET_ZFLG (((int16_t)(src)) == 0); | |
37770 | SET_NFLG (((int16_t)(src)) < 0); | |
37771 | m68k_incpc(6); | |
37772 | fill_prefetch_0 (); | |
37773 | m68k_write_memory_16(dsta,src); | |
37774 | }}}}}}endlabel2127: ; | |
37775 | return 22; | |
37776 | } | |
37777 | unsigned long CPUFUNC(op_33e8_5)(uint32_t opcode) /* MOVE */ | |
37778 | { | |
37779 | uint32_t srcreg = (opcode & 7); | |
37780 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
37781 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
37782 | if ((srca & 1) != 0) { | |
37783 | last_fault_for_exception_3 = srca; | |
37784 | last_op_for_exception_3 = opcode; | |
37785 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
37786 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37787 | goto endlabel2128; | |
37788 | } | |
37789 | {{ int16_t src = m68k_read_memory_16(srca); | |
37790 | { uint32_t dsta = get_ilong_prefetch(4); | |
37791 | if ((dsta & 1) != 0) { | |
37792 | last_fault_for_exception_3 = dsta; | |
37793 | last_op_for_exception_3 = opcode; | |
37794 | last_addr_for_exception_3 = m68k_getpc() + 8; | |
37795 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37796 | goto endlabel2128; | |
37797 | } | |
37798 | { CLEAR_CZNV; | |
37799 | SET_ZFLG (((int16_t)(src)) == 0); | |
37800 | SET_NFLG (((int16_t)(src)) < 0); | |
37801 | m68k_incpc(8); | |
37802 | fill_prefetch_0 (); | |
37803 | m68k_write_memory_16(dsta,src); | |
37804 | }}}}}}endlabel2128: ; | |
37805 | return 24; | |
37806 | } | |
37807 | unsigned long CPUFUNC(op_33f0_5)(uint32_t opcode) /* MOVE */ | |
37808 | { | |
37809 | uint32_t srcreg = (opcode & 7); | |
37810 | OpcodeFamily = 30; CurrentInstrCycles = 26; | |
37811 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
37812 | BusCyclePenalty += 2; | |
37813 | if ((srca & 1) != 0) { | |
37814 | last_fault_for_exception_3 = srca; | |
37815 | last_op_for_exception_3 = opcode; | |
37816 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
37817 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37818 | goto endlabel2129; | |
37819 | } | |
37820 | {{ int16_t src = m68k_read_memory_16(srca); | |
37821 | { uint32_t dsta = get_ilong_prefetch(4); | |
37822 | if ((dsta & 1) != 0) { | |
37823 | last_fault_for_exception_3 = dsta; | |
37824 | last_op_for_exception_3 = opcode; | |
37825 | last_addr_for_exception_3 = m68k_getpc() + 8; | |
37826 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37827 | goto endlabel2129; | |
37828 | } | |
37829 | { CLEAR_CZNV; | |
37830 | SET_ZFLG (((int16_t)(src)) == 0); | |
37831 | SET_NFLG (((int16_t)(src)) < 0); | |
37832 | m68k_incpc(8); | |
37833 | fill_prefetch_0 (); | |
37834 | m68k_write_memory_16(dsta,src); | |
37835 | }}}}}}endlabel2129: ; | |
37836 | return 26; | |
37837 | } | |
37838 | unsigned long CPUFUNC(op_33f8_5)(uint32_t opcode) /* MOVE */ | |
37839 | { | |
37840 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
37841 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
37842 | if ((srca & 1) != 0) { | |
37843 | last_fault_for_exception_3 = srca; | |
37844 | last_op_for_exception_3 = opcode; | |
37845 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
37846 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37847 | goto endlabel2130; | |
37848 | } | |
37849 | {{ int16_t src = m68k_read_memory_16(srca); | |
37850 | { uint32_t dsta = get_ilong_prefetch(4); | |
37851 | if ((dsta & 1) != 0) { | |
37852 | last_fault_for_exception_3 = dsta; | |
37853 | last_op_for_exception_3 = opcode; | |
37854 | last_addr_for_exception_3 = m68k_getpc() + 8; | |
37855 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37856 | goto endlabel2130; | |
37857 | } | |
37858 | { CLEAR_CZNV; | |
37859 | SET_ZFLG (((int16_t)(src)) == 0); | |
37860 | SET_NFLG (((int16_t)(src)) < 0); | |
37861 | m68k_incpc(8); | |
37862 | fill_prefetch_0 (); | |
37863 | m68k_write_memory_16(dsta,src); | |
37864 | }}}}}}endlabel2130: ; | |
37865 | return 24; | |
37866 | } | |
37867 | unsigned long CPUFUNC(op_33f9_5)(uint32_t opcode) /* MOVE */ | |
37868 | { | |
37869 | OpcodeFamily = 30; CurrentInstrCycles = 28; | |
37870 | {{ uint32_t srca = get_ilong_prefetch(2); | |
37871 | if ((srca & 1) != 0) { | |
37872 | last_fault_for_exception_3 = srca; | |
37873 | last_op_for_exception_3 = opcode; | |
37874 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
37875 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37876 | goto endlabel2131; | |
37877 | } | |
37878 | {{ int16_t src = m68k_read_memory_16(srca); | |
37879 | { uint32_t dsta = get_ilong_prefetch(6); | |
37880 | if ((dsta & 1) != 0) { | |
37881 | last_fault_for_exception_3 = dsta; | |
37882 | last_op_for_exception_3 = opcode; | |
37883 | last_addr_for_exception_3 = m68k_getpc() + 10; | |
37884 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37885 | goto endlabel2131; | |
37886 | } | |
37887 | { CLEAR_CZNV; | |
37888 | SET_ZFLG (((int16_t)(src)) == 0); | |
37889 | SET_NFLG (((int16_t)(src)) < 0); | |
37890 | m68k_incpc(10); | |
37891 | fill_prefetch_0 (); | |
37892 | m68k_write_memory_16(dsta,src); | |
37893 | }}}}}}endlabel2131: ; | |
37894 | return 28; | |
37895 | } | |
37896 | unsigned long CPUFUNC(op_33fa_5)(uint32_t opcode) /* MOVE */ | |
37897 | { | |
37898 | OpcodeFamily = 30; CurrentInstrCycles = 24; | |
37899 | {{ uint32_t srca = m68k_getpc () + 2; | |
37900 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
37901 | if ((srca & 1) != 0) { | |
37902 | last_fault_for_exception_3 = srca; | |
37903 | last_op_for_exception_3 = opcode; | |
37904 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
37905 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37906 | goto endlabel2132; | |
37907 | } | |
37908 | {{ int16_t src = m68k_read_memory_16(srca); | |
37909 | { uint32_t dsta = get_ilong_prefetch(4); | |
37910 | if ((dsta & 1) != 0) { | |
37911 | last_fault_for_exception_3 = dsta; | |
37912 | last_op_for_exception_3 = opcode; | |
37913 | last_addr_for_exception_3 = m68k_getpc() + 8; | |
37914 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37915 | goto endlabel2132; | |
37916 | } | |
37917 | { CLEAR_CZNV; | |
37918 | SET_ZFLG (((int16_t)(src)) == 0); | |
37919 | SET_NFLG (((int16_t)(src)) < 0); | |
37920 | m68k_incpc(8); | |
37921 | fill_prefetch_0 (); | |
37922 | m68k_write_memory_16(dsta,src); | |
37923 | }}}}}}endlabel2132: ; | |
37924 | return 24; | |
37925 | } | |
37926 | unsigned long CPUFUNC(op_33fb_5)(uint32_t opcode) /* MOVE */ | |
37927 | { | |
37928 | OpcodeFamily = 30; CurrentInstrCycles = 26; | |
37929 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
37930 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
37931 | BusCyclePenalty += 2; | |
37932 | if ((srca & 1) != 0) { | |
37933 | last_fault_for_exception_3 = srca; | |
37934 | last_op_for_exception_3 = opcode; | |
37935 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
37936 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37937 | goto endlabel2133; | |
37938 | } | |
37939 | {{ int16_t src = m68k_read_memory_16(srca); | |
37940 | { uint32_t dsta = get_ilong_prefetch(4); | |
37941 | if ((dsta & 1) != 0) { | |
37942 | last_fault_for_exception_3 = dsta; | |
37943 | last_op_for_exception_3 = opcode; | |
37944 | last_addr_for_exception_3 = m68k_getpc() + 8; | |
37945 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37946 | goto endlabel2133; | |
37947 | } | |
37948 | { CLEAR_CZNV; | |
37949 | SET_ZFLG (((int16_t)(src)) == 0); | |
37950 | SET_NFLG (((int16_t)(src)) < 0); | |
37951 | m68k_incpc(8); | |
37952 | fill_prefetch_0 (); | |
37953 | m68k_write_memory_16(dsta,src); | |
37954 | }}}}}}endlabel2133: ; | |
37955 | return 26; | |
37956 | } | |
37957 | unsigned long CPUFUNC(op_33fc_5)(uint32_t opcode) /* MOVE */ | |
37958 | { | |
37959 | OpcodeFamily = 30; CurrentInstrCycles = 20; | |
37960 | {{ int16_t src = get_iword_prefetch(2); | |
37961 | { uint32_t dsta = get_ilong_prefetch(4); | |
37962 | if ((dsta & 1) != 0) { | |
37963 | last_fault_for_exception_3 = dsta; | |
37964 | last_op_for_exception_3 = opcode; | |
37965 | last_addr_for_exception_3 = m68k_getpc() + 8; | |
37966 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
37967 | goto endlabel2134; | |
37968 | } | |
37969 | { CLEAR_CZNV; | |
37970 | SET_ZFLG (((int16_t)(src)) == 0); | |
37971 | SET_NFLG (((int16_t)(src)) < 0); | |
37972 | m68k_incpc(8); | |
37973 | fill_prefetch_0 (); | |
37974 | m68k_write_memory_16(dsta,src); | |
37975 | }}}}endlabel2134: ; | |
37976 | return 20; | |
37977 | } | |
37978 | unsigned long CPUFUNC(op_4000_5)(uint32_t opcode) /* NEGX */ | |
37979 | { | |
37980 | uint32_t srcreg = (opcode & 7); | |
37981 | OpcodeFamily = 16; CurrentInstrCycles = 4; | |
37982 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
37983 | { uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); | |
37984 | { int flgs = ((int8_t)(src)) < 0; | |
37985 | int flgo = ((int8_t)(0)) < 0; | |
37986 | int flgn = ((int8_t)(newv)) < 0; | |
37987 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
37988 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
37989 | COPY_CARRY; | |
37990 | SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); | |
37991 | SET_NFLG (((int8_t)(newv)) < 0); | |
37992 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((newv) & 0xff); | |
37993 | }}}}m68k_incpc(2); | |
37994 | fill_prefetch_2 (); | |
37995 | return 4; | |
37996 | } | |
37997 | unsigned long CPUFUNC(op_4010_5)(uint32_t opcode) /* NEGX */ | |
37998 | { | |
37999 | uint32_t srcreg = (opcode & 7); | |
38000 | OpcodeFamily = 16; CurrentInstrCycles = 12; | |
38001 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
38002 | { int8_t src = m68k_read_memory_8(srca); | |
38003 | { uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); | |
38004 | { int flgs = ((int8_t)(src)) < 0; | |
38005 | int flgo = ((int8_t)(0)) < 0; | |
38006 | int flgn = ((int8_t)(newv)) < 0; | |
38007 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
38008 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
38009 | COPY_CARRY; | |
38010 | SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); | |
38011 | SET_NFLG (((int8_t)(newv)) < 0); | |
38012 | m68k_incpc(2); | |
38013 | fill_prefetch_2 (); | |
38014 | m68k_write_memory_8(srca,newv); | |
38015 | }}}}}return 12; | |
38016 | } | |
38017 | unsigned long CPUFUNC(op_4018_5)(uint32_t opcode) /* NEGX */ | |
38018 | { | |
38019 | uint32_t srcreg = (opcode & 7); | |
38020 | OpcodeFamily = 16; CurrentInstrCycles = 12; | |
38021 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
38022 | { int8_t src = m68k_read_memory_8(srca); | |
38023 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
38024 | { uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); | |
38025 | { int flgs = ((int8_t)(src)) < 0; | |
38026 | int flgo = ((int8_t)(0)) < 0; | |
38027 | int flgn = ((int8_t)(newv)) < 0; | |
38028 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
38029 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
38030 | COPY_CARRY; | |
38031 | SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); | |
38032 | SET_NFLG (((int8_t)(newv)) < 0); | |
38033 | m68k_incpc(2); | |
38034 | fill_prefetch_2 (); | |
38035 | m68k_write_memory_8(srca,newv); | |
38036 | }}}}}return 12; | |
38037 | } | |
38038 | unsigned long CPUFUNC(op_4020_5)(uint32_t opcode) /* NEGX */ | |
38039 | { | |
38040 | uint32_t srcreg = (opcode & 7); | |
38041 | OpcodeFamily = 16; CurrentInstrCycles = 14; | |
38042 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
38043 | { int8_t src = m68k_read_memory_8(srca); | |
38044 | m68k_areg (regs, srcreg) = srca; | |
38045 | { uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); | |
38046 | { int flgs = ((int8_t)(src)) < 0; | |
38047 | int flgo = ((int8_t)(0)) < 0; | |
38048 | int flgn = ((int8_t)(newv)) < 0; | |
38049 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
38050 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
38051 | COPY_CARRY; | |
38052 | SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); | |
38053 | SET_NFLG (((int8_t)(newv)) < 0); | |
38054 | m68k_incpc(2); | |
38055 | fill_prefetch_2 (); | |
38056 | m68k_write_memory_8(srca,newv); | |
38057 | }}}}}return 14; | |
38058 | } | |
38059 | unsigned long CPUFUNC(op_4028_5)(uint32_t opcode) /* NEGX */ | |
38060 | { | |
38061 | uint32_t srcreg = (opcode & 7); | |
38062 | OpcodeFamily = 16; CurrentInstrCycles = 16; | |
38063 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
38064 | { int8_t src = m68k_read_memory_8(srca); | |
38065 | { uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); | |
38066 | { int flgs = ((int8_t)(src)) < 0; | |
38067 | int flgo = ((int8_t)(0)) < 0; | |
38068 | int flgn = ((int8_t)(newv)) < 0; | |
38069 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
38070 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
38071 | COPY_CARRY; | |
38072 | SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); | |
38073 | SET_NFLG (((int8_t)(newv)) < 0); | |
38074 | m68k_incpc(4); | |
38075 | fill_prefetch_0 (); | |
38076 | m68k_write_memory_8(srca,newv); | |
38077 | }}}}}return 16; | |
38078 | } | |
38079 | unsigned long CPUFUNC(op_4030_5)(uint32_t opcode) /* NEGX */ | |
38080 | { | |
38081 | uint32_t srcreg = (opcode & 7); | |
38082 | OpcodeFamily = 16; CurrentInstrCycles = 18; | |
38083 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
38084 | BusCyclePenalty += 2; | |
38085 | { int8_t src = m68k_read_memory_8(srca); | |
38086 | { uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); | |
38087 | { int flgs = ((int8_t)(src)) < 0; | |
38088 | int flgo = ((int8_t)(0)) < 0; | |
38089 | int flgn = ((int8_t)(newv)) < 0; | |
38090 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
38091 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
38092 | COPY_CARRY; | |
38093 | SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); | |
38094 | SET_NFLG (((int8_t)(newv)) < 0); | |
38095 | m68k_incpc(4); | |
38096 | fill_prefetch_0 (); | |
38097 | m68k_write_memory_8(srca,newv); | |
38098 | }}}}}return 18; | |
38099 | } | |
38100 | unsigned long CPUFUNC(op_4038_5)(uint32_t opcode) /* NEGX */ | |
38101 | { | |
38102 | OpcodeFamily = 16; CurrentInstrCycles = 16; | |
38103 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
38104 | { int8_t src = m68k_read_memory_8(srca); | |
38105 | { uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); | |
38106 | { int flgs = ((int8_t)(src)) < 0; | |
38107 | int flgo = ((int8_t)(0)) < 0; | |
38108 | int flgn = ((int8_t)(newv)) < 0; | |
38109 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
38110 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
38111 | COPY_CARRY; | |
38112 | SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); | |
38113 | SET_NFLG (((int8_t)(newv)) < 0); | |
38114 | m68k_incpc(4); | |
38115 | fill_prefetch_0 (); | |
38116 | m68k_write_memory_8(srca,newv); | |
38117 | }}}}}return 16; | |
38118 | } | |
38119 | unsigned long CPUFUNC(op_4039_5)(uint32_t opcode) /* NEGX */ | |
38120 | { | |
38121 | OpcodeFamily = 16; CurrentInstrCycles = 20; | |
38122 | {{ uint32_t srca = get_ilong_prefetch(2); | |
38123 | { int8_t src = m68k_read_memory_8(srca); | |
38124 | { uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); | |
38125 | { int flgs = ((int8_t)(src)) < 0; | |
38126 | int flgo = ((int8_t)(0)) < 0; | |
38127 | int flgn = ((int8_t)(newv)) < 0; | |
38128 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
38129 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
38130 | COPY_CARRY; | |
38131 | SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); | |
38132 | SET_NFLG (((int8_t)(newv)) < 0); | |
38133 | m68k_incpc(6); | |
38134 | fill_prefetch_0 (); | |
38135 | m68k_write_memory_8(srca,newv); | |
38136 | }}}}}return 20; | |
38137 | } | |
38138 | unsigned long CPUFUNC(op_4040_5)(uint32_t opcode) /* NEGX */ | |
38139 | { | |
38140 | uint32_t srcreg = (opcode & 7); | |
38141 | OpcodeFamily = 16; CurrentInstrCycles = 4; | |
38142 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
38143 | { uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); | |
38144 | { int flgs = ((int16_t)(src)) < 0; | |
38145 | int flgo = ((int16_t)(0)) < 0; | |
38146 | int flgn = ((int16_t)(newv)) < 0; | |
38147 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
38148 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
38149 | COPY_CARRY; | |
38150 | SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0)); | |
38151 | SET_NFLG (((int16_t)(newv)) < 0); | |
38152 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((newv) & 0xffff); | |
38153 | }}}}m68k_incpc(2); | |
38154 | fill_prefetch_2 (); | |
38155 | return 4; | |
38156 | } | |
38157 | unsigned long CPUFUNC(op_4050_5)(uint32_t opcode) /* NEGX */ | |
38158 | { | |
38159 | uint32_t srcreg = (opcode & 7); | |
38160 | OpcodeFamily = 16; CurrentInstrCycles = 12; | |
38161 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
38162 | if ((srca & 1) != 0) { | |
38163 | last_fault_for_exception_3 = srca; | |
38164 | last_op_for_exception_3 = opcode; | |
38165 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
38166 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
38167 | goto endlabel2144; | |
38168 | } | |
38169 | {{ int16_t src = m68k_read_memory_16(srca); | |
38170 | { uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); | |
38171 | { int flgs = ((int16_t)(src)) < 0; | |
38172 | int flgo = ((int16_t)(0)) < 0; | |
38173 | int flgn = ((int16_t)(newv)) < 0; | |
38174 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
38175 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
38176 | COPY_CARRY; | |
38177 | SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0)); | |
38178 | SET_NFLG (((int16_t)(newv)) < 0); | |
38179 | m68k_incpc(2); | |
38180 | fill_prefetch_2 (); | |
38181 | m68k_write_memory_16(srca,newv); | |
38182 | }}}}}}endlabel2144: ; | |
38183 | return 12; | |
38184 | } | |
38185 | unsigned long CPUFUNC(op_4058_5)(uint32_t opcode) /* NEGX */ | |
38186 | { | |
38187 | uint32_t srcreg = (opcode & 7); | |
38188 | OpcodeFamily = 16; CurrentInstrCycles = 12; | |
38189 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
38190 | if ((srca & 1) != 0) { | |
38191 | last_fault_for_exception_3 = srca; | |
38192 | last_op_for_exception_3 = opcode; | |
38193 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
38194 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
38195 | goto endlabel2145; | |
38196 | } | |
38197 | {{ int16_t src = m68k_read_memory_16(srca); | |
38198 | m68k_areg(regs, srcreg) += 2; | |
38199 | { uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); | |
38200 | { int flgs = ((int16_t)(src)) < 0; | |
38201 | int flgo = ((int16_t)(0)) < 0; | |
38202 | int flgn = ((int16_t)(newv)) < 0; | |
38203 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
38204 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
38205 | COPY_CARRY; | |
38206 | SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0)); | |
38207 | SET_NFLG (((int16_t)(newv)) < 0); | |
38208 | m68k_incpc(2); | |
38209 | fill_prefetch_2 (); | |
38210 | m68k_write_memory_16(srca,newv); | |
38211 | }}}}}}endlabel2145: ; | |
38212 | return 12; | |
38213 | } | |
38214 | unsigned long CPUFUNC(op_4060_5)(uint32_t opcode) /* NEGX */ | |
38215 | { | |
38216 | uint32_t srcreg = (opcode & 7); | |
38217 | OpcodeFamily = 16; CurrentInstrCycles = 14; | |
38218 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
38219 | if ((srca & 1) != 0) { | |
38220 | last_fault_for_exception_3 = srca; | |
38221 | last_op_for_exception_3 = opcode; | |
38222 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
38223 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
38224 | goto endlabel2146; | |
38225 | } | |
38226 | {{ int16_t src = m68k_read_memory_16(srca); | |
38227 | m68k_areg (regs, srcreg) = srca; | |
38228 | { uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); | |
38229 | { int flgs = ((int16_t)(src)) < 0; | |
38230 | int flgo = ((int16_t)(0)) < 0; | |
38231 | int flgn = ((int16_t)(newv)) < 0; | |
38232 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
38233 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
38234 | COPY_CARRY; | |
38235 | SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0)); | |
38236 | SET_NFLG (((int16_t)(newv)) < 0); | |
38237 | m68k_incpc(2); | |
38238 | fill_prefetch_2 (); | |
38239 | m68k_write_memory_16(srca,newv); | |
38240 | }}}}}}endlabel2146: ; | |
38241 | return 14; | |
38242 | } | |
38243 | unsigned long CPUFUNC(op_4068_5)(uint32_t opcode) /* NEGX */ | |
38244 | { | |
38245 | uint32_t srcreg = (opcode & 7); | |
38246 | OpcodeFamily = 16; CurrentInstrCycles = 16; | |
38247 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
38248 | if ((srca & 1) != 0) { | |
38249 | last_fault_for_exception_3 = srca; | |
38250 | last_op_for_exception_3 = opcode; | |
38251 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
38252 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
38253 | goto endlabel2147; | |
38254 | } | |
38255 | {{ int16_t src = m68k_read_memory_16(srca); | |
38256 | { uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); | |
38257 | { int flgs = ((int16_t)(src)) < 0; | |
38258 | int flgo = ((int16_t)(0)) < 0; | |
38259 | int flgn = ((int16_t)(newv)) < 0; | |
38260 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
38261 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
38262 | COPY_CARRY; | |
38263 | SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0)); | |
38264 | SET_NFLG (((int16_t)(newv)) < 0); | |
38265 | m68k_incpc(4); | |
38266 | fill_prefetch_0 (); | |
38267 | m68k_write_memory_16(srca,newv); | |
38268 | }}}}}}endlabel2147: ; | |
38269 | return 16; | |
38270 | } | |
38271 | unsigned long CPUFUNC(op_4070_5)(uint32_t opcode) /* NEGX */ | |
38272 | { | |
38273 | uint32_t srcreg = (opcode & 7); | |
38274 | OpcodeFamily = 16; CurrentInstrCycles = 18; | |
38275 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
38276 | BusCyclePenalty += 2; | |
38277 | if ((srca & 1) != 0) { | |
38278 | last_fault_for_exception_3 = srca; | |
38279 | last_op_for_exception_3 = opcode; | |
38280 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
38281 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
38282 | goto endlabel2148; | |
38283 | } | |
38284 | {{ int16_t src = m68k_read_memory_16(srca); | |
38285 | { uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); | |
38286 | { int flgs = ((int16_t)(src)) < 0; | |
38287 | int flgo = ((int16_t)(0)) < 0; | |
38288 | int flgn = ((int16_t)(newv)) < 0; | |
38289 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
38290 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
38291 | COPY_CARRY; | |
38292 | SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0)); | |
38293 | SET_NFLG (((int16_t)(newv)) < 0); | |
38294 | m68k_incpc(4); | |
38295 | fill_prefetch_0 (); | |
38296 | m68k_write_memory_16(srca,newv); | |
38297 | }}}}}}endlabel2148: ; | |
38298 | return 18; | |
38299 | } | |
38300 | unsigned long CPUFUNC(op_4078_5)(uint32_t opcode) /* NEGX */ | |
38301 | { | |
38302 | OpcodeFamily = 16; CurrentInstrCycles = 16; | |
38303 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
38304 | if ((srca & 1) != 0) { | |
38305 | last_fault_for_exception_3 = srca; | |
38306 | last_op_for_exception_3 = opcode; | |
38307 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
38308 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
38309 | goto endlabel2149; | |
38310 | } | |
38311 | {{ int16_t src = m68k_read_memory_16(srca); | |
38312 | { uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); | |
38313 | { int flgs = ((int16_t)(src)) < 0; | |
38314 | int flgo = ((int16_t)(0)) < 0; | |
38315 | int flgn = ((int16_t)(newv)) < 0; | |
38316 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
38317 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
38318 | COPY_CARRY; | |
38319 | SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0)); | |
38320 | SET_NFLG (((int16_t)(newv)) < 0); | |
38321 | m68k_incpc(4); | |
38322 | fill_prefetch_0 (); | |
38323 | m68k_write_memory_16(srca,newv); | |
38324 | }}}}}}endlabel2149: ; | |
38325 | return 16; | |
38326 | } | |
38327 | unsigned long CPUFUNC(op_4079_5)(uint32_t opcode) /* NEGX */ | |
38328 | { | |
38329 | OpcodeFamily = 16; CurrentInstrCycles = 20; | |
38330 | {{ uint32_t srca = get_ilong_prefetch(2); | |
38331 | if ((srca & 1) != 0) { | |
38332 | last_fault_for_exception_3 = srca; | |
38333 | last_op_for_exception_3 = opcode; | |
38334 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
38335 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
38336 | goto endlabel2150; | |
38337 | } | |
38338 | {{ int16_t src = m68k_read_memory_16(srca); | |
38339 | { uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); | |
38340 | { int flgs = ((int16_t)(src)) < 0; | |
38341 | int flgo = ((int16_t)(0)) < 0; | |
38342 | int flgn = ((int16_t)(newv)) < 0; | |
38343 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
38344 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
38345 | COPY_CARRY; | |
38346 | SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0)); | |
38347 | SET_NFLG (((int16_t)(newv)) < 0); | |
38348 | m68k_incpc(6); | |
38349 | fill_prefetch_0 (); | |
38350 | m68k_write_memory_16(srca,newv); | |
38351 | }}}}}}endlabel2150: ; | |
38352 | return 20; | |
38353 | } | |
38354 | unsigned long CPUFUNC(op_4080_5)(uint32_t opcode) /* NEGX */ | |
38355 | { | |
38356 | uint32_t srcreg = (opcode & 7); | |
38357 | OpcodeFamily = 16; CurrentInstrCycles = 6; | |
38358 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
38359 | { uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); | |
38360 | { int flgs = ((int32_t)(src)) < 0; | |
38361 | int flgo = ((int32_t)(0)) < 0; | |
38362 | int flgn = ((int32_t)(newv)) < 0; | |
38363 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
38364 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
38365 | COPY_CARRY; | |
38366 | SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0)); | |
38367 | SET_NFLG (((int32_t)(newv)) < 0); | |
38368 | m68k_dreg(regs, srcreg) = (newv); | |
38369 | }}}}m68k_incpc(2); | |
38370 | fill_prefetch_2 (); | |
38371 | return 6; | |
38372 | } | |
38373 | unsigned long CPUFUNC(op_4090_5)(uint32_t opcode) /* NEGX */ | |
38374 | { | |
38375 | uint32_t srcreg = (opcode & 7); | |
38376 | OpcodeFamily = 16; CurrentInstrCycles = 20; | |
38377 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
38378 | if ((srca & 1) != 0) { | |
38379 | last_fault_for_exception_3 = srca; | |
38380 | last_op_for_exception_3 = opcode; | |
38381 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
38382 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
38383 | goto endlabel2152; | |
38384 | } | |
38385 | {{ int32_t src = m68k_read_memory_32(srca); | |
38386 | { uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); | |
38387 | { int flgs = ((int32_t)(src)) < 0; | |
38388 | int flgo = ((int32_t)(0)) < 0; | |
38389 | int flgn = ((int32_t)(newv)) < 0; | |
38390 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
38391 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
38392 | COPY_CARRY; | |
38393 | SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0)); | |
38394 | SET_NFLG (((int32_t)(newv)) < 0); | |
38395 | m68k_incpc(2); | |
38396 | fill_prefetch_2 (); | |
38397 | m68k_write_memory_32(srca,newv); | |
38398 | }}}}}}endlabel2152: ; | |
38399 | return 20; | |
38400 | } | |
38401 | unsigned long CPUFUNC(op_4098_5)(uint32_t opcode) /* NEGX */ | |
38402 | { | |
38403 | uint32_t srcreg = (opcode & 7); | |
38404 | OpcodeFamily = 16; CurrentInstrCycles = 20; | |
38405 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
38406 | if ((srca & 1) != 0) { | |
38407 | last_fault_for_exception_3 = srca; | |
38408 | last_op_for_exception_3 = opcode; | |
38409 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
38410 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
38411 | goto endlabel2153; | |
38412 | } | |
38413 | {{ int32_t src = m68k_read_memory_32(srca); | |
38414 | m68k_areg(regs, srcreg) += 4; | |
38415 | { uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); | |
38416 | { int flgs = ((int32_t)(src)) < 0; | |
38417 | int flgo = ((int32_t)(0)) < 0; | |
38418 | int flgn = ((int32_t)(newv)) < 0; | |
38419 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
38420 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
38421 | COPY_CARRY; | |
38422 | SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0)); | |
38423 | SET_NFLG (((int32_t)(newv)) < 0); | |
38424 | m68k_incpc(2); | |
38425 | fill_prefetch_2 (); | |
38426 | m68k_write_memory_32(srca,newv); | |
38427 | }}}}}}endlabel2153: ; | |
38428 | return 20; | |
38429 | } | |
38430 | unsigned long CPUFUNC(op_40a0_5)(uint32_t opcode) /* NEGX */ | |
38431 | { | |
38432 | uint32_t srcreg = (opcode & 7); | |
38433 | OpcodeFamily = 16; CurrentInstrCycles = 22; | |
38434 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 4; | |
38435 | if ((srca & 1) != 0) { | |
38436 | last_fault_for_exception_3 = srca; | |
38437 | last_op_for_exception_3 = opcode; | |
38438 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
38439 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
38440 | goto endlabel2154; | |
38441 | } | |
38442 | {{ int32_t src = m68k_read_memory_32(srca); | |
38443 | m68k_areg (regs, srcreg) = srca; | |
38444 | { uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); | |
38445 | { int flgs = ((int32_t)(src)) < 0; | |
38446 | int flgo = ((int32_t)(0)) < 0; | |
38447 | int flgn = ((int32_t)(newv)) < 0; | |
38448 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
38449 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
38450 | COPY_CARRY; | |
38451 | SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0)); | |
38452 | SET_NFLG (((int32_t)(newv)) < 0); | |
38453 | m68k_incpc(2); | |
38454 | fill_prefetch_2 (); | |
38455 | m68k_write_memory_32(srca,newv); | |
38456 | }}}}}}endlabel2154: ; | |
38457 | return 22; | |
38458 | } | |
38459 | unsigned long CPUFUNC(op_40a8_5)(uint32_t opcode) /* NEGX */ | |
38460 | { | |
38461 | uint32_t srcreg = (opcode & 7); | |
38462 | OpcodeFamily = 16; CurrentInstrCycles = 24; | |
38463 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
38464 | if ((srca & 1) != 0) { | |
38465 | last_fault_for_exception_3 = srca; | |
38466 | last_op_for_exception_3 = opcode; | |
38467 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
38468 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
38469 | goto endlabel2155; | |
38470 | } | |
38471 | {{ int32_t src = m68k_read_memory_32(srca); | |
38472 | { uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); | |
38473 | { int flgs = ((int32_t)(src)) < 0; | |
38474 | int flgo = ((int32_t)(0)) < 0; | |
38475 | int flgn = ((int32_t)(newv)) < 0; | |
38476 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
38477 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
38478 | COPY_CARRY; | |
38479 | SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0)); | |
38480 | SET_NFLG (((int32_t)(newv)) < 0); | |
38481 | m68k_incpc(4); | |
38482 | fill_prefetch_0 (); | |
38483 | m68k_write_memory_32(srca,newv); | |
38484 | }}}}}}endlabel2155: ; | |
38485 | return 24; | |
38486 | } | |
38487 | unsigned long CPUFUNC(op_40b0_5)(uint32_t opcode) /* NEGX */ | |
38488 | { | |
38489 | uint32_t srcreg = (opcode & 7); | |
38490 | OpcodeFamily = 16; CurrentInstrCycles = 26; | |
38491 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
38492 | BusCyclePenalty += 2; | |
38493 | if ((srca & 1) != 0) { | |
38494 | last_fault_for_exception_3 = srca; | |
38495 | last_op_for_exception_3 = opcode; | |
38496 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
38497 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
38498 | goto endlabel2156; | |
38499 | } | |
38500 | {{ int32_t src = m68k_read_memory_32(srca); | |
38501 | { uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); | |
38502 | { int flgs = ((int32_t)(src)) < 0; | |
38503 | int flgo = ((int32_t)(0)) < 0; | |
38504 | int flgn = ((int32_t)(newv)) < 0; | |
38505 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
38506 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
38507 | COPY_CARRY; | |
38508 | SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0)); | |
38509 | SET_NFLG (((int32_t)(newv)) < 0); | |
38510 | m68k_incpc(4); | |
38511 | fill_prefetch_0 (); | |
38512 | m68k_write_memory_32(srca,newv); | |
38513 | }}}}}}endlabel2156: ; | |
38514 | return 26; | |
38515 | } | |
38516 | unsigned long CPUFUNC(op_40b8_5)(uint32_t opcode) /* NEGX */ | |
38517 | { | |
38518 | OpcodeFamily = 16; CurrentInstrCycles = 24; | |
38519 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
38520 | if ((srca & 1) != 0) { | |
38521 | last_fault_for_exception_3 = srca; | |
38522 | last_op_for_exception_3 = opcode; | |
38523 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
38524 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
38525 | goto endlabel2157; | |
38526 | } | |
38527 | {{ int32_t src = m68k_read_memory_32(srca); | |
38528 | { uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); | |
38529 | { int flgs = ((int32_t)(src)) < 0; | |
38530 | int flgo = ((int32_t)(0)) < 0; | |
38531 | int flgn = ((int32_t)(newv)) < 0; | |
38532 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
38533 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
38534 | COPY_CARRY; | |
38535 | SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0)); | |
38536 | SET_NFLG (((int32_t)(newv)) < 0); | |
38537 | m68k_incpc(4); | |
38538 | fill_prefetch_0 (); | |
38539 | m68k_write_memory_32(srca,newv); | |
38540 | }}}}}}endlabel2157: ; | |
38541 | return 24; | |
38542 | } | |
38543 | unsigned long CPUFUNC(op_40b9_5)(uint32_t opcode) /* NEGX */ | |
38544 | { | |
38545 | OpcodeFamily = 16; CurrentInstrCycles = 28; | |
38546 | {{ uint32_t srca = get_ilong_prefetch(2); | |
38547 | if ((srca & 1) != 0) { | |
38548 | last_fault_for_exception_3 = srca; | |
38549 | last_op_for_exception_3 = opcode; | |
38550 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
38551 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
38552 | goto endlabel2158; | |
38553 | } | |
38554 | {{ int32_t src = m68k_read_memory_32(srca); | |
38555 | { uint32_t newv = 0 - src - (GET_XFLG ? 1 : 0); | |
38556 | { int flgs = ((int32_t)(src)) < 0; | |
38557 | int flgo = ((int32_t)(0)) < 0; | |
38558 | int flgn = ((int32_t)(newv)) < 0; | |
38559 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
38560 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
38561 | COPY_CARRY; | |
38562 | SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0)); | |
38563 | SET_NFLG (((int32_t)(newv)) < 0); | |
38564 | m68k_incpc(6); | |
38565 | fill_prefetch_0 (); | |
38566 | m68k_write_memory_32(srca,newv); | |
38567 | }}}}}}endlabel2158: ; | |
38568 | return 28; | |
38569 | } | |
38570 | unsigned long CPUFUNC(op_40c0_5)(uint32_t opcode) /* MVSR2 */ | |
38571 | { | |
38572 | uint32_t srcreg = (opcode & 7); | |
38573 | OpcodeFamily = 32; CurrentInstrCycles = 6; | |
38574 | {{ MakeSR(); | |
38575 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((regs.sr) & 0xffff); | |
38576 | }}m68k_incpc(2); | |
38577 | fill_prefetch_2 (); | |
38578 | return 6; | |
38579 | } | |
38580 | unsigned long CPUFUNC(op_40d0_5)(uint32_t opcode) /* MVSR2 */ | |
38581 | { | |
38582 | uint32_t srcreg = (opcode & 7); | |
38583 | OpcodeFamily = 32; CurrentInstrCycles = 12; | |
38584 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
38585 | if ((srca & 1) != 0) { | |
38586 | last_fault_for_exception_3 = srca; | |
38587 | last_op_for_exception_3 = opcode; | |
38588 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
38589 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
38590 | goto endlabel2160; | |
38591 | } | |
38592 | { MakeSR(); | |
38593 | m68k_incpc(2); | |
38594 | fill_prefetch_2 (); | |
38595 | m68k_write_memory_16(srca,regs.sr); | |
38596 | }}}endlabel2160: ; | |
38597 | return 12; | |
38598 | } | |
38599 | unsigned long CPUFUNC(op_40d8_5)(uint32_t opcode) /* MVSR2 */ | |
38600 | { | |
38601 | uint32_t srcreg = (opcode & 7); | |
38602 | OpcodeFamily = 32; CurrentInstrCycles = 12; | |
38603 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
38604 | if ((srca & 1) != 0) { | |
38605 | last_fault_for_exception_3 = srca; | |
38606 | last_op_for_exception_3 = opcode; | |
38607 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
38608 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
38609 | goto endlabel2161; | |
38610 | } | |
38611 | { m68k_areg(regs, srcreg) += 2; | |
38612 | MakeSR(); | |
38613 | m68k_incpc(2); | |
38614 | fill_prefetch_2 (); | |
38615 | m68k_write_memory_16(srca,regs.sr); | |
38616 | }}}endlabel2161: ; | |
38617 | return 12; | |
38618 | } | |
38619 | unsigned long CPUFUNC(op_40e0_5)(uint32_t opcode) /* MVSR2 */ | |
38620 | { | |
38621 | uint32_t srcreg = (opcode & 7); | |
38622 | OpcodeFamily = 32; CurrentInstrCycles = 14; | |
38623 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
38624 | if ((srca & 1) != 0) { | |
38625 | last_fault_for_exception_3 = srca; | |
38626 | last_op_for_exception_3 = opcode; | |
38627 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
38628 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
38629 | goto endlabel2162; | |
38630 | } | |
38631 | { m68k_areg (regs, srcreg) = srca; | |
38632 | MakeSR(); | |
38633 | m68k_incpc(2); | |
38634 | fill_prefetch_2 (); | |
38635 | m68k_write_memory_16(srca,regs.sr); | |
38636 | }}}endlabel2162: ; | |
38637 | return 14; | |
38638 | } | |
38639 | unsigned long CPUFUNC(op_40e8_5)(uint32_t opcode) /* MVSR2 */ | |
38640 | { | |
38641 | uint32_t srcreg = (opcode & 7); | |
38642 | OpcodeFamily = 32; CurrentInstrCycles = 16; | |
38643 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
38644 | if ((srca & 1) != 0) { | |
38645 | last_fault_for_exception_3 = srca; | |
38646 | last_op_for_exception_3 = opcode; | |
38647 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
38648 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
38649 | goto endlabel2163; | |
38650 | } | |
38651 | { MakeSR(); | |
38652 | m68k_incpc(4); | |
38653 | fill_prefetch_0 (); | |
38654 | m68k_write_memory_16(srca,regs.sr); | |
38655 | }}}endlabel2163: ; | |
38656 | return 16; | |
38657 | } | |
38658 | unsigned long CPUFUNC(op_40f0_5)(uint32_t opcode) /* MVSR2 */ | |
38659 | { | |
38660 | uint32_t srcreg = (opcode & 7); | |
38661 | OpcodeFamily = 32; CurrentInstrCycles = 18; | |
38662 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
38663 | BusCyclePenalty += 2; | |
38664 | if ((srca & 1) != 0) { | |
38665 | last_fault_for_exception_3 = srca; | |
38666 | last_op_for_exception_3 = opcode; | |
38667 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
38668 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
38669 | goto endlabel2164; | |
38670 | } | |
38671 | { MakeSR(); | |
38672 | m68k_incpc(4); | |
38673 | fill_prefetch_0 (); | |
38674 | m68k_write_memory_16(srca,regs.sr); | |
38675 | }}}endlabel2164: ; | |
38676 | return 18; | |
38677 | } | |
38678 | unsigned long CPUFUNC(op_40f8_5)(uint32_t opcode) /* MVSR2 */ | |
38679 | { | |
38680 | OpcodeFamily = 32; CurrentInstrCycles = 16; | |
38681 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
38682 | if ((srca & 1) != 0) { | |
38683 | last_fault_for_exception_3 = srca; | |
38684 | last_op_for_exception_3 = opcode; | |
38685 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
38686 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
38687 | goto endlabel2165; | |
38688 | } | |
38689 | { MakeSR(); | |
38690 | m68k_incpc(4); | |
38691 | fill_prefetch_0 (); | |
38692 | m68k_write_memory_16(srca,regs.sr); | |
38693 | }}}endlabel2165: ; | |
38694 | return 16; | |
38695 | } | |
38696 | unsigned long CPUFUNC(op_40f9_5)(uint32_t opcode) /* MVSR2 */ | |
38697 | { | |
38698 | OpcodeFamily = 32; CurrentInstrCycles = 20; | |
38699 | {{ uint32_t srca = get_ilong_prefetch(2); | |
38700 | if ((srca & 1) != 0) { | |
38701 | last_fault_for_exception_3 = srca; | |
38702 | last_op_for_exception_3 = opcode; | |
38703 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
38704 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
38705 | goto endlabel2166; | |
38706 | } | |
38707 | { MakeSR(); | |
38708 | m68k_incpc(6); | |
38709 | fill_prefetch_0 (); | |
38710 | m68k_write_memory_16(srca,regs.sr); | |
38711 | }}}endlabel2166: ; | |
38712 | return 20; | |
38713 | } | |
38714 | unsigned long CPUFUNC(op_4180_5)(uint32_t opcode) /* CHK */ | |
38715 | { | |
38716 | uint32_t srcreg = (opcode & 7); | |
38717 | uint32_t dstreg = (opcode >> 9) & 7; | |
38718 | OpcodeFamily = 80; CurrentInstrCycles = 10; | |
38719 | { uint32_t oldpc = m68k_getpc(); | |
38720 | { int16_t src = m68k_dreg(regs, srcreg); | |
38721 | { int16_t dst = m68k_dreg(regs, dstreg); | |
38722 | m68k_incpc(2); | |
38723 | fill_prefetch_2 (); | |
38724 | if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2167; } | |
38725 | else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2167; } | |
38726 | }}}endlabel2167: ; | |
38727 | return 10; | |
38728 | } | |
38729 | unsigned long CPUFUNC(op_4190_5)(uint32_t opcode) /* CHK */ | |
38730 | { | |
38731 | uint32_t srcreg = (opcode & 7); | |
38732 | uint32_t dstreg = (opcode >> 9) & 7; | |
38733 | OpcodeFamily = 80; CurrentInstrCycles = 14; | |
38734 | { uint32_t oldpc = m68k_getpc(); | |
38735 | { uint32_t srca = m68k_areg(regs, srcreg); | |
38736 | if ((srca & 1) != 0) { | |
38737 | last_fault_for_exception_3 = srca; | |
38738 | last_op_for_exception_3 = opcode; | |
38739 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
38740 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
38741 | goto endlabel2168; | |
38742 | } | |
38743 | {{ int16_t src = m68k_read_memory_16(srca); | |
38744 | { int16_t dst = m68k_dreg(regs, dstreg); | |
38745 | m68k_incpc(2); | |
38746 | fill_prefetch_2 (); | |
38747 | if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2168; } | |
38748 | else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2168; } | |
38749 | }}}}}endlabel2168: ; | |
38750 | return 14; | |
38751 | } | |
38752 | unsigned long CPUFUNC(op_4198_5)(uint32_t opcode) /* CHK */ | |
38753 | { | |
38754 | uint32_t srcreg = (opcode & 7); | |
38755 | uint32_t dstreg = (opcode >> 9) & 7; | |
38756 | OpcodeFamily = 80; CurrentInstrCycles = 14; | |
38757 | { uint32_t oldpc = m68k_getpc(); | |
38758 | { uint32_t srca = m68k_areg(regs, srcreg); | |
38759 | if ((srca & 1) != 0) { | |
38760 | last_fault_for_exception_3 = srca; | |
38761 | last_op_for_exception_3 = opcode; | |
38762 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
38763 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
38764 | goto endlabel2169; | |
38765 | } | |
38766 | {{ int16_t src = m68k_read_memory_16(srca); | |
38767 | m68k_areg(regs, srcreg) += 2; | |
38768 | { int16_t dst = m68k_dreg(regs, dstreg); | |
38769 | m68k_incpc(2); | |
38770 | fill_prefetch_2 (); | |
38771 | if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2169; } | |
38772 | else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2169; } | |
38773 | }}}}}endlabel2169: ; | |
38774 | return 14; | |
38775 | } | |
38776 | unsigned long CPUFUNC(op_41a0_5)(uint32_t opcode) /* CHK */ | |
38777 | { | |
38778 | uint32_t srcreg = (opcode & 7); | |
38779 | uint32_t dstreg = (opcode >> 9) & 7; | |
38780 | OpcodeFamily = 80; CurrentInstrCycles = 16; | |
38781 | { uint32_t oldpc = m68k_getpc(); | |
38782 | { uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
38783 | if ((srca & 1) != 0) { | |
38784 | last_fault_for_exception_3 = srca; | |
38785 | last_op_for_exception_3 = opcode; | |
38786 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
38787 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
38788 | goto endlabel2170; | |
38789 | } | |
38790 | {{ int16_t src = m68k_read_memory_16(srca); | |
38791 | m68k_areg (regs, srcreg) = srca; | |
38792 | { int16_t dst = m68k_dreg(regs, dstreg); | |
38793 | m68k_incpc(2); | |
38794 | fill_prefetch_2 (); | |
38795 | if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2170; } | |
38796 | else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2170; } | |
38797 | }}}}}endlabel2170: ; | |
38798 | return 16; | |
38799 | } | |
38800 | unsigned long CPUFUNC(op_41a8_5)(uint32_t opcode) /* CHK */ | |
38801 | { | |
38802 | uint32_t srcreg = (opcode & 7); | |
38803 | uint32_t dstreg = (opcode >> 9) & 7; | |
38804 | OpcodeFamily = 80; CurrentInstrCycles = 18; | |
38805 | { uint32_t oldpc = m68k_getpc(); | |
38806 | { uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
38807 | if ((srca & 1) != 0) { | |
38808 | last_fault_for_exception_3 = srca; | |
38809 | last_op_for_exception_3 = opcode; | |
38810 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
38811 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
38812 | goto endlabel2171; | |
38813 | } | |
38814 | {{ int16_t src = m68k_read_memory_16(srca); | |
38815 | { int16_t dst = m68k_dreg(regs, dstreg); | |
38816 | m68k_incpc(4); | |
38817 | fill_prefetch_0 (); | |
38818 | if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2171; } | |
38819 | else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2171; } | |
38820 | }}}}}endlabel2171: ; | |
38821 | return 18; | |
38822 | } | |
38823 | unsigned long CPUFUNC(op_41b0_5)(uint32_t opcode) /* CHK */ | |
38824 | { | |
38825 | uint32_t srcreg = (opcode & 7); | |
38826 | uint32_t dstreg = (opcode >> 9) & 7; | |
38827 | OpcodeFamily = 80; CurrentInstrCycles = 20; | |
38828 | { uint32_t oldpc = m68k_getpc(); | |
38829 | { uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
38830 | BusCyclePenalty += 2; | |
38831 | if ((srca & 1) != 0) { | |
38832 | last_fault_for_exception_3 = srca; | |
38833 | last_op_for_exception_3 = opcode; | |
38834 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
38835 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
38836 | goto endlabel2172; | |
38837 | } | |
38838 | {{ int16_t src = m68k_read_memory_16(srca); | |
38839 | { int16_t dst = m68k_dreg(regs, dstreg); | |
38840 | m68k_incpc(4); | |
38841 | fill_prefetch_0 (); | |
38842 | if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2172; } | |
38843 | else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2172; } | |
38844 | }}}}}endlabel2172: ; | |
38845 | return 20; | |
38846 | } | |
38847 | unsigned long CPUFUNC(op_41b8_5)(uint32_t opcode) /* CHK */ | |
38848 | { | |
38849 | uint32_t dstreg = (opcode >> 9) & 7; | |
38850 | OpcodeFamily = 80; CurrentInstrCycles = 18; | |
38851 | { uint32_t oldpc = m68k_getpc(); | |
38852 | { uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
38853 | if ((srca & 1) != 0) { | |
38854 | last_fault_for_exception_3 = srca; | |
38855 | last_op_for_exception_3 = opcode; | |
38856 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
38857 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
38858 | goto endlabel2173; | |
38859 | } | |
38860 | {{ int16_t src = m68k_read_memory_16(srca); | |
38861 | { int16_t dst = m68k_dreg(regs, dstreg); | |
38862 | m68k_incpc(4); | |
38863 | fill_prefetch_0 (); | |
38864 | if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2173; } | |
38865 | else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2173; } | |
38866 | }}}}}endlabel2173: ; | |
38867 | return 18; | |
38868 | } | |
38869 | unsigned long CPUFUNC(op_41b9_5)(uint32_t opcode) /* CHK */ | |
38870 | { | |
38871 | uint32_t dstreg = (opcode >> 9) & 7; | |
38872 | OpcodeFamily = 80; CurrentInstrCycles = 22; | |
38873 | { uint32_t oldpc = m68k_getpc(); | |
38874 | { uint32_t srca = get_ilong_prefetch(2); | |
38875 | if ((srca & 1) != 0) { | |
38876 | last_fault_for_exception_3 = srca; | |
38877 | last_op_for_exception_3 = opcode; | |
38878 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
38879 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
38880 | goto endlabel2174; | |
38881 | } | |
38882 | {{ int16_t src = m68k_read_memory_16(srca); | |
38883 | { int16_t dst = m68k_dreg(regs, dstreg); | |
38884 | m68k_incpc(6); | |
38885 | fill_prefetch_0 (); | |
38886 | if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2174; } | |
38887 | else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2174; } | |
38888 | }}}}}endlabel2174: ; | |
38889 | return 22; | |
38890 | } | |
38891 | unsigned long CPUFUNC(op_41ba_5)(uint32_t opcode) /* CHK */ | |
38892 | { | |
38893 | uint32_t dstreg = (opcode >> 9) & 7; | |
38894 | OpcodeFamily = 80; CurrentInstrCycles = 18; | |
38895 | { uint32_t oldpc = m68k_getpc(); | |
38896 | { uint32_t srca = m68k_getpc () + 2; | |
38897 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
38898 | if ((srca & 1) != 0) { | |
38899 | last_fault_for_exception_3 = srca; | |
38900 | last_op_for_exception_3 = opcode; | |
38901 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
38902 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
38903 | goto endlabel2175; | |
38904 | } | |
38905 | {{ int16_t src = m68k_read_memory_16(srca); | |
38906 | { int16_t dst = m68k_dreg(regs, dstreg); | |
38907 | m68k_incpc(4); | |
38908 | fill_prefetch_0 (); | |
38909 | if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2175; } | |
38910 | else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2175; } | |
38911 | }}}}}endlabel2175: ; | |
38912 | return 18; | |
38913 | } | |
38914 | unsigned long CPUFUNC(op_41bb_5)(uint32_t opcode) /* CHK */ | |
38915 | { | |
38916 | uint32_t dstreg = (opcode >> 9) & 7; | |
38917 | OpcodeFamily = 80; CurrentInstrCycles = 20; | |
38918 | { uint32_t oldpc = m68k_getpc(); | |
38919 | { uint32_t tmppc = m68k_getpc() + 2; | |
38920 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
38921 | BusCyclePenalty += 2; | |
38922 | if ((srca & 1) != 0) { | |
38923 | last_fault_for_exception_3 = srca; | |
38924 | last_op_for_exception_3 = opcode; | |
38925 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
38926 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
38927 | goto endlabel2176; | |
38928 | } | |
38929 | {{ int16_t src = m68k_read_memory_16(srca); | |
38930 | { int16_t dst = m68k_dreg(regs, dstreg); | |
38931 | m68k_incpc(4); | |
38932 | fill_prefetch_0 (); | |
38933 | if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2176; } | |
38934 | else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2176; } | |
38935 | }}}}}endlabel2176: ; | |
38936 | return 20; | |
38937 | } | |
38938 | unsigned long CPUFUNC(op_41bc_5)(uint32_t opcode) /* CHK */ | |
38939 | { | |
38940 | uint32_t dstreg = (opcode >> 9) & 7; | |
38941 | OpcodeFamily = 80; CurrentInstrCycles = 14; | |
38942 | { uint32_t oldpc = m68k_getpc(); | |
38943 | { int16_t src = get_iword_prefetch(2); | |
38944 | { int16_t dst = m68k_dreg(regs, dstreg); | |
38945 | m68k_incpc(4); | |
38946 | fill_prefetch_0 (); | |
38947 | if ((int32_t)dst < 0) { SET_NFLG (1); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2177; } | |
38948 | else if (dst > src) { SET_NFLG (0); Exception(6,oldpc,M68000_EXC_SRC_CPU); goto endlabel2177; } | |
38949 | }}}endlabel2177: ; | |
38950 | return 14; | |
38951 | } | |
38952 | unsigned long CPUFUNC(op_41d0_5)(uint32_t opcode) /* LEA */ | |
38953 | { | |
38954 | uint32_t srcreg = (opcode & 7); | |
38955 | uint32_t dstreg = (opcode >> 9) & 7; | |
38956 | OpcodeFamily = 56; CurrentInstrCycles = 4; | |
38957 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
38958 | { m68k_areg(regs, dstreg) = (srca); | |
38959 | }}}m68k_incpc(2); | |
38960 | fill_prefetch_2 (); | |
38961 | return 4; | |
38962 | } | |
38963 | unsigned long CPUFUNC(op_41e8_5)(uint32_t opcode) /* LEA */ | |
38964 | { | |
38965 | uint32_t srcreg = (opcode & 7); | |
38966 | uint32_t dstreg = (opcode >> 9) & 7; | |
38967 | OpcodeFamily = 56; CurrentInstrCycles = 8; | |
38968 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
38969 | { m68k_areg(regs, dstreg) = (srca); | |
38970 | }}}m68k_incpc(4); | |
38971 | fill_prefetch_0 (); | |
38972 | return 8; | |
38973 | } | |
38974 | unsigned long CPUFUNC(op_41f0_5)(uint32_t opcode) /* LEA */ | |
38975 | { | |
38976 | uint32_t srcreg = (opcode & 7); | |
38977 | uint32_t dstreg = (opcode >> 9) & 7; | |
38978 | OpcodeFamily = 56; CurrentInstrCycles = 14; | |
38979 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
38980 | BusCyclePenalty += 2; | |
38981 | { m68k_areg(regs, dstreg) = (srca); | |
38982 | }}}m68k_incpc(4); | |
38983 | fill_prefetch_0 (); | |
38984 | return 14; | |
38985 | } | |
38986 | unsigned long CPUFUNC(op_41f8_5)(uint32_t opcode) /* LEA */ | |
38987 | { | |
38988 | uint32_t dstreg = (opcode >> 9) & 7; | |
38989 | OpcodeFamily = 56; CurrentInstrCycles = 8; | |
38990 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
38991 | { m68k_areg(regs, dstreg) = (srca); | |
38992 | }}}m68k_incpc(4); | |
38993 | fill_prefetch_0 (); | |
38994 | return 8; | |
38995 | } | |
38996 | unsigned long CPUFUNC(op_41f9_5)(uint32_t opcode) /* LEA */ | |
38997 | { | |
38998 | uint32_t dstreg = (opcode >> 9) & 7; | |
38999 | OpcodeFamily = 56; CurrentInstrCycles = 12; | |
39000 | {{ uint32_t srca = get_ilong_prefetch(2); | |
39001 | { m68k_areg(regs, dstreg) = (srca); | |
39002 | }}}m68k_incpc(6); | |
39003 | fill_prefetch_0 (); | |
39004 | return 12; | |
39005 | } | |
39006 | unsigned long CPUFUNC(op_41fa_5)(uint32_t opcode) /* LEA */ | |
39007 | { | |
39008 | uint32_t dstreg = (opcode >> 9) & 7; | |
39009 | OpcodeFamily = 56; CurrentInstrCycles = 8; | |
39010 | {{ uint32_t srca = m68k_getpc () + 2; | |
39011 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
39012 | { m68k_areg(regs, dstreg) = (srca); | |
39013 | }}}m68k_incpc(4); | |
39014 | fill_prefetch_0 (); | |
39015 | return 8; | |
39016 | } | |
39017 | unsigned long CPUFUNC(op_41fb_5)(uint32_t opcode) /* LEA */ | |
39018 | { | |
39019 | uint32_t dstreg = (opcode >> 9) & 7; | |
39020 | OpcodeFamily = 56; CurrentInstrCycles = 14; | |
39021 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
39022 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
39023 | BusCyclePenalty += 2; | |
39024 | { m68k_areg(regs, dstreg) = (srca); | |
39025 | }}}m68k_incpc(4); | |
39026 | fill_prefetch_0 (); | |
39027 | return 14; | |
39028 | } | |
39029 | unsigned long CPUFUNC(op_4200_5)(uint32_t opcode) /* CLR */ | |
39030 | { | |
39031 | uint32_t srcreg = (opcode & 7); | |
39032 | OpcodeFamily = 18; CurrentInstrCycles = 4; | |
39033 | {{ CLEAR_CZNV; | |
39034 | SET_ZFLG (((int8_t)(0)) == 0); | |
39035 | SET_NFLG (((int8_t)(0)) < 0); | |
39036 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((0) & 0xff); | |
39037 | }}m68k_incpc(2); | |
39038 | fill_prefetch_2 (); | |
39039 | return 4; | |
39040 | } | |
39041 | unsigned long CPUFUNC(op_4210_5)(uint32_t opcode) /* CLR */ | |
39042 | { | |
39043 | uint32_t srcreg = (opcode & 7); | |
39044 | OpcodeFamily = 18; CurrentInstrCycles = 12; | |
39045 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
39046 | int8_t src = m68k_read_memory_8(srca); | |
39047 | CLEAR_CZNV; | |
39048 | SET_ZFLG (((int8_t)(0)) == 0); | |
39049 | SET_NFLG (((int8_t)(0)) < 0); | |
39050 | m68k_incpc(2); | |
39051 | fill_prefetch_2 (); | |
39052 | m68k_write_memory_8(srca,0); | |
39053 | }}return 12; | |
39054 | } | |
39055 | unsigned long CPUFUNC(op_4218_5)(uint32_t opcode) /* CLR */ | |
39056 | { | |
39057 | uint32_t srcreg = (opcode & 7); | |
39058 | OpcodeFamily = 18; CurrentInstrCycles = 12; | |
39059 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
39060 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
39061 | int8_t src = m68k_read_memory_8(srca); | |
39062 | CLEAR_CZNV; | |
39063 | SET_ZFLG (((int8_t)(0)) == 0); | |
39064 | SET_NFLG (((int8_t)(0)) < 0); | |
39065 | m68k_incpc(2); | |
39066 | fill_prefetch_2 (); | |
39067 | m68k_write_memory_8(srca,0); | |
39068 | }}return 12; | |
39069 | } | |
39070 | unsigned long CPUFUNC(op_4220_5)(uint32_t opcode) /* CLR */ | |
39071 | { | |
39072 | uint32_t srcreg = (opcode & 7); | |
39073 | OpcodeFamily = 18; CurrentInstrCycles = 14; | |
39074 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
39075 | m68k_areg (regs, srcreg) = srca; | |
39076 | int8_t src = m68k_read_memory_8(srca); | |
39077 | CLEAR_CZNV; | |
39078 | SET_ZFLG (((int8_t)(0)) == 0); | |
39079 | SET_NFLG (((int8_t)(0)) < 0); | |
39080 | m68k_incpc(2); | |
39081 | fill_prefetch_2 (); | |
39082 | m68k_write_memory_8(srca,0); | |
39083 | }}return 14; | |
39084 | } | |
39085 | unsigned long CPUFUNC(op_4228_5)(uint32_t opcode) /* CLR */ | |
39086 | { | |
39087 | uint32_t srcreg = (opcode & 7); | |
39088 | OpcodeFamily = 18; CurrentInstrCycles = 16; | |
39089 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
39090 | int8_t src = m68k_read_memory_8(srca); | |
39091 | CLEAR_CZNV; | |
39092 | SET_ZFLG (((int8_t)(0)) == 0); | |
39093 | SET_NFLG (((int8_t)(0)) < 0); | |
39094 | m68k_incpc(4); | |
39095 | fill_prefetch_0 (); | |
39096 | m68k_write_memory_8(srca,0); | |
39097 | }}return 16; | |
39098 | } | |
39099 | unsigned long CPUFUNC(op_4230_5)(uint32_t opcode) /* CLR */ | |
39100 | { | |
39101 | uint32_t srcreg = (opcode & 7); | |
39102 | OpcodeFamily = 18; CurrentInstrCycles = 18; | |
39103 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
39104 | BusCyclePenalty += 2; | |
39105 | int8_t src = m68k_read_memory_8(srca); | |
39106 | CLEAR_CZNV; | |
39107 | SET_ZFLG (((int8_t)(0)) == 0); | |
39108 | SET_NFLG (((int8_t)(0)) < 0); | |
39109 | m68k_incpc(4); | |
39110 | fill_prefetch_0 (); | |
39111 | m68k_write_memory_8(srca,0); | |
39112 | }}return 18; | |
39113 | } | |
39114 | unsigned long CPUFUNC(op_4238_5)(uint32_t opcode) /* CLR */ | |
39115 | { | |
39116 | OpcodeFamily = 18; CurrentInstrCycles = 16; | |
39117 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
39118 | int8_t src = m68k_read_memory_8(srca); | |
39119 | CLEAR_CZNV; | |
39120 | SET_ZFLG (((int8_t)(0)) == 0); | |
39121 | SET_NFLG (((int8_t)(0)) < 0); | |
39122 | m68k_incpc(4); | |
39123 | fill_prefetch_0 (); | |
39124 | m68k_write_memory_8(srca,0); | |
39125 | }}return 16; | |
39126 | } | |
39127 | unsigned long CPUFUNC(op_4239_5)(uint32_t opcode) /* CLR */ | |
39128 | { | |
39129 | OpcodeFamily = 18; CurrentInstrCycles = 20; | |
39130 | {{ uint32_t srca = get_ilong_prefetch(2); | |
39131 | int8_t src = m68k_read_memory_8(srca); | |
39132 | CLEAR_CZNV; | |
39133 | SET_ZFLG (((int8_t)(0)) == 0); | |
39134 | SET_NFLG (((int8_t)(0)) < 0); | |
39135 | m68k_incpc(6); | |
39136 | fill_prefetch_0 (); | |
39137 | m68k_write_memory_8(srca,0); | |
39138 | }}return 20; | |
39139 | } | |
39140 | unsigned long CPUFUNC(op_4240_5)(uint32_t opcode) /* CLR */ | |
39141 | { | |
39142 | uint32_t srcreg = (opcode & 7); | |
39143 | OpcodeFamily = 18; CurrentInstrCycles = 4; | |
39144 | {{ CLEAR_CZNV; | |
39145 | SET_ZFLG (((int16_t)(0)) == 0); | |
39146 | SET_NFLG (((int16_t)(0)) < 0); | |
39147 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((0) & 0xffff); | |
39148 | }}m68k_incpc(2); | |
39149 | fill_prefetch_2 (); | |
39150 | return 4; | |
39151 | } | |
39152 | unsigned long CPUFUNC(op_4250_5)(uint32_t opcode) /* CLR */ | |
39153 | { | |
39154 | uint32_t srcreg = (opcode & 7); | |
39155 | OpcodeFamily = 18; CurrentInstrCycles = 12; | |
39156 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
39157 | if ((srca & 1) != 0) { | |
39158 | last_fault_for_exception_3 = srca; | |
39159 | last_op_for_exception_3 = opcode; | |
39160 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
39161 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
39162 | goto endlabel2194; | |
39163 | } | |
39164 | { int16_t src = m68k_read_memory_16(srca); | |
39165 | CLEAR_CZNV; | |
39166 | SET_ZFLG (((int16_t)(0)) == 0); | |
39167 | SET_NFLG (((int16_t)(0)) < 0); | |
39168 | m68k_incpc(2); | |
39169 | fill_prefetch_2 (); | |
39170 | m68k_write_memory_16(srca,0); | |
39171 | }}}endlabel2194: ; | |
39172 | return 12; | |
39173 | } | |
39174 | unsigned long CPUFUNC(op_4258_5)(uint32_t opcode) /* CLR */ | |
39175 | { | |
39176 | uint32_t srcreg = (opcode & 7); | |
39177 | OpcodeFamily = 18; CurrentInstrCycles = 12; | |
39178 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
39179 | if ((srca & 1) != 0) { | |
39180 | last_fault_for_exception_3 = srca; | |
39181 | last_op_for_exception_3 = opcode; | |
39182 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
39183 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
39184 | goto endlabel2195; | |
39185 | } | |
39186 | { m68k_areg(regs, srcreg) += 2; | |
39187 | int16_t src = m68k_read_memory_16(srca); | |
39188 | CLEAR_CZNV; | |
39189 | SET_ZFLG (((int16_t)(0)) == 0); | |
39190 | SET_NFLG (((int16_t)(0)) < 0); | |
39191 | m68k_incpc(2); | |
39192 | fill_prefetch_2 (); | |
39193 | m68k_write_memory_16(srca,0); | |
39194 | }}}endlabel2195: ; | |
39195 | return 12; | |
39196 | } | |
39197 | unsigned long CPUFUNC(op_4260_5)(uint32_t opcode) /* CLR */ | |
39198 | { | |
39199 | uint32_t srcreg = (opcode & 7); | |
39200 | OpcodeFamily = 18; CurrentInstrCycles = 14; | |
39201 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
39202 | if ((srca & 1) != 0) { | |
39203 | last_fault_for_exception_3 = srca; | |
39204 | last_op_for_exception_3 = opcode; | |
39205 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
39206 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
39207 | goto endlabel2196; | |
39208 | } | |
39209 | { m68k_areg (regs, srcreg) = srca; | |
39210 | int16_t src = m68k_read_memory_16(srca); | |
39211 | CLEAR_CZNV; | |
39212 | SET_ZFLG (((int16_t)(0)) == 0); | |
39213 | SET_NFLG (((int16_t)(0)) < 0); | |
39214 | m68k_incpc(2); | |
39215 | fill_prefetch_2 (); | |
39216 | m68k_write_memory_16(srca,0); | |
39217 | }}}endlabel2196: ; | |
39218 | return 14; | |
39219 | } | |
39220 | unsigned long CPUFUNC(op_4268_5)(uint32_t opcode) /* CLR */ | |
39221 | { | |
39222 | uint32_t srcreg = (opcode & 7); | |
39223 | OpcodeFamily = 18; CurrentInstrCycles = 16; | |
39224 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
39225 | if ((srca & 1) != 0) { | |
39226 | last_fault_for_exception_3 = srca; | |
39227 | last_op_for_exception_3 = opcode; | |
39228 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
39229 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
39230 | goto endlabel2197; | |
39231 | } | |
39232 | { int16_t src = m68k_read_memory_16(srca); | |
39233 | CLEAR_CZNV; | |
39234 | SET_ZFLG (((int16_t)(0)) == 0); | |
39235 | SET_NFLG (((int16_t)(0)) < 0); | |
39236 | m68k_incpc(4); | |
39237 | fill_prefetch_0 (); | |
39238 | m68k_write_memory_16(srca,0); | |
39239 | }}}endlabel2197: ; | |
39240 | return 16; | |
39241 | } | |
39242 | #endif | |
39243 | ||
39244 | #ifdef PART_4 | |
39245 | unsigned long CPUFUNC(op_4270_5)(uint32_t opcode) /* CLR */ | |
39246 | { | |
39247 | uint32_t srcreg = (opcode & 7); | |
39248 | OpcodeFamily = 18; CurrentInstrCycles = 18; | |
39249 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
39250 | BusCyclePenalty += 2; | |
39251 | if ((srca & 1) != 0) { | |
39252 | last_fault_for_exception_3 = srca; | |
39253 | last_op_for_exception_3 = opcode; | |
39254 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
39255 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
39256 | goto endlabel2198; | |
39257 | } | |
39258 | { int16_t src = m68k_read_memory_16(srca); | |
39259 | CLEAR_CZNV; | |
39260 | SET_ZFLG (((int16_t)(0)) == 0); | |
39261 | SET_NFLG (((int16_t)(0)) < 0); | |
39262 | m68k_incpc(4); | |
39263 | fill_prefetch_0 (); | |
39264 | m68k_write_memory_16(srca,0); | |
39265 | }}}endlabel2198: ; | |
39266 | return 18; | |
39267 | } | |
39268 | unsigned long CPUFUNC(op_4278_5)(uint32_t opcode) /* CLR */ | |
39269 | { | |
39270 | OpcodeFamily = 18; CurrentInstrCycles = 16; | |
39271 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
39272 | if ((srca & 1) != 0) { | |
39273 | last_fault_for_exception_3 = srca; | |
39274 | last_op_for_exception_3 = opcode; | |
39275 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
39276 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
39277 | goto endlabel2199; | |
39278 | } | |
39279 | { int16_t src = m68k_read_memory_16(srca); | |
39280 | CLEAR_CZNV; | |
39281 | SET_ZFLG (((int16_t)(0)) == 0); | |
39282 | SET_NFLG (((int16_t)(0)) < 0); | |
39283 | m68k_incpc(4); | |
39284 | fill_prefetch_0 (); | |
39285 | m68k_write_memory_16(srca,0); | |
39286 | }}}endlabel2199: ; | |
39287 | return 16; | |
39288 | } | |
39289 | unsigned long CPUFUNC(op_4279_5)(uint32_t opcode) /* CLR */ | |
39290 | { | |
39291 | OpcodeFamily = 18; CurrentInstrCycles = 20; | |
39292 | {{ uint32_t srca = get_ilong_prefetch(2); | |
39293 | if ((srca & 1) != 0) { | |
39294 | last_fault_for_exception_3 = srca; | |
39295 | last_op_for_exception_3 = opcode; | |
39296 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
39297 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
39298 | goto endlabel2200; | |
39299 | } | |
39300 | { int16_t src = m68k_read_memory_16(srca); | |
39301 | CLEAR_CZNV; | |
39302 | SET_ZFLG (((int16_t)(0)) == 0); | |
39303 | SET_NFLG (((int16_t)(0)) < 0); | |
39304 | m68k_incpc(6); | |
39305 | fill_prefetch_0 (); | |
39306 | m68k_write_memory_16(srca,0); | |
39307 | }}}endlabel2200: ; | |
39308 | return 20; | |
39309 | } | |
39310 | unsigned long CPUFUNC(op_4280_5)(uint32_t opcode) /* CLR */ | |
39311 | { | |
39312 | uint32_t srcreg = (opcode & 7); | |
39313 | OpcodeFamily = 18; CurrentInstrCycles = 6; | |
39314 | {{ CLEAR_CZNV; | |
39315 | SET_ZFLG (((int32_t)(0)) == 0); | |
39316 | SET_NFLG (((int32_t)(0)) < 0); | |
39317 | m68k_dreg(regs, srcreg) = (0); | |
39318 | }}m68k_incpc(2); | |
39319 | fill_prefetch_2 (); | |
39320 | return 6; | |
39321 | } | |
39322 | unsigned long CPUFUNC(op_4290_5)(uint32_t opcode) /* CLR */ | |
39323 | { | |
39324 | uint32_t srcreg = (opcode & 7); | |
39325 | OpcodeFamily = 18; CurrentInstrCycles = 20; | |
39326 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
39327 | if ((srca & 1) != 0) { | |
39328 | last_fault_for_exception_3 = srca; | |
39329 | last_op_for_exception_3 = opcode; | |
39330 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
39331 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
39332 | goto endlabel2202; | |
39333 | } | |
39334 | { int32_t src = m68k_read_memory_32(srca); | |
39335 | CLEAR_CZNV; | |
39336 | SET_ZFLG (((int32_t)(0)) == 0); | |
39337 | SET_NFLG (((int32_t)(0)) < 0); | |
39338 | m68k_incpc(2); | |
39339 | fill_prefetch_2 (); | |
39340 | m68k_write_memory_32(srca,0); | |
39341 | }}}endlabel2202: ; | |
39342 | return 20; | |
39343 | } | |
39344 | unsigned long CPUFUNC(op_4298_5)(uint32_t opcode) /* CLR */ | |
39345 | { | |
39346 | uint32_t srcreg = (opcode & 7); | |
39347 | OpcodeFamily = 18; CurrentInstrCycles = 20; | |
39348 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
39349 | if ((srca & 1) != 0) { | |
39350 | last_fault_for_exception_3 = srca; | |
39351 | last_op_for_exception_3 = opcode; | |
39352 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
39353 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
39354 | goto endlabel2203; | |
39355 | } | |
39356 | { m68k_areg(regs, srcreg) += 4; | |
39357 | int32_t src = m68k_read_memory_32(srca); | |
39358 | CLEAR_CZNV; | |
39359 | SET_ZFLG (((int32_t)(0)) == 0); | |
39360 | SET_NFLG (((int32_t)(0)) < 0); | |
39361 | m68k_incpc(2); | |
39362 | fill_prefetch_2 (); | |
39363 | m68k_write_memory_32(srca,0); | |
39364 | }}}endlabel2203: ; | |
39365 | return 20; | |
39366 | } | |
39367 | unsigned long CPUFUNC(op_42a0_5)(uint32_t opcode) /* CLR */ | |
39368 | { | |
39369 | uint32_t srcreg = (opcode & 7); | |
39370 | OpcodeFamily = 18; CurrentInstrCycles = 22; | |
39371 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 4; | |
39372 | if ((srca & 1) != 0) { | |
39373 | last_fault_for_exception_3 = srca; | |
39374 | last_op_for_exception_3 = opcode; | |
39375 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
39376 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
39377 | goto endlabel2204; | |
39378 | } | |
39379 | { m68k_areg (regs, srcreg) = srca; | |
39380 | int32_t src = m68k_read_memory_32(srca); | |
39381 | CLEAR_CZNV; | |
39382 | SET_ZFLG (((int32_t)(0)) == 0); | |
39383 | SET_NFLG (((int32_t)(0)) < 0); | |
39384 | m68k_incpc(2); | |
39385 | fill_prefetch_2 (); | |
39386 | m68k_write_memory_32(srca,0); | |
39387 | }}}endlabel2204: ; | |
39388 | return 22; | |
39389 | } | |
39390 | unsigned long CPUFUNC(op_42a8_5)(uint32_t opcode) /* CLR */ | |
39391 | { | |
39392 | uint32_t srcreg = (opcode & 7); | |
39393 | OpcodeFamily = 18; CurrentInstrCycles = 24; | |
39394 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
39395 | if ((srca & 1) != 0) { | |
39396 | last_fault_for_exception_3 = srca; | |
39397 | last_op_for_exception_3 = opcode; | |
39398 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
39399 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
39400 | goto endlabel2205; | |
39401 | } | |
39402 | { int32_t src = m68k_read_memory_32(srca); | |
39403 | CLEAR_CZNV; | |
39404 | SET_ZFLG (((int32_t)(0)) == 0); | |
39405 | SET_NFLG (((int32_t)(0)) < 0); | |
39406 | m68k_incpc(4); | |
39407 | fill_prefetch_0 (); | |
39408 | m68k_write_memory_32(srca,0); | |
39409 | }}}endlabel2205: ; | |
39410 | return 24; | |
39411 | } | |
39412 | unsigned long CPUFUNC(op_42b0_5)(uint32_t opcode) /* CLR */ | |
39413 | { | |
39414 | uint32_t srcreg = (opcode & 7); | |
39415 | OpcodeFamily = 18; CurrentInstrCycles = 26; | |
39416 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
39417 | BusCyclePenalty += 2; | |
39418 | if ((srca & 1) != 0) { | |
39419 | last_fault_for_exception_3 = srca; | |
39420 | last_op_for_exception_3 = opcode; | |
39421 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
39422 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
39423 | goto endlabel2206; | |
39424 | } | |
39425 | { int32_t src = m68k_read_memory_32(srca); | |
39426 | CLEAR_CZNV; | |
39427 | SET_ZFLG (((int32_t)(0)) == 0); | |
39428 | SET_NFLG (((int32_t)(0)) < 0); | |
39429 | m68k_incpc(4); | |
39430 | fill_prefetch_0 (); | |
39431 | m68k_write_memory_32(srca,0); | |
39432 | }}}endlabel2206: ; | |
39433 | return 26; | |
39434 | } | |
39435 | unsigned long CPUFUNC(op_42b8_5)(uint32_t opcode) /* CLR */ | |
39436 | { | |
39437 | OpcodeFamily = 18; CurrentInstrCycles = 24; | |
39438 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
39439 | if ((srca & 1) != 0) { | |
39440 | last_fault_for_exception_3 = srca; | |
39441 | last_op_for_exception_3 = opcode; | |
39442 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
39443 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
39444 | goto endlabel2207; | |
39445 | } | |
39446 | { int32_t src = m68k_read_memory_32(srca); | |
39447 | CLEAR_CZNV; | |
39448 | SET_ZFLG (((int32_t)(0)) == 0); | |
39449 | SET_NFLG (((int32_t)(0)) < 0); | |
39450 | m68k_incpc(4); | |
39451 | fill_prefetch_0 (); | |
39452 | m68k_write_memory_32(srca,0); | |
39453 | }}}endlabel2207: ; | |
39454 | return 24; | |
39455 | } | |
39456 | unsigned long CPUFUNC(op_42b9_5)(uint32_t opcode) /* CLR */ | |
39457 | { | |
39458 | OpcodeFamily = 18; CurrentInstrCycles = 28; | |
39459 | {{ uint32_t srca = get_ilong_prefetch(2); | |
39460 | if ((srca & 1) != 0) { | |
39461 | last_fault_for_exception_3 = srca; | |
39462 | last_op_for_exception_3 = opcode; | |
39463 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
39464 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
39465 | goto endlabel2208; | |
39466 | } | |
39467 | { int32_t src = m68k_read_memory_32(srca); | |
39468 | CLEAR_CZNV; | |
39469 | SET_ZFLG (((int32_t)(0)) == 0); | |
39470 | SET_NFLG (((int32_t)(0)) < 0); | |
39471 | m68k_incpc(6); | |
39472 | fill_prefetch_0 (); | |
39473 | m68k_write_memory_32(srca,0); | |
39474 | }}}endlabel2208: ; | |
39475 | return 28; | |
39476 | } | |
39477 | unsigned long CPUFUNC(op_4400_5)(uint32_t opcode) /* NEG */ | |
39478 | { | |
39479 | uint32_t srcreg = (opcode & 7); | |
39480 | OpcodeFamily = 15; CurrentInstrCycles = 4; | |
39481 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
39482 | {{uint32_t dst = ((int8_t)(0)) - ((int8_t)(src)); | |
39483 | { int flgs = ((int8_t)(src)) < 0; | |
39484 | int flgo = ((int8_t)(0)) < 0; | |
39485 | int flgn = ((int8_t)(dst)) < 0; | |
39486 | SET_ZFLG (((int8_t)(dst)) == 0); | |
39487 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
39488 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(0))); | |
39489 | COPY_CARRY; | |
39490 | SET_NFLG (flgn != 0); | |
39491 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((dst) & 0xff); | |
39492 | }}}}}m68k_incpc(2); | |
39493 | fill_prefetch_2 (); | |
39494 | return 4; | |
39495 | } | |
39496 | unsigned long CPUFUNC(op_4410_5)(uint32_t opcode) /* NEG */ | |
39497 | { | |
39498 | uint32_t srcreg = (opcode & 7); | |
39499 | OpcodeFamily = 15; CurrentInstrCycles = 12; | |
39500 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
39501 | { int8_t src = m68k_read_memory_8(srca); | |
39502 | {{uint32_t dst = ((int8_t)(0)) - ((int8_t)(src)); | |
39503 | { int flgs = ((int8_t)(src)) < 0; | |
39504 | int flgo = ((int8_t)(0)) < 0; | |
39505 | int flgn = ((int8_t)(dst)) < 0; | |
39506 | SET_ZFLG (((int8_t)(dst)) == 0); | |
39507 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
39508 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(0))); | |
39509 | COPY_CARRY; | |
39510 | SET_NFLG (flgn != 0); | |
39511 | m68k_incpc(2); | |
39512 | fill_prefetch_2 (); | |
39513 | m68k_write_memory_8(srca,dst); | |
39514 | }}}}}}return 12; | |
39515 | } | |
39516 | unsigned long CPUFUNC(op_4418_5)(uint32_t opcode) /* NEG */ | |
39517 | { | |
39518 | uint32_t srcreg = (opcode & 7); | |
39519 | OpcodeFamily = 15; CurrentInstrCycles = 12; | |
39520 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
39521 | { int8_t src = m68k_read_memory_8(srca); | |
39522 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
39523 | {{uint32_t dst = ((int8_t)(0)) - ((int8_t)(src)); | |
39524 | { int flgs = ((int8_t)(src)) < 0; | |
39525 | int flgo = ((int8_t)(0)) < 0; | |
39526 | int flgn = ((int8_t)(dst)) < 0; | |
39527 | SET_ZFLG (((int8_t)(dst)) == 0); | |
39528 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
39529 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(0))); | |
39530 | COPY_CARRY; | |
39531 | SET_NFLG (flgn != 0); | |
39532 | m68k_incpc(2); | |
39533 | fill_prefetch_2 (); | |
39534 | m68k_write_memory_8(srca,dst); | |
39535 | }}}}}}return 12; | |
39536 | } | |
39537 | unsigned long CPUFUNC(op_4420_5)(uint32_t opcode) /* NEG */ | |
39538 | { | |
39539 | uint32_t srcreg = (opcode & 7); | |
39540 | OpcodeFamily = 15; CurrentInstrCycles = 14; | |
39541 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
39542 | { int8_t src = m68k_read_memory_8(srca); | |
39543 | m68k_areg (regs, srcreg) = srca; | |
39544 | {{uint32_t dst = ((int8_t)(0)) - ((int8_t)(src)); | |
39545 | { int flgs = ((int8_t)(src)) < 0; | |
39546 | int flgo = ((int8_t)(0)) < 0; | |
39547 | int flgn = ((int8_t)(dst)) < 0; | |
39548 | SET_ZFLG (((int8_t)(dst)) == 0); | |
39549 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
39550 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(0))); | |
39551 | COPY_CARRY; | |
39552 | SET_NFLG (flgn != 0); | |
39553 | m68k_incpc(2); | |
39554 | fill_prefetch_2 (); | |
39555 | m68k_write_memory_8(srca,dst); | |
39556 | }}}}}}return 14; | |
39557 | } | |
39558 | unsigned long CPUFUNC(op_4428_5)(uint32_t opcode) /* NEG */ | |
39559 | { | |
39560 | uint32_t srcreg = (opcode & 7); | |
39561 | OpcodeFamily = 15; CurrentInstrCycles = 16; | |
39562 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
39563 | { int8_t src = m68k_read_memory_8(srca); | |
39564 | {{uint32_t dst = ((int8_t)(0)) - ((int8_t)(src)); | |
39565 | { int flgs = ((int8_t)(src)) < 0; | |
39566 | int flgo = ((int8_t)(0)) < 0; | |
39567 | int flgn = ((int8_t)(dst)) < 0; | |
39568 | SET_ZFLG (((int8_t)(dst)) == 0); | |
39569 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
39570 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(0))); | |
39571 | COPY_CARRY; | |
39572 | SET_NFLG (flgn != 0); | |
39573 | m68k_incpc(4); | |
39574 | fill_prefetch_0 (); | |
39575 | m68k_write_memory_8(srca,dst); | |
39576 | }}}}}}return 16; | |
39577 | } | |
39578 | unsigned long CPUFUNC(op_4430_5)(uint32_t opcode) /* NEG */ | |
39579 | { | |
39580 | uint32_t srcreg = (opcode & 7); | |
39581 | OpcodeFamily = 15; CurrentInstrCycles = 18; | |
39582 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
39583 | BusCyclePenalty += 2; | |
39584 | { int8_t src = m68k_read_memory_8(srca); | |
39585 | {{uint32_t dst = ((int8_t)(0)) - ((int8_t)(src)); | |
39586 | { int flgs = ((int8_t)(src)) < 0; | |
39587 | int flgo = ((int8_t)(0)) < 0; | |
39588 | int flgn = ((int8_t)(dst)) < 0; | |
39589 | SET_ZFLG (((int8_t)(dst)) == 0); | |
39590 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
39591 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(0))); | |
39592 | COPY_CARRY; | |
39593 | SET_NFLG (flgn != 0); | |
39594 | m68k_incpc(4); | |
39595 | fill_prefetch_0 (); | |
39596 | m68k_write_memory_8(srca,dst); | |
39597 | }}}}}}return 18; | |
39598 | } | |
39599 | unsigned long CPUFUNC(op_4438_5)(uint32_t opcode) /* NEG */ | |
39600 | { | |
39601 | OpcodeFamily = 15; CurrentInstrCycles = 16; | |
39602 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
39603 | { int8_t src = m68k_read_memory_8(srca); | |
39604 | {{uint32_t dst = ((int8_t)(0)) - ((int8_t)(src)); | |
39605 | { int flgs = ((int8_t)(src)) < 0; | |
39606 | int flgo = ((int8_t)(0)) < 0; | |
39607 | int flgn = ((int8_t)(dst)) < 0; | |
39608 | SET_ZFLG (((int8_t)(dst)) == 0); | |
39609 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
39610 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(0))); | |
39611 | COPY_CARRY; | |
39612 | SET_NFLG (flgn != 0); | |
39613 | m68k_incpc(4); | |
39614 | fill_prefetch_0 (); | |
39615 | m68k_write_memory_8(srca,dst); | |
39616 | }}}}}}return 16; | |
39617 | } | |
39618 | unsigned long CPUFUNC(op_4439_5)(uint32_t opcode) /* NEG */ | |
39619 | { | |
39620 | OpcodeFamily = 15; CurrentInstrCycles = 20; | |
39621 | {{ uint32_t srca = get_ilong_prefetch(2); | |
39622 | { int8_t src = m68k_read_memory_8(srca); | |
39623 | {{uint32_t dst = ((int8_t)(0)) - ((int8_t)(src)); | |
39624 | { int flgs = ((int8_t)(src)) < 0; | |
39625 | int flgo = ((int8_t)(0)) < 0; | |
39626 | int flgn = ((int8_t)(dst)) < 0; | |
39627 | SET_ZFLG (((int8_t)(dst)) == 0); | |
39628 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
39629 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(0))); | |
39630 | COPY_CARRY; | |
39631 | SET_NFLG (flgn != 0); | |
39632 | m68k_incpc(6); | |
39633 | fill_prefetch_0 (); | |
39634 | m68k_write_memory_8(srca,dst); | |
39635 | }}}}}}return 20; | |
39636 | } | |
39637 | unsigned long CPUFUNC(op_4440_5)(uint32_t opcode) /* NEG */ | |
39638 | { | |
39639 | uint32_t srcreg = (opcode & 7); | |
39640 | OpcodeFamily = 15; CurrentInstrCycles = 4; | |
39641 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
39642 | {{uint32_t dst = ((int16_t)(0)) - ((int16_t)(src)); | |
39643 | { int flgs = ((int16_t)(src)) < 0; | |
39644 | int flgo = ((int16_t)(0)) < 0; | |
39645 | int flgn = ((int16_t)(dst)) < 0; | |
39646 | SET_ZFLG (((int16_t)(dst)) == 0); | |
39647 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
39648 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(0))); | |
39649 | COPY_CARRY; | |
39650 | SET_NFLG (flgn != 0); | |
39651 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((dst) & 0xffff); | |
39652 | }}}}}m68k_incpc(2); | |
39653 | fill_prefetch_2 (); | |
39654 | return 4; | |
39655 | } | |
39656 | unsigned long CPUFUNC(op_4450_5)(uint32_t opcode) /* NEG */ | |
39657 | { | |
39658 | uint32_t srcreg = (opcode & 7); | |
39659 | OpcodeFamily = 15; CurrentInstrCycles = 12; | |
39660 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
39661 | if ((srca & 1) != 0) { | |
39662 | last_fault_for_exception_3 = srca; | |
39663 | last_op_for_exception_3 = opcode; | |
39664 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
39665 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
39666 | goto endlabel2218; | |
39667 | } | |
39668 | {{ int16_t src = m68k_read_memory_16(srca); | |
39669 | {{uint32_t dst = ((int16_t)(0)) - ((int16_t)(src)); | |
39670 | { int flgs = ((int16_t)(src)) < 0; | |
39671 | int flgo = ((int16_t)(0)) < 0; | |
39672 | int flgn = ((int16_t)(dst)) < 0; | |
39673 | SET_ZFLG (((int16_t)(dst)) == 0); | |
39674 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
39675 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(0))); | |
39676 | COPY_CARRY; | |
39677 | SET_NFLG (flgn != 0); | |
39678 | m68k_incpc(2); | |
39679 | fill_prefetch_2 (); | |
39680 | m68k_write_memory_16(srca,dst); | |
39681 | }}}}}}}endlabel2218: ; | |
39682 | return 12; | |
39683 | } | |
39684 | unsigned long CPUFUNC(op_4458_5)(uint32_t opcode) /* NEG */ | |
39685 | { | |
39686 | uint32_t srcreg = (opcode & 7); | |
39687 | OpcodeFamily = 15; CurrentInstrCycles = 12; | |
39688 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
39689 | if ((srca & 1) != 0) { | |
39690 | last_fault_for_exception_3 = srca; | |
39691 | last_op_for_exception_3 = opcode; | |
39692 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
39693 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
39694 | goto endlabel2219; | |
39695 | } | |
39696 | {{ int16_t src = m68k_read_memory_16(srca); | |
39697 | m68k_areg(regs, srcreg) += 2; | |
39698 | {{uint32_t dst = ((int16_t)(0)) - ((int16_t)(src)); | |
39699 | { int flgs = ((int16_t)(src)) < 0; | |
39700 | int flgo = ((int16_t)(0)) < 0; | |
39701 | int flgn = ((int16_t)(dst)) < 0; | |
39702 | SET_ZFLG (((int16_t)(dst)) == 0); | |
39703 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
39704 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(0))); | |
39705 | COPY_CARRY; | |
39706 | SET_NFLG (flgn != 0); | |
39707 | m68k_incpc(2); | |
39708 | fill_prefetch_2 (); | |
39709 | m68k_write_memory_16(srca,dst); | |
39710 | }}}}}}}endlabel2219: ; | |
39711 | return 12; | |
39712 | } | |
39713 | unsigned long CPUFUNC(op_4460_5)(uint32_t opcode) /* NEG */ | |
39714 | { | |
39715 | uint32_t srcreg = (opcode & 7); | |
39716 | OpcodeFamily = 15; CurrentInstrCycles = 14; | |
39717 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
39718 | if ((srca & 1) != 0) { | |
39719 | last_fault_for_exception_3 = srca; | |
39720 | last_op_for_exception_3 = opcode; | |
39721 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
39722 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
39723 | goto endlabel2220; | |
39724 | } | |
39725 | {{ int16_t src = m68k_read_memory_16(srca); | |
39726 | m68k_areg (regs, srcreg) = srca; | |
39727 | {{uint32_t dst = ((int16_t)(0)) - ((int16_t)(src)); | |
39728 | { int flgs = ((int16_t)(src)) < 0; | |
39729 | int flgo = ((int16_t)(0)) < 0; | |
39730 | int flgn = ((int16_t)(dst)) < 0; | |
39731 | SET_ZFLG (((int16_t)(dst)) == 0); | |
39732 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
39733 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(0))); | |
39734 | COPY_CARRY; | |
39735 | SET_NFLG (flgn != 0); | |
39736 | m68k_incpc(2); | |
39737 | fill_prefetch_2 (); | |
39738 | m68k_write_memory_16(srca,dst); | |
39739 | }}}}}}}endlabel2220: ; | |
39740 | return 14; | |
39741 | } | |
39742 | unsigned long CPUFUNC(op_4468_5)(uint32_t opcode) /* NEG */ | |
39743 | { | |
39744 | uint32_t srcreg = (opcode & 7); | |
39745 | OpcodeFamily = 15; CurrentInstrCycles = 16; | |
39746 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
39747 | if ((srca & 1) != 0) { | |
39748 | last_fault_for_exception_3 = srca; | |
39749 | last_op_for_exception_3 = opcode; | |
39750 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
39751 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
39752 | goto endlabel2221; | |
39753 | } | |
39754 | {{ int16_t src = m68k_read_memory_16(srca); | |
39755 | {{uint32_t dst = ((int16_t)(0)) - ((int16_t)(src)); | |
39756 | { int flgs = ((int16_t)(src)) < 0; | |
39757 | int flgo = ((int16_t)(0)) < 0; | |
39758 | int flgn = ((int16_t)(dst)) < 0; | |
39759 | SET_ZFLG (((int16_t)(dst)) == 0); | |
39760 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
39761 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(0))); | |
39762 | COPY_CARRY; | |
39763 | SET_NFLG (flgn != 0); | |
39764 | m68k_incpc(4); | |
39765 | fill_prefetch_0 (); | |
39766 | m68k_write_memory_16(srca,dst); | |
39767 | }}}}}}}endlabel2221: ; | |
39768 | return 16; | |
39769 | } | |
39770 | unsigned long CPUFUNC(op_4470_5)(uint32_t opcode) /* NEG */ | |
39771 | { | |
39772 | uint32_t srcreg = (opcode & 7); | |
39773 | OpcodeFamily = 15; CurrentInstrCycles = 18; | |
39774 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
39775 | BusCyclePenalty += 2; | |
39776 | if ((srca & 1) != 0) { | |
39777 | last_fault_for_exception_3 = srca; | |
39778 | last_op_for_exception_3 = opcode; | |
39779 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
39780 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
39781 | goto endlabel2222; | |
39782 | } | |
39783 | {{ int16_t src = m68k_read_memory_16(srca); | |
39784 | {{uint32_t dst = ((int16_t)(0)) - ((int16_t)(src)); | |
39785 | { int flgs = ((int16_t)(src)) < 0; | |
39786 | int flgo = ((int16_t)(0)) < 0; | |
39787 | int flgn = ((int16_t)(dst)) < 0; | |
39788 | SET_ZFLG (((int16_t)(dst)) == 0); | |
39789 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
39790 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(0))); | |
39791 | COPY_CARRY; | |
39792 | SET_NFLG (flgn != 0); | |
39793 | m68k_incpc(4); | |
39794 | fill_prefetch_0 (); | |
39795 | m68k_write_memory_16(srca,dst); | |
39796 | }}}}}}}endlabel2222: ; | |
39797 | return 18; | |
39798 | } | |
39799 | unsigned long CPUFUNC(op_4478_5)(uint32_t opcode) /* NEG */ | |
39800 | { | |
39801 | OpcodeFamily = 15; CurrentInstrCycles = 16; | |
39802 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
39803 | if ((srca & 1) != 0) { | |
39804 | last_fault_for_exception_3 = srca; | |
39805 | last_op_for_exception_3 = opcode; | |
39806 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
39807 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
39808 | goto endlabel2223; | |
39809 | } | |
39810 | {{ int16_t src = m68k_read_memory_16(srca); | |
39811 | {{uint32_t dst = ((int16_t)(0)) - ((int16_t)(src)); | |
39812 | { int flgs = ((int16_t)(src)) < 0; | |
39813 | int flgo = ((int16_t)(0)) < 0; | |
39814 | int flgn = ((int16_t)(dst)) < 0; | |
39815 | SET_ZFLG (((int16_t)(dst)) == 0); | |
39816 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
39817 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(0))); | |
39818 | COPY_CARRY; | |
39819 | SET_NFLG (flgn != 0); | |
39820 | m68k_incpc(4); | |
39821 | fill_prefetch_0 (); | |
39822 | m68k_write_memory_16(srca,dst); | |
39823 | }}}}}}}endlabel2223: ; | |
39824 | return 16; | |
39825 | } | |
39826 | unsigned long CPUFUNC(op_4479_5)(uint32_t opcode) /* NEG */ | |
39827 | { | |
39828 | OpcodeFamily = 15; CurrentInstrCycles = 20; | |
39829 | {{ uint32_t srca = get_ilong_prefetch(2); | |
39830 | if ((srca & 1) != 0) { | |
39831 | last_fault_for_exception_3 = srca; | |
39832 | last_op_for_exception_3 = opcode; | |
39833 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
39834 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
39835 | goto endlabel2224; | |
39836 | } | |
39837 | {{ int16_t src = m68k_read_memory_16(srca); | |
39838 | {{uint32_t dst = ((int16_t)(0)) - ((int16_t)(src)); | |
39839 | { int flgs = ((int16_t)(src)) < 0; | |
39840 | int flgo = ((int16_t)(0)) < 0; | |
39841 | int flgn = ((int16_t)(dst)) < 0; | |
39842 | SET_ZFLG (((int16_t)(dst)) == 0); | |
39843 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
39844 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(0))); | |
39845 | COPY_CARRY; | |
39846 | SET_NFLG (flgn != 0); | |
39847 | m68k_incpc(6); | |
39848 | fill_prefetch_0 (); | |
39849 | m68k_write_memory_16(srca,dst); | |
39850 | }}}}}}}endlabel2224: ; | |
39851 | return 20; | |
39852 | } | |
39853 | unsigned long CPUFUNC(op_4480_5)(uint32_t opcode) /* NEG */ | |
39854 | { | |
39855 | uint32_t srcreg = (opcode & 7); | |
39856 | OpcodeFamily = 15; CurrentInstrCycles = 6; | |
39857 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
39858 | {{uint32_t dst = ((int32_t)(0)) - ((int32_t)(src)); | |
39859 | { int flgs = ((int32_t)(src)) < 0; | |
39860 | int flgo = ((int32_t)(0)) < 0; | |
39861 | int flgn = ((int32_t)(dst)) < 0; | |
39862 | SET_ZFLG (((int32_t)(dst)) == 0); | |
39863 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
39864 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(0))); | |
39865 | COPY_CARRY; | |
39866 | SET_NFLG (flgn != 0); | |
39867 | m68k_dreg(regs, srcreg) = (dst); | |
39868 | }}}}}m68k_incpc(2); | |
39869 | fill_prefetch_2 (); | |
39870 | return 6; | |
39871 | } | |
39872 | unsigned long CPUFUNC(op_4490_5)(uint32_t opcode) /* NEG */ | |
39873 | { | |
39874 | uint32_t srcreg = (opcode & 7); | |
39875 | OpcodeFamily = 15; CurrentInstrCycles = 20; | |
39876 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
39877 | if ((srca & 1) != 0) { | |
39878 | last_fault_for_exception_3 = srca; | |
39879 | last_op_for_exception_3 = opcode; | |
39880 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
39881 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
39882 | goto endlabel2226; | |
39883 | } | |
39884 | {{ int32_t src = m68k_read_memory_32(srca); | |
39885 | {{uint32_t dst = ((int32_t)(0)) - ((int32_t)(src)); | |
39886 | { int flgs = ((int32_t)(src)) < 0; | |
39887 | int flgo = ((int32_t)(0)) < 0; | |
39888 | int flgn = ((int32_t)(dst)) < 0; | |
39889 | SET_ZFLG (((int32_t)(dst)) == 0); | |
39890 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
39891 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(0))); | |
39892 | COPY_CARRY; | |
39893 | SET_NFLG (flgn != 0); | |
39894 | m68k_incpc(2); | |
39895 | fill_prefetch_2 (); | |
39896 | m68k_write_memory_32(srca,dst); | |
39897 | }}}}}}}endlabel2226: ; | |
39898 | return 20; | |
39899 | } | |
39900 | unsigned long CPUFUNC(op_4498_5)(uint32_t opcode) /* NEG */ | |
39901 | { | |
39902 | uint32_t srcreg = (opcode & 7); | |
39903 | OpcodeFamily = 15; CurrentInstrCycles = 20; | |
39904 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
39905 | if ((srca & 1) != 0) { | |
39906 | last_fault_for_exception_3 = srca; | |
39907 | last_op_for_exception_3 = opcode; | |
39908 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
39909 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
39910 | goto endlabel2227; | |
39911 | } | |
39912 | {{ int32_t src = m68k_read_memory_32(srca); | |
39913 | m68k_areg(regs, srcreg) += 4; | |
39914 | {{uint32_t dst = ((int32_t)(0)) - ((int32_t)(src)); | |
39915 | { int flgs = ((int32_t)(src)) < 0; | |
39916 | int flgo = ((int32_t)(0)) < 0; | |
39917 | int flgn = ((int32_t)(dst)) < 0; | |
39918 | SET_ZFLG (((int32_t)(dst)) == 0); | |
39919 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
39920 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(0))); | |
39921 | COPY_CARRY; | |
39922 | SET_NFLG (flgn != 0); | |
39923 | m68k_incpc(2); | |
39924 | fill_prefetch_2 (); | |
39925 | m68k_write_memory_32(srca,dst); | |
39926 | }}}}}}}endlabel2227: ; | |
39927 | return 20; | |
39928 | } | |
39929 | unsigned long CPUFUNC(op_44a0_5)(uint32_t opcode) /* NEG */ | |
39930 | { | |
39931 | uint32_t srcreg = (opcode & 7); | |
39932 | OpcodeFamily = 15; CurrentInstrCycles = 22; | |
39933 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 4; | |
39934 | if ((srca & 1) != 0) { | |
39935 | last_fault_for_exception_3 = srca; | |
39936 | last_op_for_exception_3 = opcode; | |
39937 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
39938 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
39939 | goto endlabel2228; | |
39940 | } | |
39941 | {{ int32_t src = m68k_read_memory_32(srca); | |
39942 | m68k_areg (regs, srcreg) = srca; | |
39943 | {{uint32_t dst = ((int32_t)(0)) - ((int32_t)(src)); | |
39944 | { int flgs = ((int32_t)(src)) < 0; | |
39945 | int flgo = ((int32_t)(0)) < 0; | |
39946 | int flgn = ((int32_t)(dst)) < 0; | |
39947 | SET_ZFLG (((int32_t)(dst)) == 0); | |
39948 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
39949 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(0))); | |
39950 | COPY_CARRY; | |
39951 | SET_NFLG (flgn != 0); | |
39952 | m68k_incpc(2); | |
39953 | fill_prefetch_2 (); | |
39954 | m68k_write_memory_32(srca,dst); | |
39955 | }}}}}}}endlabel2228: ; | |
39956 | return 22; | |
39957 | } | |
39958 | unsigned long CPUFUNC(op_44a8_5)(uint32_t opcode) /* NEG */ | |
39959 | { | |
39960 | uint32_t srcreg = (opcode & 7); | |
39961 | OpcodeFamily = 15; CurrentInstrCycles = 24; | |
39962 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
39963 | if ((srca & 1) != 0) { | |
39964 | last_fault_for_exception_3 = srca; | |
39965 | last_op_for_exception_3 = opcode; | |
39966 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
39967 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
39968 | goto endlabel2229; | |
39969 | } | |
39970 | {{ int32_t src = m68k_read_memory_32(srca); | |
39971 | {{uint32_t dst = ((int32_t)(0)) - ((int32_t)(src)); | |
39972 | { int flgs = ((int32_t)(src)) < 0; | |
39973 | int flgo = ((int32_t)(0)) < 0; | |
39974 | int flgn = ((int32_t)(dst)) < 0; | |
39975 | SET_ZFLG (((int32_t)(dst)) == 0); | |
39976 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
39977 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(0))); | |
39978 | COPY_CARRY; | |
39979 | SET_NFLG (flgn != 0); | |
39980 | m68k_incpc(4); | |
39981 | fill_prefetch_0 (); | |
39982 | m68k_write_memory_32(srca,dst); | |
39983 | }}}}}}}endlabel2229: ; | |
39984 | return 24; | |
39985 | } | |
39986 | unsigned long CPUFUNC(op_44b0_5)(uint32_t opcode) /* NEG */ | |
39987 | { | |
39988 | uint32_t srcreg = (opcode & 7); | |
39989 | OpcodeFamily = 15; CurrentInstrCycles = 26; | |
39990 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
39991 | BusCyclePenalty += 2; | |
39992 | if ((srca & 1) != 0) { | |
39993 | last_fault_for_exception_3 = srca; | |
39994 | last_op_for_exception_3 = opcode; | |
39995 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
39996 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
39997 | goto endlabel2230; | |
39998 | } | |
39999 | {{ int32_t src = m68k_read_memory_32(srca); | |
40000 | {{uint32_t dst = ((int32_t)(0)) - ((int32_t)(src)); | |
40001 | { int flgs = ((int32_t)(src)) < 0; | |
40002 | int flgo = ((int32_t)(0)) < 0; | |
40003 | int flgn = ((int32_t)(dst)) < 0; | |
40004 | SET_ZFLG (((int32_t)(dst)) == 0); | |
40005 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
40006 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(0))); | |
40007 | COPY_CARRY; | |
40008 | SET_NFLG (flgn != 0); | |
40009 | m68k_incpc(4); | |
40010 | fill_prefetch_0 (); | |
40011 | m68k_write_memory_32(srca,dst); | |
40012 | }}}}}}}endlabel2230: ; | |
40013 | return 26; | |
40014 | } | |
40015 | unsigned long CPUFUNC(op_44b8_5)(uint32_t opcode) /* NEG */ | |
40016 | { | |
40017 | OpcodeFamily = 15; CurrentInstrCycles = 24; | |
40018 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
40019 | if ((srca & 1) != 0) { | |
40020 | last_fault_for_exception_3 = srca; | |
40021 | last_op_for_exception_3 = opcode; | |
40022 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
40023 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
40024 | goto endlabel2231; | |
40025 | } | |
40026 | {{ int32_t src = m68k_read_memory_32(srca); | |
40027 | {{uint32_t dst = ((int32_t)(0)) - ((int32_t)(src)); | |
40028 | { int flgs = ((int32_t)(src)) < 0; | |
40029 | int flgo = ((int32_t)(0)) < 0; | |
40030 | int flgn = ((int32_t)(dst)) < 0; | |
40031 | SET_ZFLG (((int32_t)(dst)) == 0); | |
40032 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
40033 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(0))); | |
40034 | COPY_CARRY; | |
40035 | SET_NFLG (flgn != 0); | |
40036 | m68k_incpc(4); | |
40037 | fill_prefetch_0 (); | |
40038 | m68k_write_memory_32(srca,dst); | |
40039 | }}}}}}}endlabel2231: ; | |
40040 | return 24; | |
40041 | } | |
40042 | unsigned long CPUFUNC(op_44b9_5)(uint32_t opcode) /* NEG */ | |
40043 | { | |
40044 | OpcodeFamily = 15; CurrentInstrCycles = 28; | |
40045 | {{ uint32_t srca = get_ilong_prefetch(2); | |
40046 | if ((srca & 1) != 0) { | |
40047 | last_fault_for_exception_3 = srca; | |
40048 | last_op_for_exception_3 = opcode; | |
40049 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
40050 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
40051 | goto endlabel2232; | |
40052 | } | |
40053 | {{ int32_t src = m68k_read_memory_32(srca); | |
40054 | {{uint32_t dst = ((int32_t)(0)) - ((int32_t)(src)); | |
40055 | { int flgs = ((int32_t)(src)) < 0; | |
40056 | int flgo = ((int32_t)(0)) < 0; | |
40057 | int flgn = ((int32_t)(dst)) < 0; | |
40058 | SET_ZFLG (((int32_t)(dst)) == 0); | |
40059 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
40060 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(0))); | |
40061 | COPY_CARRY; | |
40062 | SET_NFLG (flgn != 0); | |
40063 | m68k_incpc(6); | |
40064 | fill_prefetch_0 (); | |
40065 | m68k_write_memory_32(srca,dst); | |
40066 | }}}}}}}endlabel2232: ; | |
40067 | return 28; | |
40068 | } | |
40069 | unsigned long CPUFUNC(op_44c0_5)(uint32_t opcode) /* MV2SR */ | |
40070 | { | |
40071 | uint32_t srcreg = (opcode & 7); | |
40072 | OpcodeFamily = 33; CurrentInstrCycles = 12; | |
40073 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
40074 | MakeSR(); | |
40075 | regs.sr &= 0xFF00; | |
40076 | regs.sr |= src & 0xFF; | |
40077 | MakeFromSR(); | |
40078 | }}m68k_incpc(2); | |
40079 | fill_prefetch_2 (); | |
40080 | return 12; | |
40081 | } | |
40082 | unsigned long CPUFUNC(op_44d0_5)(uint32_t opcode) /* MV2SR */ | |
40083 | { | |
40084 | uint32_t srcreg = (opcode & 7); | |
40085 | OpcodeFamily = 33; CurrentInstrCycles = 16; | |
40086 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
40087 | if ((srca & 1) != 0) { | |
40088 | last_fault_for_exception_3 = srca; | |
40089 | last_op_for_exception_3 = opcode; | |
40090 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
40091 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
40092 | goto endlabel2234; | |
40093 | } | |
40094 | {{ int16_t src = m68k_read_memory_16(srca); | |
40095 | MakeSR(); | |
40096 | regs.sr &= 0xFF00; | |
40097 | regs.sr |= src & 0xFF; | |
40098 | MakeFromSR(); | |
40099 | }}}}m68k_incpc(2); | |
40100 | fill_prefetch_2 (); | |
40101 | endlabel2234: ; | |
40102 | return 16; | |
40103 | } | |
40104 | unsigned long CPUFUNC(op_44d8_5)(uint32_t opcode) /* MV2SR */ | |
40105 | { | |
40106 | uint32_t srcreg = (opcode & 7); | |
40107 | OpcodeFamily = 33; CurrentInstrCycles = 16; | |
40108 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
40109 | if ((srca & 1) != 0) { | |
40110 | last_fault_for_exception_3 = srca; | |
40111 | last_op_for_exception_3 = opcode; | |
40112 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
40113 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
40114 | goto endlabel2235; | |
40115 | } | |
40116 | {{ int16_t src = m68k_read_memory_16(srca); | |
40117 | m68k_areg(regs, srcreg) += 2; | |
40118 | MakeSR(); | |
40119 | regs.sr &= 0xFF00; | |
40120 | regs.sr |= src & 0xFF; | |
40121 | MakeFromSR(); | |
40122 | }}}}m68k_incpc(2); | |
40123 | fill_prefetch_2 (); | |
40124 | endlabel2235: ; | |
40125 | return 16; | |
40126 | } | |
40127 | unsigned long CPUFUNC(op_44e0_5)(uint32_t opcode) /* MV2SR */ | |
40128 | { | |
40129 | uint32_t srcreg = (opcode & 7); | |
40130 | OpcodeFamily = 33; CurrentInstrCycles = 18; | |
40131 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
40132 | if ((srca & 1) != 0) { | |
40133 | last_fault_for_exception_3 = srca; | |
40134 | last_op_for_exception_3 = opcode; | |
40135 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
40136 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
40137 | goto endlabel2236; | |
40138 | } | |
40139 | {{ int16_t src = m68k_read_memory_16(srca); | |
40140 | m68k_areg (regs, srcreg) = srca; | |
40141 | MakeSR(); | |
40142 | regs.sr &= 0xFF00; | |
40143 | regs.sr |= src & 0xFF; | |
40144 | MakeFromSR(); | |
40145 | }}}}m68k_incpc(2); | |
40146 | fill_prefetch_2 (); | |
40147 | endlabel2236: ; | |
40148 | return 18; | |
40149 | } | |
40150 | unsigned long CPUFUNC(op_44e8_5)(uint32_t opcode) /* MV2SR */ | |
40151 | { | |
40152 | uint32_t srcreg = (opcode & 7); | |
40153 | OpcodeFamily = 33; CurrentInstrCycles = 20; | |
40154 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
40155 | if ((srca & 1) != 0) { | |
40156 | last_fault_for_exception_3 = srca; | |
40157 | last_op_for_exception_3 = opcode; | |
40158 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
40159 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
40160 | goto endlabel2237; | |
40161 | } | |
40162 | {{ int16_t src = m68k_read_memory_16(srca); | |
40163 | MakeSR(); | |
40164 | regs.sr &= 0xFF00; | |
40165 | regs.sr |= src & 0xFF; | |
40166 | MakeFromSR(); | |
40167 | }}}}m68k_incpc(4); | |
40168 | fill_prefetch_0 (); | |
40169 | endlabel2237: ; | |
40170 | return 20; | |
40171 | } | |
40172 | unsigned long CPUFUNC(op_44f0_5)(uint32_t opcode) /* MV2SR */ | |
40173 | { | |
40174 | uint32_t srcreg = (opcode & 7); | |
40175 | OpcodeFamily = 33; CurrentInstrCycles = 22; | |
40176 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
40177 | BusCyclePenalty += 2; | |
40178 | if ((srca & 1) != 0) { | |
40179 | last_fault_for_exception_3 = srca; | |
40180 | last_op_for_exception_3 = opcode; | |
40181 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
40182 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
40183 | goto endlabel2238; | |
40184 | } | |
40185 | {{ int16_t src = m68k_read_memory_16(srca); | |
40186 | MakeSR(); | |
40187 | regs.sr &= 0xFF00; | |
40188 | regs.sr |= src & 0xFF; | |
40189 | MakeFromSR(); | |
40190 | }}}}m68k_incpc(4); | |
40191 | fill_prefetch_0 (); | |
40192 | endlabel2238: ; | |
40193 | return 22; | |
40194 | } | |
40195 | unsigned long CPUFUNC(op_44f8_5)(uint32_t opcode) /* MV2SR */ | |
40196 | { | |
40197 | OpcodeFamily = 33; CurrentInstrCycles = 20; | |
40198 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
40199 | if ((srca & 1) != 0) { | |
40200 | last_fault_for_exception_3 = srca; | |
40201 | last_op_for_exception_3 = opcode; | |
40202 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
40203 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
40204 | goto endlabel2239; | |
40205 | } | |
40206 | {{ int16_t src = m68k_read_memory_16(srca); | |
40207 | MakeSR(); | |
40208 | regs.sr &= 0xFF00; | |
40209 | regs.sr |= src & 0xFF; | |
40210 | MakeFromSR(); | |
40211 | }}}}m68k_incpc(4); | |
40212 | fill_prefetch_0 (); | |
40213 | endlabel2239: ; | |
40214 | return 20; | |
40215 | } | |
40216 | unsigned long CPUFUNC(op_44f9_5)(uint32_t opcode) /* MV2SR */ | |
40217 | { | |
40218 | OpcodeFamily = 33; CurrentInstrCycles = 24; | |
40219 | {{ uint32_t srca = get_ilong_prefetch(2); | |
40220 | if ((srca & 1) != 0) { | |
40221 | last_fault_for_exception_3 = srca; | |
40222 | last_op_for_exception_3 = opcode; | |
40223 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
40224 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
40225 | goto endlabel2240; | |
40226 | } | |
40227 | {{ int16_t src = m68k_read_memory_16(srca); | |
40228 | MakeSR(); | |
40229 | regs.sr &= 0xFF00; | |
40230 | regs.sr |= src & 0xFF; | |
40231 | MakeFromSR(); | |
40232 | }}}}m68k_incpc(6); | |
40233 | fill_prefetch_0 (); | |
40234 | endlabel2240: ; | |
40235 | return 24; | |
40236 | } | |
40237 | unsigned long CPUFUNC(op_44fa_5)(uint32_t opcode) /* MV2SR */ | |
40238 | { | |
40239 | OpcodeFamily = 33; CurrentInstrCycles = 20; | |
40240 | {{ uint32_t srca = m68k_getpc () + 2; | |
40241 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
40242 | if ((srca & 1) != 0) { | |
40243 | last_fault_for_exception_3 = srca; | |
40244 | last_op_for_exception_3 = opcode; | |
40245 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
40246 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
40247 | goto endlabel2241; | |
40248 | } | |
40249 | {{ int16_t src = m68k_read_memory_16(srca); | |
40250 | MakeSR(); | |
40251 | regs.sr &= 0xFF00; | |
40252 | regs.sr |= src & 0xFF; | |
40253 | MakeFromSR(); | |
40254 | }}}}m68k_incpc(4); | |
40255 | fill_prefetch_0 (); | |
40256 | endlabel2241: ; | |
40257 | return 20; | |
40258 | } | |
40259 | unsigned long CPUFUNC(op_44fb_5)(uint32_t opcode) /* MV2SR */ | |
40260 | { | |
40261 | OpcodeFamily = 33; CurrentInstrCycles = 22; | |
40262 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
40263 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
40264 | BusCyclePenalty += 2; | |
40265 | if ((srca & 1) != 0) { | |
40266 | last_fault_for_exception_3 = srca; | |
40267 | last_op_for_exception_3 = opcode; | |
40268 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
40269 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
40270 | goto endlabel2242; | |
40271 | } | |
40272 | {{ int16_t src = m68k_read_memory_16(srca); | |
40273 | MakeSR(); | |
40274 | regs.sr &= 0xFF00; | |
40275 | regs.sr |= src & 0xFF; | |
40276 | MakeFromSR(); | |
40277 | }}}}m68k_incpc(4); | |
40278 | fill_prefetch_0 (); | |
40279 | endlabel2242: ; | |
40280 | return 22; | |
40281 | } | |
40282 | unsigned long CPUFUNC(op_44fc_5)(uint32_t opcode) /* MV2SR */ | |
40283 | { | |
40284 | OpcodeFamily = 33; CurrentInstrCycles = 16; | |
40285 | {{ int16_t src = get_iword_prefetch(2); | |
40286 | MakeSR(); | |
40287 | regs.sr &= 0xFF00; | |
40288 | regs.sr |= src & 0xFF; | |
40289 | MakeFromSR(); | |
40290 | }}m68k_incpc(4); | |
40291 | fill_prefetch_0 (); | |
40292 | return 16; | |
40293 | } | |
40294 | unsigned long CPUFUNC(op_4600_5)(uint32_t opcode) /* NOT */ | |
40295 | { | |
40296 | uint32_t srcreg = (opcode & 7); | |
40297 | OpcodeFamily = 19; CurrentInstrCycles = 4; | |
40298 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
40299 | { uint32_t dst = ~src; | |
40300 | CLEAR_CZNV; | |
40301 | SET_ZFLG (((int8_t)(dst)) == 0); | |
40302 | SET_NFLG (((int8_t)(dst)) < 0); | |
40303 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((dst) & 0xff); | |
40304 | }}}m68k_incpc(2); | |
40305 | fill_prefetch_2 (); | |
40306 | return 4; | |
40307 | } | |
40308 | unsigned long CPUFUNC(op_4610_5)(uint32_t opcode) /* NOT */ | |
40309 | { | |
40310 | uint32_t srcreg = (opcode & 7); | |
40311 | OpcodeFamily = 19; CurrentInstrCycles = 12; | |
40312 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
40313 | { int8_t src = m68k_read_memory_8(srca); | |
40314 | { uint32_t dst = ~src; | |
40315 | CLEAR_CZNV; | |
40316 | SET_ZFLG (((int8_t)(dst)) == 0); | |
40317 | SET_NFLG (((int8_t)(dst)) < 0); | |
40318 | m68k_incpc(2); | |
40319 | fill_prefetch_2 (); | |
40320 | m68k_write_memory_8(srca,dst); | |
40321 | }}}}return 12; | |
40322 | } | |
40323 | unsigned long CPUFUNC(op_4618_5)(uint32_t opcode) /* NOT */ | |
40324 | { | |
40325 | uint32_t srcreg = (opcode & 7); | |
40326 | OpcodeFamily = 19; CurrentInstrCycles = 12; | |
40327 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
40328 | { int8_t src = m68k_read_memory_8(srca); | |
40329 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
40330 | { uint32_t dst = ~src; | |
40331 | CLEAR_CZNV; | |
40332 | SET_ZFLG (((int8_t)(dst)) == 0); | |
40333 | SET_NFLG (((int8_t)(dst)) < 0); | |
40334 | m68k_incpc(2); | |
40335 | fill_prefetch_2 (); | |
40336 | m68k_write_memory_8(srca,dst); | |
40337 | }}}}return 12; | |
40338 | } | |
40339 | unsigned long CPUFUNC(op_4620_5)(uint32_t opcode) /* NOT */ | |
40340 | { | |
40341 | uint32_t srcreg = (opcode & 7); | |
40342 | OpcodeFamily = 19; CurrentInstrCycles = 14; | |
40343 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
40344 | { int8_t src = m68k_read_memory_8(srca); | |
40345 | m68k_areg (regs, srcreg) = srca; | |
40346 | { uint32_t dst = ~src; | |
40347 | CLEAR_CZNV; | |
40348 | SET_ZFLG (((int8_t)(dst)) == 0); | |
40349 | SET_NFLG (((int8_t)(dst)) < 0); | |
40350 | m68k_incpc(2); | |
40351 | fill_prefetch_2 (); | |
40352 | m68k_write_memory_8(srca,dst); | |
40353 | }}}}return 14; | |
40354 | } | |
40355 | unsigned long CPUFUNC(op_4628_5)(uint32_t opcode) /* NOT */ | |
40356 | { | |
40357 | uint32_t srcreg = (opcode & 7); | |
40358 | OpcodeFamily = 19; CurrentInstrCycles = 16; | |
40359 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
40360 | { int8_t src = m68k_read_memory_8(srca); | |
40361 | { uint32_t dst = ~src; | |
40362 | CLEAR_CZNV; | |
40363 | SET_ZFLG (((int8_t)(dst)) == 0); | |
40364 | SET_NFLG (((int8_t)(dst)) < 0); | |
40365 | m68k_incpc(4); | |
40366 | fill_prefetch_0 (); | |
40367 | m68k_write_memory_8(srca,dst); | |
40368 | }}}}return 16; | |
40369 | } | |
40370 | unsigned long CPUFUNC(op_4630_5)(uint32_t opcode) /* NOT */ | |
40371 | { | |
40372 | uint32_t srcreg = (opcode & 7); | |
40373 | OpcodeFamily = 19; CurrentInstrCycles = 18; | |
40374 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
40375 | BusCyclePenalty += 2; | |
40376 | { int8_t src = m68k_read_memory_8(srca); | |
40377 | { uint32_t dst = ~src; | |
40378 | CLEAR_CZNV; | |
40379 | SET_ZFLG (((int8_t)(dst)) == 0); | |
40380 | SET_NFLG (((int8_t)(dst)) < 0); | |
40381 | m68k_incpc(4); | |
40382 | fill_prefetch_0 (); | |
40383 | m68k_write_memory_8(srca,dst); | |
40384 | }}}}return 18; | |
40385 | } | |
40386 | unsigned long CPUFUNC(op_4638_5)(uint32_t opcode) /* NOT */ | |
40387 | { | |
40388 | OpcodeFamily = 19; CurrentInstrCycles = 16; | |
40389 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
40390 | { int8_t src = m68k_read_memory_8(srca); | |
40391 | { uint32_t dst = ~src; | |
40392 | CLEAR_CZNV; | |
40393 | SET_ZFLG (((int8_t)(dst)) == 0); | |
40394 | SET_NFLG (((int8_t)(dst)) < 0); | |
40395 | m68k_incpc(4); | |
40396 | fill_prefetch_0 (); | |
40397 | m68k_write_memory_8(srca,dst); | |
40398 | }}}}return 16; | |
40399 | } | |
40400 | unsigned long CPUFUNC(op_4639_5)(uint32_t opcode) /* NOT */ | |
40401 | { | |
40402 | OpcodeFamily = 19; CurrentInstrCycles = 20; | |
40403 | {{ uint32_t srca = get_ilong_prefetch(2); | |
40404 | { int8_t src = m68k_read_memory_8(srca); | |
40405 | { uint32_t dst = ~src; | |
40406 | CLEAR_CZNV; | |
40407 | SET_ZFLG (((int8_t)(dst)) == 0); | |
40408 | SET_NFLG (((int8_t)(dst)) < 0); | |
40409 | m68k_incpc(6); | |
40410 | fill_prefetch_0 (); | |
40411 | m68k_write_memory_8(srca,dst); | |
40412 | }}}}return 20; | |
40413 | } | |
40414 | unsigned long CPUFUNC(op_4640_5)(uint32_t opcode) /* NOT */ | |
40415 | { | |
40416 | uint32_t srcreg = (opcode & 7); | |
40417 | OpcodeFamily = 19; CurrentInstrCycles = 4; | |
40418 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
40419 | { uint32_t dst = ~src; | |
40420 | CLEAR_CZNV; | |
40421 | SET_ZFLG (((int16_t)(dst)) == 0); | |
40422 | SET_NFLG (((int16_t)(dst)) < 0); | |
40423 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((dst) & 0xffff); | |
40424 | }}}m68k_incpc(2); | |
40425 | fill_prefetch_2 (); | |
40426 | return 4; | |
40427 | } | |
40428 | unsigned long CPUFUNC(op_4650_5)(uint32_t opcode) /* NOT */ | |
40429 | { | |
40430 | uint32_t srcreg = (opcode & 7); | |
40431 | OpcodeFamily = 19; CurrentInstrCycles = 12; | |
40432 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
40433 | if ((srca & 1) != 0) { | |
40434 | last_fault_for_exception_3 = srca; | |
40435 | last_op_for_exception_3 = opcode; | |
40436 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
40437 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
40438 | goto endlabel2253; | |
40439 | } | |
40440 | {{ int16_t src = m68k_read_memory_16(srca); | |
40441 | { uint32_t dst = ~src; | |
40442 | CLEAR_CZNV; | |
40443 | SET_ZFLG (((int16_t)(dst)) == 0); | |
40444 | SET_NFLG (((int16_t)(dst)) < 0); | |
40445 | m68k_incpc(2); | |
40446 | fill_prefetch_2 (); | |
40447 | m68k_write_memory_16(srca,dst); | |
40448 | }}}}}endlabel2253: ; | |
40449 | return 12; | |
40450 | } | |
40451 | unsigned long CPUFUNC(op_4658_5)(uint32_t opcode) /* NOT */ | |
40452 | { | |
40453 | uint32_t srcreg = (opcode & 7); | |
40454 | OpcodeFamily = 19; CurrentInstrCycles = 12; | |
40455 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
40456 | if ((srca & 1) != 0) { | |
40457 | last_fault_for_exception_3 = srca; | |
40458 | last_op_for_exception_3 = opcode; | |
40459 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
40460 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
40461 | goto endlabel2254; | |
40462 | } | |
40463 | {{ int16_t src = m68k_read_memory_16(srca); | |
40464 | m68k_areg(regs, srcreg) += 2; | |
40465 | { uint32_t dst = ~src; | |
40466 | CLEAR_CZNV; | |
40467 | SET_ZFLG (((int16_t)(dst)) == 0); | |
40468 | SET_NFLG (((int16_t)(dst)) < 0); | |
40469 | m68k_incpc(2); | |
40470 | fill_prefetch_2 (); | |
40471 | m68k_write_memory_16(srca,dst); | |
40472 | }}}}}endlabel2254: ; | |
40473 | return 12; | |
40474 | } | |
40475 | unsigned long CPUFUNC(op_4660_5)(uint32_t opcode) /* NOT */ | |
40476 | { | |
40477 | uint32_t srcreg = (opcode & 7); | |
40478 | OpcodeFamily = 19; CurrentInstrCycles = 14; | |
40479 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
40480 | if ((srca & 1) != 0) { | |
40481 | last_fault_for_exception_3 = srca; | |
40482 | last_op_for_exception_3 = opcode; | |
40483 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
40484 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
40485 | goto endlabel2255; | |
40486 | } | |
40487 | {{ int16_t src = m68k_read_memory_16(srca); | |
40488 | m68k_areg (regs, srcreg) = srca; | |
40489 | { uint32_t dst = ~src; | |
40490 | CLEAR_CZNV; | |
40491 | SET_ZFLG (((int16_t)(dst)) == 0); | |
40492 | SET_NFLG (((int16_t)(dst)) < 0); | |
40493 | m68k_incpc(2); | |
40494 | fill_prefetch_2 (); | |
40495 | m68k_write_memory_16(srca,dst); | |
40496 | }}}}}endlabel2255: ; | |
40497 | return 14; | |
40498 | } | |
40499 | unsigned long CPUFUNC(op_4668_5)(uint32_t opcode) /* NOT */ | |
40500 | { | |
40501 | uint32_t srcreg = (opcode & 7); | |
40502 | OpcodeFamily = 19; CurrentInstrCycles = 16; | |
40503 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
40504 | if ((srca & 1) != 0) { | |
40505 | last_fault_for_exception_3 = srca; | |
40506 | last_op_for_exception_3 = opcode; | |
40507 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
40508 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
40509 | goto endlabel2256; | |
40510 | } | |
40511 | {{ int16_t src = m68k_read_memory_16(srca); | |
40512 | { uint32_t dst = ~src; | |
40513 | CLEAR_CZNV; | |
40514 | SET_ZFLG (((int16_t)(dst)) == 0); | |
40515 | SET_NFLG (((int16_t)(dst)) < 0); | |
40516 | m68k_incpc(4); | |
40517 | fill_prefetch_0 (); | |
40518 | m68k_write_memory_16(srca,dst); | |
40519 | }}}}}endlabel2256: ; | |
40520 | return 16; | |
40521 | } | |
40522 | unsigned long CPUFUNC(op_4670_5)(uint32_t opcode) /* NOT */ | |
40523 | { | |
40524 | uint32_t srcreg = (opcode & 7); | |
40525 | OpcodeFamily = 19; CurrentInstrCycles = 18; | |
40526 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
40527 | BusCyclePenalty += 2; | |
40528 | if ((srca & 1) != 0) { | |
40529 | last_fault_for_exception_3 = srca; | |
40530 | last_op_for_exception_3 = opcode; | |
40531 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
40532 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
40533 | goto endlabel2257; | |
40534 | } | |
40535 | {{ int16_t src = m68k_read_memory_16(srca); | |
40536 | { uint32_t dst = ~src; | |
40537 | CLEAR_CZNV; | |
40538 | SET_ZFLG (((int16_t)(dst)) == 0); | |
40539 | SET_NFLG (((int16_t)(dst)) < 0); | |
40540 | m68k_incpc(4); | |
40541 | fill_prefetch_0 (); | |
40542 | m68k_write_memory_16(srca,dst); | |
40543 | }}}}}endlabel2257: ; | |
40544 | return 18; | |
40545 | } | |
40546 | unsigned long CPUFUNC(op_4678_5)(uint32_t opcode) /* NOT */ | |
40547 | { | |
40548 | OpcodeFamily = 19; CurrentInstrCycles = 16; | |
40549 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
40550 | if ((srca & 1) != 0) { | |
40551 | last_fault_for_exception_3 = srca; | |
40552 | last_op_for_exception_3 = opcode; | |
40553 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
40554 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
40555 | goto endlabel2258; | |
40556 | } | |
40557 | {{ int16_t src = m68k_read_memory_16(srca); | |
40558 | { uint32_t dst = ~src; | |
40559 | CLEAR_CZNV; | |
40560 | SET_ZFLG (((int16_t)(dst)) == 0); | |
40561 | SET_NFLG (((int16_t)(dst)) < 0); | |
40562 | m68k_incpc(4); | |
40563 | fill_prefetch_0 (); | |
40564 | m68k_write_memory_16(srca,dst); | |
40565 | }}}}}endlabel2258: ; | |
40566 | return 16; | |
40567 | } | |
40568 | unsigned long CPUFUNC(op_4679_5)(uint32_t opcode) /* NOT */ | |
40569 | { | |
40570 | OpcodeFamily = 19; CurrentInstrCycles = 20; | |
40571 | {{ uint32_t srca = get_ilong_prefetch(2); | |
40572 | if ((srca & 1) != 0) { | |
40573 | last_fault_for_exception_3 = srca; | |
40574 | last_op_for_exception_3 = opcode; | |
40575 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
40576 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
40577 | goto endlabel2259; | |
40578 | } | |
40579 | {{ int16_t src = m68k_read_memory_16(srca); | |
40580 | { uint32_t dst = ~src; | |
40581 | CLEAR_CZNV; | |
40582 | SET_ZFLG (((int16_t)(dst)) == 0); | |
40583 | SET_NFLG (((int16_t)(dst)) < 0); | |
40584 | m68k_incpc(6); | |
40585 | fill_prefetch_0 (); | |
40586 | m68k_write_memory_16(srca,dst); | |
40587 | }}}}}endlabel2259: ; | |
40588 | return 20; | |
40589 | } | |
40590 | unsigned long CPUFUNC(op_4680_5)(uint32_t opcode) /* NOT */ | |
40591 | { | |
40592 | uint32_t srcreg = (opcode & 7); | |
40593 | OpcodeFamily = 19; CurrentInstrCycles = 6; | |
40594 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
40595 | { uint32_t dst = ~src; | |
40596 | CLEAR_CZNV; | |
40597 | SET_ZFLG (((int32_t)(dst)) == 0); | |
40598 | SET_NFLG (((int32_t)(dst)) < 0); | |
40599 | m68k_dreg(regs, srcreg) = (dst); | |
40600 | }}}m68k_incpc(2); | |
40601 | fill_prefetch_2 (); | |
40602 | return 6; | |
40603 | } | |
40604 | unsigned long CPUFUNC(op_4690_5)(uint32_t opcode) /* NOT */ | |
40605 | { | |
40606 | uint32_t srcreg = (opcode & 7); | |
40607 | OpcodeFamily = 19; CurrentInstrCycles = 20; | |
40608 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
40609 | if ((srca & 1) != 0) { | |
40610 | last_fault_for_exception_3 = srca; | |
40611 | last_op_for_exception_3 = opcode; | |
40612 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
40613 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
40614 | goto endlabel2261; | |
40615 | } | |
40616 | {{ int32_t src = m68k_read_memory_32(srca); | |
40617 | { uint32_t dst = ~src; | |
40618 | CLEAR_CZNV; | |
40619 | SET_ZFLG (((int32_t)(dst)) == 0); | |
40620 | SET_NFLG (((int32_t)(dst)) < 0); | |
40621 | m68k_incpc(2); | |
40622 | fill_prefetch_2 (); | |
40623 | m68k_write_memory_32(srca,dst); | |
40624 | }}}}}endlabel2261: ; | |
40625 | return 20; | |
40626 | } | |
40627 | unsigned long CPUFUNC(op_4698_5)(uint32_t opcode) /* NOT */ | |
40628 | { | |
40629 | uint32_t srcreg = (opcode & 7); | |
40630 | OpcodeFamily = 19; CurrentInstrCycles = 20; | |
40631 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
40632 | if ((srca & 1) != 0) { | |
40633 | last_fault_for_exception_3 = srca; | |
40634 | last_op_for_exception_3 = opcode; | |
40635 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
40636 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
40637 | goto endlabel2262; | |
40638 | } | |
40639 | {{ int32_t src = m68k_read_memory_32(srca); | |
40640 | m68k_areg(regs, srcreg) += 4; | |
40641 | { uint32_t dst = ~src; | |
40642 | CLEAR_CZNV; | |
40643 | SET_ZFLG (((int32_t)(dst)) == 0); | |
40644 | SET_NFLG (((int32_t)(dst)) < 0); | |
40645 | m68k_incpc(2); | |
40646 | fill_prefetch_2 (); | |
40647 | m68k_write_memory_32(srca,dst); | |
40648 | }}}}}endlabel2262: ; | |
40649 | return 20; | |
40650 | } | |
40651 | unsigned long CPUFUNC(op_46a0_5)(uint32_t opcode) /* NOT */ | |
40652 | { | |
40653 | uint32_t srcreg = (opcode & 7); | |
40654 | OpcodeFamily = 19; CurrentInstrCycles = 22; | |
40655 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 4; | |
40656 | if ((srca & 1) != 0) { | |
40657 | last_fault_for_exception_3 = srca; | |
40658 | last_op_for_exception_3 = opcode; | |
40659 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
40660 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
40661 | goto endlabel2263; | |
40662 | } | |
40663 | {{ int32_t src = m68k_read_memory_32(srca); | |
40664 | m68k_areg (regs, srcreg) = srca; | |
40665 | { uint32_t dst = ~src; | |
40666 | CLEAR_CZNV; | |
40667 | SET_ZFLG (((int32_t)(dst)) == 0); | |
40668 | SET_NFLG (((int32_t)(dst)) < 0); | |
40669 | m68k_incpc(2); | |
40670 | fill_prefetch_2 (); | |
40671 | m68k_write_memory_32(srca,dst); | |
40672 | }}}}}endlabel2263: ; | |
40673 | return 22; | |
40674 | } | |
40675 | unsigned long CPUFUNC(op_46a8_5)(uint32_t opcode) /* NOT */ | |
40676 | { | |
40677 | uint32_t srcreg = (opcode & 7); | |
40678 | OpcodeFamily = 19; CurrentInstrCycles = 24; | |
40679 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
40680 | if ((srca & 1) != 0) { | |
40681 | last_fault_for_exception_3 = srca; | |
40682 | last_op_for_exception_3 = opcode; | |
40683 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
40684 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
40685 | goto endlabel2264; | |
40686 | } | |
40687 | {{ int32_t src = m68k_read_memory_32(srca); | |
40688 | { uint32_t dst = ~src; | |
40689 | CLEAR_CZNV; | |
40690 | SET_ZFLG (((int32_t)(dst)) == 0); | |
40691 | SET_NFLG (((int32_t)(dst)) < 0); | |
40692 | m68k_incpc(4); | |
40693 | fill_prefetch_0 (); | |
40694 | m68k_write_memory_32(srca,dst); | |
40695 | }}}}}endlabel2264: ; | |
40696 | return 24; | |
40697 | } | |
40698 | unsigned long CPUFUNC(op_46b0_5)(uint32_t opcode) /* NOT */ | |
40699 | { | |
40700 | uint32_t srcreg = (opcode & 7); | |
40701 | OpcodeFamily = 19; CurrentInstrCycles = 26; | |
40702 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
40703 | BusCyclePenalty += 2; | |
40704 | if ((srca & 1) != 0) { | |
40705 | last_fault_for_exception_3 = srca; | |
40706 | last_op_for_exception_3 = opcode; | |
40707 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
40708 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
40709 | goto endlabel2265; | |
40710 | } | |
40711 | {{ int32_t src = m68k_read_memory_32(srca); | |
40712 | { uint32_t dst = ~src; | |
40713 | CLEAR_CZNV; | |
40714 | SET_ZFLG (((int32_t)(dst)) == 0); | |
40715 | SET_NFLG (((int32_t)(dst)) < 0); | |
40716 | m68k_incpc(4); | |
40717 | fill_prefetch_0 (); | |
40718 | m68k_write_memory_32(srca,dst); | |
40719 | }}}}}endlabel2265: ; | |
40720 | return 26; | |
40721 | } | |
40722 | unsigned long CPUFUNC(op_46b8_5)(uint32_t opcode) /* NOT */ | |
40723 | { | |
40724 | OpcodeFamily = 19; CurrentInstrCycles = 24; | |
40725 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
40726 | if ((srca & 1) != 0) { | |
40727 | last_fault_for_exception_3 = srca; | |
40728 | last_op_for_exception_3 = opcode; | |
40729 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
40730 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
40731 | goto endlabel2266; | |
40732 | } | |
40733 | {{ int32_t src = m68k_read_memory_32(srca); | |
40734 | { uint32_t dst = ~src; | |
40735 | CLEAR_CZNV; | |
40736 | SET_ZFLG (((int32_t)(dst)) == 0); | |
40737 | SET_NFLG (((int32_t)(dst)) < 0); | |
40738 | m68k_incpc(4); | |
40739 | fill_prefetch_0 (); | |
40740 | m68k_write_memory_32(srca,dst); | |
40741 | }}}}}endlabel2266: ; | |
40742 | return 24; | |
40743 | } | |
40744 | unsigned long CPUFUNC(op_46b9_5)(uint32_t opcode) /* NOT */ | |
40745 | { | |
40746 | OpcodeFamily = 19; CurrentInstrCycles = 28; | |
40747 | {{ uint32_t srca = get_ilong_prefetch(2); | |
40748 | if ((srca & 1) != 0) { | |
40749 | last_fault_for_exception_3 = srca; | |
40750 | last_op_for_exception_3 = opcode; | |
40751 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
40752 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
40753 | goto endlabel2267; | |
40754 | } | |
40755 | {{ int32_t src = m68k_read_memory_32(srca); | |
40756 | { uint32_t dst = ~src; | |
40757 | CLEAR_CZNV; | |
40758 | SET_ZFLG (((int32_t)(dst)) == 0); | |
40759 | SET_NFLG (((int32_t)(dst)) < 0); | |
40760 | m68k_incpc(6); | |
40761 | fill_prefetch_0 (); | |
40762 | m68k_write_memory_32(srca,dst); | |
40763 | }}}}}endlabel2267: ; | |
40764 | return 28; | |
40765 | } | |
40766 | unsigned long CPUFUNC(op_46c0_5)(uint32_t opcode) /* MV2SR */ | |
40767 | { | |
40768 | uint32_t srcreg = (opcode & 7); | |
40769 | OpcodeFamily = 33; CurrentInstrCycles = 12; | |
40770 | {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2268; } | |
40771 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
40772 | regs.sr = src; | |
40773 | MakeFromSR(); | |
40774 | }}}m68k_incpc(2); | |
40775 | fill_prefetch_2 (); | |
40776 | endlabel2268: ; | |
40777 | return 12; | |
40778 | } | |
40779 | unsigned long CPUFUNC(op_46d0_5)(uint32_t opcode) /* MV2SR */ | |
40780 | { | |
40781 | uint32_t srcreg = (opcode & 7); | |
40782 | OpcodeFamily = 33; CurrentInstrCycles = 16; | |
40783 | {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2269; } | |
40784 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
40785 | if ((srca & 1) != 0) { | |
40786 | last_fault_for_exception_3 = srca; | |
40787 | last_op_for_exception_3 = opcode; | |
40788 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
40789 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
40790 | goto endlabel2269; | |
40791 | } | |
40792 | {{ int16_t src = m68k_read_memory_16(srca); | |
40793 | regs.sr = src; | |
40794 | MakeFromSR(); | |
40795 | }}}}}m68k_incpc(2); | |
40796 | fill_prefetch_2 (); | |
40797 | endlabel2269: ; | |
40798 | return 16; | |
40799 | } | |
40800 | unsigned long CPUFUNC(op_46d8_5)(uint32_t opcode) /* MV2SR */ | |
40801 | { | |
40802 | uint32_t srcreg = (opcode & 7); | |
40803 | OpcodeFamily = 33; CurrentInstrCycles = 16; | |
40804 | {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2270; } | |
40805 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
40806 | if ((srca & 1) != 0) { | |
40807 | last_fault_for_exception_3 = srca; | |
40808 | last_op_for_exception_3 = opcode; | |
40809 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
40810 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
40811 | goto endlabel2270; | |
40812 | } | |
40813 | {{ int16_t src = m68k_read_memory_16(srca); | |
40814 | m68k_areg(regs, srcreg) += 2; | |
40815 | regs.sr = src; | |
40816 | MakeFromSR(); | |
40817 | }}}}}m68k_incpc(2); | |
40818 | fill_prefetch_2 (); | |
40819 | endlabel2270: ; | |
40820 | return 16; | |
40821 | } | |
40822 | unsigned long CPUFUNC(op_46e0_5)(uint32_t opcode) /* MV2SR */ | |
40823 | { | |
40824 | uint32_t srcreg = (opcode & 7); | |
40825 | OpcodeFamily = 33; CurrentInstrCycles = 18; | |
40826 | {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2271; } | |
40827 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
40828 | if ((srca & 1) != 0) { | |
40829 | last_fault_for_exception_3 = srca; | |
40830 | last_op_for_exception_3 = opcode; | |
40831 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
40832 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
40833 | goto endlabel2271; | |
40834 | } | |
40835 | {{ int16_t src = m68k_read_memory_16(srca); | |
40836 | m68k_areg (regs, srcreg) = srca; | |
40837 | regs.sr = src; | |
40838 | MakeFromSR(); | |
40839 | }}}}}m68k_incpc(2); | |
40840 | fill_prefetch_2 (); | |
40841 | endlabel2271: ; | |
40842 | return 18; | |
40843 | } | |
40844 | unsigned long CPUFUNC(op_46e8_5)(uint32_t opcode) /* MV2SR */ | |
40845 | { | |
40846 | uint32_t srcreg = (opcode & 7); | |
40847 | OpcodeFamily = 33; CurrentInstrCycles = 20; | |
40848 | {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2272; } | |
40849 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
40850 | if ((srca & 1) != 0) { | |
40851 | last_fault_for_exception_3 = srca; | |
40852 | last_op_for_exception_3 = opcode; | |
40853 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
40854 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
40855 | goto endlabel2272; | |
40856 | } | |
40857 | {{ int16_t src = m68k_read_memory_16(srca); | |
40858 | regs.sr = src; | |
40859 | MakeFromSR(); | |
40860 | }}}}}m68k_incpc(4); | |
40861 | fill_prefetch_0 (); | |
40862 | endlabel2272: ; | |
40863 | return 20; | |
40864 | } | |
40865 | unsigned long CPUFUNC(op_46f0_5)(uint32_t opcode) /* MV2SR */ | |
40866 | { | |
40867 | uint32_t srcreg = (opcode & 7); | |
40868 | OpcodeFamily = 33; CurrentInstrCycles = 22; | |
40869 | {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2273; } | |
40870 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
40871 | BusCyclePenalty += 2; | |
40872 | if ((srca & 1) != 0) { | |
40873 | last_fault_for_exception_3 = srca; | |
40874 | last_op_for_exception_3 = opcode; | |
40875 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
40876 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
40877 | goto endlabel2273; | |
40878 | } | |
40879 | {{ int16_t src = m68k_read_memory_16(srca); | |
40880 | regs.sr = src; | |
40881 | MakeFromSR(); | |
40882 | }}}}}m68k_incpc(4); | |
40883 | fill_prefetch_0 (); | |
40884 | endlabel2273: ; | |
40885 | return 22; | |
40886 | } | |
40887 | unsigned long CPUFUNC(op_46f8_5)(uint32_t opcode) /* MV2SR */ | |
40888 | { | |
40889 | OpcodeFamily = 33; CurrentInstrCycles = 20; | |
40890 | {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2274; } | |
40891 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
40892 | if ((srca & 1) != 0) { | |
40893 | last_fault_for_exception_3 = srca; | |
40894 | last_op_for_exception_3 = opcode; | |
40895 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
40896 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
40897 | goto endlabel2274; | |
40898 | } | |
40899 | {{ int16_t src = m68k_read_memory_16(srca); | |
40900 | regs.sr = src; | |
40901 | MakeFromSR(); | |
40902 | }}}}}m68k_incpc(4); | |
40903 | fill_prefetch_0 (); | |
40904 | endlabel2274: ; | |
40905 | return 20; | |
40906 | } | |
40907 | unsigned long CPUFUNC(op_46f9_5)(uint32_t opcode) /* MV2SR */ | |
40908 | { | |
40909 | OpcodeFamily = 33; CurrentInstrCycles = 24; | |
40910 | {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2275; } | |
40911 | {{ uint32_t srca = get_ilong_prefetch(2); | |
40912 | if ((srca & 1) != 0) { | |
40913 | last_fault_for_exception_3 = srca; | |
40914 | last_op_for_exception_3 = opcode; | |
40915 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
40916 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
40917 | goto endlabel2275; | |
40918 | } | |
40919 | {{ int16_t src = m68k_read_memory_16(srca); | |
40920 | regs.sr = src; | |
40921 | MakeFromSR(); | |
40922 | }}}}}m68k_incpc(6); | |
40923 | fill_prefetch_0 (); | |
40924 | endlabel2275: ; | |
40925 | return 24; | |
40926 | } | |
40927 | unsigned long CPUFUNC(op_46fa_5)(uint32_t opcode) /* MV2SR */ | |
40928 | { | |
40929 | OpcodeFamily = 33; CurrentInstrCycles = 20; | |
40930 | {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2276; } | |
40931 | {{ uint32_t srca = m68k_getpc () + 2; | |
40932 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
40933 | if ((srca & 1) != 0) { | |
40934 | last_fault_for_exception_3 = srca; | |
40935 | last_op_for_exception_3 = opcode; | |
40936 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
40937 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
40938 | goto endlabel2276; | |
40939 | } | |
40940 | {{ int16_t src = m68k_read_memory_16(srca); | |
40941 | regs.sr = src; | |
40942 | MakeFromSR(); | |
40943 | }}}}}m68k_incpc(4); | |
40944 | fill_prefetch_0 (); | |
40945 | endlabel2276: ; | |
40946 | return 20; | |
40947 | } | |
40948 | unsigned long CPUFUNC(op_46fb_5)(uint32_t opcode) /* MV2SR */ | |
40949 | { | |
40950 | OpcodeFamily = 33; CurrentInstrCycles = 22; | |
40951 | {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2277; } | |
40952 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
40953 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
40954 | BusCyclePenalty += 2; | |
40955 | if ((srca & 1) != 0) { | |
40956 | last_fault_for_exception_3 = srca; | |
40957 | last_op_for_exception_3 = opcode; | |
40958 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
40959 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
40960 | goto endlabel2277; | |
40961 | } | |
40962 | {{ int16_t src = m68k_read_memory_16(srca); | |
40963 | regs.sr = src; | |
40964 | MakeFromSR(); | |
40965 | }}}}}m68k_incpc(4); | |
40966 | fill_prefetch_0 (); | |
40967 | endlabel2277: ; | |
40968 | return 22; | |
40969 | } | |
40970 | unsigned long CPUFUNC(op_46fc_5)(uint32_t opcode) /* MV2SR */ | |
40971 | { | |
40972 | OpcodeFamily = 33; CurrentInstrCycles = 16; | |
40973 | {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2278; } | |
40974 | {{ int16_t src = get_iword_prefetch(2); | |
40975 | regs.sr = src; | |
40976 | MakeFromSR(); | |
40977 | }}}m68k_incpc(4); | |
40978 | fill_prefetch_0 (); | |
40979 | endlabel2278: ; | |
40980 | return 16; | |
40981 | } | |
40982 | unsigned long CPUFUNC(op_4800_5)(uint32_t opcode) /* NBCD */ | |
40983 | { | |
40984 | uint32_t srcreg = (opcode & 7); | |
40985 | OpcodeFamily = 17; CurrentInstrCycles = 6; | |
40986 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
40987 | { uint16_t newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0); | |
40988 | uint16_t newv_hi = - (src & 0xF0); | |
40989 | uint16_t newv; | |
40990 | int cflg; | |
40991 | if (newv_lo > 9) { newv_lo -= 6; } | |
40992 | newv = newv_hi + newv_lo; cflg = (newv & 0x1F0) > 0x90; | |
40993 | if (cflg) newv -= 0x60; | |
40994 | SET_CFLG (cflg); | |
40995 | COPY_CARRY; | |
40996 | SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); | |
40997 | SET_NFLG (((int8_t)(newv)) < 0); | |
40998 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((newv) & 0xff); | |
40999 | }}}m68k_incpc(2); | |
41000 | fill_prefetch_2 (); | |
41001 | return 6; | |
41002 | } | |
41003 | unsigned long CPUFUNC(op_4810_5)(uint32_t opcode) /* NBCD */ | |
41004 | { | |
41005 | uint32_t srcreg = (opcode & 7); | |
41006 | OpcodeFamily = 17; CurrentInstrCycles = 12; | |
41007 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
41008 | { int8_t src = m68k_read_memory_8(srca); | |
41009 | { uint16_t newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0); | |
41010 | uint16_t newv_hi = - (src & 0xF0); | |
41011 | uint16_t newv; | |
41012 | int cflg; | |
41013 | if (newv_lo > 9) { newv_lo -= 6; } | |
41014 | newv = newv_hi + newv_lo; cflg = (newv & 0x1F0) > 0x90; | |
41015 | if (cflg) newv -= 0x60; | |
41016 | SET_CFLG (cflg); | |
41017 | COPY_CARRY; | |
41018 | SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); | |
41019 | SET_NFLG (((int8_t)(newv)) < 0); | |
41020 | m68k_incpc(2); | |
41021 | fill_prefetch_2 (); | |
41022 | m68k_write_memory_8(srca,newv); | |
41023 | }}}}return 12; | |
41024 | } | |
41025 | unsigned long CPUFUNC(op_4818_5)(uint32_t opcode) /* NBCD */ | |
41026 | { | |
41027 | uint32_t srcreg = (opcode & 7); | |
41028 | OpcodeFamily = 17; CurrentInstrCycles = 12; | |
41029 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
41030 | { int8_t src = m68k_read_memory_8(srca); | |
41031 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
41032 | { uint16_t newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0); | |
41033 | uint16_t newv_hi = - (src & 0xF0); | |
41034 | uint16_t newv; | |
41035 | int cflg; | |
41036 | if (newv_lo > 9) { newv_lo -= 6; } | |
41037 | newv = newv_hi + newv_lo; cflg = (newv & 0x1F0) > 0x90; | |
41038 | if (cflg) newv -= 0x60; | |
41039 | SET_CFLG (cflg); | |
41040 | COPY_CARRY; | |
41041 | SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); | |
41042 | SET_NFLG (((int8_t)(newv)) < 0); | |
41043 | m68k_incpc(2); | |
41044 | fill_prefetch_2 (); | |
41045 | m68k_write_memory_8(srca,newv); | |
41046 | }}}}return 12; | |
41047 | } | |
41048 | unsigned long CPUFUNC(op_4820_5)(uint32_t opcode) /* NBCD */ | |
41049 | { | |
41050 | uint32_t srcreg = (opcode & 7); | |
41051 | OpcodeFamily = 17; CurrentInstrCycles = 14; | |
41052 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
41053 | { int8_t src = m68k_read_memory_8(srca); | |
41054 | m68k_areg (regs, srcreg) = srca; | |
41055 | { uint16_t newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0); | |
41056 | uint16_t newv_hi = - (src & 0xF0); | |
41057 | uint16_t newv; | |
41058 | int cflg; | |
41059 | if (newv_lo > 9) { newv_lo -= 6; } | |
41060 | newv = newv_hi + newv_lo; cflg = (newv & 0x1F0) > 0x90; | |
41061 | if (cflg) newv -= 0x60; | |
41062 | SET_CFLG (cflg); | |
41063 | COPY_CARRY; | |
41064 | SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); | |
41065 | SET_NFLG (((int8_t)(newv)) < 0); | |
41066 | m68k_incpc(2); | |
41067 | fill_prefetch_2 (); | |
41068 | m68k_write_memory_8(srca,newv); | |
41069 | }}}}return 14; | |
41070 | } | |
41071 | unsigned long CPUFUNC(op_4828_5)(uint32_t opcode) /* NBCD */ | |
41072 | { | |
41073 | uint32_t srcreg = (opcode & 7); | |
41074 | OpcodeFamily = 17; CurrentInstrCycles = 16; | |
41075 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
41076 | { int8_t src = m68k_read_memory_8(srca); | |
41077 | { uint16_t newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0); | |
41078 | uint16_t newv_hi = - (src & 0xF0); | |
41079 | uint16_t newv; | |
41080 | int cflg; | |
41081 | if (newv_lo > 9) { newv_lo -= 6; } | |
41082 | newv = newv_hi + newv_lo; cflg = (newv & 0x1F0) > 0x90; | |
41083 | if (cflg) newv -= 0x60; | |
41084 | SET_CFLG (cflg); | |
41085 | COPY_CARRY; | |
41086 | SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); | |
41087 | SET_NFLG (((int8_t)(newv)) < 0); | |
41088 | m68k_incpc(4); | |
41089 | fill_prefetch_0 (); | |
41090 | m68k_write_memory_8(srca,newv); | |
41091 | }}}}return 16; | |
41092 | } | |
41093 | unsigned long CPUFUNC(op_4830_5)(uint32_t opcode) /* NBCD */ | |
41094 | { | |
41095 | uint32_t srcreg = (opcode & 7); | |
41096 | OpcodeFamily = 17; CurrentInstrCycles = 18; | |
41097 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
41098 | BusCyclePenalty += 2; | |
41099 | { int8_t src = m68k_read_memory_8(srca); | |
41100 | { uint16_t newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0); | |
41101 | uint16_t newv_hi = - (src & 0xF0); | |
41102 | uint16_t newv; | |
41103 | int cflg; | |
41104 | if (newv_lo > 9) { newv_lo -= 6; } | |
41105 | newv = newv_hi + newv_lo; cflg = (newv & 0x1F0) > 0x90; | |
41106 | if (cflg) newv -= 0x60; | |
41107 | SET_CFLG (cflg); | |
41108 | COPY_CARRY; | |
41109 | SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); | |
41110 | SET_NFLG (((int8_t)(newv)) < 0); | |
41111 | m68k_incpc(4); | |
41112 | fill_prefetch_0 (); | |
41113 | m68k_write_memory_8(srca,newv); | |
41114 | }}}}return 18; | |
41115 | } | |
41116 | unsigned long CPUFUNC(op_4838_5)(uint32_t opcode) /* NBCD */ | |
41117 | { | |
41118 | OpcodeFamily = 17; CurrentInstrCycles = 16; | |
41119 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
41120 | { int8_t src = m68k_read_memory_8(srca); | |
41121 | { uint16_t newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0); | |
41122 | uint16_t newv_hi = - (src & 0xF0); | |
41123 | uint16_t newv; | |
41124 | int cflg; | |
41125 | if (newv_lo > 9) { newv_lo -= 6; } | |
41126 | newv = newv_hi + newv_lo; cflg = (newv & 0x1F0) > 0x90; | |
41127 | if (cflg) newv -= 0x60; | |
41128 | SET_CFLG (cflg); | |
41129 | COPY_CARRY; | |
41130 | SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); | |
41131 | SET_NFLG (((int8_t)(newv)) < 0); | |
41132 | m68k_incpc(4); | |
41133 | fill_prefetch_0 (); | |
41134 | m68k_write_memory_8(srca,newv); | |
41135 | }}}}return 16; | |
41136 | } | |
41137 | unsigned long CPUFUNC(op_4839_5)(uint32_t opcode) /* NBCD */ | |
41138 | { | |
41139 | OpcodeFamily = 17; CurrentInstrCycles = 20; | |
41140 | {{ uint32_t srca = get_ilong_prefetch(2); | |
41141 | { int8_t src = m68k_read_memory_8(srca); | |
41142 | { uint16_t newv_lo = - (src & 0xF) - (GET_XFLG ? 1 : 0); | |
41143 | uint16_t newv_hi = - (src & 0xF0); | |
41144 | uint16_t newv; | |
41145 | int cflg; | |
41146 | if (newv_lo > 9) { newv_lo -= 6; } | |
41147 | newv = newv_hi + newv_lo; cflg = (newv & 0x1F0) > 0x90; | |
41148 | if (cflg) newv -= 0x60; | |
41149 | SET_CFLG (cflg); | |
41150 | COPY_CARRY; | |
41151 | SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); | |
41152 | SET_NFLG (((int8_t)(newv)) < 0); | |
41153 | m68k_incpc(6); | |
41154 | fill_prefetch_0 (); | |
41155 | m68k_write_memory_8(srca,newv); | |
41156 | }}}}return 20; | |
41157 | } | |
41158 | unsigned long CPUFUNC(op_4840_5)(uint32_t opcode) /* SWAP */ | |
41159 | { | |
41160 | uint32_t srcreg = (opcode & 7); | |
41161 | OpcodeFamily = 34; CurrentInstrCycles = 4; | |
41162 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
41163 | { uint32_t dst = ((src >> 16)&0xFFFF) | ((src&0xFFFF)<<16); | |
41164 | CLEAR_CZNV; | |
41165 | SET_ZFLG (((int32_t)(dst)) == 0); | |
41166 | SET_NFLG (((int32_t)(dst)) < 0); | |
41167 | m68k_dreg(regs, srcreg) = (dst); | |
41168 | }}}m68k_incpc(2); | |
41169 | fill_prefetch_2 (); | |
41170 | return 4; | |
41171 | } | |
41172 | unsigned long CPUFUNC(op_4850_5)(uint32_t opcode) /* PEA */ | |
41173 | { | |
41174 | uint32_t srcreg = (opcode & 7); | |
41175 | OpcodeFamily = 57; CurrentInstrCycles = 12; | |
41176 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
41177 | { uint32_t dsta = m68k_areg(regs, 7) - 4; | |
41178 | if ((dsta & 1) != 0) { | |
41179 | last_fault_for_exception_3 = dsta; | |
41180 | last_op_for_exception_3 = opcode; | |
41181 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
41182 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
41183 | goto endlabel2288; | |
41184 | } | |
41185 | { m68k_areg (regs, 7) = dsta; | |
41186 | m68k_incpc(2); | |
41187 | fill_prefetch_2 (); | |
41188 | m68k_write_memory_32(dsta,srca); | |
41189 | }}}}endlabel2288: ; | |
41190 | return 12; | |
41191 | } | |
41192 | unsigned long CPUFUNC(op_4868_5)(uint32_t opcode) /* PEA */ | |
41193 | { | |
41194 | uint32_t srcreg = (opcode & 7); | |
41195 | OpcodeFamily = 57; CurrentInstrCycles = 16; | |
41196 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
41197 | { uint32_t dsta = m68k_areg(regs, 7) - 4; | |
41198 | if ((dsta & 1) != 0) { | |
41199 | last_fault_for_exception_3 = dsta; | |
41200 | last_op_for_exception_3 = opcode; | |
41201 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
41202 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
41203 | goto endlabel2289; | |
41204 | } | |
41205 | { m68k_areg (regs, 7) = dsta; | |
41206 | m68k_incpc(4); | |
41207 | fill_prefetch_0 (); | |
41208 | m68k_write_memory_32(dsta,srca); | |
41209 | }}}}endlabel2289: ; | |
41210 | return 16; | |
41211 | } | |
41212 | unsigned long CPUFUNC(op_4870_5)(uint32_t opcode) /* PEA */ | |
41213 | { | |
41214 | uint32_t srcreg = (opcode & 7); | |
41215 | OpcodeFamily = 57; CurrentInstrCycles = 22; | |
41216 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
41217 | BusCyclePenalty += 2; | |
41218 | { uint32_t dsta = m68k_areg(regs, 7) - 4; | |
41219 | if ((dsta & 1) != 0) { | |
41220 | last_fault_for_exception_3 = dsta; | |
41221 | last_op_for_exception_3 = opcode; | |
41222 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
41223 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
41224 | goto endlabel2290; | |
41225 | } | |
41226 | { m68k_areg (regs, 7) = dsta; | |
41227 | m68k_incpc(4); | |
41228 | fill_prefetch_0 (); | |
41229 | m68k_write_memory_32(dsta,srca); | |
41230 | }}}}endlabel2290: ; | |
41231 | return 22; | |
41232 | } | |
41233 | unsigned long CPUFUNC(op_4878_5)(uint32_t opcode) /* PEA */ | |
41234 | { | |
41235 | OpcodeFamily = 57; CurrentInstrCycles = 16; | |
41236 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
41237 | { uint32_t dsta = m68k_areg(regs, 7) - 4; | |
41238 | if ((dsta & 1) != 0) { | |
41239 | last_fault_for_exception_3 = dsta; | |
41240 | last_op_for_exception_3 = opcode; | |
41241 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
41242 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
41243 | goto endlabel2291; | |
41244 | } | |
41245 | { m68k_areg (regs, 7) = dsta; | |
41246 | m68k_incpc(4); | |
41247 | fill_prefetch_0 (); | |
41248 | m68k_write_memory_32(dsta,srca); | |
41249 | }}}}endlabel2291: ; | |
41250 | return 16; | |
41251 | } | |
41252 | unsigned long CPUFUNC(op_4879_5)(uint32_t opcode) /* PEA */ | |
41253 | { | |
41254 | OpcodeFamily = 57; CurrentInstrCycles = 20; | |
41255 | {{ uint32_t srca = get_ilong_prefetch(2); | |
41256 | { uint32_t dsta = m68k_areg(regs, 7) - 4; | |
41257 | if ((dsta & 1) != 0) { | |
41258 | last_fault_for_exception_3 = dsta; | |
41259 | last_op_for_exception_3 = opcode; | |
41260 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
41261 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
41262 | goto endlabel2292; | |
41263 | } | |
41264 | { m68k_areg (regs, 7) = dsta; | |
41265 | m68k_incpc(6); | |
41266 | fill_prefetch_0 (); | |
41267 | m68k_write_memory_32(dsta,srca); | |
41268 | }}}}endlabel2292: ; | |
41269 | return 20; | |
41270 | } | |
41271 | unsigned long CPUFUNC(op_487a_5)(uint32_t opcode) /* PEA */ | |
41272 | { | |
41273 | OpcodeFamily = 57; CurrentInstrCycles = 16; | |
41274 | {{ uint32_t srca = m68k_getpc () + 2; | |
41275 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
41276 | { uint32_t dsta = m68k_areg(regs, 7) - 4; | |
41277 | if ((dsta & 1) != 0) { | |
41278 | last_fault_for_exception_3 = dsta; | |
41279 | last_op_for_exception_3 = opcode; | |
41280 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
41281 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
41282 | goto endlabel2293; | |
41283 | } | |
41284 | { m68k_areg (regs, 7) = dsta; | |
41285 | m68k_incpc(4); | |
41286 | fill_prefetch_0 (); | |
41287 | m68k_write_memory_32(dsta,srca); | |
41288 | }}}}endlabel2293: ; | |
41289 | return 16; | |
41290 | } | |
41291 | unsigned long CPUFUNC(op_487b_5)(uint32_t opcode) /* PEA */ | |
41292 | { | |
41293 | OpcodeFamily = 57; CurrentInstrCycles = 22; | |
41294 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
41295 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
41296 | BusCyclePenalty += 2; | |
41297 | { uint32_t dsta = m68k_areg(regs, 7) - 4; | |
41298 | if ((dsta & 1) != 0) { | |
41299 | last_fault_for_exception_3 = dsta; | |
41300 | last_op_for_exception_3 = opcode; | |
41301 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
41302 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
41303 | goto endlabel2294; | |
41304 | } | |
41305 | { m68k_areg (regs, 7) = dsta; | |
41306 | m68k_incpc(4); | |
41307 | fill_prefetch_0 (); | |
41308 | m68k_write_memory_32(dsta,srca); | |
41309 | }}}}endlabel2294: ; | |
41310 | return 22; | |
41311 | } | |
41312 | unsigned long CPUFUNC(op_4880_5)(uint32_t opcode) /* EXT */ | |
41313 | { | |
41314 | uint32_t srcreg = (opcode & 7); | |
41315 | OpcodeFamily = 36; CurrentInstrCycles = 4; | |
41316 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
41317 | { uint16_t dst = (int16_t)(int8_t)src; | |
41318 | CLEAR_CZNV; | |
41319 | SET_ZFLG (((int16_t)(dst)) == 0); | |
41320 | SET_NFLG (((int16_t)(dst)) < 0); | |
41321 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | ((dst) & 0xffff); | |
41322 | }}}m68k_incpc(2); | |
41323 | fill_prefetch_2 (); | |
41324 | return 4; | |
41325 | } | |
41326 | unsigned long CPUFUNC(op_4890_5)(uint32_t opcode) /* MVMLE */ | |
41327 | { | |
41328 | uint32_t dstreg = opcode & 7; | |
41329 | unsigned int retcycles = 0; | |
41330 | OpcodeFamily = 38; CurrentInstrCycles = 8; | |
41331 | { uint16_t mask = get_iword_prefetch(2); | |
41332 | retcycles = 0; | |
41333 | { uint32_t srca = m68k_areg(regs, dstreg); | |
41334 | if ((srca & 1) != 0) { | |
41335 | last_fault_for_exception_3 = srca; | |
41336 | last_op_for_exception_3 = opcode; | |
41337 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
41338 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
41339 | goto endlabel2296; | |
41340 | } | |
41341 | {m68k_incpc(4); | |
41342 | fill_prefetch_0 (); | |
41343 | { uint16_t dmask = mask & 0xff, amask = (mask >> 8) & 0xff; | |
41344 | while (dmask) { m68k_write_memory_16(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; retcycles+=4; } | |
41345 | while (amask) { m68k_write_memory_16(srca, m68k_areg(regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; retcycles+=4; } | |
41346 | }}}}endlabel2296: ; | |
41347 | return (8+retcycles); | |
41348 | } | |
41349 | unsigned long CPUFUNC(op_48a0_5)(uint32_t opcode) /* MVMLE */ | |
41350 | { | |
41351 | uint32_t dstreg = opcode & 7; | |
41352 | unsigned int retcycles = 0; | |
41353 | OpcodeFamily = 38; CurrentInstrCycles = 8; | |
41354 | { uint16_t mask = get_iword_prefetch(2); | |
41355 | retcycles = 0; | |
41356 | { uint32_t srca = m68k_areg(regs, dstreg) - 0; | |
41357 | if ((srca & 1) != 0) { | |
41358 | last_fault_for_exception_3 = srca; | |
41359 | last_op_for_exception_3 = opcode; | |
41360 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
41361 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
41362 | goto endlabel2297; | |
41363 | } | |
41364 | {m68k_incpc(4); | |
41365 | fill_prefetch_0 (); | |
41366 | { uint16_t amask = mask & 0xff, dmask = (mask >> 8) & 0xff; | |
41367 | while (amask) { srca -= 2; m68k_write_memory_16(srca, m68k_areg(regs, movem_index2[amask])); amask = movem_next[amask]; retcycles+=4; } | |
41368 | while (dmask) { srca -= 2; m68k_write_memory_16(srca, m68k_dreg(regs, movem_index2[dmask])); dmask = movem_next[dmask]; retcycles+=4; } | |
41369 | m68k_areg(regs, dstreg) = srca; | |
41370 | }}}}endlabel2297: ; | |
41371 | return (8+retcycles); | |
41372 | } | |
41373 | unsigned long CPUFUNC(op_48a8_5)(uint32_t opcode) /* MVMLE */ | |
41374 | { | |
41375 | uint32_t dstreg = opcode & 7; | |
41376 | unsigned int retcycles = 0; | |
41377 | OpcodeFamily = 38; CurrentInstrCycles = 12; | |
41378 | { uint16_t mask = get_iword_prefetch(2); | |
41379 | retcycles = 0; | |
41380 | { uint32_t srca = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); | |
41381 | if ((srca & 1) != 0) { | |
41382 | last_fault_for_exception_3 = srca; | |
41383 | last_op_for_exception_3 = opcode; | |
41384 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
41385 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
41386 | goto endlabel2298; | |
41387 | } | |
41388 | {m68k_incpc(6); | |
41389 | fill_prefetch_0 (); | |
41390 | { uint16_t dmask = mask & 0xff, amask = (mask >> 8) & 0xff; | |
41391 | while (dmask) { m68k_write_memory_16(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; retcycles+=4; } | |
41392 | while (amask) { m68k_write_memory_16(srca, m68k_areg(regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; retcycles+=4; } | |
41393 | }}}}endlabel2298: ; | |
41394 | return (12+retcycles); | |
41395 | } | |
41396 | unsigned long CPUFUNC(op_48b0_5)(uint32_t opcode) /* MVMLE */ | |
41397 | { | |
41398 | uint32_t dstreg = opcode & 7; | |
41399 | unsigned int retcycles = 0; | |
41400 | OpcodeFamily = 38; CurrentInstrCycles = 14; | |
41401 | { uint16_t mask = get_iword_prefetch(2); | |
41402 | retcycles = 0; | |
41403 | { uint32_t srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); | |
41404 | BusCyclePenalty += 2; | |
41405 | if ((srca & 1) != 0) { | |
41406 | last_fault_for_exception_3 = srca; | |
41407 | last_op_for_exception_3 = opcode; | |
41408 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
41409 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
41410 | goto endlabel2299; | |
41411 | } | |
41412 | {m68k_incpc(6); | |
41413 | fill_prefetch_0 (); | |
41414 | { uint16_t dmask = mask & 0xff, amask = (mask >> 8) & 0xff; | |
41415 | while (dmask) { m68k_write_memory_16(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; retcycles+=4; } | |
41416 | while (amask) { m68k_write_memory_16(srca, m68k_areg(regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; retcycles+=4; } | |
41417 | }}}}endlabel2299: ; | |
41418 | return (14+retcycles); | |
41419 | } | |
41420 | unsigned long CPUFUNC(op_48b8_5)(uint32_t opcode) /* MVMLE */ | |
41421 | { | |
41422 | unsigned int retcycles = 0; | |
41423 | OpcodeFamily = 38; CurrentInstrCycles = 12; | |
41424 | { uint16_t mask = get_iword_prefetch(2); | |
41425 | retcycles = 0; | |
41426 | { uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(4); | |
41427 | if ((srca & 1) != 0) { | |
41428 | last_fault_for_exception_3 = srca; | |
41429 | last_op_for_exception_3 = opcode; | |
41430 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
41431 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
41432 | goto endlabel2300; | |
41433 | } | |
41434 | {m68k_incpc(6); | |
41435 | fill_prefetch_0 (); | |
41436 | { uint16_t dmask = mask & 0xff, amask = (mask >> 8) & 0xff; | |
41437 | while (dmask) { m68k_write_memory_16(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; retcycles+=4; } | |
41438 | while (amask) { m68k_write_memory_16(srca, m68k_areg(regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; retcycles+=4; } | |
41439 | }}}}endlabel2300: ; | |
41440 | return (12+retcycles); | |
41441 | } | |
41442 | unsigned long CPUFUNC(op_48b9_5)(uint32_t opcode) /* MVMLE */ | |
41443 | { | |
41444 | unsigned int retcycles = 0; | |
41445 | OpcodeFamily = 38; CurrentInstrCycles = 16; | |
41446 | { uint16_t mask = get_iword_prefetch(2); | |
41447 | retcycles = 0; | |
41448 | { uint32_t srca = get_ilong_prefetch(4); | |
41449 | if ((srca & 1) != 0) { | |
41450 | last_fault_for_exception_3 = srca; | |
41451 | last_op_for_exception_3 = opcode; | |
41452 | last_addr_for_exception_3 = m68k_getpc() + 8; | |
41453 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
41454 | goto endlabel2301; | |
41455 | } | |
41456 | {m68k_incpc(8); | |
41457 | fill_prefetch_0 (); | |
41458 | { uint16_t dmask = mask & 0xff, amask = (mask >> 8) & 0xff; | |
41459 | while (dmask) { m68k_write_memory_16(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 2; dmask = movem_next[dmask]; retcycles+=4; } | |
41460 | while (amask) { m68k_write_memory_16(srca, m68k_areg(regs, movem_index1[amask])); srca += 2; amask = movem_next[amask]; retcycles+=4; } | |
41461 | }}}}endlabel2301: ; | |
41462 | return (16+retcycles); | |
41463 | } | |
41464 | unsigned long CPUFUNC(op_48c0_5)(uint32_t opcode) /* EXT */ | |
41465 | { | |
41466 | uint32_t srcreg = (opcode & 7); | |
41467 | OpcodeFamily = 36; CurrentInstrCycles = 4; | |
41468 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
41469 | { uint32_t dst = (int32_t)(int16_t)src; | |
41470 | CLEAR_CZNV; | |
41471 | SET_ZFLG (((int32_t)(dst)) == 0); | |
41472 | SET_NFLG (((int32_t)(dst)) < 0); | |
41473 | m68k_dreg(regs, srcreg) = (dst); | |
41474 | }}}m68k_incpc(2); | |
41475 | fill_prefetch_2 (); | |
41476 | return 4; | |
41477 | } | |
41478 | unsigned long CPUFUNC(op_48d0_5)(uint32_t opcode) /* MVMLE */ | |
41479 | { | |
41480 | uint32_t dstreg = opcode & 7; | |
41481 | unsigned int retcycles = 0; | |
41482 | OpcodeFamily = 38; CurrentInstrCycles = 8; | |
41483 | { uint16_t mask = get_iword_prefetch(2); | |
41484 | retcycles = 0; | |
41485 | { uint32_t srca = m68k_areg(regs, dstreg); | |
41486 | if ((srca & 1) != 0) { | |
41487 | last_fault_for_exception_3 = srca; | |
41488 | last_op_for_exception_3 = opcode; | |
41489 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
41490 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
41491 | goto endlabel2303; | |
41492 | } | |
41493 | {m68k_incpc(4); | |
41494 | fill_prefetch_0 (); | |
41495 | { uint16_t dmask = mask & 0xff, amask = (mask >> 8) & 0xff; | |
41496 | while (dmask) { m68k_write_memory_32(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; retcycles+=8; } | |
41497 | while (amask) { m68k_write_memory_32(srca, m68k_areg(regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; retcycles+=8; } | |
41498 | }}}}endlabel2303: ; | |
41499 | return (8+retcycles); | |
41500 | } | |
41501 | unsigned long CPUFUNC(op_48e0_5)(uint32_t opcode) /* MVMLE */ | |
41502 | { | |
41503 | uint32_t dstreg = opcode & 7; | |
41504 | unsigned int retcycles = 0; | |
41505 | OpcodeFamily = 38; CurrentInstrCycles = 8; | |
41506 | { uint16_t mask = get_iword_prefetch(2); | |
41507 | retcycles = 0; | |
41508 | { uint32_t srca = m68k_areg(regs, dstreg) - 0; | |
41509 | if ((srca & 1) != 0) { | |
41510 | last_fault_for_exception_3 = srca; | |
41511 | last_op_for_exception_3 = opcode; | |
41512 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
41513 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
41514 | goto endlabel2304; | |
41515 | } | |
41516 | {m68k_incpc(4); | |
41517 | fill_prefetch_0 (); | |
41518 | { uint16_t amask = mask & 0xff, dmask = (mask >> 8) & 0xff; | |
41519 | while (amask) { srca -= 4; m68k_write_memory_32(srca, m68k_areg(regs, movem_index2[amask])); amask = movem_next[amask]; retcycles+=8; } | |
41520 | while (dmask) { srca -= 4; m68k_write_memory_32(srca, m68k_dreg(regs, movem_index2[dmask])); dmask = movem_next[dmask]; retcycles+=8; } | |
41521 | m68k_areg(regs, dstreg) = srca; | |
41522 | }}}}endlabel2304: ; | |
41523 | return (8+retcycles); | |
41524 | } | |
41525 | unsigned long CPUFUNC(op_48e8_5)(uint32_t opcode) /* MVMLE */ | |
41526 | { | |
41527 | uint32_t dstreg = opcode & 7; | |
41528 | unsigned int retcycles = 0; | |
41529 | OpcodeFamily = 38; CurrentInstrCycles = 12; | |
41530 | { uint16_t mask = get_iword_prefetch(2); | |
41531 | retcycles = 0; | |
41532 | { uint32_t srca = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); | |
41533 | if ((srca & 1) != 0) { | |
41534 | last_fault_for_exception_3 = srca; | |
41535 | last_op_for_exception_3 = opcode; | |
41536 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
41537 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
41538 | goto endlabel2305; | |
41539 | } | |
41540 | {m68k_incpc(6); | |
41541 | fill_prefetch_0 (); | |
41542 | { uint16_t dmask = mask & 0xff, amask = (mask >> 8) & 0xff; | |
41543 | while (dmask) { m68k_write_memory_32(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; retcycles+=8; } | |
41544 | while (amask) { m68k_write_memory_32(srca, m68k_areg(regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; retcycles+=8; } | |
41545 | }}}}endlabel2305: ; | |
41546 | return (12+retcycles); | |
41547 | } | |
41548 | unsigned long CPUFUNC(op_48f0_5)(uint32_t opcode) /* MVMLE */ | |
41549 | { | |
41550 | uint32_t dstreg = opcode & 7; | |
41551 | unsigned int retcycles = 0; | |
41552 | OpcodeFamily = 38; CurrentInstrCycles = 14; | |
41553 | { uint16_t mask = get_iword_prefetch(2); | |
41554 | retcycles = 0; | |
41555 | { uint32_t srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); | |
41556 | BusCyclePenalty += 2; | |
41557 | if ((srca & 1) != 0) { | |
41558 | last_fault_for_exception_3 = srca; | |
41559 | last_op_for_exception_3 = opcode; | |
41560 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
41561 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
41562 | goto endlabel2306; | |
41563 | } | |
41564 | {m68k_incpc(6); | |
41565 | fill_prefetch_0 (); | |
41566 | { uint16_t dmask = mask & 0xff, amask = (mask >> 8) & 0xff; | |
41567 | while (dmask) { m68k_write_memory_32(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; retcycles+=8; } | |
41568 | while (amask) { m68k_write_memory_32(srca, m68k_areg(regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; retcycles+=8; } | |
41569 | }}}}endlabel2306: ; | |
41570 | return (14+retcycles); | |
41571 | } | |
41572 | unsigned long CPUFUNC(op_48f8_5)(uint32_t opcode) /* MVMLE */ | |
41573 | { | |
41574 | unsigned int retcycles = 0; | |
41575 | OpcodeFamily = 38; CurrentInstrCycles = 12; | |
41576 | { uint16_t mask = get_iword_prefetch(2); | |
41577 | retcycles = 0; | |
41578 | { uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(4); | |
41579 | if ((srca & 1) != 0) { | |
41580 | last_fault_for_exception_3 = srca; | |
41581 | last_op_for_exception_3 = opcode; | |
41582 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
41583 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
41584 | goto endlabel2307; | |
41585 | } | |
41586 | {m68k_incpc(6); | |
41587 | fill_prefetch_0 (); | |
41588 | { uint16_t dmask = mask & 0xff, amask = (mask >> 8) & 0xff; | |
41589 | while (dmask) { m68k_write_memory_32(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; retcycles+=8; } | |
41590 | while (amask) { m68k_write_memory_32(srca, m68k_areg(regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; retcycles+=8; } | |
41591 | }}}}endlabel2307: ; | |
41592 | return (12+retcycles); | |
41593 | } | |
41594 | unsigned long CPUFUNC(op_48f9_5)(uint32_t opcode) /* MVMLE */ | |
41595 | { | |
41596 | unsigned int retcycles = 0; | |
41597 | OpcodeFamily = 38; CurrentInstrCycles = 16; | |
41598 | { uint16_t mask = get_iword_prefetch(2); | |
41599 | retcycles = 0; | |
41600 | { uint32_t srca = get_ilong_prefetch(4); | |
41601 | if ((srca & 1) != 0) { | |
41602 | last_fault_for_exception_3 = srca; | |
41603 | last_op_for_exception_3 = opcode; | |
41604 | last_addr_for_exception_3 = m68k_getpc() + 8; | |
41605 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
41606 | goto endlabel2308; | |
41607 | } | |
41608 | {m68k_incpc(8); | |
41609 | fill_prefetch_0 (); | |
41610 | { uint16_t dmask = mask & 0xff, amask = (mask >> 8) & 0xff; | |
41611 | while (dmask) { m68k_write_memory_32(srca, m68k_dreg(regs, movem_index1[dmask])); srca += 4; dmask = movem_next[dmask]; retcycles+=8; } | |
41612 | while (amask) { m68k_write_memory_32(srca, m68k_areg(regs, movem_index1[amask])); srca += 4; amask = movem_next[amask]; retcycles+=8; } | |
41613 | }}}}endlabel2308: ; | |
41614 | return (16+retcycles); | |
41615 | } | |
41616 | unsigned long CPUFUNC(op_4a00_5)(uint32_t opcode) /* TST */ | |
41617 | { | |
41618 | uint32_t srcreg = (opcode & 7); | |
41619 | OpcodeFamily = 20; CurrentInstrCycles = 4; | |
41620 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
41621 | CLEAR_CZNV; | |
41622 | SET_ZFLG (((int8_t)(src)) == 0); | |
41623 | SET_NFLG (((int8_t)(src)) < 0); | |
41624 | }}m68k_incpc(2); | |
41625 | fill_prefetch_2 (); | |
41626 | return 4; | |
41627 | } | |
41628 | unsigned long CPUFUNC(op_4a10_5)(uint32_t opcode) /* TST */ | |
41629 | { | |
41630 | uint32_t srcreg = (opcode & 7); | |
41631 | OpcodeFamily = 20; CurrentInstrCycles = 8; | |
41632 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
41633 | { int8_t src = m68k_read_memory_8(srca); | |
41634 | CLEAR_CZNV; | |
41635 | SET_ZFLG (((int8_t)(src)) == 0); | |
41636 | SET_NFLG (((int8_t)(src)) < 0); | |
41637 | }}}m68k_incpc(2); | |
41638 | fill_prefetch_2 (); | |
41639 | return 8; | |
41640 | } | |
41641 | unsigned long CPUFUNC(op_4a18_5)(uint32_t opcode) /* TST */ | |
41642 | { | |
41643 | uint32_t srcreg = (opcode & 7); | |
41644 | OpcodeFamily = 20; CurrentInstrCycles = 8; | |
41645 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
41646 | { int8_t src = m68k_read_memory_8(srca); | |
41647 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
41648 | CLEAR_CZNV; | |
41649 | SET_ZFLG (((int8_t)(src)) == 0); | |
41650 | SET_NFLG (((int8_t)(src)) < 0); | |
41651 | }}}m68k_incpc(2); | |
41652 | fill_prefetch_2 (); | |
41653 | return 8; | |
41654 | } | |
41655 | unsigned long CPUFUNC(op_4a20_5)(uint32_t opcode) /* TST */ | |
41656 | { | |
41657 | uint32_t srcreg = (opcode & 7); | |
41658 | OpcodeFamily = 20; CurrentInstrCycles = 10; | |
41659 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
41660 | { int8_t src = m68k_read_memory_8(srca); | |
41661 | m68k_areg (regs, srcreg) = srca; | |
41662 | CLEAR_CZNV; | |
41663 | SET_ZFLG (((int8_t)(src)) == 0); | |
41664 | SET_NFLG (((int8_t)(src)) < 0); | |
41665 | }}}m68k_incpc(2); | |
41666 | fill_prefetch_2 (); | |
41667 | return 10; | |
41668 | } | |
41669 | unsigned long CPUFUNC(op_4a28_5)(uint32_t opcode) /* TST */ | |
41670 | { | |
41671 | uint32_t srcreg = (opcode & 7); | |
41672 | OpcodeFamily = 20; CurrentInstrCycles = 12; | |
41673 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
41674 | { int8_t src = m68k_read_memory_8(srca); | |
41675 | CLEAR_CZNV; | |
41676 | SET_ZFLG (((int8_t)(src)) == 0); | |
41677 | SET_NFLG (((int8_t)(src)) < 0); | |
41678 | }}}m68k_incpc(4); | |
41679 | fill_prefetch_0 (); | |
41680 | return 12; | |
41681 | } | |
41682 | unsigned long CPUFUNC(op_4a30_5)(uint32_t opcode) /* TST */ | |
41683 | { | |
41684 | uint32_t srcreg = (opcode & 7); | |
41685 | OpcodeFamily = 20; CurrentInstrCycles = 14; | |
41686 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
41687 | BusCyclePenalty += 2; | |
41688 | { int8_t src = m68k_read_memory_8(srca); | |
41689 | CLEAR_CZNV; | |
41690 | SET_ZFLG (((int8_t)(src)) == 0); | |
41691 | SET_NFLG (((int8_t)(src)) < 0); | |
41692 | }}}m68k_incpc(4); | |
41693 | fill_prefetch_0 (); | |
41694 | return 14; | |
41695 | } | |
41696 | unsigned long CPUFUNC(op_4a38_5)(uint32_t opcode) /* TST */ | |
41697 | { | |
41698 | OpcodeFamily = 20; CurrentInstrCycles = 12; | |
41699 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
41700 | { int8_t src = m68k_read_memory_8(srca); | |
41701 | CLEAR_CZNV; | |
41702 | SET_ZFLG (((int8_t)(src)) == 0); | |
41703 | SET_NFLG (((int8_t)(src)) < 0); | |
41704 | }}}m68k_incpc(4); | |
41705 | fill_prefetch_0 (); | |
41706 | return 12; | |
41707 | } | |
41708 | unsigned long CPUFUNC(op_4a39_5)(uint32_t opcode) /* TST */ | |
41709 | { | |
41710 | OpcodeFamily = 20; CurrentInstrCycles = 16; | |
41711 | {{ uint32_t srca = get_ilong_prefetch(2); | |
41712 | { int8_t src = m68k_read_memory_8(srca); | |
41713 | CLEAR_CZNV; | |
41714 | SET_ZFLG (((int8_t)(src)) == 0); | |
41715 | SET_NFLG (((int8_t)(src)) < 0); | |
41716 | }}}m68k_incpc(6); | |
41717 | fill_prefetch_0 (); | |
41718 | return 16; | |
41719 | } | |
41720 | unsigned long CPUFUNC(op_4a3a_5)(uint32_t opcode) /* TST */ | |
41721 | { | |
41722 | OpcodeFamily = 20; CurrentInstrCycles = 12; | |
41723 | {{ uint32_t srca = m68k_getpc () + 2; | |
41724 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
41725 | { int8_t src = m68k_read_memory_8(srca); | |
41726 | CLEAR_CZNV; | |
41727 | SET_ZFLG (((int8_t)(src)) == 0); | |
41728 | SET_NFLG (((int8_t)(src)) < 0); | |
41729 | }}}m68k_incpc(4); | |
41730 | fill_prefetch_0 (); | |
41731 | return 12; | |
41732 | } | |
41733 | unsigned long CPUFUNC(op_4a3b_5)(uint32_t opcode) /* TST */ | |
41734 | { | |
41735 | OpcodeFamily = 20; CurrentInstrCycles = 14; | |
41736 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
41737 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
41738 | BusCyclePenalty += 2; | |
41739 | { int8_t src = m68k_read_memory_8(srca); | |
41740 | CLEAR_CZNV; | |
41741 | SET_ZFLG (((int8_t)(src)) == 0); | |
41742 | SET_NFLG (((int8_t)(src)) < 0); | |
41743 | }}}m68k_incpc(4); | |
41744 | fill_prefetch_0 (); | |
41745 | return 14; | |
41746 | } | |
41747 | unsigned long CPUFUNC(op_4a3c_5)(uint32_t opcode) /* TST */ | |
41748 | { | |
41749 | OpcodeFamily = 20; CurrentInstrCycles = 8; | |
41750 | {{ int8_t src = get_ibyte_prefetch(2); | |
41751 | CLEAR_CZNV; | |
41752 | SET_ZFLG (((int8_t)(src)) == 0); | |
41753 | SET_NFLG (((int8_t)(src)) < 0); | |
41754 | }}m68k_incpc(4); | |
41755 | fill_prefetch_0 (); | |
41756 | return 8; | |
41757 | } | |
41758 | unsigned long CPUFUNC(op_4a40_5)(uint32_t opcode) /* TST */ | |
41759 | { | |
41760 | uint32_t srcreg = (opcode & 7); | |
41761 | OpcodeFamily = 20; CurrentInstrCycles = 4; | |
41762 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
41763 | CLEAR_CZNV; | |
41764 | SET_ZFLG (((int16_t)(src)) == 0); | |
41765 | SET_NFLG (((int16_t)(src)) < 0); | |
41766 | }}m68k_incpc(2); | |
41767 | fill_prefetch_2 (); | |
41768 | return 4; | |
41769 | } | |
41770 | unsigned long CPUFUNC(op_4a48_5)(uint32_t opcode) /* TST */ | |
41771 | { | |
41772 | uint32_t srcreg = (opcode & 7); | |
41773 | OpcodeFamily = 20; CurrentInstrCycles = 4; | |
41774 | {{ int16_t src = m68k_areg(regs, srcreg); | |
41775 | CLEAR_CZNV; | |
41776 | SET_ZFLG (((int16_t)(src)) == 0); | |
41777 | SET_NFLG (((int16_t)(src)) < 0); | |
41778 | }}m68k_incpc(2); | |
41779 | fill_prefetch_2 (); | |
41780 | return 4; | |
41781 | } | |
41782 | unsigned long CPUFUNC(op_4a50_5)(uint32_t opcode) /* TST */ | |
41783 | { | |
41784 | uint32_t srcreg = (opcode & 7); | |
41785 | OpcodeFamily = 20; CurrentInstrCycles = 8; | |
41786 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
41787 | if ((srca & 1) != 0) { | |
41788 | last_fault_for_exception_3 = srca; | |
41789 | last_op_for_exception_3 = opcode; | |
41790 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
41791 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
41792 | goto endlabel2322; | |
41793 | } | |
41794 | {{ int16_t src = m68k_read_memory_16(srca); | |
41795 | CLEAR_CZNV; | |
41796 | SET_ZFLG (((int16_t)(src)) == 0); | |
41797 | SET_NFLG (((int16_t)(src)) < 0); | |
41798 | }}}}m68k_incpc(2); | |
41799 | fill_prefetch_2 (); | |
41800 | endlabel2322: ; | |
41801 | return 8; | |
41802 | } | |
41803 | unsigned long CPUFUNC(op_4a58_5)(uint32_t opcode) /* TST */ | |
41804 | { | |
41805 | uint32_t srcreg = (opcode & 7); | |
41806 | OpcodeFamily = 20; CurrentInstrCycles = 8; | |
41807 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
41808 | if ((srca & 1) != 0) { | |
41809 | last_fault_for_exception_3 = srca; | |
41810 | last_op_for_exception_3 = opcode; | |
41811 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
41812 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
41813 | goto endlabel2323; | |
41814 | } | |
41815 | {{ int16_t src = m68k_read_memory_16(srca); | |
41816 | m68k_areg(regs, srcreg) += 2; | |
41817 | CLEAR_CZNV; | |
41818 | SET_ZFLG (((int16_t)(src)) == 0); | |
41819 | SET_NFLG (((int16_t)(src)) < 0); | |
41820 | }}}}m68k_incpc(2); | |
41821 | fill_prefetch_2 (); | |
41822 | endlabel2323: ; | |
41823 | return 8; | |
41824 | } | |
41825 | unsigned long CPUFUNC(op_4a60_5)(uint32_t opcode) /* TST */ | |
41826 | { | |
41827 | uint32_t srcreg = (opcode & 7); | |
41828 | OpcodeFamily = 20; CurrentInstrCycles = 10; | |
41829 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
41830 | if ((srca & 1) != 0) { | |
41831 | last_fault_for_exception_3 = srca; | |
41832 | last_op_for_exception_3 = opcode; | |
41833 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
41834 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
41835 | goto endlabel2324; | |
41836 | } | |
41837 | {{ int16_t src = m68k_read_memory_16(srca); | |
41838 | m68k_areg (regs, srcreg) = srca; | |
41839 | CLEAR_CZNV; | |
41840 | SET_ZFLG (((int16_t)(src)) == 0); | |
41841 | SET_NFLG (((int16_t)(src)) < 0); | |
41842 | }}}}m68k_incpc(2); | |
41843 | fill_prefetch_2 (); | |
41844 | endlabel2324: ; | |
41845 | return 10; | |
41846 | } | |
41847 | unsigned long CPUFUNC(op_4a68_5)(uint32_t opcode) /* TST */ | |
41848 | { | |
41849 | uint32_t srcreg = (opcode & 7); | |
41850 | OpcodeFamily = 20; CurrentInstrCycles = 12; | |
41851 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
41852 | if ((srca & 1) != 0) { | |
41853 | last_fault_for_exception_3 = srca; | |
41854 | last_op_for_exception_3 = opcode; | |
41855 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
41856 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
41857 | goto endlabel2325; | |
41858 | } | |
41859 | {{ int16_t src = m68k_read_memory_16(srca); | |
41860 | CLEAR_CZNV; | |
41861 | SET_ZFLG (((int16_t)(src)) == 0); | |
41862 | SET_NFLG (((int16_t)(src)) < 0); | |
41863 | }}}}m68k_incpc(4); | |
41864 | fill_prefetch_0 (); | |
41865 | endlabel2325: ; | |
41866 | return 12; | |
41867 | } | |
41868 | unsigned long CPUFUNC(op_4a70_5)(uint32_t opcode) /* TST */ | |
41869 | { | |
41870 | uint32_t srcreg = (opcode & 7); | |
41871 | OpcodeFamily = 20; CurrentInstrCycles = 14; | |
41872 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
41873 | BusCyclePenalty += 2; | |
41874 | if ((srca & 1) != 0) { | |
41875 | last_fault_for_exception_3 = srca; | |
41876 | last_op_for_exception_3 = opcode; | |
41877 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
41878 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
41879 | goto endlabel2326; | |
41880 | } | |
41881 | {{ int16_t src = m68k_read_memory_16(srca); | |
41882 | CLEAR_CZNV; | |
41883 | SET_ZFLG (((int16_t)(src)) == 0); | |
41884 | SET_NFLG (((int16_t)(src)) < 0); | |
41885 | }}}}m68k_incpc(4); | |
41886 | fill_prefetch_0 (); | |
41887 | endlabel2326: ; | |
41888 | return 14; | |
41889 | } | |
41890 | unsigned long CPUFUNC(op_4a78_5)(uint32_t opcode) /* TST */ | |
41891 | { | |
41892 | OpcodeFamily = 20; CurrentInstrCycles = 12; | |
41893 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
41894 | if ((srca & 1) != 0) { | |
41895 | last_fault_for_exception_3 = srca; | |
41896 | last_op_for_exception_3 = opcode; | |
41897 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
41898 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
41899 | goto endlabel2327; | |
41900 | } | |
41901 | {{ int16_t src = m68k_read_memory_16(srca); | |
41902 | CLEAR_CZNV; | |
41903 | SET_ZFLG (((int16_t)(src)) == 0); | |
41904 | SET_NFLG (((int16_t)(src)) < 0); | |
41905 | }}}}m68k_incpc(4); | |
41906 | fill_prefetch_0 (); | |
41907 | endlabel2327: ; | |
41908 | return 12; | |
41909 | } | |
41910 | unsigned long CPUFUNC(op_4a79_5)(uint32_t opcode) /* TST */ | |
41911 | { | |
41912 | OpcodeFamily = 20; CurrentInstrCycles = 16; | |
41913 | {{ uint32_t srca = get_ilong_prefetch(2); | |
41914 | if ((srca & 1) != 0) { | |
41915 | last_fault_for_exception_3 = srca; | |
41916 | last_op_for_exception_3 = opcode; | |
41917 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
41918 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
41919 | goto endlabel2328; | |
41920 | } | |
41921 | {{ int16_t src = m68k_read_memory_16(srca); | |
41922 | CLEAR_CZNV; | |
41923 | SET_ZFLG (((int16_t)(src)) == 0); | |
41924 | SET_NFLG (((int16_t)(src)) < 0); | |
41925 | }}}}m68k_incpc(6); | |
41926 | fill_prefetch_0 (); | |
41927 | endlabel2328: ; | |
41928 | return 16; | |
41929 | } | |
41930 | unsigned long CPUFUNC(op_4a7a_5)(uint32_t opcode) /* TST */ | |
41931 | { | |
41932 | OpcodeFamily = 20; CurrentInstrCycles = 12; | |
41933 | {{ uint32_t srca = m68k_getpc () + 2; | |
41934 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
41935 | if ((srca & 1) != 0) { | |
41936 | last_fault_for_exception_3 = srca; | |
41937 | last_op_for_exception_3 = opcode; | |
41938 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
41939 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
41940 | goto endlabel2329; | |
41941 | } | |
41942 | {{ int16_t src = m68k_read_memory_16(srca); | |
41943 | CLEAR_CZNV; | |
41944 | SET_ZFLG (((int16_t)(src)) == 0); | |
41945 | SET_NFLG (((int16_t)(src)) < 0); | |
41946 | }}}}m68k_incpc(4); | |
41947 | fill_prefetch_0 (); | |
41948 | endlabel2329: ; | |
41949 | return 12; | |
41950 | } | |
41951 | unsigned long CPUFUNC(op_4a7b_5)(uint32_t opcode) /* TST */ | |
41952 | { | |
41953 | OpcodeFamily = 20; CurrentInstrCycles = 14; | |
41954 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
41955 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
41956 | BusCyclePenalty += 2; | |
41957 | if ((srca & 1) != 0) { | |
41958 | last_fault_for_exception_3 = srca; | |
41959 | last_op_for_exception_3 = opcode; | |
41960 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
41961 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
41962 | goto endlabel2330; | |
41963 | } | |
41964 | {{ int16_t src = m68k_read_memory_16(srca); | |
41965 | CLEAR_CZNV; | |
41966 | SET_ZFLG (((int16_t)(src)) == 0); | |
41967 | SET_NFLG (((int16_t)(src)) < 0); | |
41968 | }}}}m68k_incpc(4); | |
41969 | fill_prefetch_0 (); | |
41970 | endlabel2330: ; | |
41971 | return 14; | |
41972 | } | |
41973 | unsigned long CPUFUNC(op_4a7c_5)(uint32_t opcode) /* TST */ | |
41974 | { | |
41975 | OpcodeFamily = 20; CurrentInstrCycles = 8; | |
41976 | {{ int16_t src = get_iword_prefetch(2); | |
41977 | CLEAR_CZNV; | |
41978 | SET_ZFLG (((int16_t)(src)) == 0); | |
41979 | SET_NFLG (((int16_t)(src)) < 0); | |
41980 | }}m68k_incpc(4); | |
41981 | fill_prefetch_0 (); | |
41982 | return 8; | |
41983 | } | |
41984 | unsigned long CPUFUNC(op_4a80_5)(uint32_t opcode) /* TST */ | |
41985 | { | |
41986 | uint32_t srcreg = (opcode & 7); | |
41987 | OpcodeFamily = 20; CurrentInstrCycles = 4; | |
41988 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
41989 | CLEAR_CZNV; | |
41990 | SET_ZFLG (((int32_t)(src)) == 0); | |
41991 | SET_NFLG (((int32_t)(src)) < 0); | |
41992 | }}m68k_incpc(2); | |
41993 | fill_prefetch_2 (); | |
41994 | return 4; | |
41995 | } | |
41996 | unsigned long CPUFUNC(op_4a88_5)(uint32_t opcode) /* TST */ | |
41997 | { | |
41998 | uint32_t srcreg = (opcode & 7); | |
41999 | OpcodeFamily = 20; CurrentInstrCycles = 4; | |
42000 | {{ int32_t src = m68k_areg(regs, srcreg); | |
42001 | CLEAR_CZNV; | |
42002 | SET_ZFLG (((int32_t)(src)) == 0); | |
42003 | SET_NFLG (((int32_t)(src)) < 0); | |
42004 | }}m68k_incpc(2); | |
42005 | fill_prefetch_2 (); | |
42006 | return 4; | |
42007 | } | |
42008 | unsigned long CPUFUNC(op_4a90_5)(uint32_t opcode) /* TST */ | |
42009 | { | |
42010 | uint32_t srcreg = (opcode & 7); | |
42011 | OpcodeFamily = 20; CurrentInstrCycles = 12; | |
42012 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
42013 | if ((srca & 1) != 0) { | |
42014 | last_fault_for_exception_3 = srca; | |
42015 | last_op_for_exception_3 = opcode; | |
42016 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
42017 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
42018 | goto endlabel2334; | |
42019 | } | |
42020 | {{ int32_t src = m68k_read_memory_32(srca); | |
42021 | CLEAR_CZNV; | |
42022 | SET_ZFLG (((int32_t)(src)) == 0); | |
42023 | SET_NFLG (((int32_t)(src)) < 0); | |
42024 | }}}}m68k_incpc(2); | |
42025 | fill_prefetch_2 (); | |
42026 | endlabel2334: ; | |
42027 | return 12; | |
42028 | } | |
42029 | unsigned long CPUFUNC(op_4a98_5)(uint32_t opcode) /* TST */ | |
42030 | { | |
42031 | uint32_t srcreg = (opcode & 7); | |
42032 | OpcodeFamily = 20; CurrentInstrCycles = 12; | |
42033 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
42034 | if ((srca & 1) != 0) { | |
42035 | last_fault_for_exception_3 = srca; | |
42036 | last_op_for_exception_3 = opcode; | |
42037 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
42038 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
42039 | goto endlabel2335; | |
42040 | } | |
42041 | {{ int32_t src = m68k_read_memory_32(srca); | |
42042 | m68k_areg(regs, srcreg) += 4; | |
42043 | CLEAR_CZNV; | |
42044 | SET_ZFLG (((int32_t)(src)) == 0); | |
42045 | SET_NFLG (((int32_t)(src)) < 0); | |
42046 | }}}}m68k_incpc(2); | |
42047 | fill_prefetch_2 (); | |
42048 | endlabel2335: ; | |
42049 | return 12; | |
42050 | } | |
42051 | unsigned long CPUFUNC(op_4aa0_5)(uint32_t opcode) /* TST */ | |
42052 | { | |
42053 | uint32_t srcreg = (opcode & 7); | |
42054 | OpcodeFamily = 20; CurrentInstrCycles = 14; | |
42055 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 4; | |
42056 | if ((srca & 1) != 0) { | |
42057 | last_fault_for_exception_3 = srca; | |
42058 | last_op_for_exception_3 = opcode; | |
42059 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
42060 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
42061 | goto endlabel2336; | |
42062 | } | |
42063 | {{ int32_t src = m68k_read_memory_32(srca); | |
42064 | m68k_areg (regs, srcreg) = srca; | |
42065 | CLEAR_CZNV; | |
42066 | SET_ZFLG (((int32_t)(src)) == 0); | |
42067 | SET_NFLG (((int32_t)(src)) < 0); | |
42068 | }}}}m68k_incpc(2); | |
42069 | fill_prefetch_2 (); | |
42070 | endlabel2336: ; | |
42071 | return 14; | |
42072 | } | |
42073 | unsigned long CPUFUNC(op_4aa8_5)(uint32_t opcode) /* TST */ | |
42074 | { | |
42075 | uint32_t srcreg = (opcode & 7); | |
42076 | OpcodeFamily = 20; CurrentInstrCycles = 16; | |
42077 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
42078 | if ((srca & 1) != 0) { | |
42079 | last_fault_for_exception_3 = srca; | |
42080 | last_op_for_exception_3 = opcode; | |
42081 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
42082 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
42083 | goto endlabel2337; | |
42084 | } | |
42085 | {{ int32_t src = m68k_read_memory_32(srca); | |
42086 | CLEAR_CZNV; | |
42087 | SET_ZFLG (((int32_t)(src)) == 0); | |
42088 | SET_NFLG (((int32_t)(src)) < 0); | |
42089 | }}}}m68k_incpc(4); | |
42090 | fill_prefetch_0 (); | |
42091 | endlabel2337: ; | |
42092 | return 16; | |
42093 | } | |
42094 | unsigned long CPUFUNC(op_4ab0_5)(uint32_t opcode) /* TST */ | |
42095 | { | |
42096 | uint32_t srcreg = (opcode & 7); | |
42097 | OpcodeFamily = 20; CurrentInstrCycles = 18; | |
42098 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
42099 | BusCyclePenalty += 2; | |
42100 | if ((srca & 1) != 0) { | |
42101 | last_fault_for_exception_3 = srca; | |
42102 | last_op_for_exception_3 = opcode; | |
42103 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
42104 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
42105 | goto endlabel2338; | |
42106 | } | |
42107 | {{ int32_t src = m68k_read_memory_32(srca); | |
42108 | CLEAR_CZNV; | |
42109 | SET_ZFLG (((int32_t)(src)) == 0); | |
42110 | SET_NFLG (((int32_t)(src)) < 0); | |
42111 | }}}}m68k_incpc(4); | |
42112 | fill_prefetch_0 (); | |
42113 | endlabel2338: ; | |
42114 | return 18; | |
42115 | } | |
42116 | unsigned long CPUFUNC(op_4ab8_5)(uint32_t opcode) /* TST */ | |
42117 | { | |
42118 | OpcodeFamily = 20; CurrentInstrCycles = 16; | |
42119 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
42120 | if ((srca & 1) != 0) { | |
42121 | last_fault_for_exception_3 = srca; | |
42122 | last_op_for_exception_3 = opcode; | |
42123 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
42124 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
42125 | goto endlabel2339; | |
42126 | } | |
42127 | {{ int32_t src = m68k_read_memory_32(srca); | |
42128 | CLEAR_CZNV; | |
42129 | SET_ZFLG (((int32_t)(src)) == 0); | |
42130 | SET_NFLG (((int32_t)(src)) < 0); | |
42131 | }}}}m68k_incpc(4); | |
42132 | fill_prefetch_0 (); | |
42133 | endlabel2339: ; | |
42134 | return 16; | |
42135 | } | |
42136 | unsigned long CPUFUNC(op_4ab9_5)(uint32_t opcode) /* TST */ | |
42137 | { | |
42138 | OpcodeFamily = 20; CurrentInstrCycles = 20; | |
42139 | {{ uint32_t srca = get_ilong_prefetch(2); | |
42140 | if ((srca & 1) != 0) { | |
42141 | last_fault_for_exception_3 = srca; | |
42142 | last_op_for_exception_3 = opcode; | |
42143 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
42144 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
42145 | goto endlabel2340; | |
42146 | } | |
42147 | {{ int32_t src = m68k_read_memory_32(srca); | |
42148 | CLEAR_CZNV; | |
42149 | SET_ZFLG (((int32_t)(src)) == 0); | |
42150 | SET_NFLG (((int32_t)(src)) < 0); | |
42151 | }}}}m68k_incpc(6); | |
42152 | fill_prefetch_0 (); | |
42153 | endlabel2340: ; | |
42154 | return 20; | |
42155 | } | |
42156 | unsigned long CPUFUNC(op_4aba_5)(uint32_t opcode) /* TST */ | |
42157 | { | |
42158 | OpcodeFamily = 20; CurrentInstrCycles = 16; | |
42159 | {{ uint32_t srca = m68k_getpc () + 2; | |
42160 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
42161 | if ((srca & 1) != 0) { | |
42162 | last_fault_for_exception_3 = srca; | |
42163 | last_op_for_exception_3 = opcode; | |
42164 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
42165 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
42166 | goto endlabel2341; | |
42167 | } | |
42168 | {{ int32_t src = m68k_read_memory_32(srca); | |
42169 | CLEAR_CZNV; | |
42170 | SET_ZFLG (((int32_t)(src)) == 0); | |
42171 | SET_NFLG (((int32_t)(src)) < 0); | |
42172 | }}}}m68k_incpc(4); | |
42173 | fill_prefetch_0 (); | |
42174 | endlabel2341: ; | |
42175 | return 16; | |
42176 | } | |
42177 | unsigned long CPUFUNC(op_4abb_5)(uint32_t opcode) /* TST */ | |
42178 | { | |
42179 | OpcodeFamily = 20; CurrentInstrCycles = 18; | |
42180 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
42181 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
42182 | BusCyclePenalty += 2; | |
42183 | if ((srca & 1) != 0) { | |
42184 | last_fault_for_exception_3 = srca; | |
42185 | last_op_for_exception_3 = opcode; | |
42186 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
42187 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
42188 | goto endlabel2342; | |
42189 | } | |
42190 | {{ int32_t src = m68k_read_memory_32(srca); | |
42191 | CLEAR_CZNV; | |
42192 | SET_ZFLG (((int32_t)(src)) == 0); | |
42193 | SET_NFLG (((int32_t)(src)) < 0); | |
42194 | }}}}m68k_incpc(4); | |
42195 | fill_prefetch_0 (); | |
42196 | endlabel2342: ; | |
42197 | return 18; | |
42198 | } | |
42199 | unsigned long CPUFUNC(op_4abc_5)(uint32_t opcode) /* TST */ | |
42200 | { | |
42201 | OpcodeFamily = 20; CurrentInstrCycles = 12; | |
42202 | {{ int32_t src = get_ilong_prefetch(2); | |
42203 | CLEAR_CZNV; | |
42204 | SET_ZFLG (((int32_t)(src)) == 0); | |
42205 | SET_NFLG (((int32_t)(src)) < 0); | |
42206 | }}m68k_incpc(6); | |
42207 | fill_prefetch_0 (); | |
42208 | return 12; | |
42209 | } | |
42210 | unsigned long CPUFUNC(op_4ac0_5)(uint32_t opcode) /* TAS */ | |
42211 | { | |
42212 | uint32_t srcreg = (opcode & 7); | |
42213 | OpcodeFamily = 98; CurrentInstrCycles = 4; | |
42214 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
42215 | CLEAR_CZNV; | |
42216 | SET_ZFLG (((int8_t)(src)) == 0); | |
42217 | SET_NFLG (((int8_t)(src)) < 0); | |
42218 | src |= 0x80; | |
42219 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((src) & 0xff); | |
42220 | }}m68k_incpc(2); | |
42221 | fill_prefetch_2 (); | |
42222 | return 4; | |
42223 | } | |
42224 | unsigned long CPUFUNC(op_4ad0_5)(uint32_t opcode) /* TAS */ | |
42225 | { | |
42226 | uint32_t srcreg = (opcode & 7); | |
42227 | OpcodeFamily = 98; CurrentInstrCycles = 14; | |
42228 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
42229 | { int8_t src = m68k_read_memory_8(srca); | |
42230 | CLEAR_CZNV; | |
42231 | SET_ZFLG (((int8_t)(src)) == 0); | |
42232 | SET_NFLG (((int8_t)(src)) < 0); | |
42233 | src |= 0x80; | |
42234 | m68k_incpc(2); | |
42235 | fill_prefetch_2 (); | |
42236 | m68k_write_memory_8(srca,src); | |
42237 | }}}return 14; | |
42238 | } | |
42239 | unsigned long CPUFUNC(op_4ad8_5)(uint32_t opcode) /* TAS */ | |
42240 | { | |
42241 | uint32_t srcreg = (opcode & 7); | |
42242 | OpcodeFamily = 98; CurrentInstrCycles = 14; | |
42243 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
42244 | { int8_t src = m68k_read_memory_8(srca); | |
42245 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
42246 | CLEAR_CZNV; | |
42247 | SET_ZFLG (((int8_t)(src)) == 0); | |
42248 | SET_NFLG (((int8_t)(src)) < 0); | |
42249 | src |= 0x80; | |
42250 | m68k_incpc(2); | |
42251 | fill_prefetch_2 (); | |
42252 | m68k_write_memory_8(srca,src); | |
42253 | }}}return 14; | |
42254 | } | |
42255 | unsigned long CPUFUNC(op_4ae0_5)(uint32_t opcode) /* TAS */ | |
42256 | { | |
42257 | uint32_t srcreg = (opcode & 7); | |
42258 | OpcodeFamily = 98; CurrentInstrCycles = 16; | |
42259 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
42260 | { int8_t src = m68k_read_memory_8(srca); | |
42261 | m68k_areg (regs, srcreg) = srca; | |
42262 | CLEAR_CZNV; | |
42263 | SET_ZFLG (((int8_t)(src)) == 0); | |
42264 | SET_NFLG (((int8_t)(src)) < 0); | |
42265 | src |= 0x80; | |
42266 | m68k_incpc(2); | |
42267 | fill_prefetch_2 (); | |
42268 | m68k_write_memory_8(srca,src); | |
42269 | }}}return 16; | |
42270 | } | |
42271 | unsigned long CPUFUNC(op_4ae8_5)(uint32_t opcode) /* TAS */ | |
42272 | { | |
42273 | uint32_t srcreg = (opcode & 7); | |
42274 | OpcodeFamily = 98; CurrentInstrCycles = 18; | |
42275 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
42276 | { int8_t src = m68k_read_memory_8(srca); | |
42277 | CLEAR_CZNV; | |
42278 | SET_ZFLG (((int8_t)(src)) == 0); | |
42279 | SET_NFLG (((int8_t)(src)) < 0); | |
42280 | src |= 0x80; | |
42281 | m68k_incpc(4); | |
42282 | fill_prefetch_0 (); | |
42283 | m68k_write_memory_8(srca,src); | |
42284 | }}}return 18; | |
42285 | } | |
42286 | unsigned long CPUFUNC(op_4af0_5)(uint32_t opcode) /* TAS */ | |
42287 | { | |
42288 | uint32_t srcreg = (opcode & 7); | |
42289 | OpcodeFamily = 98; CurrentInstrCycles = 20; | |
42290 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
42291 | BusCyclePenalty += 2; | |
42292 | { int8_t src = m68k_read_memory_8(srca); | |
42293 | CLEAR_CZNV; | |
42294 | SET_ZFLG (((int8_t)(src)) == 0); | |
42295 | SET_NFLG (((int8_t)(src)) < 0); | |
42296 | src |= 0x80; | |
42297 | m68k_incpc(4); | |
42298 | fill_prefetch_0 (); | |
42299 | m68k_write_memory_8(srca,src); | |
42300 | }}}return 20; | |
42301 | } | |
42302 | unsigned long CPUFUNC(op_4af8_5)(uint32_t opcode) /* TAS */ | |
42303 | { | |
42304 | OpcodeFamily = 98; CurrentInstrCycles = 18; | |
42305 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
42306 | { int8_t src = m68k_read_memory_8(srca); | |
42307 | CLEAR_CZNV; | |
42308 | SET_ZFLG (((int8_t)(src)) == 0); | |
42309 | SET_NFLG (((int8_t)(src)) < 0); | |
42310 | src |= 0x80; | |
42311 | m68k_incpc(4); | |
42312 | fill_prefetch_0 (); | |
42313 | m68k_write_memory_8(srca,src); | |
42314 | }}}return 18; | |
42315 | } | |
42316 | unsigned long CPUFUNC(op_4af9_5)(uint32_t opcode) /* TAS */ | |
42317 | { | |
42318 | OpcodeFamily = 98; CurrentInstrCycles = 22; | |
42319 | {{ uint32_t srca = get_ilong_prefetch(2); | |
42320 | { int8_t src = m68k_read_memory_8(srca); | |
42321 | CLEAR_CZNV; | |
42322 | SET_ZFLG (((int8_t)(src)) == 0); | |
42323 | SET_NFLG (((int8_t)(src)) < 0); | |
42324 | src |= 0x80; | |
42325 | m68k_incpc(6); | |
42326 | fill_prefetch_0 (); | |
42327 | m68k_write_memory_8(srca,src); | |
42328 | }}}return 22; | |
42329 | } | |
42330 | unsigned long CPUFUNC(op_4c90_5)(uint32_t opcode) /* MVMEL */ | |
42331 | { | |
42332 | uint32_t dstreg = opcode & 7; | |
42333 | unsigned int retcycles = 0; | |
42334 | OpcodeFamily = 37; CurrentInstrCycles = 12; | |
42335 | { uint16_t mask = get_iword_prefetch(2); | |
42336 | unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; | |
42337 | retcycles = 0; | |
42338 | { uint32_t srca = m68k_areg(regs, dstreg); | |
42339 | if ((srca & 1) != 0) { | |
42340 | last_fault_for_exception_3 = srca; | |
42341 | last_op_for_exception_3 = opcode; | |
42342 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
42343 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
42344 | goto endlabel2352; | |
42345 | } | |
42346 | {{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; } | |
42347 | while (amask) { m68k_areg(regs, movem_index1[amask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; } | |
42348 | }}}}m68k_incpc(4); | |
42349 | fill_prefetch_0 (); | |
42350 | endlabel2352: ; | |
42351 | return (12+retcycles); | |
42352 | } | |
42353 | unsigned long CPUFUNC(op_4c98_5)(uint32_t opcode) /* MVMEL */ | |
42354 | { | |
42355 | uint32_t dstreg = opcode & 7; | |
42356 | unsigned int retcycles = 0; | |
42357 | OpcodeFamily = 37; CurrentInstrCycles = 12; | |
42358 | { uint16_t mask = get_iword_prefetch(2); | |
42359 | unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; | |
42360 | retcycles = 0; | |
42361 | { uint32_t srca = m68k_areg(regs, dstreg); | |
42362 | if ((srca & 1) != 0) { | |
42363 | last_fault_for_exception_3 = srca; | |
42364 | last_op_for_exception_3 = opcode; | |
42365 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
42366 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
42367 | goto endlabel2353; | |
42368 | } | |
42369 | {{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; } | |
42370 | while (amask) { m68k_areg(regs, movem_index1[amask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; } | |
42371 | m68k_areg(regs, dstreg) = srca; | |
42372 | }}}}m68k_incpc(4); | |
42373 | fill_prefetch_0 (); | |
42374 | endlabel2353: ; | |
42375 | return (12+retcycles); | |
42376 | } | |
42377 | unsigned long CPUFUNC(op_4ca8_5)(uint32_t opcode) /* MVMEL */ | |
42378 | { | |
42379 | uint32_t dstreg = opcode & 7; | |
42380 | unsigned int retcycles = 0; | |
42381 | OpcodeFamily = 37; CurrentInstrCycles = 16; | |
42382 | { uint16_t mask = get_iword_prefetch(2); | |
42383 | unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; | |
42384 | retcycles = 0; | |
42385 | { uint32_t srca = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); | |
42386 | if ((srca & 1) != 0) { | |
42387 | last_fault_for_exception_3 = srca; | |
42388 | last_op_for_exception_3 = opcode; | |
42389 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
42390 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
42391 | goto endlabel2354; | |
42392 | } | |
42393 | {{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; } | |
42394 | while (amask) { m68k_areg(regs, movem_index1[amask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; } | |
42395 | }}}}m68k_incpc(6); | |
42396 | fill_prefetch_0 (); | |
42397 | endlabel2354: ; | |
42398 | return (16+retcycles); | |
42399 | } | |
42400 | unsigned long CPUFUNC(op_4cb0_5)(uint32_t opcode) /* MVMEL */ | |
42401 | { | |
42402 | uint32_t dstreg = opcode & 7; | |
42403 | unsigned int retcycles = 0; | |
42404 | OpcodeFamily = 37; CurrentInstrCycles = 18; | |
42405 | { uint16_t mask = get_iword_prefetch(2); | |
42406 | unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; | |
42407 | retcycles = 0; | |
42408 | { uint32_t srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); | |
42409 | BusCyclePenalty += 2; | |
42410 | if ((srca & 1) != 0) { | |
42411 | last_fault_for_exception_3 = srca; | |
42412 | last_op_for_exception_3 = opcode; | |
42413 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
42414 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
42415 | goto endlabel2355; | |
42416 | } | |
42417 | {{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; } | |
42418 | while (amask) { m68k_areg(regs, movem_index1[amask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; } | |
42419 | }}}}m68k_incpc(6); | |
42420 | fill_prefetch_0 (); | |
42421 | endlabel2355: ; | |
42422 | return (18+retcycles); | |
42423 | } | |
42424 | unsigned long CPUFUNC(op_4cb8_5)(uint32_t opcode) /* MVMEL */ | |
42425 | { | |
42426 | unsigned int retcycles = 0; | |
42427 | OpcodeFamily = 37; CurrentInstrCycles = 16; | |
42428 | { uint16_t mask = get_iword_prefetch(2); | |
42429 | unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; | |
42430 | retcycles = 0; | |
42431 | { uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(4); | |
42432 | if ((srca & 1) != 0) { | |
42433 | last_fault_for_exception_3 = srca; | |
42434 | last_op_for_exception_3 = opcode; | |
42435 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
42436 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
42437 | goto endlabel2356; | |
42438 | } | |
42439 | {{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; } | |
42440 | while (amask) { m68k_areg(regs, movem_index1[amask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; } | |
42441 | }}}}m68k_incpc(6); | |
42442 | fill_prefetch_0 (); | |
42443 | endlabel2356: ; | |
42444 | return (16+retcycles); | |
42445 | } | |
42446 | unsigned long CPUFUNC(op_4cb9_5)(uint32_t opcode) /* MVMEL */ | |
42447 | { | |
42448 | unsigned int retcycles = 0; | |
42449 | OpcodeFamily = 37; CurrentInstrCycles = 20; | |
42450 | { uint16_t mask = get_iword_prefetch(2); | |
42451 | unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; | |
42452 | retcycles = 0; | |
42453 | { uint32_t srca = get_ilong_prefetch(4); | |
42454 | if ((srca & 1) != 0) { | |
42455 | last_fault_for_exception_3 = srca; | |
42456 | last_op_for_exception_3 = opcode; | |
42457 | last_addr_for_exception_3 = m68k_getpc() + 8; | |
42458 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
42459 | goto endlabel2357; | |
42460 | } | |
42461 | {{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; } | |
42462 | while (amask) { m68k_areg(regs, movem_index1[amask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; } | |
42463 | }}}}m68k_incpc(8); | |
42464 | fill_prefetch_0 (); | |
42465 | endlabel2357: ; | |
42466 | return (20+retcycles); | |
42467 | } | |
42468 | unsigned long CPUFUNC(op_4cba_5)(uint32_t opcode) /* MVMEL */ | |
42469 | { | |
42470 | uint32_t dstreg = 2; | |
42471 | unsigned int retcycles = 0; | |
42472 | OpcodeFamily = 37; CurrentInstrCycles = 16; | |
42473 | { uint16_t mask = get_iword_prefetch(2); | |
42474 | unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; | |
42475 | retcycles = 0; | |
42476 | { uint32_t srca = m68k_getpc () + 4; | |
42477 | srca += (int32_t)(int16_t)get_iword_prefetch(4); | |
42478 | if ((srca & 1) != 0) { | |
42479 | last_fault_for_exception_3 = srca; | |
42480 | last_op_for_exception_3 = opcode; | |
42481 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
42482 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
42483 | goto endlabel2358; | |
42484 | } | |
42485 | {{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; } | |
42486 | while (amask) { m68k_areg(regs, movem_index1[amask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; } | |
42487 | }}}}m68k_incpc(6); | |
42488 | fill_prefetch_0 (); | |
42489 | endlabel2358: ; | |
42490 | return (16+retcycles); | |
42491 | } | |
42492 | unsigned long CPUFUNC(op_4cbb_5)(uint32_t opcode) /* MVMEL */ | |
42493 | { | |
42494 | uint32_t dstreg = 3; | |
42495 | unsigned int retcycles = 0; | |
42496 | OpcodeFamily = 37; CurrentInstrCycles = 18; | |
42497 | { uint16_t mask = get_iword_prefetch(2); | |
42498 | unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; | |
42499 | retcycles = 0; | |
42500 | { uint32_t tmppc = m68k_getpc() + 4; | |
42501 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(4)); | |
42502 | BusCyclePenalty += 2; | |
42503 | if ((srca & 1) != 0) { | |
42504 | last_fault_for_exception_3 = srca; | |
42505 | last_op_for_exception_3 = opcode; | |
42506 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
42507 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
42508 | goto endlabel2359; | |
42509 | } | |
42510 | {{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; dmask = movem_next[dmask]; retcycles+=4; } | |
42511 | while (amask) { m68k_areg(regs, movem_index1[amask]) = (int32_t)(int16_t)m68k_read_memory_16(srca); srca += 2; amask = movem_next[amask]; retcycles+=4; } | |
42512 | }}}}m68k_incpc(6); | |
42513 | fill_prefetch_0 (); | |
42514 | endlabel2359: ; | |
42515 | return (18+retcycles); | |
42516 | } | |
42517 | unsigned long CPUFUNC(op_4cd0_5)(uint32_t opcode) /* MVMEL */ | |
42518 | { | |
42519 | uint32_t dstreg = opcode & 7; | |
42520 | unsigned int retcycles = 0; | |
42521 | OpcodeFamily = 37; CurrentInstrCycles = 12; | |
42522 | { uint16_t mask = get_iword_prefetch(2); | |
42523 | unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; | |
42524 | retcycles = 0; | |
42525 | { uint32_t srca = m68k_areg(regs, dstreg); | |
42526 | if ((srca & 1) != 0) { | |
42527 | last_fault_for_exception_3 = srca; | |
42528 | last_op_for_exception_3 = opcode; | |
42529 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
42530 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
42531 | goto endlabel2360; | |
42532 | } | |
42533 | {{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = m68k_read_memory_32(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; } | |
42534 | while (amask) { m68k_areg(regs, movem_index1[amask]) = m68k_read_memory_32(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; } | |
42535 | }}}}m68k_incpc(4); | |
42536 | fill_prefetch_0 (); | |
42537 | endlabel2360: ; | |
42538 | return (12+retcycles); | |
42539 | } | |
42540 | unsigned long CPUFUNC(op_4cd8_5)(uint32_t opcode) /* MVMEL */ | |
42541 | { | |
42542 | uint32_t dstreg = opcode & 7; | |
42543 | unsigned int retcycles = 0; | |
42544 | OpcodeFamily = 37; CurrentInstrCycles = 12; | |
42545 | { uint16_t mask = get_iword_prefetch(2); | |
42546 | unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; | |
42547 | retcycles = 0; | |
42548 | { uint32_t srca = m68k_areg(regs, dstreg); | |
42549 | if ((srca & 1) != 0) { | |
42550 | last_fault_for_exception_3 = srca; | |
42551 | last_op_for_exception_3 = opcode; | |
42552 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
42553 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
42554 | goto endlabel2361; | |
42555 | } | |
42556 | {{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = m68k_read_memory_32(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; } | |
42557 | while (amask) { m68k_areg(regs, movem_index1[amask]) = m68k_read_memory_32(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; } | |
42558 | m68k_areg(regs, dstreg) = srca; | |
42559 | }}}}m68k_incpc(4); | |
42560 | fill_prefetch_0 (); | |
42561 | endlabel2361: ; | |
42562 | return (12+retcycles); | |
42563 | } | |
42564 | unsigned long CPUFUNC(op_4ce8_5)(uint32_t opcode) /* MVMEL */ | |
42565 | { | |
42566 | uint32_t dstreg = opcode & 7; | |
42567 | unsigned int retcycles = 0; | |
42568 | OpcodeFamily = 37; CurrentInstrCycles = 16; | |
42569 | { uint16_t mask = get_iword_prefetch(2); | |
42570 | unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; | |
42571 | retcycles = 0; | |
42572 | { uint32_t srca = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(4); | |
42573 | if ((srca & 1) != 0) { | |
42574 | last_fault_for_exception_3 = srca; | |
42575 | last_op_for_exception_3 = opcode; | |
42576 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
42577 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
42578 | goto endlabel2362; | |
42579 | } | |
42580 | {{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = m68k_read_memory_32(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; } | |
42581 | while (amask) { m68k_areg(regs, movem_index1[amask]) = m68k_read_memory_32(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; } | |
42582 | }}}}m68k_incpc(6); | |
42583 | fill_prefetch_0 (); | |
42584 | endlabel2362: ; | |
42585 | return (16+retcycles); | |
42586 | } | |
42587 | unsigned long CPUFUNC(op_4cf0_5)(uint32_t opcode) /* MVMEL */ | |
42588 | { | |
42589 | uint32_t dstreg = opcode & 7; | |
42590 | unsigned int retcycles = 0; | |
42591 | OpcodeFamily = 37; CurrentInstrCycles = 18; | |
42592 | { uint16_t mask = get_iword_prefetch(2); | |
42593 | unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; | |
42594 | retcycles = 0; | |
42595 | { uint32_t srca = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(4)); | |
42596 | BusCyclePenalty += 2; | |
42597 | if ((srca & 1) != 0) { | |
42598 | last_fault_for_exception_3 = srca; | |
42599 | last_op_for_exception_3 = opcode; | |
42600 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
42601 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
42602 | goto endlabel2363; | |
42603 | } | |
42604 | {{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = m68k_read_memory_32(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; } | |
42605 | while (amask) { m68k_areg(regs, movem_index1[amask]) = m68k_read_memory_32(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; } | |
42606 | }}}}m68k_incpc(6); | |
42607 | fill_prefetch_0 (); | |
42608 | endlabel2363: ; | |
42609 | return (18+retcycles); | |
42610 | } | |
42611 | unsigned long CPUFUNC(op_4cf8_5)(uint32_t opcode) /* MVMEL */ | |
42612 | { | |
42613 | unsigned int retcycles = 0; | |
42614 | OpcodeFamily = 37; CurrentInstrCycles = 16; | |
42615 | { uint16_t mask = get_iword_prefetch(2); | |
42616 | unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; | |
42617 | retcycles = 0; | |
42618 | { uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(4); | |
42619 | if ((srca & 1) != 0) { | |
42620 | last_fault_for_exception_3 = srca; | |
42621 | last_op_for_exception_3 = opcode; | |
42622 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
42623 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
42624 | goto endlabel2364; | |
42625 | } | |
42626 | {{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = m68k_read_memory_32(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; } | |
42627 | while (amask) { m68k_areg(regs, movem_index1[amask]) = m68k_read_memory_32(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; } | |
42628 | }}}}m68k_incpc(6); | |
42629 | fill_prefetch_0 (); | |
42630 | endlabel2364: ; | |
42631 | return (16+retcycles); | |
42632 | } | |
42633 | unsigned long CPUFUNC(op_4cf9_5)(uint32_t opcode) /* MVMEL */ | |
42634 | { | |
42635 | unsigned int retcycles = 0; | |
42636 | OpcodeFamily = 37; CurrentInstrCycles = 20; | |
42637 | { uint16_t mask = get_iword_prefetch(2); | |
42638 | unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; | |
42639 | retcycles = 0; | |
42640 | { uint32_t srca = get_ilong_prefetch(4); | |
42641 | if ((srca & 1) != 0) { | |
42642 | last_fault_for_exception_3 = srca; | |
42643 | last_op_for_exception_3 = opcode; | |
42644 | last_addr_for_exception_3 = m68k_getpc() + 8; | |
42645 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
42646 | goto endlabel2365; | |
42647 | } | |
42648 | {{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = m68k_read_memory_32(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; } | |
42649 | while (amask) { m68k_areg(regs, movem_index1[amask]) = m68k_read_memory_32(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; } | |
42650 | }}}}m68k_incpc(8); | |
42651 | fill_prefetch_0 (); | |
42652 | endlabel2365: ; | |
42653 | return (20+retcycles); | |
42654 | } | |
42655 | unsigned long CPUFUNC(op_4cfa_5)(uint32_t opcode) /* MVMEL */ | |
42656 | { | |
42657 | uint32_t dstreg = 2; | |
42658 | unsigned int retcycles = 0; | |
42659 | OpcodeFamily = 37; CurrentInstrCycles = 16; | |
42660 | { uint16_t mask = get_iword_prefetch(2); | |
42661 | unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; | |
42662 | retcycles = 0; | |
42663 | { uint32_t srca = m68k_getpc () + 4; | |
42664 | srca += (int32_t)(int16_t)get_iword_prefetch(4); | |
42665 | if ((srca & 1) != 0) { | |
42666 | last_fault_for_exception_3 = srca; | |
42667 | last_op_for_exception_3 = opcode; | |
42668 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
42669 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
42670 | goto endlabel2366; | |
42671 | } | |
42672 | {{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = m68k_read_memory_32(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; } | |
42673 | while (amask) { m68k_areg(regs, movem_index1[amask]) = m68k_read_memory_32(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; } | |
42674 | }}}}m68k_incpc(6); | |
42675 | fill_prefetch_0 (); | |
42676 | endlabel2366: ; | |
42677 | return (16+retcycles); | |
42678 | } | |
42679 | unsigned long CPUFUNC(op_4cfb_5)(uint32_t opcode) /* MVMEL */ | |
42680 | { | |
42681 | uint32_t dstreg = 3; | |
42682 | unsigned int retcycles = 0; | |
42683 | OpcodeFamily = 37; CurrentInstrCycles = 18; | |
42684 | { uint16_t mask = get_iword_prefetch(2); | |
42685 | unsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff; | |
42686 | retcycles = 0; | |
42687 | { uint32_t tmppc = m68k_getpc() + 4; | |
42688 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(4)); | |
42689 | BusCyclePenalty += 2; | |
42690 | if ((srca & 1) != 0) { | |
42691 | last_fault_for_exception_3 = srca; | |
42692 | last_op_for_exception_3 = opcode; | |
42693 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
42694 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
42695 | goto endlabel2367; | |
42696 | } | |
42697 | {{ while (dmask) { m68k_dreg(regs, movem_index1[dmask]) = m68k_read_memory_32(srca); srca += 4; dmask = movem_next[dmask]; retcycles+=8; } | |
42698 | while (amask) { m68k_areg(regs, movem_index1[amask]) = m68k_read_memory_32(srca); srca += 4; amask = movem_next[amask]; retcycles+=8; } | |
42699 | }}}}m68k_incpc(6); | |
42700 | fill_prefetch_0 (); | |
42701 | endlabel2367: ; | |
42702 | return (18+retcycles); | |
42703 | } | |
42704 | unsigned long CPUFUNC(op_4e40_5)(uint32_t opcode) /* TRAP */ | |
42705 | { | |
42706 | uint32_t srcreg = (opcode & 15); | |
42707 | OpcodeFamily = 39; CurrentInstrCycles = 4; | |
42708 | {{ uint32_t src = srcreg; | |
42709 | m68k_incpc(2); | |
42710 | fill_prefetch_2 (); | |
42711 | Exception(src+32,0,M68000_EXC_SRC_CPU); | |
42712 | }}return 4; | |
42713 | } | |
42714 | unsigned long CPUFUNC(op_4e50_5)(uint32_t opcode) /* LINK */ | |
42715 | { | |
42716 | uint32_t srcreg = (opcode & 7); | |
42717 | OpcodeFamily = 47; CurrentInstrCycles = 18; | |
42718 | {{ uint32_t olda = m68k_areg(regs, 7) - 4; | |
42719 | if ((olda & 1) != 0) { | |
42720 | last_fault_for_exception_3 = olda; | |
42721 | last_op_for_exception_3 = opcode; | |
42722 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
42723 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
42724 | goto endlabel2369; | |
42725 | } | |
42726 | { m68k_areg (regs, 7) = olda; | |
42727 | { int32_t src = m68k_areg(regs, srcreg); | |
42728 | m68k_incpc(2); | |
42729 | fill_prefetch_2 (); | |
42730 | m68k_write_memory_32(olda,src); | |
42731 | m68k_areg(regs, srcreg) = (m68k_areg(regs, 7)); | |
42732 | { int16_t offs = get_iword_prefetch(0); | |
42733 | m68k_areg(regs, 7) += offs; | |
42734 | }}}}}m68k_incpc(2); | |
42735 | fill_prefetch_2 (); | |
42736 | endlabel2369: ; | |
42737 | return 18; | |
42738 | } | |
42739 | unsigned long CPUFUNC(op_4e58_5)(uint32_t opcode) /* UNLK */ | |
42740 | { | |
42741 | uint32_t srcreg = (opcode & 7); | |
42742 | OpcodeFamily = 48; CurrentInstrCycles = 12; | |
42743 | {{ int32_t src = m68k_areg(regs, srcreg); | |
42744 | m68k_areg(regs, 7) = src; | |
42745 | { uint32_t olda = m68k_areg(regs, 7); | |
42746 | if ((olda & 1) != 0) { | |
42747 | last_fault_for_exception_3 = olda; | |
42748 | last_op_for_exception_3 = opcode; | |
42749 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
42750 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
42751 | goto endlabel2370; | |
42752 | } | |
42753 | {{ int32_t old = m68k_read_memory_32(olda); | |
42754 | m68k_areg(regs, 7) += 4; | |
42755 | m68k_areg(regs, srcreg) = (old); | |
42756 | }}}}}m68k_incpc(2); | |
42757 | fill_prefetch_2 (); | |
42758 | endlabel2370: ; | |
42759 | return 12; | |
42760 | } | |
42761 | unsigned long CPUFUNC(op_4e60_5)(uint32_t opcode) /* MVR2USP */ | |
42762 | { | |
42763 | uint32_t srcreg = (opcode & 7); | |
42764 | OpcodeFamily = 40; CurrentInstrCycles = 4; | |
42765 | {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2371; } | |
42766 | {{ int32_t src = m68k_areg(regs, srcreg); | |
42767 | regs.usp = src; | |
42768 | }}}m68k_incpc(2); | |
42769 | fill_prefetch_2 (); | |
42770 | endlabel2371: ; | |
42771 | return 4; | |
42772 | } | |
42773 | unsigned long CPUFUNC(op_4e68_5)(uint32_t opcode) /* MVUSP2R */ | |
42774 | { | |
42775 | uint32_t srcreg = (opcode & 7); | |
42776 | OpcodeFamily = 41; CurrentInstrCycles = 4; | |
42777 | {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2372; } | |
42778 | {{ m68k_areg(regs, srcreg) = (regs.usp); | |
42779 | }}}m68k_incpc(2); | |
42780 | fill_prefetch_2 (); | |
42781 | endlabel2372: ; | |
42782 | return 4; | |
42783 | } | |
42784 | unsigned long CPUFUNC(op_4e70_5)(uint32_t opcode) /* RESET */ | |
42785 | { | |
42786 | OpcodeFamily = 42; CurrentInstrCycles = 132; | |
42787 | {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2373; } | |
42788 | {}}m68k_incpc(2); | |
42789 | fill_prefetch_2 (); | |
42790 | endlabel2373: ; | |
42791 | return 132; | |
42792 | } | |
42793 | unsigned long CPUFUNC(op_4e71_5)(uint32_t opcode) /* NOP */ | |
42794 | { | |
42795 | OpcodeFamily = 43; CurrentInstrCycles = 4; | |
42796 | {}m68k_incpc(2); | |
42797 | fill_prefetch_2 (); | |
42798 | return 4; | |
42799 | } | |
42800 | unsigned long CPUFUNC(op_4e72_5)(uint32_t opcode) /* STOP */ | |
42801 | { | |
42802 | OpcodeFamily = 44; CurrentInstrCycles = 4; | |
42803 | {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2375; } | |
42804 | {{ int16_t src = get_iword_prefetch(2); | |
42805 | regs.sr = src; | |
42806 | MakeFromSR(); | |
42807 | m68k_setstopped(1); | |
42808 | }}}m68k_incpc(4); | |
42809 | fill_prefetch_0 (); | |
42810 | endlabel2375: ; | |
42811 | return 4; | |
42812 | } | |
42813 | unsigned long CPUFUNC(op_4e73_5)(uint32_t opcode) /* RTE */ | |
42814 | { | |
42815 | OpcodeFamily = 45; CurrentInstrCycles = 20; | |
42816 | {if (!regs.s) { Exception(8,0,M68000_EXC_SRC_CPU); goto endlabel2376; } | |
42817 | {{ uint32_t sra = m68k_areg(regs, 7); | |
42818 | if ((sra & 1) != 0) { | |
42819 | last_fault_for_exception_3 = sra; | |
42820 | last_op_for_exception_3 = opcode; | |
42821 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
42822 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
42823 | goto endlabel2376; | |
42824 | } | |
42825 | {{ int16_t sr = m68k_read_memory_16(sra); | |
42826 | m68k_areg(regs, 7) += 2; | |
42827 | { uint32_t pca = m68k_areg(regs, 7); | |
42828 | if ((pca & 1) != 0) { | |
42829 | last_fault_for_exception_3 = pca; | |
42830 | last_op_for_exception_3 = opcode; | |
42831 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
42832 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
42833 | goto endlabel2376; | |
42834 | } | |
42835 | {{ int32_t pc = m68k_read_memory_32(pca); | |
42836 | m68k_areg(regs, 7) += 4; | |
42837 | regs.sr = sr; m68k_setpc_rte(pc); | |
42838 | fill_prefetch_0 (); | |
42839 | MakeFromSR(); | |
42840 | }}}}}}}}endlabel2376: ; | |
42841 | return 20; | |
42842 | } | |
42843 | unsigned long CPUFUNC(op_4e74_5)(uint32_t opcode) /* RTD */ | |
42844 | { | |
42845 | OpcodeFamily = 46; CurrentInstrCycles = 16; | |
42846 | {{ uint32_t pca = m68k_areg(regs, 7); | |
42847 | if ((pca & 1) != 0) { | |
42848 | last_fault_for_exception_3 = pca; | |
42849 | last_op_for_exception_3 = opcode; | |
42850 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
42851 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
42852 | goto endlabel2377; | |
42853 | } | |
42854 | {{ int32_t pc = m68k_read_memory_32(pca); | |
42855 | m68k_areg(regs, 7) += 4; | |
42856 | { int16_t offs = get_iword_prefetch(2); | |
42857 | m68k_areg(regs, 7) += offs; | |
42858 | m68k_setpc_rte(pc); | |
42859 | fill_prefetch_0 (); | |
42860 | }}}}}endlabel2377: ; | |
42861 | return 16; | |
42862 | } | |
42863 | unsigned long CPUFUNC(op_4e75_5)(uint32_t opcode) /* RTS */ | |
42864 | { | |
42865 | OpcodeFamily = 49; CurrentInstrCycles = 16; | |
42866 | { m68k_do_rts(); | |
42867 | fill_prefetch_0 (); | |
42868 | }return 16; | |
42869 | } | |
42870 | unsigned long CPUFUNC(op_4e76_5)(uint32_t opcode) /* TRAPV */ | |
42871 | { | |
42872 | OpcodeFamily = 50; CurrentInstrCycles = 4; | |
42873 | {m68k_incpc(2); | |
42874 | fill_prefetch_2 (); | |
42875 | if (GET_VFLG) { Exception(7,m68k_getpc(),M68000_EXC_SRC_CPU); goto endlabel2379; } | |
42876 | }endlabel2379: ; | |
42877 | return 4; | |
42878 | } | |
42879 | unsigned long CPUFUNC(op_4e77_5)(uint32_t opcode) /* RTR */ | |
42880 | { | |
42881 | OpcodeFamily = 51; CurrentInstrCycles = 20; | |
42882 | { MakeSR(); | |
42883 | { uint32_t sra = m68k_areg(regs, 7); | |
42884 | if ((sra & 1) != 0) { | |
42885 | last_fault_for_exception_3 = sra; | |
42886 | last_op_for_exception_3 = opcode; | |
42887 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
42888 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
42889 | goto endlabel2380; | |
42890 | } | |
42891 | {{ int16_t sr = m68k_read_memory_16(sra); | |
42892 | m68k_areg(regs, 7) += 2; | |
42893 | { uint32_t pca = m68k_areg(regs, 7); | |
42894 | if ((pca & 1) != 0) { | |
42895 | last_fault_for_exception_3 = pca; | |
42896 | last_op_for_exception_3 = opcode; | |
42897 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
42898 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
42899 | goto endlabel2380; | |
42900 | } | |
42901 | {{ int32_t pc = m68k_read_memory_32(pca); | |
42902 | m68k_areg(regs, 7) += 4; | |
42903 | regs.sr &= 0xFF00; sr &= 0xFF; | |
42904 | regs.sr |= sr; m68k_setpc(pc); | |
42905 | fill_prefetch_0 (); | |
42906 | MakeFromSR(); | |
42907 | }}}}}}}endlabel2380: ; | |
42908 | return 20; | |
42909 | } | |
42910 | unsigned long CPUFUNC(op_4e90_5)(uint32_t opcode) /* JSR */ | |
42911 | { | |
42912 | uint32_t srcreg = (opcode & 7); | |
42913 | OpcodeFamily = 52; CurrentInstrCycles = 16; | |
42914 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
42915 | uint32_t oldpc = m68k_getpc () + 2; | |
42916 | if (srca & 1) { | |
42917 | last_addr_for_exception_3 = oldpc; | |
42918 | last_fault_for_exception_3 = srca; | |
42919 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2381; | |
42920 | } | |
42921 | m68k_do_jsr(m68k_getpc() + 2, srca); | |
42922 | fill_prefetch_0 (); | |
42923 | }}endlabel2381: ; | |
42924 | return 16; | |
42925 | } | |
42926 | unsigned long CPUFUNC(op_4ea8_5)(uint32_t opcode) /* JSR */ | |
42927 | { | |
42928 | uint32_t srcreg = (opcode & 7); | |
42929 | OpcodeFamily = 52; CurrentInstrCycles = 18; | |
42930 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
42931 | uint32_t oldpc = m68k_getpc () + 4; | |
42932 | if (srca & 1) { | |
42933 | last_addr_for_exception_3 = oldpc; | |
42934 | last_fault_for_exception_3 = srca; | |
42935 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2382; | |
42936 | } | |
42937 | m68k_do_jsr(m68k_getpc() + 4, srca); | |
42938 | fill_prefetch_0 (); | |
42939 | }}endlabel2382: ; | |
42940 | return 18; | |
42941 | } | |
42942 | unsigned long CPUFUNC(op_4eb0_5)(uint32_t opcode) /* JSR */ | |
42943 | { | |
42944 | uint32_t srcreg = (opcode & 7); | |
42945 | OpcodeFamily = 52; CurrentInstrCycles = 22; | |
42946 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
42947 | BusCyclePenalty += 2; | |
42948 | uint32_t oldpc = m68k_getpc () + 4; | |
42949 | if (srca & 1) { | |
42950 | last_addr_for_exception_3 = oldpc; | |
42951 | last_fault_for_exception_3 = srca; | |
42952 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2383; | |
42953 | } | |
42954 | m68k_do_jsr(m68k_getpc() + 4, srca); | |
42955 | fill_prefetch_0 (); | |
42956 | }}endlabel2383: ; | |
42957 | return 22; | |
42958 | } | |
42959 | unsigned long CPUFUNC(op_4eb8_5)(uint32_t opcode) /* JSR */ | |
42960 | { | |
42961 | OpcodeFamily = 52; CurrentInstrCycles = 18; | |
42962 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
42963 | uint32_t oldpc = m68k_getpc () + 4; | |
42964 | if (srca & 1) { | |
42965 | last_addr_for_exception_3 = oldpc; | |
42966 | last_fault_for_exception_3 = srca; | |
42967 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2384; | |
42968 | } | |
42969 | m68k_do_jsr(m68k_getpc() + 4, srca); | |
42970 | fill_prefetch_0 (); | |
42971 | }}endlabel2384: ; | |
42972 | return 18; | |
42973 | } | |
42974 | unsigned long CPUFUNC(op_4eb9_5)(uint32_t opcode) /* JSR */ | |
42975 | { | |
42976 | OpcodeFamily = 52; CurrentInstrCycles = 20; | |
42977 | {{ uint32_t srca = get_ilong_prefetch(2); | |
42978 | uint32_t oldpc = m68k_getpc () + 6; | |
42979 | if (srca & 1) { | |
42980 | last_addr_for_exception_3 = oldpc; | |
42981 | last_fault_for_exception_3 = srca; | |
42982 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2385; | |
42983 | } | |
42984 | m68k_do_jsr(m68k_getpc() + 6, srca); | |
42985 | fill_prefetch_0 (); | |
42986 | }}endlabel2385: ; | |
42987 | return 20; | |
42988 | } | |
42989 | unsigned long CPUFUNC(op_4eba_5)(uint32_t opcode) /* JSR */ | |
42990 | { | |
42991 | OpcodeFamily = 52; CurrentInstrCycles = 18; | |
42992 | {{ uint32_t srca = m68k_getpc () + 2; | |
42993 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
42994 | uint32_t oldpc = m68k_getpc () + 4; | |
42995 | if (srca & 1) { | |
42996 | last_addr_for_exception_3 = oldpc; | |
42997 | last_fault_for_exception_3 = srca; | |
42998 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2386; | |
42999 | } | |
43000 | m68k_do_jsr(m68k_getpc() + 4, srca); | |
43001 | fill_prefetch_0 (); | |
43002 | }}endlabel2386: ; | |
43003 | return 18; | |
43004 | } | |
43005 | unsigned long CPUFUNC(op_4ebb_5)(uint32_t opcode) /* JSR */ | |
43006 | { | |
43007 | OpcodeFamily = 52; CurrentInstrCycles = 22; | |
43008 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
43009 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
43010 | BusCyclePenalty += 2; | |
43011 | uint32_t oldpc = m68k_getpc () + 4; | |
43012 | if (srca & 1) { | |
43013 | last_addr_for_exception_3 = oldpc; | |
43014 | last_fault_for_exception_3 = srca; | |
43015 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2387; | |
43016 | } | |
43017 | m68k_do_jsr(m68k_getpc() + 4, srca); | |
43018 | fill_prefetch_0 (); | |
43019 | }}endlabel2387: ; | |
43020 | return 22; | |
43021 | } | |
43022 | unsigned long CPUFUNC(op_4ed0_5)(uint32_t opcode) /* JMP */ | |
43023 | { | |
43024 | uint32_t srcreg = (opcode & 7); | |
43025 | OpcodeFamily = 53; CurrentInstrCycles = 8; | |
43026 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
43027 | if (srca & 1) { | |
43028 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
43029 | last_fault_for_exception_3 = srca; | |
43030 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2388; | |
43031 | } | |
43032 | m68k_setpc(srca); | |
43033 | fill_prefetch_0 (); | |
43034 | }}endlabel2388: ; | |
43035 | return 8; | |
43036 | } | |
43037 | unsigned long CPUFUNC(op_4ee8_5)(uint32_t opcode) /* JMP */ | |
43038 | { | |
43039 | uint32_t srcreg = (opcode & 7); | |
43040 | OpcodeFamily = 53; CurrentInstrCycles = 10; | |
43041 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
43042 | if (srca & 1) { | |
43043 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
43044 | last_fault_for_exception_3 = srca; | |
43045 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2389; | |
43046 | } | |
43047 | m68k_setpc(srca); | |
43048 | fill_prefetch_0 (); | |
43049 | }}endlabel2389: ; | |
43050 | return 10; | |
43051 | } | |
43052 | unsigned long CPUFUNC(op_4ef0_5)(uint32_t opcode) /* JMP */ | |
43053 | { | |
43054 | uint32_t srcreg = (opcode & 7); | |
43055 | OpcodeFamily = 53; CurrentInstrCycles = 14; | |
43056 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
43057 | BusCyclePenalty += 2; | |
43058 | if (srca & 1) { | |
43059 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
43060 | last_fault_for_exception_3 = srca; | |
43061 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2390; | |
43062 | } | |
43063 | m68k_setpc(srca); | |
43064 | fill_prefetch_0 (); | |
43065 | }}endlabel2390: ; | |
43066 | return 14; | |
43067 | } | |
43068 | unsigned long CPUFUNC(op_4ef8_5)(uint32_t opcode) /* JMP */ | |
43069 | { | |
43070 | OpcodeFamily = 53; CurrentInstrCycles = 10; | |
43071 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
43072 | if (srca & 1) { | |
43073 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
43074 | last_fault_for_exception_3 = srca; | |
43075 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2391; | |
43076 | } | |
43077 | m68k_setpc(srca); | |
43078 | fill_prefetch_0 (); | |
43079 | }}endlabel2391: ; | |
43080 | return 10; | |
43081 | } | |
43082 | unsigned long CPUFUNC(op_4ef9_5)(uint32_t opcode) /* JMP */ | |
43083 | { | |
43084 | OpcodeFamily = 53; CurrentInstrCycles = 12; | |
43085 | {{ uint32_t srca = get_ilong_prefetch(2); | |
43086 | if (srca & 1) { | |
43087 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
43088 | last_fault_for_exception_3 = srca; | |
43089 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2392; | |
43090 | } | |
43091 | m68k_setpc(srca); | |
43092 | fill_prefetch_0 (); | |
43093 | }}endlabel2392: ; | |
43094 | return 12; | |
43095 | } | |
43096 | unsigned long CPUFUNC(op_4efa_5)(uint32_t opcode) /* JMP */ | |
43097 | { | |
43098 | OpcodeFamily = 53; CurrentInstrCycles = 10; | |
43099 | {{ uint32_t srca = m68k_getpc () + 2; | |
43100 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
43101 | if (srca & 1) { | |
43102 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
43103 | last_fault_for_exception_3 = srca; | |
43104 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2393; | |
43105 | } | |
43106 | m68k_setpc(srca); | |
43107 | fill_prefetch_0 (); | |
43108 | }}endlabel2393: ; | |
43109 | return 10; | |
43110 | } | |
43111 | unsigned long CPUFUNC(op_4efb_5)(uint32_t opcode) /* JMP */ | |
43112 | { | |
43113 | OpcodeFamily = 53; CurrentInstrCycles = 14; | |
43114 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
43115 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
43116 | BusCyclePenalty += 2; | |
43117 | if (srca & 1) { | |
43118 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
43119 | last_fault_for_exception_3 = srca; | |
43120 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2394; | |
43121 | } | |
43122 | m68k_setpc(srca); | |
43123 | fill_prefetch_0 (); | |
43124 | }}endlabel2394: ; | |
43125 | return 14; | |
43126 | } | |
43127 | unsigned long CPUFUNC(op_5000_5)(uint32_t opcode) /* ADD */ | |
43128 | { | |
43129 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
43130 | uint32_t dstreg = opcode & 7; | |
43131 | OpcodeFamily = 11; CurrentInstrCycles = 4; | |
43132 | {{ uint32_t src = srcreg; | |
43133 | { int8_t dst = m68k_dreg(regs, dstreg); | |
43134 | { refill_prefetch (m68k_getpc(), 2); | |
43135 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
43136 | { int flgs = ((int8_t)(src)) < 0; | |
43137 | int flgo = ((int8_t)(dst)) < 0; | |
43138 | int flgn = ((int8_t)(newv)) < 0; | |
43139 | SET_ZFLG (((int8_t)(newv)) == 0); | |
43140 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
43141 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
43142 | COPY_CARRY; | |
43143 | SET_NFLG (flgn != 0); | |
43144 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
43145 | }}}}}}m68k_incpc(2); | |
43146 | fill_prefetch_2 (); | |
43147 | return 4; | |
43148 | } | |
43149 | unsigned long CPUFUNC(op_5010_5)(uint32_t opcode) /* ADD */ | |
43150 | { | |
43151 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
43152 | uint32_t dstreg = opcode & 7; | |
43153 | OpcodeFamily = 11; CurrentInstrCycles = 12; | |
43154 | {{ uint32_t src = srcreg; | |
43155 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
43156 | { int8_t dst = m68k_read_memory_8(dsta); | |
43157 | { refill_prefetch (m68k_getpc(), 2); | |
43158 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
43159 | { int flgs = ((int8_t)(src)) < 0; | |
43160 | int flgo = ((int8_t)(dst)) < 0; | |
43161 | int flgn = ((int8_t)(newv)) < 0; | |
43162 | SET_ZFLG (((int8_t)(newv)) == 0); | |
43163 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
43164 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
43165 | COPY_CARRY; | |
43166 | SET_NFLG (flgn != 0); | |
43167 | m68k_incpc(2); | |
43168 | fill_prefetch_2 (); | |
43169 | m68k_write_memory_8(dsta,newv); | |
43170 | }}}}}}}return 12; | |
43171 | } | |
43172 | unsigned long CPUFUNC(op_5018_5)(uint32_t opcode) /* ADD */ | |
43173 | { | |
43174 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
43175 | uint32_t dstreg = opcode & 7; | |
43176 | OpcodeFamily = 11; CurrentInstrCycles = 12; | |
43177 | {{ uint32_t src = srcreg; | |
43178 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
43179 | { int8_t dst = m68k_read_memory_8(dsta); | |
43180 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
43181 | { refill_prefetch (m68k_getpc(), 2); | |
43182 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
43183 | { int flgs = ((int8_t)(src)) < 0; | |
43184 | int flgo = ((int8_t)(dst)) < 0; | |
43185 | int flgn = ((int8_t)(newv)) < 0; | |
43186 | SET_ZFLG (((int8_t)(newv)) == 0); | |
43187 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
43188 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
43189 | COPY_CARRY; | |
43190 | SET_NFLG (flgn != 0); | |
43191 | m68k_incpc(2); | |
43192 | fill_prefetch_2 (); | |
43193 | m68k_write_memory_8(dsta,newv); | |
43194 | }}}}}}}return 12; | |
43195 | } | |
43196 | #endif | |
43197 | ||
43198 | #ifdef PART_5 | |
43199 | unsigned long CPUFUNC(op_5020_5)(uint32_t opcode) /* ADD */ | |
43200 | { | |
43201 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
43202 | uint32_t dstreg = opcode & 7; | |
43203 | OpcodeFamily = 11; CurrentInstrCycles = 14; | |
43204 | {{ uint32_t src = srcreg; | |
43205 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
43206 | { int8_t dst = m68k_read_memory_8(dsta); | |
43207 | m68k_areg (regs, dstreg) = dsta; | |
43208 | { refill_prefetch (m68k_getpc(), 2); | |
43209 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
43210 | { int flgs = ((int8_t)(src)) < 0; | |
43211 | int flgo = ((int8_t)(dst)) < 0; | |
43212 | int flgn = ((int8_t)(newv)) < 0; | |
43213 | SET_ZFLG (((int8_t)(newv)) == 0); | |
43214 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
43215 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
43216 | COPY_CARRY; | |
43217 | SET_NFLG (flgn != 0); | |
43218 | m68k_incpc(2); | |
43219 | fill_prefetch_2 (); | |
43220 | m68k_write_memory_8(dsta,newv); | |
43221 | }}}}}}}return 14; | |
43222 | } | |
43223 | unsigned long CPUFUNC(op_5028_5)(uint32_t opcode) /* ADD */ | |
43224 | { | |
43225 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
43226 | uint32_t dstreg = opcode & 7; | |
43227 | OpcodeFamily = 11; CurrentInstrCycles = 16; | |
43228 | {{ uint32_t src = srcreg; | |
43229 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
43230 | { int8_t dst = m68k_read_memory_8(dsta); | |
43231 | { refill_prefetch (m68k_getpc(), 2); | |
43232 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
43233 | { int flgs = ((int8_t)(src)) < 0; | |
43234 | int flgo = ((int8_t)(dst)) < 0; | |
43235 | int flgn = ((int8_t)(newv)) < 0; | |
43236 | SET_ZFLG (((int8_t)(newv)) == 0); | |
43237 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
43238 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
43239 | COPY_CARRY; | |
43240 | SET_NFLG (flgn != 0); | |
43241 | m68k_incpc(4); | |
43242 | fill_prefetch_0 (); | |
43243 | m68k_write_memory_8(dsta,newv); | |
43244 | }}}}}}}return 16; | |
43245 | } | |
43246 | unsigned long CPUFUNC(op_5030_5)(uint32_t opcode) /* ADD */ | |
43247 | { | |
43248 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
43249 | uint32_t dstreg = opcode & 7; | |
43250 | OpcodeFamily = 11; CurrentInstrCycles = 18; | |
43251 | {{ uint32_t src = srcreg; | |
43252 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); | |
43253 | BusCyclePenalty += 2; | |
43254 | { int8_t dst = m68k_read_memory_8(dsta); | |
43255 | { refill_prefetch (m68k_getpc(), 2); | |
43256 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
43257 | { int flgs = ((int8_t)(src)) < 0; | |
43258 | int flgo = ((int8_t)(dst)) < 0; | |
43259 | int flgn = ((int8_t)(newv)) < 0; | |
43260 | SET_ZFLG (((int8_t)(newv)) == 0); | |
43261 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
43262 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
43263 | COPY_CARRY; | |
43264 | SET_NFLG (flgn != 0); | |
43265 | m68k_incpc(4); | |
43266 | fill_prefetch_0 (); | |
43267 | m68k_write_memory_8(dsta,newv); | |
43268 | }}}}}}}return 18; | |
43269 | } | |
43270 | unsigned long CPUFUNC(op_5038_5)(uint32_t opcode) /* ADD */ | |
43271 | { | |
43272 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
43273 | OpcodeFamily = 11; CurrentInstrCycles = 16; | |
43274 | {{ uint32_t src = srcreg; | |
43275 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); | |
43276 | { int8_t dst = m68k_read_memory_8(dsta); | |
43277 | { refill_prefetch (m68k_getpc(), 2); | |
43278 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
43279 | { int flgs = ((int8_t)(src)) < 0; | |
43280 | int flgo = ((int8_t)(dst)) < 0; | |
43281 | int flgn = ((int8_t)(newv)) < 0; | |
43282 | SET_ZFLG (((int8_t)(newv)) == 0); | |
43283 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
43284 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
43285 | COPY_CARRY; | |
43286 | SET_NFLG (flgn != 0); | |
43287 | m68k_incpc(4); | |
43288 | fill_prefetch_0 (); | |
43289 | m68k_write_memory_8(dsta,newv); | |
43290 | }}}}}}}return 16; | |
43291 | } | |
43292 | unsigned long CPUFUNC(op_5039_5)(uint32_t opcode) /* ADD */ | |
43293 | { | |
43294 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
43295 | OpcodeFamily = 11; CurrentInstrCycles = 20; | |
43296 | {{ uint32_t src = srcreg; | |
43297 | { uint32_t dsta = get_ilong_prefetch(2); | |
43298 | { int8_t dst = m68k_read_memory_8(dsta); | |
43299 | { refill_prefetch (m68k_getpc(), 2); | |
43300 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
43301 | { int flgs = ((int8_t)(src)) < 0; | |
43302 | int flgo = ((int8_t)(dst)) < 0; | |
43303 | int flgn = ((int8_t)(newv)) < 0; | |
43304 | SET_ZFLG (((int8_t)(newv)) == 0); | |
43305 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
43306 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
43307 | COPY_CARRY; | |
43308 | SET_NFLG (flgn != 0); | |
43309 | m68k_incpc(6); | |
43310 | fill_prefetch_0 (); | |
43311 | m68k_write_memory_8(dsta,newv); | |
43312 | }}}}}}}return 20; | |
43313 | } | |
43314 | unsigned long CPUFUNC(op_5040_5)(uint32_t opcode) /* ADD */ | |
43315 | { | |
43316 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
43317 | uint32_t dstreg = opcode & 7; | |
43318 | OpcodeFamily = 11; CurrentInstrCycles = 4; | |
43319 | {{ uint32_t src = srcreg; | |
43320 | { int16_t dst = m68k_dreg(regs, dstreg); | |
43321 | { refill_prefetch (m68k_getpc(), 2); | |
43322 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
43323 | { int flgs = ((int16_t)(src)) < 0; | |
43324 | int flgo = ((int16_t)(dst)) < 0; | |
43325 | int flgn = ((int16_t)(newv)) < 0; | |
43326 | SET_ZFLG (((int16_t)(newv)) == 0); | |
43327 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
43328 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
43329 | COPY_CARRY; | |
43330 | SET_NFLG (flgn != 0); | |
43331 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
43332 | }}}}}}m68k_incpc(2); | |
43333 | fill_prefetch_2 (); | |
43334 | return 4; | |
43335 | } | |
43336 | unsigned long CPUFUNC(op_5048_5)(uint32_t opcode) /* ADDA */ | |
43337 | { | |
43338 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
43339 | uint32_t dstreg = opcode & 7; | |
43340 | OpcodeFamily = 12; CurrentInstrCycles = 8; | |
43341 | {{ uint32_t src = srcreg; | |
43342 | { int32_t dst = m68k_areg(regs, dstreg); | |
43343 | { uint32_t newv = dst + src; | |
43344 | m68k_areg(regs, dstreg) = (newv); | |
43345 | }}}}m68k_incpc(2); | |
43346 | fill_prefetch_2 (); | |
43347 | return 8; | |
43348 | } | |
43349 | unsigned long CPUFUNC(op_5050_5)(uint32_t opcode) /* ADD */ | |
43350 | { | |
43351 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
43352 | uint32_t dstreg = opcode & 7; | |
43353 | OpcodeFamily = 11; CurrentInstrCycles = 12; | |
43354 | {{ uint32_t src = srcreg; | |
43355 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
43356 | if ((dsta & 1) != 0) { | |
43357 | last_fault_for_exception_3 = dsta; | |
43358 | last_op_for_exception_3 = opcode; | |
43359 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
43360 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
43361 | goto endlabel2405; | |
43362 | } | |
43363 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
43364 | { refill_prefetch (m68k_getpc(), 2); | |
43365 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
43366 | { int flgs = ((int16_t)(src)) < 0; | |
43367 | int flgo = ((int16_t)(dst)) < 0; | |
43368 | int flgn = ((int16_t)(newv)) < 0; | |
43369 | SET_ZFLG (((int16_t)(newv)) == 0); | |
43370 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
43371 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
43372 | COPY_CARRY; | |
43373 | SET_NFLG (flgn != 0); | |
43374 | m68k_incpc(2); | |
43375 | fill_prefetch_2 (); | |
43376 | m68k_write_memory_16(dsta,newv); | |
43377 | }}}}}}}}endlabel2405: ; | |
43378 | return 12; | |
43379 | } | |
43380 | unsigned long CPUFUNC(op_5058_5)(uint32_t opcode) /* ADD */ | |
43381 | { | |
43382 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
43383 | uint32_t dstreg = opcode & 7; | |
43384 | OpcodeFamily = 11; CurrentInstrCycles = 12; | |
43385 | {{ uint32_t src = srcreg; | |
43386 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
43387 | if ((dsta & 1) != 0) { | |
43388 | last_fault_for_exception_3 = dsta; | |
43389 | last_op_for_exception_3 = opcode; | |
43390 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
43391 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
43392 | goto endlabel2406; | |
43393 | } | |
43394 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
43395 | m68k_areg(regs, dstreg) += 2; | |
43396 | { refill_prefetch (m68k_getpc(), 2); | |
43397 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
43398 | { int flgs = ((int16_t)(src)) < 0; | |
43399 | int flgo = ((int16_t)(dst)) < 0; | |
43400 | int flgn = ((int16_t)(newv)) < 0; | |
43401 | SET_ZFLG (((int16_t)(newv)) == 0); | |
43402 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
43403 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
43404 | COPY_CARRY; | |
43405 | SET_NFLG (flgn != 0); | |
43406 | m68k_incpc(2); | |
43407 | fill_prefetch_2 (); | |
43408 | m68k_write_memory_16(dsta,newv); | |
43409 | }}}}}}}}endlabel2406: ; | |
43410 | return 12; | |
43411 | } | |
43412 | unsigned long CPUFUNC(op_5060_5)(uint32_t opcode) /* ADD */ | |
43413 | { | |
43414 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
43415 | uint32_t dstreg = opcode & 7; | |
43416 | OpcodeFamily = 11; CurrentInstrCycles = 14; | |
43417 | {{ uint32_t src = srcreg; | |
43418 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
43419 | if ((dsta & 1) != 0) { | |
43420 | last_fault_for_exception_3 = dsta; | |
43421 | last_op_for_exception_3 = opcode; | |
43422 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
43423 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
43424 | goto endlabel2407; | |
43425 | } | |
43426 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
43427 | m68k_areg (regs, dstreg) = dsta; | |
43428 | { refill_prefetch (m68k_getpc(), 2); | |
43429 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
43430 | { int flgs = ((int16_t)(src)) < 0; | |
43431 | int flgo = ((int16_t)(dst)) < 0; | |
43432 | int flgn = ((int16_t)(newv)) < 0; | |
43433 | SET_ZFLG (((int16_t)(newv)) == 0); | |
43434 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
43435 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
43436 | COPY_CARRY; | |
43437 | SET_NFLG (flgn != 0); | |
43438 | m68k_incpc(2); | |
43439 | fill_prefetch_2 (); | |
43440 | m68k_write_memory_16(dsta,newv); | |
43441 | }}}}}}}}endlabel2407: ; | |
43442 | return 14; | |
43443 | } | |
43444 | unsigned long CPUFUNC(op_5068_5)(uint32_t opcode) /* ADD */ | |
43445 | { | |
43446 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
43447 | uint32_t dstreg = opcode & 7; | |
43448 | OpcodeFamily = 11; CurrentInstrCycles = 16; | |
43449 | {{ uint32_t src = srcreg; | |
43450 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
43451 | if ((dsta & 1) != 0) { | |
43452 | last_fault_for_exception_3 = dsta; | |
43453 | last_op_for_exception_3 = opcode; | |
43454 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
43455 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
43456 | goto endlabel2408; | |
43457 | } | |
43458 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
43459 | { refill_prefetch (m68k_getpc(), 2); | |
43460 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
43461 | { int flgs = ((int16_t)(src)) < 0; | |
43462 | int flgo = ((int16_t)(dst)) < 0; | |
43463 | int flgn = ((int16_t)(newv)) < 0; | |
43464 | SET_ZFLG (((int16_t)(newv)) == 0); | |
43465 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
43466 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
43467 | COPY_CARRY; | |
43468 | SET_NFLG (flgn != 0); | |
43469 | m68k_incpc(4); | |
43470 | fill_prefetch_0 (); | |
43471 | m68k_write_memory_16(dsta,newv); | |
43472 | }}}}}}}}endlabel2408: ; | |
43473 | return 16; | |
43474 | } | |
43475 | unsigned long CPUFUNC(op_5070_5)(uint32_t opcode) /* ADD */ | |
43476 | { | |
43477 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
43478 | uint32_t dstreg = opcode & 7; | |
43479 | OpcodeFamily = 11; CurrentInstrCycles = 18; | |
43480 | {{ uint32_t src = srcreg; | |
43481 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); | |
43482 | BusCyclePenalty += 2; | |
43483 | if ((dsta & 1) != 0) { | |
43484 | last_fault_for_exception_3 = dsta; | |
43485 | last_op_for_exception_3 = opcode; | |
43486 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
43487 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
43488 | goto endlabel2409; | |
43489 | } | |
43490 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
43491 | { refill_prefetch (m68k_getpc(), 2); | |
43492 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
43493 | { int flgs = ((int16_t)(src)) < 0; | |
43494 | int flgo = ((int16_t)(dst)) < 0; | |
43495 | int flgn = ((int16_t)(newv)) < 0; | |
43496 | SET_ZFLG (((int16_t)(newv)) == 0); | |
43497 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
43498 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
43499 | COPY_CARRY; | |
43500 | SET_NFLG (flgn != 0); | |
43501 | m68k_incpc(4); | |
43502 | fill_prefetch_0 (); | |
43503 | m68k_write_memory_16(dsta,newv); | |
43504 | }}}}}}}}endlabel2409: ; | |
43505 | return 18; | |
43506 | } | |
43507 | unsigned long CPUFUNC(op_5078_5)(uint32_t opcode) /* ADD */ | |
43508 | { | |
43509 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
43510 | OpcodeFamily = 11; CurrentInstrCycles = 16; | |
43511 | {{ uint32_t src = srcreg; | |
43512 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); | |
43513 | if ((dsta & 1) != 0) { | |
43514 | last_fault_for_exception_3 = dsta; | |
43515 | last_op_for_exception_3 = opcode; | |
43516 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
43517 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
43518 | goto endlabel2410; | |
43519 | } | |
43520 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
43521 | { refill_prefetch (m68k_getpc(), 2); | |
43522 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
43523 | { int flgs = ((int16_t)(src)) < 0; | |
43524 | int flgo = ((int16_t)(dst)) < 0; | |
43525 | int flgn = ((int16_t)(newv)) < 0; | |
43526 | SET_ZFLG (((int16_t)(newv)) == 0); | |
43527 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
43528 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
43529 | COPY_CARRY; | |
43530 | SET_NFLG (flgn != 0); | |
43531 | m68k_incpc(4); | |
43532 | fill_prefetch_0 (); | |
43533 | m68k_write_memory_16(dsta,newv); | |
43534 | }}}}}}}}endlabel2410: ; | |
43535 | return 16; | |
43536 | } | |
43537 | unsigned long CPUFUNC(op_5079_5)(uint32_t opcode) /* ADD */ | |
43538 | { | |
43539 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
43540 | OpcodeFamily = 11; CurrentInstrCycles = 20; | |
43541 | {{ uint32_t src = srcreg; | |
43542 | { uint32_t dsta = get_ilong_prefetch(2); | |
43543 | if ((dsta & 1) != 0) { | |
43544 | last_fault_for_exception_3 = dsta; | |
43545 | last_op_for_exception_3 = opcode; | |
43546 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
43547 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
43548 | goto endlabel2411; | |
43549 | } | |
43550 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
43551 | { refill_prefetch (m68k_getpc(), 2); | |
43552 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
43553 | { int flgs = ((int16_t)(src)) < 0; | |
43554 | int flgo = ((int16_t)(dst)) < 0; | |
43555 | int flgn = ((int16_t)(newv)) < 0; | |
43556 | SET_ZFLG (((int16_t)(newv)) == 0); | |
43557 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
43558 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
43559 | COPY_CARRY; | |
43560 | SET_NFLG (flgn != 0); | |
43561 | m68k_incpc(6); | |
43562 | fill_prefetch_0 (); | |
43563 | m68k_write_memory_16(dsta,newv); | |
43564 | }}}}}}}}endlabel2411: ; | |
43565 | return 20; | |
43566 | } | |
43567 | unsigned long CPUFUNC(op_5080_5)(uint32_t opcode) /* ADD */ | |
43568 | { | |
43569 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
43570 | uint32_t dstreg = opcode & 7; | |
43571 | OpcodeFamily = 11; CurrentInstrCycles = 8; | |
43572 | {{ uint32_t src = srcreg; | |
43573 | { int32_t dst = m68k_dreg(regs, dstreg); | |
43574 | { refill_prefetch (m68k_getpc(), 2); | |
43575 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
43576 | { int flgs = ((int32_t)(src)) < 0; | |
43577 | int flgo = ((int32_t)(dst)) < 0; | |
43578 | int flgn = ((int32_t)(newv)) < 0; | |
43579 | SET_ZFLG (((int32_t)(newv)) == 0); | |
43580 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
43581 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
43582 | COPY_CARRY; | |
43583 | SET_NFLG (flgn != 0); | |
43584 | m68k_dreg(regs, dstreg) = (newv); | |
43585 | }}}}}}m68k_incpc(2); | |
43586 | fill_prefetch_2 (); | |
43587 | return 8; | |
43588 | } | |
43589 | unsigned long CPUFUNC(op_5088_5)(uint32_t opcode) /* ADDA */ | |
43590 | { | |
43591 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
43592 | uint32_t dstreg = opcode & 7; | |
43593 | OpcodeFamily = 12; CurrentInstrCycles = 8; | |
43594 | {{ uint32_t src = srcreg; | |
43595 | { int32_t dst = m68k_areg(regs, dstreg); | |
43596 | { uint32_t newv = dst + src; | |
43597 | m68k_areg(regs, dstreg) = (newv); | |
43598 | }}}}m68k_incpc(2); | |
43599 | fill_prefetch_2 (); | |
43600 | return 8; | |
43601 | } | |
43602 | unsigned long CPUFUNC(op_5090_5)(uint32_t opcode) /* ADD */ | |
43603 | { | |
43604 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
43605 | uint32_t dstreg = opcode & 7; | |
43606 | OpcodeFamily = 11; CurrentInstrCycles = 20; | |
43607 | {{ uint32_t src = srcreg; | |
43608 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
43609 | if ((dsta & 1) != 0) { | |
43610 | last_fault_for_exception_3 = dsta; | |
43611 | last_op_for_exception_3 = opcode; | |
43612 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
43613 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
43614 | goto endlabel2414; | |
43615 | } | |
43616 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
43617 | { refill_prefetch (m68k_getpc(), 2); | |
43618 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
43619 | { int flgs = ((int32_t)(src)) < 0; | |
43620 | int flgo = ((int32_t)(dst)) < 0; | |
43621 | int flgn = ((int32_t)(newv)) < 0; | |
43622 | SET_ZFLG (((int32_t)(newv)) == 0); | |
43623 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
43624 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
43625 | COPY_CARRY; | |
43626 | SET_NFLG (flgn != 0); | |
43627 | m68k_incpc(2); | |
43628 | fill_prefetch_2 (); | |
43629 | m68k_write_memory_32(dsta,newv); | |
43630 | }}}}}}}}endlabel2414: ; | |
43631 | return 20; | |
43632 | } | |
43633 | unsigned long CPUFUNC(op_5098_5)(uint32_t opcode) /* ADD */ | |
43634 | { | |
43635 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
43636 | uint32_t dstreg = opcode & 7; | |
43637 | OpcodeFamily = 11; CurrentInstrCycles = 20; | |
43638 | {{ uint32_t src = srcreg; | |
43639 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
43640 | if ((dsta & 1) != 0) { | |
43641 | last_fault_for_exception_3 = dsta; | |
43642 | last_op_for_exception_3 = opcode; | |
43643 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
43644 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
43645 | goto endlabel2415; | |
43646 | } | |
43647 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
43648 | m68k_areg(regs, dstreg) += 4; | |
43649 | { refill_prefetch (m68k_getpc(), 2); | |
43650 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
43651 | { int flgs = ((int32_t)(src)) < 0; | |
43652 | int flgo = ((int32_t)(dst)) < 0; | |
43653 | int flgn = ((int32_t)(newv)) < 0; | |
43654 | SET_ZFLG (((int32_t)(newv)) == 0); | |
43655 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
43656 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
43657 | COPY_CARRY; | |
43658 | SET_NFLG (flgn != 0); | |
43659 | m68k_incpc(2); | |
43660 | fill_prefetch_2 (); | |
43661 | m68k_write_memory_32(dsta,newv); | |
43662 | }}}}}}}}endlabel2415: ; | |
43663 | return 20; | |
43664 | } | |
43665 | unsigned long CPUFUNC(op_50a0_5)(uint32_t opcode) /* ADD */ | |
43666 | { | |
43667 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
43668 | uint32_t dstreg = opcode & 7; | |
43669 | OpcodeFamily = 11; CurrentInstrCycles = 22; | |
43670 | {{ uint32_t src = srcreg; | |
43671 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
43672 | if ((dsta & 1) != 0) { | |
43673 | last_fault_for_exception_3 = dsta; | |
43674 | last_op_for_exception_3 = opcode; | |
43675 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
43676 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
43677 | goto endlabel2416; | |
43678 | } | |
43679 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
43680 | m68k_areg (regs, dstreg) = dsta; | |
43681 | { refill_prefetch (m68k_getpc(), 2); | |
43682 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
43683 | { int flgs = ((int32_t)(src)) < 0; | |
43684 | int flgo = ((int32_t)(dst)) < 0; | |
43685 | int flgn = ((int32_t)(newv)) < 0; | |
43686 | SET_ZFLG (((int32_t)(newv)) == 0); | |
43687 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
43688 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
43689 | COPY_CARRY; | |
43690 | SET_NFLG (flgn != 0); | |
43691 | m68k_incpc(2); | |
43692 | fill_prefetch_2 (); | |
43693 | m68k_write_memory_32(dsta,newv); | |
43694 | }}}}}}}}endlabel2416: ; | |
43695 | return 22; | |
43696 | } | |
43697 | unsigned long CPUFUNC(op_50a8_5)(uint32_t opcode) /* ADD */ | |
43698 | { | |
43699 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
43700 | uint32_t dstreg = opcode & 7; | |
43701 | OpcodeFamily = 11; CurrentInstrCycles = 24; | |
43702 | {{ uint32_t src = srcreg; | |
43703 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
43704 | if ((dsta & 1) != 0) { | |
43705 | last_fault_for_exception_3 = dsta; | |
43706 | last_op_for_exception_3 = opcode; | |
43707 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
43708 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
43709 | goto endlabel2417; | |
43710 | } | |
43711 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
43712 | { refill_prefetch (m68k_getpc(), 2); | |
43713 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
43714 | { int flgs = ((int32_t)(src)) < 0; | |
43715 | int flgo = ((int32_t)(dst)) < 0; | |
43716 | int flgn = ((int32_t)(newv)) < 0; | |
43717 | SET_ZFLG (((int32_t)(newv)) == 0); | |
43718 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
43719 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
43720 | COPY_CARRY; | |
43721 | SET_NFLG (flgn != 0); | |
43722 | m68k_incpc(4); | |
43723 | fill_prefetch_0 (); | |
43724 | m68k_write_memory_32(dsta,newv); | |
43725 | }}}}}}}}endlabel2417: ; | |
43726 | return 24; | |
43727 | } | |
43728 | unsigned long CPUFUNC(op_50b0_5)(uint32_t opcode) /* ADD */ | |
43729 | { | |
43730 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
43731 | uint32_t dstreg = opcode & 7; | |
43732 | OpcodeFamily = 11; CurrentInstrCycles = 26; | |
43733 | {{ uint32_t src = srcreg; | |
43734 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); | |
43735 | BusCyclePenalty += 2; | |
43736 | if ((dsta & 1) != 0) { | |
43737 | last_fault_for_exception_3 = dsta; | |
43738 | last_op_for_exception_3 = opcode; | |
43739 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
43740 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
43741 | goto endlabel2418; | |
43742 | } | |
43743 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
43744 | { refill_prefetch (m68k_getpc(), 2); | |
43745 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
43746 | { int flgs = ((int32_t)(src)) < 0; | |
43747 | int flgo = ((int32_t)(dst)) < 0; | |
43748 | int flgn = ((int32_t)(newv)) < 0; | |
43749 | SET_ZFLG (((int32_t)(newv)) == 0); | |
43750 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
43751 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
43752 | COPY_CARRY; | |
43753 | SET_NFLG (flgn != 0); | |
43754 | m68k_incpc(4); | |
43755 | fill_prefetch_0 (); | |
43756 | m68k_write_memory_32(dsta,newv); | |
43757 | }}}}}}}}endlabel2418: ; | |
43758 | return 26; | |
43759 | } | |
43760 | unsigned long CPUFUNC(op_50b8_5)(uint32_t opcode) /* ADD */ | |
43761 | { | |
43762 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
43763 | OpcodeFamily = 11; CurrentInstrCycles = 24; | |
43764 | {{ uint32_t src = srcreg; | |
43765 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); | |
43766 | if ((dsta & 1) != 0) { | |
43767 | last_fault_for_exception_3 = dsta; | |
43768 | last_op_for_exception_3 = opcode; | |
43769 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
43770 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
43771 | goto endlabel2419; | |
43772 | } | |
43773 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
43774 | { refill_prefetch (m68k_getpc(), 2); | |
43775 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
43776 | { int flgs = ((int32_t)(src)) < 0; | |
43777 | int flgo = ((int32_t)(dst)) < 0; | |
43778 | int flgn = ((int32_t)(newv)) < 0; | |
43779 | SET_ZFLG (((int32_t)(newv)) == 0); | |
43780 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
43781 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
43782 | COPY_CARRY; | |
43783 | SET_NFLG (flgn != 0); | |
43784 | m68k_incpc(4); | |
43785 | fill_prefetch_0 (); | |
43786 | m68k_write_memory_32(dsta,newv); | |
43787 | }}}}}}}}endlabel2419: ; | |
43788 | return 24; | |
43789 | } | |
43790 | unsigned long CPUFUNC(op_50b9_5)(uint32_t opcode) /* ADD */ | |
43791 | { | |
43792 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
43793 | OpcodeFamily = 11; CurrentInstrCycles = 28; | |
43794 | {{ uint32_t src = srcreg; | |
43795 | { uint32_t dsta = get_ilong_prefetch(2); | |
43796 | if ((dsta & 1) != 0) { | |
43797 | last_fault_for_exception_3 = dsta; | |
43798 | last_op_for_exception_3 = opcode; | |
43799 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
43800 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
43801 | goto endlabel2420; | |
43802 | } | |
43803 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
43804 | { refill_prefetch (m68k_getpc(), 2); | |
43805 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
43806 | { int flgs = ((int32_t)(src)) < 0; | |
43807 | int flgo = ((int32_t)(dst)) < 0; | |
43808 | int flgn = ((int32_t)(newv)) < 0; | |
43809 | SET_ZFLG (((int32_t)(newv)) == 0); | |
43810 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
43811 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
43812 | COPY_CARRY; | |
43813 | SET_NFLG (flgn != 0); | |
43814 | m68k_incpc(6); | |
43815 | fill_prefetch_0 (); | |
43816 | m68k_write_memory_32(dsta,newv); | |
43817 | }}}}}}}}endlabel2420: ; | |
43818 | return 28; | |
43819 | } | |
43820 | unsigned long CPUFUNC(op_50c0_5)(uint32_t opcode) /* Scc */ | |
43821 | { | |
43822 | uint32_t srcreg = (opcode & 7); | |
43823 | OpcodeFamily = 59; CurrentInstrCycles = 4; | |
43824 | {{{ int val = cctrue(0) ? 0xff : 0; | |
43825 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); | |
43826 | if (val) { m68k_incpc(2) ; return 4+2; } | |
43827 | }}}m68k_incpc(2); | |
43828 | fill_prefetch_2 (); | |
43829 | return 4; | |
43830 | } | |
43831 | unsigned long CPUFUNC(op_50c8_5)(uint32_t opcode) /* DBcc */ | |
43832 | { | |
43833 | uint32_t srcreg = (opcode & 7); | |
43834 | OpcodeFamily = 58; CurrentInstrCycles = 12; | |
43835 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
43836 | { int16_t offs = get_iword_prefetch(2); | |
43837 | if (!cctrue(0)) { | |
43838 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); | |
43839 | if (src) { | |
43840 | if (offs & 1) { | |
43841 | last_addr_for_exception_3 = m68k_getpc() + 2 + 2; | |
43842 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)offs + 2; | |
43843 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2422; | |
43844 | } | |
43845 | m68k_incpc((int32_t)offs + 2); | |
43846 | fill_prefetch_0 (); | |
43847 | return 10; | |
43848 | } else { | |
43849 | m68k_incpc(4); | |
43850 | fill_prefetch_0 (); | |
43851 | return 14; | |
43852 | } | |
43853 | } | |
43854 | }}}m68k_incpc(4); | |
43855 | fill_prefetch_0 (); | |
43856 | endlabel2422: ; | |
43857 | return 12; | |
43858 | } | |
43859 | unsigned long CPUFUNC(op_50d0_5)(uint32_t opcode) /* Scc */ | |
43860 | { | |
43861 | uint32_t srcreg = (opcode & 7); | |
43862 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
43863 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
43864 | { int val = cctrue(0) ? 0xff : 0; | |
43865 | m68k_incpc(2); | |
43866 | fill_prefetch_2 (); | |
43867 | m68k_write_memory_8(srca,val); | |
43868 | }}}return 12; | |
43869 | } | |
43870 | unsigned long CPUFUNC(op_50d8_5)(uint32_t opcode) /* Scc */ | |
43871 | { | |
43872 | uint32_t srcreg = (opcode & 7); | |
43873 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
43874 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
43875 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
43876 | { int val = cctrue(0) ? 0xff : 0; | |
43877 | m68k_incpc(2); | |
43878 | fill_prefetch_2 (); | |
43879 | m68k_write_memory_8(srca,val); | |
43880 | }}}return 12; | |
43881 | } | |
43882 | unsigned long CPUFUNC(op_50e0_5)(uint32_t opcode) /* Scc */ | |
43883 | { | |
43884 | uint32_t srcreg = (opcode & 7); | |
43885 | OpcodeFamily = 59; CurrentInstrCycles = 14; | |
43886 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
43887 | m68k_areg (regs, srcreg) = srca; | |
43888 | { int val = cctrue(0) ? 0xff : 0; | |
43889 | m68k_incpc(2); | |
43890 | fill_prefetch_2 (); | |
43891 | m68k_write_memory_8(srca,val); | |
43892 | }}}return 14; | |
43893 | } | |
43894 | unsigned long CPUFUNC(op_50e8_5)(uint32_t opcode) /* Scc */ | |
43895 | { | |
43896 | uint32_t srcreg = (opcode & 7); | |
43897 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
43898 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
43899 | { int val = cctrue(0) ? 0xff : 0; | |
43900 | m68k_incpc(4); | |
43901 | fill_prefetch_0 (); | |
43902 | m68k_write_memory_8(srca,val); | |
43903 | }}}return 16; | |
43904 | } | |
43905 | unsigned long CPUFUNC(op_50f0_5)(uint32_t opcode) /* Scc */ | |
43906 | { | |
43907 | uint32_t srcreg = (opcode & 7); | |
43908 | OpcodeFamily = 59; CurrentInstrCycles = 18; | |
43909 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
43910 | BusCyclePenalty += 2; | |
43911 | { int val = cctrue(0) ? 0xff : 0; | |
43912 | m68k_incpc(4); | |
43913 | fill_prefetch_0 (); | |
43914 | m68k_write_memory_8(srca,val); | |
43915 | }}}return 18; | |
43916 | } | |
43917 | unsigned long CPUFUNC(op_50f8_5)(uint32_t opcode) /* Scc */ | |
43918 | { | |
43919 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
43920 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
43921 | { int val = cctrue(0) ? 0xff : 0; | |
43922 | m68k_incpc(4); | |
43923 | fill_prefetch_0 (); | |
43924 | m68k_write_memory_8(srca,val); | |
43925 | }}}return 16; | |
43926 | } | |
43927 | unsigned long CPUFUNC(op_50f9_5)(uint32_t opcode) /* Scc */ | |
43928 | { | |
43929 | OpcodeFamily = 59; CurrentInstrCycles = 20; | |
43930 | {{ uint32_t srca = get_ilong_prefetch(2); | |
43931 | { int val = cctrue(0) ? 0xff : 0; | |
43932 | m68k_incpc(6); | |
43933 | fill_prefetch_0 (); | |
43934 | m68k_write_memory_8(srca,val); | |
43935 | }}}return 20; | |
43936 | } | |
43937 | unsigned long CPUFUNC(op_5100_5)(uint32_t opcode) /* SUB */ | |
43938 | { | |
43939 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
43940 | uint32_t dstreg = opcode & 7; | |
43941 | OpcodeFamily = 7; CurrentInstrCycles = 4; | |
43942 | {{ uint32_t src = srcreg; | |
43943 | { int8_t dst = m68k_dreg(regs, dstreg); | |
43944 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
43945 | { int flgs = ((int8_t)(src)) < 0; | |
43946 | int flgo = ((int8_t)(dst)) < 0; | |
43947 | int flgn = ((int8_t)(newv)) < 0; | |
43948 | SET_ZFLG (((int8_t)(newv)) == 0); | |
43949 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
43950 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
43951 | COPY_CARRY; | |
43952 | SET_NFLG (flgn != 0); | |
43953 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
43954 | }}}}}}m68k_incpc(2); | |
43955 | fill_prefetch_2 (); | |
43956 | return 4; | |
43957 | } | |
43958 | unsigned long CPUFUNC(op_5110_5)(uint32_t opcode) /* SUB */ | |
43959 | { | |
43960 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
43961 | uint32_t dstreg = opcode & 7; | |
43962 | OpcodeFamily = 7; CurrentInstrCycles = 12; | |
43963 | {{ uint32_t src = srcreg; | |
43964 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
43965 | { int8_t dst = m68k_read_memory_8(dsta); | |
43966 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
43967 | { int flgs = ((int8_t)(src)) < 0; | |
43968 | int flgo = ((int8_t)(dst)) < 0; | |
43969 | int flgn = ((int8_t)(newv)) < 0; | |
43970 | SET_ZFLG (((int8_t)(newv)) == 0); | |
43971 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
43972 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
43973 | COPY_CARRY; | |
43974 | SET_NFLG (flgn != 0); | |
43975 | m68k_incpc(2); | |
43976 | fill_prefetch_2 (); | |
43977 | m68k_write_memory_8(dsta,newv); | |
43978 | }}}}}}}return 12; | |
43979 | } | |
43980 | unsigned long CPUFUNC(op_5118_5)(uint32_t opcode) /* SUB */ | |
43981 | { | |
43982 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
43983 | uint32_t dstreg = opcode & 7; | |
43984 | OpcodeFamily = 7; CurrentInstrCycles = 12; | |
43985 | {{ uint32_t src = srcreg; | |
43986 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
43987 | { int8_t dst = m68k_read_memory_8(dsta); | |
43988 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
43989 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
43990 | { int flgs = ((int8_t)(src)) < 0; | |
43991 | int flgo = ((int8_t)(dst)) < 0; | |
43992 | int flgn = ((int8_t)(newv)) < 0; | |
43993 | SET_ZFLG (((int8_t)(newv)) == 0); | |
43994 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
43995 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
43996 | COPY_CARRY; | |
43997 | SET_NFLG (flgn != 0); | |
43998 | m68k_incpc(2); | |
43999 | fill_prefetch_2 (); | |
44000 | m68k_write_memory_8(dsta,newv); | |
44001 | }}}}}}}return 12; | |
44002 | } | |
44003 | unsigned long CPUFUNC(op_5120_5)(uint32_t opcode) /* SUB */ | |
44004 | { | |
44005 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
44006 | uint32_t dstreg = opcode & 7; | |
44007 | OpcodeFamily = 7; CurrentInstrCycles = 14; | |
44008 | {{ uint32_t src = srcreg; | |
44009 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
44010 | { int8_t dst = m68k_read_memory_8(dsta); | |
44011 | m68k_areg (regs, dstreg) = dsta; | |
44012 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
44013 | { int flgs = ((int8_t)(src)) < 0; | |
44014 | int flgo = ((int8_t)(dst)) < 0; | |
44015 | int flgn = ((int8_t)(newv)) < 0; | |
44016 | SET_ZFLG (((int8_t)(newv)) == 0); | |
44017 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
44018 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
44019 | COPY_CARRY; | |
44020 | SET_NFLG (flgn != 0); | |
44021 | m68k_incpc(2); | |
44022 | fill_prefetch_2 (); | |
44023 | m68k_write_memory_8(dsta,newv); | |
44024 | }}}}}}}return 14; | |
44025 | } | |
44026 | unsigned long CPUFUNC(op_5128_5)(uint32_t opcode) /* SUB */ | |
44027 | { | |
44028 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
44029 | uint32_t dstreg = opcode & 7; | |
44030 | OpcodeFamily = 7; CurrentInstrCycles = 16; | |
44031 | {{ uint32_t src = srcreg; | |
44032 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
44033 | { int8_t dst = m68k_read_memory_8(dsta); | |
44034 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
44035 | { int flgs = ((int8_t)(src)) < 0; | |
44036 | int flgo = ((int8_t)(dst)) < 0; | |
44037 | int flgn = ((int8_t)(newv)) < 0; | |
44038 | SET_ZFLG (((int8_t)(newv)) == 0); | |
44039 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
44040 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
44041 | COPY_CARRY; | |
44042 | SET_NFLG (flgn != 0); | |
44043 | m68k_incpc(4); | |
44044 | fill_prefetch_0 (); | |
44045 | m68k_write_memory_8(dsta,newv); | |
44046 | }}}}}}}return 16; | |
44047 | } | |
44048 | unsigned long CPUFUNC(op_5130_5)(uint32_t opcode) /* SUB */ | |
44049 | { | |
44050 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
44051 | uint32_t dstreg = opcode & 7; | |
44052 | OpcodeFamily = 7; CurrentInstrCycles = 18; | |
44053 | {{ uint32_t src = srcreg; | |
44054 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); | |
44055 | BusCyclePenalty += 2; | |
44056 | { int8_t dst = m68k_read_memory_8(dsta); | |
44057 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
44058 | { int flgs = ((int8_t)(src)) < 0; | |
44059 | int flgo = ((int8_t)(dst)) < 0; | |
44060 | int flgn = ((int8_t)(newv)) < 0; | |
44061 | SET_ZFLG (((int8_t)(newv)) == 0); | |
44062 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
44063 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
44064 | COPY_CARRY; | |
44065 | SET_NFLG (flgn != 0); | |
44066 | m68k_incpc(4); | |
44067 | fill_prefetch_0 (); | |
44068 | m68k_write_memory_8(dsta,newv); | |
44069 | }}}}}}}return 18; | |
44070 | } | |
44071 | unsigned long CPUFUNC(op_5138_5)(uint32_t opcode) /* SUB */ | |
44072 | { | |
44073 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
44074 | OpcodeFamily = 7; CurrentInstrCycles = 16; | |
44075 | {{ uint32_t src = srcreg; | |
44076 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); | |
44077 | { int8_t dst = m68k_read_memory_8(dsta); | |
44078 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
44079 | { int flgs = ((int8_t)(src)) < 0; | |
44080 | int flgo = ((int8_t)(dst)) < 0; | |
44081 | int flgn = ((int8_t)(newv)) < 0; | |
44082 | SET_ZFLG (((int8_t)(newv)) == 0); | |
44083 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
44084 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
44085 | COPY_CARRY; | |
44086 | SET_NFLG (flgn != 0); | |
44087 | m68k_incpc(4); | |
44088 | fill_prefetch_0 (); | |
44089 | m68k_write_memory_8(dsta,newv); | |
44090 | }}}}}}}return 16; | |
44091 | } | |
44092 | unsigned long CPUFUNC(op_5139_5)(uint32_t opcode) /* SUB */ | |
44093 | { | |
44094 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
44095 | OpcodeFamily = 7; CurrentInstrCycles = 20; | |
44096 | {{ uint32_t src = srcreg; | |
44097 | { uint32_t dsta = get_ilong_prefetch(2); | |
44098 | { int8_t dst = m68k_read_memory_8(dsta); | |
44099 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
44100 | { int flgs = ((int8_t)(src)) < 0; | |
44101 | int flgo = ((int8_t)(dst)) < 0; | |
44102 | int flgn = ((int8_t)(newv)) < 0; | |
44103 | SET_ZFLG (((int8_t)(newv)) == 0); | |
44104 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
44105 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
44106 | COPY_CARRY; | |
44107 | SET_NFLG (flgn != 0); | |
44108 | m68k_incpc(6); | |
44109 | fill_prefetch_0 (); | |
44110 | m68k_write_memory_8(dsta,newv); | |
44111 | }}}}}}}return 20; | |
44112 | } | |
44113 | unsigned long CPUFUNC(op_5140_5)(uint32_t opcode) /* SUB */ | |
44114 | { | |
44115 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
44116 | uint32_t dstreg = opcode & 7; | |
44117 | OpcodeFamily = 7; CurrentInstrCycles = 4; | |
44118 | {{ uint32_t src = srcreg; | |
44119 | { int16_t dst = m68k_dreg(regs, dstreg); | |
44120 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
44121 | { int flgs = ((int16_t)(src)) < 0; | |
44122 | int flgo = ((int16_t)(dst)) < 0; | |
44123 | int flgn = ((int16_t)(newv)) < 0; | |
44124 | SET_ZFLG (((int16_t)(newv)) == 0); | |
44125 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
44126 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
44127 | COPY_CARRY; | |
44128 | SET_NFLG (flgn != 0); | |
44129 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
44130 | }}}}}}m68k_incpc(2); | |
44131 | fill_prefetch_2 (); | |
44132 | return 4; | |
44133 | } | |
44134 | unsigned long CPUFUNC(op_5148_5)(uint32_t opcode) /* SUBA */ | |
44135 | { | |
44136 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
44137 | uint32_t dstreg = opcode & 7; | |
44138 | OpcodeFamily = 8; CurrentInstrCycles = 8; | |
44139 | {{ uint32_t src = srcreg; | |
44140 | { int32_t dst = m68k_areg(regs, dstreg); | |
44141 | { uint32_t newv = dst - src; | |
44142 | m68k_areg(regs, dstreg) = (newv); | |
44143 | }}}}m68k_incpc(2); | |
44144 | fill_prefetch_2 (); | |
44145 | return 8; | |
44146 | } | |
44147 | unsigned long CPUFUNC(op_5150_5)(uint32_t opcode) /* SUB */ | |
44148 | { | |
44149 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
44150 | uint32_t dstreg = opcode & 7; | |
44151 | OpcodeFamily = 7; CurrentInstrCycles = 12; | |
44152 | {{ uint32_t src = srcreg; | |
44153 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
44154 | if ((dsta & 1) != 0) { | |
44155 | last_fault_for_exception_3 = dsta; | |
44156 | last_op_for_exception_3 = opcode; | |
44157 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
44158 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
44159 | goto endlabel2440; | |
44160 | } | |
44161 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
44162 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
44163 | { int flgs = ((int16_t)(src)) < 0; | |
44164 | int flgo = ((int16_t)(dst)) < 0; | |
44165 | int flgn = ((int16_t)(newv)) < 0; | |
44166 | SET_ZFLG (((int16_t)(newv)) == 0); | |
44167 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
44168 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
44169 | COPY_CARRY; | |
44170 | SET_NFLG (flgn != 0); | |
44171 | m68k_incpc(2); | |
44172 | fill_prefetch_2 (); | |
44173 | m68k_write_memory_16(dsta,newv); | |
44174 | }}}}}}}}endlabel2440: ; | |
44175 | return 12; | |
44176 | } | |
44177 | unsigned long CPUFUNC(op_5158_5)(uint32_t opcode) /* SUB */ | |
44178 | { | |
44179 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
44180 | uint32_t dstreg = opcode & 7; | |
44181 | OpcodeFamily = 7; CurrentInstrCycles = 12; | |
44182 | {{ uint32_t src = srcreg; | |
44183 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
44184 | if ((dsta & 1) != 0) { | |
44185 | last_fault_for_exception_3 = dsta; | |
44186 | last_op_for_exception_3 = opcode; | |
44187 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
44188 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
44189 | goto endlabel2441; | |
44190 | } | |
44191 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
44192 | m68k_areg(regs, dstreg) += 2; | |
44193 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
44194 | { int flgs = ((int16_t)(src)) < 0; | |
44195 | int flgo = ((int16_t)(dst)) < 0; | |
44196 | int flgn = ((int16_t)(newv)) < 0; | |
44197 | SET_ZFLG (((int16_t)(newv)) == 0); | |
44198 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
44199 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
44200 | COPY_CARRY; | |
44201 | SET_NFLG (flgn != 0); | |
44202 | m68k_incpc(2); | |
44203 | fill_prefetch_2 (); | |
44204 | m68k_write_memory_16(dsta,newv); | |
44205 | }}}}}}}}endlabel2441: ; | |
44206 | return 12; | |
44207 | } | |
44208 | unsigned long CPUFUNC(op_5160_5)(uint32_t opcode) /* SUB */ | |
44209 | { | |
44210 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
44211 | uint32_t dstreg = opcode & 7; | |
44212 | OpcodeFamily = 7; CurrentInstrCycles = 14; | |
44213 | {{ uint32_t src = srcreg; | |
44214 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
44215 | if ((dsta & 1) != 0) { | |
44216 | last_fault_for_exception_3 = dsta; | |
44217 | last_op_for_exception_3 = opcode; | |
44218 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
44219 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
44220 | goto endlabel2442; | |
44221 | } | |
44222 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
44223 | m68k_areg (regs, dstreg) = dsta; | |
44224 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
44225 | { int flgs = ((int16_t)(src)) < 0; | |
44226 | int flgo = ((int16_t)(dst)) < 0; | |
44227 | int flgn = ((int16_t)(newv)) < 0; | |
44228 | SET_ZFLG (((int16_t)(newv)) == 0); | |
44229 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
44230 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
44231 | COPY_CARRY; | |
44232 | SET_NFLG (flgn != 0); | |
44233 | m68k_incpc(2); | |
44234 | fill_prefetch_2 (); | |
44235 | m68k_write_memory_16(dsta,newv); | |
44236 | }}}}}}}}endlabel2442: ; | |
44237 | return 14; | |
44238 | } | |
44239 | unsigned long CPUFUNC(op_5168_5)(uint32_t opcode) /* SUB */ | |
44240 | { | |
44241 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
44242 | uint32_t dstreg = opcode & 7; | |
44243 | OpcodeFamily = 7; CurrentInstrCycles = 16; | |
44244 | {{ uint32_t src = srcreg; | |
44245 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
44246 | if ((dsta & 1) != 0) { | |
44247 | last_fault_for_exception_3 = dsta; | |
44248 | last_op_for_exception_3 = opcode; | |
44249 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
44250 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
44251 | goto endlabel2443; | |
44252 | } | |
44253 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
44254 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
44255 | { int flgs = ((int16_t)(src)) < 0; | |
44256 | int flgo = ((int16_t)(dst)) < 0; | |
44257 | int flgn = ((int16_t)(newv)) < 0; | |
44258 | SET_ZFLG (((int16_t)(newv)) == 0); | |
44259 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
44260 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
44261 | COPY_CARRY; | |
44262 | SET_NFLG (flgn != 0); | |
44263 | m68k_incpc(4); | |
44264 | fill_prefetch_0 (); | |
44265 | m68k_write_memory_16(dsta,newv); | |
44266 | }}}}}}}}endlabel2443: ; | |
44267 | return 16; | |
44268 | } | |
44269 | unsigned long CPUFUNC(op_5170_5)(uint32_t opcode) /* SUB */ | |
44270 | { | |
44271 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
44272 | uint32_t dstreg = opcode & 7; | |
44273 | OpcodeFamily = 7; CurrentInstrCycles = 18; | |
44274 | {{ uint32_t src = srcreg; | |
44275 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); | |
44276 | BusCyclePenalty += 2; | |
44277 | if ((dsta & 1) != 0) { | |
44278 | last_fault_for_exception_3 = dsta; | |
44279 | last_op_for_exception_3 = opcode; | |
44280 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
44281 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
44282 | goto endlabel2444; | |
44283 | } | |
44284 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
44285 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
44286 | { int flgs = ((int16_t)(src)) < 0; | |
44287 | int flgo = ((int16_t)(dst)) < 0; | |
44288 | int flgn = ((int16_t)(newv)) < 0; | |
44289 | SET_ZFLG (((int16_t)(newv)) == 0); | |
44290 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
44291 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
44292 | COPY_CARRY; | |
44293 | SET_NFLG (flgn != 0); | |
44294 | m68k_incpc(4); | |
44295 | fill_prefetch_0 (); | |
44296 | m68k_write_memory_16(dsta,newv); | |
44297 | }}}}}}}}endlabel2444: ; | |
44298 | return 18; | |
44299 | } | |
44300 | unsigned long CPUFUNC(op_5178_5)(uint32_t opcode) /* SUB */ | |
44301 | { | |
44302 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
44303 | OpcodeFamily = 7; CurrentInstrCycles = 16; | |
44304 | {{ uint32_t src = srcreg; | |
44305 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); | |
44306 | if ((dsta & 1) != 0) { | |
44307 | last_fault_for_exception_3 = dsta; | |
44308 | last_op_for_exception_3 = opcode; | |
44309 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
44310 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
44311 | goto endlabel2445; | |
44312 | } | |
44313 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
44314 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
44315 | { int flgs = ((int16_t)(src)) < 0; | |
44316 | int flgo = ((int16_t)(dst)) < 0; | |
44317 | int flgn = ((int16_t)(newv)) < 0; | |
44318 | SET_ZFLG (((int16_t)(newv)) == 0); | |
44319 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
44320 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
44321 | COPY_CARRY; | |
44322 | SET_NFLG (flgn != 0); | |
44323 | m68k_incpc(4); | |
44324 | fill_prefetch_0 (); | |
44325 | m68k_write_memory_16(dsta,newv); | |
44326 | }}}}}}}}endlabel2445: ; | |
44327 | return 16; | |
44328 | } | |
44329 | unsigned long CPUFUNC(op_5179_5)(uint32_t opcode) /* SUB */ | |
44330 | { | |
44331 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
44332 | OpcodeFamily = 7; CurrentInstrCycles = 20; | |
44333 | {{ uint32_t src = srcreg; | |
44334 | { uint32_t dsta = get_ilong_prefetch(2); | |
44335 | if ((dsta & 1) != 0) { | |
44336 | last_fault_for_exception_3 = dsta; | |
44337 | last_op_for_exception_3 = opcode; | |
44338 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
44339 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
44340 | goto endlabel2446; | |
44341 | } | |
44342 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
44343 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
44344 | { int flgs = ((int16_t)(src)) < 0; | |
44345 | int flgo = ((int16_t)(dst)) < 0; | |
44346 | int flgn = ((int16_t)(newv)) < 0; | |
44347 | SET_ZFLG (((int16_t)(newv)) == 0); | |
44348 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
44349 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
44350 | COPY_CARRY; | |
44351 | SET_NFLG (flgn != 0); | |
44352 | m68k_incpc(6); | |
44353 | fill_prefetch_0 (); | |
44354 | m68k_write_memory_16(dsta,newv); | |
44355 | }}}}}}}}endlabel2446: ; | |
44356 | return 20; | |
44357 | } | |
44358 | unsigned long CPUFUNC(op_5180_5)(uint32_t opcode) /* SUB */ | |
44359 | { | |
44360 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
44361 | uint32_t dstreg = opcode & 7; | |
44362 | OpcodeFamily = 7; CurrentInstrCycles = 8; | |
44363 | {{ uint32_t src = srcreg; | |
44364 | { int32_t dst = m68k_dreg(regs, dstreg); | |
44365 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
44366 | { int flgs = ((int32_t)(src)) < 0; | |
44367 | int flgo = ((int32_t)(dst)) < 0; | |
44368 | int flgn = ((int32_t)(newv)) < 0; | |
44369 | SET_ZFLG (((int32_t)(newv)) == 0); | |
44370 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
44371 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
44372 | COPY_CARRY; | |
44373 | SET_NFLG (flgn != 0); | |
44374 | m68k_dreg(regs, dstreg) = (newv); | |
44375 | }}}}}}m68k_incpc(2); | |
44376 | fill_prefetch_2 (); | |
44377 | return 8; | |
44378 | } | |
44379 | unsigned long CPUFUNC(op_5188_5)(uint32_t opcode) /* SUBA */ | |
44380 | { | |
44381 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
44382 | uint32_t dstreg = opcode & 7; | |
44383 | OpcodeFamily = 8; CurrentInstrCycles = 8; | |
44384 | {{ uint32_t src = srcreg; | |
44385 | { int32_t dst = m68k_areg(regs, dstreg); | |
44386 | { uint32_t newv = dst - src; | |
44387 | m68k_areg(regs, dstreg) = (newv); | |
44388 | }}}}m68k_incpc(2); | |
44389 | fill_prefetch_2 (); | |
44390 | return 8; | |
44391 | } | |
44392 | unsigned long CPUFUNC(op_5190_5)(uint32_t opcode) /* SUB */ | |
44393 | { | |
44394 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
44395 | uint32_t dstreg = opcode & 7; | |
44396 | OpcodeFamily = 7; CurrentInstrCycles = 20; | |
44397 | {{ uint32_t src = srcreg; | |
44398 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
44399 | if ((dsta & 1) != 0) { | |
44400 | last_fault_for_exception_3 = dsta; | |
44401 | last_op_for_exception_3 = opcode; | |
44402 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
44403 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
44404 | goto endlabel2449; | |
44405 | } | |
44406 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
44407 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
44408 | { int flgs = ((int32_t)(src)) < 0; | |
44409 | int flgo = ((int32_t)(dst)) < 0; | |
44410 | int flgn = ((int32_t)(newv)) < 0; | |
44411 | SET_ZFLG (((int32_t)(newv)) == 0); | |
44412 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
44413 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
44414 | COPY_CARRY; | |
44415 | SET_NFLG (flgn != 0); | |
44416 | m68k_incpc(2); | |
44417 | fill_prefetch_2 (); | |
44418 | m68k_write_memory_32(dsta,newv); | |
44419 | }}}}}}}}endlabel2449: ; | |
44420 | return 20; | |
44421 | } | |
44422 | unsigned long CPUFUNC(op_5198_5)(uint32_t opcode) /* SUB */ | |
44423 | { | |
44424 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
44425 | uint32_t dstreg = opcode & 7; | |
44426 | OpcodeFamily = 7; CurrentInstrCycles = 20; | |
44427 | {{ uint32_t src = srcreg; | |
44428 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
44429 | if ((dsta & 1) != 0) { | |
44430 | last_fault_for_exception_3 = dsta; | |
44431 | last_op_for_exception_3 = opcode; | |
44432 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
44433 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
44434 | goto endlabel2450; | |
44435 | } | |
44436 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
44437 | m68k_areg(regs, dstreg) += 4; | |
44438 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
44439 | { int flgs = ((int32_t)(src)) < 0; | |
44440 | int flgo = ((int32_t)(dst)) < 0; | |
44441 | int flgn = ((int32_t)(newv)) < 0; | |
44442 | SET_ZFLG (((int32_t)(newv)) == 0); | |
44443 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
44444 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
44445 | COPY_CARRY; | |
44446 | SET_NFLG (flgn != 0); | |
44447 | m68k_incpc(2); | |
44448 | fill_prefetch_2 (); | |
44449 | m68k_write_memory_32(dsta,newv); | |
44450 | }}}}}}}}endlabel2450: ; | |
44451 | return 20; | |
44452 | } | |
44453 | unsigned long CPUFUNC(op_51a0_5)(uint32_t opcode) /* SUB */ | |
44454 | { | |
44455 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
44456 | uint32_t dstreg = opcode & 7; | |
44457 | OpcodeFamily = 7; CurrentInstrCycles = 22; | |
44458 | {{ uint32_t src = srcreg; | |
44459 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
44460 | if ((dsta & 1) != 0) { | |
44461 | last_fault_for_exception_3 = dsta; | |
44462 | last_op_for_exception_3 = opcode; | |
44463 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
44464 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
44465 | goto endlabel2451; | |
44466 | } | |
44467 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
44468 | m68k_areg (regs, dstreg) = dsta; | |
44469 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
44470 | { int flgs = ((int32_t)(src)) < 0; | |
44471 | int flgo = ((int32_t)(dst)) < 0; | |
44472 | int flgn = ((int32_t)(newv)) < 0; | |
44473 | SET_ZFLG (((int32_t)(newv)) == 0); | |
44474 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
44475 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
44476 | COPY_CARRY; | |
44477 | SET_NFLG (flgn != 0); | |
44478 | m68k_incpc(2); | |
44479 | fill_prefetch_2 (); | |
44480 | m68k_write_memory_32(dsta,newv); | |
44481 | }}}}}}}}endlabel2451: ; | |
44482 | return 22; | |
44483 | } | |
44484 | unsigned long CPUFUNC(op_51a8_5)(uint32_t opcode) /* SUB */ | |
44485 | { | |
44486 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
44487 | uint32_t dstreg = opcode & 7; | |
44488 | OpcodeFamily = 7; CurrentInstrCycles = 24; | |
44489 | {{ uint32_t src = srcreg; | |
44490 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
44491 | if ((dsta & 1) != 0) { | |
44492 | last_fault_for_exception_3 = dsta; | |
44493 | last_op_for_exception_3 = opcode; | |
44494 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
44495 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
44496 | goto endlabel2452; | |
44497 | } | |
44498 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
44499 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
44500 | { int flgs = ((int32_t)(src)) < 0; | |
44501 | int flgo = ((int32_t)(dst)) < 0; | |
44502 | int flgn = ((int32_t)(newv)) < 0; | |
44503 | SET_ZFLG (((int32_t)(newv)) == 0); | |
44504 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
44505 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
44506 | COPY_CARRY; | |
44507 | SET_NFLG (flgn != 0); | |
44508 | m68k_incpc(4); | |
44509 | fill_prefetch_0 (); | |
44510 | m68k_write_memory_32(dsta,newv); | |
44511 | }}}}}}}}endlabel2452: ; | |
44512 | return 24; | |
44513 | } | |
44514 | unsigned long CPUFUNC(op_51b0_5)(uint32_t opcode) /* SUB */ | |
44515 | { | |
44516 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
44517 | uint32_t dstreg = opcode & 7; | |
44518 | OpcodeFamily = 7; CurrentInstrCycles = 26; | |
44519 | {{ uint32_t src = srcreg; | |
44520 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); | |
44521 | BusCyclePenalty += 2; | |
44522 | if ((dsta & 1) != 0) { | |
44523 | last_fault_for_exception_3 = dsta; | |
44524 | last_op_for_exception_3 = opcode; | |
44525 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
44526 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
44527 | goto endlabel2453; | |
44528 | } | |
44529 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
44530 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
44531 | { int flgs = ((int32_t)(src)) < 0; | |
44532 | int flgo = ((int32_t)(dst)) < 0; | |
44533 | int flgn = ((int32_t)(newv)) < 0; | |
44534 | SET_ZFLG (((int32_t)(newv)) == 0); | |
44535 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
44536 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
44537 | COPY_CARRY; | |
44538 | SET_NFLG (flgn != 0); | |
44539 | m68k_incpc(4); | |
44540 | fill_prefetch_0 (); | |
44541 | m68k_write_memory_32(dsta,newv); | |
44542 | }}}}}}}}endlabel2453: ; | |
44543 | return 26; | |
44544 | } | |
44545 | unsigned long CPUFUNC(op_51b8_5)(uint32_t opcode) /* SUB */ | |
44546 | { | |
44547 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
44548 | OpcodeFamily = 7; CurrentInstrCycles = 24; | |
44549 | {{ uint32_t src = srcreg; | |
44550 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); | |
44551 | if ((dsta & 1) != 0) { | |
44552 | last_fault_for_exception_3 = dsta; | |
44553 | last_op_for_exception_3 = opcode; | |
44554 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
44555 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
44556 | goto endlabel2454; | |
44557 | } | |
44558 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
44559 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
44560 | { int flgs = ((int32_t)(src)) < 0; | |
44561 | int flgo = ((int32_t)(dst)) < 0; | |
44562 | int flgn = ((int32_t)(newv)) < 0; | |
44563 | SET_ZFLG (((int32_t)(newv)) == 0); | |
44564 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
44565 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
44566 | COPY_CARRY; | |
44567 | SET_NFLG (flgn != 0); | |
44568 | m68k_incpc(4); | |
44569 | fill_prefetch_0 (); | |
44570 | m68k_write_memory_32(dsta,newv); | |
44571 | }}}}}}}}endlabel2454: ; | |
44572 | return 24; | |
44573 | } | |
44574 | unsigned long CPUFUNC(op_51b9_5)(uint32_t opcode) /* SUB */ | |
44575 | { | |
44576 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
44577 | OpcodeFamily = 7; CurrentInstrCycles = 28; | |
44578 | {{ uint32_t src = srcreg; | |
44579 | { uint32_t dsta = get_ilong_prefetch(2); | |
44580 | if ((dsta & 1) != 0) { | |
44581 | last_fault_for_exception_3 = dsta; | |
44582 | last_op_for_exception_3 = opcode; | |
44583 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
44584 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
44585 | goto endlabel2455; | |
44586 | } | |
44587 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
44588 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
44589 | { int flgs = ((int32_t)(src)) < 0; | |
44590 | int flgo = ((int32_t)(dst)) < 0; | |
44591 | int flgn = ((int32_t)(newv)) < 0; | |
44592 | SET_ZFLG (((int32_t)(newv)) == 0); | |
44593 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
44594 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
44595 | COPY_CARRY; | |
44596 | SET_NFLG (flgn != 0); | |
44597 | m68k_incpc(6); | |
44598 | fill_prefetch_0 (); | |
44599 | m68k_write_memory_32(dsta,newv); | |
44600 | }}}}}}}}endlabel2455: ; | |
44601 | return 28; | |
44602 | } | |
44603 | unsigned long CPUFUNC(op_51c0_5)(uint32_t opcode) /* Scc */ | |
44604 | { | |
44605 | uint32_t srcreg = (opcode & 7); | |
44606 | OpcodeFamily = 59; CurrentInstrCycles = 4; | |
44607 | {{{ int val = cctrue(1) ? 0xff : 0; | |
44608 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); | |
44609 | if (val) { m68k_incpc(2) ; return 4+2; } | |
44610 | }}}m68k_incpc(2); | |
44611 | fill_prefetch_2 (); | |
44612 | return 4; | |
44613 | } | |
44614 | unsigned long CPUFUNC(op_51c8_5)(uint32_t opcode) /* DBcc */ | |
44615 | { | |
44616 | uint32_t srcreg = (opcode & 7); | |
44617 | OpcodeFamily = 58; CurrentInstrCycles = 12; | |
44618 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
44619 | { int16_t offs = get_iword_prefetch(2); | |
44620 | if (!cctrue(1)) { | |
44621 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); | |
44622 | if (src) { | |
44623 | if (offs & 1) { | |
44624 | last_addr_for_exception_3 = m68k_getpc() + 2 + 2; | |
44625 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)offs + 2; | |
44626 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2457; | |
44627 | } | |
44628 | m68k_incpc((int32_t)offs + 2); | |
44629 | fill_prefetch_0 (); | |
44630 | return 10; | |
44631 | } else { | |
44632 | m68k_incpc(4); | |
44633 | fill_prefetch_0 (); | |
44634 | return 14; | |
44635 | } | |
44636 | } | |
44637 | }}}m68k_incpc(4); | |
44638 | fill_prefetch_0 (); | |
44639 | endlabel2457: ; | |
44640 | return 12; | |
44641 | } | |
44642 | unsigned long CPUFUNC(op_51d0_5)(uint32_t opcode) /* Scc */ | |
44643 | { | |
44644 | uint32_t srcreg = (opcode & 7); | |
44645 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
44646 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
44647 | { int val = cctrue(1) ? 0xff : 0; | |
44648 | m68k_incpc(2); | |
44649 | fill_prefetch_2 (); | |
44650 | m68k_write_memory_8(srca,val); | |
44651 | }}}return 12; | |
44652 | } | |
44653 | unsigned long CPUFUNC(op_51d8_5)(uint32_t opcode) /* Scc */ | |
44654 | { | |
44655 | uint32_t srcreg = (opcode & 7); | |
44656 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
44657 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
44658 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
44659 | { int val = cctrue(1) ? 0xff : 0; | |
44660 | m68k_incpc(2); | |
44661 | fill_prefetch_2 (); | |
44662 | m68k_write_memory_8(srca,val); | |
44663 | }}}return 12; | |
44664 | } | |
44665 | unsigned long CPUFUNC(op_51e0_5)(uint32_t opcode) /* Scc */ | |
44666 | { | |
44667 | uint32_t srcreg = (opcode & 7); | |
44668 | OpcodeFamily = 59; CurrentInstrCycles = 14; | |
44669 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
44670 | m68k_areg (regs, srcreg) = srca; | |
44671 | { int val = cctrue(1) ? 0xff : 0; | |
44672 | m68k_incpc(2); | |
44673 | fill_prefetch_2 (); | |
44674 | m68k_write_memory_8(srca,val); | |
44675 | }}}return 14; | |
44676 | } | |
44677 | unsigned long CPUFUNC(op_51e8_5)(uint32_t opcode) /* Scc */ | |
44678 | { | |
44679 | uint32_t srcreg = (opcode & 7); | |
44680 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
44681 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
44682 | { int val = cctrue(1) ? 0xff : 0; | |
44683 | m68k_incpc(4); | |
44684 | fill_prefetch_0 (); | |
44685 | m68k_write_memory_8(srca,val); | |
44686 | }}}return 16; | |
44687 | } | |
44688 | unsigned long CPUFUNC(op_51f0_5)(uint32_t opcode) /* Scc */ | |
44689 | { | |
44690 | uint32_t srcreg = (opcode & 7); | |
44691 | OpcodeFamily = 59; CurrentInstrCycles = 18; | |
44692 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
44693 | BusCyclePenalty += 2; | |
44694 | { int val = cctrue(1) ? 0xff : 0; | |
44695 | m68k_incpc(4); | |
44696 | fill_prefetch_0 (); | |
44697 | m68k_write_memory_8(srca,val); | |
44698 | }}}return 18; | |
44699 | } | |
44700 | unsigned long CPUFUNC(op_51f8_5)(uint32_t opcode) /* Scc */ | |
44701 | { | |
44702 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
44703 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
44704 | { int val = cctrue(1) ? 0xff : 0; | |
44705 | m68k_incpc(4); | |
44706 | fill_prefetch_0 (); | |
44707 | m68k_write_memory_8(srca,val); | |
44708 | }}}return 16; | |
44709 | } | |
44710 | unsigned long CPUFUNC(op_51f9_5)(uint32_t opcode) /* Scc */ | |
44711 | { | |
44712 | OpcodeFamily = 59; CurrentInstrCycles = 20; | |
44713 | {{ uint32_t srca = get_ilong_prefetch(2); | |
44714 | { int val = cctrue(1) ? 0xff : 0; | |
44715 | m68k_incpc(6); | |
44716 | fill_prefetch_0 (); | |
44717 | m68k_write_memory_8(srca,val); | |
44718 | }}}return 20; | |
44719 | } | |
44720 | unsigned long CPUFUNC(op_52c0_5)(uint32_t opcode) /* Scc */ | |
44721 | { | |
44722 | uint32_t srcreg = (opcode & 7); | |
44723 | OpcodeFamily = 59; CurrentInstrCycles = 4; | |
44724 | {{{ int val = cctrue(2) ? 0xff : 0; | |
44725 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); | |
44726 | if (val) { m68k_incpc(2) ; return 4+2; } | |
44727 | }}}m68k_incpc(2); | |
44728 | fill_prefetch_2 (); | |
44729 | return 4; | |
44730 | } | |
44731 | unsigned long CPUFUNC(op_52c8_5)(uint32_t opcode) /* DBcc */ | |
44732 | { | |
44733 | uint32_t srcreg = (opcode & 7); | |
44734 | OpcodeFamily = 58; CurrentInstrCycles = 12; | |
44735 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
44736 | { int16_t offs = get_iword_prefetch(2); | |
44737 | if (!cctrue(2)) { | |
44738 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); | |
44739 | if (src) { | |
44740 | if (offs & 1) { | |
44741 | last_addr_for_exception_3 = m68k_getpc() + 2 + 2; | |
44742 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)offs + 2; | |
44743 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2466; | |
44744 | } | |
44745 | m68k_incpc((int32_t)offs + 2); | |
44746 | fill_prefetch_0 (); | |
44747 | return 10; | |
44748 | } else { | |
44749 | m68k_incpc(4); | |
44750 | fill_prefetch_0 (); | |
44751 | return 14; | |
44752 | } | |
44753 | } | |
44754 | }}}m68k_incpc(4); | |
44755 | fill_prefetch_0 (); | |
44756 | endlabel2466: ; | |
44757 | return 12; | |
44758 | } | |
44759 | unsigned long CPUFUNC(op_52d0_5)(uint32_t opcode) /* Scc */ | |
44760 | { | |
44761 | uint32_t srcreg = (opcode & 7); | |
44762 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
44763 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
44764 | { int val = cctrue(2) ? 0xff : 0; | |
44765 | m68k_incpc(2); | |
44766 | fill_prefetch_2 (); | |
44767 | m68k_write_memory_8(srca,val); | |
44768 | }}}return 12; | |
44769 | } | |
44770 | unsigned long CPUFUNC(op_52d8_5)(uint32_t opcode) /* Scc */ | |
44771 | { | |
44772 | uint32_t srcreg = (opcode & 7); | |
44773 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
44774 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
44775 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
44776 | { int val = cctrue(2) ? 0xff : 0; | |
44777 | m68k_incpc(2); | |
44778 | fill_prefetch_2 (); | |
44779 | m68k_write_memory_8(srca,val); | |
44780 | }}}return 12; | |
44781 | } | |
44782 | unsigned long CPUFUNC(op_52e0_5)(uint32_t opcode) /* Scc */ | |
44783 | { | |
44784 | uint32_t srcreg = (opcode & 7); | |
44785 | OpcodeFamily = 59; CurrentInstrCycles = 14; | |
44786 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
44787 | m68k_areg (regs, srcreg) = srca; | |
44788 | { int val = cctrue(2) ? 0xff : 0; | |
44789 | m68k_incpc(2); | |
44790 | fill_prefetch_2 (); | |
44791 | m68k_write_memory_8(srca,val); | |
44792 | }}}return 14; | |
44793 | } | |
44794 | unsigned long CPUFUNC(op_52e8_5)(uint32_t opcode) /* Scc */ | |
44795 | { | |
44796 | uint32_t srcreg = (opcode & 7); | |
44797 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
44798 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
44799 | { int val = cctrue(2) ? 0xff : 0; | |
44800 | m68k_incpc(4); | |
44801 | fill_prefetch_0 (); | |
44802 | m68k_write_memory_8(srca,val); | |
44803 | }}}return 16; | |
44804 | } | |
44805 | unsigned long CPUFUNC(op_52f0_5)(uint32_t opcode) /* Scc */ | |
44806 | { | |
44807 | uint32_t srcreg = (opcode & 7); | |
44808 | OpcodeFamily = 59; CurrentInstrCycles = 18; | |
44809 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
44810 | BusCyclePenalty += 2; | |
44811 | { int val = cctrue(2) ? 0xff : 0; | |
44812 | m68k_incpc(4); | |
44813 | fill_prefetch_0 (); | |
44814 | m68k_write_memory_8(srca,val); | |
44815 | }}}return 18; | |
44816 | } | |
44817 | unsigned long CPUFUNC(op_52f8_5)(uint32_t opcode) /* Scc */ | |
44818 | { | |
44819 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
44820 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
44821 | { int val = cctrue(2) ? 0xff : 0; | |
44822 | m68k_incpc(4); | |
44823 | fill_prefetch_0 (); | |
44824 | m68k_write_memory_8(srca,val); | |
44825 | }}}return 16; | |
44826 | } | |
44827 | unsigned long CPUFUNC(op_52f9_5)(uint32_t opcode) /* Scc */ | |
44828 | { | |
44829 | OpcodeFamily = 59; CurrentInstrCycles = 20; | |
44830 | {{ uint32_t srca = get_ilong_prefetch(2); | |
44831 | { int val = cctrue(2) ? 0xff : 0; | |
44832 | m68k_incpc(6); | |
44833 | fill_prefetch_0 (); | |
44834 | m68k_write_memory_8(srca,val); | |
44835 | }}}return 20; | |
44836 | } | |
44837 | unsigned long CPUFUNC(op_53c0_5)(uint32_t opcode) /* Scc */ | |
44838 | { | |
44839 | uint32_t srcreg = (opcode & 7); | |
44840 | OpcodeFamily = 59; CurrentInstrCycles = 4; | |
44841 | {{{ int val = cctrue(3) ? 0xff : 0; | |
44842 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); | |
44843 | if (val) { m68k_incpc(2) ; return 4+2; } | |
44844 | }}}m68k_incpc(2); | |
44845 | fill_prefetch_2 (); | |
44846 | return 4; | |
44847 | } | |
44848 | unsigned long CPUFUNC(op_53c8_5)(uint32_t opcode) /* DBcc */ | |
44849 | { | |
44850 | uint32_t srcreg = (opcode & 7); | |
44851 | OpcodeFamily = 58; CurrentInstrCycles = 12; | |
44852 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
44853 | { int16_t offs = get_iword_prefetch(2); | |
44854 | if (!cctrue(3)) { | |
44855 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); | |
44856 | if (src) { | |
44857 | if (offs & 1) { | |
44858 | last_addr_for_exception_3 = m68k_getpc() + 2 + 2; | |
44859 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)offs + 2; | |
44860 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2475; | |
44861 | } | |
44862 | m68k_incpc((int32_t)offs + 2); | |
44863 | fill_prefetch_0 (); | |
44864 | return 10; | |
44865 | } else { | |
44866 | m68k_incpc(4); | |
44867 | fill_prefetch_0 (); | |
44868 | return 14; | |
44869 | } | |
44870 | } | |
44871 | }}}m68k_incpc(4); | |
44872 | fill_prefetch_0 (); | |
44873 | endlabel2475: ; | |
44874 | return 12; | |
44875 | } | |
44876 | unsigned long CPUFUNC(op_53d0_5)(uint32_t opcode) /* Scc */ | |
44877 | { | |
44878 | uint32_t srcreg = (opcode & 7); | |
44879 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
44880 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
44881 | { int val = cctrue(3) ? 0xff : 0; | |
44882 | m68k_incpc(2); | |
44883 | fill_prefetch_2 (); | |
44884 | m68k_write_memory_8(srca,val); | |
44885 | }}}return 12; | |
44886 | } | |
44887 | unsigned long CPUFUNC(op_53d8_5)(uint32_t opcode) /* Scc */ | |
44888 | { | |
44889 | uint32_t srcreg = (opcode & 7); | |
44890 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
44891 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
44892 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
44893 | { int val = cctrue(3) ? 0xff : 0; | |
44894 | m68k_incpc(2); | |
44895 | fill_prefetch_2 (); | |
44896 | m68k_write_memory_8(srca,val); | |
44897 | }}}return 12; | |
44898 | } | |
44899 | unsigned long CPUFUNC(op_53e0_5)(uint32_t opcode) /* Scc */ | |
44900 | { | |
44901 | uint32_t srcreg = (opcode & 7); | |
44902 | OpcodeFamily = 59; CurrentInstrCycles = 14; | |
44903 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
44904 | m68k_areg (regs, srcreg) = srca; | |
44905 | { int val = cctrue(3) ? 0xff : 0; | |
44906 | m68k_incpc(2); | |
44907 | fill_prefetch_2 (); | |
44908 | m68k_write_memory_8(srca,val); | |
44909 | }}}return 14; | |
44910 | } | |
44911 | unsigned long CPUFUNC(op_53e8_5)(uint32_t opcode) /* Scc */ | |
44912 | { | |
44913 | uint32_t srcreg = (opcode & 7); | |
44914 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
44915 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
44916 | { int val = cctrue(3) ? 0xff : 0; | |
44917 | m68k_incpc(4); | |
44918 | fill_prefetch_0 (); | |
44919 | m68k_write_memory_8(srca,val); | |
44920 | }}}return 16; | |
44921 | } | |
44922 | unsigned long CPUFUNC(op_53f0_5)(uint32_t opcode) /* Scc */ | |
44923 | { | |
44924 | uint32_t srcreg = (opcode & 7); | |
44925 | OpcodeFamily = 59; CurrentInstrCycles = 18; | |
44926 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
44927 | BusCyclePenalty += 2; | |
44928 | { int val = cctrue(3) ? 0xff : 0; | |
44929 | m68k_incpc(4); | |
44930 | fill_prefetch_0 (); | |
44931 | m68k_write_memory_8(srca,val); | |
44932 | }}}return 18; | |
44933 | } | |
44934 | unsigned long CPUFUNC(op_53f8_5)(uint32_t opcode) /* Scc */ | |
44935 | { | |
44936 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
44937 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
44938 | { int val = cctrue(3) ? 0xff : 0; | |
44939 | m68k_incpc(4); | |
44940 | fill_prefetch_0 (); | |
44941 | m68k_write_memory_8(srca,val); | |
44942 | }}}return 16; | |
44943 | } | |
44944 | unsigned long CPUFUNC(op_53f9_5)(uint32_t opcode) /* Scc */ | |
44945 | { | |
44946 | OpcodeFamily = 59; CurrentInstrCycles = 20; | |
44947 | {{ uint32_t srca = get_ilong_prefetch(2); | |
44948 | { int val = cctrue(3) ? 0xff : 0; | |
44949 | m68k_incpc(6); | |
44950 | fill_prefetch_0 (); | |
44951 | m68k_write_memory_8(srca,val); | |
44952 | }}}return 20; | |
44953 | } | |
44954 | unsigned long CPUFUNC(op_54c0_5)(uint32_t opcode) /* Scc */ | |
44955 | { | |
44956 | uint32_t srcreg = (opcode & 7); | |
44957 | OpcodeFamily = 59; CurrentInstrCycles = 4; | |
44958 | {{{ int val = cctrue(4) ? 0xff : 0; | |
44959 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); | |
44960 | if (val) { m68k_incpc(2) ; return 4+2; } | |
44961 | }}}m68k_incpc(2); | |
44962 | fill_prefetch_2 (); | |
44963 | return 4; | |
44964 | } | |
44965 | unsigned long CPUFUNC(op_54c8_5)(uint32_t opcode) /* DBcc */ | |
44966 | { | |
44967 | uint32_t srcreg = (opcode & 7); | |
44968 | OpcodeFamily = 58; CurrentInstrCycles = 12; | |
44969 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
44970 | { int16_t offs = get_iword_prefetch(2); | |
44971 | if (!cctrue(4)) { | |
44972 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); | |
44973 | if (src) { | |
44974 | if (offs & 1) { | |
44975 | last_addr_for_exception_3 = m68k_getpc() + 2 + 2; | |
44976 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)offs + 2; | |
44977 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2484; | |
44978 | } | |
44979 | m68k_incpc((int32_t)offs + 2); | |
44980 | fill_prefetch_0 (); | |
44981 | return 10; | |
44982 | } else { | |
44983 | m68k_incpc(4); | |
44984 | fill_prefetch_0 (); | |
44985 | return 14; | |
44986 | } | |
44987 | } | |
44988 | }}}m68k_incpc(4); | |
44989 | fill_prefetch_0 (); | |
44990 | endlabel2484: ; | |
44991 | return 12; | |
44992 | } | |
44993 | unsigned long CPUFUNC(op_54d0_5)(uint32_t opcode) /* Scc */ | |
44994 | { | |
44995 | uint32_t srcreg = (opcode & 7); | |
44996 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
44997 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
44998 | { int val = cctrue(4) ? 0xff : 0; | |
44999 | m68k_incpc(2); | |
45000 | fill_prefetch_2 (); | |
45001 | m68k_write_memory_8(srca,val); | |
45002 | }}}return 12; | |
45003 | } | |
45004 | unsigned long CPUFUNC(op_54d8_5)(uint32_t opcode) /* Scc */ | |
45005 | { | |
45006 | uint32_t srcreg = (opcode & 7); | |
45007 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
45008 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
45009 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
45010 | { int val = cctrue(4) ? 0xff : 0; | |
45011 | m68k_incpc(2); | |
45012 | fill_prefetch_2 (); | |
45013 | m68k_write_memory_8(srca,val); | |
45014 | }}}return 12; | |
45015 | } | |
45016 | unsigned long CPUFUNC(op_54e0_5)(uint32_t opcode) /* Scc */ | |
45017 | { | |
45018 | uint32_t srcreg = (opcode & 7); | |
45019 | OpcodeFamily = 59; CurrentInstrCycles = 14; | |
45020 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
45021 | m68k_areg (regs, srcreg) = srca; | |
45022 | { int val = cctrue(4) ? 0xff : 0; | |
45023 | m68k_incpc(2); | |
45024 | fill_prefetch_2 (); | |
45025 | m68k_write_memory_8(srca,val); | |
45026 | }}}return 14; | |
45027 | } | |
45028 | unsigned long CPUFUNC(op_54e8_5)(uint32_t opcode) /* Scc */ | |
45029 | { | |
45030 | uint32_t srcreg = (opcode & 7); | |
45031 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
45032 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
45033 | { int val = cctrue(4) ? 0xff : 0; | |
45034 | m68k_incpc(4); | |
45035 | fill_prefetch_0 (); | |
45036 | m68k_write_memory_8(srca,val); | |
45037 | }}}return 16; | |
45038 | } | |
45039 | unsigned long CPUFUNC(op_54f0_5)(uint32_t opcode) /* Scc */ | |
45040 | { | |
45041 | uint32_t srcreg = (opcode & 7); | |
45042 | OpcodeFamily = 59; CurrentInstrCycles = 18; | |
45043 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
45044 | BusCyclePenalty += 2; | |
45045 | { int val = cctrue(4) ? 0xff : 0; | |
45046 | m68k_incpc(4); | |
45047 | fill_prefetch_0 (); | |
45048 | m68k_write_memory_8(srca,val); | |
45049 | }}}return 18; | |
45050 | } | |
45051 | unsigned long CPUFUNC(op_54f8_5)(uint32_t opcode) /* Scc */ | |
45052 | { | |
45053 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
45054 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
45055 | { int val = cctrue(4) ? 0xff : 0; | |
45056 | m68k_incpc(4); | |
45057 | fill_prefetch_0 (); | |
45058 | m68k_write_memory_8(srca,val); | |
45059 | }}}return 16; | |
45060 | } | |
45061 | unsigned long CPUFUNC(op_54f9_5)(uint32_t opcode) /* Scc */ | |
45062 | { | |
45063 | OpcodeFamily = 59; CurrentInstrCycles = 20; | |
45064 | {{ uint32_t srca = get_ilong_prefetch(2); | |
45065 | { int val = cctrue(4) ? 0xff : 0; | |
45066 | m68k_incpc(6); | |
45067 | fill_prefetch_0 (); | |
45068 | m68k_write_memory_8(srca,val); | |
45069 | }}}return 20; | |
45070 | } | |
45071 | unsigned long CPUFUNC(op_55c0_5)(uint32_t opcode) /* Scc */ | |
45072 | { | |
45073 | uint32_t srcreg = (opcode & 7); | |
45074 | OpcodeFamily = 59; CurrentInstrCycles = 4; | |
45075 | {{{ int val = cctrue(5) ? 0xff : 0; | |
45076 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); | |
45077 | if (val) { m68k_incpc(2) ; return 4+2; } | |
45078 | }}}m68k_incpc(2); | |
45079 | fill_prefetch_2 (); | |
45080 | return 4; | |
45081 | } | |
45082 | unsigned long CPUFUNC(op_55c8_5)(uint32_t opcode) /* DBcc */ | |
45083 | { | |
45084 | uint32_t srcreg = (opcode & 7); | |
45085 | OpcodeFamily = 58; CurrentInstrCycles = 12; | |
45086 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
45087 | { int16_t offs = get_iword_prefetch(2); | |
45088 | if (!cctrue(5)) { | |
45089 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); | |
45090 | if (src) { | |
45091 | if (offs & 1) { | |
45092 | last_addr_for_exception_3 = m68k_getpc() + 2 + 2; | |
45093 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)offs + 2; | |
45094 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2493; | |
45095 | } | |
45096 | m68k_incpc((int32_t)offs + 2); | |
45097 | fill_prefetch_0 (); | |
45098 | return 10; | |
45099 | } else { | |
45100 | m68k_incpc(4); | |
45101 | fill_prefetch_0 (); | |
45102 | return 14; | |
45103 | } | |
45104 | } | |
45105 | }}}m68k_incpc(4); | |
45106 | fill_prefetch_0 (); | |
45107 | endlabel2493: ; | |
45108 | return 12; | |
45109 | } | |
45110 | unsigned long CPUFUNC(op_55d0_5)(uint32_t opcode) /* Scc */ | |
45111 | { | |
45112 | uint32_t srcreg = (opcode & 7); | |
45113 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
45114 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
45115 | { int val = cctrue(5) ? 0xff : 0; | |
45116 | m68k_incpc(2); | |
45117 | fill_prefetch_2 (); | |
45118 | m68k_write_memory_8(srca,val); | |
45119 | }}}return 12; | |
45120 | } | |
45121 | unsigned long CPUFUNC(op_55d8_5)(uint32_t opcode) /* Scc */ | |
45122 | { | |
45123 | uint32_t srcreg = (opcode & 7); | |
45124 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
45125 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
45126 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
45127 | { int val = cctrue(5) ? 0xff : 0; | |
45128 | m68k_incpc(2); | |
45129 | fill_prefetch_2 (); | |
45130 | m68k_write_memory_8(srca,val); | |
45131 | }}}return 12; | |
45132 | } | |
45133 | unsigned long CPUFUNC(op_55e0_5)(uint32_t opcode) /* Scc */ | |
45134 | { | |
45135 | uint32_t srcreg = (opcode & 7); | |
45136 | OpcodeFamily = 59; CurrentInstrCycles = 14; | |
45137 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
45138 | m68k_areg (regs, srcreg) = srca; | |
45139 | { int val = cctrue(5) ? 0xff : 0; | |
45140 | m68k_incpc(2); | |
45141 | fill_prefetch_2 (); | |
45142 | m68k_write_memory_8(srca,val); | |
45143 | }}}return 14; | |
45144 | } | |
45145 | unsigned long CPUFUNC(op_55e8_5)(uint32_t opcode) /* Scc */ | |
45146 | { | |
45147 | uint32_t srcreg = (opcode & 7); | |
45148 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
45149 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
45150 | { int val = cctrue(5) ? 0xff : 0; | |
45151 | m68k_incpc(4); | |
45152 | fill_prefetch_0 (); | |
45153 | m68k_write_memory_8(srca,val); | |
45154 | }}}return 16; | |
45155 | } | |
45156 | unsigned long CPUFUNC(op_55f0_5)(uint32_t opcode) /* Scc */ | |
45157 | { | |
45158 | uint32_t srcreg = (opcode & 7); | |
45159 | OpcodeFamily = 59; CurrentInstrCycles = 18; | |
45160 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
45161 | BusCyclePenalty += 2; | |
45162 | { int val = cctrue(5) ? 0xff : 0; | |
45163 | m68k_incpc(4); | |
45164 | fill_prefetch_0 (); | |
45165 | m68k_write_memory_8(srca,val); | |
45166 | }}}return 18; | |
45167 | } | |
45168 | unsigned long CPUFUNC(op_55f8_5)(uint32_t opcode) /* Scc */ | |
45169 | { | |
45170 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
45171 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
45172 | { int val = cctrue(5) ? 0xff : 0; | |
45173 | m68k_incpc(4); | |
45174 | fill_prefetch_0 (); | |
45175 | m68k_write_memory_8(srca,val); | |
45176 | }}}return 16; | |
45177 | } | |
45178 | unsigned long CPUFUNC(op_55f9_5)(uint32_t opcode) /* Scc */ | |
45179 | { | |
45180 | OpcodeFamily = 59; CurrentInstrCycles = 20; | |
45181 | {{ uint32_t srca = get_ilong_prefetch(2); | |
45182 | { int val = cctrue(5) ? 0xff : 0; | |
45183 | m68k_incpc(6); | |
45184 | fill_prefetch_0 (); | |
45185 | m68k_write_memory_8(srca,val); | |
45186 | }}}return 20; | |
45187 | } | |
45188 | unsigned long CPUFUNC(op_56c0_5)(uint32_t opcode) /* Scc */ | |
45189 | { | |
45190 | uint32_t srcreg = (opcode & 7); | |
45191 | OpcodeFamily = 59; CurrentInstrCycles = 4; | |
45192 | {{{ int val = cctrue(6) ? 0xff : 0; | |
45193 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); | |
45194 | if (val) { m68k_incpc(2) ; return 4+2; } | |
45195 | }}}m68k_incpc(2); | |
45196 | fill_prefetch_2 (); | |
45197 | return 4; | |
45198 | } | |
45199 | unsigned long CPUFUNC(op_56c8_5)(uint32_t opcode) /* DBcc */ | |
45200 | { | |
45201 | uint32_t srcreg = (opcode & 7); | |
45202 | OpcodeFamily = 58; CurrentInstrCycles = 12; | |
45203 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
45204 | { int16_t offs = get_iword_prefetch(2); | |
45205 | if (!cctrue(6)) { | |
45206 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); | |
45207 | if (src) { | |
45208 | if (offs & 1) { | |
45209 | last_addr_for_exception_3 = m68k_getpc() + 2 + 2; | |
45210 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)offs + 2; | |
45211 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2502; | |
45212 | } | |
45213 | m68k_incpc((int32_t)offs + 2); | |
45214 | fill_prefetch_0 (); | |
45215 | return 10; | |
45216 | } else { | |
45217 | m68k_incpc(4); | |
45218 | fill_prefetch_0 (); | |
45219 | return 14; | |
45220 | } | |
45221 | } | |
45222 | }}}m68k_incpc(4); | |
45223 | fill_prefetch_0 (); | |
45224 | endlabel2502: ; | |
45225 | return 12; | |
45226 | } | |
45227 | unsigned long CPUFUNC(op_56d0_5)(uint32_t opcode) /* Scc */ | |
45228 | { | |
45229 | uint32_t srcreg = (opcode & 7); | |
45230 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
45231 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
45232 | { int val = cctrue(6) ? 0xff : 0; | |
45233 | m68k_incpc(2); | |
45234 | fill_prefetch_2 (); | |
45235 | m68k_write_memory_8(srca,val); | |
45236 | }}}return 12; | |
45237 | } | |
45238 | unsigned long CPUFUNC(op_56d8_5)(uint32_t opcode) /* Scc */ | |
45239 | { | |
45240 | uint32_t srcreg = (opcode & 7); | |
45241 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
45242 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
45243 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
45244 | { int val = cctrue(6) ? 0xff : 0; | |
45245 | m68k_incpc(2); | |
45246 | fill_prefetch_2 (); | |
45247 | m68k_write_memory_8(srca,val); | |
45248 | }}}return 12; | |
45249 | } | |
45250 | unsigned long CPUFUNC(op_56e0_5)(uint32_t opcode) /* Scc */ | |
45251 | { | |
45252 | uint32_t srcreg = (opcode & 7); | |
45253 | OpcodeFamily = 59; CurrentInstrCycles = 14; | |
45254 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
45255 | m68k_areg (regs, srcreg) = srca; | |
45256 | { int val = cctrue(6) ? 0xff : 0; | |
45257 | m68k_incpc(2); | |
45258 | fill_prefetch_2 (); | |
45259 | m68k_write_memory_8(srca,val); | |
45260 | }}}return 14; | |
45261 | } | |
45262 | unsigned long CPUFUNC(op_56e8_5)(uint32_t opcode) /* Scc */ | |
45263 | { | |
45264 | uint32_t srcreg = (opcode & 7); | |
45265 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
45266 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
45267 | { int val = cctrue(6) ? 0xff : 0; | |
45268 | m68k_incpc(4); | |
45269 | fill_prefetch_0 (); | |
45270 | m68k_write_memory_8(srca,val); | |
45271 | }}}return 16; | |
45272 | } | |
45273 | unsigned long CPUFUNC(op_56f0_5)(uint32_t opcode) /* Scc */ | |
45274 | { | |
45275 | uint32_t srcreg = (opcode & 7); | |
45276 | OpcodeFamily = 59; CurrentInstrCycles = 18; | |
45277 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
45278 | BusCyclePenalty += 2; | |
45279 | { int val = cctrue(6) ? 0xff : 0; | |
45280 | m68k_incpc(4); | |
45281 | fill_prefetch_0 (); | |
45282 | m68k_write_memory_8(srca,val); | |
45283 | }}}return 18; | |
45284 | } | |
45285 | unsigned long CPUFUNC(op_56f8_5)(uint32_t opcode) /* Scc */ | |
45286 | { | |
45287 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
45288 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
45289 | { int val = cctrue(6) ? 0xff : 0; | |
45290 | m68k_incpc(4); | |
45291 | fill_prefetch_0 (); | |
45292 | m68k_write_memory_8(srca,val); | |
45293 | }}}return 16; | |
45294 | } | |
45295 | unsigned long CPUFUNC(op_56f9_5)(uint32_t opcode) /* Scc */ | |
45296 | { | |
45297 | OpcodeFamily = 59; CurrentInstrCycles = 20; | |
45298 | {{ uint32_t srca = get_ilong_prefetch(2); | |
45299 | { int val = cctrue(6) ? 0xff : 0; | |
45300 | m68k_incpc(6); | |
45301 | fill_prefetch_0 (); | |
45302 | m68k_write_memory_8(srca,val); | |
45303 | }}}return 20; | |
45304 | } | |
45305 | unsigned long CPUFUNC(op_57c0_5)(uint32_t opcode) /* Scc */ | |
45306 | { | |
45307 | uint32_t srcreg = (opcode & 7); | |
45308 | OpcodeFamily = 59; CurrentInstrCycles = 4; | |
45309 | {{{ int val = cctrue(7) ? 0xff : 0; | |
45310 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); | |
45311 | if (val) { m68k_incpc(2) ; return 4+2; } | |
45312 | }}}m68k_incpc(2); | |
45313 | fill_prefetch_2 (); | |
45314 | return 4; | |
45315 | } | |
45316 | unsigned long CPUFUNC(op_57c8_5)(uint32_t opcode) /* DBcc */ | |
45317 | { | |
45318 | uint32_t srcreg = (opcode & 7); | |
45319 | OpcodeFamily = 58; CurrentInstrCycles = 12; | |
45320 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
45321 | { int16_t offs = get_iword_prefetch(2); | |
45322 | if (!cctrue(7)) { | |
45323 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); | |
45324 | if (src) { | |
45325 | if (offs & 1) { | |
45326 | last_addr_for_exception_3 = m68k_getpc() + 2 + 2; | |
45327 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)offs + 2; | |
45328 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2511; | |
45329 | } | |
45330 | m68k_incpc((int32_t)offs + 2); | |
45331 | fill_prefetch_0 (); | |
45332 | return 10; | |
45333 | } else { | |
45334 | m68k_incpc(4); | |
45335 | fill_prefetch_0 (); | |
45336 | return 14; | |
45337 | } | |
45338 | } | |
45339 | }}}m68k_incpc(4); | |
45340 | fill_prefetch_0 (); | |
45341 | endlabel2511: ; | |
45342 | return 12; | |
45343 | } | |
45344 | unsigned long CPUFUNC(op_57d0_5)(uint32_t opcode) /* Scc */ | |
45345 | { | |
45346 | uint32_t srcreg = (opcode & 7); | |
45347 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
45348 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
45349 | { int val = cctrue(7) ? 0xff : 0; | |
45350 | m68k_incpc(2); | |
45351 | fill_prefetch_2 (); | |
45352 | m68k_write_memory_8(srca,val); | |
45353 | }}}return 12; | |
45354 | } | |
45355 | unsigned long CPUFUNC(op_57d8_5)(uint32_t opcode) /* Scc */ | |
45356 | { | |
45357 | uint32_t srcreg = (opcode & 7); | |
45358 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
45359 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
45360 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
45361 | { int val = cctrue(7) ? 0xff : 0; | |
45362 | m68k_incpc(2); | |
45363 | fill_prefetch_2 (); | |
45364 | m68k_write_memory_8(srca,val); | |
45365 | }}}return 12; | |
45366 | } | |
45367 | unsigned long CPUFUNC(op_57e0_5)(uint32_t opcode) /* Scc */ | |
45368 | { | |
45369 | uint32_t srcreg = (opcode & 7); | |
45370 | OpcodeFamily = 59; CurrentInstrCycles = 14; | |
45371 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
45372 | m68k_areg (regs, srcreg) = srca; | |
45373 | { int val = cctrue(7) ? 0xff : 0; | |
45374 | m68k_incpc(2); | |
45375 | fill_prefetch_2 (); | |
45376 | m68k_write_memory_8(srca,val); | |
45377 | }}}return 14; | |
45378 | } | |
45379 | unsigned long CPUFUNC(op_57e8_5)(uint32_t opcode) /* Scc */ | |
45380 | { | |
45381 | uint32_t srcreg = (opcode & 7); | |
45382 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
45383 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
45384 | { int val = cctrue(7) ? 0xff : 0; | |
45385 | m68k_incpc(4); | |
45386 | fill_prefetch_0 (); | |
45387 | m68k_write_memory_8(srca,val); | |
45388 | }}}return 16; | |
45389 | } | |
45390 | unsigned long CPUFUNC(op_57f0_5)(uint32_t opcode) /* Scc */ | |
45391 | { | |
45392 | uint32_t srcreg = (opcode & 7); | |
45393 | OpcodeFamily = 59; CurrentInstrCycles = 18; | |
45394 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
45395 | BusCyclePenalty += 2; | |
45396 | { int val = cctrue(7) ? 0xff : 0; | |
45397 | m68k_incpc(4); | |
45398 | fill_prefetch_0 (); | |
45399 | m68k_write_memory_8(srca,val); | |
45400 | }}}return 18; | |
45401 | } | |
45402 | unsigned long CPUFUNC(op_57f8_5)(uint32_t opcode) /* Scc */ | |
45403 | { | |
45404 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
45405 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
45406 | { int val = cctrue(7) ? 0xff : 0; | |
45407 | m68k_incpc(4); | |
45408 | fill_prefetch_0 (); | |
45409 | m68k_write_memory_8(srca,val); | |
45410 | }}}return 16; | |
45411 | } | |
45412 | unsigned long CPUFUNC(op_57f9_5)(uint32_t opcode) /* Scc */ | |
45413 | { | |
45414 | OpcodeFamily = 59; CurrentInstrCycles = 20; | |
45415 | {{ uint32_t srca = get_ilong_prefetch(2); | |
45416 | { int val = cctrue(7) ? 0xff : 0; | |
45417 | m68k_incpc(6); | |
45418 | fill_prefetch_0 (); | |
45419 | m68k_write_memory_8(srca,val); | |
45420 | }}}return 20; | |
45421 | } | |
45422 | unsigned long CPUFUNC(op_58c0_5)(uint32_t opcode) /* Scc */ | |
45423 | { | |
45424 | uint32_t srcreg = (opcode & 7); | |
45425 | OpcodeFamily = 59; CurrentInstrCycles = 4; | |
45426 | {{{ int val = cctrue(8) ? 0xff : 0; | |
45427 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); | |
45428 | if (val) { m68k_incpc(2) ; return 4+2; } | |
45429 | }}}m68k_incpc(2); | |
45430 | fill_prefetch_2 (); | |
45431 | return 4; | |
45432 | } | |
45433 | unsigned long CPUFUNC(op_58c8_5)(uint32_t opcode) /* DBcc */ | |
45434 | { | |
45435 | uint32_t srcreg = (opcode & 7); | |
45436 | OpcodeFamily = 58; CurrentInstrCycles = 12; | |
45437 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
45438 | { int16_t offs = get_iword_prefetch(2); | |
45439 | if (!cctrue(8)) { | |
45440 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); | |
45441 | if (src) { | |
45442 | if (offs & 1) { | |
45443 | last_addr_for_exception_3 = m68k_getpc() + 2 + 2; | |
45444 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)offs + 2; | |
45445 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2520; | |
45446 | } | |
45447 | m68k_incpc((int32_t)offs + 2); | |
45448 | fill_prefetch_0 (); | |
45449 | return 10; | |
45450 | } else { | |
45451 | m68k_incpc(4); | |
45452 | fill_prefetch_0 (); | |
45453 | return 14; | |
45454 | } | |
45455 | } | |
45456 | }}}m68k_incpc(4); | |
45457 | fill_prefetch_0 (); | |
45458 | endlabel2520: ; | |
45459 | return 12; | |
45460 | } | |
45461 | unsigned long CPUFUNC(op_58d0_5)(uint32_t opcode) /* Scc */ | |
45462 | { | |
45463 | uint32_t srcreg = (opcode & 7); | |
45464 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
45465 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
45466 | { int val = cctrue(8) ? 0xff : 0; | |
45467 | m68k_incpc(2); | |
45468 | fill_prefetch_2 (); | |
45469 | m68k_write_memory_8(srca,val); | |
45470 | }}}return 12; | |
45471 | } | |
45472 | unsigned long CPUFUNC(op_58d8_5)(uint32_t opcode) /* Scc */ | |
45473 | { | |
45474 | uint32_t srcreg = (opcode & 7); | |
45475 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
45476 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
45477 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
45478 | { int val = cctrue(8) ? 0xff : 0; | |
45479 | m68k_incpc(2); | |
45480 | fill_prefetch_2 (); | |
45481 | m68k_write_memory_8(srca,val); | |
45482 | }}}return 12; | |
45483 | } | |
45484 | unsigned long CPUFUNC(op_58e0_5)(uint32_t opcode) /* Scc */ | |
45485 | { | |
45486 | uint32_t srcreg = (opcode & 7); | |
45487 | OpcodeFamily = 59; CurrentInstrCycles = 14; | |
45488 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
45489 | m68k_areg (regs, srcreg) = srca; | |
45490 | { int val = cctrue(8) ? 0xff : 0; | |
45491 | m68k_incpc(2); | |
45492 | fill_prefetch_2 (); | |
45493 | m68k_write_memory_8(srca,val); | |
45494 | }}}return 14; | |
45495 | } | |
45496 | unsigned long CPUFUNC(op_58e8_5)(uint32_t opcode) /* Scc */ | |
45497 | { | |
45498 | uint32_t srcreg = (opcode & 7); | |
45499 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
45500 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
45501 | { int val = cctrue(8) ? 0xff : 0; | |
45502 | m68k_incpc(4); | |
45503 | fill_prefetch_0 (); | |
45504 | m68k_write_memory_8(srca,val); | |
45505 | }}}return 16; | |
45506 | } | |
45507 | unsigned long CPUFUNC(op_58f0_5)(uint32_t opcode) /* Scc */ | |
45508 | { | |
45509 | uint32_t srcreg = (opcode & 7); | |
45510 | OpcodeFamily = 59; CurrentInstrCycles = 18; | |
45511 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
45512 | BusCyclePenalty += 2; | |
45513 | { int val = cctrue(8) ? 0xff : 0; | |
45514 | m68k_incpc(4); | |
45515 | fill_prefetch_0 (); | |
45516 | m68k_write_memory_8(srca,val); | |
45517 | }}}return 18; | |
45518 | } | |
45519 | unsigned long CPUFUNC(op_58f8_5)(uint32_t opcode) /* Scc */ | |
45520 | { | |
45521 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
45522 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
45523 | { int val = cctrue(8) ? 0xff : 0; | |
45524 | m68k_incpc(4); | |
45525 | fill_prefetch_0 (); | |
45526 | m68k_write_memory_8(srca,val); | |
45527 | }}}return 16; | |
45528 | } | |
45529 | unsigned long CPUFUNC(op_58f9_5)(uint32_t opcode) /* Scc */ | |
45530 | { | |
45531 | OpcodeFamily = 59; CurrentInstrCycles = 20; | |
45532 | {{ uint32_t srca = get_ilong_prefetch(2); | |
45533 | { int val = cctrue(8) ? 0xff : 0; | |
45534 | m68k_incpc(6); | |
45535 | fill_prefetch_0 (); | |
45536 | m68k_write_memory_8(srca,val); | |
45537 | }}}return 20; | |
45538 | } | |
45539 | unsigned long CPUFUNC(op_59c0_5)(uint32_t opcode) /* Scc */ | |
45540 | { | |
45541 | uint32_t srcreg = (opcode & 7); | |
45542 | OpcodeFamily = 59; CurrentInstrCycles = 4; | |
45543 | {{{ int val = cctrue(9) ? 0xff : 0; | |
45544 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); | |
45545 | if (val) { m68k_incpc(2) ; return 4+2; } | |
45546 | }}}m68k_incpc(2); | |
45547 | fill_prefetch_2 (); | |
45548 | return 4; | |
45549 | } | |
45550 | unsigned long CPUFUNC(op_59c8_5)(uint32_t opcode) /* DBcc */ | |
45551 | { | |
45552 | uint32_t srcreg = (opcode & 7); | |
45553 | OpcodeFamily = 58; CurrentInstrCycles = 12; | |
45554 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
45555 | { int16_t offs = get_iword_prefetch(2); | |
45556 | if (!cctrue(9)) { | |
45557 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); | |
45558 | if (src) { | |
45559 | if (offs & 1) { | |
45560 | last_addr_for_exception_3 = m68k_getpc() + 2 + 2; | |
45561 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)offs + 2; | |
45562 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2529; | |
45563 | } | |
45564 | m68k_incpc((int32_t)offs + 2); | |
45565 | fill_prefetch_0 (); | |
45566 | return 10; | |
45567 | } else { | |
45568 | m68k_incpc(4); | |
45569 | fill_prefetch_0 (); | |
45570 | return 14; | |
45571 | } | |
45572 | } | |
45573 | }}}m68k_incpc(4); | |
45574 | fill_prefetch_0 (); | |
45575 | endlabel2529: ; | |
45576 | return 12; | |
45577 | } | |
45578 | unsigned long CPUFUNC(op_59d0_5)(uint32_t opcode) /* Scc */ | |
45579 | { | |
45580 | uint32_t srcreg = (opcode & 7); | |
45581 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
45582 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
45583 | { int val = cctrue(9) ? 0xff : 0; | |
45584 | m68k_incpc(2); | |
45585 | fill_prefetch_2 (); | |
45586 | m68k_write_memory_8(srca,val); | |
45587 | }}}return 12; | |
45588 | } | |
45589 | unsigned long CPUFUNC(op_59d8_5)(uint32_t opcode) /* Scc */ | |
45590 | { | |
45591 | uint32_t srcreg = (opcode & 7); | |
45592 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
45593 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
45594 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
45595 | { int val = cctrue(9) ? 0xff : 0; | |
45596 | m68k_incpc(2); | |
45597 | fill_prefetch_2 (); | |
45598 | m68k_write_memory_8(srca,val); | |
45599 | }}}return 12; | |
45600 | } | |
45601 | unsigned long CPUFUNC(op_59e0_5)(uint32_t opcode) /* Scc */ | |
45602 | { | |
45603 | uint32_t srcreg = (opcode & 7); | |
45604 | OpcodeFamily = 59; CurrentInstrCycles = 14; | |
45605 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
45606 | m68k_areg (regs, srcreg) = srca; | |
45607 | { int val = cctrue(9) ? 0xff : 0; | |
45608 | m68k_incpc(2); | |
45609 | fill_prefetch_2 (); | |
45610 | m68k_write_memory_8(srca,val); | |
45611 | }}}return 14; | |
45612 | } | |
45613 | unsigned long CPUFUNC(op_59e8_5)(uint32_t opcode) /* Scc */ | |
45614 | { | |
45615 | uint32_t srcreg = (opcode & 7); | |
45616 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
45617 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
45618 | { int val = cctrue(9) ? 0xff : 0; | |
45619 | m68k_incpc(4); | |
45620 | fill_prefetch_0 (); | |
45621 | m68k_write_memory_8(srca,val); | |
45622 | }}}return 16; | |
45623 | } | |
45624 | unsigned long CPUFUNC(op_59f0_5)(uint32_t opcode) /* Scc */ | |
45625 | { | |
45626 | uint32_t srcreg = (opcode & 7); | |
45627 | OpcodeFamily = 59; CurrentInstrCycles = 18; | |
45628 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
45629 | BusCyclePenalty += 2; | |
45630 | { int val = cctrue(9) ? 0xff : 0; | |
45631 | m68k_incpc(4); | |
45632 | fill_prefetch_0 (); | |
45633 | m68k_write_memory_8(srca,val); | |
45634 | }}}return 18; | |
45635 | } | |
45636 | unsigned long CPUFUNC(op_59f8_5)(uint32_t opcode) /* Scc */ | |
45637 | { | |
45638 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
45639 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
45640 | { int val = cctrue(9) ? 0xff : 0; | |
45641 | m68k_incpc(4); | |
45642 | fill_prefetch_0 (); | |
45643 | m68k_write_memory_8(srca,val); | |
45644 | }}}return 16; | |
45645 | } | |
45646 | unsigned long CPUFUNC(op_59f9_5)(uint32_t opcode) /* Scc */ | |
45647 | { | |
45648 | OpcodeFamily = 59; CurrentInstrCycles = 20; | |
45649 | {{ uint32_t srca = get_ilong_prefetch(2); | |
45650 | { int val = cctrue(9) ? 0xff : 0; | |
45651 | m68k_incpc(6); | |
45652 | fill_prefetch_0 (); | |
45653 | m68k_write_memory_8(srca,val); | |
45654 | }}}return 20; | |
45655 | } | |
45656 | unsigned long CPUFUNC(op_5ac0_5)(uint32_t opcode) /* Scc */ | |
45657 | { | |
45658 | uint32_t srcreg = (opcode & 7); | |
45659 | OpcodeFamily = 59; CurrentInstrCycles = 4; | |
45660 | {{{ int val = cctrue(10) ? 0xff : 0; | |
45661 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); | |
45662 | if (val) { m68k_incpc(2) ; return 4+2; } | |
45663 | }}}m68k_incpc(2); | |
45664 | fill_prefetch_2 (); | |
45665 | return 4; | |
45666 | } | |
45667 | unsigned long CPUFUNC(op_5ac8_5)(uint32_t opcode) /* DBcc */ | |
45668 | { | |
45669 | uint32_t srcreg = (opcode & 7); | |
45670 | OpcodeFamily = 58; CurrentInstrCycles = 12; | |
45671 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
45672 | { int16_t offs = get_iword_prefetch(2); | |
45673 | if (!cctrue(10)) { | |
45674 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); | |
45675 | if (src) { | |
45676 | if (offs & 1) { | |
45677 | last_addr_for_exception_3 = m68k_getpc() + 2 + 2; | |
45678 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)offs + 2; | |
45679 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2538; | |
45680 | } | |
45681 | m68k_incpc((int32_t)offs + 2); | |
45682 | fill_prefetch_0 (); | |
45683 | return 10; | |
45684 | } else { | |
45685 | m68k_incpc(4); | |
45686 | fill_prefetch_0 (); | |
45687 | return 14; | |
45688 | } | |
45689 | } | |
45690 | }}}m68k_incpc(4); | |
45691 | fill_prefetch_0 (); | |
45692 | endlabel2538: ; | |
45693 | return 12; | |
45694 | } | |
45695 | unsigned long CPUFUNC(op_5ad0_5)(uint32_t opcode) /* Scc */ | |
45696 | { | |
45697 | uint32_t srcreg = (opcode & 7); | |
45698 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
45699 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
45700 | { int val = cctrue(10) ? 0xff : 0; | |
45701 | m68k_incpc(2); | |
45702 | fill_prefetch_2 (); | |
45703 | m68k_write_memory_8(srca,val); | |
45704 | }}}return 12; | |
45705 | } | |
45706 | unsigned long CPUFUNC(op_5ad8_5)(uint32_t opcode) /* Scc */ | |
45707 | { | |
45708 | uint32_t srcreg = (opcode & 7); | |
45709 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
45710 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
45711 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
45712 | { int val = cctrue(10) ? 0xff : 0; | |
45713 | m68k_incpc(2); | |
45714 | fill_prefetch_2 (); | |
45715 | m68k_write_memory_8(srca,val); | |
45716 | }}}return 12; | |
45717 | } | |
45718 | unsigned long CPUFUNC(op_5ae0_5)(uint32_t opcode) /* Scc */ | |
45719 | { | |
45720 | uint32_t srcreg = (opcode & 7); | |
45721 | OpcodeFamily = 59; CurrentInstrCycles = 14; | |
45722 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
45723 | m68k_areg (regs, srcreg) = srca; | |
45724 | { int val = cctrue(10) ? 0xff : 0; | |
45725 | m68k_incpc(2); | |
45726 | fill_prefetch_2 (); | |
45727 | m68k_write_memory_8(srca,val); | |
45728 | }}}return 14; | |
45729 | } | |
45730 | unsigned long CPUFUNC(op_5ae8_5)(uint32_t opcode) /* Scc */ | |
45731 | { | |
45732 | uint32_t srcreg = (opcode & 7); | |
45733 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
45734 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
45735 | { int val = cctrue(10) ? 0xff : 0; | |
45736 | m68k_incpc(4); | |
45737 | fill_prefetch_0 (); | |
45738 | m68k_write_memory_8(srca,val); | |
45739 | }}}return 16; | |
45740 | } | |
45741 | unsigned long CPUFUNC(op_5af0_5)(uint32_t opcode) /* Scc */ | |
45742 | { | |
45743 | uint32_t srcreg = (opcode & 7); | |
45744 | OpcodeFamily = 59; CurrentInstrCycles = 18; | |
45745 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
45746 | BusCyclePenalty += 2; | |
45747 | { int val = cctrue(10) ? 0xff : 0; | |
45748 | m68k_incpc(4); | |
45749 | fill_prefetch_0 (); | |
45750 | m68k_write_memory_8(srca,val); | |
45751 | }}}return 18; | |
45752 | } | |
45753 | unsigned long CPUFUNC(op_5af8_5)(uint32_t opcode) /* Scc */ | |
45754 | { | |
45755 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
45756 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
45757 | { int val = cctrue(10) ? 0xff : 0; | |
45758 | m68k_incpc(4); | |
45759 | fill_prefetch_0 (); | |
45760 | m68k_write_memory_8(srca,val); | |
45761 | }}}return 16; | |
45762 | } | |
45763 | unsigned long CPUFUNC(op_5af9_5)(uint32_t opcode) /* Scc */ | |
45764 | { | |
45765 | OpcodeFamily = 59; CurrentInstrCycles = 20; | |
45766 | {{ uint32_t srca = get_ilong_prefetch(2); | |
45767 | { int val = cctrue(10) ? 0xff : 0; | |
45768 | m68k_incpc(6); | |
45769 | fill_prefetch_0 (); | |
45770 | m68k_write_memory_8(srca,val); | |
45771 | }}}return 20; | |
45772 | } | |
45773 | unsigned long CPUFUNC(op_5bc0_5)(uint32_t opcode) /* Scc */ | |
45774 | { | |
45775 | uint32_t srcreg = (opcode & 7); | |
45776 | OpcodeFamily = 59; CurrentInstrCycles = 4; | |
45777 | {{{ int val = cctrue(11) ? 0xff : 0; | |
45778 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); | |
45779 | if (val) { m68k_incpc(2) ; return 4+2; } | |
45780 | }}}m68k_incpc(2); | |
45781 | fill_prefetch_2 (); | |
45782 | return 4; | |
45783 | } | |
45784 | unsigned long CPUFUNC(op_5bc8_5)(uint32_t opcode) /* DBcc */ | |
45785 | { | |
45786 | uint32_t srcreg = (opcode & 7); | |
45787 | OpcodeFamily = 58; CurrentInstrCycles = 12; | |
45788 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
45789 | { int16_t offs = get_iword_prefetch(2); | |
45790 | if (!cctrue(11)) { | |
45791 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); | |
45792 | if (src) { | |
45793 | if (offs & 1) { | |
45794 | last_addr_for_exception_3 = m68k_getpc() + 2 + 2; | |
45795 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)offs + 2; | |
45796 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2547; | |
45797 | } | |
45798 | m68k_incpc((int32_t)offs + 2); | |
45799 | fill_prefetch_0 (); | |
45800 | return 10; | |
45801 | } else { | |
45802 | m68k_incpc(4); | |
45803 | fill_prefetch_0 (); | |
45804 | return 14; | |
45805 | } | |
45806 | } | |
45807 | }}}m68k_incpc(4); | |
45808 | fill_prefetch_0 (); | |
45809 | endlabel2547: ; | |
45810 | return 12; | |
45811 | } | |
45812 | unsigned long CPUFUNC(op_5bd0_5)(uint32_t opcode) /* Scc */ | |
45813 | { | |
45814 | uint32_t srcreg = (opcode & 7); | |
45815 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
45816 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
45817 | { int val = cctrue(11) ? 0xff : 0; | |
45818 | m68k_incpc(2); | |
45819 | fill_prefetch_2 (); | |
45820 | m68k_write_memory_8(srca,val); | |
45821 | }}}return 12; | |
45822 | } | |
45823 | unsigned long CPUFUNC(op_5bd8_5)(uint32_t opcode) /* Scc */ | |
45824 | { | |
45825 | uint32_t srcreg = (opcode & 7); | |
45826 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
45827 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
45828 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
45829 | { int val = cctrue(11) ? 0xff : 0; | |
45830 | m68k_incpc(2); | |
45831 | fill_prefetch_2 (); | |
45832 | m68k_write_memory_8(srca,val); | |
45833 | }}}return 12; | |
45834 | } | |
45835 | unsigned long CPUFUNC(op_5be0_5)(uint32_t opcode) /* Scc */ | |
45836 | { | |
45837 | uint32_t srcreg = (opcode & 7); | |
45838 | OpcodeFamily = 59; CurrentInstrCycles = 14; | |
45839 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
45840 | m68k_areg (regs, srcreg) = srca; | |
45841 | { int val = cctrue(11) ? 0xff : 0; | |
45842 | m68k_incpc(2); | |
45843 | fill_prefetch_2 (); | |
45844 | m68k_write_memory_8(srca,val); | |
45845 | }}}return 14; | |
45846 | } | |
45847 | unsigned long CPUFUNC(op_5be8_5)(uint32_t opcode) /* Scc */ | |
45848 | { | |
45849 | uint32_t srcreg = (opcode & 7); | |
45850 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
45851 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
45852 | { int val = cctrue(11) ? 0xff : 0; | |
45853 | m68k_incpc(4); | |
45854 | fill_prefetch_0 (); | |
45855 | m68k_write_memory_8(srca,val); | |
45856 | }}}return 16; | |
45857 | } | |
45858 | unsigned long CPUFUNC(op_5bf0_5)(uint32_t opcode) /* Scc */ | |
45859 | { | |
45860 | uint32_t srcreg = (opcode & 7); | |
45861 | OpcodeFamily = 59; CurrentInstrCycles = 18; | |
45862 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
45863 | BusCyclePenalty += 2; | |
45864 | { int val = cctrue(11) ? 0xff : 0; | |
45865 | m68k_incpc(4); | |
45866 | fill_prefetch_0 (); | |
45867 | m68k_write_memory_8(srca,val); | |
45868 | }}}return 18; | |
45869 | } | |
45870 | unsigned long CPUFUNC(op_5bf8_5)(uint32_t opcode) /* Scc */ | |
45871 | { | |
45872 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
45873 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
45874 | { int val = cctrue(11) ? 0xff : 0; | |
45875 | m68k_incpc(4); | |
45876 | fill_prefetch_0 (); | |
45877 | m68k_write_memory_8(srca,val); | |
45878 | }}}return 16; | |
45879 | } | |
45880 | unsigned long CPUFUNC(op_5bf9_5)(uint32_t opcode) /* Scc */ | |
45881 | { | |
45882 | OpcodeFamily = 59; CurrentInstrCycles = 20; | |
45883 | {{ uint32_t srca = get_ilong_prefetch(2); | |
45884 | { int val = cctrue(11) ? 0xff : 0; | |
45885 | m68k_incpc(6); | |
45886 | fill_prefetch_0 (); | |
45887 | m68k_write_memory_8(srca,val); | |
45888 | }}}return 20; | |
45889 | } | |
45890 | unsigned long CPUFUNC(op_5cc0_5)(uint32_t opcode) /* Scc */ | |
45891 | { | |
45892 | uint32_t srcreg = (opcode & 7); | |
45893 | OpcodeFamily = 59; CurrentInstrCycles = 4; | |
45894 | {{{ int val = cctrue(12) ? 0xff : 0; | |
45895 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); | |
45896 | if (val) { m68k_incpc(2) ; return 4+2; } | |
45897 | }}}m68k_incpc(2); | |
45898 | fill_prefetch_2 (); | |
45899 | return 4; | |
45900 | } | |
45901 | unsigned long CPUFUNC(op_5cc8_5)(uint32_t opcode) /* DBcc */ | |
45902 | { | |
45903 | uint32_t srcreg = (opcode & 7); | |
45904 | OpcodeFamily = 58; CurrentInstrCycles = 12; | |
45905 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
45906 | { int16_t offs = get_iword_prefetch(2); | |
45907 | if (!cctrue(12)) { | |
45908 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); | |
45909 | if (src) { | |
45910 | if (offs & 1) { | |
45911 | last_addr_for_exception_3 = m68k_getpc() + 2 + 2; | |
45912 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)offs + 2; | |
45913 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2556; | |
45914 | } | |
45915 | m68k_incpc((int32_t)offs + 2); | |
45916 | fill_prefetch_0 (); | |
45917 | return 10; | |
45918 | } else { | |
45919 | m68k_incpc(4); | |
45920 | fill_prefetch_0 (); | |
45921 | return 14; | |
45922 | } | |
45923 | } | |
45924 | }}}m68k_incpc(4); | |
45925 | fill_prefetch_0 (); | |
45926 | endlabel2556: ; | |
45927 | return 12; | |
45928 | } | |
45929 | unsigned long CPUFUNC(op_5cd0_5)(uint32_t opcode) /* Scc */ | |
45930 | { | |
45931 | uint32_t srcreg = (opcode & 7); | |
45932 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
45933 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
45934 | { int val = cctrue(12) ? 0xff : 0; | |
45935 | m68k_incpc(2); | |
45936 | fill_prefetch_2 (); | |
45937 | m68k_write_memory_8(srca,val); | |
45938 | }}}return 12; | |
45939 | } | |
45940 | unsigned long CPUFUNC(op_5cd8_5)(uint32_t opcode) /* Scc */ | |
45941 | { | |
45942 | uint32_t srcreg = (opcode & 7); | |
45943 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
45944 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
45945 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
45946 | { int val = cctrue(12) ? 0xff : 0; | |
45947 | m68k_incpc(2); | |
45948 | fill_prefetch_2 (); | |
45949 | m68k_write_memory_8(srca,val); | |
45950 | }}}return 12; | |
45951 | } | |
45952 | unsigned long CPUFUNC(op_5ce0_5)(uint32_t opcode) /* Scc */ | |
45953 | { | |
45954 | uint32_t srcreg = (opcode & 7); | |
45955 | OpcodeFamily = 59; CurrentInstrCycles = 14; | |
45956 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
45957 | m68k_areg (regs, srcreg) = srca; | |
45958 | { int val = cctrue(12) ? 0xff : 0; | |
45959 | m68k_incpc(2); | |
45960 | fill_prefetch_2 (); | |
45961 | m68k_write_memory_8(srca,val); | |
45962 | }}}return 14; | |
45963 | } | |
45964 | unsigned long CPUFUNC(op_5ce8_5)(uint32_t opcode) /* Scc */ | |
45965 | { | |
45966 | uint32_t srcreg = (opcode & 7); | |
45967 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
45968 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
45969 | { int val = cctrue(12) ? 0xff : 0; | |
45970 | m68k_incpc(4); | |
45971 | fill_prefetch_0 (); | |
45972 | m68k_write_memory_8(srca,val); | |
45973 | }}}return 16; | |
45974 | } | |
45975 | unsigned long CPUFUNC(op_5cf0_5)(uint32_t opcode) /* Scc */ | |
45976 | { | |
45977 | uint32_t srcreg = (opcode & 7); | |
45978 | OpcodeFamily = 59; CurrentInstrCycles = 18; | |
45979 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
45980 | BusCyclePenalty += 2; | |
45981 | { int val = cctrue(12) ? 0xff : 0; | |
45982 | m68k_incpc(4); | |
45983 | fill_prefetch_0 (); | |
45984 | m68k_write_memory_8(srca,val); | |
45985 | }}}return 18; | |
45986 | } | |
45987 | unsigned long CPUFUNC(op_5cf8_5)(uint32_t opcode) /* Scc */ | |
45988 | { | |
45989 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
45990 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
45991 | { int val = cctrue(12) ? 0xff : 0; | |
45992 | m68k_incpc(4); | |
45993 | fill_prefetch_0 (); | |
45994 | m68k_write_memory_8(srca,val); | |
45995 | }}}return 16; | |
45996 | } | |
45997 | unsigned long CPUFUNC(op_5cf9_5)(uint32_t opcode) /* Scc */ | |
45998 | { | |
45999 | OpcodeFamily = 59; CurrentInstrCycles = 20; | |
46000 | {{ uint32_t srca = get_ilong_prefetch(2); | |
46001 | { int val = cctrue(12) ? 0xff : 0; | |
46002 | m68k_incpc(6); | |
46003 | fill_prefetch_0 (); | |
46004 | m68k_write_memory_8(srca,val); | |
46005 | }}}return 20; | |
46006 | } | |
46007 | unsigned long CPUFUNC(op_5dc0_5)(uint32_t opcode) /* Scc */ | |
46008 | { | |
46009 | uint32_t srcreg = (opcode & 7); | |
46010 | OpcodeFamily = 59; CurrentInstrCycles = 4; | |
46011 | {{{ int val = cctrue(13) ? 0xff : 0; | |
46012 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); | |
46013 | if (val) { m68k_incpc(2) ; return 4+2; } | |
46014 | }}}m68k_incpc(2); | |
46015 | fill_prefetch_2 (); | |
46016 | return 4; | |
46017 | } | |
46018 | unsigned long CPUFUNC(op_5dc8_5)(uint32_t opcode) /* DBcc */ | |
46019 | { | |
46020 | uint32_t srcreg = (opcode & 7); | |
46021 | OpcodeFamily = 58; CurrentInstrCycles = 12; | |
46022 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
46023 | { int16_t offs = get_iword_prefetch(2); | |
46024 | if (!cctrue(13)) { | |
46025 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); | |
46026 | if (src) { | |
46027 | if (offs & 1) { | |
46028 | last_addr_for_exception_3 = m68k_getpc() + 2 + 2; | |
46029 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)offs + 2; | |
46030 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2565; | |
46031 | } | |
46032 | m68k_incpc((int32_t)offs + 2); | |
46033 | fill_prefetch_0 (); | |
46034 | return 10; | |
46035 | } else { | |
46036 | m68k_incpc(4); | |
46037 | fill_prefetch_0 (); | |
46038 | return 14; | |
46039 | } | |
46040 | } | |
46041 | }}}m68k_incpc(4); | |
46042 | fill_prefetch_0 (); | |
46043 | endlabel2565: ; | |
46044 | return 12; | |
46045 | } | |
46046 | unsigned long CPUFUNC(op_5dd0_5)(uint32_t opcode) /* Scc */ | |
46047 | { | |
46048 | uint32_t srcreg = (opcode & 7); | |
46049 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
46050 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
46051 | { int val = cctrue(13) ? 0xff : 0; | |
46052 | m68k_incpc(2); | |
46053 | fill_prefetch_2 (); | |
46054 | m68k_write_memory_8(srca,val); | |
46055 | }}}return 12; | |
46056 | } | |
46057 | unsigned long CPUFUNC(op_5dd8_5)(uint32_t opcode) /* Scc */ | |
46058 | { | |
46059 | uint32_t srcreg = (opcode & 7); | |
46060 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
46061 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
46062 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
46063 | { int val = cctrue(13) ? 0xff : 0; | |
46064 | m68k_incpc(2); | |
46065 | fill_prefetch_2 (); | |
46066 | m68k_write_memory_8(srca,val); | |
46067 | }}}return 12; | |
46068 | } | |
46069 | unsigned long CPUFUNC(op_5de0_5)(uint32_t opcode) /* Scc */ | |
46070 | { | |
46071 | uint32_t srcreg = (opcode & 7); | |
46072 | OpcodeFamily = 59; CurrentInstrCycles = 14; | |
46073 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
46074 | m68k_areg (regs, srcreg) = srca; | |
46075 | { int val = cctrue(13) ? 0xff : 0; | |
46076 | m68k_incpc(2); | |
46077 | fill_prefetch_2 (); | |
46078 | m68k_write_memory_8(srca,val); | |
46079 | }}}return 14; | |
46080 | } | |
46081 | unsigned long CPUFUNC(op_5de8_5)(uint32_t opcode) /* Scc */ | |
46082 | { | |
46083 | uint32_t srcreg = (opcode & 7); | |
46084 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
46085 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
46086 | { int val = cctrue(13) ? 0xff : 0; | |
46087 | m68k_incpc(4); | |
46088 | fill_prefetch_0 (); | |
46089 | m68k_write_memory_8(srca,val); | |
46090 | }}}return 16; | |
46091 | } | |
46092 | unsigned long CPUFUNC(op_5df0_5)(uint32_t opcode) /* Scc */ | |
46093 | { | |
46094 | uint32_t srcreg = (opcode & 7); | |
46095 | OpcodeFamily = 59; CurrentInstrCycles = 18; | |
46096 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
46097 | BusCyclePenalty += 2; | |
46098 | { int val = cctrue(13) ? 0xff : 0; | |
46099 | m68k_incpc(4); | |
46100 | fill_prefetch_0 (); | |
46101 | m68k_write_memory_8(srca,val); | |
46102 | }}}return 18; | |
46103 | } | |
46104 | unsigned long CPUFUNC(op_5df8_5)(uint32_t opcode) /* Scc */ | |
46105 | { | |
46106 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
46107 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
46108 | { int val = cctrue(13) ? 0xff : 0; | |
46109 | m68k_incpc(4); | |
46110 | fill_prefetch_0 (); | |
46111 | m68k_write_memory_8(srca,val); | |
46112 | }}}return 16; | |
46113 | } | |
46114 | unsigned long CPUFUNC(op_5df9_5)(uint32_t opcode) /* Scc */ | |
46115 | { | |
46116 | OpcodeFamily = 59; CurrentInstrCycles = 20; | |
46117 | {{ uint32_t srca = get_ilong_prefetch(2); | |
46118 | { int val = cctrue(13) ? 0xff : 0; | |
46119 | m68k_incpc(6); | |
46120 | fill_prefetch_0 (); | |
46121 | m68k_write_memory_8(srca,val); | |
46122 | }}}return 20; | |
46123 | } | |
46124 | unsigned long CPUFUNC(op_5ec0_5)(uint32_t opcode) /* Scc */ | |
46125 | { | |
46126 | uint32_t srcreg = (opcode & 7); | |
46127 | OpcodeFamily = 59; CurrentInstrCycles = 4; | |
46128 | {{{ int val = cctrue(14) ? 0xff : 0; | |
46129 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); | |
46130 | if (val) { m68k_incpc(2) ; return 4+2; } | |
46131 | }}}m68k_incpc(2); | |
46132 | fill_prefetch_2 (); | |
46133 | return 4; | |
46134 | } | |
46135 | unsigned long CPUFUNC(op_5ec8_5)(uint32_t opcode) /* DBcc */ | |
46136 | { | |
46137 | uint32_t srcreg = (opcode & 7); | |
46138 | OpcodeFamily = 58; CurrentInstrCycles = 12; | |
46139 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
46140 | { int16_t offs = get_iword_prefetch(2); | |
46141 | if (!cctrue(14)) { | |
46142 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); | |
46143 | if (src) { | |
46144 | if (offs & 1) { | |
46145 | last_addr_for_exception_3 = m68k_getpc() + 2 + 2; | |
46146 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)offs + 2; | |
46147 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2574; | |
46148 | } | |
46149 | m68k_incpc((int32_t)offs + 2); | |
46150 | fill_prefetch_0 (); | |
46151 | return 10; | |
46152 | } else { | |
46153 | m68k_incpc(4); | |
46154 | fill_prefetch_0 (); | |
46155 | return 14; | |
46156 | } | |
46157 | } | |
46158 | }}}m68k_incpc(4); | |
46159 | fill_prefetch_0 (); | |
46160 | endlabel2574: ; | |
46161 | return 12; | |
46162 | } | |
46163 | unsigned long CPUFUNC(op_5ed0_5)(uint32_t opcode) /* Scc */ | |
46164 | { | |
46165 | uint32_t srcreg = (opcode & 7); | |
46166 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
46167 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
46168 | { int val = cctrue(14) ? 0xff : 0; | |
46169 | m68k_incpc(2); | |
46170 | fill_prefetch_2 (); | |
46171 | m68k_write_memory_8(srca,val); | |
46172 | }}}return 12; | |
46173 | } | |
46174 | unsigned long CPUFUNC(op_5ed8_5)(uint32_t opcode) /* Scc */ | |
46175 | { | |
46176 | uint32_t srcreg = (opcode & 7); | |
46177 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
46178 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
46179 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
46180 | { int val = cctrue(14) ? 0xff : 0; | |
46181 | m68k_incpc(2); | |
46182 | fill_prefetch_2 (); | |
46183 | m68k_write_memory_8(srca,val); | |
46184 | }}}return 12; | |
46185 | } | |
46186 | unsigned long CPUFUNC(op_5ee0_5)(uint32_t opcode) /* Scc */ | |
46187 | { | |
46188 | uint32_t srcreg = (opcode & 7); | |
46189 | OpcodeFamily = 59; CurrentInstrCycles = 14; | |
46190 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
46191 | m68k_areg (regs, srcreg) = srca; | |
46192 | { int val = cctrue(14) ? 0xff : 0; | |
46193 | m68k_incpc(2); | |
46194 | fill_prefetch_2 (); | |
46195 | m68k_write_memory_8(srca,val); | |
46196 | }}}return 14; | |
46197 | } | |
46198 | unsigned long CPUFUNC(op_5ee8_5)(uint32_t opcode) /* Scc */ | |
46199 | { | |
46200 | uint32_t srcreg = (opcode & 7); | |
46201 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
46202 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
46203 | { int val = cctrue(14) ? 0xff : 0; | |
46204 | m68k_incpc(4); | |
46205 | fill_prefetch_0 (); | |
46206 | m68k_write_memory_8(srca,val); | |
46207 | }}}return 16; | |
46208 | } | |
46209 | unsigned long CPUFUNC(op_5ef0_5)(uint32_t opcode) /* Scc */ | |
46210 | { | |
46211 | uint32_t srcreg = (opcode & 7); | |
46212 | OpcodeFamily = 59; CurrentInstrCycles = 18; | |
46213 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
46214 | BusCyclePenalty += 2; | |
46215 | { int val = cctrue(14) ? 0xff : 0; | |
46216 | m68k_incpc(4); | |
46217 | fill_prefetch_0 (); | |
46218 | m68k_write_memory_8(srca,val); | |
46219 | }}}return 18; | |
46220 | } | |
46221 | unsigned long CPUFUNC(op_5ef8_5)(uint32_t opcode) /* Scc */ | |
46222 | { | |
46223 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
46224 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
46225 | { int val = cctrue(14) ? 0xff : 0; | |
46226 | m68k_incpc(4); | |
46227 | fill_prefetch_0 (); | |
46228 | m68k_write_memory_8(srca,val); | |
46229 | }}}return 16; | |
46230 | } | |
46231 | unsigned long CPUFUNC(op_5ef9_5)(uint32_t opcode) /* Scc */ | |
46232 | { | |
46233 | OpcodeFamily = 59; CurrentInstrCycles = 20; | |
46234 | {{ uint32_t srca = get_ilong_prefetch(2); | |
46235 | { int val = cctrue(14) ? 0xff : 0; | |
46236 | m68k_incpc(6); | |
46237 | fill_prefetch_0 (); | |
46238 | m68k_write_memory_8(srca,val); | |
46239 | }}}return 20; | |
46240 | } | |
46241 | unsigned long CPUFUNC(op_5fc0_5)(uint32_t opcode) /* Scc */ | |
46242 | { | |
46243 | uint32_t srcreg = (opcode & 7); | |
46244 | OpcodeFamily = 59; CurrentInstrCycles = 4; | |
46245 | {{{ int val = cctrue(15) ? 0xff : 0; | |
46246 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xff) | ((val) & 0xff); | |
46247 | if (val) { m68k_incpc(2) ; return 4+2; } | |
46248 | }}}m68k_incpc(2); | |
46249 | fill_prefetch_2 (); | |
46250 | return 4; | |
46251 | } | |
46252 | unsigned long CPUFUNC(op_5fc8_5)(uint32_t opcode) /* DBcc */ | |
46253 | { | |
46254 | uint32_t srcreg = (opcode & 7); | |
46255 | OpcodeFamily = 58; CurrentInstrCycles = 12; | |
46256 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
46257 | { int16_t offs = get_iword_prefetch(2); | |
46258 | if (!cctrue(15)) { | |
46259 | m68k_dreg(regs, srcreg) = (m68k_dreg(regs, srcreg) & ~0xffff) | (((src-1)) & 0xffff); | |
46260 | if (src) { | |
46261 | if (offs & 1) { | |
46262 | last_addr_for_exception_3 = m68k_getpc() + 2 + 2; | |
46263 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)offs + 2; | |
46264 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2583; | |
46265 | } | |
46266 | m68k_incpc((int32_t)offs + 2); | |
46267 | fill_prefetch_0 (); | |
46268 | return 10; | |
46269 | } else { | |
46270 | m68k_incpc(4); | |
46271 | fill_prefetch_0 (); | |
46272 | return 14; | |
46273 | } | |
46274 | } | |
46275 | }}}m68k_incpc(4); | |
46276 | fill_prefetch_0 (); | |
46277 | endlabel2583: ; | |
46278 | return 12; | |
46279 | } | |
46280 | unsigned long CPUFUNC(op_5fd0_5)(uint32_t opcode) /* Scc */ | |
46281 | { | |
46282 | uint32_t srcreg = (opcode & 7); | |
46283 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
46284 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
46285 | { int val = cctrue(15) ? 0xff : 0; | |
46286 | m68k_incpc(2); | |
46287 | fill_prefetch_2 (); | |
46288 | m68k_write_memory_8(srca,val); | |
46289 | }}}return 12; | |
46290 | } | |
46291 | unsigned long CPUFUNC(op_5fd8_5)(uint32_t opcode) /* Scc */ | |
46292 | { | |
46293 | uint32_t srcreg = (opcode & 7); | |
46294 | OpcodeFamily = 59; CurrentInstrCycles = 12; | |
46295 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
46296 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
46297 | { int val = cctrue(15) ? 0xff : 0; | |
46298 | m68k_incpc(2); | |
46299 | fill_prefetch_2 (); | |
46300 | m68k_write_memory_8(srca,val); | |
46301 | }}}return 12; | |
46302 | } | |
46303 | unsigned long CPUFUNC(op_5fe0_5)(uint32_t opcode) /* Scc */ | |
46304 | { | |
46305 | uint32_t srcreg = (opcode & 7); | |
46306 | OpcodeFamily = 59; CurrentInstrCycles = 14; | |
46307 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
46308 | m68k_areg (regs, srcreg) = srca; | |
46309 | { int val = cctrue(15) ? 0xff : 0; | |
46310 | m68k_incpc(2); | |
46311 | fill_prefetch_2 (); | |
46312 | m68k_write_memory_8(srca,val); | |
46313 | }}}return 14; | |
46314 | } | |
46315 | #endif | |
46316 | ||
46317 | #ifdef PART_6 | |
46318 | unsigned long CPUFUNC(op_5fe8_5)(uint32_t opcode) /* Scc */ | |
46319 | { | |
46320 | uint32_t srcreg = (opcode & 7); | |
46321 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
46322 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
46323 | { int val = cctrue(15) ? 0xff : 0; | |
46324 | m68k_incpc(4); | |
46325 | fill_prefetch_0 (); | |
46326 | m68k_write_memory_8(srca,val); | |
46327 | }}}return 16; | |
46328 | } | |
46329 | unsigned long CPUFUNC(op_5ff0_5)(uint32_t opcode) /* Scc */ | |
46330 | { | |
46331 | uint32_t srcreg = (opcode & 7); | |
46332 | OpcodeFamily = 59; CurrentInstrCycles = 18; | |
46333 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
46334 | BusCyclePenalty += 2; | |
46335 | { int val = cctrue(15) ? 0xff : 0; | |
46336 | m68k_incpc(4); | |
46337 | fill_prefetch_0 (); | |
46338 | m68k_write_memory_8(srca,val); | |
46339 | }}}return 18; | |
46340 | } | |
46341 | unsigned long CPUFUNC(op_5ff8_5)(uint32_t opcode) /* Scc */ | |
46342 | { | |
46343 | OpcodeFamily = 59; CurrentInstrCycles = 16; | |
46344 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
46345 | { int val = cctrue(15) ? 0xff : 0; | |
46346 | m68k_incpc(4); | |
46347 | fill_prefetch_0 (); | |
46348 | m68k_write_memory_8(srca,val); | |
46349 | }}}return 16; | |
46350 | } | |
46351 | unsigned long CPUFUNC(op_5ff9_5)(uint32_t opcode) /* Scc */ | |
46352 | { | |
46353 | OpcodeFamily = 59; CurrentInstrCycles = 20; | |
46354 | {{ uint32_t srca = get_ilong_prefetch(2); | |
46355 | { int val = cctrue(15) ? 0xff : 0; | |
46356 | m68k_incpc(6); | |
46357 | fill_prefetch_0 (); | |
46358 | m68k_write_memory_8(srca,val); | |
46359 | }}}return 20; | |
46360 | } | |
46361 | unsigned long CPUFUNC(op_6000_5)(uint32_t opcode) /* Bcc */ | |
46362 | { | |
46363 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
46364 | {{ int16_t src = get_iword_prefetch(2); | |
46365 | if (!cctrue(0)) goto didnt_jump; | |
46366 | if (src & 1) { | |
46367 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
46368 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; | |
46369 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2591; | |
46370 | } | |
46371 | m68k_incpc ((int32_t)src + 2); | |
46372 | fill_prefetch_0 (); | |
46373 | return 10; | |
46374 | didnt_jump:; | |
46375 | }}m68k_incpc(4); | |
46376 | fill_prefetch_0 (); | |
46377 | endlabel2591: ; | |
46378 | return 12; | |
46379 | } | |
46380 | unsigned long CPUFUNC(op_6001_5)(uint32_t opcode) /* Bcc */ | |
46381 | { | |
46382 | uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); | |
46383 | OpcodeFamily = 55; CurrentInstrCycles = 8; | |
46384 | {{ uint32_t src = srcreg; | |
46385 | if (!cctrue(0)) goto didnt_jump; | |
46386 | if (src & 1) { | |
46387 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
46388 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; | |
46389 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2592; | |
46390 | } | |
46391 | m68k_incpc ((int32_t)src + 2); | |
46392 | fill_prefetch_0 (); | |
46393 | return 10; | |
46394 | didnt_jump:; | |
46395 | }}m68k_incpc(2); | |
46396 | fill_prefetch_2 (); | |
46397 | endlabel2592: ; | |
46398 | return 8; | |
46399 | } | |
46400 | unsigned long CPUFUNC(op_60ff_5)(uint32_t opcode) /* Bcc */ | |
46401 | { | |
46402 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
46403 | { m68k_incpc(2); | |
46404 | if (!cctrue(0)) goto endlabel2593; | |
46405 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
46406 | last_fault_for_exception_3 = m68k_getpc() + 1; | |
46407 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2593; | |
46408 | { int32_t src = get_ilong_prefetch(2); | |
46409 | if (!cctrue(0)) goto didnt_jump; | |
46410 | if (src & 1) { | |
46411 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
46412 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; | |
46413 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2593; | |
46414 | } | |
46415 | m68k_incpc ((int32_t)src + 2); | |
46416 | fill_prefetch_0 (); | |
46417 | return 10; | |
46418 | didnt_jump:; | |
46419 | }}m68k_incpc(6); | |
46420 | fill_prefetch_0 (); | |
46421 | endlabel2593: ; | |
46422 | return 12; | |
46423 | } | |
46424 | unsigned long CPUFUNC(op_6100_5)(uint32_t opcode) /* BSR */ | |
46425 | { | |
46426 | OpcodeFamily = 54; CurrentInstrCycles = 18; | |
46427 | {{ int16_t src = get_iword_prefetch(2); | |
46428 | int32_t s = (int32_t)src + 2; | |
46429 | if (src & 1) { | |
46430 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
46431 | last_fault_for_exception_3 = m68k_getpc() + s; | |
46432 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2594; | |
46433 | } | |
46434 | m68k_do_bsr(m68k_getpc() + 4, s); | |
46435 | fill_prefetch_0 (); | |
46436 | }}endlabel2594: ; | |
46437 | return 18; | |
46438 | } | |
46439 | unsigned long CPUFUNC(op_6101_5)(uint32_t opcode) /* BSR */ | |
46440 | { | |
46441 | uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); | |
46442 | OpcodeFamily = 54; CurrentInstrCycles = 18; | |
46443 | {{ uint32_t src = srcreg; | |
46444 | int32_t s = (int32_t)src + 2; | |
46445 | if (src & 1) { | |
46446 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
46447 | last_fault_for_exception_3 = m68k_getpc() + s; | |
46448 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2595; | |
46449 | } | |
46450 | m68k_do_bsr(m68k_getpc() + 2, s); | |
46451 | fill_prefetch_0 (); | |
46452 | }}endlabel2595: ; | |
46453 | return 18; | |
46454 | } | |
46455 | unsigned long CPUFUNC(op_61ff_5)(uint32_t opcode) /* BSR */ | |
46456 | { | |
46457 | OpcodeFamily = 54; CurrentInstrCycles = 18; | |
46458 | {{ int32_t src = get_ilong_prefetch(2); | |
46459 | int32_t s = (int32_t)src + 2; | |
46460 | if (src & 1) { | |
46461 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
46462 | last_fault_for_exception_3 = m68k_getpc() + s; | |
46463 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2596; | |
46464 | } | |
46465 | m68k_do_bsr(m68k_getpc() + 6, s); | |
46466 | fill_prefetch_0 (); | |
46467 | }}endlabel2596: ; | |
46468 | return 18; | |
46469 | } | |
46470 | unsigned long CPUFUNC(op_6200_5)(uint32_t opcode) /* Bcc */ | |
46471 | { | |
46472 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
46473 | {{ int16_t src = get_iword_prefetch(2); | |
46474 | if (!cctrue(2)) goto didnt_jump; | |
46475 | if (src & 1) { | |
46476 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
46477 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; | |
46478 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2597; | |
46479 | } | |
46480 | m68k_incpc ((int32_t)src + 2); | |
46481 | fill_prefetch_0 (); | |
46482 | return 10; | |
46483 | didnt_jump:; | |
46484 | }}m68k_incpc(4); | |
46485 | fill_prefetch_0 (); | |
46486 | endlabel2597: ; | |
46487 | return 12; | |
46488 | } | |
46489 | unsigned long CPUFUNC(op_6201_5)(uint32_t opcode) /* Bcc */ | |
46490 | { | |
46491 | uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); | |
46492 | OpcodeFamily = 55; CurrentInstrCycles = 8; | |
46493 | {{ uint32_t src = srcreg; | |
46494 | if (!cctrue(2)) goto didnt_jump; | |
46495 | if (src & 1) { | |
46496 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
46497 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; | |
46498 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2598; | |
46499 | } | |
46500 | m68k_incpc ((int32_t)src + 2); | |
46501 | fill_prefetch_0 (); | |
46502 | return 10; | |
46503 | didnt_jump:; | |
46504 | }}m68k_incpc(2); | |
46505 | fill_prefetch_2 (); | |
46506 | endlabel2598: ; | |
46507 | return 8; | |
46508 | } | |
46509 | unsigned long CPUFUNC(op_62ff_5)(uint32_t opcode) /* Bcc */ | |
46510 | { | |
46511 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
46512 | { m68k_incpc(2); | |
46513 | if (!cctrue(2)) goto endlabel2599; | |
46514 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
46515 | last_fault_for_exception_3 = m68k_getpc() + 1; | |
46516 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2599; | |
46517 | { int32_t src = get_ilong_prefetch(2); | |
46518 | if (!cctrue(2)) goto didnt_jump; | |
46519 | if (src & 1) { | |
46520 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
46521 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; | |
46522 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2599; | |
46523 | } | |
46524 | m68k_incpc ((int32_t)src + 2); | |
46525 | fill_prefetch_0 (); | |
46526 | return 10; | |
46527 | didnt_jump:; | |
46528 | }}m68k_incpc(6); | |
46529 | fill_prefetch_0 (); | |
46530 | endlabel2599: ; | |
46531 | return 12; | |
46532 | } | |
46533 | unsigned long CPUFUNC(op_6300_5)(uint32_t opcode) /* Bcc */ | |
46534 | { | |
46535 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
46536 | {{ int16_t src = get_iword_prefetch(2); | |
46537 | if (!cctrue(3)) goto didnt_jump; | |
46538 | if (src & 1) { | |
46539 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
46540 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; | |
46541 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2600; | |
46542 | } | |
46543 | m68k_incpc ((int32_t)src + 2); | |
46544 | fill_prefetch_0 (); | |
46545 | return 10; | |
46546 | didnt_jump:; | |
46547 | }}m68k_incpc(4); | |
46548 | fill_prefetch_0 (); | |
46549 | endlabel2600: ; | |
46550 | return 12; | |
46551 | } | |
46552 | unsigned long CPUFUNC(op_6301_5)(uint32_t opcode) /* Bcc */ | |
46553 | { | |
46554 | uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); | |
46555 | OpcodeFamily = 55; CurrentInstrCycles = 8; | |
46556 | {{ uint32_t src = srcreg; | |
46557 | if (!cctrue(3)) goto didnt_jump; | |
46558 | if (src & 1) { | |
46559 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
46560 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; | |
46561 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2601; | |
46562 | } | |
46563 | m68k_incpc ((int32_t)src + 2); | |
46564 | fill_prefetch_0 (); | |
46565 | return 10; | |
46566 | didnt_jump:; | |
46567 | }}m68k_incpc(2); | |
46568 | fill_prefetch_2 (); | |
46569 | endlabel2601: ; | |
46570 | return 8; | |
46571 | } | |
46572 | unsigned long CPUFUNC(op_63ff_5)(uint32_t opcode) /* Bcc */ | |
46573 | { | |
46574 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
46575 | { m68k_incpc(2); | |
46576 | if (!cctrue(3)) goto endlabel2602; | |
46577 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
46578 | last_fault_for_exception_3 = m68k_getpc() + 1; | |
46579 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2602; | |
46580 | { int32_t src = get_ilong_prefetch(2); | |
46581 | if (!cctrue(3)) goto didnt_jump; | |
46582 | if (src & 1) { | |
46583 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
46584 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; | |
46585 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2602; | |
46586 | } | |
46587 | m68k_incpc ((int32_t)src + 2); | |
46588 | fill_prefetch_0 (); | |
46589 | return 10; | |
46590 | didnt_jump:; | |
46591 | }}m68k_incpc(6); | |
46592 | fill_prefetch_0 (); | |
46593 | endlabel2602: ; | |
46594 | return 12; | |
46595 | } | |
46596 | unsigned long CPUFUNC(op_6400_5)(uint32_t opcode) /* Bcc */ | |
46597 | { | |
46598 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
46599 | {{ int16_t src = get_iword_prefetch(2); | |
46600 | if (!cctrue(4)) goto didnt_jump; | |
46601 | if (src & 1) { | |
46602 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
46603 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; | |
46604 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2603; | |
46605 | } | |
46606 | m68k_incpc ((int32_t)src + 2); | |
46607 | fill_prefetch_0 (); | |
46608 | return 10; | |
46609 | didnt_jump:; | |
46610 | }}m68k_incpc(4); | |
46611 | fill_prefetch_0 (); | |
46612 | endlabel2603: ; | |
46613 | return 12; | |
46614 | } | |
46615 | unsigned long CPUFUNC(op_6401_5)(uint32_t opcode) /* Bcc */ | |
46616 | { | |
46617 | uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); | |
46618 | OpcodeFamily = 55; CurrentInstrCycles = 8; | |
46619 | {{ uint32_t src = srcreg; | |
46620 | if (!cctrue(4)) goto didnt_jump; | |
46621 | if (src & 1) { | |
46622 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
46623 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; | |
46624 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2604; | |
46625 | } | |
46626 | m68k_incpc ((int32_t)src + 2); | |
46627 | fill_prefetch_0 (); | |
46628 | return 10; | |
46629 | didnt_jump:; | |
46630 | }}m68k_incpc(2); | |
46631 | fill_prefetch_2 (); | |
46632 | endlabel2604: ; | |
46633 | return 8; | |
46634 | } | |
46635 | unsigned long CPUFUNC(op_64ff_5)(uint32_t opcode) /* Bcc */ | |
46636 | { | |
46637 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
46638 | { m68k_incpc(2); | |
46639 | if (!cctrue(4)) goto endlabel2605; | |
46640 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
46641 | last_fault_for_exception_3 = m68k_getpc() + 1; | |
46642 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2605; | |
46643 | { int32_t src = get_ilong_prefetch(2); | |
46644 | if (!cctrue(4)) goto didnt_jump; | |
46645 | if (src & 1) { | |
46646 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
46647 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; | |
46648 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2605; | |
46649 | } | |
46650 | m68k_incpc ((int32_t)src + 2); | |
46651 | fill_prefetch_0 (); | |
46652 | return 10; | |
46653 | didnt_jump:; | |
46654 | }}m68k_incpc(6); | |
46655 | fill_prefetch_0 (); | |
46656 | endlabel2605: ; | |
46657 | return 12; | |
46658 | } | |
46659 | unsigned long CPUFUNC(op_6500_5)(uint32_t opcode) /* Bcc */ | |
46660 | { | |
46661 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
46662 | {{ int16_t src = get_iword_prefetch(2); | |
46663 | if (!cctrue(5)) goto didnt_jump; | |
46664 | if (src & 1) { | |
46665 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
46666 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; | |
46667 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2606; | |
46668 | } | |
46669 | m68k_incpc ((int32_t)src + 2); | |
46670 | fill_prefetch_0 (); | |
46671 | return 10; | |
46672 | didnt_jump:; | |
46673 | }}m68k_incpc(4); | |
46674 | fill_prefetch_0 (); | |
46675 | endlabel2606: ; | |
46676 | return 12; | |
46677 | } | |
46678 | unsigned long CPUFUNC(op_6501_5)(uint32_t opcode) /* Bcc */ | |
46679 | { | |
46680 | uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); | |
46681 | OpcodeFamily = 55; CurrentInstrCycles = 8; | |
46682 | {{ uint32_t src = srcreg; | |
46683 | if (!cctrue(5)) goto didnt_jump; | |
46684 | if (src & 1) { | |
46685 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
46686 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; | |
46687 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2607; | |
46688 | } | |
46689 | m68k_incpc ((int32_t)src + 2); | |
46690 | fill_prefetch_0 (); | |
46691 | return 10; | |
46692 | didnt_jump:; | |
46693 | }}m68k_incpc(2); | |
46694 | fill_prefetch_2 (); | |
46695 | endlabel2607: ; | |
46696 | return 8; | |
46697 | } | |
46698 | unsigned long CPUFUNC(op_65ff_5)(uint32_t opcode) /* Bcc */ | |
46699 | { | |
46700 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
46701 | { m68k_incpc(2); | |
46702 | if (!cctrue(5)) goto endlabel2608; | |
46703 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
46704 | last_fault_for_exception_3 = m68k_getpc() + 1; | |
46705 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2608; | |
46706 | { int32_t src = get_ilong_prefetch(2); | |
46707 | if (!cctrue(5)) goto didnt_jump; | |
46708 | if (src & 1) { | |
46709 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
46710 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; | |
46711 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2608; | |
46712 | } | |
46713 | m68k_incpc ((int32_t)src + 2); | |
46714 | fill_prefetch_0 (); | |
46715 | return 10; | |
46716 | didnt_jump:; | |
46717 | }}m68k_incpc(6); | |
46718 | fill_prefetch_0 (); | |
46719 | endlabel2608: ; | |
46720 | return 12; | |
46721 | } | |
46722 | unsigned long CPUFUNC(op_6600_5)(uint32_t opcode) /* Bcc */ | |
46723 | { | |
46724 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
46725 | {{ int16_t src = get_iword_prefetch(2); | |
46726 | if (!cctrue(6)) goto didnt_jump; | |
46727 | if (src & 1) { | |
46728 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
46729 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; | |
46730 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2609; | |
46731 | } | |
46732 | m68k_incpc ((int32_t)src + 2); | |
46733 | fill_prefetch_0 (); | |
46734 | return 10; | |
46735 | didnt_jump:; | |
46736 | }}m68k_incpc(4); | |
46737 | fill_prefetch_0 (); | |
46738 | endlabel2609: ; | |
46739 | return 12; | |
46740 | } | |
46741 | unsigned long CPUFUNC(op_6601_5)(uint32_t opcode) /* Bcc */ | |
46742 | { | |
46743 | uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); | |
46744 | OpcodeFamily = 55; CurrentInstrCycles = 8; | |
46745 | {{ uint32_t src = srcreg; | |
46746 | if (!cctrue(6)) goto didnt_jump; | |
46747 | if (src & 1) { | |
46748 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
46749 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; | |
46750 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2610; | |
46751 | } | |
46752 | m68k_incpc ((int32_t)src + 2); | |
46753 | fill_prefetch_0 (); | |
46754 | return 10; | |
46755 | didnt_jump:; | |
46756 | }}m68k_incpc(2); | |
46757 | fill_prefetch_2 (); | |
46758 | endlabel2610: ; | |
46759 | return 8; | |
46760 | } | |
46761 | unsigned long CPUFUNC(op_66ff_5)(uint32_t opcode) /* Bcc */ | |
46762 | { | |
46763 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
46764 | { m68k_incpc(2); | |
46765 | if (!cctrue(6)) goto endlabel2611; | |
46766 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
46767 | last_fault_for_exception_3 = m68k_getpc() + 1; | |
46768 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2611; | |
46769 | { int32_t src = get_ilong_prefetch(2); | |
46770 | if (!cctrue(6)) goto didnt_jump; | |
46771 | if (src & 1) { | |
46772 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
46773 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; | |
46774 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2611; | |
46775 | } | |
46776 | m68k_incpc ((int32_t)src + 2); | |
46777 | fill_prefetch_0 (); | |
46778 | return 10; | |
46779 | didnt_jump:; | |
46780 | }}m68k_incpc(6); | |
46781 | fill_prefetch_0 (); | |
46782 | endlabel2611: ; | |
46783 | return 12; | |
46784 | } | |
46785 | unsigned long CPUFUNC(op_6700_5)(uint32_t opcode) /* Bcc */ | |
46786 | { | |
46787 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
46788 | {{ int16_t src = get_iword_prefetch(2); | |
46789 | if (!cctrue(7)) goto didnt_jump; | |
46790 | if (src & 1) { | |
46791 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
46792 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; | |
46793 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2612; | |
46794 | } | |
46795 | m68k_incpc ((int32_t)src + 2); | |
46796 | fill_prefetch_0 (); | |
46797 | return 10; | |
46798 | didnt_jump:; | |
46799 | }}m68k_incpc(4); | |
46800 | fill_prefetch_0 (); | |
46801 | endlabel2612: ; | |
46802 | return 12; | |
46803 | } | |
46804 | unsigned long CPUFUNC(op_6701_5)(uint32_t opcode) /* Bcc */ | |
46805 | { | |
46806 | uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); | |
46807 | OpcodeFamily = 55; CurrentInstrCycles = 8; | |
46808 | {{ uint32_t src = srcreg; | |
46809 | if (!cctrue(7)) goto didnt_jump; | |
46810 | if (src & 1) { | |
46811 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
46812 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; | |
46813 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2613; | |
46814 | } | |
46815 | m68k_incpc ((int32_t)src + 2); | |
46816 | fill_prefetch_0 (); | |
46817 | return 10; | |
46818 | didnt_jump:; | |
46819 | }}m68k_incpc(2); | |
46820 | fill_prefetch_2 (); | |
46821 | endlabel2613: ; | |
46822 | return 8; | |
46823 | } | |
46824 | unsigned long CPUFUNC(op_67ff_5)(uint32_t opcode) /* Bcc */ | |
46825 | { | |
46826 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
46827 | { m68k_incpc(2); | |
46828 | if (!cctrue(7)) goto endlabel2614; | |
46829 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
46830 | last_fault_for_exception_3 = m68k_getpc() + 1; | |
46831 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2614; | |
46832 | { int32_t src = get_ilong_prefetch(2); | |
46833 | if (!cctrue(7)) goto didnt_jump; | |
46834 | if (src & 1) { | |
46835 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
46836 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; | |
46837 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2614; | |
46838 | } | |
46839 | m68k_incpc ((int32_t)src + 2); | |
46840 | fill_prefetch_0 (); | |
46841 | return 10; | |
46842 | didnt_jump:; | |
46843 | }}m68k_incpc(6); | |
46844 | fill_prefetch_0 (); | |
46845 | endlabel2614: ; | |
46846 | return 12; | |
46847 | } | |
46848 | unsigned long CPUFUNC(op_6800_5)(uint32_t opcode) /* Bcc */ | |
46849 | { | |
46850 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
46851 | {{ int16_t src = get_iword_prefetch(2); | |
46852 | if (!cctrue(8)) goto didnt_jump; | |
46853 | if (src & 1) { | |
46854 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
46855 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; | |
46856 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2615; | |
46857 | } | |
46858 | m68k_incpc ((int32_t)src + 2); | |
46859 | fill_prefetch_0 (); | |
46860 | return 10; | |
46861 | didnt_jump:; | |
46862 | }}m68k_incpc(4); | |
46863 | fill_prefetch_0 (); | |
46864 | endlabel2615: ; | |
46865 | return 12; | |
46866 | } | |
46867 | unsigned long CPUFUNC(op_6801_5)(uint32_t opcode) /* Bcc */ | |
46868 | { | |
46869 | uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); | |
46870 | OpcodeFamily = 55; CurrentInstrCycles = 8; | |
46871 | {{ uint32_t src = srcreg; | |
46872 | if (!cctrue(8)) goto didnt_jump; | |
46873 | if (src & 1) { | |
46874 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
46875 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; | |
46876 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2616; | |
46877 | } | |
46878 | m68k_incpc ((int32_t)src + 2); | |
46879 | fill_prefetch_0 (); | |
46880 | return 10; | |
46881 | didnt_jump:; | |
46882 | }}m68k_incpc(2); | |
46883 | fill_prefetch_2 (); | |
46884 | endlabel2616: ; | |
46885 | return 8; | |
46886 | } | |
46887 | unsigned long CPUFUNC(op_68ff_5)(uint32_t opcode) /* Bcc */ | |
46888 | { | |
46889 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
46890 | { m68k_incpc(2); | |
46891 | if (!cctrue(8)) goto endlabel2617; | |
46892 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
46893 | last_fault_for_exception_3 = m68k_getpc() + 1; | |
46894 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2617; | |
46895 | { int32_t src = get_ilong_prefetch(2); | |
46896 | if (!cctrue(8)) goto didnt_jump; | |
46897 | if (src & 1) { | |
46898 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
46899 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; | |
46900 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2617; | |
46901 | } | |
46902 | m68k_incpc ((int32_t)src + 2); | |
46903 | fill_prefetch_0 (); | |
46904 | return 10; | |
46905 | didnt_jump:; | |
46906 | }}m68k_incpc(6); | |
46907 | fill_prefetch_0 (); | |
46908 | endlabel2617: ; | |
46909 | return 12; | |
46910 | } | |
46911 | unsigned long CPUFUNC(op_6900_5)(uint32_t opcode) /* Bcc */ | |
46912 | { | |
46913 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
46914 | {{ int16_t src = get_iword_prefetch(2); | |
46915 | if (!cctrue(9)) goto didnt_jump; | |
46916 | if (src & 1) { | |
46917 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
46918 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; | |
46919 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2618; | |
46920 | } | |
46921 | m68k_incpc ((int32_t)src + 2); | |
46922 | fill_prefetch_0 (); | |
46923 | return 10; | |
46924 | didnt_jump:; | |
46925 | }}m68k_incpc(4); | |
46926 | fill_prefetch_0 (); | |
46927 | endlabel2618: ; | |
46928 | return 12; | |
46929 | } | |
46930 | unsigned long CPUFUNC(op_6901_5)(uint32_t opcode) /* Bcc */ | |
46931 | { | |
46932 | uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); | |
46933 | OpcodeFamily = 55; CurrentInstrCycles = 8; | |
46934 | {{ uint32_t src = srcreg; | |
46935 | if (!cctrue(9)) goto didnt_jump; | |
46936 | if (src & 1) { | |
46937 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
46938 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; | |
46939 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2619; | |
46940 | } | |
46941 | m68k_incpc ((int32_t)src + 2); | |
46942 | fill_prefetch_0 (); | |
46943 | return 10; | |
46944 | didnt_jump:; | |
46945 | }}m68k_incpc(2); | |
46946 | fill_prefetch_2 (); | |
46947 | endlabel2619: ; | |
46948 | return 8; | |
46949 | } | |
46950 | unsigned long CPUFUNC(op_69ff_5)(uint32_t opcode) /* Bcc */ | |
46951 | { | |
46952 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
46953 | { m68k_incpc(2); | |
46954 | if (!cctrue(9)) goto endlabel2620; | |
46955 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
46956 | last_fault_for_exception_3 = m68k_getpc() + 1; | |
46957 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2620; | |
46958 | { int32_t src = get_ilong_prefetch(2); | |
46959 | if (!cctrue(9)) goto didnt_jump; | |
46960 | if (src & 1) { | |
46961 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
46962 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; | |
46963 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2620; | |
46964 | } | |
46965 | m68k_incpc ((int32_t)src + 2); | |
46966 | fill_prefetch_0 (); | |
46967 | return 10; | |
46968 | didnt_jump:; | |
46969 | }}m68k_incpc(6); | |
46970 | fill_prefetch_0 (); | |
46971 | endlabel2620: ; | |
46972 | return 12; | |
46973 | } | |
46974 | unsigned long CPUFUNC(op_6a00_5)(uint32_t opcode) /* Bcc */ | |
46975 | { | |
46976 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
46977 | {{ int16_t src = get_iword_prefetch(2); | |
46978 | if (!cctrue(10)) goto didnt_jump; | |
46979 | if (src & 1) { | |
46980 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
46981 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; | |
46982 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2621; | |
46983 | } | |
46984 | m68k_incpc ((int32_t)src + 2); | |
46985 | fill_prefetch_0 (); | |
46986 | return 10; | |
46987 | didnt_jump:; | |
46988 | }}m68k_incpc(4); | |
46989 | fill_prefetch_0 (); | |
46990 | endlabel2621: ; | |
46991 | return 12; | |
46992 | } | |
46993 | unsigned long CPUFUNC(op_6a01_5)(uint32_t opcode) /* Bcc */ | |
46994 | { | |
46995 | uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); | |
46996 | OpcodeFamily = 55; CurrentInstrCycles = 8; | |
46997 | {{ uint32_t src = srcreg; | |
46998 | if (!cctrue(10)) goto didnt_jump; | |
46999 | if (src & 1) { | |
47000 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
47001 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; | |
47002 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2622; | |
47003 | } | |
47004 | m68k_incpc ((int32_t)src + 2); | |
47005 | fill_prefetch_0 (); | |
47006 | return 10; | |
47007 | didnt_jump:; | |
47008 | }}m68k_incpc(2); | |
47009 | fill_prefetch_2 (); | |
47010 | endlabel2622: ; | |
47011 | return 8; | |
47012 | } | |
47013 | unsigned long CPUFUNC(op_6aff_5)(uint32_t opcode) /* Bcc */ | |
47014 | { | |
47015 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
47016 | { m68k_incpc(2); | |
47017 | if (!cctrue(10)) goto endlabel2623; | |
47018 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
47019 | last_fault_for_exception_3 = m68k_getpc() + 1; | |
47020 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2623; | |
47021 | { int32_t src = get_ilong_prefetch(2); | |
47022 | if (!cctrue(10)) goto didnt_jump; | |
47023 | if (src & 1) { | |
47024 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
47025 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; | |
47026 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2623; | |
47027 | } | |
47028 | m68k_incpc ((int32_t)src + 2); | |
47029 | fill_prefetch_0 (); | |
47030 | return 10; | |
47031 | didnt_jump:; | |
47032 | }}m68k_incpc(6); | |
47033 | fill_prefetch_0 (); | |
47034 | endlabel2623: ; | |
47035 | return 12; | |
47036 | } | |
47037 | unsigned long CPUFUNC(op_6b00_5)(uint32_t opcode) /* Bcc */ | |
47038 | { | |
47039 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
47040 | {{ int16_t src = get_iword_prefetch(2); | |
47041 | if (!cctrue(11)) goto didnt_jump; | |
47042 | if (src & 1) { | |
47043 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
47044 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; | |
47045 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2624; | |
47046 | } | |
47047 | m68k_incpc ((int32_t)src + 2); | |
47048 | fill_prefetch_0 (); | |
47049 | return 10; | |
47050 | didnt_jump:; | |
47051 | }}m68k_incpc(4); | |
47052 | fill_prefetch_0 (); | |
47053 | endlabel2624: ; | |
47054 | return 12; | |
47055 | } | |
47056 | unsigned long CPUFUNC(op_6b01_5)(uint32_t opcode) /* Bcc */ | |
47057 | { | |
47058 | uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); | |
47059 | OpcodeFamily = 55; CurrentInstrCycles = 8; | |
47060 | {{ uint32_t src = srcreg; | |
47061 | if (!cctrue(11)) goto didnt_jump; | |
47062 | if (src & 1) { | |
47063 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
47064 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; | |
47065 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2625; | |
47066 | } | |
47067 | m68k_incpc ((int32_t)src + 2); | |
47068 | fill_prefetch_0 (); | |
47069 | return 10; | |
47070 | didnt_jump:; | |
47071 | }}m68k_incpc(2); | |
47072 | fill_prefetch_2 (); | |
47073 | endlabel2625: ; | |
47074 | return 8; | |
47075 | } | |
47076 | unsigned long CPUFUNC(op_6bff_5)(uint32_t opcode) /* Bcc */ | |
47077 | { | |
47078 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
47079 | { m68k_incpc(2); | |
47080 | if (!cctrue(11)) goto endlabel2626; | |
47081 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
47082 | last_fault_for_exception_3 = m68k_getpc() + 1; | |
47083 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2626; | |
47084 | { int32_t src = get_ilong_prefetch(2); | |
47085 | if (!cctrue(11)) goto didnt_jump; | |
47086 | if (src & 1) { | |
47087 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
47088 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; | |
47089 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2626; | |
47090 | } | |
47091 | m68k_incpc ((int32_t)src + 2); | |
47092 | fill_prefetch_0 (); | |
47093 | return 10; | |
47094 | didnt_jump:; | |
47095 | }}m68k_incpc(6); | |
47096 | fill_prefetch_0 (); | |
47097 | endlabel2626: ; | |
47098 | return 12; | |
47099 | } | |
47100 | unsigned long CPUFUNC(op_6c00_5)(uint32_t opcode) /* Bcc */ | |
47101 | { | |
47102 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
47103 | {{ int16_t src = get_iword_prefetch(2); | |
47104 | if (!cctrue(12)) goto didnt_jump; | |
47105 | if (src & 1) { | |
47106 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
47107 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; | |
47108 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2627; | |
47109 | } | |
47110 | m68k_incpc ((int32_t)src + 2); | |
47111 | fill_prefetch_0 (); | |
47112 | return 10; | |
47113 | didnt_jump:; | |
47114 | }}m68k_incpc(4); | |
47115 | fill_prefetch_0 (); | |
47116 | endlabel2627: ; | |
47117 | return 12; | |
47118 | } | |
47119 | unsigned long CPUFUNC(op_6c01_5)(uint32_t opcode) /* Bcc */ | |
47120 | { | |
47121 | uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); | |
47122 | OpcodeFamily = 55; CurrentInstrCycles = 8; | |
47123 | {{ uint32_t src = srcreg; | |
47124 | if (!cctrue(12)) goto didnt_jump; | |
47125 | if (src & 1) { | |
47126 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
47127 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; | |
47128 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2628; | |
47129 | } | |
47130 | m68k_incpc ((int32_t)src + 2); | |
47131 | fill_prefetch_0 (); | |
47132 | return 10; | |
47133 | didnt_jump:; | |
47134 | }}m68k_incpc(2); | |
47135 | fill_prefetch_2 (); | |
47136 | endlabel2628: ; | |
47137 | return 8; | |
47138 | } | |
47139 | unsigned long CPUFUNC(op_6cff_5)(uint32_t opcode) /* Bcc */ | |
47140 | { | |
47141 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
47142 | { m68k_incpc(2); | |
47143 | if (!cctrue(12)) goto endlabel2629; | |
47144 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
47145 | last_fault_for_exception_3 = m68k_getpc() + 1; | |
47146 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2629; | |
47147 | { int32_t src = get_ilong_prefetch(2); | |
47148 | if (!cctrue(12)) goto didnt_jump; | |
47149 | if (src & 1) { | |
47150 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
47151 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; | |
47152 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2629; | |
47153 | } | |
47154 | m68k_incpc ((int32_t)src + 2); | |
47155 | fill_prefetch_0 (); | |
47156 | return 10; | |
47157 | didnt_jump:; | |
47158 | }}m68k_incpc(6); | |
47159 | fill_prefetch_0 (); | |
47160 | endlabel2629: ; | |
47161 | return 12; | |
47162 | } | |
47163 | unsigned long CPUFUNC(op_6d00_5)(uint32_t opcode) /* Bcc */ | |
47164 | { | |
47165 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
47166 | {{ int16_t src = get_iword_prefetch(2); | |
47167 | if (!cctrue(13)) goto didnt_jump; | |
47168 | if (src & 1) { | |
47169 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
47170 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; | |
47171 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2630; | |
47172 | } | |
47173 | m68k_incpc ((int32_t)src + 2); | |
47174 | fill_prefetch_0 (); | |
47175 | return 10; | |
47176 | didnt_jump:; | |
47177 | }}m68k_incpc(4); | |
47178 | fill_prefetch_0 (); | |
47179 | endlabel2630: ; | |
47180 | return 12; | |
47181 | } | |
47182 | unsigned long CPUFUNC(op_6d01_5)(uint32_t opcode) /* Bcc */ | |
47183 | { | |
47184 | uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); | |
47185 | OpcodeFamily = 55; CurrentInstrCycles = 8; | |
47186 | {{ uint32_t src = srcreg; | |
47187 | if (!cctrue(13)) goto didnt_jump; | |
47188 | if (src & 1) { | |
47189 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
47190 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; | |
47191 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2631; | |
47192 | } | |
47193 | m68k_incpc ((int32_t)src + 2); | |
47194 | fill_prefetch_0 (); | |
47195 | return 10; | |
47196 | didnt_jump:; | |
47197 | }}m68k_incpc(2); | |
47198 | fill_prefetch_2 (); | |
47199 | endlabel2631: ; | |
47200 | return 8; | |
47201 | } | |
47202 | unsigned long CPUFUNC(op_6dff_5)(uint32_t opcode) /* Bcc */ | |
47203 | { | |
47204 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
47205 | { m68k_incpc(2); | |
47206 | if (!cctrue(13)) goto endlabel2632; | |
47207 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
47208 | last_fault_for_exception_3 = m68k_getpc() + 1; | |
47209 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2632; | |
47210 | { int32_t src = get_ilong_prefetch(2); | |
47211 | if (!cctrue(13)) goto didnt_jump; | |
47212 | if (src & 1) { | |
47213 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
47214 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; | |
47215 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2632; | |
47216 | } | |
47217 | m68k_incpc ((int32_t)src + 2); | |
47218 | fill_prefetch_0 (); | |
47219 | return 10; | |
47220 | didnt_jump:; | |
47221 | }}m68k_incpc(6); | |
47222 | fill_prefetch_0 (); | |
47223 | endlabel2632: ; | |
47224 | return 12; | |
47225 | } | |
47226 | unsigned long CPUFUNC(op_6e00_5)(uint32_t opcode) /* Bcc */ | |
47227 | { | |
47228 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
47229 | {{ int16_t src = get_iword_prefetch(2); | |
47230 | if (!cctrue(14)) goto didnt_jump; | |
47231 | if (src & 1) { | |
47232 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
47233 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; | |
47234 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2633; | |
47235 | } | |
47236 | m68k_incpc ((int32_t)src + 2); | |
47237 | fill_prefetch_0 (); | |
47238 | return 10; | |
47239 | didnt_jump:; | |
47240 | }}m68k_incpc(4); | |
47241 | fill_prefetch_0 (); | |
47242 | endlabel2633: ; | |
47243 | return 12; | |
47244 | } | |
47245 | unsigned long CPUFUNC(op_6e01_5)(uint32_t opcode) /* Bcc */ | |
47246 | { | |
47247 | uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); | |
47248 | OpcodeFamily = 55; CurrentInstrCycles = 8; | |
47249 | {{ uint32_t src = srcreg; | |
47250 | if (!cctrue(14)) goto didnt_jump; | |
47251 | if (src & 1) { | |
47252 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
47253 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; | |
47254 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2634; | |
47255 | } | |
47256 | m68k_incpc ((int32_t)src + 2); | |
47257 | fill_prefetch_0 (); | |
47258 | return 10; | |
47259 | didnt_jump:; | |
47260 | }}m68k_incpc(2); | |
47261 | fill_prefetch_2 (); | |
47262 | endlabel2634: ; | |
47263 | return 8; | |
47264 | } | |
47265 | unsigned long CPUFUNC(op_6eff_5)(uint32_t opcode) /* Bcc */ | |
47266 | { | |
47267 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
47268 | { m68k_incpc(2); | |
47269 | if (!cctrue(14)) goto endlabel2635; | |
47270 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
47271 | last_fault_for_exception_3 = m68k_getpc() + 1; | |
47272 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2635; | |
47273 | { int32_t src = get_ilong_prefetch(2); | |
47274 | if (!cctrue(14)) goto didnt_jump; | |
47275 | if (src & 1) { | |
47276 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
47277 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; | |
47278 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2635; | |
47279 | } | |
47280 | m68k_incpc ((int32_t)src + 2); | |
47281 | fill_prefetch_0 (); | |
47282 | return 10; | |
47283 | didnt_jump:; | |
47284 | }}m68k_incpc(6); | |
47285 | fill_prefetch_0 (); | |
47286 | endlabel2635: ; | |
47287 | return 12; | |
47288 | } | |
47289 | unsigned long CPUFUNC(op_6f00_5)(uint32_t opcode) /* Bcc */ | |
47290 | { | |
47291 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
47292 | {{ int16_t src = get_iword_prefetch(2); | |
47293 | if (!cctrue(15)) goto didnt_jump; | |
47294 | if (src & 1) { | |
47295 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
47296 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; | |
47297 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2636; | |
47298 | } | |
47299 | m68k_incpc ((int32_t)src + 2); | |
47300 | fill_prefetch_0 (); | |
47301 | return 10; | |
47302 | didnt_jump:; | |
47303 | }}m68k_incpc(4); | |
47304 | fill_prefetch_0 (); | |
47305 | endlabel2636: ; | |
47306 | return 12; | |
47307 | } | |
47308 | unsigned long CPUFUNC(op_6f01_5)(uint32_t opcode) /* Bcc */ | |
47309 | { | |
47310 | uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); | |
47311 | OpcodeFamily = 55; CurrentInstrCycles = 8; | |
47312 | {{ uint32_t src = srcreg; | |
47313 | if (!cctrue(15)) goto didnt_jump; | |
47314 | if (src & 1) { | |
47315 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
47316 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; | |
47317 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2637; | |
47318 | } | |
47319 | m68k_incpc ((int32_t)src + 2); | |
47320 | fill_prefetch_0 (); | |
47321 | return 10; | |
47322 | didnt_jump:; | |
47323 | }}m68k_incpc(2); | |
47324 | fill_prefetch_2 (); | |
47325 | endlabel2637: ; | |
47326 | return 8; | |
47327 | } | |
47328 | unsigned long CPUFUNC(op_6fff_5)(uint32_t opcode) /* Bcc */ | |
47329 | { | |
47330 | OpcodeFamily = 55; CurrentInstrCycles = 12; | |
47331 | { m68k_incpc(2); | |
47332 | if (!cctrue(15)) goto endlabel2638; | |
47333 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
47334 | last_fault_for_exception_3 = m68k_getpc() + 1; | |
47335 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2638; | |
47336 | { int32_t src = get_ilong_prefetch(2); | |
47337 | if (!cctrue(15)) goto didnt_jump; | |
47338 | if (src & 1) { | |
47339 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
47340 | last_fault_for_exception_3 = m68k_getpc() + 2 + (int32_t)src; | |
47341 | last_op_for_exception_3 = opcode; Exception(3,0,M68000_EXC_SRC_CPU); goto endlabel2638; | |
47342 | } | |
47343 | m68k_incpc ((int32_t)src + 2); | |
47344 | fill_prefetch_0 (); | |
47345 | return 10; | |
47346 | didnt_jump:; | |
47347 | }}m68k_incpc(6); | |
47348 | fill_prefetch_0 (); | |
47349 | endlabel2638: ; | |
47350 | return 12; | |
47351 | } | |
47352 | unsigned long CPUFUNC(op_7000_5)(uint32_t opcode) /* MOVE */ | |
47353 | { | |
47354 | uint32_t srcreg = (int32_t)(int8_t)(opcode & 255); | |
47355 | uint32_t dstreg = (opcode >> 9) & 7; | |
47356 | OpcodeFamily = 30; CurrentInstrCycles = 4; | |
47357 | {{ uint32_t src = srcreg; | |
47358 | { CLEAR_CZNV; | |
47359 | SET_ZFLG (((int32_t)(src)) == 0); | |
47360 | SET_NFLG (((int32_t)(src)) < 0); | |
47361 | m68k_dreg(regs, dstreg) = (src); | |
47362 | }}}m68k_incpc(2); | |
47363 | fill_prefetch_2 (); | |
47364 | return 4; | |
47365 | } | |
47366 | unsigned long CPUFUNC(op_8000_5)(uint32_t opcode) /* OR */ | |
47367 | { | |
47368 | uint32_t srcreg = (opcode & 7); | |
47369 | uint32_t dstreg = (opcode >> 9) & 7; | |
47370 | OpcodeFamily = 1; CurrentInstrCycles = 4; | |
47371 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
47372 | { int8_t dst = m68k_dreg(regs, dstreg); | |
47373 | src |= dst; | |
47374 | CLEAR_CZNV; | |
47375 | SET_ZFLG (((int8_t)(src)) == 0); | |
47376 | SET_NFLG (((int8_t)(src)) < 0); | |
47377 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
47378 | }}}m68k_incpc(2); | |
47379 | fill_prefetch_2 (); | |
47380 | return 4; | |
47381 | } | |
47382 | unsigned long CPUFUNC(op_8010_5)(uint32_t opcode) /* OR */ | |
47383 | { | |
47384 | uint32_t srcreg = (opcode & 7); | |
47385 | uint32_t dstreg = (opcode >> 9) & 7; | |
47386 | OpcodeFamily = 1; CurrentInstrCycles = 8; | |
47387 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
47388 | { int8_t src = m68k_read_memory_8(srca); | |
47389 | { int8_t dst = m68k_dreg(regs, dstreg); | |
47390 | src |= dst; | |
47391 | CLEAR_CZNV; | |
47392 | SET_ZFLG (((int8_t)(src)) == 0); | |
47393 | SET_NFLG (((int8_t)(src)) < 0); | |
47394 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
47395 | }}}}m68k_incpc(2); | |
47396 | fill_prefetch_2 (); | |
47397 | return 8; | |
47398 | } | |
47399 | unsigned long CPUFUNC(op_8018_5)(uint32_t opcode) /* OR */ | |
47400 | { | |
47401 | uint32_t srcreg = (opcode & 7); | |
47402 | uint32_t dstreg = (opcode >> 9) & 7; | |
47403 | OpcodeFamily = 1; CurrentInstrCycles = 8; | |
47404 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
47405 | { int8_t src = m68k_read_memory_8(srca); | |
47406 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
47407 | { int8_t dst = m68k_dreg(regs, dstreg); | |
47408 | src |= dst; | |
47409 | CLEAR_CZNV; | |
47410 | SET_ZFLG (((int8_t)(src)) == 0); | |
47411 | SET_NFLG (((int8_t)(src)) < 0); | |
47412 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
47413 | }}}}m68k_incpc(2); | |
47414 | fill_prefetch_2 (); | |
47415 | return 8; | |
47416 | } | |
47417 | unsigned long CPUFUNC(op_8020_5)(uint32_t opcode) /* OR */ | |
47418 | { | |
47419 | uint32_t srcreg = (opcode & 7); | |
47420 | uint32_t dstreg = (opcode >> 9) & 7; | |
47421 | OpcodeFamily = 1; CurrentInstrCycles = 10; | |
47422 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
47423 | { int8_t src = m68k_read_memory_8(srca); | |
47424 | m68k_areg (regs, srcreg) = srca; | |
47425 | { int8_t dst = m68k_dreg(regs, dstreg); | |
47426 | src |= dst; | |
47427 | CLEAR_CZNV; | |
47428 | SET_ZFLG (((int8_t)(src)) == 0); | |
47429 | SET_NFLG (((int8_t)(src)) < 0); | |
47430 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
47431 | }}}}m68k_incpc(2); | |
47432 | fill_prefetch_2 (); | |
47433 | return 10; | |
47434 | } | |
47435 | unsigned long CPUFUNC(op_8028_5)(uint32_t opcode) /* OR */ | |
47436 | { | |
47437 | uint32_t srcreg = (opcode & 7); | |
47438 | uint32_t dstreg = (opcode >> 9) & 7; | |
47439 | OpcodeFamily = 1; CurrentInstrCycles = 12; | |
47440 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
47441 | { int8_t src = m68k_read_memory_8(srca); | |
47442 | { int8_t dst = m68k_dreg(regs, dstreg); | |
47443 | src |= dst; | |
47444 | CLEAR_CZNV; | |
47445 | SET_ZFLG (((int8_t)(src)) == 0); | |
47446 | SET_NFLG (((int8_t)(src)) < 0); | |
47447 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
47448 | }}}}m68k_incpc(4); | |
47449 | fill_prefetch_0 (); | |
47450 | return 12; | |
47451 | } | |
47452 | unsigned long CPUFUNC(op_8030_5)(uint32_t opcode) /* OR */ | |
47453 | { | |
47454 | uint32_t srcreg = (opcode & 7); | |
47455 | uint32_t dstreg = (opcode >> 9) & 7; | |
47456 | OpcodeFamily = 1; CurrentInstrCycles = 14; | |
47457 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
47458 | BusCyclePenalty += 2; | |
47459 | { int8_t src = m68k_read_memory_8(srca); | |
47460 | { int8_t dst = m68k_dreg(regs, dstreg); | |
47461 | src |= dst; | |
47462 | CLEAR_CZNV; | |
47463 | SET_ZFLG (((int8_t)(src)) == 0); | |
47464 | SET_NFLG (((int8_t)(src)) < 0); | |
47465 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
47466 | }}}}m68k_incpc(4); | |
47467 | fill_prefetch_0 (); | |
47468 | return 14; | |
47469 | } | |
47470 | unsigned long CPUFUNC(op_8038_5)(uint32_t opcode) /* OR */ | |
47471 | { | |
47472 | uint32_t dstreg = (opcode >> 9) & 7; | |
47473 | OpcodeFamily = 1; CurrentInstrCycles = 12; | |
47474 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
47475 | { int8_t src = m68k_read_memory_8(srca); | |
47476 | { int8_t dst = m68k_dreg(regs, dstreg); | |
47477 | src |= dst; | |
47478 | CLEAR_CZNV; | |
47479 | SET_ZFLG (((int8_t)(src)) == 0); | |
47480 | SET_NFLG (((int8_t)(src)) < 0); | |
47481 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
47482 | }}}}m68k_incpc(4); | |
47483 | fill_prefetch_0 (); | |
47484 | return 12; | |
47485 | } | |
47486 | unsigned long CPUFUNC(op_8039_5)(uint32_t opcode) /* OR */ | |
47487 | { | |
47488 | uint32_t dstreg = (opcode >> 9) & 7; | |
47489 | OpcodeFamily = 1; CurrentInstrCycles = 16; | |
47490 | {{ uint32_t srca = get_ilong_prefetch(2); | |
47491 | { int8_t src = m68k_read_memory_8(srca); | |
47492 | { int8_t dst = m68k_dreg(regs, dstreg); | |
47493 | src |= dst; | |
47494 | CLEAR_CZNV; | |
47495 | SET_ZFLG (((int8_t)(src)) == 0); | |
47496 | SET_NFLG (((int8_t)(src)) < 0); | |
47497 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
47498 | }}}}m68k_incpc(6); | |
47499 | fill_prefetch_0 (); | |
47500 | return 16; | |
47501 | } | |
47502 | unsigned long CPUFUNC(op_803a_5)(uint32_t opcode) /* OR */ | |
47503 | { | |
47504 | uint32_t dstreg = (opcode >> 9) & 7; | |
47505 | OpcodeFamily = 1; CurrentInstrCycles = 12; | |
47506 | {{ uint32_t srca = m68k_getpc () + 2; | |
47507 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
47508 | { int8_t src = m68k_read_memory_8(srca); | |
47509 | { int8_t dst = m68k_dreg(regs, dstreg); | |
47510 | src |= dst; | |
47511 | CLEAR_CZNV; | |
47512 | SET_ZFLG (((int8_t)(src)) == 0); | |
47513 | SET_NFLG (((int8_t)(src)) < 0); | |
47514 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
47515 | }}}}m68k_incpc(4); | |
47516 | fill_prefetch_0 (); | |
47517 | return 12; | |
47518 | } | |
47519 | unsigned long CPUFUNC(op_803b_5)(uint32_t opcode) /* OR */ | |
47520 | { | |
47521 | uint32_t dstreg = (opcode >> 9) & 7; | |
47522 | OpcodeFamily = 1; CurrentInstrCycles = 14; | |
47523 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
47524 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
47525 | BusCyclePenalty += 2; | |
47526 | { int8_t src = m68k_read_memory_8(srca); | |
47527 | { int8_t dst = m68k_dreg(regs, dstreg); | |
47528 | src |= dst; | |
47529 | CLEAR_CZNV; | |
47530 | SET_ZFLG (((int8_t)(src)) == 0); | |
47531 | SET_NFLG (((int8_t)(src)) < 0); | |
47532 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
47533 | }}}}m68k_incpc(4); | |
47534 | fill_prefetch_0 (); | |
47535 | return 14; | |
47536 | } | |
47537 | unsigned long CPUFUNC(op_803c_5)(uint32_t opcode) /* OR */ | |
47538 | { | |
47539 | uint32_t dstreg = (opcode >> 9) & 7; | |
47540 | OpcodeFamily = 1; CurrentInstrCycles = 8; | |
47541 | {{ int8_t src = get_ibyte_prefetch(2); | |
47542 | { int8_t dst = m68k_dreg(regs, dstreg); | |
47543 | src |= dst; | |
47544 | CLEAR_CZNV; | |
47545 | SET_ZFLG (((int8_t)(src)) == 0); | |
47546 | SET_NFLG (((int8_t)(src)) < 0); | |
47547 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
47548 | }}}m68k_incpc(4); | |
47549 | fill_prefetch_0 (); | |
47550 | return 8; | |
47551 | } | |
47552 | unsigned long CPUFUNC(op_8040_5)(uint32_t opcode) /* OR */ | |
47553 | { | |
47554 | uint32_t srcreg = (opcode & 7); | |
47555 | uint32_t dstreg = (opcode >> 9) & 7; | |
47556 | OpcodeFamily = 1; CurrentInstrCycles = 4; | |
47557 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
47558 | { int16_t dst = m68k_dreg(regs, dstreg); | |
47559 | src |= dst; | |
47560 | CLEAR_CZNV; | |
47561 | SET_ZFLG (((int16_t)(src)) == 0); | |
47562 | SET_NFLG (((int16_t)(src)) < 0); | |
47563 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
47564 | }}}m68k_incpc(2); | |
47565 | fill_prefetch_2 (); | |
47566 | return 4; | |
47567 | } | |
47568 | unsigned long CPUFUNC(op_8050_5)(uint32_t opcode) /* OR */ | |
47569 | { | |
47570 | uint32_t srcreg = (opcode & 7); | |
47571 | uint32_t dstreg = (opcode >> 9) & 7; | |
47572 | OpcodeFamily = 1; CurrentInstrCycles = 8; | |
47573 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
47574 | if ((srca & 1) != 0) { | |
47575 | last_fault_for_exception_3 = srca; | |
47576 | last_op_for_exception_3 = opcode; | |
47577 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
47578 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
47579 | goto endlabel2652; | |
47580 | } | |
47581 | {{ int16_t src = m68k_read_memory_16(srca); | |
47582 | { int16_t dst = m68k_dreg(regs, dstreg); | |
47583 | src |= dst; | |
47584 | CLEAR_CZNV; | |
47585 | SET_ZFLG (((int16_t)(src)) == 0); | |
47586 | SET_NFLG (((int16_t)(src)) < 0); | |
47587 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
47588 | }}}}}m68k_incpc(2); | |
47589 | fill_prefetch_2 (); | |
47590 | endlabel2652: ; | |
47591 | return 8; | |
47592 | } | |
47593 | unsigned long CPUFUNC(op_8058_5)(uint32_t opcode) /* OR */ | |
47594 | { | |
47595 | uint32_t srcreg = (opcode & 7); | |
47596 | uint32_t dstreg = (opcode >> 9) & 7; | |
47597 | OpcodeFamily = 1; CurrentInstrCycles = 8; | |
47598 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
47599 | if ((srca & 1) != 0) { | |
47600 | last_fault_for_exception_3 = srca; | |
47601 | last_op_for_exception_3 = opcode; | |
47602 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
47603 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
47604 | goto endlabel2653; | |
47605 | } | |
47606 | {{ int16_t src = m68k_read_memory_16(srca); | |
47607 | m68k_areg(regs, srcreg) += 2; | |
47608 | { int16_t dst = m68k_dreg(regs, dstreg); | |
47609 | src |= dst; | |
47610 | CLEAR_CZNV; | |
47611 | SET_ZFLG (((int16_t)(src)) == 0); | |
47612 | SET_NFLG (((int16_t)(src)) < 0); | |
47613 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
47614 | }}}}}m68k_incpc(2); | |
47615 | fill_prefetch_2 (); | |
47616 | endlabel2653: ; | |
47617 | return 8; | |
47618 | } | |
47619 | unsigned long CPUFUNC(op_8060_5)(uint32_t opcode) /* OR */ | |
47620 | { | |
47621 | uint32_t srcreg = (opcode & 7); | |
47622 | uint32_t dstreg = (opcode >> 9) & 7; | |
47623 | OpcodeFamily = 1; CurrentInstrCycles = 10; | |
47624 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
47625 | if ((srca & 1) != 0) { | |
47626 | last_fault_for_exception_3 = srca; | |
47627 | last_op_for_exception_3 = opcode; | |
47628 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
47629 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
47630 | goto endlabel2654; | |
47631 | } | |
47632 | {{ int16_t src = m68k_read_memory_16(srca); | |
47633 | m68k_areg (regs, srcreg) = srca; | |
47634 | { int16_t dst = m68k_dreg(regs, dstreg); | |
47635 | src |= dst; | |
47636 | CLEAR_CZNV; | |
47637 | SET_ZFLG (((int16_t)(src)) == 0); | |
47638 | SET_NFLG (((int16_t)(src)) < 0); | |
47639 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
47640 | }}}}}m68k_incpc(2); | |
47641 | fill_prefetch_2 (); | |
47642 | endlabel2654: ; | |
47643 | return 10; | |
47644 | } | |
47645 | unsigned long CPUFUNC(op_8068_5)(uint32_t opcode) /* OR */ | |
47646 | { | |
47647 | uint32_t srcreg = (opcode & 7); | |
47648 | uint32_t dstreg = (opcode >> 9) & 7; | |
47649 | OpcodeFamily = 1; CurrentInstrCycles = 12; | |
47650 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
47651 | if ((srca & 1) != 0) { | |
47652 | last_fault_for_exception_3 = srca; | |
47653 | last_op_for_exception_3 = opcode; | |
47654 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
47655 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
47656 | goto endlabel2655; | |
47657 | } | |
47658 | {{ int16_t src = m68k_read_memory_16(srca); | |
47659 | { int16_t dst = m68k_dreg(regs, dstreg); | |
47660 | src |= dst; | |
47661 | CLEAR_CZNV; | |
47662 | SET_ZFLG (((int16_t)(src)) == 0); | |
47663 | SET_NFLG (((int16_t)(src)) < 0); | |
47664 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
47665 | }}}}}m68k_incpc(4); | |
47666 | fill_prefetch_0 (); | |
47667 | endlabel2655: ; | |
47668 | return 12; | |
47669 | } | |
47670 | unsigned long CPUFUNC(op_8070_5)(uint32_t opcode) /* OR */ | |
47671 | { | |
47672 | uint32_t srcreg = (opcode & 7); | |
47673 | uint32_t dstreg = (opcode >> 9) & 7; | |
47674 | OpcodeFamily = 1; CurrentInstrCycles = 14; | |
47675 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
47676 | BusCyclePenalty += 2; | |
47677 | if ((srca & 1) != 0) { | |
47678 | last_fault_for_exception_3 = srca; | |
47679 | last_op_for_exception_3 = opcode; | |
47680 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
47681 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
47682 | goto endlabel2656; | |
47683 | } | |
47684 | {{ int16_t src = m68k_read_memory_16(srca); | |
47685 | { int16_t dst = m68k_dreg(regs, dstreg); | |
47686 | src |= dst; | |
47687 | CLEAR_CZNV; | |
47688 | SET_ZFLG (((int16_t)(src)) == 0); | |
47689 | SET_NFLG (((int16_t)(src)) < 0); | |
47690 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
47691 | }}}}}m68k_incpc(4); | |
47692 | fill_prefetch_0 (); | |
47693 | endlabel2656: ; | |
47694 | return 14; | |
47695 | } | |
47696 | unsigned long CPUFUNC(op_8078_5)(uint32_t opcode) /* OR */ | |
47697 | { | |
47698 | uint32_t dstreg = (opcode >> 9) & 7; | |
47699 | OpcodeFamily = 1; CurrentInstrCycles = 12; | |
47700 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
47701 | if ((srca & 1) != 0) { | |
47702 | last_fault_for_exception_3 = srca; | |
47703 | last_op_for_exception_3 = opcode; | |
47704 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
47705 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
47706 | goto endlabel2657; | |
47707 | } | |
47708 | {{ int16_t src = m68k_read_memory_16(srca); | |
47709 | { int16_t dst = m68k_dreg(regs, dstreg); | |
47710 | src |= dst; | |
47711 | CLEAR_CZNV; | |
47712 | SET_ZFLG (((int16_t)(src)) == 0); | |
47713 | SET_NFLG (((int16_t)(src)) < 0); | |
47714 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
47715 | }}}}}m68k_incpc(4); | |
47716 | fill_prefetch_0 (); | |
47717 | endlabel2657: ; | |
47718 | return 12; | |
47719 | } | |
47720 | unsigned long CPUFUNC(op_8079_5)(uint32_t opcode) /* OR */ | |
47721 | { | |
47722 | uint32_t dstreg = (opcode >> 9) & 7; | |
47723 | OpcodeFamily = 1; CurrentInstrCycles = 16; | |
47724 | {{ uint32_t srca = get_ilong_prefetch(2); | |
47725 | if ((srca & 1) != 0) { | |
47726 | last_fault_for_exception_3 = srca; | |
47727 | last_op_for_exception_3 = opcode; | |
47728 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
47729 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
47730 | goto endlabel2658; | |
47731 | } | |
47732 | {{ int16_t src = m68k_read_memory_16(srca); | |
47733 | { int16_t dst = m68k_dreg(regs, dstreg); | |
47734 | src |= dst; | |
47735 | CLEAR_CZNV; | |
47736 | SET_ZFLG (((int16_t)(src)) == 0); | |
47737 | SET_NFLG (((int16_t)(src)) < 0); | |
47738 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
47739 | }}}}}m68k_incpc(6); | |
47740 | fill_prefetch_0 (); | |
47741 | endlabel2658: ; | |
47742 | return 16; | |
47743 | } | |
47744 | unsigned long CPUFUNC(op_807a_5)(uint32_t opcode) /* OR */ | |
47745 | { | |
47746 | uint32_t dstreg = (opcode >> 9) & 7; | |
47747 | OpcodeFamily = 1; CurrentInstrCycles = 12; | |
47748 | {{ uint32_t srca = m68k_getpc () + 2; | |
47749 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
47750 | if ((srca & 1) != 0) { | |
47751 | last_fault_for_exception_3 = srca; | |
47752 | last_op_for_exception_3 = opcode; | |
47753 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
47754 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
47755 | goto endlabel2659; | |
47756 | } | |
47757 | {{ int16_t src = m68k_read_memory_16(srca); | |
47758 | { int16_t dst = m68k_dreg(regs, dstreg); | |
47759 | src |= dst; | |
47760 | CLEAR_CZNV; | |
47761 | SET_ZFLG (((int16_t)(src)) == 0); | |
47762 | SET_NFLG (((int16_t)(src)) < 0); | |
47763 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
47764 | }}}}}m68k_incpc(4); | |
47765 | fill_prefetch_0 (); | |
47766 | endlabel2659: ; | |
47767 | return 12; | |
47768 | } | |
47769 | unsigned long CPUFUNC(op_807b_5)(uint32_t opcode) /* OR */ | |
47770 | { | |
47771 | uint32_t dstreg = (opcode >> 9) & 7; | |
47772 | OpcodeFamily = 1; CurrentInstrCycles = 14; | |
47773 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
47774 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
47775 | BusCyclePenalty += 2; | |
47776 | if ((srca & 1) != 0) { | |
47777 | last_fault_for_exception_3 = srca; | |
47778 | last_op_for_exception_3 = opcode; | |
47779 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
47780 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
47781 | goto endlabel2660; | |
47782 | } | |
47783 | {{ int16_t src = m68k_read_memory_16(srca); | |
47784 | { int16_t dst = m68k_dreg(regs, dstreg); | |
47785 | src |= dst; | |
47786 | CLEAR_CZNV; | |
47787 | SET_ZFLG (((int16_t)(src)) == 0); | |
47788 | SET_NFLG (((int16_t)(src)) < 0); | |
47789 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
47790 | }}}}}m68k_incpc(4); | |
47791 | fill_prefetch_0 (); | |
47792 | endlabel2660: ; | |
47793 | return 14; | |
47794 | } | |
47795 | unsigned long CPUFUNC(op_807c_5)(uint32_t opcode) /* OR */ | |
47796 | { | |
47797 | uint32_t dstreg = (opcode >> 9) & 7; | |
47798 | OpcodeFamily = 1; CurrentInstrCycles = 8; | |
47799 | {{ int16_t src = get_iword_prefetch(2); | |
47800 | { int16_t dst = m68k_dreg(regs, dstreg); | |
47801 | src |= dst; | |
47802 | CLEAR_CZNV; | |
47803 | SET_ZFLG (((int16_t)(src)) == 0); | |
47804 | SET_NFLG (((int16_t)(src)) < 0); | |
47805 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
47806 | }}}m68k_incpc(4); | |
47807 | fill_prefetch_0 (); | |
47808 | return 8; | |
47809 | } | |
47810 | unsigned long CPUFUNC(op_8080_5)(uint32_t opcode) /* OR */ | |
47811 | { | |
47812 | uint32_t srcreg = (opcode & 7); | |
47813 | uint32_t dstreg = (opcode >> 9) & 7; | |
47814 | OpcodeFamily = 1; CurrentInstrCycles = 8; | |
47815 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
47816 | { int32_t dst = m68k_dreg(regs, dstreg); | |
47817 | src |= dst; | |
47818 | CLEAR_CZNV; | |
47819 | SET_ZFLG (((int32_t)(src)) == 0); | |
47820 | SET_NFLG (((int32_t)(src)) < 0); | |
47821 | m68k_dreg(regs, dstreg) = (src); | |
47822 | }}}m68k_incpc(2); | |
47823 | fill_prefetch_2 (); | |
47824 | return 8; | |
47825 | } | |
47826 | unsigned long CPUFUNC(op_8090_5)(uint32_t opcode) /* OR */ | |
47827 | { | |
47828 | uint32_t srcreg = (opcode & 7); | |
47829 | uint32_t dstreg = (opcode >> 9) & 7; | |
47830 | OpcodeFamily = 1; CurrentInstrCycles = 14; | |
47831 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
47832 | if ((srca & 1) != 0) { | |
47833 | last_fault_for_exception_3 = srca; | |
47834 | last_op_for_exception_3 = opcode; | |
47835 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
47836 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
47837 | goto endlabel2663; | |
47838 | } | |
47839 | {{ int32_t src = m68k_read_memory_32(srca); | |
47840 | { int32_t dst = m68k_dreg(regs, dstreg); | |
47841 | src |= dst; | |
47842 | CLEAR_CZNV; | |
47843 | SET_ZFLG (((int32_t)(src)) == 0); | |
47844 | SET_NFLG (((int32_t)(src)) < 0); | |
47845 | m68k_dreg(regs, dstreg) = (src); | |
47846 | }}}}}m68k_incpc(2); | |
47847 | fill_prefetch_2 (); | |
47848 | endlabel2663: ; | |
47849 | return 14; | |
47850 | } | |
47851 | unsigned long CPUFUNC(op_8098_5)(uint32_t opcode) /* OR */ | |
47852 | { | |
47853 | uint32_t srcreg = (opcode & 7); | |
47854 | uint32_t dstreg = (opcode >> 9) & 7; | |
47855 | OpcodeFamily = 1; CurrentInstrCycles = 14; | |
47856 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
47857 | if ((srca & 1) != 0) { | |
47858 | last_fault_for_exception_3 = srca; | |
47859 | last_op_for_exception_3 = opcode; | |
47860 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
47861 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
47862 | goto endlabel2664; | |
47863 | } | |
47864 | {{ int32_t src = m68k_read_memory_32(srca); | |
47865 | m68k_areg(regs, srcreg) += 4; | |
47866 | { int32_t dst = m68k_dreg(regs, dstreg); | |
47867 | src |= dst; | |
47868 | CLEAR_CZNV; | |
47869 | SET_ZFLG (((int32_t)(src)) == 0); | |
47870 | SET_NFLG (((int32_t)(src)) < 0); | |
47871 | m68k_dreg(regs, dstreg) = (src); | |
47872 | }}}}}m68k_incpc(2); | |
47873 | fill_prefetch_2 (); | |
47874 | endlabel2664: ; | |
47875 | return 14; | |
47876 | } | |
47877 | unsigned long CPUFUNC(op_80a0_5)(uint32_t opcode) /* OR */ | |
47878 | { | |
47879 | uint32_t srcreg = (opcode & 7); | |
47880 | uint32_t dstreg = (opcode >> 9) & 7; | |
47881 | OpcodeFamily = 1; CurrentInstrCycles = 16; | |
47882 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 4; | |
47883 | if ((srca & 1) != 0) { | |
47884 | last_fault_for_exception_3 = srca; | |
47885 | last_op_for_exception_3 = opcode; | |
47886 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
47887 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
47888 | goto endlabel2665; | |
47889 | } | |
47890 | {{ int32_t src = m68k_read_memory_32(srca); | |
47891 | m68k_areg (regs, srcreg) = srca; | |
47892 | { int32_t dst = m68k_dreg(regs, dstreg); | |
47893 | src |= dst; | |
47894 | CLEAR_CZNV; | |
47895 | SET_ZFLG (((int32_t)(src)) == 0); | |
47896 | SET_NFLG (((int32_t)(src)) < 0); | |
47897 | m68k_dreg(regs, dstreg) = (src); | |
47898 | }}}}}m68k_incpc(2); | |
47899 | fill_prefetch_2 (); | |
47900 | endlabel2665: ; | |
47901 | return 16; | |
47902 | } | |
47903 | unsigned long CPUFUNC(op_80a8_5)(uint32_t opcode) /* OR */ | |
47904 | { | |
47905 | uint32_t srcreg = (opcode & 7); | |
47906 | uint32_t dstreg = (opcode >> 9) & 7; | |
47907 | OpcodeFamily = 1; CurrentInstrCycles = 18; | |
47908 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
47909 | if ((srca & 1) != 0) { | |
47910 | last_fault_for_exception_3 = srca; | |
47911 | last_op_for_exception_3 = opcode; | |
47912 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
47913 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
47914 | goto endlabel2666; | |
47915 | } | |
47916 | {{ int32_t src = m68k_read_memory_32(srca); | |
47917 | { int32_t dst = m68k_dreg(regs, dstreg); | |
47918 | src |= dst; | |
47919 | CLEAR_CZNV; | |
47920 | SET_ZFLG (((int32_t)(src)) == 0); | |
47921 | SET_NFLG (((int32_t)(src)) < 0); | |
47922 | m68k_dreg(regs, dstreg) = (src); | |
47923 | }}}}}m68k_incpc(4); | |
47924 | fill_prefetch_0 (); | |
47925 | endlabel2666: ; | |
47926 | return 18; | |
47927 | } | |
47928 | unsigned long CPUFUNC(op_80b0_5)(uint32_t opcode) /* OR */ | |
47929 | { | |
47930 | uint32_t srcreg = (opcode & 7); | |
47931 | uint32_t dstreg = (opcode >> 9) & 7; | |
47932 | OpcodeFamily = 1; CurrentInstrCycles = 20; | |
47933 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
47934 | BusCyclePenalty += 2; | |
47935 | if ((srca & 1) != 0) { | |
47936 | last_fault_for_exception_3 = srca; | |
47937 | last_op_for_exception_3 = opcode; | |
47938 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
47939 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
47940 | goto endlabel2667; | |
47941 | } | |
47942 | {{ int32_t src = m68k_read_memory_32(srca); | |
47943 | { int32_t dst = m68k_dreg(regs, dstreg); | |
47944 | src |= dst; | |
47945 | CLEAR_CZNV; | |
47946 | SET_ZFLG (((int32_t)(src)) == 0); | |
47947 | SET_NFLG (((int32_t)(src)) < 0); | |
47948 | m68k_dreg(regs, dstreg) = (src); | |
47949 | }}}}}m68k_incpc(4); | |
47950 | fill_prefetch_0 (); | |
47951 | endlabel2667: ; | |
47952 | return 20; | |
47953 | } | |
47954 | unsigned long CPUFUNC(op_80b8_5)(uint32_t opcode) /* OR */ | |
47955 | { | |
47956 | uint32_t dstreg = (opcode >> 9) & 7; | |
47957 | OpcodeFamily = 1; CurrentInstrCycles = 18; | |
47958 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
47959 | if ((srca & 1) != 0) { | |
47960 | last_fault_for_exception_3 = srca; | |
47961 | last_op_for_exception_3 = opcode; | |
47962 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
47963 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
47964 | goto endlabel2668; | |
47965 | } | |
47966 | {{ int32_t src = m68k_read_memory_32(srca); | |
47967 | { int32_t dst = m68k_dreg(regs, dstreg); | |
47968 | src |= dst; | |
47969 | CLEAR_CZNV; | |
47970 | SET_ZFLG (((int32_t)(src)) == 0); | |
47971 | SET_NFLG (((int32_t)(src)) < 0); | |
47972 | m68k_dreg(regs, dstreg) = (src); | |
47973 | }}}}}m68k_incpc(4); | |
47974 | fill_prefetch_0 (); | |
47975 | endlabel2668: ; | |
47976 | return 18; | |
47977 | } | |
47978 | unsigned long CPUFUNC(op_80b9_5)(uint32_t opcode) /* OR */ | |
47979 | { | |
47980 | uint32_t dstreg = (opcode >> 9) & 7; | |
47981 | OpcodeFamily = 1; CurrentInstrCycles = 22; | |
47982 | {{ uint32_t srca = get_ilong_prefetch(2); | |
47983 | if ((srca & 1) != 0) { | |
47984 | last_fault_for_exception_3 = srca; | |
47985 | last_op_for_exception_3 = opcode; | |
47986 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
47987 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
47988 | goto endlabel2669; | |
47989 | } | |
47990 | {{ int32_t src = m68k_read_memory_32(srca); | |
47991 | { int32_t dst = m68k_dreg(regs, dstreg); | |
47992 | src |= dst; | |
47993 | CLEAR_CZNV; | |
47994 | SET_ZFLG (((int32_t)(src)) == 0); | |
47995 | SET_NFLG (((int32_t)(src)) < 0); | |
47996 | m68k_dreg(regs, dstreg) = (src); | |
47997 | }}}}}m68k_incpc(6); | |
47998 | fill_prefetch_0 (); | |
47999 | endlabel2669: ; | |
48000 | return 22; | |
48001 | } | |
48002 | unsigned long CPUFUNC(op_80ba_5)(uint32_t opcode) /* OR */ | |
48003 | { | |
48004 | uint32_t dstreg = (opcode >> 9) & 7; | |
48005 | OpcodeFamily = 1; CurrentInstrCycles = 18; | |
48006 | {{ uint32_t srca = m68k_getpc () + 2; | |
48007 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
48008 | if ((srca & 1) != 0) { | |
48009 | last_fault_for_exception_3 = srca; | |
48010 | last_op_for_exception_3 = opcode; | |
48011 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
48012 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
48013 | goto endlabel2670; | |
48014 | } | |
48015 | {{ int32_t src = m68k_read_memory_32(srca); | |
48016 | { int32_t dst = m68k_dreg(regs, dstreg); | |
48017 | src |= dst; | |
48018 | CLEAR_CZNV; | |
48019 | SET_ZFLG (((int32_t)(src)) == 0); | |
48020 | SET_NFLG (((int32_t)(src)) < 0); | |
48021 | m68k_dreg(regs, dstreg) = (src); | |
48022 | }}}}}m68k_incpc(4); | |
48023 | fill_prefetch_0 (); | |
48024 | endlabel2670: ; | |
48025 | return 18; | |
48026 | } | |
48027 | unsigned long CPUFUNC(op_80bb_5)(uint32_t opcode) /* OR */ | |
48028 | { | |
48029 | uint32_t dstreg = (opcode >> 9) & 7; | |
48030 | OpcodeFamily = 1; CurrentInstrCycles = 20; | |
48031 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
48032 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
48033 | BusCyclePenalty += 2; | |
48034 | if ((srca & 1) != 0) { | |
48035 | last_fault_for_exception_3 = srca; | |
48036 | last_op_for_exception_3 = opcode; | |
48037 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
48038 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
48039 | goto endlabel2671; | |
48040 | } | |
48041 | {{ int32_t src = m68k_read_memory_32(srca); | |
48042 | { int32_t dst = m68k_dreg(regs, dstreg); | |
48043 | src |= dst; | |
48044 | CLEAR_CZNV; | |
48045 | SET_ZFLG (((int32_t)(src)) == 0); | |
48046 | SET_NFLG (((int32_t)(src)) < 0); | |
48047 | m68k_dreg(regs, dstreg) = (src); | |
48048 | }}}}}m68k_incpc(4); | |
48049 | fill_prefetch_0 (); | |
48050 | endlabel2671: ; | |
48051 | return 20; | |
48052 | } | |
48053 | unsigned long CPUFUNC(op_80bc_5)(uint32_t opcode) /* OR */ | |
48054 | { | |
48055 | uint32_t dstreg = (opcode >> 9) & 7; | |
48056 | OpcodeFamily = 1; CurrentInstrCycles = 16; | |
48057 | {{ int32_t src = get_ilong_prefetch(2); | |
48058 | { int32_t dst = m68k_dreg(regs, dstreg); | |
48059 | src |= dst; | |
48060 | CLEAR_CZNV; | |
48061 | SET_ZFLG (((int32_t)(src)) == 0); | |
48062 | SET_NFLG (((int32_t)(src)) < 0); | |
48063 | m68k_dreg(regs, dstreg) = (src); | |
48064 | }}}m68k_incpc(6); | |
48065 | fill_prefetch_0 (); | |
48066 | return 16; | |
48067 | } | |
48068 | unsigned long CPUFUNC(op_80c0_5)(uint32_t opcode) /* DIVU */ | |
48069 | { | |
48070 | uint32_t srcreg = (opcode & 7); | |
48071 | uint32_t dstreg = (opcode >> 9) & 7; | |
48072 | unsigned int retcycles = 0; | |
48073 | OpcodeFamily = 60; CurrentInstrCycles = 4; | |
48074 | { uint32_t oldpc = m68k_getpc(); | |
48075 | { int16_t src = m68k_dreg(regs, srcreg); | |
48076 | { int32_t dst = m68k_dreg(regs, dstreg); | |
48077 | m68k_incpc(2); | |
48078 | fill_prefetch_2 (); | |
48079 | if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel2673; } else { | |
48080 | uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src; | |
48081 | uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src; | |
48082 | if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else | |
48083 | { | |
48084 | CLEAR_CZNV; | |
48085 | SET_ZFLG (((int16_t)(newv)) == 0); | |
48086 | SET_NFLG (((int16_t)(newv)) < 0); | |
48087 | newv = (newv & 0xffff) | ((uint32_t)rem << 16); | |
48088 | m68k_dreg(regs, dstreg) = (newv); | |
48089 | } | |
48090 | } | |
48091 | retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src); | |
48092 | }}}endlabel2673: ; | |
48093 | return (4+retcycles); | |
48094 | } | |
48095 | unsigned long CPUFUNC(op_80d0_5)(uint32_t opcode) /* DIVU */ | |
48096 | { | |
48097 | uint32_t srcreg = (opcode & 7); | |
48098 | uint32_t dstreg = (opcode >> 9) & 7; | |
48099 | unsigned int retcycles = 0; | |
48100 | OpcodeFamily = 60; CurrentInstrCycles = 8; | |
48101 | { uint32_t oldpc = m68k_getpc(); | |
48102 | { uint32_t srca = m68k_areg(regs, srcreg); | |
48103 | if ((srca & 1) != 0) { | |
48104 | last_fault_for_exception_3 = srca; | |
48105 | last_op_for_exception_3 = opcode; | |
48106 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
48107 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
48108 | goto endlabel2674; | |
48109 | } | |
48110 | {{ int16_t src = m68k_read_memory_16(srca); | |
48111 | { int32_t dst = m68k_dreg(regs, dstreg); | |
48112 | m68k_incpc(2); | |
48113 | fill_prefetch_2 (); | |
48114 | if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel2674; } else { | |
48115 | uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src; | |
48116 | uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src; | |
48117 | if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else | |
48118 | { | |
48119 | CLEAR_CZNV; | |
48120 | SET_ZFLG (((int16_t)(newv)) == 0); | |
48121 | SET_NFLG (((int16_t)(newv)) < 0); | |
48122 | newv = (newv & 0xffff) | ((uint32_t)rem << 16); | |
48123 | m68k_dreg(regs, dstreg) = (newv); | |
48124 | } | |
48125 | } | |
48126 | retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src); | |
48127 | }}}}}endlabel2674: ; | |
48128 | return (8+retcycles); | |
48129 | } | |
48130 | unsigned long CPUFUNC(op_80d8_5)(uint32_t opcode) /* DIVU */ | |
48131 | { | |
48132 | uint32_t srcreg = (opcode & 7); | |
48133 | uint32_t dstreg = (opcode >> 9) & 7; | |
48134 | unsigned int retcycles = 0; | |
48135 | OpcodeFamily = 60; CurrentInstrCycles = 8; | |
48136 | { uint32_t oldpc = m68k_getpc(); | |
48137 | { uint32_t srca = m68k_areg(regs, srcreg); | |
48138 | if ((srca & 1) != 0) { | |
48139 | last_fault_for_exception_3 = srca; | |
48140 | last_op_for_exception_3 = opcode; | |
48141 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
48142 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
48143 | goto endlabel2675; | |
48144 | } | |
48145 | {{ int16_t src = m68k_read_memory_16(srca); | |
48146 | m68k_areg(regs, srcreg) += 2; | |
48147 | { int32_t dst = m68k_dreg(regs, dstreg); | |
48148 | m68k_incpc(2); | |
48149 | fill_prefetch_2 (); | |
48150 | if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel2675; } else { | |
48151 | uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src; | |
48152 | uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src; | |
48153 | if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else | |
48154 | { | |
48155 | CLEAR_CZNV; | |
48156 | SET_ZFLG (((int16_t)(newv)) == 0); | |
48157 | SET_NFLG (((int16_t)(newv)) < 0); | |
48158 | newv = (newv & 0xffff) | ((uint32_t)rem << 16); | |
48159 | m68k_dreg(regs, dstreg) = (newv); | |
48160 | } | |
48161 | } | |
48162 | retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src); | |
48163 | }}}}}endlabel2675: ; | |
48164 | return (8+retcycles); | |
48165 | } | |
48166 | unsigned long CPUFUNC(op_80e0_5)(uint32_t opcode) /* DIVU */ | |
48167 | { | |
48168 | uint32_t srcreg = (opcode & 7); | |
48169 | uint32_t dstreg = (opcode >> 9) & 7; | |
48170 | unsigned int retcycles = 0; | |
48171 | OpcodeFamily = 60; CurrentInstrCycles = 10; | |
48172 | { uint32_t oldpc = m68k_getpc(); | |
48173 | { uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
48174 | if ((srca & 1) != 0) { | |
48175 | last_fault_for_exception_3 = srca; | |
48176 | last_op_for_exception_3 = opcode; | |
48177 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
48178 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
48179 | goto endlabel2676; | |
48180 | } | |
48181 | {{ int16_t src = m68k_read_memory_16(srca); | |
48182 | m68k_areg (regs, srcreg) = srca; | |
48183 | { int32_t dst = m68k_dreg(regs, dstreg); | |
48184 | m68k_incpc(2); | |
48185 | fill_prefetch_2 (); | |
48186 | if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel2676; } else { | |
48187 | uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src; | |
48188 | uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src; | |
48189 | if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else | |
48190 | { | |
48191 | CLEAR_CZNV; | |
48192 | SET_ZFLG (((int16_t)(newv)) == 0); | |
48193 | SET_NFLG (((int16_t)(newv)) < 0); | |
48194 | newv = (newv & 0xffff) | ((uint32_t)rem << 16); | |
48195 | m68k_dreg(regs, dstreg) = (newv); | |
48196 | } | |
48197 | } | |
48198 | retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src); | |
48199 | }}}}}endlabel2676: ; | |
48200 | return (10+retcycles); | |
48201 | } | |
48202 | unsigned long CPUFUNC(op_80e8_5)(uint32_t opcode) /* DIVU */ | |
48203 | { | |
48204 | uint32_t srcreg = (opcode & 7); | |
48205 | uint32_t dstreg = (opcode >> 9) & 7; | |
48206 | unsigned int retcycles = 0; | |
48207 | OpcodeFamily = 60; CurrentInstrCycles = 12; | |
48208 | { uint32_t oldpc = m68k_getpc(); | |
48209 | { uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
48210 | if ((srca & 1) != 0) { | |
48211 | last_fault_for_exception_3 = srca; | |
48212 | last_op_for_exception_3 = opcode; | |
48213 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
48214 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
48215 | goto endlabel2677; | |
48216 | } | |
48217 | {{ int16_t src = m68k_read_memory_16(srca); | |
48218 | { int32_t dst = m68k_dreg(regs, dstreg); | |
48219 | m68k_incpc(4); | |
48220 | fill_prefetch_0 (); | |
48221 | if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel2677; } else { | |
48222 | uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src; | |
48223 | uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src; | |
48224 | if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else | |
48225 | { | |
48226 | CLEAR_CZNV; | |
48227 | SET_ZFLG (((int16_t)(newv)) == 0); | |
48228 | SET_NFLG (((int16_t)(newv)) < 0); | |
48229 | newv = (newv & 0xffff) | ((uint32_t)rem << 16); | |
48230 | m68k_dreg(regs, dstreg) = (newv); | |
48231 | } | |
48232 | } | |
48233 | retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src); | |
48234 | }}}}}endlabel2677: ; | |
48235 | return (12+retcycles); | |
48236 | } | |
48237 | unsigned long CPUFUNC(op_80f0_5)(uint32_t opcode) /* DIVU */ | |
48238 | { | |
48239 | uint32_t srcreg = (opcode & 7); | |
48240 | uint32_t dstreg = (opcode >> 9) & 7; | |
48241 | unsigned int retcycles = 0; | |
48242 | OpcodeFamily = 60; CurrentInstrCycles = 14; | |
48243 | { uint32_t oldpc = m68k_getpc(); | |
48244 | { uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
48245 | BusCyclePenalty += 2; | |
48246 | if ((srca & 1) != 0) { | |
48247 | last_fault_for_exception_3 = srca; | |
48248 | last_op_for_exception_3 = opcode; | |
48249 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
48250 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
48251 | goto endlabel2678; | |
48252 | } | |
48253 | {{ int16_t src = m68k_read_memory_16(srca); | |
48254 | { int32_t dst = m68k_dreg(regs, dstreg); | |
48255 | m68k_incpc(4); | |
48256 | fill_prefetch_0 (); | |
48257 | if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel2678; } else { | |
48258 | uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src; | |
48259 | uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src; | |
48260 | if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else | |
48261 | { | |
48262 | CLEAR_CZNV; | |
48263 | SET_ZFLG (((int16_t)(newv)) == 0); | |
48264 | SET_NFLG (((int16_t)(newv)) < 0); | |
48265 | newv = (newv & 0xffff) | ((uint32_t)rem << 16); | |
48266 | m68k_dreg(regs, dstreg) = (newv); | |
48267 | } | |
48268 | } | |
48269 | retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src); | |
48270 | }}}}}endlabel2678: ; | |
48271 | return (14+retcycles); | |
48272 | } | |
48273 | unsigned long CPUFUNC(op_80f8_5)(uint32_t opcode) /* DIVU */ | |
48274 | { | |
48275 | uint32_t dstreg = (opcode >> 9) & 7; | |
48276 | unsigned int retcycles = 0; | |
48277 | OpcodeFamily = 60; CurrentInstrCycles = 12; | |
48278 | { uint32_t oldpc = m68k_getpc(); | |
48279 | { uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
48280 | if ((srca & 1) != 0) { | |
48281 | last_fault_for_exception_3 = srca; | |
48282 | last_op_for_exception_3 = opcode; | |
48283 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
48284 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
48285 | goto endlabel2679; | |
48286 | } | |
48287 | {{ int16_t src = m68k_read_memory_16(srca); | |
48288 | { int32_t dst = m68k_dreg(regs, dstreg); | |
48289 | m68k_incpc(4); | |
48290 | fill_prefetch_0 (); | |
48291 | if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel2679; } else { | |
48292 | uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src; | |
48293 | uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src; | |
48294 | if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else | |
48295 | { | |
48296 | CLEAR_CZNV; | |
48297 | SET_ZFLG (((int16_t)(newv)) == 0); | |
48298 | SET_NFLG (((int16_t)(newv)) < 0); | |
48299 | newv = (newv & 0xffff) | ((uint32_t)rem << 16); | |
48300 | m68k_dreg(regs, dstreg) = (newv); | |
48301 | } | |
48302 | } | |
48303 | retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src); | |
48304 | }}}}}endlabel2679: ; | |
48305 | return (12+retcycles); | |
48306 | } | |
48307 | unsigned long CPUFUNC(op_80f9_5)(uint32_t opcode) /* DIVU */ | |
48308 | { | |
48309 | uint32_t dstreg = (opcode >> 9) & 7; | |
48310 | unsigned int retcycles = 0; | |
48311 | OpcodeFamily = 60; CurrentInstrCycles = 16; | |
48312 | { uint32_t oldpc = m68k_getpc(); | |
48313 | { uint32_t srca = get_ilong_prefetch(2); | |
48314 | if ((srca & 1) != 0) { | |
48315 | last_fault_for_exception_3 = srca; | |
48316 | last_op_for_exception_3 = opcode; | |
48317 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
48318 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
48319 | goto endlabel2680; | |
48320 | } | |
48321 | {{ int16_t src = m68k_read_memory_16(srca); | |
48322 | { int32_t dst = m68k_dreg(regs, dstreg); | |
48323 | m68k_incpc(6); | |
48324 | fill_prefetch_0 (); | |
48325 | if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel2680; } else { | |
48326 | uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src; | |
48327 | uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src; | |
48328 | if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else | |
48329 | { | |
48330 | CLEAR_CZNV; | |
48331 | SET_ZFLG (((int16_t)(newv)) == 0); | |
48332 | SET_NFLG (((int16_t)(newv)) < 0); | |
48333 | newv = (newv & 0xffff) | ((uint32_t)rem << 16); | |
48334 | m68k_dreg(regs, dstreg) = (newv); | |
48335 | } | |
48336 | } | |
48337 | retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src); | |
48338 | }}}}}endlabel2680: ; | |
48339 | return (16+retcycles); | |
48340 | } | |
48341 | unsigned long CPUFUNC(op_80fa_5)(uint32_t opcode) /* DIVU */ | |
48342 | { | |
48343 | uint32_t dstreg = (opcode >> 9) & 7; | |
48344 | unsigned int retcycles = 0; | |
48345 | OpcodeFamily = 60; CurrentInstrCycles = 12; | |
48346 | { uint32_t oldpc = m68k_getpc(); | |
48347 | { uint32_t srca = m68k_getpc () + 2; | |
48348 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
48349 | if ((srca & 1) != 0) { | |
48350 | last_fault_for_exception_3 = srca; | |
48351 | last_op_for_exception_3 = opcode; | |
48352 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
48353 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
48354 | goto endlabel2681; | |
48355 | } | |
48356 | {{ int16_t src = m68k_read_memory_16(srca); | |
48357 | { int32_t dst = m68k_dreg(regs, dstreg); | |
48358 | m68k_incpc(4); | |
48359 | fill_prefetch_0 (); | |
48360 | if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel2681; } else { | |
48361 | uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src; | |
48362 | uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src; | |
48363 | if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else | |
48364 | { | |
48365 | CLEAR_CZNV; | |
48366 | SET_ZFLG (((int16_t)(newv)) == 0); | |
48367 | SET_NFLG (((int16_t)(newv)) < 0); | |
48368 | newv = (newv & 0xffff) | ((uint32_t)rem << 16); | |
48369 | m68k_dreg(regs, dstreg) = (newv); | |
48370 | } | |
48371 | } | |
48372 | retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src); | |
48373 | }}}}}endlabel2681: ; | |
48374 | return (12+retcycles); | |
48375 | } | |
48376 | unsigned long CPUFUNC(op_80fb_5)(uint32_t opcode) /* DIVU */ | |
48377 | { | |
48378 | uint32_t dstreg = (opcode >> 9) & 7; | |
48379 | unsigned int retcycles = 0; | |
48380 | OpcodeFamily = 60; CurrentInstrCycles = 14; | |
48381 | { uint32_t oldpc = m68k_getpc(); | |
48382 | { uint32_t tmppc = m68k_getpc() + 2; | |
48383 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
48384 | BusCyclePenalty += 2; | |
48385 | if ((srca & 1) != 0) { | |
48386 | last_fault_for_exception_3 = srca; | |
48387 | last_op_for_exception_3 = opcode; | |
48388 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
48389 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
48390 | goto endlabel2682; | |
48391 | } | |
48392 | {{ int16_t src = m68k_read_memory_16(srca); | |
48393 | { int32_t dst = m68k_dreg(regs, dstreg); | |
48394 | m68k_incpc(4); | |
48395 | fill_prefetch_0 (); | |
48396 | if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel2682; } else { | |
48397 | uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src; | |
48398 | uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src; | |
48399 | if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else | |
48400 | { | |
48401 | CLEAR_CZNV; | |
48402 | SET_ZFLG (((int16_t)(newv)) == 0); | |
48403 | SET_NFLG (((int16_t)(newv)) < 0); | |
48404 | newv = (newv & 0xffff) | ((uint32_t)rem << 16); | |
48405 | m68k_dreg(regs, dstreg) = (newv); | |
48406 | } | |
48407 | } | |
48408 | retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src); | |
48409 | }}}}}endlabel2682: ; | |
48410 | return (14+retcycles); | |
48411 | } | |
48412 | unsigned long CPUFUNC(op_80fc_5)(uint32_t opcode) /* DIVU */ | |
48413 | { | |
48414 | uint32_t dstreg = (opcode >> 9) & 7; | |
48415 | unsigned int retcycles = 0; | |
48416 | OpcodeFamily = 60; CurrentInstrCycles = 8; | |
48417 | { uint32_t oldpc = m68k_getpc(); | |
48418 | { int16_t src = get_iword_prefetch(2); | |
48419 | { int32_t dst = m68k_dreg(regs, dstreg); | |
48420 | m68k_incpc(4); | |
48421 | fill_prefetch_0 (); | |
48422 | if (src == 0) { SET_VFLG (0); Exception (5, oldpc,M68000_EXC_SRC_CPU); goto endlabel2683; } else { | |
48423 | uint32_t newv = (uint32_t)dst / (uint32_t)(uint16_t)src; | |
48424 | uint32_t rem = (uint32_t)dst % (uint32_t)(uint16_t)src; | |
48425 | if (newv > 0xffff) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else | |
48426 | { | |
48427 | CLEAR_CZNV; | |
48428 | SET_ZFLG (((int16_t)(newv)) == 0); | |
48429 | SET_NFLG (((int16_t)(newv)) < 0); | |
48430 | newv = (newv & 0xffff) | ((uint32_t)rem << 16); | |
48431 | m68k_dreg(regs, dstreg) = (newv); | |
48432 | } | |
48433 | } | |
48434 | retcycles = getDivu68kCycles((uint32_t)dst, (uint16_t)src); | |
48435 | }}}endlabel2683: ; | |
48436 | return (8+retcycles); | |
48437 | } | |
48438 | unsigned long CPUFUNC(op_8100_5)(uint32_t opcode) /* SBCD */ | |
48439 | { | |
48440 | uint32_t srcreg = (opcode & 7); | |
48441 | uint32_t dstreg = (opcode >> 9) & 7; | |
48442 | OpcodeFamily = 10; CurrentInstrCycles = 6; | |
48443 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
48444 | { int8_t dst = m68k_dreg(regs, dstreg); | |
48445 | { uint16_t newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG ? 1 : 0); | |
48446 | uint16_t newv_hi = (dst & 0xF0) - (src & 0xF0); | |
48447 | uint16_t newv, tmp_newv; | |
48448 | int bcd = 0; | |
48449 | newv = tmp_newv = newv_hi + newv_lo; | |
48450 | if (newv_lo & 0xF0) { newv -= 6; bcd = 6; }; | |
48451 | if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; } | |
48452 | SET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG ? 1 : 0)) & 0x300) > 0xFF); | |
48453 | COPY_CARRY; | |
48454 | SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); | |
48455 | SET_NFLG (((int8_t)(newv)) < 0); | |
48456 | SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0); | |
48457 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
48458 | }}}}m68k_incpc(2); | |
48459 | fill_prefetch_2 (); | |
48460 | return 6; | |
48461 | } | |
48462 | unsigned long CPUFUNC(op_8108_5)(uint32_t opcode) /* SBCD */ | |
48463 | { | |
48464 | uint32_t srcreg = (opcode & 7); | |
48465 | uint32_t dstreg = (opcode >> 9) & 7; | |
48466 | OpcodeFamily = 10; CurrentInstrCycles = 18; | |
48467 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
48468 | { int8_t src = m68k_read_memory_8(srca); | |
48469 | m68k_areg (regs, srcreg) = srca; | |
48470 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
48471 | { int8_t dst = m68k_read_memory_8(dsta); | |
48472 | m68k_areg (regs, dstreg) = dsta; | |
48473 | { uint16_t newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG ? 1 : 0); | |
48474 | uint16_t newv_hi = (dst & 0xF0) - (src & 0xF0); | |
48475 | uint16_t newv, tmp_newv; | |
48476 | int bcd = 0; | |
48477 | newv = tmp_newv = newv_hi + newv_lo; | |
48478 | if (newv_lo & 0xF0) { newv -= 6; bcd = 6; }; | |
48479 | if ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; } | |
48480 | SET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG ? 1 : 0)) & 0x300) > 0xFF); | |
48481 | COPY_CARRY; | |
48482 | SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); | |
48483 | SET_NFLG (((int8_t)(newv)) < 0); | |
48484 | SET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0); | |
48485 | m68k_incpc(2); | |
48486 | fill_prefetch_2 (); | |
48487 | m68k_write_memory_8(dsta,newv); | |
48488 | }}}}}}return 18; | |
48489 | } | |
48490 | unsigned long CPUFUNC(op_8110_5)(uint32_t opcode) /* OR */ | |
48491 | { | |
48492 | uint32_t srcreg = ((opcode >> 9) & 7); | |
48493 | uint32_t dstreg = opcode & 7; | |
48494 | OpcodeFamily = 1; CurrentInstrCycles = 12; | |
48495 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
48496 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
48497 | { int8_t dst = m68k_read_memory_8(dsta); | |
48498 | src |= dst; | |
48499 | CLEAR_CZNV; | |
48500 | SET_ZFLG (((int8_t)(src)) == 0); | |
48501 | SET_NFLG (((int8_t)(src)) < 0); | |
48502 | m68k_incpc(2); | |
48503 | fill_prefetch_2 (); | |
48504 | m68k_write_memory_8(dsta,src); | |
48505 | }}}}return 12; | |
48506 | } | |
48507 | unsigned long CPUFUNC(op_8118_5)(uint32_t opcode) /* OR */ | |
48508 | { | |
48509 | uint32_t srcreg = ((opcode >> 9) & 7); | |
48510 | uint32_t dstreg = opcode & 7; | |
48511 | OpcodeFamily = 1; CurrentInstrCycles = 12; | |
48512 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
48513 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
48514 | { int8_t dst = m68k_read_memory_8(dsta); | |
48515 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
48516 | src |= dst; | |
48517 | CLEAR_CZNV; | |
48518 | SET_ZFLG (((int8_t)(src)) == 0); | |
48519 | SET_NFLG (((int8_t)(src)) < 0); | |
48520 | m68k_incpc(2); | |
48521 | fill_prefetch_2 (); | |
48522 | m68k_write_memory_8(dsta,src); | |
48523 | }}}}return 12; | |
48524 | } | |
48525 | unsigned long CPUFUNC(op_8120_5)(uint32_t opcode) /* OR */ | |
48526 | { | |
48527 | uint32_t srcreg = ((opcode >> 9) & 7); | |
48528 | uint32_t dstreg = opcode & 7; | |
48529 | OpcodeFamily = 1; CurrentInstrCycles = 14; | |
48530 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
48531 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
48532 | { int8_t dst = m68k_read_memory_8(dsta); | |
48533 | m68k_areg (regs, dstreg) = dsta; | |
48534 | src |= dst; | |
48535 | CLEAR_CZNV; | |
48536 | SET_ZFLG (((int8_t)(src)) == 0); | |
48537 | SET_NFLG (((int8_t)(src)) < 0); | |
48538 | m68k_incpc(2); | |
48539 | fill_prefetch_2 (); | |
48540 | m68k_write_memory_8(dsta,src); | |
48541 | }}}}return 14; | |
48542 | } | |
48543 | unsigned long CPUFUNC(op_8128_5)(uint32_t opcode) /* OR */ | |
48544 | { | |
48545 | uint32_t srcreg = ((opcode >> 9) & 7); | |
48546 | uint32_t dstreg = opcode & 7; | |
48547 | OpcodeFamily = 1; CurrentInstrCycles = 16; | |
48548 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
48549 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
48550 | { int8_t dst = m68k_read_memory_8(dsta); | |
48551 | src |= dst; | |
48552 | CLEAR_CZNV; | |
48553 | SET_ZFLG (((int8_t)(src)) == 0); | |
48554 | SET_NFLG (((int8_t)(src)) < 0); | |
48555 | m68k_incpc(4); | |
48556 | fill_prefetch_0 (); | |
48557 | m68k_write_memory_8(dsta,src); | |
48558 | }}}}return 16; | |
48559 | } | |
48560 | unsigned long CPUFUNC(op_8130_5)(uint32_t opcode) /* OR */ | |
48561 | { | |
48562 | uint32_t srcreg = ((opcode >> 9) & 7); | |
48563 | uint32_t dstreg = opcode & 7; | |
48564 | OpcodeFamily = 1; CurrentInstrCycles = 18; | |
48565 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
48566 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); | |
48567 | BusCyclePenalty += 2; | |
48568 | { int8_t dst = m68k_read_memory_8(dsta); | |
48569 | src |= dst; | |
48570 | CLEAR_CZNV; | |
48571 | SET_ZFLG (((int8_t)(src)) == 0); | |
48572 | SET_NFLG (((int8_t)(src)) < 0); | |
48573 | m68k_incpc(4); | |
48574 | fill_prefetch_0 (); | |
48575 | m68k_write_memory_8(dsta,src); | |
48576 | }}}}return 18; | |
48577 | } | |
48578 | unsigned long CPUFUNC(op_8138_5)(uint32_t opcode) /* OR */ | |
48579 | { | |
48580 | uint32_t srcreg = ((opcode >> 9) & 7); | |
48581 | OpcodeFamily = 1; CurrentInstrCycles = 16; | |
48582 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
48583 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); | |
48584 | { int8_t dst = m68k_read_memory_8(dsta); | |
48585 | src |= dst; | |
48586 | CLEAR_CZNV; | |
48587 | SET_ZFLG (((int8_t)(src)) == 0); | |
48588 | SET_NFLG (((int8_t)(src)) < 0); | |
48589 | m68k_incpc(4); | |
48590 | fill_prefetch_0 (); | |
48591 | m68k_write_memory_8(dsta,src); | |
48592 | }}}}return 16; | |
48593 | } | |
48594 | unsigned long CPUFUNC(op_8139_5)(uint32_t opcode) /* OR */ | |
48595 | { | |
48596 | uint32_t srcreg = ((opcode >> 9) & 7); | |
48597 | OpcodeFamily = 1; CurrentInstrCycles = 20; | |
48598 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
48599 | { uint32_t dsta = get_ilong_prefetch(2); | |
48600 | { int8_t dst = m68k_read_memory_8(dsta); | |
48601 | src |= dst; | |
48602 | CLEAR_CZNV; | |
48603 | SET_ZFLG (((int8_t)(src)) == 0); | |
48604 | SET_NFLG (((int8_t)(src)) < 0); | |
48605 | m68k_incpc(6); | |
48606 | fill_prefetch_0 (); | |
48607 | m68k_write_memory_8(dsta,src); | |
48608 | }}}}return 20; | |
48609 | } | |
48610 | unsigned long CPUFUNC(op_8150_5)(uint32_t opcode) /* OR */ | |
48611 | { | |
48612 | uint32_t srcreg = ((opcode >> 9) & 7); | |
48613 | uint32_t dstreg = opcode & 7; | |
48614 | OpcodeFamily = 1; CurrentInstrCycles = 12; | |
48615 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
48616 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
48617 | if ((dsta & 1) != 0) { | |
48618 | last_fault_for_exception_3 = dsta; | |
48619 | last_op_for_exception_3 = opcode; | |
48620 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
48621 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
48622 | goto endlabel2693; | |
48623 | } | |
48624 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
48625 | src |= dst; | |
48626 | CLEAR_CZNV; | |
48627 | SET_ZFLG (((int16_t)(src)) == 0); | |
48628 | SET_NFLG (((int16_t)(src)) < 0); | |
48629 | m68k_incpc(2); | |
48630 | fill_prefetch_2 (); | |
48631 | m68k_write_memory_16(dsta,src); | |
48632 | }}}}}endlabel2693: ; | |
48633 | return 12; | |
48634 | } | |
48635 | unsigned long CPUFUNC(op_8158_5)(uint32_t opcode) /* OR */ | |
48636 | { | |
48637 | uint32_t srcreg = ((opcode >> 9) & 7); | |
48638 | uint32_t dstreg = opcode & 7; | |
48639 | OpcodeFamily = 1; CurrentInstrCycles = 12; | |
48640 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
48641 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
48642 | if ((dsta & 1) != 0) { | |
48643 | last_fault_for_exception_3 = dsta; | |
48644 | last_op_for_exception_3 = opcode; | |
48645 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
48646 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
48647 | goto endlabel2694; | |
48648 | } | |
48649 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
48650 | m68k_areg(regs, dstreg) += 2; | |
48651 | src |= dst; | |
48652 | CLEAR_CZNV; | |
48653 | SET_ZFLG (((int16_t)(src)) == 0); | |
48654 | SET_NFLG (((int16_t)(src)) < 0); | |
48655 | m68k_incpc(2); | |
48656 | fill_prefetch_2 (); | |
48657 | m68k_write_memory_16(dsta,src); | |
48658 | }}}}}endlabel2694: ; | |
48659 | return 12; | |
48660 | } | |
48661 | unsigned long CPUFUNC(op_8160_5)(uint32_t opcode) /* OR */ | |
48662 | { | |
48663 | uint32_t srcreg = ((opcode >> 9) & 7); | |
48664 | uint32_t dstreg = opcode & 7; | |
48665 | OpcodeFamily = 1; CurrentInstrCycles = 14; | |
48666 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
48667 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
48668 | if ((dsta & 1) != 0) { | |
48669 | last_fault_for_exception_3 = dsta; | |
48670 | last_op_for_exception_3 = opcode; | |
48671 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
48672 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
48673 | goto endlabel2695; | |
48674 | } | |
48675 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
48676 | m68k_areg (regs, dstreg) = dsta; | |
48677 | src |= dst; | |
48678 | CLEAR_CZNV; | |
48679 | SET_ZFLG (((int16_t)(src)) == 0); | |
48680 | SET_NFLG (((int16_t)(src)) < 0); | |
48681 | m68k_incpc(2); | |
48682 | fill_prefetch_2 (); | |
48683 | m68k_write_memory_16(dsta,src); | |
48684 | }}}}}endlabel2695: ; | |
48685 | return 14; | |
48686 | } | |
48687 | unsigned long CPUFUNC(op_8168_5)(uint32_t opcode) /* OR */ | |
48688 | { | |
48689 | uint32_t srcreg = ((opcode >> 9) & 7); | |
48690 | uint32_t dstreg = opcode & 7; | |
48691 | OpcodeFamily = 1; CurrentInstrCycles = 16; | |
48692 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
48693 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
48694 | if ((dsta & 1) != 0) { | |
48695 | last_fault_for_exception_3 = dsta; | |
48696 | last_op_for_exception_3 = opcode; | |
48697 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
48698 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
48699 | goto endlabel2696; | |
48700 | } | |
48701 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
48702 | src |= dst; | |
48703 | CLEAR_CZNV; | |
48704 | SET_ZFLG (((int16_t)(src)) == 0); | |
48705 | SET_NFLG (((int16_t)(src)) < 0); | |
48706 | m68k_incpc(4); | |
48707 | fill_prefetch_0 (); | |
48708 | m68k_write_memory_16(dsta,src); | |
48709 | }}}}}endlabel2696: ; | |
48710 | return 16; | |
48711 | } | |
48712 | unsigned long CPUFUNC(op_8170_5)(uint32_t opcode) /* OR */ | |
48713 | { | |
48714 | uint32_t srcreg = ((opcode >> 9) & 7); | |
48715 | uint32_t dstreg = opcode & 7; | |
48716 | OpcodeFamily = 1; CurrentInstrCycles = 18; | |
48717 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
48718 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); | |
48719 | BusCyclePenalty += 2; | |
48720 | if ((dsta & 1) != 0) { | |
48721 | last_fault_for_exception_3 = dsta; | |
48722 | last_op_for_exception_3 = opcode; | |
48723 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
48724 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
48725 | goto endlabel2697; | |
48726 | } | |
48727 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
48728 | src |= dst; | |
48729 | CLEAR_CZNV; | |
48730 | SET_ZFLG (((int16_t)(src)) == 0); | |
48731 | SET_NFLG (((int16_t)(src)) < 0); | |
48732 | m68k_incpc(4); | |
48733 | fill_prefetch_0 (); | |
48734 | m68k_write_memory_16(dsta,src); | |
48735 | }}}}}endlabel2697: ; | |
48736 | return 18; | |
48737 | } | |
48738 | unsigned long CPUFUNC(op_8178_5)(uint32_t opcode) /* OR */ | |
48739 | { | |
48740 | uint32_t srcreg = ((opcode >> 9) & 7); | |
48741 | OpcodeFamily = 1; CurrentInstrCycles = 16; | |
48742 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
48743 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); | |
48744 | if ((dsta & 1) != 0) { | |
48745 | last_fault_for_exception_3 = dsta; | |
48746 | last_op_for_exception_3 = opcode; | |
48747 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
48748 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
48749 | goto endlabel2698; | |
48750 | } | |
48751 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
48752 | src |= dst; | |
48753 | CLEAR_CZNV; | |
48754 | SET_ZFLG (((int16_t)(src)) == 0); | |
48755 | SET_NFLG (((int16_t)(src)) < 0); | |
48756 | m68k_incpc(4); | |
48757 | fill_prefetch_0 (); | |
48758 | m68k_write_memory_16(dsta,src); | |
48759 | }}}}}endlabel2698: ; | |
48760 | return 16; | |
48761 | } | |
48762 | unsigned long CPUFUNC(op_8179_5)(uint32_t opcode) /* OR */ | |
48763 | { | |
48764 | uint32_t srcreg = ((opcode >> 9) & 7); | |
48765 | OpcodeFamily = 1; CurrentInstrCycles = 20; | |
48766 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
48767 | { uint32_t dsta = get_ilong_prefetch(2); | |
48768 | if ((dsta & 1) != 0) { | |
48769 | last_fault_for_exception_3 = dsta; | |
48770 | last_op_for_exception_3 = opcode; | |
48771 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
48772 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
48773 | goto endlabel2699; | |
48774 | } | |
48775 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
48776 | src |= dst; | |
48777 | CLEAR_CZNV; | |
48778 | SET_ZFLG (((int16_t)(src)) == 0); | |
48779 | SET_NFLG (((int16_t)(src)) < 0); | |
48780 | m68k_incpc(6); | |
48781 | fill_prefetch_0 (); | |
48782 | m68k_write_memory_16(dsta,src); | |
48783 | }}}}}endlabel2699: ; | |
48784 | return 20; | |
48785 | } | |
48786 | unsigned long CPUFUNC(op_8190_5)(uint32_t opcode) /* OR */ | |
48787 | { | |
48788 | uint32_t srcreg = ((opcode >> 9) & 7); | |
48789 | uint32_t dstreg = opcode & 7; | |
48790 | OpcodeFamily = 1; CurrentInstrCycles = 20; | |
48791 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
48792 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
48793 | if ((dsta & 1) != 0) { | |
48794 | last_fault_for_exception_3 = dsta; | |
48795 | last_op_for_exception_3 = opcode; | |
48796 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
48797 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
48798 | goto endlabel2700; | |
48799 | } | |
48800 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
48801 | src |= dst; | |
48802 | CLEAR_CZNV; | |
48803 | SET_ZFLG (((int32_t)(src)) == 0); | |
48804 | SET_NFLG (((int32_t)(src)) < 0); | |
48805 | m68k_incpc(2); | |
48806 | fill_prefetch_2 (); | |
48807 | m68k_write_memory_32(dsta,src); | |
48808 | }}}}}endlabel2700: ; | |
48809 | return 20; | |
48810 | } | |
48811 | unsigned long CPUFUNC(op_8198_5)(uint32_t opcode) /* OR */ | |
48812 | { | |
48813 | uint32_t srcreg = ((opcode >> 9) & 7); | |
48814 | uint32_t dstreg = opcode & 7; | |
48815 | OpcodeFamily = 1; CurrentInstrCycles = 20; | |
48816 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
48817 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
48818 | if ((dsta & 1) != 0) { | |
48819 | last_fault_for_exception_3 = dsta; | |
48820 | last_op_for_exception_3 = opcode; | |
48821 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
48822 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
48823 | goto endlabel2701; | |
48824 | } | |
48825 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
48826 | m68k_areg(regs, dstreg) += 4; | |
48827 | src |= dst; | |
48828 | CLEAR_CZNV; | |
48829 | SET_ZFLG (((int32_t)(src)) == 0); | |
48830 | SET_NFLG (((int32_t)(src)) < 0); | |
48831 | m68k_incpc(2); | |
48832 | fill_prefetch_2 (); | |
48833 | m68k_write_memory_32(dsta,src); | |
48834 | }}}}}endlabel2701: ; | |
48835 | return 20; | |
48836 | } | |
48837 | unsigned long CPUFUNC(op_81a0_5)(uint32_t opcode) /* OR */ | |
48838 | { | |
48839 | uint32_t srcreg = ((opcode >> 9) & 7); | |
48840 | uint32_t dstreg = opcode & 7; | |
48841 | OpcodeFamily = 1; CurrentInstrCycles = 22; | |
48842 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
48843 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
48844 | if ((dsta & 1) != 0) { | |
48845 | last_fault_for_exception_3 = dsta; | |
48846 | last_op_for_exception_3 = opcode; | |
48847 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
48848 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
48849 | goto endlabel2702; | |
48850 | } | |
48851 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
48852 | m68k_areg (regs, dstreg) = dsta; | |
48853 | src |= dst; | |
48854 | CLEAR_CZNV; | |
48855 | SET_ZFLG (((int32_t)(src)) == 0); | |
48856 | SET_NFLG (((int32_t)(src)) < 0); | |
48857 | m68k_incpc(2); | |
48858 | fill_prefetch_2 (); | |
48859 | m68k_write_memory_32(dsta,src); | |
48860 | }}}}}endlabel2702: ; | |
48861 | return 22; | |
48862 | } | |
48863 | unsigned long CPUFUNC(op_81a8_5)(uint32_t opcode) /* OR */ | |
48864 | { | |
48865 | uint32_t srcreg = ((opcode >> 9) & 7); | |
48866 | uint32_t dstreg = opcode & 7; | |
48867 | OpcodeFamily = 1; CurrentInstrCycles = 24; | |
48868 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
48869 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
48870 | if ((dsta & 1) != 0) { | |
48871 | last_fault_for_exception_3 = dsta; | |
48872 | last_op_for_exception_3 = opcode; | |
48873 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
48874 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
48875 | goto endlabel2703; | |
48876 | } | |
48877 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
48878 | src |= dst; | |
48879 | CLEAR_CZNV; | |
48880 | SET_ZFLG (((int32_t)(src)) == 0); | |
48881 | SET_NFLG (((int32_t)(src)) < 0); | |
48882 | m68k_incpc(4); | |
48883 | fill_prefetch_0 (); | |
48884 | m68k_write_memory_32(dsta,src); | |
48885 | }}}}}endlabel2703: ; | |
48886 | return 24; | |
48887 | } | |
48888 | unsigned long CPUFUNC(op_81b0_5)(uint32_t opcode) /* OR */ | |
48889 | { | |
48890 | uint32_t srcreg = ((opcode >> 9) & 7); | |
48891 | uint32_t dstreg = opcode & 7; | |
48892 | OpcodeFamily = 1; CurrentInstrCycles = 26; | |
48893 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
48894 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); | |
48895 | BusCyclePenalty += 2; | |
48896 | if ((dsta & 1) != 0) { | |
48897 | last_fault_for_exception_3 = dsta; | |
48898 | last_op_for_exception_3 = opcode; | |
48899 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
48900 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
48901 | goto endlabel2704; | |
48902 | } | |
48903 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
48904 | src |= dst; | |
48905 | CLEAR_CZNV; | |
48906 | SET_ZFLG (((int32_t)(src)) == 0); | |
48907 | SET_NFLG (((int32_t)(src)) < 0); | |
48908 | m68k_incpc(4); | |
48909 | fill_prefetch_0 (); | |
48910 | m68k_write_memory_32(dsta,src); | |
48911 | }}}}}endlabel2704: ; | |
48912 | return 26; | |
48913 | } | |
48914 | unsigned long CPUFUNC(op_81b8_5)(uint32_t opcode) /* OR */ | |
48915 | { | |
48916 | uint32_t srcreg = ((opcode >> 9) & 7); | |
48917 | OpcodeFamily = 1; CurrentInstrCycles = 24; | |
48918 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
48919 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); | |
48920 | if ((dsta & 1) != 0) { | |
48921 | last_fault_for_exception_3 = dsta; | |
48922 | last_op_for_exception_3 = opcode; | |
48923 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
48924 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
48925 | goto endlabel2705; | |
48926 | } | |
48927 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
48928 | src |= dst; | |
48929 | CLEAR_CZNV; | |
48930 | SET_ZFLG (((int32_t)(src)) == 0); | |
48931 | SET_NFLG (((int32_t)(src)) < 0); | |
48932 | m68k_incpc(4); | |
48933 | fill_prefetch_0 (); | |
48934 | m68k_write_memory_32(dsta,src); | |
48935 | }}}}}endlabel2705: ; | |
48936 | return 24; | |
48937 | } | |
48938 | unsigned long CPUFUNC(op_81b9_5)(uint32_t opcode) /* OR */ | |
48939 | { | |
48940 | uint32_t srcreg = ((opcode >> 9) & 7); | |
48941 | OpcodeFamily = 1; CurrentInstrCycles = 28; | |
48942 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
48943 | { uint32_t dsta = get_ilong_prefetch(2); | |
48944 | if ((dsta & 1) != 0) { | |
48945 | last_fault_for_exception_3 = dsta; | |
48946 | last_op_for_exception_3 = opcode; | |
48947 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
48948 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
48949 | goto endlabel2706; | |
48950 | } | |
48951 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
48952 | src |= dst; | |
48953 | CLEAR_CZNV; | |
48954 | SET_ZFLG (((int32_t)(src)) == 0); | |
48955 | SET_NFLG (((int32_t)(src)) < 0); | |
48956 | m68k_incpc(6); | |
48957 | fill_prefetch_0 (); | |
48958 | m68k_write_memory_32(dsta,src); | |
48959 | }}}}}endlabel2706: ; | |
48960 | return 28; | |
48961 | } | |
48962 | unsigned long CPUFUNC(op_81c0_5)(uint32_t opcode) /* DIVS */ | |
48963 | { | |
48964 | uint32_t srcreg = (opcode & 7); | |
48965 | uint32_t dstreg = (opcode >> 9) & 7; | |
48966 | unsigned int retcycles = 0; | |
48967 | OpcodeFamily = 61; CurrentInstrCycles = 4; | |
48968 | { uint32_t oldpc = m68k_getpc(); | |
48969 | { int16_t src = m68k_dreg(regs, srcreg); | |
48970 | { int32_t dst = m68k_dreg(regs, dstreg); | |
48971 | m68k_incpc(2); | |
48972 | fill_prefetch_2 (); | |
48973 | if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel2707; } else { | |
48974 | int32_t newv = (int32_t)dst / (int32_t)(int16_t)src; | |
48975 | uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src; | |
48976 | if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else | |
48977 | { | |
48978 | if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem; | |
48979 | CLEAR_CZNV; | |
48980 | SET_ZFLG (((int16_t)(newv)) == 0); | |
48981 | SET_NFLG (((int16_t)(newv)) < 0); | |
48982 | newv = (newv & 0xffff) | ((uint32_t)rem << 16); | |
48983 | m68k_dreg(regs, dstreg) = (newv); | |
48984 | } | |
48985 | } | |
48986 | retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src); | |
48987 | }}}endlabel2707: ; | |
48988 | return (4+retcycles); | |
48989 | } | |
48990 | unsigned long CPUFUNC(op_81d0_5)(uint32_t opcode) /* DIVS */ | |
48991 | { | |
48992 | uint32_t srcreg = (opcode & 7); | |
48993 | uint32_t dstreg = (opcode >> 9) & 7; | |
48994 | unsigned int retcycles = 0; | |
48995 | OpcodeFamily = 61; CurrentInstrCycles = 8; | |
48996 | { uint32_t oldpc = m68k_getpc(); | |
48997 | { uint32_t srca = m68k_areg(regs, srcreg); | |
48998 | if ((srca & 1) != 0) { | |
48999 | last_fault_for_exception_3 = srca; | |
49000 | last_op_for_exception_3 = opcode; | |
49001 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
49002 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
49003 | goto endlabel2708; | |
49004 | } | |
49005 | {{ int16_t src = m68k_read_memory_16(srca); | |
49006 | { int32_t dst = m68k_dreg(regs, dstreg); | |
49007 | m68k_incpc(2); | |
49008 | fill_prefetch_2 (); | |
49009 | if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel2708; } else { | |
49010 | int32_t newv = (int32_t)dst / (int32_t)(int16_t)src; | |
49011 | uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src; | |
49012 | if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else | |
49013 | { | |
49014 | if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem; | |
49015 | CLEAR_CZNV; | |
49016 | SET_ZFLG (((int16_t)(newv)) == 0); | |
49017 | SET_NFLG (((int16_t)(newv)) < 0); | |
49018 | newv = (newv & 0xffff) | ((uint32_t)rem << 16); | |
49019 | m68k_dreg(regs, dstreg) = (newv); | |
49020 | } | |
49021 | } | |
49022 | retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src); | |
49023 | }}}}}endlabel2708: ; | |
49024 | return (8+retcycles); | |
49025 | } | |
49026 | unsigned long CPUFUNC(op_81d8_5)(uint32_t opcode) /* DIVS */ | |
49027 | { | |
49028 | uint32_t srcreg = (opcode & 7); | |
49029 | uint32_t dstreg = (opcode >> 9) & 7; | |
49030 | unsigned int retcycles = 0; | |
49031 | OpcodeFamily = 61; CurrentInstrCycles = 8; | |
49032 | { uint32_t oldpc = m68k_getpc(); | |
49033 | { uint32_t srca = m68k_areg(regs, srcreg); | |
49034 | if ((srca & 1) != 0) { | |
49035 | last_fault_for_exception_3 = srca; | |
49036 | last_op_for_exception_3 = opcode; | |
49037 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
49038 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
49039 | goto endlabel2709; | |
49040 | } | |
49041 | {{ int16_t src = m68k_read_memory_16(srca); | |
49042 | m68k_areg(regs, srcreg) += 2; | |
49043 | { int32_t dst = m68k_dreg(regs, dstreg); | |
49044 | m68k_incpc(2); | |
49045 | fill_prefetch_2 (); | |
49046 | if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel2709; } else { | |
49047 | int32_t newv = (int32_t)dst / (int32_t)(int16_t)src; | |
49048 | uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src; | |
49049 | if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else | |
49050 | { | |
49051 | if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem; | |
49052 | CLEAR_CZNV; | |
49053 | SET_ZFLG (((int16_t)(newv)) == 0); | |
49054 | SET_NFLG (((int16_t)(newv)) < 0); | |
49055 | newv = (newv & 0xffff) | ((uint32_t)rem << 16); | |
49056 | m68k_dreg(regs, dstreg) = (newv); | |
49057 | } | |
49058 | } | |
49059 | retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src); | |
49060 | }}}}}endlabel2709: ; | |
49061 | return (8+retcycles); | |
49062 | } | |
49063 | unsigned long CPUFUNC(op_81e0_5)(uint32_t opcode) /* DIVS */ | |
49064 | { | |
49065 | uint32_t srcreg = (opcode & 7); | |
49066 | uint32_t dstreg = (opcode >> 9) & 7; | |
49067 | unsigned int retcycles = 0; | |
49068 | OpcodeFamily = 61; CurrentInstrCycles = 10; | |
49069 | { uint32_t oldpc = m68k_getpc(); | |
49070 | { uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
49071 | if ((srca & 1) != 0) { | |
49072 | last_fault_for_exception_3 = srca; | |
49073 | last_op_for_exception_3 = opcode; | |
49074 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
49075 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
49076 | goto endlabel2710; | |
49077 | } | |
49078 | {{ int16_t src = m68k_read_memory_16(srca); | |
49079 | m68k_areg (regs, srcreg) = srca; | |
49080 | { int32_t dst = m68k_dreg(regs, dstreg); | |
49081 | m68k_incpc(2); | |
49082 | fill_prefetch_2 (); | |
49083 | if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel2710; } else { | |
49084 | int32_t newv = (int32_t)dst / (int32_t)(int16_t)src; | |
49085 | uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src; | |
49086 | if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else | |
49087 | { | |
49088 | if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem; | |
49089 | CLEAR_CZNV; | |
49090 | SET_ZFLG (((int16_t)(newv)) == 0); | |
49091 | SET_NFLG (((int16_t)(newv)) < 0); | |
49092 | newv = (newv & 0xffff) | ((uint32_t)rem << 16); | |
49093 | m68k_dreg(regs, dstreg) = (newv); | |
49094 | } | |
49095 | } | |
49096 | retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src); | |
49097 | }}}}}endlabel2710: ; | |
49098 | return (10+retcycles); | |
49099 | } | |
49100 | unsigned long CPUFUNC(op_81e8_5)(uint32_t opcode) /* DIVS */ | |
49101 | { | |
49102 | uint32_t srcreg = (opcode & 7); | |
49103 | uint32_t dstreg = (opcode >> 9) & 7; | |
49104 | unsigned int retcycles = 0; | |
49105 | OpcodeFamily = 61; CurrentInstrCycles = 12; | |
49106 | { uint32_t oldpc = m68k_getpc(); | |
49107 | { uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
49108 | if ((srca & 1) != 0) { | |
49109 | last_fault_for_exception_3 = srca; | |
49110 | last_op_for_exception_3 = opcode; | |
49111 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
49112 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
49113 | goto endlabel2711; | |
49114 | } | |
49115 | {{ int16_t src = m68k_read_memory_16(srca); | |
49116 | { int32_t dst = m68k_dreg(regs, dstreg); | |
49117 | m68k_incpc(4); | |
49118 | fill_prefetch_0 (); | |
49119 | if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel2711; } else { | |
49120 | int32_t newv = (int32_t)dst / (int32_t)(int16_t)src; | |
49121 | uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src; | |
49122 | if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else | |
49123 | { | |
49124 | if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem; | |
49125 | CLEAR_CZNV; | |
49126 | SET_ZFLG (((int16_t)(newv)) == 0); | |
49127 | SET_NFLG (((int16_t)(newv)) < 0); | |
49128 | newv = (newv & 0xffff) | ((uint32_t)rem << 16); | |
49129 | m68k_dreg(regs, dstreg) = (newv); | |
49130 | } | |
49131 | } | |
49132 | retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src); | |
49133 | }}}}}endlabel2711: ; | |
49134 | return (12+retcycles); | |
49135 | } | |
49136 | unsigned long CPUFUNC(op_81f0_5)(uint32_t opcode) /* DIVS */ | |
49137 | { | |
49138 | uint32_t srcreg = (opcode & 7); | |
49139 | uint32_t dstreg = (opcode >> 9) & 7; | |
49140 | unsigned int retcycles = 0; | |
49141 | OpcodeFamily = 61; CurrentInstrCycles = 14; | |
49142 | { uint32_t oldpc = m68k_getpc(); | |
49143 | { uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
49144 | BusCyclePenalty += 2; | |
49145 | if ((srca & 1) != 0) { | |
49146 | last_fault_for_exception_3 = srca; | |
49147 | last_op_for_exception_3 = opcode; | |
49148 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
49149 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
49150 | goto endlabel2712; | |
49151 | } | |
49152 | {{ int16_t src = m68k_read_memory_16(srca); | |
49153 | { int32_t dst = m68k_dreg(regs, dstreg); | |
49154 | m68k_incpc(4); | |
49155 | fill_prefetch_0 (); | |
49156 | if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel2712; } else { | |
49157 | int32_t newv = (int32_t)dst / (int32_t)(int16_t)src; | |
49158 | uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src; | |
49159 | if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else | |
49160 | { | |
49161 | if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem; | |
49162 | CLEAR_CZNV; | |
49163 | SET_ZFLG (((int16_t)(newv)) == 0); | |
49164 | SET_NFLG (((int16_t)(newv)) < 0); | |
49165 | newv = (newv & 0xffff) | ((uint32_t)rem << 16); | |
49166 | m68k_dreg(regs, dstreg) = (newv); | |
49167 | } | |
49168 | } | |
49169 | retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src); | |
49170 | }}}}}endlabel2712: ; | |
49171 | return (14+retcycles); | |
49172 | } | |
49173 | unsigned long CPUFUNC(op_81f8_5)(uint32_t opcode) /* DIVS */ | |
49174 | { | |
49175 | uint32_t dstreg = (opcode >> 9) & 7; | |
49176 | unsigned int retcycles = 0; | |
49177 | OpcodeFamily = 61; CurrentInstrCycles = 12; | |
49178 | { uint32_t oldpc = m68k_getpc(); | |
49179 | { uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
49180 | if ((srca & 1) != 0) { | |
49181 | last_fault_for_exception_3 = srca; | |
49182 | last_op_for_exception_3 = opcode; | |
49183 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
49184 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
49185 | goto endlabel2713; | |
49186 | } | |
49187 | {{ int16_t src = m68k_read_memory_16(srca); | |
49188 | { int32_t dst = m68k_dreg(regs, dstreg); | |
49189 | m68k_incpc(4); | |
49190 | fill_prefetch_0 (); | |
49191 | if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel2713; } else { | |
49192 | int32_t newv = (int32_t)dst / (int32_t)(int16_t)src; | |
49193 | uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src; | |
49194 | if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else | |
49195 | { | |
49196 | if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem; | |
49197 | CLEAR_CZNV; | |
49198 | SET_ZFLG (((int16_t)(newv)) == 0); | |
49199 | SET_NFLG (((int16_t)(newv)) < 0); | |
49200 | newv = (newv & 0xffff) | ((uint32_t)rem << 16); | |
49201 | m68k_dreg(regs, dstreg) = (newv); | |
49202 | } | |
49203 | } | |
49204 | retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src); | |
49205 | }}}}}endlabel2713: ; | |
49206 | return (12+retcycles); | |
49207 | } | |
49208 | unsigned long CPUFUNC(op_81f9_5)(uint32_t opcode) /* DIVS */ | |
49209 | { | |
49210 | uint32_t dstreg = (opcode >> 9) & 7; | |
49211 | unsigned int retcycles = 0; | |
49212 | OpcodeFamily = 61; CurrentInstrCycles = 16; | |
49213 | { uint32_t oldpc = m68k_getpc(); | |
49214 | { uint32_t srca = get_ilong_prefetch(2); | |
49215 | if ((srca & 1) != 0) { | |
49216 | last_fault_for_exception_3 = srca; | |
49217 | last_op_for_exception_3 = opcode; | |
49218 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
49219 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
49220 | goto endlabel2714; | |
49221 | } | |
49222 | {{ int16_t src = m68k_read_memory_16(srca); | |
49223 | { int32_t dst = m68k_dreg(regs, dstreg); | |
49224 | m68k_incpc(6); | |
49225 | fill_prefetch_0 (); | |
49226 | if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel2714; } else { | |
49227 | int32_t newv = (int32_t)dst / (int32_t)(int16_t)src; | |
49228 | uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src; | |
49229 | if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else | |
49230 | { | |
49231 | if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem; | |
49232 | CLEAR_CZNV; | |
49233 | SET_ZFLG (((int16_t)(newv)) == 0); | |
49234 | SET_NFLG (((int16_t)(newv)) < 0); | |
49235 | newv = (newv & 0xffff) | ((uint32_t)rem << 16); | |
49236 | m68k_dreg(regs, dstreg) = (newv); | |
49237 | } | |
49238 | } | |
49239 | retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src); | |
49240 | }}}}}endlabel2714: ; | |
49241 | return (16+retcycles); | |
49242 | } | |
49243 | unsigned long CPUFUNC(op_81fa_5)(uint32_t opcode) /* DIVS */ | |
49244 | { | |
49245 | uint32_t dstreg = (opcode >> 9) & 7; | |
49246 | unsigned int retcycles = 0; | |
49247 | OpcodeFamily = 61; CurrentInstrCycles = 12; | |
49248 | { uint32_t oldpc = m68k_getpc(); | |
49249 | { uint32_t srca = m68k_getpc () + 2; | |
49250 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
49251 | if ((srca & 1) != 0) { | |
49252 | last_fault_for_exception_3 = srca; | |
49253 | last_op_for_exception_3 = opcode; | |
49254 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
49255 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
49256 | goto endlabel2715; | |
49257 | } | |
49258 | {{ int16_t src = m68k_read_memory_16(srca); | |
49259 | { int32_t dst = m68k_dreg(regs, dstreg); | |
49260 | m68k_incpc(4); | |
49261 | fill_prefetch_0 (); | |
49262 | if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel2715; } else { | |
49263 | int32_t newv = (int32_t)dst / (int32_t)(int16_t)src; | |
49264 | uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src; | |
49265 | if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else | |
49266 | { | |
49267 | if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem; | |
49268 | CLEAR_CZNV; | |
49269 | SET_ZFLG (((int16_t)(newv)) == 0); | |
49270 | SET_NFLG (((int16_t)(newv)) < 0); | |
49271 | newv = (newv & 0xffff) | ((uint32_t)rem << 16); | |
49272 | m68k_dreg(regs, dstreg) = (newv); | |
49273 | } | |
49274 | } | |
49275 | retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src); | |
49276 | }}}}}endlabel2715: ; | |
49277 | return (12+retcycles); | |
49278 | } | |
49279 | unsigned long CPUFUNC(op_81fb_5)(uint32_t opcode) /* DIVS */ | |
49280 | { | |
49281 | uint32_t dstreg = (opcode >> 9) & 7; | |
49282 | unsigned int retcycles = 0; | |
49283 | OpcodeFamily = 61; CurrentInstrCycles = 14; | |
49284 | { uint32_t oldpc = m68k_getpc(); | |
49285 | { uint32_t tmppc = m68k_getpc() + 2; | |
49286 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
49287 | BusCyclePenalty += 2; | |
49288 | if ((srca & 1) != 0) { | |
49289 | last_fault_for_exception_3 = srca; | |
49290 | last_op_for_exception_3 = opcode; | |
49291 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
49292 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
49293 | goto endlabel2716; | |
49294 | } | |
49295 | {{ int16_t src = m68k_read_memory_16(srca); | |
49296 | { int32_t dst = m68k_dreg(regs, dstreg); | |
49297 | m68k_incpc(4); | |
49298 | fill_prefetch_0 (); | |
49299 | if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel2716; } else { | |
49300 | int32_t newv = (int32_t)dst / (int32_t)(int16_t)src; | |
49301 | uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src; | |
49302 | if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else | |
49303 | { | |
49304 | if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem; | |
49305 | CLEAR_CZNV; | |
49306 | SET_ZFLG (((int16_t)(newv)) == 0); | |
49307 | SET_NFLG (((int16_t)(newv)) < 0); | |
49308 | newv = (newv & 0xffff) | ((uint32_t)rem << 16); | |
49309 | m68k_dreg(regs, dstreg) = (newv); | |
49310 | } | |
49311 | } | |
49312 | retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src); | |
49313 | }}}}}endlabel2716: ; | |
49314 | return (14+retcycles); | |
49315 | } | |
49316 | unsigned long CPUFUNC(op_81fc_5)(uint32_t opcode) /* DIVS */ | |
49317 | { | |
49318 | uint32_t dstreg = (opcode >> 9) & 7; | |
49319 | unsigned int retcycles = 0; | |
49320 | OpcodeFamily = 61; CurrentInstrCycles = 8; | |
49321 | { uint32_t oldpc = m68k_getpc(); | |
49322 | { int16_t src = get_iword_prefetch(2); | |
49323 | { int32_t dst = m68k_dreg(regs, dstreg); | |
49324 | m68k_incpc(4); | |
49325 | fill_prefetch_0 (); | |
49326 | if (src == 0) { SET_VFLG (0); Exception(5,oldpc,M68000_EXC_SRC_CPU); goto endlabel2717; } else { | |
49327 | int32_t newv = (int32_t)dst / (int32_t)(int16_t)src; | |
49328 | uint16_t rem = (int32_t)dst % (int32_t)(int16_t)src; | |
49329 | if ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else | |
49330 | { | |
49331 | if (((int16_t)rem < 0) != ((int32_t)dst < 0)) rem = -rem; | |
49332 | CLEAR_CZNV; | |
49333 | SET_ZFLG (((int16_t)(newv)) == 0); | |
49334 | SET_NFLG (((int16_t)(newv)) < 0); | |
49335 | newv = (newv & 0xffff) | ((uint32_t)rem << 16); | |
49336 | m68k_dreg(regs, dstreg) = (newv); | |
49337 | } | |
49338 | } | |
49339 | retcycles = getDivs68kCycles((int32_t)dst, (int16_t)src); | |
49340 | }}}endlabel2717: ; | |
49341 | return (8+retcycles); | |
49342 | } | |
49343 | unsigned long CPUFUNC(op_9000_5)(uint32_t opcode) /* SUB */ | |
49344 | { | |
49345 | uint32_t srcreg = (opcode & 7); | |
49346 | uint32_t dstreg = (opcode >> 9) & 7; | |
49347 | OpcodeFamily = 7; CurrentInstrCycles = 4; | |
49348 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
49349 | { int8_t dst = m68k_dreg(regs, dstreg); | |
49350 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
49351 | { int flgs = ((int8_t)(src)) < 0; | |
49352 | int flgo = ((int8_t)(dst)) < 0; | |
49353 | int flgn = ((int8_t)(newv)) < 0; | |
49354 | SET_ZFLG (((int8_t)(newv)) == 0); | |
49355 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
49356 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
49357 | COPY_CARRY; | |
49358 | SET_NFLG (flgn != 0); | |
49359 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
49360 | }}}}}}m68k_incpc(2); | |
49361 | fill_prefetch_2 (); | |
49362 | return 4; | |
49363 | } | |
49364 | unsigned long CPUFUNC(op_9010_5)(uint32_t opcode) /* SUB */ | |
49365 | { | |
49366 | uint32_t srcreg = (opcode & 7); | |
49367 | uint32_t dstreg = (opcode >> 9) & 7; | |
49368 | OpcodeFamily = 7; CurrentInstrCycles = 8; | |
49369 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
49370 | { int8_t src = m68k_read_memory_8(srca); | |
49371 | { int8_t dst = m68k_dreg(regs, dstreg); | |
49372 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
49373 | { int flgs = ((int8_t)(src)) < 0; | |
49374 | int flgo = ((int8_t)(dst)) < 0; | |
49375 | int flgn = ((int8_t)(newv)) < 0; | |
49376 | SET_ZFLG (((int8_t)(newv)) == 0); | |
49377 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
49378 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
49379 | COPY_CARRY; | |
49380 | SET_NFLG (flgn != 0); | |
49381 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
49382 | }}}}}}}m68k_incpc(2); | |
49383 | fill_prefetch_2 (); | |
49384 | return 8; | |
49385 | } | |
49386 | unsigned long CPUFUNC(op_9018_5)(uint32_t opcode) /* SUB */ | |
49387 | { | |
49388 | uint32_t srcreg = (opcode & 7); | |
49389 | uint32_t dstreg = (opcode >> 9) & 7; | |
49390 | OpcodeFamily = 7; CurrentInstrCycles = 8; | |
49391 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
49392 | { int8_t src = m68k_read_memory_8(srca); | |
49393 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
49394 | { int8_t dst = m68k_dreg(regs, dstreg); | |
49395 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
49396 | { int flgs = ((int8_t)(src)) < 0; | |
49397 | int flgo = ((int8_t)(dst)) < 0; | |
49398 | int flgn = ((int8_t)(newv)) < 0; | |
49399 | SET_ZFLG (((int8_t)(newv)) == 0); | |
49400 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
49401 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
49402 | COPY_CARRY; | |
49403 | SET_NFLG (flgn != 0); | |
49404 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
49405 | }}}}}}}m68k_incpc(2); | |
49406 | fill_prefetch_2 (); | |
49407 | return 8; | |
49408 | } | |
49409 | unsigned long CPUFUNC(op_9020_5)(uint32_t opcode) /* SUB */ | |
49410 | { | |
49411 | uint32_t srcreg = (opcode & 7); | |
49412 | uint32_t dstreg = (opcode >> 9) & 7; | |
49413 | OpcodeFamily = 7; CurrentInstrCycles = 10; | |
49414 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
49415 | { int8_t src = m68k_read_memory_8(srca); | |
49416 | m68k_areg (regs, srcreg) = srca; | |
49417 | { int8_t dst = m68k_dreg(regs, dstreg); | |
49418 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
49419 | { int flgs = ((int8_t)(src)) < 0; | |
49420 | int flgo = ((int8_t)(dst)) < 0; | |
49421 | int flgn = ((int8_t)(newv)) < 0; | |
49422 | SET_ZFLG (((int8_t)(newv)) == 0); | |
49423 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
49424 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
49425 | COPY_CARRY; | |
49426 | SET_NFLG (flgn != 0); | |
49427 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
49428 | }}}}}}}m68k_incpc(2); | |
49429 | fill_prefetch_2 (); | |
49430 | return 10; | |
49431 | } | |
49432 | unsigned long CPUFUNC(op_9028_5)(uint32_t opcode) /* SUB */ | |
49433 | { | |
49434 | uint32_t srcreg = (opcode & 7); | |
49435 | uint32_t dstreg = (opcode >> 9) & 7; | |
49436 | OpcodeFamily = 7; CurrentInstrCycles = 12; | |
49437 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
49438 | { int8_t src = m68k_read_memory_8(srca); | |
49439 | { int8_t dst = m68k_dreg(regs, dstreg); | |
49440 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
49441 | { int flgs = ((int8_t)(src)) < 0; | |
49442 | int flgo = ((int8_t)(dst)) < 0; | |
49443 | int flgn = ((int8_t)(newv)) < 0; | |
49444 | SET_ZFLG (((int8_t)(newv)) == 0); | |
49445 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
49446 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
49447 | COPY_CARRY; | |
49448 | SET_NFLG (flgn != 0); | |
49449 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
49450 | }}}}}}}m68k_incpc(4); | |
49451 | fill_prefetch_0 (); | |
49452 | return 12; | |
49453 | } | |
49454 | unsigned long CPUFUNC(op_9030_5)(uint32_t opcode) /* SUB */ | |
49455 | { | |
49456 | uint32_t srcreg = (opcode & 7); | |
49457 | uint32_t dstreg = (opcode >> 9) & 7; | |
49458 | OpcodeFamily = 7; CurrentInstrCycles = 14; | |
49459 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
49460 | BusCyclePenalty += 2; | |
49461 | { int8_t src = m68k_read_memory_8(srca); | |
49462 | { int8_t dst = m68k_dreg(regs, dstreg); | |
49463 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
49464 | { int flgs = ((int8_t)(src)) < 0; | |
49465 | int flgo = ((int8_t)(dst)) < 0; | |
49466 | int flgn = ((int8_t)(newv)) < 0; | |
49467 | SET_ZFLG (((int8_t)(newv)) == 0); | |
49468 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
49469 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
49470 | COPY_CARRY; | |
49471 | SET_NFLG (flgn != 0); | |
49472 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
49473 | }}}}}}}m68k_incpc(4); | |
49474 | fill_prefetch_0 (); | |
49475 | return 14; | |
49476 | } | |
49477 | unsigned long CPUFUNC(op_9038_5)(uint32_t opcode) /* SUB */ | |
49478 | { | |
49479 | uint32_t dstreg = (opcode >> 9) & 7; | |
49480 | OpcodeFamily = 7; CurrentInstrCycles = 12; | |
49481 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
49482 | { int8_t src = m68k_read_memory_8(srca); | |
49483 | { int8_t dst = m68k_dreg(regs, dstreg); | |
49484 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
49485 | { int flgs = ((int8_t)(src)) < 0; | |
49486 | int flgo = ((int8_t)(dst)) < 0; | |
49487 | int flgn = ((int8_t)(newv)) < 0; | |
49488 | SET_ZFLG (((int8_t)(newv)) == 0); | |
49489 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
49490 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
49491 | COPY_CARRY; | |
49492 | SET_NFLG (flgn != 0); | |
49493 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
49494 | }}}}}}}m68k_incpc(4); | |
49495 | fill_prefetch_0 (); | |
49496 | return 12; | |
49497 | } | |
49498 | unsigned long CPUFUNC(op_9039_5)(uint32_t opcode) /* SUB */ | |
49499 | { | |
49500 | uint32_t dstreg = (opcode >> 9) & 7; | |
49501 | OpcodeFamily = 7; CurrentInstrCycles = 16; | |
49502 | {{ uint32_t srca = get_ilong_prefetch(2); | |
49503 | { int8_t src = m68k_read_memory_8(srca); | |
49504 | { int8_t dst = m68k_dreg(regs, dstreg); | |
49505 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
49506 | { int flgs = ((int8_t)(src)) < 0; | |
49507 | int flgo = ((int8_t)(dst)) < 0; | |
49508 | int flgn = ((int8_t)(newv)) < 0; | |
49509 | SET_ZFLG (((int8_t)(newv)) == 0); | |
49510 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
49511 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
49512 | COPY_CARRY; | |
49513 | SET_NFLG (flgn != 0); | |
49514 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
49515 | }}}}}}}m68k_incpc(6); | |
49516 | fill_prefetch_0 (); | |
49517 | return 16; | |
49518 | } | |
49519 | unsigned long CPUFUNC(op_903a_5)(uint32_t opcode) /* SUB */ | |
49520 | { | |
49521 | uint32_t dstreg = (opcode >> 9) & 7; | |
49522 | OpcodeFamily = 7; CurrentInstrCycles = 12; | |
49523 | {{ uint32_t srca = m68k_getpc () + 2; | |
49524 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
49525 | { int8_t src = m68k_read_memory_8(srca); | |
49526 | { int8_t dst = m68k_dreg(regs, dstreg); | |
49527 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
49528 | { int flgs = ((int8_t)(src)) < 0; | |
49529 | int flgo = ((int8_t)(dst)) < 0; | |
49530 | int flgn = ((int8_t)(newv)) < 0; | |
49531 | SET_ZFLG (((int8_t)(newv)) == 0); | |
49532 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
49533 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
49534 | COPY_CARRY; | |
49535 | SET_NFLG (flgn != 0); | |
49536 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
49537 | }}}}}}}m68k_incpc(4); | |
49538 | fill_prefetch_0 (); | |
49539 | return 12; | |
49540 | } | |
49541 | unsigned long CPUFUNC(op_903b_5)(uint32_t opcode) /* SUB */ | |
49542 | { | |
49543 | uint32_t dstreg = (opcode >> 9) & 7; | |
49544 | OpcodeFamily = 7; CurrentInstrCycles = 14; | |
49545 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
49546 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
49547 | BusCyclePenalty += 2; | |
49548 | { int8_t src = m68k_read_memory_8(srca); | |
49549 | { int8_t dst = m68k_dreg(regs, dstreg); | |
49550 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
49551 | { int flgs = ((int8_t)(src)) < 0; | |
49552 | int flgo = ((int8_t)(dst)) < 0; | |
49553 | int flgn = ((int8_t)(newv)) < 0; | |
49554 | SET_ZFLG (((int8_t)(newv)) == 0); | |
49555 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
49556 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
49557 | COPY_CARRY; | |
49558 | SET_NFLG (flgn != 0); | |
49559 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
49560 | }}}}}}}m68k_incpc(4); | |
49561 | fill_prefetch_0 (); | |
49562 | return 14; | |
49563 | } | |
49564 | unsigned long CPUFUNC(op_903c_5)(uint32_t opcode) /* SUB */ | |
49565 | { | |
49566 | uint32_t dstreg = (opcode >> 9) & 7; | |
49567 | OpcodeFamily = 7; CurrentInstrCycles = 8; | |
49568 | {{ int8_t src = get_ibyte_prefetch(2); | |
49569 | { int8_t dst = m68k_dreg(regs, dstreg); | |
49570 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
49571 | { int flgs = ((int8_t)(src)) < 0; | |
49572 | int flgo = ((int8_t)(dst)) < 0; | |
49573 | int flgn = ((int8_t)(newv)) < 0; | |
49574 | SET_ZFLG (((int8_t)(newv)) == 0); | |
49575 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
49576 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
49577 | COPY_CARRY; | |
49578 | SET_NFLG (flgn != 0); | |
49579 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
49580 | }}}}}}m68k_incpc(4); | |
49581 | fill_prefetch_0 (); | |
49582 | return 8; | |
49583 | } | |
49584 | unsigned long CPUFUNC(op_9040_5)(uint32_t opcode) /* SUB */ | |
49585 | { | |
49586 | uint32_t srcreg = (opcode & 7); | |
49587 | uint32_t dstreg = (opcode >> 9) & 7; | |
49588 | OpcodeFamily = 7; CurrentInstrCycles = 4; | |
49589 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
49590 | { int16_t dst = m68k_dreg(regs, dstreg); | |
49591 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
49592 | { int flgs = ((int16_t)(src)) < 0; | |
49593 | int flgo = ((int16_t)(dst)) < 0; | |
49594 | int flgn = ((int16_t)(newv)) < 0; | |
49595 | SET_ZFLG (((int16_t)(newv)) == 0); | |
49596 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
49597 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
49598 | COPY_CARRY; | |
49599 | SET_NFLG (flgn != 0); | |
49600 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
49601 | }}}}}}m68k_incpc(2); | |
49602 | fill_prefetch_2 (); | |
49603 | return 4; | |
49604 | } | |
49605 | unsigned long CPUFUNC(op_9048_5)(uint32_t opcode) /* SUB */ | |
49606 | { | |
49607 | uint32_t srcreg = (opcode & 7); | |
49608 | uint32_t dstreg = (opcode >> 9) & 7; | |
49609 | OpcodeFamily = 7; CurrentInstrCycles = 4; | |
49610 | {{ int16_t src = m68k_areg(regs, srcreg); | |
49611 | { int16_t dst = m68k_dreg(regs, dstreg); | |
49612 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
49613 | { int flgs = ((int16_t)(src)) < 0; | |
49614 | int flgo = ((int16_t)(dst)) < 0; | |
49615 | int flgn = ((int16_t)(newv)) < 0; | |
49616 | SET_ZFLG (((int16_t)(newv)) == 0); | |
49617 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
49618 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
49619 | COPY_CARRY; | |
49620 | SET_NFLG (flgn != 0); | |
49621 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
49622 | }}}}}}m68k_incpc(2); | |
49623 | fill_prefetch_2 (); | |
49624 | return 4; | |
49625 | } | |
49626 | unsigned long CPUFUNC(op_9050_5)(uint32_t opcode) /* SUB */ | |
49627 | { | |
49628 | uint32_t srcreg = (opcode & 7); | |
49629 | uint32_t dstreg = (opcode >> 9) & 7; | |
49630 | OpcodeFamily = 7; CurrentInstrCycles = 8; | |
49631 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
49632 | if ((srca & 1) != 0) { | |
49633 | last_fault_for_exception_3 = srca; | |
49634 | last_op_for_exception_3 = opcode; | |
49635 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
49636 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
49637 | goto endlabel2731; | |
49638 | } | |
49639 | {{ int16_t src = m68k_read_memory_16(srca); | |
49640 | { int16_t dst = m68k_dreg(regs, dstreg); | |
49641 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
49642 | { int flgs = ((int16_t)(src)) < 0; | |
49643 | int flgo = ((int16_t)(dst)) < 0; | |
49644 | int flgn = ((int16_t)(newv)) < 0; | |
49645 | SET_ZFLG (((int16_t)(newv)) == 0); | |
49646 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
49647 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
49648 | COPY_CARRY; | |
49649 | SET_NFLG (flgn != 0); | |
49650 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
49651 | }}}}}}}}m68k_incpc(2); | |
49652 | fill_prefetch_2 (); | |
49653 | endlabel2731: ; | |
49654 | return 8; | |
49655 | } | |
49656 | unsigned long CPUFUNC(op_9058_5)(uint32_t opcode) /* SUB */ | |
49657 | { | |
49658 | uint32_t srcreg = (opcode & 7); | |
49659 | uint32_t dstreg = (opcode >> 9) & 7; | |
49660 | OpcodeFamily = 7; CurrentInstrCycles = 8; | |
49661 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
49662 | if ((srca & 1) != 0) { | |
49663 | last_fault_for_exception_3 = srca; | |
49664 | last_op_for_exception_3 = opcode; | |
49665 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
49666 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
49667 | goto endlabel2732; | |
49668 | } | |
49669 | {{ int16_t src = m68k_read_memory_16(srca); | |
49670 | m68k_areg(regs, srcreg) += 2; | |
49671 | { int16_t dst = m68k_dreg(regs, dstreg); | |
49672 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
49673 | { int flgs = ((int16_t)(src)) < 0; | |
49674 | int flgo = ((int16_t)(dst)) < 0; | |
49675 | int flgn = ((int16_t)(newv)) < 0; | |
49676 | SET_ZFLG (((int16_t)(newv)) == 0); | |
49677 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
49678 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
49679 | COPY_CARRY; | |
49680 | SET_NFLG (flgn != 0); | |
49681 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
49682 | }}}}}}}}m68k_incpc(2); | |
49683 | fill_prefetch_2 (); | |
49684 | endlabel2732: ; | |
49685 | return 8; | |
49686 | } | |
49687 | unsigned long CPUFUNC(op_9060_5)(uint32_t opcode) /* SUB */ | |
49688 | { | |
49689 | uint32_t srcreg = (opcode & 7); | |
49690 | uint32_t dstreg = (opcode >> 9) & 7; | |
49691 | OpcodeFamily = 7; CurrentInstrCycles = 10; | |
49692 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
49693 | if ((srca & 1) != 0) { | |
49694 | last_fault_for_exception_3 = srca; | |
49695 | last_op_for_exception_3 = opcode; | |
49696 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
49697 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
49698 | goto endlabel2733; | |
49699 | } | |
49700 | {{ int16_t src = m68k_read_memory_16(srca); | |
49701 | m68k_areg (regs, srcreg) = srca; | |
49702 | { int16_t dst = m68k_dreg(regs, dstreg); | |
49703 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
49704 | { int flgs = ((int16_t)(src)) < 0; | |
49705 | int flgo = ((int16_t)(dst)) < 0; | |
49706 | int flgn = ((int16_t)(newv)) < 0; | |
49707 | SET_ZFLG (((int16_t)(newv)) == 0); | |
49708 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
49709 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
49710 | COPY_CARRY; | |
49711 | SET_NFLG (flgn != 0); | |
49712 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
49713 | }}}}}}}}m68k_incpc(2); | |
49714 | fill_prefetch_2 (); | |
49715 | endlabel2733: ; | |
49716 | return 10; | |
49717 | } | |
49718 | unsigned long CPUFUNC(op_9068_5)(uint32_t opcode) /* SUB */ | |
49719 | { | |
49720 | uint32_t srcreg = (opcode & 7); | |
49721 | uint32_t dstreg = (opcode >> 9) & 7; | |
49722 | OpcodeFamily = 7; CurrentInstrCycles = 12; | |
49723 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
49724 | if ((srca & 1) != 0) { | |
49725 | last_fault_for_exception_3 = srca; | |
49726 | last_op_for_exception_3 = opcode; | |
49727 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
49728 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
49729 | goto endlabel2734; | |
49730 | } | |
49731 | {{ int16_t src = m68k_read_memory_16(srca); | |
49732 | { int16_t dst = m68k_dreg(regs, dstreg); | |
49733 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
49734 | { int flgs = ((int16_t)(src)) < 0; | |
49735 | int flgo = ((int16_t)(dst)) < 0; | |
49736 | int flgn = ((int16_t)(newv)) < 0; | |
49737 | SET_ZFLG (((int16_t)(newv)) == 0); | |
49738 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
49739 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
49740 | COPY_CARRY; | |
49741 | SET_NFLG (flgn != 0); | |
49742 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
49743 | }}}}}}}}m68k_incpc(4); | |
49744 | fill_prefetch_0 (); | |
49745 | endlabel2734: ; | |
49746 | return 12; | |
49747 | } | |
49748 | unsigned long CPUFUNC(op_9070_5)(uint32_t opcode) /* SUB */ | |
49749 | { | |
49750 | uint32_t srcreg = (opcode & 7); | |
49751 | uint32_t dstreg = (opcode >> 9) & 7; | |
49752 | OpcodeFamily = 7; CurrentInstrCycles = 14; | |
49753 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
49754 | BusCyclePenalty += 2; | |
49755 | if ((srca & 1) != 0) { | |
49756 | last_fault_for_exception_3 = srca; | |
49757 | last_op_for_exception_3 = opcode; | |
49758 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
49759 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
49760 | goto endlabel2735; | |
49761 | } | |
49762 | {{ int16_t src = m68k_read_memory_16(srca); | |
49763 | { int16_t dst = m68k_dreg(regs, dstreg); | |
49764 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
49765 | { int flgs = ((int16_t)(src)) < 0; | |
49766 | int flgo = ((int16_t)(dst)) < 0; | |
49767 | int flgn = ((int16_t)(newv)) < 0; | |
49768 | SET_ZFLG (((int16_t)(newv)) == 0); | |
49769 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
49770 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
49771 | COPY_CARRY; | |
49772 | SET_NFLG (flgn != 0); | |
49773 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
49774 | }}}}}}}}m68k_incpc(4); | |
49775 | fill_prefetch_0 (); | |
49776 | endlabel2735: ; | |
49777 | return 14; | |
49778 | } | |
49779 | unsigned long CPUFUNC(op_9078_5)(uint32_t opcode) /* SUB */ | |
49780 | { | |
49781 | uint32_t dstreg = (opcode >> 9) & 7; | |
49782 | OpcodeFamily = 7; CurrentInstrCycles = 12; | |
49783 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
49784 | if ((srca & 1) != 0) { | |
49785 | last_fault_for_exception_3 = srca; | |
49786 | last_op_for_exception_3 = opcode; | |
49787 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
49788 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
49789 | goto endlabel2736; | |
49790 | } | |
49791 | {{ int16_t src = m68k_read_memory_16(srca); | |
49792 | { int16_t dst = m68k_dreg(regs, dstreg); | |
49793 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
49794 | { int flgs = ((int16_t)(src)) < 0; | |
49795 | int flgo = ((int16_t)(dst)) < 0; | |
49796 | int flgn = ((int16_t)(newv)) < 0; | |
49797 | SET_ZFLG (((int16_t)(newv)) == 0); | |
49798 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
49799 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
49800 | COPY_CARRY; | |
49801 | SET_NFLG (flgn != 0); | |
49802 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
49803 | }}}}}}}}m68k_incpc(4); | |
49804 | fill_prefetch_0 (); | |
49805 | endlabel2736: ; | |
49806 | return 12; | |
49807 | } | |
49808 | unsigned long CPUFUNC(op_9079_5)(uint32_t opcode) /* SUB */ | |
49809 | { | |
49810 | uint32_t dstreg = (opcode >> 9) & 7; | |
49811 | OpcodeFamily = 7; CurrentInstrCycles = 16; | |
49812 | {{ uint32_t srca = get_ilong_prefetch(2); | |
49813 | if ((srca & 1) != 0) { | |
49814 | last_fault_for_exception_3 = srca; | |
49815 | last_op_for_exception_3 = opcode; | |
49816 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
49817 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
49818 | goto endlabel2737; | |
49819 | } | |
49820 | {{ int16_t src = m68k_read_memory_16(srca); | |
49821 | { int16_t dst = m68k_dreg(regs, dstreg); | |
49822 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
49823 | { int flgs = ((int16_t)(src)) < 0; | |
49824 | int flgo = ((int16_t)(dst)) < 0; | |
49825 | int flgn = ((int16_t)(newv)) < 0; | |
49826 | SET_ZFLG (((int16_t)(newv)) == 0); | |
49827 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
49828 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
49829 | COPY_CARRY; | |
49830 | SET_NFLG (flgn != 0); | |
49831 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
49832 | }}}}}}}}m68k_incpc(6); | |
49833 | fill_prefetch_0 (); | |
49834 | endlabel2737: ; | |
49835 | return 16; | |
49836 | } | |
49837 | unsigned long CPUFUNC(op_907a_5)(uint32_t opcode) /* SUB */ | |
49838 | { | |
49839 | uint32_t dstreg = (opcode >> 9) & 7; | |
49840 | OpcodeFamily = 7; CurrentInstrCycles = 12; | |
49841 | {{ uint32_t srca = m68k_getpc () + 2; | |
49842 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
49843 | if ((srca & 1) != 0) { | |
49844 | last_fault_for_exception_3 = srca; | |
49845 | last_op_for_exception_3 = opcode; | |
49846 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
49847 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
49848 | goto endlabel2738; | |
49849 | } | |
49850 | {{ int16_t src = m68k_read_memory_16(srca); | |
49851 | { int16_t dst = m68k_dreg(regs, dstreg); | |
49852 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
49853 | { int flgs = ((int16_t)(src)) < 0; | |
49854 | int flgo = ((int16_t)(dst)) < 0; | |
49855 | int flgn = ((int16_t)(newv)) < 0; | |
49856 | SET_ZFLG (((int16_t)(newv)) == 0); | |
49857 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
49858 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
49859 | COPY_CARRY; | |
49860 | SET_NFLG (flgn != 0); | |
49861 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
49862 | }}}}}}}}m68k_incpc(4); | |
49863 | fill_prefetch_0 (); | |
49864 | endlabel2738: ; | |
49865 | return 12; | |
49866 | } | |
49867 | unsigned long CPUFUNC(op_907b_5)(uint32_t opcode) /* SUB */ | |
49868 | { | |
49869 | uint32_t dstreg = (opcode >> 9) & 7; | |
49870 | OpcodeFamily = 7; CurrentInstrCycles = 14; | |
49871 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
49872 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
49873 | BusCyclePenalty += 2; | |
49874 | if ((srca & 1) != 0) { | |
49875 | last_fault_for_exception_3 = srca; | |
49876 | last_op_for_exception_3 = opcode; | |
49877 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
49878 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
49879 | goto endlabel2739; | |
49880 | } | |
49881 | {{ int16_t src = m68k_read_memory_16(srca); | |
49882 | { int16_t dst = m68k_dreg(regs, dstreg); | |
49883 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
49884 | { int flgs = ((int16_t)(src)) < 0; | |
49885 | int flgo = ((int16_t)(dst)) < 0; | |
49886 | int flgn = ((int16_t)(newv)) < 0; | |
49887 | SET_ZFLG (((int16_t)(newv)) == 0); | |
49888 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
49889 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
49890 | COPY_CARRY; | |
49891 | SET_NFLG (flgn != 0); | |
49892 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
49893 | }}}}}}}}m68k_incpc(4); | |
49894 | fill_prefetch_0 (); | |
49895 | endlabel2739: ; | |
49896 | return 14; | |
49897 | } | |
49898 | unsigned long CPUFUNC(op_907c_5)(uint32_t opcode) /* SUB */ | |
49899 | { | |
49900 | uint32_t dstreg = (opcode >> 9) & 7; | |
49901 | OpcodeFamily = 7; CurrentInstrCycles = 8; | |
49902 | {{ int16_t src = get_iword_prefetch(2); | |
49903 | { int16_t dst = m68k_dreg(regs, dstreg); | |
49904 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
49905 | { int flgs = ((int16_t)(src)) < 0; | |
49906 | int flgo = ((int16_t)(dst)) < 0; | |
49907 | int flgn = ((int16_t)(newv)) < 0; | |
49908 | SET_ZFLG (((int16_t)(newv)) == 0); | |
49909 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
49910 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
49911 | COPY_CARRY; | |
49912 | SET_NFLG (flgn != 0); | |
49913 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
49914 | }}}}}}m68k_incpc(4); | |
49915 | fill_prefetch_0 (); | |
49916 | return 8; | |
49917 | } | |
49918 | unsigned long CPUFUNC(op_9080_5)(uint32_t opcode) /* SUB */ | |
49919 | { | |
49920 | uint32_t srcreg = (opcode & 7); | |
49921 | uint32_t dstreg = (opcode >> 9) & 7; | |
49922 | OpcodeFamily = 7; CurrentInstrCycles = 8; | |
49923 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
49924 | { int32_t dst = m68k_dreg(regs, dstreg); | |
49925 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
49926 | { int flgs = ((int32_t)(src)) < 0; | |
49927 | int flgo = ((int32_t)(dst)) < 0; | |
49928 | int flgn = ((int32_t)(newv)) < 0; | |
49929 | SET_ZFLG (((int32_t)(newv)) == 0); | |
49930 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
49931 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
49932 | COPY_CARRY; | |
49933 | SET_NFLG (flgn != 0); | |
49934 | m68k_dreg(regs, dstreg) = (newv); | |
49935 | }}}}}}m68k_incpc(2); | |
49936 | fill_prefetch_2 (); | |
49937 | return 8; | |
49938 | } | |
49939 | unsigned long CPUFUNC(op_9088_5)(uint32_t opcode) /* SUB */ | |
49940 | { | |
49941 | uint32_t srcreg = (opcode & 7); | |
49942 | uint32_t dstreg = (opcode >> 9) & 7; | |
49943 | OpcodeFamily = 7; CurrentInstrCycles = 8; | |
49944 | {{ int32_t src = m68k_areg(regs, srcreg); | |
49945 | { int32_t dst = m68k_dreg(regs, dstreg); | |
49946 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
49947 | { int flgs = ((int32_t)(src)) < 0; | |
49948 | int flgo = ((int32_t)(dst)) < 0; | |
49949 | int flgn = ((int32_t)(newv)) < 0; | |
49950 | SET_ZFLG (((int32_t)(newv)) == 0); | |
49951 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
49952 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
49953 | COPY_CARRY; | |
49954 | SET_NFLG (flgn != 0); | |
49955 | m68k_dreg(regs, dstreg) = (newv); | |
49956 | }}}}}}m68k_incpc(2); | |
49957 | fill_prefetch_2 (); | |
49958 | return 8; | |
49959 | } | |
49960 | unsigned long CPUFUNC(op_9090_5)(uint32_t opcode) /* SUB */ | |
49961 | { | |
49962 | uint32_t srcreg = (opcode & 7); | |
49963 | uint32_t dstreg = (opcode >> 9) & 7; | |
49964 | OpcodeFamily = 7; CurrentInstrCycles = 14; | |
49965 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
49966 | if ((srca & 1) != 0) { | |
49967 | last_fault_for_exception_3 = srca; | |
49968 | last_op_for_exception_3 = opcode; | |
49969 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
49970 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
49971 | goto endlabel2743; | |
49972 | } | |
49973 | {{ int32_t src = m68k_read_memory_32(srca); | |
49974 | { int32_t dst = m68k_dreg(regs, dstreg); | |
49975 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
49976 | { int flgs = ((int32_t)(src)) < 0; | |
49977 | int flgo = ((int32_t)(dst)) < 0; | |
49978 | int flgn = ((int32_t)(newv)) < 0; | |
49979 | SET_ZFLG (((int32_t)(newv)) == 0); | |
49980 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
49981 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
49982 | COPY_CARRY; | |
49983 | SET_NFLG (flgn != 0); | |
49984 | m68k_dreg(regs, dstreg) = (newv); | |
49985 | }}}}}}}}m68k_incpc(2); | |
49986 | fill_prefetch_2 (); | |
49987 | endlabel2743: ; | |
49988 | return 14; | |
49989 | } | |
49990 | unsigned long CPUFUNC(op_9098_5)(uint32_t opcode) /* SUB */ | |
49991 | { | |
49992 | uint32_t srcreg = (opcode & 7); | |
49993 | uint32_t dstreg = (opcode >> 9) & 7; | |
49994 | OpcodeFamily = 7; CurrentInstrCycles = 14; | |
49995 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
49996 | if ((srca & 1) != 0) { | |
49997 | last_fault_for_exception_3 = srca; | |
49998 | last_op_for_exception_3 = opcode; | |
49999 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
50000 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
50001 | goto endlabel2744; | |
50002 | } | |
50003 | {{ int32_t src = m68k_read_memory_32(srca); | |
50004 | m68k_areg(regs, srcreg) += 4; | |
50005 | { int32_t dst = m68k_dreg(regs, dstreg); | |
50006 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
50007 | { int flgs = ((int32_t)(src)) < 0; | |
50008 | int flgo = ((int32_t)(dst)) < 0; | |
50009 | int flgn = ((int32_t)(newv)) < 0; | |
50010 | SET_ZFLG (((int32_t)(newv)) == 0); | |
50011 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
50012 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
50013 | COPY_CARRY; | |
50014 | SET_NFLG (flgn != 0); | |
50015 | m68k_dreg(regs, dstreg) = (newv); | |
50016 | }}}}}}}}m68k_incpc(2); | |
50017 | fill_prefetch_2 (); | |
50018 | endlabel2744: ; | |
50019 | return 14; | |
50020 | } | |
50021 | unsigned long CPUFUNC(op_90a0_5)(uint32_t opcode) /* SUB */ | |
50022 | { | |
50023 | uint32_t srcreg = (opcode & 7); | |
50024 | uint32_t dstreg = (opcode >> 9) & 7; | |
50025 | OpcodeFamily = 7; CurrentInstrCycles = 16; | |
50026 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 4; | |
50027 | if ((srca & 1) != 0) { | |
50028 | last_fault_for_exception_3 = srca; | |
50029 | last_op_for_exception_3 = opcode; | |
50030 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
50031 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
50032 | goto endlabel2745; | |
50033 | } | |
50034 | {{ int32_t src = m68k_read_memory_32(srca); | |
50035 | m68k_areg (regs, srcreg) = srca; | |
50036 | { int32_t dst = m68k_dreg(regs, dstreg); | |
50037 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
50038 | { int flgs = ((int32_t)(src)) < 0; | |
50039 | int flgo = ((int32_t)(dst)) < 0; | |
50040 | int flgn = ((int32_t)(newv)) < 0; | |
50041 | SET_ZFLG (((int32_t)(newv)) == 0); | |
50042 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
50043 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
50044 | COPY_CARRY; | |
50045 | SET_NFLG (flgn != 0); | |
50046 | m68k_dreg(regs, dstreg) = (newv); | |
50047 | }}}}}}}}m68k_incpc(2); | |
50048 | fill_prefetch_2 (); | |
50049 | endlabel2745: ; | |
50050 | return 16; | |
50051 | } | |
50052 | unsigned long CPUFUNC(op_90a8_5)(uint32_t opcode) /* SUB */ | |
50053 | { | |
50054 | uint32_t srcreg = (opcode & 7); | |
50055 | uint32_t dstreg = (opcode >> 9) & 7; | |
50056 | OpcodeFamily = 7; CurrentInstrCycles = 18; | |
50057 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
50058 | if ((srca & 1) != 0) { | |
50059 | last_fault_for_exception_3 = srca; | |
50060 | last_op_for_exception_3 = opcode; | |
50061 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
50062 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
50063 | goto endlabel2746; | |
50064 | } | |
50065 | {{ int32_t src = m68k_read_memory_32(srca); | |
50066 | { int32_t dst = m68k_dreg(regs, dstreg); | |
50067 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
50068 | { int flgs = ((int32_t)(src)) < 0; | |
50069 | int flgo = ((int32_t)(dst)) < 0; | |
50070 | int flgn = ((int32_t)(newv)) < 0; | |
50071 | SET_ZFLG (((int32_t)(newv)) == 0); | |
50072 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
50073 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
50074 | COPY_CARRY; | |
50075 | SET_NFLG (flgn != 0); | |
50076 | m68k_dreg(regs, dstreg) = (newv); | |
50077 | }}}}}}}}m68k_incpc(4); | |
50078 | fill_prefetch_0 (); | |
50079 | endlabel2746: ; | |
50080 | return 18; | |
50081 | } | |
50082 | unsigned long CPUFUNC(op_90b0_5)(uint32_t opcode) /* SUB */ | |
50083 | { | |
50084 | uint32_t srcreg = (opcode & 7); | |
50085 | uint32_t dstreg = (opcode >> 9) & 7; | |
50086 | OpcodeFamily = 7; CurrentInstrCycles = 20; | |
50087 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
50088 | BusCyclePenalty += 2; | |
50089 | if ((srca & 1) != 0) { | |
50090 | last_fault_for_exception_3 = srca; | |
50091 | last_op_for_exception_3 = opcode; | |
50092 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
50093 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
50094 | goto endlabel2747; | |
50095 | } | |
50096 | {{ int32_t src = m68k_read_memory_32(srca); | |
50097 | { int32_t dst = m68k_dreg(regs, dstreg); | |
50098 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
50099 | { int flgs = ((int32_t)(src)) < 0; | |
50100 | int flgo = ((int32_t)(dst)) < 0; | |
50101 | int flgn = ((int32_t)(newv)) < 0; | |
50102 | SET_ZFLG (((int32_t)(newv)) == 0); | |
50103 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
50104 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
50105 | COPY_CARRY; | |
50106 | SET_NFLG (flgn != 0); | |
50107 | m68k_dreg(regs, dstreg) = (newv); | |
50108 | }}}}}}}}m68k_incpc(4); | |
50109 | fill_prefetch_0 (); | |
50110 | endlabel2747: ; | |
50111 | return 20; | |
50112 | } | |
50113 | unsigned long CPUFUNC(op_90b8_5)(uint32_t opcode) /* SUB */ | |
50114 | { | |
50115 | uint32_t dstreg = (opcode >> 9) & 7; | |
50116 | OpcodeFamily = 7; CurrentInstrCycles = 18; | |
50117 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
50118 | if ((srca & 1) != 0) { | |
50119 | last_fault_for_exception_3 = srca; | |
50120 | last_op_for_exception_3 = opcode; | |
50121 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
50122 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
50123 | goto endlabel2748; | |
50124 | } | |
50125 | {{ int32_t src = m68k_read_memory_32(srca); | |
50126 | { int32_t dst = m68k_dreg(regs, dstreg); | |
50127 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
50128 | { int flgs = ((int32_t)(src)) < 0; | |
50129 | int flgo = ((int32_t)(dst)) < 0; | |
50130 | int flgn = ((int32_t)(newv)) < 0; | |
50131 | SET_ZFLG (((int32_t)(newv)) == 0); | |
50132 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
50133 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
50134 | COPY_CARRY; | |
50135 | SET_NFLG (flgn != 0); | |
50136 | m68k_dreg(regs, dstreg) = (newv); | |
50137 | }}}}}}}}m68k_incpc(4); | |
50138 | fill_prefetch_0 (); | |
50139 | endlabel2748: ; | |
50140 | return 18; | |
50141 | } | |
50142 | unsigned long CPUFUNC(op_90b9_5)(uint32_t opcode) /* SUB */ | |
50143 | { | |
50144 | uint32_t dstreg = (opcode >> 9) & 7; | |
50145 | OpcodeFamily = 7; CurrentInstrCycles = 22; | |
50146 | {{ uint32_t srca = get_ilong_prefetch(2); | |
50147 | if ((srca & 1) != 0) { | |
50148 | last_fault_for_exception_3 = srca; | |
50149 | last_op_for_exception_3 = opcode; | |
50150 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
50151 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
50152 | goto endlabel2749; | |
50153 | } | |
50154 | {{ int32_t src = m68k_read_memory_32(srca); | |
50155 | { int32_t dst = m68k_dreg(regs, dstreg); | |
50156 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
50157 | { int flgs = ((int32_t)(src)) < 0; | |
50158 | int flgo = ((int32_t)(dst)) < 0; | |
50159 | int flgn = ((int32_t)(newv)) < 0; | |
50160 | SET_ZFLG (((int32_t)(newv)) == 0); | |
50161 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
50162 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
50163 | COPY_CARRY; | |
50164 | SET_NFLG (flgn != 0); | |
50165 | m68k_dreg(regs, dstreg) = (newv); | |
50166 | }}}}}}}}m68k_incpc(6); | |
50167 | fill_prefetch_0 (); | |
50168 | endlabel2749: ; | |
50169 | return 22; | |
50170 | } | |
50171 | unsigned long CPUFUNC(op_90ba_5)(uint32_t opcode) /* SUB */ | |
50172 | { | |
50173 | uint32_t dstreg = (opcode >> 9) & 7; | |
50174 | OpcodeFamily = 7; CurrentInstrCycles = 18; | |
50175 | {{ uint32_t srca = m68k_getpc () + 2; | |
50176 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
50177 | if ((srca & 1) != 0) { | |
50178 | last_fault_for_exception_3 = srca; | |
50179 | last_op_for_exception_3 = opcode; | |
50180 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
50181 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
50182 | goto endlabel2750; | |
50183 | } | |
50184 | {{ int32_t src = m68k_read_memory_32(srca); | |
50185 | { int32_t dst = m68k_dreg(regs, dstreg); | |
50186 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
50187 | { int flgs = ((int32_t)(src)) < 0; | |
50188 | int flgo = ((int32_t)(dst)) < 0; | |
50189 | int flgn = ((int32_t)(newv)) < 0; | |
50190 | SET_ZFLG (((int32_t)(newv)) == 0); | |
50191 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
50192 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
50193 | COPY_CARRY; | |
50194 | SET_NFLG (flgn != 0); | |
50195 | m68k_dreg(regs, dstreg) = (newv); | |
50196 | }}}}}}}}m68k_incpc(4); | |
50197 | fill_prefetch_0 (); | |
50198 | endlabel2750: ; | |
50199 | return 18; | |
50200 | } | |
50201 | unsigned long CPUFUNC(op_90bb_5)(uint32_t opcode) /* SUB */ | |
50202 | { | |
50203 | uint32_t dstreg = (opcode >> 9) & 7; | |
50204 | OpcodeFamily = 7; CurrentInstrCycles = 20; | |
50205 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
50206 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
50207 | BusCyclePenalty += 2; | |
50208 | if ((srca & 1) != 0) { | |
50209 | last_fault_for_exception_3 = srca; | |
50210 | last_op_for_exception_3 = opcode; | |
50211 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
50212 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
50213 | goto endlabel2751; | |
50214 | } | |
50215 | {{ int32_t src = m68k_read_memory_32(srca); | |
50216 | { int32_t dst = m68k_dreg(regs, dstreg); | |
50217 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
50218 | { int flgs = ((int32_t)(src)) < 0; | |
50219 | int flgo = ((int32_t)(dst)) < 0; | |
50220 | int flgn = ((int32_t)(newv)) < 0; | |
50221 | SET_ZFLG (((int32_t)(newv)) == 0); | |
50222 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
50223 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
50224 | COPY_CARRY; | |
50225 | SET_NFLG (flgn != 0); | |
50226 | m68k_dreg(regs, dstreg) = (newv); | |
50227 | }}}}}}}}m68k_incpc(4); | |
50228 | fill_prefetch_0 (); | |
50229 | endlabel2751: ; | |
50230 | return 20; | |
50231 | } | |
50232 | unsigned long CPUFUNC(op_90bc_5)(uint32_t opcode) /* SUB */ | |
50233 | { | |
50234 | uint32_t dstreg = (opcode >> 9) & 7; | |
50235 | OpcodeFamily = 7; CurrentInstrCycles = 16; | |
50236 | {{ int32_t src = get_ilong_prefetch(2); | |
50237 | { int32_t dst = m68k_dreg(regs, dstreg); | |
50238 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
50239 | { int flgs = ((int32_t)(src)) < 0; | |
50240 | int flgo = ((int32_t)(dst)) < 0; | |
50241 | int flgn = ((int32_t)(newv)) < 0; | |
50242 | SET_ZFLG (((int32_t)(newv)) == 0); | |
50243 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
50244 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
50245 | COPY_CARRY; | |
50246 | SET_NFLG (flgn != 0); | |
50247 | m68k_dreg(regs, dstreg) = (newv); | |
50248 | }}}}}}m68k_incpc(6); | |
50249 | fill_prefetch_0 (); | |
50250 | return 16; | |
50251 | } | |
50252 | unsigned long CPUFUNC(op_90c0_5)(uint32_t opcode) /* SUBA */ | |
50253 | { | |
50254 | uint32_t srcreg = (opcode & 7); | |
50255 | uint32_t dstreg = (opcode >> 9) & 7; | |
50256 | OpcodeFamily = 8; CurrentInstrCycles = 8; | |
50257 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
50258 | { int32_t dst = m68k_areg(regs, dstreg); | |
50259 | { uint32_t newv = dst - src; | |
50260 | m68k_areg(regs, dstreg) = (newv); | |
50261 | }}}}m68k_incpc(2); | |
50262 | fill_prefetch_2 (); | |
50263 | return 8; | |
50264 | } | |
50265 | unsigned long CPUFUNC(op_90c8_5)(uint32_t opcode) /* SUBA */ | |
50266 | { | |
50267 | uint32_t srcreg = (opcode & 7); | |
50268 | uint32_t dstreg = (opcode >> 9) & 7; | |
50269 | OpcodeFamily = 8; CurrentInstrCycles = 8; | |
50270 | {{ int16_t src = m68k_areg(regs, srcreg); | |
50271 | { int32_t dst = m68k_areg(regs, dstreg); | |
50272 | { uint32_t newv = dst - src; | |
50273 | m68k_areg(regs, dstreg) = (newv); | |
50274 | }}}}m68k_incpc(2); | |
50275 | fill_prefetch_2 (); | |
50276 | return 8; | |
50277 | } | |
50278 | unsigned long CPUFUNC(op_90d0_5)(uint32_t opcode) /* SUBA */ | |
50279 | { | |
50280 | uint32_t srcreg = (opcode & 7); | |
50281 | uint32_t dstreg = (opcode >> 9) & 7; | |
50282 | OpcodeFamily = 8; CurrentInstrCycles = 12; | |
50283 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
50284 | if ((srca & 1) != 0) { | |
50285 | last_fault_for_exception_3 = srca; | |
50286 | last_op_for_exception_3 = opcode; | |
50287 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
50288 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
50289 | goto endlabel2755; | |
50290 | } | |
50291 | {{ int16_t src = m68k_read_memory_16(srca); | |
50292 | { int32_t dst = m68k_areg(regs, dstreg); | |
50293 | { uint32_t newv = dst - src; | |
50294 | m68k_areg(regs, dstreg) = (newv); | |
50295 | }}}}}}m68k_incpc(2); | |
50296 | fill_prefetch_2 (); | |
50297 | endlabel2755: ; | |
50298 | return 12; | |
50299 | } | |
50300 | unsigned long CPUFUNC(op_90d8_5)(uint32_t opcode) /* SUBA */ | |
50301 | { | |
50302 | uint32_t srcreg = (opcode & 7); | |
50303 | uint32_t dstreg = (opcode >> 9) & 7; | |
50304 | OpcodeFamily = 8; CurrentInstrCycles = 12; | |
50305 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
50306 | if ((srca & 1) != 0) { | |
50307 | last_fault_for_exception_3 = srca; | |
50308 | last_op_for_exception_3 = opcode; | |
50309 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
50310 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
50311 | goto endlabel2756; | |
50312 | } | |
50313 | {{ int16_t src = m68k_read_memory_16(srca); | |
50314 | m68k_areg(regs, srcreg) += 2; | |
50315 | { int32_t dst = m68k_areg(regs, dstreg); | |
50316 | { uint32_t newv = dst - src; | |
50317 | m68k_areg(regs, dstreg) = (newv); | |
50318 | }}}}}}m68k_incpc(2); | |
50319 | fill_prefetch_2 (); | |
50320 | endlabel2756: ; | |
50321 | return 12; | |
50322 | } | |
50323 | unsigned long CPUFUNC(op_90e0_5)(uint32_t opcode) /* SUBA */ | |
50324 | { | |
50325 | uint32_t srcreg = (opcode & 7); | |
50326 | uint32_t dstreg = (opcode >> 9) & 7; | |
50327 | OpcodeFamily = 8; CurrentInstrCycles = 14; | |
50328 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
50329 | if ((srca & 1) != 0) { | |
50330 | last_fault_for_exception_3 = srca; | |
50331 | last_op_for_exception_3 = opcode; | |
50332 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
50333 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
50334 | goto endlabel2757; | |
50335 | } | |
50336 | {{ int16_t src = m68k_read_memory_16(srca); | |
50337 | m68k_areg (regs, srcreg) = srca; | |
50338 | { int32_t dst = m68k_areg(regs, dstreg); | |
50339 | { uint32_t newv = dst - src; | |
50340 | m68k_areg(regs, dstreg) = (newv); | |
50341 | }}}}}}m68k_incpc(2); | |
50342 | fill_prefetch_2 (); | |
50343 | endlabel2757: ; | |
50344 | return 14; | |
50345 | } | |
50346 | unsigned long CPUFUNC(op_90e8_5)(uint32_t opcode) /* SUBA */ | |
50347 | { | |
50348 | uint32_t srcreg = (opcode & 7); | |
50349 | uint32_t dstreg = (opcode >> 9) & 7; | |
50350 | OpcodeFamily = 8; CurrentInstrCycles = 16; | |
50351 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
50352 | if ((srca & 1) != 0) { | |
50353 | last_fault_for_exception_3 = srca; | |
50354 | last_op_for_exception_3 = opcode; | |
50355 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
50356 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
50357 | goto endlabel2758; | |
50358 | } | |
50359 | {{ int16_t src = m68k_read_memory_16(srca); | |
50360 | { int32_t dst = m68k_areg(regs, dstreg); | |
50361 | { uint32_t newv = dst - src; | |
50362 | m68k_areg(regs, dstreg) = (newv); | |
50363 | }}}}}}m68k_incpc(4); | |
50364 | fill_prefetch_0 (); | |
50365 | endlabel2758: ; | |
50366 | return 16; | |
50367 | } | |
50368 | unsigned long CPUFUNC(op_90f0_5)(uint32_t opcode) /* SUBA */ | |
50369 | { | |
50370 | uint32_t srcreg = (opcode & 7); | |
50371 | uint32_t dstreg = (opcode >> 9) & 7; | |
50372 | OpcodeFamily = 8; CurrentInstrCycles = 18; | |
50373 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
50374 | BusCyclePenalty += 2; | |
50375 | if ((srca & 1) != 0) { | |
50376 | last_fault_for_exception_3 = srca; | |
50377 | last_op_for_exception_3 = opcode; | |
50378 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
50379 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
50380 | goto endlabel2759; | |
50381 | } | |
50382 | {{ int16_t src = m68k_read_memory_16(srca); | |
50383 | { int32_t dst = m68k_areg(regs, dstreg); | |
50384 | { uint32_t newv = dst - src; | |
50385 | m68k_areg(regs, dstreg) = (newv); | |
50386 | }}}}}}m68k_incpc(4); | |
50387 | fill_prefetch_0 (); | |
50388 | endlabel2759: ; | |
50389 | return 18; | |
50390 | } | |
50391 | unsigned long CPUFUNC(op_90f8_5)(uint32_t opcode) /* SUBA */ | |
50392 | { | |
50393 | uint32_t dstreg = (opcode >> 9) & 7; | |
50394 | OpcodeFamily = 8; CurrentInstrCycles = 16; | |
50395 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
50396 | if ((srca & 1) != 0) { | |
50397 | last_fault_for_exception_3 = srca; | |
50398 | last_op_for_exception_3 = opcode; | |
50399 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
50400 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
50401 | goto endlabel2760; | |
50402 | } | |
50403 | {{ int16_t src = m68k_read_memory_16(srca); | |
50404 | { int32_t dst = m68k_areg(regs, dstreg); | |
50405 | { uint32_t newv = dst - src; | |
50406 | m68k_areg(regs, dstreg) = (newv); | |
50407 | }}}}}}m68k_incpc(4); | |
50408 | fill_prefetch_0 (); | |
50409 | endlabel2760: ; | |
50410 | return 16; | |
50411 | } | |
50412 | unsigned long CPUFUNC(op_90f9_5)(uint32_t opcode) /* SUBA */ | |
50413 | { | |
50414 | uint32_t dstreg = (opcode >> 9) & 7; | |
50415 | OpcodeFamily = 8; CurrentInstrCycles = 20; | |
50416 | {{ uint32_t srca = get_ilong_prefetch(2); | |
50417 | if ((srca & 1) != 0) { | |
50418 | last_fault_for_exception_3 = srca; | |
50419 | last_op_for_exception_3 = opcode; | |
50420 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
50421 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
50422 | goto endlabel2761; | |
50423 | } | |
50424 | {{ int16_t src = m68k_read_memory_16(srca); | |
50425 | { int32_t dst = m68k_areg(regs, dstreg); | |
50426 | { uint32_t newv = dst - src; | |
50427 | m68k_areg(regs, dstreg) = (newv); | |
50428 | }}}}}}m68k_incpc(6); | |
50429 | fill_prefetch_0 (); | |
50430 | endlabel2761: ; | |
50431 | return 20; | |
50432 | } | |
50433 | unsigned long CPUFUNC(op_90fa_5)(uint32_t opcode) /* SUBA */ | |
50434 | { | |
50435 | uint32_t dstreg = (opcode >> 9) & 7; | |
50436 | OpcodeFamily = 8; CurrentInstrCycles = 16; | |
50437 | {{ uint32_t srca = m68k_getpc () + 2; | |
50438 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
50439 | if ((srca & 1) != 0) { | |
50440 | last_fault_for_exception_3 = srca; | |
50441 | last_op_for_exception_3 = opcode; | |
50442 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
50443 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
50444 | goto endlabel2762; | |
50445 | } | |
50446 | {{ int16_t src = m68k_read_memory_16(srca); | |
50447 | { int32_t dst = m68k_areg(regs, dstreg); | |
50448 | { uint32_t newv = dst - src; | |
50449 | m68k_areg(regs, dstreg) = (newv); | |
50450 | }}}}}}m68k_incpc(4); | |
50451 | fill_prefetch_0 (); | |
50452 | endlabel2762: ; | |
50453 | return 16; | |
50454 | } | |
50455 | unsigned long CPUFUNC(op_90fb_5)(uint32_t opcode) /* SUBA */ | |
50456 | { | |
50457 | uint32_t dstreg = (opcode >> 9) & 7; | |
50458 | OpcodeFamily = 8; CurrentInstrCycles = 18; | |
50459 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
50460 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
50461 | BusCyclePenalty += 2; | |
50462 | if ((srca & 1) != 0) { | |
50463 | last_fault_for_exception_3 = srca; | |
50464 | last_op_for_exception_3 = opcode; | |
50465 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
50466 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
50467 | goto endlabel2763; | |
50468 | } | |
50469 | {{ int16_t src = m68k_read_memory_16(srca); | |
50470 | { int32_t dst = m68k_areg(regs, dstreg); | |
50471 | { uint32_t newv = dst - src; | |
50472 | m68k_areg(regs, dstreg) = (newv); | |
50473 | }}}}}}m68k_incpc(4); | |
50474 | fill_prefetch_0 (); | |
50475 | endlabel2763: ; | |
50476 | return 18; | |
50477 | } | |
50478 | unsigned long CPUFUNC(op_90fc_5)(uint32_t opcode) /* SUBA */ | |
50479 | { | |
50480 | uint32_t dstreg = (opcode >> 9) & 7; | |
50481 | OpcodeFamily = 8; CurrentInstrCycles = 12; | |
50482 | {{ int16_t src = get_iword_prefetch(2); | |
50483 | { int32_t dst = m68k_areg(regs, dstreg); | |
50484 | { uint32_t newv = dst - src; | |
50485 | m68k_areg(regs, dstreg) = (newv); | |
50486 | }}}}m68k_incpc(4); | |
50487 | fill_prefetch_0 (); | |
50488 | return 12; | |
50489 | } | |
50490 | unsigned long CPUFUNC(op_9100_5)(uint32_t opcode) /* SUBX */ | |
50491 | { | |
50492 | uint32_t srcreg = (opcode & 7); | |
50493 | uint32_t dstreg = (opcode >> 9) & 7; | |
50494 | OpcodeFamily = 9; CurrentInstrCycles = 4; | |
50495 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
50496 | { int8_t dst = m68k_dreg(regs, dstreg); | |
50497 | { uint32_t newv = dst - src - (GET_XFLG ? 1 : 0); | |
50498 | { int flgs = ((int8_t)(src)) < 0; | |
50499 | int flgo = ((int8_t)(dst)) < 0; | |
50500 | int flgn = ((int8_t)(newv)) < 0; | |
50501 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
50502 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
50503 | COPY_CARRY; | |
50504 | SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); | |
50505 | SET_NFLG (((int8_t)(newv)) < 0); | |
50506 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
50507 | }}}}}m68k_incpc(2); | |
50508 | fill_prefetch_2 (); | |
50509 | return 4; | |
50510 | } | |
50511 | unsigned long CPUFUNC(op_9108_5)(uint32_t opcode) /* SUBX */ | |
50512 | { | |
50513 | uint32_t srcreg = (opcode & 7); | |
50514 | uint32_t dstreg = (opcode >> 9) & 7; | |
50515 | OpcodeFamily = 9; CurrentInstrCycles = 18; | |
50516 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
50517 | { int8_t src = m68k_read_memory_8(srca); | |
50518 | m68k_areg (regs, srcreg) = srca; | |
50519 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
50520 | { int8_t dst = m68k_read_memory_8(dsta); | |
50521 | m68k_areg (regs, dstreg) = dsta; | |
50522 | { uint32_t newv = dst - src - (GET_XFLG ? 1 : 0); | |
50523 | { int flgs = ((int8_t)(src)) < 0; | |
50524 | int flgo = ((int8_t)(dst)) < 0; | |
50525 | int flgn = ((int8_t)(newv)) < 0; | |
50526 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
50527 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
50528 | COPY_CARRY; | |
50529 | SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); | |
50530 | SET_NFLG (((int8_t)(newv)) < 0); | |
50531 | m68k_incpc(2); | |
50532 | fill_prefetch_2 (); | |
50533 | m68k_write_memory_8(dsta,newv); | |
50534 | }}}}}}}return 18; | |
50535 | } | |
50536 | unsigned long CPUFUNC(op_9110_5)(uint32_t opcode) /* SUB */ | |
50537 | { | |
50538 | uint32_t srcreg = ((opcode >> 9) & 7); | |
50539 | uint32_t dstreg = opcode & 7; | |
50540 | OpcodeFamily = 7; CurrentInstrCycles = 12; | |
50541 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
50542 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
50543 | { int8_t dst = m68k_read_memory_8(dsta); | |
50544 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
50545 | { int flgs = ((int8_t)(src)) < 0; | |
50546 | int flgo = ((int8_t)(dst)) < 0; | |
50547 | int flgn = ((int8_t)(newv)) < 0; | |
50548 | SET_ZFLG (((int8_t)(newv)) == 0); | |
50549 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
50550 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
50551 | COPY_CARRY; | |
50552 | SET_NFLG (flgn != 0); | |
50553 | m68k_incpc(2); | |
50554 | fill_prefetch_2 (); | |
50555 | m68k_write_memory_8(dsta,newv); | |
50556 | }}}}}}}return 12; | |
50557 | } | |
50558 | unsigned long CPUFUNC(op_9118_5)(uint32_t opcode) /* SUB */ | |
50559 | { | |
50560 | uint32_t srcreg = ((opcode >> 9) & 7); | |
50561 | uint32_t dstreg = opcode & 7; | |
50562 | OpcodeFamily = 7; CurrentInstrCycles = 12; | |
50563 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
50564 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
50565 | { int8_t dst = m68k_read_memory_8(dsta); | |
50566 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
50567 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
50568 | { int flgs = ((int8_t)(src)) < 0; | |
50569 | int flgo = ((int8_t)(dst)) < 0; | |
50570 | int flgn = ((int8_t)(newv)) < 0; | |
50571 | SET_ZFLG (((int8_t)(newv)) == 0); | |
50572 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
50573 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
50574 | COPY_CARRY; | |
50575 | SET_NFLG (flgn != 0); | |
50576 | m68k_incpc(2); | |
50577 | fill_prefetch_2 (); | |
50578 | m68k_write_memory_8(dsta,newv); | |
50579 | }}}}}}}return 12; | |
50580 | } | |
50581 | unsigned long CPUFUNC(op_9120_5)(uint32_t opcode) /* SUB */ | |
50582 | { | |
50583 | uint32_t srcreg = ((opcode >> 9) & 7); | |
50584 | uint32_t dstreg = opcode & 7; | |
50585 | OpcodeFamily = 7; CurrentInstrCycles = 14; | |
50586 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
50587 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
50588 | { int8_t dst = m68k_read_memory_8(dsta); | |
50589 | m68k_areg (regs, dstreg) = dsta; | |
50590 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
50591 | { int flgs = ((int8_t)(src)) < 0; | |
50592 | int flgo = ((int8_t)(dst)) < 0; | |
50593 | int flgn = ((int8_t)(newv)) < 0; | |
50594 | SET_ZFLG (((int8_t)(newv)) == 0); | |
50595 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
50596 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
50597 | COPY_CARRY; | |
50598 | SET_NFLG (flgn != 0); | |
50599 | m68k_incpc(2); | |
50600 | fill_prefetch_2 (); | |
50601 | m68k_write_memory_8(dsta,newv); | |
50602 | }}}}}}}return 14; | |
50603 | } | |
50604 | unsigned long CPUFUNC(op_9128_5)(uint32_t opcode) /* SUB */ | |
50605 | { | |
50606 | uint32_t srcreg = ((opcode >> 9) & 7); | |
50607 | uint32_t dstreg = opcode & 7; | |
50608 | OpcodeFamily = 7; CurrentInstrCycles = 16; | |
50609 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
50610 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
50611 | { int8_t dst = m68k_read_memory_8(dsta); | |
50612 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
50613 | { int flgs = ((int8_t)(src)) < 0; | |
50614 | int flgo = ((int8_t)(dst)) < 0; | |
50615 | int flgn = ((int8_t)(newv)) < 0; | |
50616 | SET_ZFLG (((int8_t)(newv)) == 0); | |
50617 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
50618 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
50619 | COPY_CARRY; | |
50620 | SET_NFLG (flgn != 0); | |
50621 | m68k_incpc(4); | |
50622 | fill_prefetch_0 (); | |
50623 | m68k_write_memory_8(dsta,newv); | |
50624 | }}}}}}}return 16; | |
50625 | } | |
50626 | unsigned long CPUFUNC(op_9130_5)(uint32_t opcode) /* SUB */ | |
50627 | { | |
50628 | uint32_t srcreg = ((opcode >> 9) & 7); | |
50629 | uint32_t dstreg = opcode & 7; | |
50630 | OpcodeFamily = 7; CurrentInstrCycles = 18; | |
50631 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
50632 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); | |
50633 | BusCyclePenalty += 2; | |
50634 | { int8_t dst = m68k_read_memory_8(dsta); | |
50635 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
50636 | { int flgs = ((int8_t)(src)) < 0; | |
50637 | int flgo = ((int8_t)(dst)) < 0; | |
50638 | int flgn = ((int8_t)(newv)) < 0; | |
50639 | SET_ZFLG (((int8_t)(newv)) == 0); | |
50640 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
50641 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
50642 | COPY_CARRY; | |
50643 | SET_NFLG (flgn != 0); | |
50644 | m68k_incpc(4); | |
50645 | fill_prefetch_0 (); | |
50646 | m68k_write_memory_8(dsta,newv); | |
50647 | }}}}}}}return 18; | |
50648 | } | |
50649 | unsigned long CPUFUNC(op_9138_5)(uint32_t opcode) /* SUB */ | |
50650 | { | |
50651 | uint32_t srcreg = ((opcode >> 9) & 7); | |
50652 | OpcodeFamily = 7; CurrentInstrCycles = 16; | |
50653 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
50654 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); | |
50655 | { int8_t dst = m68k_read_memory_8(dsta); | |
50656 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
50657 | { int flgs = ((int8_t)(src)) < 0; | |
50658 | int flgo = ((int8_t)(dst)) < 0; | |
50659 | int flgn = ((int8_t)(newv)) < 0; | |
50660 | SET_ZFLG (((int8_t)(newv)) == 0); | |
50661 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
50662 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
50663 | COPY_CARRY; | |
50664 | SET_NFLG (flgn != 0); | |
50665 | m68k_incpc(4); | |
50666 | fill_prefetch_0 (); | |
50667 | m68k_write_memory_8(dsta,newv); | |
50668 | }}}}}}}return 16; | |
50669 | } | |
50670 | unsigned long CPUFUNC(op_9139_5)(uint32_t opcode) /* SUB */ | |
50671 | { | |
50672 | uint32_t srcreg = ((opcode >> 9) & 7); | |
50673 | OpcodeFamily = 7; CurrentInstrCycles = 20; | |
50674 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
50675 | { uint32_t dsta = get_ilong_prefetch(2); | |
50676 | { int8_t dst = m68k_read_memory_8(dsta); | |
50677 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
50678 | { int flgs = ((int8_t)(src)) < 0; | |
50679 | int flgo = ((int8_t)(dst)) < 0; | |
50680 | int flgn = ((int8_t)(newv)) < 0; | |
50681 | SET_ZFLG (((int8_t)(newv)) == 0); | |
50682 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
50683 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
50684 | COPY_CARRY; | |
50685 | SET_NFLG (flgn != 0); | |
50686 | m68k_incpc(6); | |
50687 | fill_prefetch_0 (); | |
50688 | m68k_write_memory_8(dsta,newv); | |
50689 | }}}}}}}return 20; | |
50690 | } | |
50691 | unsigned long CPUFUNC(op_9140_5)(uint32_t opcode) /* SUBX */ | |
50692 | { | |
50693 | uint32_t srcreg = (opcode & 7); | |
50694 | uint32_t dstreg = (opcode >> 9) & 7; | |
50695 | OpcodeFamily = 9; CurrentInstrCycles = 4; | |
50696 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
50697 | { int16_t dst = m68k_dreg(regs, dstreg); | |
50698 | { uint32_t newv = dst - src - (GET_XFLG ? 1 : 0); | |
50699 | { int flgs = ((int16_t)(src)) < 0; | |
50700 | int flgo = ((int16_t)(dst)) < 0; | |
50701 | int flgn = ((int16_t)(newv)) < 0; | |
50702 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
50703 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
50704 | COPY_CARRY; | |
50705 | SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0)); | |
50706 | SET_NFLG (((int16_t)(newv)) < 0); | |
50707 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
50708 | }}}}}m68k_incpc(2); | |
50709 | fill_prefetch_2 (); | |
50710 | return 4; | |
50711 | } | |
50712 | unsigned long CPUFUNC(op_9148_5)(uint32_t opcode) /* SUBX */ | |
50713 | { | |
50714 | uint32_t srcreg = (opcode & 7); | |
50715 | uint32_t dstreg = (opcode >> 9) & 7; | |
50716 | OpcodeFamily = 9; CurrentInstrCycles = 18; | |
50717 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
50718 | if ((srca & 1) != 0) { | |
50719 | last_fault_for_exception_3 = srca; | |
50720 | last_op_for_exception_3 = opcode; | |
50721 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
50722 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
50723 | goto endlabel2775; | |
50724 | } | |
50725 | {{ int16_t src = m68k_read_memory_16(srca); | |
50726 | m68k_areg (regs, srcreg) = srca; | |
50727 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
50728 | if ((dsta & 1) != 0) { | |
50729 | last_fault_for_exception_3 = dsta; | |
50730 | last_op_for_exception_3 = opcode; | |
50731 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
50732 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
50733 | goto endlabel2775; | |
50734 | } | |
50735 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
50736 | m68k_areg (regs, dstreg) = dsta; | |
50737 | { uint32_t newv = dst - src - (GET_XFLG ? 1 : 0); | |
50738 | { int flgs = ((int16_t)(src)) < 0; | |
50739 | int flgo = ((int16_t)(dst)) < 0; | |
50740 | int flgn = ((int16_t)(newv)) < 0; | |
50741 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
50742 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
50743 | COPY_CARRY; | |
50744 | SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0)); | |
50745 | SET_NFLG (((int16_t)(newv)) < 0); | |
50746 | m68k_incpc(2); | |
50747 | fill_prefetch_2 (); | |
50748 | m68k_write_memory_16(dsta,newv); | |
50749 | }}}}}}}}}endlabel2775: ; | |
50750 | return 18; | |
50751 | } | |
50752 | unsigned long CPUFUNC(op_9150_5)(uint32_t opcode) /* SUB */ | |
50753 | { | |
50754 | uint32_t srcreg = ((opcode >> 9) & 7); | |
50755 | uint32_t dstreg = opcode & 7; | |
50756 | OpcodeFamily = 7; CurrentInstrCycles = 12; | |
50757 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
50758 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
50759 | if ((dsta & 1) != 0) { | |
50760 | last_fault_for_exception_3 = dsta; | |
50761 | last_op_for_exception_3 = opcode; | |
50762 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
50763 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
50764 | goto endlabel2776; | |
50765 | } | |
50766 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
50767 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
50768 | { int flgs = ((int16_t)(src)) < 0; | |
50769 | int flgo = ((int16_t)(dst)) < 0; | |
50770 | int flgn = ((int16_t)(newv)) < 0; | |
50771 | SET_ZFLG (((int16_t)(newv)) == 0); | |
50772 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
50773 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
50774 | COPY_CARRY; | |
50775 | SET_NFLG (flgn != 0); | |
50776 | m68k_incpc(2); | |
50777 | fill_prefetch_2 (); | |
50778 | m68k_write_memory_16(dsta,newv); | |
50779 | }}}}}}}}endlabel2776: ; | |
50780 | return 12; | |
50781 | } | |
50782 | unsigned long CPUFUNC(op_9158_5)(uint32_t opcode) /* SUB */ | |
50783 | { | |
50784 | uint32_t srcreg = ((opcode >> 9) & 7); | |
50785 | uint32_t dstreg = opcode & 7; | |
50786 | OpcodeFamily = 7; CurrentInstrCycles = 12; | |
50787 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
50788 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
50789 | if ((dsta & 1) != 0) { | |
50790 | last_fault_for_exception_3 = dsta; | |
50791 | last_op_for_exception_3 = opcode; | |
50792 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
50793 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
50794 | goto endlabel2777; | |
50795 | } | |
50796 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
50797 | m68k_areg(regs, dstreg) += 2; | |
50798 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
50799 | { int flgs = ((int16_t)(src)) < 0; | |
50800 | int flgo = ((int16_t)(dst)) < 0; | |
50801 | int flgn = ((int16_t)(newv)) < 0; | |
50802 | SET_ZFLG (((int16_t)(newv)) == 0); | |
50803 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
50804 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
50805 | COPY_CARRY; | |
50806 | SET_NFLG (flgn != 0); | |
50807 | m68k_incpc(2); | |
50808 | fill_prefetch_2 (); | |
50809 | m68k_write_memory_16(dsta,newv); | |
50810 | }}}}}}}}endlabel2777: ; | |
50811 | return 12; | |
50812 | } | |
50813 | unsigned long CPUFUNC(op_9160_5)(uint32_t opcode) /* SUB */ | |
50814 | { | |
50815 | uint32_t srcreg = ((opcode >> 9) & 7); | |
50816 | uint32_t dstreg = opcode & 7; | |
50817 | OpcodeFamily = 7; CurrentInstrCycles = 14; | |
50818 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
50819 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
50820 | if ((dsta & 1) != 0) { | |
50821 | last_fault_for_exception_3 = dsta; | |
50822 | last_op_for_exception_3 = opcode; | |
50823 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
50824 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
50825 | goto endlabel2778; | |
50826 | } | |
50827 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
50828 | m68k_areg (regs, dstreg) = dsta; | |
50829 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
50830 | { int flgs = ((int16_t)(src)) < 0; | |
50831 | int flgo = ((int16_t)(dst)) < 0; | |
50832 | int flgn = ((int16_t)(newv)) < 0; | |
50833 | SET_ZFLG (((int16_t)(newv)) == 0); | |
50834 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
50835 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
50836 | COPY_CARRY; | |
50837 | SET_NFLG (flgn != 0); | |
50838 | m68k_incpc(2); | |
50839 | fill_prefetch_2 (); | |
50840 | m68k_write_memory_16(dsta,newv); | |
50841 | }}}}}}}}endlabel2778: ; | |
50842 | return 14; | |
50843 | } | |
50844 | unsigned long CPUFUNC(op_9168_5)(uint32_t opcode) /* SUB */ | |
50845 | { | |
50846 | uint32_t srcreg = ((opcode >> 9) & 7); | |
50847 | uint32_t dstreg = opcode & 7; | |
50848 | OpcodeFamily = 7; CurrentInstrCycles = 16; | |
50849 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
50850 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
50851 | if ((dsta & 1) != 0) { | |
50852 | last_fault_for_exception_3 = dsta; | |
50853 | last_op_for_exception_3 = opcode; | |
50854 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
50855 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
50856 | goto endlabel2779; | |
50857 | } | |
50858 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
50859 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
50860 | { int flgs = ((int16_t)(src)) < 0; | |
50861 | int flgo = ((int16_t)(dst)) < 0; | |
50862 | int flgn = ((int16_t)(newv)) < 0; | |
50863 | SET_ZFLG (((int16_t)(newv)) == 0); | |
50864 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
50865 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
50866 | COPY_CARRY; | |
50867 | SET_NFLG (flgn != 0); | |
50868 | m68k_incpc(4); | |
50869 | fill_prefetch_0 (); | |
50870 | m68k_write_memory_16(dsta,newv); | |
50871 | }}}}}}}}endlabel2779: ; | |
50872 | return 16; | |
50873 | } | |
50874 | unsigned long CPUFUNC(op_9170_5)(uint32_t opcode) /* SUB */ | |
50875 | { | |
50876 | uint32_t srcreg = ((opcode >> 9) & 7); | |
50877 | uint32_t dstreg = opcode & 7; | |
50878 | OpcodeFamily = 7; CurrentInstrCycles = 18; | |
50879 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
50880 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); | |
50881 | BusCyclePenalty += 2; | |
50882 | if ((dsta & 1) != 0) { | |
50883 | last_fault_for_exception_3 = dsta; | |
50884 | last_op_for_exception_3 = opcode; | |
50885 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
50886 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
50887 | goto endlabel2780; | |
50888 | } | |
50889 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
50890 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
50891 | { int flgs = ((int16_t)(src)) < 0; | |
50892 | int flgo = ((int16_t)(dst)) < 0; | |
50893 | int flgn = ((int16_t)(newv)) < 0; | |
50894 | SET_ZFLG (((int16_t)(newv)) == 0); | |
50895 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
50896 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
50897 | COPY_CARRY; | |
50898 | SET_NFLG (flgn != 0); | |
50899 | m68k_incpc(4); | |
50900 | fill_prefetch_0 (); | |
50901 | m68k_write_memory_16(dsta,newv); | |
50902 | }}}}}}}}endlabel2780: ; | |
50903 | return 18; | |
50904 | } | |
50905 | unsigned long CPUFUNC(op_9178_5)(uint32_t opcode) /* SUB */ | |
50906 | { | |
50907 | uint32_t srcreg = ((opcode >> 9) & 7); | |
50908 | OpcodeFamily = 7; CurrentInstrCycles = 16; | |
50909 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
50910 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); | |
50911 | if ((dsta & 1) != 0) { | |
50912 | last_fault_for_exception_3 = dsta; | |
50913 | last_op_for_exception_3 = opcode; | |
50914 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
50915 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
50916 | goto endlabel2781; | |
50917 | } | |
50918 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
50919 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
50920 | { int flgs = ((int16_t)(src)) < 0; | |
50921 | int flgo = ((int16_t)(dst)) < 0; | |
50922 | int flgn = ((int16_t)(newv)) < 0; | |
50923 | SET_ZFLG (((int16_t)(newv)) == 0); | |
50924 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
50925 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
50926 | COPY_CARRY; | |
50927 | SET_NFLG (flgn != 0); | |
50928 | m68k_incpc(4); | |
50929 | fill_prefetch_0 (); | |
50930 | m68k_write_memory_16(dsta,newv); | |
50931 | }}}}}}}}endlabel2781: ; | |
50932 | return 16; | |
50933 | } | |
50934 | unsigned long CPUFUNC(op_9179_5)(uint32_t opcode) /* SUB */ | |
50935 | { | |
50936 | uint32_t srcreg = ((opcode >> 9) & 7); | |
50937 | OpcodeFamily = 7; CurrentInstrCycles = 20; | |
50938 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
50939 | { uint32_t dsta = get_ilong_prefetch(2); | |
50940 | if ((dsta & 1) != 0) { | |
50941 | last_fault_for_exception_3 = dsta; | |
50942 | last_op_for_exception_3 = opcode; | |
50943 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
50944 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
50945 | goto endlabel2782; | |
50946 | } | |
50947 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
50948 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
50949 | { int flgs = ((int16_t)(src)) < 0; | |
50950 | int flgo = ((int16_t)(dst)) < 0; | |
50951 | int flgn = ((int16_t)(newv)) < 0; | |
50952 | SET_ZFLG (((int16_t)(newv)) == 0); | |
50953 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
50954 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
50955 | COPY_CARRY; | |
50956 | SET_NFLG (flgn != 0); | |
50957 | m68k_incpc(6); | |
50958 | fill_prefetch_0 (); | |
50959 | m68k_write_memory_16(dsta,newv); | |
50960 | }}}}}}}}endlabel2782: ; | |
50961 | return 20; | |
50962 | } | |
50963 | unsigned long CPUFUNC(op_9180_5)(uint32_t opcode) /* SUBX */ | |
50964 | { | |
50965 | uint32_t srcreg = (opcode & 7); | |
50966 | uint32_t dstreg = (opcode >> 9) & 7; | |
50967 | OpcodeFamily = 9; CurrentInstrCycles = 8; | |
50968 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
50969 | { int32_t dst = m68k_dreg(regs, dstreg); | |
50970 | { uint32_t newv = dst - src - (GET_XFLG ? 1 : 0); | |
50971 | { int flgs = ((int32_t)(src)) < 0; | |
50972 | int flgo = ((int32_t)(dst)) < 0; | |
50973 | int flgn = ((int32_t)(newv)) < 0; | |
50974 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
50975 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
50976 | COPY_CARRY; | |
50977 | SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0)); | |
50978 | SET_NFLG (((int32_t)(newv)) < 0); | |
50979 | m68k_dreg(regs, dstreg) = (newv); | |
50980 | }}}}}m68k_incpc(2); | |
50981 | fill_prefetch_2 (); | |
50982 | return 8; | |
50983 | } | |
50984 | unsigned long CPUFUNC(op_9188_5)(uint32_t opcode) /* SUBX */ | |
50985 | { | |
50986 | uint32_t srcreg = (opcode & 7); | |
50987 | uint32_t dstreg = (opcode >> 9) & 7; | |
50988 | OpcodeFamily = 9; CurrentInstrCycles = 30; | |
50989 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 4; | |
50990 | if ((srca & 1) != 0) { | |
50991 | last_fault_for_exception_3 = srca; | |
50992 | last_op_for_exception_3 = opcode; | |
50993 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
50994 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
50995 | goto endlabel2784; | |
50996 | } | |
50997 | {{ int32_t src = m68k_read_memory_32(srca); | |
50998 | m68k_areg (regs, srcreg) = srca; | |
50999 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
51000 | if ((dsta & 1) != 0) { | |
51001 | last_fault_for_exception_3 = dsta; | |
51002 | last_op_for_exception_3 = opcode; | |
51003 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
51004 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
51005 | goto endlabel2784; | |
51006 | } | |
51007 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
51008 | m68k_areg (regs, dstreg) = dsta; | |
51009 | { uint32_t newv = dst - src - (GET_XFLG ? 1 : 0); | |
51010 | { int flgs = ((int32_t)(src)) < 0; | |
51011 | int flgo = ((int32_t)(dst)) < 0; | |
51012 | int flgn = ((int32_t)(newv)) < 0; | |
51013 | SET_VFLG ((flgs ^ flgo) & (flgo ^ flgn)); | |
51014 | SET_CFLG (flgs ^ ((flgs ^ flgn) & (flgo ^ flgn))); | |
51015 | COPY_CARRY; | |
51016 | SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0)); | |
51017 | SET_NFLG (((int32_t)(newv)) < 0); | |
51018 | m68k_incpc(2); | |
51019 | fill_prefetch_2 (); | |
51020 | m68k_write_memory_32(dsta,newv); | |
51021 | }}}}}}}}}endlabel2784: ; | |
51022 | return 30; | |
51023 | } | |
51024 | unsigned long CPUFUNC(op_9190_5)(uint32_t opcode) /* SUB */ | |
51025 | { | |
51026 | uint32_t srcreg = ((opcode >> 9) & 7); | |
51027 | uint32_t dstreg = opcode & 7; | |
51028 | OpcodeFamily = 7; CurrentInstrCycles = 20; | |
51029 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
51030 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
51031 | if ((dsta & 1) != 0) { | |
51032 | last_fault_for_exception_3 = dsta; | |
51033 | last_op_for_exception_3 = opcode; | |
51034 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
51035 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
51036 | goto endlabel2785; | |
51037 | } | |
51038 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
51039 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
51040 | { int flgs = ((int32_t)(src)) < 0; | |
51041 | int flgo = ((int32_t)(dst)) < 0; | |
51042 | int flgn = ((int32_t)(newv)) < 0; | |
51043 | SET_ZFLG (((int32_t)(newv)) == 0); | |
51044 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
51045 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
51046 | COPY_CARRY; | |
51047 | SET_NFLG (flgn != 0); | |
51048 | m68k_incpc(2); | |
51049 | fill_prefetch_2 (); | |
51050 | m68k_write_memory_32(dsta,newv); | |
51051 | }}}}}}}}endlabel2785: ; | |
51052 | return 20; | |
51053 | } | |
51054 | unsigned long CPUFUNC(op_9198_5)(uint32_t opcode) /* SUB */ | |
51055 | { | |
51056 | uint32_t srcreg = ((opcode >> 9) & 7); | |
51057 | uint32_t dstreg = opcode & 7; | |
51058 | OpcodeFamily = 7; CurrentInstrCycles = 20; | |
51059 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
51060 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
51061 | if ((dsta & 1) != 0) { | |
51062 | last_fault_for_exception_3 = dsta; | |
51063 | last_op_for_exception_3 = opcode; | |
51064 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
51065 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
51066 | goto endlabel2786; | |
51067 | } | |
51068 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
51069 | m68k_areg(regs, dstreg) += 4; | |
51070 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
51071 | { int flgs = ((int32_t)(src)) < 0; | |
51072 | int flgo = ((int32_t)(dst)) < 0; | |
51073 | int flgn = ((int32_t)(newv)) < 0; | |
51074 | SET_ZFLG (((int32_t)(newv)) == 0); | |
51075 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
51076 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
51077 | COPY_CARRY; | |
51078 | SET_NFLG (flgn != 0); | |
51079 | m68k_incpc(2); | |
51080 | fill_prefetch_2 (); | |
51081 | m68k_write_memory_32(dsta,newv); | |
51082 | }}}}}}}}endlabel2786: ; | |
51083 | return 20; | |
51084 | } | |
51085 | unsigned long CPUFUNC(op_91a0_5)(uint32_t opcode) /* SUB */ | |
51086 | { | |
51087 | uint32_t srcreg = ((opcode >> 9) & 7); | |
51088 | uint32_t dstreg = opcode & 7; | |
51089 | OpcodeFamily = 7; CurrentInstrCycles = 22; | |
51090 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
51091 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
51092 | if ((dsta & 1) != 0) { | |
51093 | last_fault_for_exception_3 = dsta; | |
51094 | last_op_for_exception_3 = opcode; | |
51095 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
51096 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
51097 | goto endlabel2787; | |
51098 | } | |
51099 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
51100 | m68k_areg (regs, dstreg) = dsta; | |
51101 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
51102 | { int flgs = ((int32_t)(src)) < 0; | |
51103 | int flgo = ((int32_t)(dst)) < 0; | |
51104 | int flgn = ((int32_t)(newv)) < 0; | |
51105 | SET_ZFLG (((int32_t)(newv)) == 0); | |
51106 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
51107 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
51108 | COPY_CARRY; | |
51109 | SET_NFLG (flgn != 0); | |
51110 | m68k_incpc(2); | |
51111 | fill_prefetch_2 (); | |
51112 | m68k_write_memory_32(dsta,newv); | |
51113 | }}}}}}}}endlabel2787: ; | |
51114 | return 22; | |
51115 | } | |
51116 | unsigned long CPUFUNC(op_91a8_5)(uint32_t opcode) /* SUB */ | |
51117 | { | |
51118 | uint32_t srcreg = ((opcode >> 9) & 7); | |
51119 | uint32_t dstreg = opcode & 7; | |
51120 | OpcodeFamily = 7; CurrentInstrCycles = 24; | |
51121 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
51122 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
51123 | if ((dsta & 1) != 0) { | |
51124 | last_fault_for_exception_3 = dsta; | |
51125 | last_op_for_exception_3 = opcode; | |
51126 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
51127 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
51128 | goto endlabel2788; | |
51129 | } | |
51130 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
51131 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
51132 | { int flgs = ((int32_t)(src)) < 0; | |
51133 | int flgo = ((int32_t)(dst)) < 0; | |
51134 | int flgn = ((int32_t)(newv)) < 0; | |
51135 | SET_ZFLG (((int32_t)(newv)) == 0); | |
51136 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
51137 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
51138 | COPY_CARRY; | |
51139 | SET_NFLG (flgn != 0); | |
51140 | m68k_incpc(4); | |
51141 | fill_prefetch_0 (); | |
51142 | m68k_write_memory_32(dsta,newv); | |
51143 | }}}}}}}}endlabel2788: ; | |
51144 | return 24; | |
51145 | } | |
51146 | unsigned long CPUFUNC(op_91b0_5)(uint32_t opcode) /* SUB */ | |
51147 | { | |
51148 | uint32_t srcreg = ((opcode >> 9) & 7); | |
51149 | uint32_t dstreg = opcode & 7; | |
51150 | OpcodeFamily = 7; CurrentInstrCycles = 26; | |
51151 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
51152 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); | |
51153 | BusCyclePenalty += 2; | |
51154 | if ((dsta & 1) != 0) { | |
51155 | last_fault_for_exception_3 = dsta; | |
51156 | last_op_for_exception_3 = opcode; | |
51157 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
51158 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
51159 | goto endlabel2789; | |
51160 | } | |
51161 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
51162 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
51163 | { int flgs = ((int32_t)(src)) < 0; | |
51164 | int flgo = ((int32_t)(dst)) < 0; | |
51165 | int flgn = ((int32_t)(newv)) < 0; | |
51166 | SET_ZFLG (((int32_t)(newv)) == 0); | |
51167 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
51168 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
51169 | COPY_CARRY; | |
51170 | SET_NFLG (flgn != 0); | |
51171 | m68k_incpc(4); | |
51172 | fill_prefetch_0 (); | |
51173 | m68k_write_memory_32(dsta,newv); | |
51174 | }}}}}}}}endlabel2789: ; | |
51175 | return 26; | |
51176 | } | |
51177 | unsigned long CPUFUNC(op_91b8_5)(uint32_t opcode) /* SUB */ | |
51178 | { | |
51179 | uint32_t srcreg = ((opcode >> 9) & 7); | |
51180 | OpcodeFamily = 7; CurrentInstrCycles = 24; | |
51181 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
51182 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); | |
51183 | if ((dsta & 1) != 0) { | |
51184 | last_fault_for_exception_3 = dsta; | |
51185 | last_op_for_exception_3 = opcode; | |
51186 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
51187 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
51188 | goto endlabel2790; | |
51189 | } | |
51190 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
51191 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
51192 | { int flgs = ((int32_t)(src)) < 0; | |
51193 | int flgo = ((int32_t)(dst)) < 0; | |
51194 | int flgn = ((int32_t)(newv)) < 0; | |
51195 | SET_ZFLG (((int32_t)(newv)) == 0); | |
51196 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
51197 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
51198 | COPY_CARRY; | |
51199 | SET_NFLG (flgn != 0); | |
51200 | m68k_incpc(4); | |
51201 | fill_prefetch_0 (); | |
51202 | m68k_write_memory_32(dsta,newv); | |
51203 | }}}}}}}}endlabel2790: ; | |
51204 | return 24; | |
51205 | } | |
51206 | unsigned long CPUFUNC(op_91b9_5)(uint32_t opcode) /* SUB */ | |
51207 | { | |
51208 | uint32_t srcreg = ((opcode >> 9) & 7); | |
51209 | OpcodeFamily = 7; CurrentInstrCycles = 28; | |
51210 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
51211 | { uint32_t dsta = get_ilong_prefetch(2); | |
51212 | if ((dsta & 1) != 0) { | |
51213 | last_fault_for_exception_3 = dsta; | |
51214 | last_op_for_exception_3 = opcode; | |
51215 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
51216 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
51217 | goto endlabel2791; | |
51218 | } | |
51219 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
51220 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
51221 | { int flgs = ((int32_t)(src)) < 0; | |
51222 | int flgo = ((int32_t)(dst)) < 0; | |
51223 | int flgn = ((int32_t)(newv)) < 0; | |
51224 | SET_ZFLG (((int32_t)(newv)) == 0); | |
51225 | SET_VFLG ((flgs ^ flgo) & (flgn ^ flgo)); | |
51226 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
51227 | COPY_CARRY; | |
51228 | SET_NFLG (flgn != 0); | |
51229 | m68k_incpc(6); | |
51230 | fill_prefetch_0 (); | |
51231 | m68k_write_memory_32(dsta,newv); | |
51232 | }}}}}}}}endlabel2791: ; | |
51233 | return 28; | |
51234 | } | |
51235 | unsigned long CPUFUNC(op_91c0_5)(uint32_t opcode) /* SUBA */ | |
51236 | { | |
51237 | uint32_t srcreg = (opcode & 7); | |
51238 | uint32_t dstreg = (opcode >> 9) & 7; | |
51239 | OpcodeFamily = 8; CurrentInstrCycles = 8; | |
51240 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
51241 | { int32_t dst = m68k_areg(regs, dstreg); | |
51242 | { uint32_t newv = dst - src; | |
51243 | m68k_areg(regs, dstreg) = (newv); | |
51244 | }}}}m68k_incpc(2); | |
51245 | fill_prefetch_2 (); | |
51246 | return 8; | |
51247 | } | |
51248 | unsigned long CPUFUNC(op_91c8_5)(uint32_t opcode) /* SUBA */ | |
51249 | { | |
51250 | uint32_t srcreg = (opcode & 7); | |
51251 | uint32_t dstreg = (opcode >> 9) & 7; | |
51252 | OpcodeFamily = 8; CurrentInstrCycles = 8; | |
51253 | {{ int32_t src = m68k_areg(regs, srcreg); | |
51254 | { int32_t dst = m68k_areg(regs, dstreg); | |
51255 | { uint32_t newv = dst - src; | |
51256 | m68k_areg(regs, dstreg) = (newv); | |
51257 | }}}}m68k_incpc(2); | |
51258 | fill_prefetch_2 (); | |
51259 | return 8; | |
51260 | } | |
51261 | unsigned long CPUFUNC(op_91d0_5)(uint32_t opcode) /* SUBA */ | |
51262 | { | |
51263 | uint32_t srcreg = (opcode & 7); | |
51264 | uint32_t dstreg = (opcode >> 9) & 7; | |
51265 | OpcodeFamily = 8; CurrentInstrCycles = 14; | |
51266 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
51267 | if ((srca & 1) != 0) { | |
51268 | last_fault_for_exception_3 = srca; | |
51269 | last_op_for_exception_3 = opcode; | |
51270 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
51271 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
51272 | goto endlabel2794; | |
51273 | } | |
51274 | {{ int32_t src = m68k_read_memory_32(srca); | |
51275 | { int32_t dst = m68k_areg(regs, dstreg); | |
51276 | { uint32_t newv = dst - src; | |
51277 | m68k_areg(regs, dstreg) = (newv); | |
51278 | }}}}}}m68k_incpc(2); | |
51279 | fill_prefetch_2 (); | |
51280 | endlabel2794: ; | |
51281 | return 14; | |
51282 | } | |
51283 | unsigned long CPUFUNC(op_91d8_5)(uint32_t opcode) /* SUBA */ | |
51284 | { | |
51285 | uint32_t srcreg = (opcode & 7); | |
51286 | uint32_t dstreg = (opcode >> 9) & 7; | |
51287 | OpcodeFamily = 8; CurrentInstrCycles = 14; | |
51288 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
51289 | if ((srca & 1) != 0) { | |
51290 | last_fault_for_exception_3 = srca; | |
51291 | last_op_for_exception_3 = opcode; | |
51292 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
51293 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
51294 | goto endlabel2795; | |
51295 | } | |
51296 | {{ int32_t src = m68k_read_memory_32(srca); | |
51297 | m68k_areg(regs, srcreg) += 4; | |
51298 | { int32_t dst = m68k_areg(regs, dstreg); | |
51299 | { uint32_t newv = dst - src; | |
51300 | m68k_areg(regs, dstreg) = (newv); | |
51301 | }}}}}}m68k_incpc(2); | |
51302 | fill_prefetch_2 (); | |
51303 | endlabel2795: ; | |
51304 | return 14; | |
51305 | } | |
51306 | unsigned long CPUFUNC(op_91e0_5)(uint32_t opcode) /* SUBA */ | |
51307 | { | |
51308 | uint32_t srcreg = (opcode & 7); | |
51309 | uint32_t dstreg = (opcode >> 9) & 7; | |
51310 | OpcodeFamily = 8; CurrentInstrCycles = 16; | |
51311 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 4; | |
51312 | if ((srca & 1) != 0) { | |
51313 | last_fault_for_exception_3 = srca; | |
51314 | last_op_for_exception_3 = opcode; | |
51315 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
51316 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
51317 | goto endlabel2796; | |
51318 | } | |
51319 | {{ int32_t src = m68k_read_memory_32(srca); | |
51320 | m68k_areg (regs, srcreg) = srca; | |
51321 | { int32_t dst = m68k_areg(regs, dstreg); | |
51322 | { uint32_t newv = dst - src; | |
51323 | m68k_areg(regs, dstreg) = (newv); | |
51324 | }}}}}}m68k_incpc(2); | |
51325 | fill_prefetch_2 (); | |
51326 | endlabel2796: ; | |
51327 | return 16; | |
51328 | } | |
51329 | unsigned long CPUFUNC(op_91e8_5)(uint32_t opcode) /* SUBA */ | |
51330 | { | |
51331 | uint32_t srcreg = (opcode & 7); | |
51332 | uint32_t dstreg = (opcode >> 9) & 7; | |
51333 | OpcodeFamily = 8; CurrentInstrCycles = 18; | |
51334 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
51335 | if ((srca & 1) != 0) { | |
51336 | last_fault_for_exception_3 = srca; | |
51337 | last_op_for_exception_3 = opcode; | |
51338 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
51339 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
51340 | goto endlabel2797; | |
51341 | } | |
51342 | {{ int32_t src = m68k_read_memory_32(srca); | |
51343 | { int32_t dst = m68k_areg(regs, dstreg); | |
51344 | { uint32_t newv = dst - src; | |
51345 | m68k_areg(regs, dstreg) = (newv); | |
51346 | }}}}}}m68k_incpc(4); | |
51347 | fill_prefetch_0 (); | |
51348 | endlabel2797: ; | |
51349 | return 18; | |
51350 | } | |
51351 | unsigned long CPUFUNC(op_91f0_5)(uint32_t opcode) /* SUBA */ | |
51352 | { | |
51353 | uint32_t srcreg = (opcode & 7); | |
51354 | uint32_t dstreg = (opcode >> 9) & 7; | |
51355 | OpcodeFamily = 8; CurrentInstrCycles = 20; | |
51356 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
51357 | BusCyclePenalty += 2; | |
51358 | if ((srca & 1) != 0) { | |
51359 | last_fault_for_exception_3 = srca; | |
51360 | last_op_for_exception_3 = opcode; | |
51361 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
51362 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
51363 | goto endlabel2798; | |
51364 | } | |
51365 | {{ int32_t src = m68k_read_memory_32(srca); | |
51366 | { int32_t dst = m68k_areg(regs, dstreg); | |
51367 | { uint32_t newv = dst - src; | |
51368 | m68k_areg(regs, dstreg) = (newv); | |
51369 | }}}}}}m68k_incpc(4); | |
51370 | fill_prefetch_0 (); | |
51371 | endlabel2798: ; | |
51372 | return 20; | |
51373 | } | |
51374 | unsigned long CPUFUNC(op_91f8_5)(uint32_t opcode) /* SUBA */ | |
51375 | { | |
51376 | uint32_t dstreg = (opcode >> 9) & 7; | |
51377 | OpcodeFamily = 8; CurrentInstrCycles = 18; | |
51378 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
51379 | if ((srca & 1) != 0) { | |
51380 | last_fault_for_exception_3 = srca; | |
51381 | last_op_for_exception_3 = opcode; | |
51382 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
51383 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
51384 | goto endlabel2799; | |
51385 | } | |
51386 | {{ int32_t src = m68k_read_memory_32(srca); | |
51387 | { int32_t dst = m68k_areg(regs, dstreg); | |
51388 | { uint32_t newv = dst - src; | |
51389 | m68k_areg(regs, dstreg) = (newv); | |
51390 | }}}}}}m68k_incpc(4); | |
51391 | fill_prefetch_0 (); | |
51392 | endlabel2799: ; | |
51393 | return 18; | |
51394 | } | |
51395 | unsigned long CPUFUNC(op_91f9_5)(uint32_t opcode) /* SUBA */ | |
51396 | { | |
51397 | uint32_t dstreg = (opcode >> 9) & 7; | |
51398 | OpcodeFamily = 8; CurrentInstrCycles = 22; | |
51399 | {{ uint32_t srca = get_ilong_prefetch(2); | |
51400 | if ((srca & 1) != 0) { | |
51401 | last_fault_for_exception_3 = srca; | |
51402 | last_op_for_exception_3 = opcode; | |
51403 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
51404 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
51405 | goto endlabel2800; | |
51406 | } | |
51407 | {{ int32_t src = m68k_read_memory_32(srca); | |
51408 | { int32_t dst = m68k_areg(regs, dstreg); | |
51409 | { uint32_t newv = dst - src; | |
51410 | m68k_areg(regs, dstreg) = (newv); | |
51411 | }}}}}}m68k_incpc(6); | |
51412 | fill_prefetch_0 (); | |
51413 | endlabel2800: ; | |
51414 | return 22; | |
51415 | } | |
51416 | unsigned long CPUFUNC(op_91fa_5)(uint32_t opcode) /* SUBA */ | |
51417 | { | |
51418 | uint32_t dstreg = (opcode >> 9) & 7; | |
51419 | OpcodeFamily = 8; CurrentInstrCycles = 18; | |
51420 | {{ uint32_t srca = m68k_getpc () + 2; | |
51421 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
51422 | if ((srca & 1) != 0) { | |
51423 | last_fault_for_exception_3 = srca; | |
51424 | last_op_for_exception_3 = opcode; | |
51425 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
51426 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
51427 | goto endlabel2801; | |
51428 | } | |
51429 | {{ int32_t src = m68k_read_memory_32(srca); | |
51430 | { int32_t dst = m68k_areg(regs, dstreg); | |
51431 | { uint32_t newv = dst - src; | |
51432 | m68k_areg(regs, dstreg) = (newv); | |
51433 | }}}}}}m68k_incpc(4); | |
51434 | fill_prefetch_0 (); | |
51435 | endlabel2801: ; | |
51436 | return 18; | |
51437 | } | |
51438 | unsigned long CPUFUNC(op_91fb_5)(uint32_t opcode) /* SUBA */ | |
51439 | { | |
51440 | uint32_t dstreg = (opcode >> 9) & 7; | |
51441 | OpcodeFamily = 8; CurrentInstrCycles = 20; | |
51442 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
51443 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
51444 | BusCyclePenalty += 2; | |
51445 | if ((srca & 1) != 0) { | |
51446 | last_fault_for_exception_3 = srca; | |
51447 | last_op_for_exception_3 = opcode; | |
51448 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
51449 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
51450 | goto endlabel2802; | |
51451 | } | |
51452 | {{ int32_t src = m68k_read_memory_32(srca); | |
51453 | { int32_t dst = m68k_areg(regs, dstreg); | |
51454 | { uint32_t newv = dst - src; | |
51455 | m68k_areg(regs, dstreg) = (newv); | |
51456 | }}}}}}m68k_incpc(4); | |
51457 | fill_prefetch_0 (); | |
51458 | endlabel2802: ; | |
51459 | return 20; | |
51460 | } | |
51461 | unsigned long CPUFUNC(op_91fc_5)(uint32_t opcode) /* SUBA */ | |
51462 | { | |
51463 | uint32_t dstreg = (opcode >> 9) & 7; | |
51464 | OpcodeFamily = 8; CurrentInstrCycles = 16; | |
51465 | {{ int32_t src = get_ilong_prefetch(2); | |
51466 | { int32_t dst = m68k_areg(regs, dstreg); | |
51467 | { uint32_t newv = dst - src; | |
51468 | m68k_areg(regs, dstreg) = (newv); | |
51469 | }}}}m68k_incpc(6); | |
51470 | fill_prefetch_0 (); | |
51471 | return 16; | |
51472 | } | |
51473 | unsigned long CPUFUNC(op_b000_5)(uint32_t opcode) /* CMP */ | |
51474 | { | |
51475 | uint32_t srcreg = (opcode & 7); | |
51476 | uint32_t dstreg = (opcode >> 9) & 7; | |
51477 | OpcodeFamily = 25; CurrentInstrCycles = 4; | |
51478 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
51479 | { int8_t dst = m68k_dreg(regs, dstreg); | |
51480 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
51481 | { int flgs = ((int8_t)(src)) < 0; | |
51482 | int flgo = ((int8_t)(dst)) < 0; | |
51483 | int flgn = ((int8_t)(newv)) < 0; | |
51484 | SET_ZFLG (((int8_t)(newv)) == 0); | |
51485 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
51486 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
51487 | SET_NFLG (flgn != 0); | |
51488 | }}}}}}m68k_incpc(2); | |
51489 | fill_prefetch_2 (); | |
51490 | return 4; | |
51491 | } | |
51492 | unsigned long CPUFUNC(op_b010_5)(uint32_t opcode) /* CMP */ | |
51493 | { | |
51494 | uint32_t srcreg = (opcode & 7); | |
51495 | uint32_t dstreg = (opcode >> 9) & 7; | |
51496 | OpcodeFamily = 25; CurrentInstrCycles = 8; | |
51497 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
51498 | { int8_t src = m68k_read_memory_8(srca); | |
51499 | { int8_t dst = m68k_dreg(regs, dstreg); | |
51500 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
51501 | { int flgs = ((int8_t)(src)) < 0; | |
51502 | int flgo = ((int8_t)(dst)) < 0; | |
51503 | int flgn = ((int8_t)(newv)) < 0; | |
51504 | SET_ZFLG (((int8_t)(newv)) == 0); | |
51505 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
51506 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
51507 | SET_NFLG (flgn != 0); | |
51508 | }}}}}}}m68k_incpc(2); | |
51509 | fill_prefetch_2 (); | |
51510 | return 8; | |
51511 | } | |
51512 | unsigned long CPUFUNC(op_b018_5)(uint32_t opcode) /* CMP */ | |
51513 | { | |
51514 | uint32_t srcreg = (opcode & 7); | |
51515 | uint32_t dstreg = (opcode >> 9) & 7; | |
51516 | OpcodeFamily = 25; CurrentInstrCycles = 8; | |
51517 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
51518 | { int8_t src = m68k_read_memory_8(srca); | |
51519 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
51520 | { int8_t dst = m68k_dreg(regs, dstreg); | |
51521 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
51522 | { int flgs = ((int8_t)(src)) < 0; | |
51523 | int flgo = ((int8_t)(dst)) < 0; | |
51524 | int flgn = ((int8_t)(newv)) < 0; | |
51525 | SET_ZFLG (((int8_t)(newv)) == 0); | |
51526 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
51527 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
51528 | SET_NFLG (flgn != 0); | |
51529 | }}}}}}}m68k_incpc(2); | |
51530 | fill_prefetch_2 (); | |
51531 | return 8; | |
51532 | } | |
51533 | unsigned long CPUFUNC(op_b020_5)(uint32_t opcode) /* CMP */ | |
51534 | { | |
51535 | uint32_t srcreg = (opcode & 7); | |
51536 | uint32_t dstreg = (opcode >> 9) & 7; | |
51537 | OpcodeFamily = 25; CurrentInstrCycles = 10; | |
51538 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
51539 | { int8_t src = m68k_read_memory_8(srca); | |
51540 | m68k_areg (regs, srcreg) = srca; | |
51541 | { int8_t dst = m68k_dreg(regs, dstreg); | |
51542 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
51543 | { int flgs = ((int8_t)(src)) < 0; | |
51544 | int flgo = ((int8_t)(dst)) < 0; | |
51545 | int flgn = ((int8_t)(newv)) < 0; | |
51546 | SET_ZFLG (((int8_t)(newv)) == 0); | |
51547 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
51548 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
51549 | SET_NFLG (flgn != 0); | |
51550 | }}}}}}}m68k_incpc(2); | |
51551 | fill_prefetch_2 (); | |
51552 | return 10; | |
51553 | } | |
51554 | unsigned long CPUFUNC(op_b028_5)(uint32_t opcode) /* CMP */ | |
51555 | { | |
51556 | uint32_t srcreg = (opcode & 7); | |
51557 | uint32_t dstreg = (opcode >> 9) & 7; | |
51558 | OpcodeFamily = 25; CurrentInstrCycles = 12; | |
51559 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
51560 | { int8_t src = m68k_read_memory_8(srca); | |
51561 | { int8_t dst = m68k_dreg(regs, dstreg); | |
51562 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
51563 | { int flgs = ((int8_t)(src)) < 0; | |
51564 | int flgo = ((int8_t)(dst)) < 0; | |
51565 | int flgn = ((int8_t)(newv)) < 0; | |
51566 | SET_ZFLG (((int8_t)(newv)) == 0); | |
51567 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
51568 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
51569 | SET_NFLG (flgn != 0); | |
51570 | }}}}}}}m68k_incpc(4); | |
51571 | fill_prefetch_0 (); | |
51572 | return 12; | |
51573 | } | |
51574 | unsigned long CPUFUNC(op_b030_5)(uint32_t opcode) /* CMP */ | |
51575 | { | |
51576 | uint32_t srcreg = (opcode & 7); | |
51577 | uint32_t dstreg = (opcode >> 9) & 7; | |
51578 | OpcodeFamily = 25; CurrentInstrCycles = 14; | |
51579 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
51580 | BusCyclePenalty += 2; | |
51581 | { int8_t src = m68k_read_memory_8(srca); | |
51582 | { int8_t dst = m68k_dreg(regs, dstreg); | |
51583 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
51584 | { int flgs = ((int8_t)(src)) < 0; | |
51585 | int flgo = ((int8_t)(dst)) < 0; | |
51586 | int flgn = ((int8_t)(newv)) < 0; | |
51587 | SET_ZFLG (((int8_t)(newv)) == 0); | |
51588 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
51589 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
51590 | SET_NFLG (flgn != 0); | |
51591 | }}}}}}}m68k_incpc(4); | |
51592 | fill_prefetch_0 (); | |
51593 | return 14; | |
51594 | } | |
51595 | unsigned long CPUFUNC(op_b038_5)(uint32_t opcode) /* CMP */ | |
51596 | { | |
51597 | uint32_t dstreg = (opcode >> 9) & 7; | |
51598 | OpcodeFamily = 25; CurrentInstrCycles = 12; | |
51599 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
51600 | { int8_t src = m68k_read_memory_8(srca); | |
51601 | { int8_t dst = m68k_dreg(regs, dstreg); | |
51602 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
51603 | { int flgs = ((int8_t)(src)) < 0; | |
51604 | int flgo = ((int8_t)(dst)) < 0; | |
51605 | int flgn = ((int8_t)(newv)) < 0; | |
51606 | SET_ZFLG (((int8_t)(newv)) == 0); | |
51607 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
51608 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
51609 | SET_NFLG (flgn != 0); | |
51610 | }}}}}}}m68k_incpc(4); | |
51611 | fill_prefetch_0 (); | |
51612 | return 12; | |
51613 | } | |
51614 | unsigned long CPUFUNC(op_b039_5)(uint32_t opcode) /* CMP */ | |
51615 | { | |
51616 | uint32_t dstreg = (opcode >> 9) & 7; | |
51617 | OpcodeFamily = 25; CurrentInstrCycles = 16; | |
51618 | {{ uint32_t srca = get_ilong_prefetch(2); | |
51619 | { int8_t src = m68k_read_memory_8(srca); | |
51620 | { int8_t dst = m68k_dreg(regs, dstreg); | |
51621 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
51622 | { int flgs = ((int8_t)(src)) < 0; | |
51623 | int flgo = ((int8_t)(dst)) < 0; | |
51624 | int flgn = ((int8_t)(newv)) < 0; | |
51625 | SET_ZFLG (((int8_t)(newv)) == 0); | |
51626 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
51627 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
51628 | SET_NFLG (flgn != 0); | |
51629 | }}}}}}}m68k_incpc(6); | |
51630 | fill_prefetch_0 (); | |
51631 | return 16; | |
51632 | } | |
51633 | unsigned long CPUFUNC(op_b03a_5)(uint32_t opcode) /* CMP */ | |
51634 | { | |
51635 | uint32_t dstreg = (opcode >> 9) & 7; | |
51636 | OpcodeFamily = 25; CurrentInstrCycles = 12; | |
51637 | {{ uint32_t srca = m68k_getpc () + 2; | |
51638 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
51639 | { int8_t src = m68k_read_memory_8(srca); | |
51640 | { int8_t dst = m68k_dreg(regs, dstreg); | |
51641 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
51642 | { int flgs = ((int8_t)(src)) < 0; | |
51643 | int flgo = ((int8_t)(dst)) < 0; | |
51644 | int flgn = ((int8_t)(newv)) < 0; | |
51645 | SET_ZFLG (((int8_t)(newv)) == 0); | |
51646 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
51647 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
51648 | SET_NFLG (flgn != 0); | |
51649 | }}}}}}}m68k_incpc(4); | |
51650 | fill_prefetch_0 (); | |
51651 | return 12; | |
51652 | } | |
51653 | unsigned long CPUFUNC(op_b03b_5)(uint32_t opcode) /* CMP */ | |
51654 | { | |
51655 | uint32_t dstreg = (opcode >> 9) & 7; | |
51656 | OpcodeFamily = 25; CurrentInstrCycles = 14; | |
51657 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
51658 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
51659 | BusCyclePenalty += 2; | |
51660 | { int8_t src = m68k_read_memory_8(srca); | |
51661 | { int8_t dst = m68k_dreg(regs, dstreg); | |
51662 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
51663 | { int flgs = ((int8_t)(src)) < 0; | |
51664 | int flgo = ((int8_t)(dst)) < 0; | |
51665 | int flgn = ((int8_t)(newv)) < 0; | |
51666 | SET_ZFLG (((int8_t)(newv)) == 0); | |
51667 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
51668 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
51669 | SET_NFLG (flgn != 0); | |
51670 | }}}}}}}m68k_incpc(4); | |
51671 | fill_prefetch_0 (); | |
51672 | return 14; | |
51673 | } | |
51674 | #endif | |
51675 | ||
51676 | #ifdef PART_7 | |
51677 | unsigned long CPUFUNC(op_b03c_5)(uint32_t opcode) /* CMP */ | |
51678 | { | |
51679 | uint32_t dstreg = (opcode >> 9) & 7; | |
51680 | OpcodeFamily = 25; CurrentInstrCycles = 8; | |
51681 | {{ int8_t src = get_ibyte_prefetch(2); | |
51682 | { int8_t dst = m68k_dreg(regs, dstreg); | |
51683 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
51684 | { int flgs = ((int8_t)(src)) < 0; | |
51685 | int flgo = ((int8_t)(dst)) < 0; | |
51686 | int flgn = ((int8_t)(newv)) < 0; | |
51687 | SET_ZFLG (((int8_t)(newv)) == 0); | |
51688 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
51689 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
51690 | SET_NFLG (flgn != 0); | |
51691 | }}}}}}m68k_incpc(4); | |
51692 | fill_prefetch_0 (); | |
51693 | return 8; | |
51694 | } | |
51695 | unsigned long CPUFUNC(op_b040_5)(uint32_t opcode) /* CMP */ | |
51696 | { | |
51697 | uint32_t srcreg = (opcode & 7); | |
51698 | uint32_t dstreg = (opcode >> 9) & 7; | |
51699 | OpcodeFamily = 25; CurrentInstrCycles = 4; | |
51700 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
51701 | { int16_t dst = m68k_dreg(regs, dstreg); | |
51702 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
51703 | { int flgs = ((int16_t)(src)) < 0; | |
51704 | int flgo = ((int16_t)(dst)) < 0; | |
51705 | int flgn = ((int16_t)(newv)) < 0; | |
51706 | SET_ZFLG (((int16_t)(newv)) == 0); | |
51707 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
51708 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
51709 | SET_NFLG (flgn != 0); | |
51710 | }}}}}}m68k_incpc(2); | |
51711 | fill_prefetch_2 (); | |
51712 | return 4; | |
51713 | } | |
51714 | unsigned long CPUFUNC(op_b048_5)(uint32_t opcode) /* CMP */ | |
51715 | { | |
51716 | uint32_t srcreg = (opcode & 7); | |
51717 | uint32_t dstreg = (opcode >> 9) & 7; | |
51718 | OpcodeFamily = 25; CurrentInstrCycles = 4; | |
51719 | {{ int16_t src = m68k_areg(regs, srcreg); | |
51720 | { int16_t dst = m68k_dreg(regs, dstreg); | |
51721 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
51722 | { int flgs = ((int16_t)(src)) < 0; | |
51723 | int flgo = ((int16_t)(dst)) < 0; | |
51724 | int flgn = ((int16_t)(newv)) < 0; | |
51725 | SET_ZFLG (((int16_t)(newv)) == 0); | |
51726 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
51727 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
51728 | SET_NFLG (flgn != 0); | |
51729 | }}}}}}m68k_incpc(2); | |
51730 | fill_prefetch_2 (); | |
51731 | return 4; | |
51732 | } | |
51733 | unsigned long CPUFUNC(op_b050_5)(uint32_t opcode) /* CMP */ | |
51734 | { | |
51735 | uint32_t srcreg = (opcode & 7); | |
51736 | uint32_t dstreg = (opcode >> 9) & 7; | |
51737 | OpcodeFamily = 25; CurrentInstrCycles = 8; | |
51738 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
51739 | if ((srca & 1) != 0) { | |
51740 | last_fault_for_exception_3 = srca; | |
51741 | last_op_for_exception_3 = opcode; | |
51742 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
51743 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
51744 | goto endlabel2817; | |
51745 | } | |
51746 | {{ int16_t src = m68k_read_memory_16(srca); | |
51747 | { int16_t dst = m68k_dreg(regs, dstreg); | |
51748 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
51749 | { int flgs = ((int16_t)(src)) < 0; | |
51750 | int flgo = ((int16_t)(dst)) < 0; | |
51751 | int flgn = ((int16_t)(newv)) < 0; | |
51752 | SET_ZFLG (((int16_t)(newv)) == 0); | |
51753 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
51754 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
51755 | SET_NFLG (flgn != 0); | |
51756 | }}}}}}}}m68k_incpc(2); | |
51757 | fill_prefetch_2 (); | |
51758 | endlabel2817: ; | |
51759 | return 8; | |
51760 | } | |
51761 | unsigned long CPUFUNC(op_b058_5)(uint32_t opcode) /* CMP */ | |
51762 | { | |
51763 | uint32_t srcreg = (opcode & 7); | |
51764 | uint32_t dstreg = (opcode >> 9) & 7; | |
51765 | OpcodeFamily = 25; CurrentInstrCycles = 8; | |
51766 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
51767 | if ((srca & 1) != 0) { | |
51768 | last_fault_for_exception_3 = srca; | |
51769 | last_op_for_exception_3 = opcode; | |
51770 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
51771 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
51772 | goto endlabel2818; | |
51773 | } | |
51774 | {{ int16_t src = m68k_read_memory_16(srca); | |
51775 | m68k_areg(regs, srcreg) += 2; | |
51776 | { int16_t dst = m68k_dreg(regs, dstreg); | |
51777 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
51778 | { int flgs = ((int16_t)(src)) < 0; | |
51779 | int flgo = ((int16_t)(dst)) < 0; | |
51780 | int flgn = ((int16_t)(newv)) < 0; | |
51781 | SET_ZFLG (((int16_t)(newv)) == 0); | |
51782 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
51783 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
51784 | SET_NFLG (flgn != 0); | |
51785 | }}}}}}}}m68k_incpc(2); | |
51786 | fill_prefetch_2 (); | |
51787 | endlabel2818: ; | |
51788 | return 8; | |
51789 | } | |
51790 | unsigned long CPUFUNC(op_b060_5)(uint32_t opcode) /* CMP */ | |
51791 | { | |
51792 | uint32_t srcreg = (opcode & 7); | |
51793 | uint32_t dstreg = (opcode >> 9) & 7; | |
51794 | OpcodeFamily = 25; CurrentInstrCycles = 10; | |
51795 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
51796 | if ((srca & 1) != 0) { | |
51797 | last_fault_for_exception_3 = srca; | |
51798 | last_op_for_exception_3 = opcode; | |
51799 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
51800 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
51801 | goto endlabel2819; | |
51802 | } | |
51803 | {{ int16_t src = m68k_read_memory_16(srca); | |
51804 | m68k_areg (regs, srcreg) = srca; | |
51805 | { int16_t dst = m68k_dreg(regs, dstreg); | |
51806 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
51807 | { int flgs = ((int16_t)(src)) < 0; | |
51808 | int flgo = ((int16_t)(dst)) < 0; | |
51809 | int flgn = ((int16_t)(newv)) < 0; | |
51810 | SET_ZFLG (((int16_t)(newv)) == 0); | |
51811 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
51812 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
51813 | SET_NFLG (flgn != 0); | |
51814 | }}}}}}}}m68k_incpc(2); | |
51815 | fill_prefetch_2 (); | |
51816 | endlabel2819: ; | |
51817 | return 10; | |
51818 | } | |
51819 | unsigned long CPUFUNC(op_b068_5)(uint32_t opcode) /* CMP */ | |
51820 | { | |
51821 | uint32_t srcreg = (opcode & 7); | |
51822 | uint32_t dstreg = (opcode >> 9) & 7; | |
51823 | OpcodeFamily = 25; CurrentInstrCycles = 12; | |
51824 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
51825 | if ((srca & 1) != 0) { | |
51826 | last_fault_for_exception_3 = srca; | |
51827 | last_op_for_exception_3 = opcode; | |
51828 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
51829 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
51830 | goto endlabel2820; | |
51831 | } | |
51832 | {{ int16_t src = m68k_read_memory_16(srca); | |
51833 | { int16_t dst = m68k_dreg(regs, dstreg); | |
51834 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
51835 | { int flgs = ((int16_t)(src)) < 0; | |
51836 | int flgo = ((int16_t)(dst)) < 0; | |
51837 | int flgn = ((int16_t)(newv)) < 0; | |
51838 | SET_ZFLG (((int16_t)(newv)) == 0); | |
51839 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
51840 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
51841 | SET_NFLG (flgn != 0); | |
51842 | }}}}}}}}m68k_incpc(4); | |
51843 | fill_prefetch_0 (); | |
51844 | endlabel2820: ; | |
51845 | return 12; | |
51846 | } | |
51847 | unsigned long CPUFUNC(op_b070_5)(uint32_t opcode) /* CMP */ | |
51848 | { | |
51849 | uint32_t srcreg = (opcode & 7); | |
51850 | uint32_t dstreg = (opcode >> 9) & 7; | |
51851 | OpcodeFamily = 25; CurrentInstrCycles = 14; | |
51852 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
51853 | BusCyclePenalty += 2; | |
51854 | if ((srca & 1) != 0) { | |
51855 | last_fault_for_exception_3 = srca; | |
51856 | last_op_for_exception_3 = opcode; | |
51857 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
51858 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
51859 | goto endlabel2821; | |
51860 | } | |
51861 | {{ int16_t src = m68k_read_memory_16(srca); | |
51862 | { int16_t dst = m68k_dreg(regs, dstreg); | |
51863 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
51864 | { int flgs = ((int16_t)(src)) < 0; | |
51865 | int flgo = ((int16_t)(dst)) < 0; | |
51866 | int flgn = ((int16_t)(newv)) < 0; | |
51867 | SET_ZFLG (((int16_t)(newv)) == 0); | |
51868 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
51869 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
51870 | SET_NFLG (flgn != 0); | |
51871 | }}}}}}}}m68k_incpc(4); | |
51872 | fill_prefetch_0 (); | |
51873 | endlabel2821: ; | |
51874 | return 14; | |
51875 | } | |
51876 | unsigned long CPUFUNC(op_b078_5)(uint32_t opcode) /* CMP */ | |
51877 | { | |
51878 | uint32_t dstreg = (opcode >> 9) & 7; | |
51879 | OpcodeFamily = 25; CurrentInstrCycles = 12; | |
51880 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
51881 | if ((srca & 1) != 0) { | |
51882 | last_fault_for_exception_3 = srca; | |
51883 | last_op_for_exception_3 = opcode; | |
51884 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
51885 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
51886 | goto endlabel2822; | |
51887 | } | |
51888 | {{ int16_t src = m68k_read_memory_16(srca); | |
51889 | { int16_t dst = m68k_dreg(regs, dstreg); | |
51890 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
51891 | { int flgs = ((int16_t)(src)) < 0; | |
51892 | int flgo = ((int16_t)(dst)) < 0; | |
51893 | int flgn = ((int16_t)(newv)) < 0; | |
51894 | SET_ZFLG (((int16_t)(newv)) == 0); | |
51895 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
51896 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
51897 | SET_NFLG (flgn != 0); | |
51898 | }}}}}}}}m68k_incpc(4); | |
51899 | fill_prefetch_0 (); | |
51900 | endlabel2822: ; | |
51901 | return 12; | |
51902 | } | |
51903 | unsigned long CPUFUNC(op_b079_5)(uint32_t opcode) /* CMP */ | |
51904 | { | |
51905 | uint32_t dstreg = (opcode >> 9) & 7; | |
51906 | OpcodeFamily = 25; CurrentInstrCycles = 16; | |
51907 | {{ uint32_t srca = get_ilong_prefetch(2); | |
51908 | if ((srca & 1) != 0) { | |
51909 | last_fault_for_exception_3 = srca; | |
51910 | last_op_for_exception_3 = opcode; | |
51911 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
51912 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
51913 | goto endlabel2823; | |
51914 | } | |
51915 | {{ int16_t src = m68k_read_memory_16(srca); | |
51916 | { int16_t dst = m68k_dreg(regs, dstreg); | |
51917 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
51918 | { int flgs = ((int16_t)(src)) < 0; | |
51919 | int flgo = ((int16_t)(dst)) < 0; | |
51920 | int flgn = ((int16_t)(newv)) < 0; | |
51921 | SET_ZFLG (((int16_t)(newv)) == 0); | |
51922 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
51923 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
51924 | SET_NFLG (flgn != 0); | |
51925 | }}}}}}}}m68k_incpc(6); | |
51926 | fill_prefetch_0 (); | |
51927 | endlabel2823: ; | |
51928 | return 16; | |
51929 | } | |
51930 | unsigned long CPUFUNC(op_b07a_5)(uint32_t opcode) /* CMP */ | |
51931 | { | |
51932 | uint32_t dstreg = (opcode >> 9) & 7; | |
51933 | OpcodeFamily = 25; CurrentInstrCycles = 12; | |
51934 | {{ uint32_t srca = m68k_getpc () + 2; | |
51935 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
51936 | if ((srca & 1) != 0) { | |
51937 | last_fault_for_exception_3 = srca; | |
51938 | last_op_for_exception_3 = opcode; | |
51939 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
51940 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
51941 | goto endlabel2824; | |
51942 | } | |
51943 | {{ int16_t src = m68k_read_memory_16(srca); | |
51944 | { int16_t dst = m68k_dreg(regs, dstreg); | |
51945 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
51946 | { int flgs = ((int16_t)(src)) < 0; | |
51947 | int flgo = ((int16_t)(dst)) < 0; | |
51948 | int flgn = ((int16_t)(newv)) < 0; | |
51949 | SET_ZFLG (((int16_t)(newv)) == 0); | |
51950 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
51951 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
51952 | SET_NFLG (flgn != 0); | |
51953 | }}}}}}}}m68k_incpc(4); | |
51954 | fill_prefetch_0 (); | |
51955 | endlabel2824: ; | |
51956 | return 12; | |
51957 | } | |
51958 | unsigned long CPUFUNC(op_b07b_5)(uint32_t opcode) /* CMP */ | |
51959 | { | |
51960 | uint32_t dstreg = (opcode >> 9) & 7; | |
51961 | OpcodeFamily = 25; CurrentInstrCycles = 14; | |
51962 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
51963 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
51964 | BusCyclePenalty += 2; | |
51965 | if ((srca & 1) != 0) { | |
51966 | last_fault_for_exception_3 = srca; | |
51967 | last_op_for_exception_3 = opcode; | |
51968 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
51969 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
51970 | goto endlabel2825; | |
51971 | } | |
51972 | {{ int16_t src = m68k_read_memory_16(srca); | |
51973 | { int16_t dst = m68k_dreg(regs, dstreg); | |
51974 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
51975 | { int flgs = ((int16_t)(src)) < 0; | |
51976 | int flgo = ((int16_t)(dst)) < 0; | |
51977 | int flgn = ((int16_t)(newv)) < 0; | |
51978 | SET_ZFLG (((int16_t)(newv)) == 0); | |
51979 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
51980 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
51981 | SET_NFLG (flgn != 0); | |
51982 | }}}}}}}}m68k_incpc(4); | |
51983 | fill_prefetch_0 (); | |
51984 | endlabel2825: ; | |
51985 | return 14; | |
51986 | } | |
51987 | unsigned long CPUFUNC(op_b07c_5)(uint32_t opcode) /* CMP */ | |
51988 | { | |
51989 | uint32_t dstreg = (opcode >> 9) & 7; | |
51990 | OpcodeFamily = 25; CurrentInstrCycles = 8; | |
51991 | {{ int16_t src = get_iword_prefetch(2); | |
51992 | { int16_t dst = m68k_dreg(regs, dstreg); | |
51993 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
51994 | { int flgs = ((int16_t)(src)) < 0; | |
51995 | int flgo = ((int16_t)(dst)) < 0; | |
51996 | int flgn = ((int16_t)(newv)) < 0; | |
51997 | SET_ZFLG (((int16_t)(newv)) == 0); | |
51998 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
51999 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
52000 | SET_NFLG (flgn != 0); | |
52001 | }}}}}}m68k_incpc(4); | |
52002 | fill_prefetch_0 (); | |
52003 | return 8; | |
52004 | } | |
52005 | unsigned long CPUFUNC(op_b080_5)(uint32_t opcode) /* CMP */ | |
52006 | { | |
52007 | uint32_t srcreg = (opcode & 7); | |
52008 | uint32_t dstreg = (opcode >> 9) & 7; | |
52009 | OpcodeFamily = 25; CurrentInstrCycles = 6; | |
52010 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
52011 | { int32_t dst = m68k_dreg(regs, dstreg); | |
52012 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
52013 | { int flgs = ((int32_t)(src)) < 0; | |
52014 | int flgo = ((int32_t)(dst)) < 0; | |
52015 | int flgn = ((int32_t)(newv)) < 0; | |
52016 | SET_ZFLG (((int32_t)(newv)) == 0); | |
52017 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
52018 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
52019 | SET_NFLG (flgn != 0); | |
52020 | }}}}}}m68k_incpc(2); | |
52021 | fill_prefetch_2 (); | |
52022 | return 6; | |
52023 | } | |
52024 | unsigned long CPUFUNC(op_b088_5)(uint32_t opcode) /* CMP */ | |
52025 | { | |
52026 | uint32_t srcreg = (opcode & 7); | |
52027 | uint32_t dstreg = (opcode >> 9) & 7; | |
52028 | OpcodeFamily = 25; CurrentInstrCycles = 6; | |
52029 | {{ int32_t src = m68k_areg(regs, srcreg); | |
52030 | { int32_t dst = m68k_dreg(regs, dstreg); | |
52031 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
52032 | { int flgs = ((int32_t)(src)) < 0; | |
52033 | int flgo = ((int32_t)(dst)) < 0; | |
52034 | int flgn = ((int32_t)(newv)) < 0; | |
52035 | SET_ZFLG (((int32_t)(newv)) == 0); | |
52036 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
52037 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
52038 | SET_NFLG (flgn != 0); | |
52039 | }}}}}}m68k_incpc(2); | |
52040 | fill_prefetch_2 (); | |
52041 | return 6; | |
52042 | } | |
52043 | unsigned long CPUFUNC(op_b090_5)(uint32_t opcode) /* CMP */ | |
52044 | { | |
52045 | uint32_t srcreg = (opcode & 7); | |
52046 | uint32_t dstreg = (opcode >> 9) & 7; | |
52047 | OpcodeFamily = 25; CurrentInstrCycles = 14; | |
52048 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
52049 | if ((srca & 1) != 0) { | |
52050 | last_fault_for_exception_3 = srca; | |
52051 | last_op_for_exception_3 = opcode; | |
52052 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
52053 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
52054 | goto endlabel2829; | |
52055 | } | |
52056 | {{ int32_t src = m68k_read_memory_32(srca); | |
52057 | { int32_t dst = m68k_dreg(regs, dstreg); | |
52058 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
52059 | { int flgs = ((int32_t)(src)) < 0; | |
52060 | int flgo = ((int32_t)(dst)) < 0; | |
52061 | int flgn = ((int32_t)(newv)) < 0; | |
52062 | SET_ZFLG (((int32_t)(newv)) == 0); | |
52063 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
52064 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
52065 | SET_NFLG (flgn != 0); | |
52066 | }}}}}}}}m68k_incpc(2); | |
52067 | fill_prefetch_2 (); | |
52068 | endlabel2829: ; | |
52069 | return 14; | |
52070 | } | |
52071 | unsigned long CPUFUNC(op_b098_5)(uint32_t opcode) /* CMP */ | |
52072 | { | |
52073 | uint32_t srcreg = (opcode & 7); | |
52074 | uint32_t dstreg = (opcode >> 9) & 7; | |
52075 | OpcodeFamily = 25; CurrentInstrCycles = 14; | |
52076 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
52077 | if ((srca & 1) != 0) { | |
52078 | last_fault_for_exception_3 = srca; | |
52079 | last_op_for_exception_3 = opcode; | |
52080 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
52081 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
52082 | goto endlabel2830; | |
52083 | } | |
52084 | {{ int32_t src = m68k_read_memory_32(srca); | |
52085 | m68k_areg(regs, srcreg) += 4; | |
52086 | { int32_t dst = m68k_dreg(regs, dstreg); | |
52087 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
52088 | { int flgs = ((int32_t)(src)) < 0; | |
52089 | int flgo = ((int32_t)(dst)) < 0; | |
52090 | int flgn = ((int32_t)(newv)) < 0; | |
52091 | SET_ZFLG (((int32_t)(newv)) == 0); | |
52092 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
52093 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
52094 | SET_NFLG (flgn != 0); | |
52095 | }}}}}}}}m68k_incpc(2); | |
52096 | fill_prefetch_2 (); | |
52097 | endlabel2830: ; | |
52098 | return 14; | |
52099 | } | |
52100 | unsigned long CPUFUNC(op_b0a0_5)(uint32_t opcode) /* CMP */ | |
52101 | { | |
52102 | uint32_t srcreg = (opcode & 7); | |
52103 | uint32_t dstreg = (opcode >> 9) & 7; | |
52104 | OpcodeFamily = 25; CurrentInstrCycles = 16; | |
52105 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 4; | |
52106 | if ((srca & 1) != 0) { | |
52107 | last_fault_for_exception_3 = srca; | |
52108 | last_op_for_exception_3 = opcode; | |
52109 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
52110 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
52111 | goto endlabel2831; | |
52112 | } | |
52113 | {{ int32_t src = m68k_read_memory_32(srca); | |
52114 | m68k_areg (regs, srcreg) = srca; | |
52115 | { int32_t dst = m68k_dreg(regs, dstreg); | |
52116 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
52117 | { int flgs = ((int32_t)(src)) < 0; | |
52118 | int flgo = ((int32_t)(dst)) < 0; | |
52119 | int flgn = ((int32_t)(newv)) < 0; | |
52120 | SET_ZFLG (((int32_t)(newv)) == 0); | |
52121 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
52122 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
52123 | SET_NFLG (flgn != 0); | |
52124 | }}}}}}}}m68k_incpc(2); | |
52125 | fill_prefetch_2 (); | |
52126 | endlabel2831: ; | |
52127 | return 16; | |
52128 | } | |
52129 | unsigned long CPUFUNC(op_b0a8_5)(uint32_t opcode) /* CMP */ | |
52130 | { | |
52131 | uint32_t srcreg = (opcode & 7); | |
52132 | uint32_t dstreg = (opcode >> 9) & 7; | |
52133 | OpcodeFamily = 25; CurrentInstrCycles = 18; | |
52134 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
52135 | if ((srca & 1) != 0) { | |
52136 | last_fault_for_exception_3 = srca; | |
52137 | last_op_for_exception_3 = opcode; | |
52138 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
52139 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
52140 | goto endlabel2832; | |
52141 | } | |
52142 | {{ int32_t src = m68k_read_memory_32(srca); | |
52143 | { int32_t dst = m68k_dreg(regs, dstreg); | |
52144 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
52145 | { int flgs = ((int32_t)(src)) < 0; | |
52146 | int flgo = ((int32_t)(dst)) < 0; | |
52147 | int flgn = ((int32_t)(newv)) < 0; | |
52148 | SET_ZFLG (((int32_t)(newv)) == 0); | |
52149 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
52150 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
52151 | SET_NFLG (flgn != 0); | |
52152 | }}}}}}}}m68k_incpc(4); | |
52153 | fill_prefetch_0 (); | |
52154 | endlabel2832: ; | |
52155 | return 18; | |
52156 | } | |
52157 | unsigned long CPUFUNC(op_b0b0_5)(uint32_t opcode) /* CMP */ | |
52158 | { | |
52159 | uint32_t srcreg = (opcode & 7); | |
52160 | uint32_t dstreg = (opcode >> 9) & 7; | |
52161 | OpcodeFamily = 25; CurrentInstrCycles = 20; | |
52162 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
52163 | BusCyclePenalty += 2; | |
52164 | if ((srca & 1) != 0) { | |
52165 | last_fault_for_exception_3 = srca; | |
52166 | last_op_for_exception_3 = opcode; | |
52167 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
52168 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
52169 | goto endlabel2833; | |
52170 | } | |
52171 | {{ int32_t src = m68k_read_memory_32(srca); | |
52172 | { int32_t dst = m68k_dreg(regs, dstreg); | |
52173 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
52174 | { int flgs = ((int32_t)(src)) < 0; | |
52175 | int flgo = ((int32_t)(dst)) < 0; | |
52176 | int flgn = ((int32_t)(newv)) < 0; | |
52177 | SET_ZFLG (((int32_t)(newv)) == 0); | |
52178 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
52179 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
52180 | SET_NFLG (flgn != 0); | |
52181 | }}}}}}}}m68k_incpc(4); | |
52182 | fill_prefetch_0 (); | |
52183 | endlabel2833: ; | |
52184 | return 20; | |
52185 | } | |
52186 | unsigned long CPUFUNC(op_b0b8_5)(uint32_t opcode) /* CMP */ | |
52187 | { | |
52188 | uint32_t dstreg = (opcode >> 9) & 7; | |
52189 | OpcodeFamily = 25; CurrentInstrCycles = 18; | |
52190 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
52191 | if ((srca & 1) != 0) { | |
52192 | last_fault_for_exception_3 = srca; | |
52193 | last_op_for_exception_3 = opcode; | |
52194 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
52195 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
52196 | goto endlabel2834; | |
52197 | } | |
52198 | {{ int32_t src = m68k_read_memory_32(srca); | |
52199 | { int32_t dst = m68k_dreg(regs, dstreg); | |
52200 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
52201 | { int flgs = ((int32_t)(src)) < 0; | |
52202 | int flgo = ((int32_t)(dst)) < 0; | |
52203 | int flgn = ((int32_t)(newv)) < 0; | |
52204 | SET_ZFLG (((int32_t)(newv)) == 0); | |
52205 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
52206 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
52207 | SET_NFLG (flgn != 0); | |
52208 | }}}}}}}}m68k_incpc(4); | |
52209 | fill_prefetch_0 (); | |
52210 | endlabel2834: ; | |
52211 | return 18; | |
52212 | } | |
52213 | unsigned long CPUFUNC(op_b0b9_5)(uint32_t opcode) /* CMP */ | |
52214 | { | |
52215 | uint32_t dstreg = (opcode >> 9) & 7; | |
52216 | OpcodeFamily = 25; CurrentInstrCycles = 22; | |
52217 | {{ uint32_t srca = get_ilong_prefetch(2); | |
52218 | if ((srca & 1) != 0) { | |
52219 | last_fault_for_exception_3 = srca; | |
52220 | last_op_for_exception_3 = opcode; | |
52221 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
52222 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
52223 | goto endlabel2835; | |
52224 | } | |
52225 | {{ int32_t src = m68k_read_memory_32(srca); | |
52226 | { int32_t dst = m68k_dreg(regs, dstreg); | |
52227 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
52228 | { int flgs = ((int32_t)(src)) < 0; | |
52229 | int flgo = ((int32_t)(dst)) < 0; | |
52230 | int flgn = ((int32_t)(newv)) < 0; | |
52231 | SET_ZFLG (((int32_t)(newv)) == 0); | |
52232 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
52233 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
52234 | SET_NFLG (flgn != 0); | |
52235 | }}}}}}}}m68k_incpc(6); | |
52236 | fill_prefetch_0 (); | |
52237 | endlabel2835: ; | |
52238 | return 22; | |
52239 | } | |
52240 | unsigned long CPUFUNC(op_b0ba_5)(uint32_t opcode) /* CMP */ | |
52241 | { | |
52242 | uint32_t dstreg = (opcode >> 9) & 7; | |
52243 | OpcodeFamily = 25; CurrentInstrCycles = 18; | |
52244 | {{ uint32_t srca = m68k_getpc () + 2; | |
52245 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
52246 | if ((srca & 1) != 0) { | |
52247 | last_fault_for_exception_3 = srca; | |
52248 | last_op_for_exception_3 = opcode; | |
52249 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
52250 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
52251 | goto endlabel2836; | |
52252 | } | |
52253 | {{ int32_t src = m68k_read_memory_32(srca); | |
52254 | { int32_t dst = m68k_dreg(regs, dstreg); | |
52255 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
52256 | { int flgs = ((int32_t)(src)) < 0; | |
52257 | int flgo = ((int32_t)(dst)) < 0; | |
52258 | int flgn = ((int32_t)(newv)) < 0; | |
52259 | SET_ZFLG (((int32_t)(newv)) == 0); | |
52260 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
52261 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
52262 | SET_NFLG (flgn != 0); | |
52263 | }}}}}}}}m68k_incpc(4); | |
52264 | fill_prefetch_0 (); | |
52265 | endlabel2836: ; | |
52266 | return 18; | |
52267 | } | |
52268 | unsigned long CPUFUNC(op_b0bb_5)(uint32_t opcode) /* CMP */ | |
52269 | { | |
52270 | uint32_t dstreg = (opcode >> 9) & 7; | |
52271 | OpcodeFamily = 25; CurrentInstrCycles = 20; | |
52272 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
52273 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
52274 | BusCyclePenalty += 2; | |
52275 | if ((srca & 1) != 0) { | |
52276 | last_fault_for_exception_3 = srca; | |
52277 | last_op_for_exception_3 = opcode; | |
52278 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
52279 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
52280 | goto endlabel2837; | |
52281 | } | |
52282 | {{ int32_t src = m68k_read_memory_32(srca); | |
52283 | { int32_t dst = m68k_dreg(regs, dstreg); | |
52284 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
52285 | { int flgs = ((int32_t)(src)) < 0; | |
52286 | int flgo = ((int32_t)(dst)) < 0; | |
52287 | int flgn = ((int32_t)(newv)) < 0; | |
52288 | SET_ZFLG (((int32_t)(newv)) == 0); | |
52289 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
52290 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
52291 | SET_NFLG (flgn != 0); | |
52292 | }}}}}}}}m68k_incpc(4); | |
52293 | fill_prefetch_0 (); | |
52294 | endlabel2837: ; | |
52295 | return 20; | |
52296 | } | |
52297 | unsigned long CPUFUNC(op_b0bc_5)(uint32_t opcode) /* CMP */ | |
52298 | { | |
52299 | uint32_t dstreg = (opcode >> 9) & 7; | |
52300 | OpcodeFamily = 25; CurrentInstrCycles = 14; | |
52301 | {{ int32_t src = get_ilong_prefetch(2); | |
52302 | { int32_t dst = m68k_dreg(regs, dstreg); | |
52303 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
52304 | { int flgs = ((int32_t)(src)) < 0; | |
52305 | int flgo = ((int32_t)(dst)) < 0; | |
52306 | int flgn = ((int32_t)(newv)) < 0; | |
52307 | SET_ZFLG (((int32_t)(newv)) == 0); | |
52308 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
52309 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
52310 | SET_NFLG (flgn != 0); | |
52311 | }}}}}}m68k_incpc(6); | |
52312 | fill_prefetch_0 (); | |
52313 | return 14; | |
52314 | } | |
52315 | unsigned long CPUFUNC(op_b0c0_5)(uint32_t opcode) /* CMPA */ | |
52316 | { | |
52317 | uint32_t srcreg = (opcode & 7); | |
52318 | uint32_t dstreg = (opcode >> 9) & 7; | |
52319 | OpcodeFamily = 27; CurrentInstrCycles = 6; | |
52320 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
52321 | { int32_t dst = m68k_areg(regs, dstreg); | |
52322 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
52323 | { int flgs = ((int32_t)(src)) < 0; | |
52324 | int flgo = ((int32_t)(dst)) < 0; | |
52325 | int flgn = ((int32_t)(newv)) < 0; | |
52326 | SET_ZFLG (((int32_t)(newv)) == 0); | |
52327 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
52328 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
52329 | SET_NFLG (flgn != 0); | |
52330 | }}}}}}m68k_incpc(2); | |
52331 | fill_prefetch_2 (); | |
52332 | return 6; | |
52333 | } | |
52334 | unsigned long CPUFUNC(op_b0c8_5)(uint32_t opcode) /* CMPA */ | |
52335 | { | |
52336 | uint32_t srcreg = (opcode & 7); | |
52337 | uint32_t dstreg = (opcode >> 9) & 7; | |
52338 | OpcodeFamily = 27; CurrentInstrCycles = 6; | |
52339 | {{ int16_t src = m68k_areg(regs, srcreg); | |
52340 | { int32_t dst = m68k_areg(regs, dstreg); | |
52341 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
52342 | { int flgs = ((int32_t)(src)) < 0; | |
52343 | int flgo = ((int32_t)(dst)) < 0; | |
52344 | int flgn = ((int32_t)(newv)) < 0; | |
52345 | SET_ZFLG (((int32_t)(newv)) == 0); | |
52346 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
52347 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
52348 | SET_NFLG (flgn != 0); | |
52349 | }}}}}}m68k_incpc(2); | |
52350 | fill_prefetch_2 (); | |
52351 | return 6; | |
52352 | } | |
52353 | unsigned long CPUFUNC(op_b0d0_5)(uint32_t opcode) /* CMPA */ | |
52354 | { | |
52355 | uint32_t srcreg = (opcode & 7); | |
52356 | uint32_t dstreg = (opcode >> 9) & 7; | |
52357 | OpcodeFamily = 27; CurrentInstrCycles = 10; | |
52358 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
52359 | if ((srca & 1) != 0) { | |
52360 | last_fault_for_exception_3 = srca; | |
52361 | last_op_for_exception_3 = opcode; | |
52362 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
52363 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
52364 | goto endlabel2841; | |
52365 | } | |
52366 | {{ int16_t src = m68k_read_memory_16(srca); | |
52367 | { int32_t dst = m68k_areg(regs, dstreg); | |
52368 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
52369 | { int flgs = ((int32_t)(src)) < 0; | |
52370 | int flgo = ((int32_t)(dst)) < 0; | |
52371 | int flgn = ((int32_t)(newv)) < 0; | |
52372 | SET_ZFLG (((int32_t)(newv)) == 0); | |
52373 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
52374 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
52375 | SET_NFLG (flgn != 0); | |
52376 | }}}}}}}}m68k_incpc(2); | |
52377 | fill_prefetch_2 (); | |
52378 | endlabel2841: ; | |
52379 | return 10; | |
52380 | } | |
52381 | unsigned long CPUFUNC(op_b0d8_5)(uint32_t opcode) /* CMPA */ | |
52382 | { | |
52383 | uint32_t srcreg = (opcode & 7); | |
52384 | uint32_t dstreg = (opcode >> 9) & 7; | |
52385 | OpcodeFamily = 27; CurrentInstrCycles = 10; | |
52386 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
52387 | if ((srca & 1) != 0) { | |
52388 | last_fault_for_exception_3 = srca; | |
52389 | last_op_for_exception_3 = opcode; | |
52390 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
52391 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
52392 | goto endlabel2842; | |
52393 | } | |
52394 | {{ int16_t src = m68k_read_memory_16(srca); | |
52395 | m68k_areg(regs, srcreg) += 2; | |
52396 | { int32_t dst = m68k_areg(regs, dstreg); | |
52397 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
52398 | { int flgs = ((int32_t)(src)) < 0; | |
52399 | int flgo = ((int32_t)(dst)) < 0; | |
52400 | int flgn = ((int32_t)(newv)) < 0; | |
52401 | SET_ZFLG (((int32_t)(newv)) == 0); | |
52402 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
52403 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
52404 | SET_NFLG (flgn != 0); | |
52405 | }}}}}}}}m68k_incpc(2); | |
52406 | fill_prefetch_2 (); | |
52407 | endlabel2842: ; | |
52408 | return 10; | |
52409 | } | |
52410 | unsigned long CPUFUNC(op_b0e0_5)(uint32_t opcode) /* CMPA */ | |
52411 | { | |
52412 | uint32_t srcreg = (opcode & 7); | |
52413 | uint32_t dstreg = (opcode >> 9) & 7; | |
52414 | OpcodeFamily = 27; CurrentInstrCycles = 12; | |
52415 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
52416 | if ((srca & 1) != 0) { | |
52417 | last_fault_for_exception_3 = srca; | |
52418 | last_op_for_exception_3 = opcode; | |
52419 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
52420 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
52421 | goto endlabel2843; | |
52422 | } | |
52423 | {{ int16_t src = m68k_read_memory_16(srca); | |
52424 | m68k_areg (regs, srcreg) = srca; | |
52425 | { int32_t dst = m68k_areg(regs, dstreg); | |
52426 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
52427 | { int flgs = ((int32_t)(src)) < 0; | |
52428 | int flgo = ((int32_t)(dst)) < 0; | |
52429 | int flgn = ((int32_t)(newv)) < 0; | |
52430 | SET_ZFLG (((int32_t)(newv)) == 0); | |
52431 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
52432 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
52433 | SET_NFLG (flgn != 0); | |
52434 | }}}}}}}}m68k_incpc(2); | |
52435 | fill_prefetch_2 (); | |
52436 | endlabel2843: ; | |
52437 | return 12; | |
52438 | } | |
52439 | unsigned long CPUFUNC(op_b0e8_5)(uint32_t opcode) /* CMPA */ | |
52440 | { | |
52441 | uint32_t srcreg = (opcode & 7); | |
52442 | uint32_t dstreg = (opcode >> 9) & 7; | |
52443 | OpcodeFamily = 27; CurrentInstrCycles = 14; | |
52444 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
52445 | if ((srca & 1) != 0) { | |
52446 | last_fault_for_exception_3 = srca; | |
52447 | last_op_for_exception_3 = opcode; | |
52448 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
52449 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
52450 | goto endlabel2844; | |
52451 | } | |
52452 | {{ int16_t src = m68k_read_memory_16(srca); | |
52453 | { int32_t dst = m68k_areg(regs, dstreg); | |
52454 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
52455 | { int flgs = ((int32_t)(src)) < 0; | |
52456 | int flgo = ((int32_t)(dst)) < 0; | |
52457 | int flgn = ((int32_t)(newv)) < 0; | |
52458 | SET_ZFLG (((int32_t)(newv)) == 0); | |
52459 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
52460 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
52461 | SET_NFLG (flgn != 0); | |
52462 | }}}}}}}}m68k_incpc(4); | |
52463 | fill_prefetch_0 (); | |
52464 | endlabel2844: ; | |
52465 | return 14; | |
52466 | } | |
52467 | unsigned long CPUFUNC(op_b0f0_5)(uint32_t opcode) /* CMPA */ | |
52468 | { | |
52469 | uint32_t srcreg = (opcode & 7); | |
52470 | uint32_t dstreg = (opcode >> 9) & 7; | |
52471 | OpcodeFamily = 27; CurrentInstrCycles = 16; | |
52472 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
52473 | BusCyclePenalty += 2; | |
52474 | if ((srca & 1) != 0) { | |
52475 | last_fault_for_exception_3 = srca; | |
52476 | last_op_for_exception_3 = opcode; | |
52477 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
52478 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
52479 | goto endlabel2845; | |
52480 | } | |
52481 | {{ int16_t src = m68k_read_memory_16(srca); | |
52482 | { int32_t dst = m68k_areg(regs, dstreg); | |
52483 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
52484 | { int flgs = ((int32_t)(src)) < 0; | |
52485 | int flgo = ((int32_t)(dst)) < 0; | |
52486 | int flgn = ((int32_t)(newv)) < 0; | |
52487 | SET_ZFLG (((int32_t)(newv)) == 0); | |
52488 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
52489 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
52490 | SET_NFLG (flgn != 0); | |
52491 | }}}}}}}}m68k_incpc(4); | |
52492 | fill_prefetch_0 (); | |
52493 | endlabel2845: ; | |
52494 | return 16; | |
52495 | } | |
52496 | unsigned long CPUFUNC(op_b0f8_5)(uint32_t opcode) /* CMPA */ | |
52497 | { | |
52498 | uint32_t dstreg = (opcode >> 9) & 7; | |
52499 | OpcodeFamily = 27; CurrentInstrCycles = 14; | |
52500 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
52501 | if ((srca & 1) != 0) { | |
52502 | last_fault_for_exception_3 = srca; | |
52503 | last_op_for_exception_3 = opcode; | |
52504 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
52505 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
52506 | goto endlabel2846; | |
52507 | } | |
52508 | {{ int16_t src = m68k_read_memory_16(srca); | |
52509 | { int32_t dst = m68k_areg(regs, dstreg); | |
52510 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
52511 | { int flgs = ((int32_t)(src)) < 0; | |
52512 | int flgo = ((int32_t)(dst)) < 0; | |
52513 | int flgn = ((int32_t)(newv)) < 0; | |
52514 | SET_ZFLG (((int32_t)(newv)) == 0); | |
52515 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
52516 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
52517 | SET_NFLG (flgn != 0); | |
52518 | }}}}}}}}m68k_incpc(4); | |
52519 | fill_prefetch_0 (); | |
52520 | endlabel2846: ; | |
52521 | return 14; | |
52522 | } | |
52523 | unsigned long CPUFUNC(op_b0f9_5)(uint32_t opcode) /* CMPA */ | |
52524 | { | |
52525 | uint32_t dstreg = (opcode >> 9) & 7; | |
52526 | OpcodeFamily = 27; CurrentInstrCycles = 18; | |
52527 | {{ uint32_t srca = get_ilong_prefetch(2); | |
52528 | if ((srca & 1) != 0) { | |
52529 | last_fault_for_exception_3 = srca; | |
52530 | last_op_for_exception_3 = opcode; | |
52531 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
52532 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
52533 | goto endlabel2847; | |
52534 | } | |
52535 | {{ int16_t src = m68k_read_memory_16(srca); | |
52536 | { int32_t dst = m68k_areg(regs, dstreg); | |
52537 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
52538 | { int flgs = ((int32_t)(src)) < 0; | |
52539 | int flgo = ((int32_t)(dst)) < 0; | |
52540 | int flgn = ((int32_t)(newv)) < 0; | |
52541 | SET_ZFLG (((int32_t)(newv)) == 0); | |
52542 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
52543 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
52544 | SET_NFLG (flgn != 0); | |
52545 | }}}}}}}}m68k_incpc(6); | |
52546 | fill_prefetch_0 (); | |
52547 | endlabel2847: ; | |
52548 | return 18; | |
52549 | } | |
52550 | unsigned long CPUFUNC(op_b0fa_5)(uint32_t opcode) /* CMPA */ | |
52551 | { | |
52552 | uint32_t dstreg = (opcode >> 9) & 7; | |
52553 | OpcodeFamily = 27; CurrentInstrCycles = 14; | |
52554 | {{ uint32_t srca = m68k_getpc () + 2; | |
52555 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
52556 | if ((srca & 1) != 0) { | |
52557 | last_fault_for_exception_3 = srca; | |
52558 | last_op_for_exception_3 = opcode; | |
52559 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
52560 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
52561 | goto endlabel2848; | |
52562 | } | |
52563 | {{ int16_t src = m68k_read_memory_16(srca); | |
52564 | { int32_t dst = m68k_areg(regs, dstreg); | |
52565 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
52566 | { int flgs = ((int32_t)(src)) < 0; | |
52567 | int flgo = ((int32_t)(dst)) < 0; | |
52568 | int flgn = ((int32_t)(newv)) < 0; | |
52569 | SET_ZFLG (((int32_t)(newv)) == 0); | |
52570 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
52571 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
52572 | SET_NFLG (flgn != 0); | |
52573 | }}}}}}}}m68k_incpc(4); | |
52574 | fill_prefetch_0 (); | |
52575 | endlabel2848: ; | |
52576 | return 14; | |
52577 | } | |
52578 | unsigned long CPUFUNC(op_b0fb_5)(uint32_t opcode) /* CMPA */ | |
52579 | { | |
52580 | uint32_t dstreg = (opcode >> 9) & 7; | |
52581 | OpcodeFamily = 27; CurrentInstrCycles = 16; | |
52582 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
52583 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
52584 | BusCyclePenalty += 2; | |
52585 | if ((srca & 1) != 0) { | |
52586 | last_fault_for_exception_3 = srca; | |
52587 | last_op_for_exception_3 = opcode; | |
52588 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
52589 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
52590 | goto endlabel2849; | |
52591 | } | |
52592 | {{ int16_t src = m68k_read_memory_16(srca); | |
52593 | { int32_t dst = m68k_areg(regs, dstreg); | |
52594 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
52595 | { int flgs = ((int32_t)(src)) < 0; | |
52596 | int flgo = ((int32_t)(dst)) < 0; | |
52597 | int flgn = ((int32_t)(newv)) < 0; | |
52598 | SET_ZFLG (((int32_t)(newv)) == 0); | |
52599 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
52600 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
52601 | SET_NFLG (flgn != 0); | |
52602 | }}}}}}}}m68k_incpc(4); | |
52603 | fill_prefetch_0 (); | |
52604 | endlabel2849: ; | |
52605 | return 16; | |
52606 | } | |
52607 | unsigned long CPUFUNC(op_b0fc_5)(uint32_t opcode) /* CMPA */ | |
52608 | { | |
52609 | uint32_t dstreg = (opcode >> 9) & 7; | |
52610 | OpcodeFamily = 27; CurrentInstrCycles = 10; | |
52611 | {{ int16_t src = get_iword_prefetch(2); | |
52612 | { int32_t dst = m68k_areg(regs, dstreg); | |
52613 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
52614 | { int flgs = ((int32_t)(src)) < 0; | |
52615 | int flgo = ((int32_t)(dst)) < 0; | |
52616 | int flgn = ((int32_t)(newv)) < 0; | |
52617 | SET_ZFLG (((int32_t)(newv)) == 0); | |
52618 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
52619 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
52620 | SET_NFLG (flgn != 0); | |
52621 | }}}}}}m68k_incpc(4); | |
52622 | fill_prefetch_0 (); | |
52623 | return 10; | |
52624 | } | |
52625 | unsigned long CPUFUNC(op_b100_5)(uint32_t opcode) /* EOR */ | |
52626 | { | |
52627 | uint32_t srcreg = ((opcode >> 9) & 7); | |
52628 | uint32_t dstreg = opcode & 7; | |
52629 | OpcodeFamily = 3; CurrentInstrCycles = 4; | |
52630 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
52631 | { int8_t dst = m68k_dreg(regs, dstreg); | |
52632 | src ^= dst; | |
52633 | CLEAR_CZNV; | |
52634 | SET_ZFLG (((int8_t)(src)) == 0); | |
52635 | SET_NFLG (((int8_t)(src)) < 0); | |
52636 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
52637 | }}}m68k_incpc(2); | |
52638 | fill_prefetch_2 (); | |
52639 | return 4; | |
52640 | } | |
52641 | unsigned long CPUFUNC(op_b108_5)(uint32_t opcode) /* CMPM */ | |
52642 | { | |
52643 | uint32_t srcreg = (opcode & 7); | |
52644 | uint32_t dstreg = (opcode >> 9) & 7; | |
52645 | OpcodeFamily = 26; CurrentInstrCycles = 12; | |
52646 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
52647 | { int8_t src = m68k_read_memory_8(srca); | |
52648 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
52649 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
52650 | { int8_t dst = m68k_read_memory_8(dsta); | |
52651 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
52652 | {{uint32_t newv = ((int8_t)(dst)) - ((int8_t)(src)); | |
52653 | { int flgs = ((int8_t)(src)) < 0; | |
52654 | int flgo = ((int8_t)(dst)) < 0; | |
52655 | int flgn = ((int8_t)(newv)) < 0; | |
52656 | SET_ZFLG (((int8_t)(newv)) == 0); | |
52657 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
52658 | SET_CFLG (((uint8_t)(src)) > ((uint8_t)(dst))); | |
52659 | SET_NFLG (flgn != 0); | |
52660 | }}}}}}}}m68k_incpc(2); | |
52661 | fill_prefetch_2 (); | |
52662 | return 12; | |
52663 | } | |
52664 | unsigned long CPUFUNC(op_b110_5)(uint32_t opcode) /* EOR */ | |
52665 | { | |
52666 | uint32_t srcreg = ((opcode >> 9) & 7); | |
52667 | uint32_t dstreg = opcode & 7; | |
52668 | OpcodeFamily = 3; CurrentInstrCycles = 12; | |
52669 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
52670 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
52671 | { int8_t dst = m68k_read_memory_8(dsta); | |
52672 | src ^= dst; | |
52673 | CLEAR_CZNV; | |
52674 | SET_ZFLG (((int8_t)(src)) == 0); | |
52675 | SET_NFLG (((int8_t)(src)) < 0); | |
52676 | m68k_incpc(2); | |
52677 | fill_prefetch_2 (); | |
52678 | m68k_write_memory_8(dsta,src); | |
52679 | }}}}return 12; | |
52680 | } | |
52681 | unsigned long CPUFUNC(op_b118_5)(uint32_t opcode) /* EOR */ | |
52682 | { | |
52683 | uint32_t srcreg = ((opcode >> 9) & 7); | |
52684 | uint32_t dstreg = opcode & 7; | |
52685 | OpcodeFamily = 3; CurrentInstrCycles = 12; | |
52686 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
52687 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
52688 | { int8_t dst = m68k_read_memory_8(dsta); | |
52689 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
52690 | src ^= dst; | |
52691 | CLEAR_CZNV; | |
52692 | SET_ZFLG (((int8_t)(src)) == 0); | |
52693 | SET_NFLG (((int8_t)(src)) < 0); | |
52694 | m68k_incpc(2); | |
52695 | fill_prefetch_2 (); | |
52696 | m68k_write_memory_8(dsta,src); | |
52697 | }}}}return 12; | |
52698 | } | |
52699 | unsigned long CPUFUNC(op_b120_5)(uint32_t opcode) /* EOR */ | |
52700 | { | |
52701 | uint32_t srcreg = ((opcode >> 9) & 7); | |
52702 | uint32_t dstreg = opcode & 7; | |
52703 | OpcodeFamily = 3; CurrentInstrCycles = 14; | |
52704 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
52705 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
52706 | { int8_t dst = m68k_read_memory_8(dsta); | |
52707 | m68k_areg (regs, dstreg) = dsta; | |
52708 | src ^= dst; | |
52709 | CLEAR_CZNV; | |
52710 | SET_ZFLG (((int8_t)(src)) == 0); | |
52711 | SET_NFLG (((int8_t)(src)) < 0); | |
52712 | m68k_incpc(2); | |
52713 | fill_prefetch_2 (); | |
52714 | m68k_write_memory_8(dsta,src); | |
52715 | }}}}return 14; | |
52716 | } | |
52717 | unsigned long CPUFUNC(op_b128_5)(uint32_t opcode) /* EOR */ | |
52718 | { | |
52719 | uint32_t srcreg = ((opcode >> 9) & 7); | |
52720 | uint32_t dstreg = opcode & 7; | |
52721 | OpcodeFamily = 3; CurrentInstrCycles = 16; | |
52722 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
52723 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
52724 | { int8_t dst = m68k_read_memory_8(dsta); | |
52725 | src ^= dst; | |
52726 | CLEAR_CZNV; | |
52727 | SET_ZFLG (((int8_t)(src)) == 0); | |
52728 | SET_NFLG (((int8_t)(src)) < 0); | |
52729 | m68k_incpc(4); | |
52730 | fill_prefetch_0 (); | |
52731 | m68k_write_memory_8(dsta,src); | |
52732 | }}}}return 16; | |
52733 | } | |
52734 | unsigned long CPUFUNC(op_b130_5)(uint32_t opcode) /* EOR */ | |
52735 | { | |
52736 | uint32_t srcreg = ((opcode >> 9) & 7); | |
52737 | uint32_t dstreg = opcode & 7; | |
52738 | OpcodeFamily = 3; CurrentInstrCycles = 18; | |
52739 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
52740 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); | |
52741 | BusCyclePenalty += 2; | |
52742 | { int8_t dst = m68k_read_memory_8(dsta); | |
52743 | src ^= dst; | |
52744 | CLEAR_CZNV; | |
52745 | SET_ZFLG (((int8_t)(src)) == 0); | |
52746 | SET_NFLG (((int8_t)(src)) < 0); | |
52747 | m68k_incpc(4); | |
52748 | fill_prefetch_0 (); | |
52749 | m68k_write_memory_8(dsta,src); | |
52750 | }}}}return 18; | |
52751 | } | |
52752 | unsigned long CPUFUNC(op_b138_5)(uint32_t opcode) /* EOR */ | |
52753 | { | |
52754 | uint32_t srcreg = ((opcode >> 9) & 7); | |
52755 | OpcodeFamily = 3; CurrentInstrCycles = 16; | |
52756 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
52757 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); | |
52758 | { int8_t dst = m68k_read_memory_8(dsta); | |
52759 | src ^= dst; | |
52760 | CLEAR_CZNV; | |
52761 | SET_ZFLG (((int8_t)(src)) == 0); | |
52762 | SET_NFLG (((int8_t)(src)) < 0); | |
52763 | m68k_incpc(4); | |
52764 | fill_prefetch_0 (); | |
52765 | m68k_write_memory_8(dsta,src); | |
52766 | }}}}return 16; | |
52767 | } | |
52768 | unsigned long CPUFUNC(op_b139_5)(uint32_t opcode) /* EOR */ | |
52769 | { | |
52770 | uint32_t srcreg = ((opcode >> 9) & 7); | |
52771 | OpcodeFamily = 3; CurrentInstrCycles = 20; | |
52772 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
52773 | { uint32_t dsta = get_ilong_prefetch(2); | |
52774 | { int8_t dst = m68k_read_memory_8(dsta); | |
52775 | src ^= dst; | |
52776 | CLEAR_CZNV; | |
52777 | SET_ZFLG (((int8_t)(src)) == 0); | |
52778 | SET_NFLG (((int8_t)(src)) < 0); | |
52779 | m68k_incpc(6); | |
52780 | fill_prefetch_0 (); | |
52781 | m68k_write_memory_8(dsta,src); | |
52782 | }}}}return 20; | |
52783 | } | |
52784 | unsigned long CPUFUNC(op_b140_5)(uint32_t opcode) /* EOR */ | |
52785 | { | |
52786 | uint32_t srcreg = ((opcode >> 9) & 7); | |
52787 | uint32_t dstreg = opcode & 7; | |
52788 | OpcodeFamily = 3; CurrentInstrCycles = 4; | |
52789 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
52790 | { int16_t dst = m68k_dreg(regs, dstreg); | |
52791 | src ^= dst; | |
52792 | CLEAR_CZNV; | |
52793 | SET_ZFLG (((int16_t)(src)) == 0); | |
52794 | SET_NFLG (((int16_t)(src)) < 0); | |
52795 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
52796 | }}}m68k_incpc(2); | |
52797 | fill_prefetch_2 (); | |
52798 | return 4; | |
52799 | } | |
52800 | unsigned long CPUFUNC(op_b148_5)(uint32_t opcode) /* CMPM */ | |
52801 | { | |
52802 | uint32_t srcreg = (opcode & 7); | |
52803 | uint32_t dstreg = (opcode >> 9) & 7; | |
52804 | OpcodeFamily = 26; CurrentInstrCycles = 12; | |
52805 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
52806 | if ((srca & 1) != 0) { | |
52807 | last_fault_for_exception_3 = srca; | |
52808 | last_op_for_exception_3 = opcode; | |
52809 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
52810 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
52811 | goto endlabel2861; | |
52812 | } | |
52813 | {{ int16_t src = m68k_read_memory_16(srca); | |
52814 | m68k_areg(regs, srcreg) += 2; | |
52815 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
52816 | if ((dsta & 1) != 0) { | |
52817 | last_fault_for_exception_3 = dsta; | |
52818 | last_op_for_exception_3 = opcode; | |
52819 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
52820 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
52821 | goto endlabel2861; | |
52822 | } | |
52823 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
52824 | m68k_areg(regs, dstreg) += 2; | |
52825 | {{uint32_t newv = ((int16_t)(dst)) - ((int16_t)(src)); | |
52826 | { int flgs = ((int16_t)(src)) < 0; | |
52827 | int flgo = ((int16_t)(dst)) < 0; | |
52828 | int flgn = ((int16_t)(newv)) < 0; | |
52829 | SET_ZFLG (((int16_t)(newv)) == 0); | |
52830 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
52831 | SET_CFLG (((uint16_t)(src)) > ((uint16_t)(dst))); | |
52832 | SET_NFLG (flgn != 0); | |
52833 | }}}}}}}}}}m68k_incpc(2); | |
52834 | fill_prefetch_2 (); | |
52835 | endlabel2861: ; | |
52836 | return 12; | |
52837 | } | |
52838 | unsigned long CPUFUNC(op_b150_5)(uint32_t opcode) /* EOR */ | |
52839 | { | |
52840 | uint32_t srcreg = ((opcode >> 9) & 7); | |
52841 | uint32_t dstreg = opcode & 7; | |
52842 | OpcodeFamily = 3; CurrentInstrCycles = 12; | |
52843 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
52844 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
52845 | if ((dsta & 1) != 0) { | |
52846 | last_fault_for_exception_3 = dsta; | |
52847 | last_op_for_exception_3 = opcode; | |
52848 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
52849 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
52850 | goto endlabel2862; | |
52851 | } | |
52852 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
52853 | src ^= dst; | |
52854 | CLEAR_CZNV; | |
52855 | SET_ZFLG (((int16_t)(src)) == 0); | |
52856 | SET_NFLG (((int16_t)(src)) < 0); | |
52857 | m68k_incpc(2); | |
52858 | fill_prefetch_2 (); | |
52859 | m68k_write_memory_16(dsta,src); | |
52860 | }}}}}endlabel2862: ; | |
52861 | return 12; | |
52862 | } | |
52863 | unsigned long CPUFUNC(op_b158_5)(uint32_t opcode) /* EOR */ | |
52864 | { | |
52865 | uint32_t srcreg = ((opcode >> 9) & 7); | |
52866 | uint32_t dstreg = opcode & 7; | |
52867 | OpcodeFamily = 3; CurrentInstrCycles = 12; | |
52868 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
52869 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
52870 | if ((dsta & 1) != 0) { | |
52871 | last_fault_for_exception_3 = dsta; | |
52872 | last_op_for_exception_3 = opcode; | |
52873 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
52874 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
52875 | goto endlabel2863; | |
52876 | } | |
52877 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
52878 | m68k_areg(regs, dstreg) += 2; | |
52879 | src ^= dst; | |
52880 | CLEAR_CZNV; | |
52881 | SET_ZFLG (((int16_t)(src)) == 0); | |
52882 | SET_NFLG (((int16_t)(src)) < 0); | |
52883 | m68k_incpc(2); | |
52884 | fill_prefetch_2 (); | |
52885 | m68k_write_memory_16(dsta,src); | |
52886 | }}}}}endlabel2863: ; | |
52887 | return 12; | |
52888 | } | |
52889 | unsigned long CPUFUNC(op_b160_5)(uint32_t opcode) /* EOR */ | |
52890 | { | |
52891 | uint32_t srcreg = ((opcode >> 9) & 7); | |
52892 | uint32_t dstreg = opcode & 7; | |
52893 | OpcodeFamily = 3; CurrentInstrCycles = 14; | |
52894 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
52895 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
52896 | if ((dsta & 1) != 0) { | |
52897 | last_fault_for_exception_3 = dsta; | |
52898 | last_op_for_exception_3 = opcode; | |
52899 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
52900 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
52901 | goto endlabel2864; | |
52902 | } | |
52903 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
52904 | m68k_areg (regs, dstreg) = dsta; | |
52905 | src ^= dst; | |
52906 | CLEAR_CZNV; | |
52907 | SET_ZFLG (((int16_t)(src)) == 0); | |
52908 | SET_NFLG (((int16_t)(src)) < 0); | |
52909 | m68k_incpc(2); | |
52910 | fill_prefetch_2 (); | |
52911 | m68k_write_memory_16(dsta,src); | |
52912 | }}}}}endlabel2864: ; | |
52913 | return 14; | |
52914 | } | |
52915 | unsigned long CPUFUNC(op_b168_5)(uint32_t opcode) /* EOR */ | |
52916 | { | |
52917 | uint32_t srcreg = ((opcode >> 9) & 7); | |
52918 | uint32_t dstreg = opcode & 7; | |
52919 | OpcodeFamily = 3; CurrentInstrCycles = 16; | |
52920 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
52921 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
52922 | if ((dsta & 1) != 0) { | |
52923 | last_fault_for_exception_3 = dsta; | |
52924 | last_op_for_exception_3 = opcode; | |
52925 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
52926 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
52927 | goto endlabel2865; | |
52928 | } | |
52929 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
52930 | src ^= dst; | |
52931 | CLEAR_CZNV; | |
52932 | SET_ZFLG (((int16_t)(src)) == 0); | |
52933 | SET_NFLG (((int16_t)(src)) < 0); | |
52934 | m68k_incpc(4); | |
52935 | fill_prefetch_0 (); | |
52936 | m68k_write_memory_16(dsta,src); | |
52937 | }}}}}endlabel2865: ; | |
52938 | return 16; | |
52939 | } | |
52940 | unsigned long CPUFUNC(op_b170_5)(uint32_t opcode) /* EOR */ | |
52941 | { | |
52942 | uint32_t srcreg = ((opcode >> 9) & 7); | |
52943 | uint32_t dstreg = opcode & 7; | |
52944 | OpcodeFamily = 3; CurrentInstrCycles = 18; | |
52945 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
52946 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); | |
52947 | BusCyclePenalty += 2; | |
52948 | if ((dsta & 1) != 0) { | |
52949 | last_fault_for_exception_3 = dsta; | |
52950 | last_op_for_exception_3 = opcode; | |
52951 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
52952 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
52953 | goto endlabel2866; | |
52954 | } | |
52955 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
52956 | src ^= dst; | |
52957 | CLEAR_CZNV; | |
52958 | SET_ZFLG (((int16_t)(src)) == 0); | |
52959 | SET_NFLG (((int16_t)(src)) < 0); | |
52960 | m68k_incpc(4); | |
52961 | fill_prefetch_0 (); | |
52962 | m68k_write_memory_16(dsta,src); | |
52963 | }}}}}endlabel2866: ; | |
52964 | return 18; | |
52965 | } | |
52966 | unsigned long CPUFUNC(op_b178_5)(uint32_t opcode) /* EOR */ | |
52967 | { | |
52968 | uint32_t srcreg = ((opcode >> 9) & 7); | |
52969 | OpcodeFamily = 3; CurrentInstrCycles = 16; | |
52970 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
52971 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); | |
52972 | if ((dsta & 1) != 0) { | |
52973 | last_fault_for_exception_3 = dsta; | |
52974 | last_op_for_exception_3 = opcode; | |
52975 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
52976 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
52977 | goto endlabel2867; | |
52978 | } | |
52979 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
52980 | src ^= dst; | |
52981 | CLEAR_CZNV; | |
52982 | SET_ZFLG (((int16_t)(src)) == 0); | |
52983 | SET_NFLG (((int16_t)(src)) < 0); | |
52984 | m68k_incpc(4); | |
52985 | fill_prefetch_0 (); | |
52986 | m68k_write_memory_16(dsta,src); | |
52987 | }}}}}endlabel2867: ; | |
52988 | return 16; | |
52989 | } | |
52990 | unsigned long CPUFUNC(op_b179_5)(uint32_t opcode) /* EOR */ | |
52991 | { | |
52992 | uint32_t srcreg = ((opcode >> 9) & 7); | |
52993 | OpcodeFamily = 3; CurrentInstrCycles = 20; | |
52994 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
52995 | { uint32_t dsta = get_ilong_prefetch(2); | |
52996 | if ((dsta & 1) != 0) { | |
52997 | last_fault_for_exception_3 = dsta; | |
52998 | last_op_for_exception_3 = opcode; | |
52999 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
53000 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
53001 | goto endlabel2868; | |
53002 | } | |
53003 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
53004 | src ^= dst; | |
53005 | CLEAR_CZNV; | |
53006 | SET_ZFLG (((int16_t)(src)) == 0); | |
53007 | SET_NFLG (((int16_t)(src)) < 0); | |
53008 | m68k_incpc(6); | |
53009 | fill_prefetch_0 (); | |
53010 | m68k_write_memory_16(dsta,src); | |
53011 | }}}}}endlabel2868: ; | |
53012 | return 20; | |
53013 | } | |
53014 | unsigned long CPUFUNC(op_b180_5)(uint32_t opcode) /* EOR */ | |
53015 | { | |
53016 | uint32_t srcreg = ((opcode >> 9) & 7); | |
53017 | uint32_t dstreg = opcode & 7; | |
53018 | OpcodeFamily = 3; CurrentInstrCycles = 8; | |
53019 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
53020 | { int32_t dst = m68k_dreg(regs, dstreg); | |
53021 | src ^= dst; | |
53022 | CLEAR_CZNV; | |
53023 | SET_ZFLG (((int32_t)(src)) == 0); | |
53024 | SET_NFLG (((int32_t)(src)) < 0); | |
53025 | m68k_dreg(regs, dstreg) = (src); | |
53026 | }}}m68k_incpc(2); | |
53027 | fill_prefetch_2 (); | |
53028 | return 8; | |
53029 | } | |
53030 | unsigned long CPUFUNC(op_b188_5)(uint32_t opcode) /* CMPM */ | |
53031 | { | |
53032 | uint32_t srcreg = (opcode & 7); | |
53033 | uint32_t dstreg = (opcode >> 9) & 7; | |
53034 | OpcodeFamily = 26; CurrentInstrCycles = 20; | |
53035 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
53036 | if ((srca & 1) != 0) { | |
53037 | last_fault_for_exception_3 = srca; | |
53038 | last_op_for_exception_3 = opcode; | |
53039 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
53040 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
53041 | goto endlabel2870; | |
53042 | } | |
53043 | {{ int32_t src = m68k_read_memory_32(srca); | |
53044 | m68k_areg(regs, srcreg) += 4; | |
53045 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
53046 | if ((dsta & 1) != 0) { | |
53047 | last_fault_for_exception_3 = dsta; | |
53048 | last_op_for_exception_3 = opcode; | |
53049 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
53050 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
53051 | goto endlabel2870; | |
53052 | } | |
53053 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
53054 | m68k_areg(regs, dstreg) += 4; | |
53055 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
53056 | { int flgs = ((int32_t)(src)) < 0; | |
53057 | int flgo = ((int32_t)(dst)) < 0; | |
53058 | int flgn = ((int32_t)(newv)) < 0; | |
53059 | SET_ZFLG (((int32_t)(newv)) == 0); | |
53060 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
53061 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
53062 | SET_NFLG (flgn != 0); | |
53063 | }}}}}}}}}}m68k_incpc(2); | |
53064 | fill_prefetch_2 (); | |
53065 | endlabel2870: ; | |
53066 | return 20; | |
53067 | } | |
53068 | unsigned long CPUFUNC(op_b190_5)(uint32_t opcode) /* EOR */ | |
53069 | { | |
53070 | uint32_t srcreg = ((opcode >> 9) & 7); | |
53071 | uint32_t dstreg = opcode & 7; | |
53072 | OpcodeFamily = 3; CurrentInstrCycles = 20; | |
53073 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
53074 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
53075 | if ((dsta & 1) != 0) { | |
53076 | last_fault_for_exception_3 = dsta; | |
53077 | last_op_for_exception_3 = opcode; | |
53078 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
53079 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
53080 | goto endlabel2871; | |
53081 | } | |
53082 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
53083 | src ^= dst; | |
53084 | CLEAR_CZNV; | |
53085 | SET_ZFLG (((int32_t)(src)) == 0); | |
53086 | SET_NFLG (((int32_t)(src)) < 0); | |
53087 | m68k_incpc(2); | |
53088 | fill_prefetch_2 (); | |
53089 | m68k_write_memory_32(dsta,src); | |
53090 | }}}}}endlabel2871: ; | |
53091 | return 20; | |
53092 | } | |
53093 | unsigned long CPUFUNC(op_b198_5)(uint32_t opcode) /* EOR */ | |
53094 | { | |
53095 | uint32_t srcreg = ((opcode >> 9) & 7); | |
53096 | uint32_t dstreg = opcode & 7; | |
53097 | OpcodeFamily = 3; CurrentInstrCycles = 20; | |
53098 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
53099 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
53100 | if ((dsta & 1) != 0) { | |
53101 | last_fault_for_exception_3 = dsta; | |
53102 | last_op_for_exception_3 = opcode; | |
53103 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
53104 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
53105 | goto endlabel2872; | |
53106 | } | |
53107 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
53108 | m68k_areg(regs, dstreg) += 4; | |
53109 | src ^= dst; | |
53110 | CLEAR_CZNV; | |
53111 | SET_ZFLG (((int32_t)(src)) == 0); | |
53112 | SET_NFLG (((int32_t)(src)) < 0); | |
53113 | m68k_incpc(2); | |
53114 | fill_prefetch_2 (); | |
53115 | m68k_write_memory_32(dsta,src); | |
53116 | }}}}}endlabel2872: ; | |
53117 | return 20; | |
53118 | } | |
53119 | unsigned long CPUFUNC(op_b1a0_5)(uint32_t opcode) /* EOR */ | |
53120 | { | |
53121 | uint32_t srcreg = ((opcode >> 9) & 7); | |
53122 | uint32_t dstreg = opcode & 7; | |
53123 | OpcodeFamily = 3; CurrentInstrCycles = 22; | |
53124 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
53125 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
53126 | if ((dsta & 1) != 0) { | |
53127 | last_fault_for_exception_3 = dsta; | |
53128 | last_op_for_exception_3 = opcode; | |
53129 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
53130 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
53131 | goto endlabel2873; | |
53132 | } | |
53133 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
53134 | m68k_areg (regs, dstreg) = dsta; | |
53135 | src ^= dst; | |
53136 | CLEAR_CZNV; | |
53137 | SET_ZFLG (((int32_t)(src)) == 0); | |
53138 | SET_NFLG (((int32_t)(src)) < 0); | |
53139 | m68k_incpc(2); | |
53140 | fill_prefetch_2 (); | |
53141 | m68k_write_memory_32(dsta,src); | |
53142 | }}}}}endlabel2873: ; | |
53143 | return 22; | |
53144 | } | |
53145 | unsigned long CPUFUNC(op_b1a8_5)(uint32_t opcode) /* EOR */ | |
53146 | { | |
53147 | uint32_t srcreg = ((opcode >> 9) & 7); | |
53148 | uint32_t dstreg = opcode & 7; | |
53149 | OpcodeFamily = 3; CurrentInstrCycles = 24; | |
53150 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
53151 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
53152 | if ((dsta & 1) != 0) { | |
53153 | last_fault_for_exception_3 = dsta; | |
53154 | last_op_for_exception_3 = opcode; | |
53155 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
53156 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
53157 | goto endlabel2874; | |
53158 | } | |
53159 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
53160 | src ^= dst; | |
53161 | CLEAR_CZNV; | |
53162 | SET_ZFLG (((int32_t)(src)) == 0); | |
53163 | SET_NFLG (((int32_t)(src)) < 0); | |
53164 | m68k_incpc(4); | |
53165 | fill_prefetch_0 (); | |
53166 | m68k_write_memory_32(dsta,src); | |
53167 | }}}}}endlabel2874: ; | |
53168 | return 24; | |
53169 | } | |
53170 | unsigned long CPUFUNC(op_b1b0_5)(uint32_t opcode) /* EOR */ | |
53171 | { | |
53172 | uint32_t srcreg = ((opcode >> 9) & 7); | |
53173 | uint32_t dstreg = opcode & 7; | |
53174 | OpcodeFamily = 3; CurrentInstrCycles = 26; | |
53175 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
53176 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); | |
53177 | BusCyclePenalty += 2; | |
53178 | if ((dsta & 1) != 0) { | |
53179 | last_fault_for_exception_3 = dsta; | |
53180 | last_op_for_exception_3 = opcode; | |
53181 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
53182 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
53183 | goto endlabel2875; | |
53184 | } | |
53185 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
53186 | src ^= dst; | |
53187 | CLEAR_CZNV; | |
53188 | SET_ZFLG (((int32_t)(src)) == 0); | |
53189 | SET_NFLG (((int32_t)(src)) < 0); | |
53190 | m68k_incpc(4); | |
53191 | fill_prefetch_0 (); | |
53192 | m68k_write_memory_32(dsta,src); | |
53193 | }}}}}endlabel2875: ; | |
53194 | return 26; | |
53195 | } | |
53196 | unsigned long CPUFUNC(op_b1b8_5)(uint32_t opcode) /* EOR */ | |
53197 | { | |
53198 | uint32_t srcreg = ((opcode >> 9) & 7); | |
53199 | OpcodeFamily = 3; CurrentInstrCycles = 24; | |
53200 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
53201 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); | |
53202 | if ((dsta & 1) != 0) { | |
53203 | last_fault_for_exception_3 = dsta; | |
53204 | last_op_for_exception_3 = opcode; | |
53205 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
53206 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
53207 | goto endlabel2876; | |
53208 | } | |
53209 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
53210 | src ^= dst; | |
53211 | CLEAR_CZNV; | |
53212 | SET_ZFLG (((int32_t)(src)) == 0); | |
53213 | SET_NFLG (((int32_t)(src)) < 0); | |
53214 | m68k_incpc(4); | |
53215 | fill_prefetch_0 (); | |
53216 | m68k_write_memory_32(dsta,src); | |
53217 | }}}}}endlabel2876: ; | |
53218 | return 24; | |
53219 | } | |
53220 | unsigned long CPUFUNC(op_b1b9_5)(uint32_t opcode) /* EOR */ | |
53221 | { | |
53222 | uint32_t srcreg = ((opcode >> 9) & 7); | |
53223 | OpcodeFamily = 3; CurrentInstrCycles = 28; | |
53224 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
53225 | { uint32_t dsta = get_ilong_prefetch(2); | |
53226 | if ((dsta & 1) != 0) { | |
53227 | last_fault_for_exception_3 = dsta; | |
53228 | last_op_for_exception_3 = opcode; | |
53229 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
53230 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
53231 | goto endlabel2877; | |
53232 | } | |
53233 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
53234 | src ^= dst; | |
53235 | CLEAR_CZNV; | |
53236 | SET_ZFLG (((int32_t)(src)) == 0); | |
53237 | SET_NFLG (((int32_t)(src)) < 0); | |
53238 | m68k_incpc(6); | |
53239 | fill_prefetch_0 (); | |
53240 | m68k_write_memory_32(dsta,src); | |
53241 | }}}}}endlabel2877: ; | |
53242 | return 28; | |
53243 | } | |
53244 | unsigned long CPUFUNC(op_b1c0_5)(uint32_t opcode) /* CMPA */ | |
53245 | { | |
53246 | uint32_t srcreg = (opcode & 7); | |
53247 | uint32_t dstreg = (opcode >> 9) & 7; | |
53248 | OpcodeFamily = 27; CurrentInstrCycles = 6; | |
53249 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
53250 | { int32_t dst = m68k_areg(regs, dstreg); | |
53251 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
53252 | { int flgs = ((int32_t)(src)) < 0; | |
53253 | int flgo = ((int32_t)(dst)) < 0; | |
53254 | int flgn = ((int32_t)(newv)) < 0; | |
53255 | SET_ZFLG (((int32_t)(newv)) == 0); | |
53256 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
53257 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
53258 | SET_NFLG (flgn != 0); | |
53259 | }}}}}}m68k_incpc(2); | |
53260 | fill_prefetch_2 (); | |
53261 | return 6; | |
53262 | } | |
53263 | unsigned long CPUFUNC(op_b1c8_5)(uint32_t opcode) /* CMPA */ | |
53264 | { | |
53265 | uint32_t srcreg = (opcode & 7); | |
53266 | uint32_t dstreg = (opcode >> 9) & 7; | |
53267 | OpcodeFamily = 27; CurrentInstrCycles = 6; | |
53268 | {{ int32_t src = m68k_areg(regs, srcreg); | |
53269 | { int32_t dst = m68k_areg(regs, dstreg); | |
53270 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
53271 | { int flgs = ((int32_t)(src)) < 0; | |
53272 | int flgo = ((int32_t)(dst)) < 0; | |
53273 | int flgn = ((int32_t)(newv)) < 0; | |
53274 | SET_ZFLG (((int32_t)(newv)) == 0); | |
53275 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
53276 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
53277 | SET_NFLG (flgn != 0); | |
53278 | }}}}}}m68k_incpc(2); | |
53279 | fill_prefetch_2 (); | |
53280 | return 6; | |
53281 | } | |
53282 | unsigned long CPUFUNC(op_b1d0_5)(uint32_t opcode) /* CMPA */ | |
53283 | { | |
53284 | uint32_t srcreg = (opcode & 7); | |
53285 | uint32_t dstreg = (opcode >> 9) & 7; | |
53286 | OpcodeFamily = 27; CurrentInstrCycles = 14; | |
53287 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
53288 | if ((srca & 1) != 0) { | |
53289 | last_fault_for_exception_3 = srca; | |
53290 | last_op_for_exception_3 = opcode; | |
53291 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
53292 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
53293 | goto endlabel2880; | |
53294 | } | |
53295 | {{ int32_t src = m68k_read_memory_32(srca); | |
53296 | { int32_t dst = m68k_areg(regs, dstreg); | |
53297 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
53298 | { int flgs = ((int32_t)(src)) < 0; | |
53299 | int flgo = ((int32_t)(dst)) < 0; | |
53300 | int flgn = ((int32_t)(newv)) < 0; | |
53301 | SET_ZFLG (((int32_t)(newv)) == 0); | |
53302 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
53303 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
53304 | SET_NFLG (flgn != 0); | |
53305 | }}}}}}}}m68k_incpc(2); | |
53306 | fill_prefetch_2 (); | |
53307 | endlabel2880: ; | |
53308 | return 14; | |
53309 | } | |
53310 | unsigned long CPUFUNC(op_b1d8_5)(uint32_t opcode) /* CMPA */ | |
53311 | { | |
53312 | uint32_t srcreg = (opcode & 7); | |
53313 | uint32_t dstreg = (opcode >> 9) & 7; | |
53314 | OpcodeFamily = 27; CurrentInstrCycles = 14; | |
53315 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
53316 | if ((srca & 1) != 0) { | |
53317 | last_fault_for_exception_3 = srca; | |
53318 | last_op_for_exception_3 = opcode; | |
53319 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
53320 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
53321 | goto endlabel2881; | |
53322 | } | |
53323 | {{ int32_t src = m68k_read_memory_32(srca); | |
53324 | m68k_areg(regs, srcreg) += 4; | |
53325 | { int32_t dst = m68k_areg(regs, dstreg); | |
53326 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
53327 | { int flgs = ((int32_t)(src)) < 0; | |
53328 | int flgo = ((int32_t)(dst)) < 0; | |
53329 | int flgn = ((int32_t)(newv)) < 0; | |
53330 | SET_ZFLG (((int32_t)(newv)) == 0); | |
53331 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
53332 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
53333 | SET_NFLG (flgn != 0); | |
53334 | }}}}}}}}m68k_incpc(2); | |
53335 | fill_prefetch_2 (); | |
53336 | endlabel2881: ; | |
53337 | return 14; | |
53338 | } | |
53339 | unsigned long CPUFUNC(op_b1e0_5)(uint32_t opcode) /* CMPA */ | |
53340 | { | |
53341 | uint32_t srcreg = (opcode & 7); | |
53342 | uint32_t dstreg = (opcode >> 9) & 7; | |
53343 | OpcodeFamily = 27; CurrentInstrCycles = 16; | |
53344 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 4; | |
53345 | if ((srca & 1) != 0) { | |
53346 | last_fault_for_exception_3 = srca; | |
53347 | last_op_for_exception_3 = opcode; | |
53348 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
53349 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
53350 | goto endlabel2882; | |
53351 | } | |
53352 | {{ int32_t src = m68k_read_memory_32(srca); | |
53353 | m68k_areg (regs, srcreg) = srca; | |
53354 | { int32_t dst = m68k_areg(regs, dstreg); | |
53355 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
53356 | { int flgs = ((int32_t)(src)) < 0; | |
53357 | int flgo = ((int32_t)(dst)) < 0; | |
53358 | int flgn = ((int32_t)(newv)) < 0; | |
53359 | SET_ZFLG (((int32_t)(newv)) == 0); | |
53360 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
53361 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
53362 | SET_NFLG (flgn != 0); | |
53363 | }}}}}}}}m68k_incpc(2); | |
53364 | fill_prefetch_2 (); | |
53365 | endlabel2882: ; | |
53366 | return 16; | |
53367 | } | |
53368 | unsigned long CPUFUNC(op_b1e8_5)(uint32_t opcode) /* CMPA */ | |
53369 | { | |
53370 | uint32_t srcreg = (opcode & 7); | |
53371 | uint32_t dstreg = (opcode >> 9) & 7; | |
53372 | OpcodeFamily = 27; CurrentInstrCycles = 18; | |
53373 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
53374 | if ((srca & 1) != 0) { | |
53375 | last_fault_for_exception_3 = srca; | |
53376 | last_op_for_exception_3 = opcode; | |
53377 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
53378 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
53379 | goto endlabel2883; | |
53380 | } | |
53381 | {{ int32_t src = m68k_read_memory_32(srca); | |
53382 | { int32_t dst = m68k_areg(regs, dstreg); | |
53383 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
53384 | { int flgs = ((int32_t)(src)) < 0; | |
53385 | int flgo = ((int32_t)(dst)) < 0; | |
53386 | int flgn = ((int32_t)(newv)) < 0; | |
53387 | SET_ZFLG (((int32_t)(newv)) == 0); | |
53388 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
53389 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
53390 | SET_NFLG (flgn != 0); | |
53391 | }}}}}}}}m68k_incpc(4); | |
53392 | fill_prefetch_0 (); | |
53393 | endlabel2883: ; | |
53394 | return 18; | |
53395 | } | |
53396 | unsigned long CPUFUNC(op_b1f0_5)(uint32_t opcode) /* CMPA */ | |
53397 | { | |
53398 | uint32_t srcreg = (opcode & 7); | |
53399 | uint32_t dstreg = (opcode >> 9) & 7; | |
53400 | OpcodeFamily = 27; CurrentInstrCycles = 20; | |
53401 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
53402 | BusCyclePenalty += 2; | |
53403 | if ((srca & 1) != 0) { | |
53404 | last_fault_for_exception_3 = srca; | |
53405 | last_op_for_exception_3 = opcode; | |
53406 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
53407 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
53408 | goto endlabel2884; | |
53409 | } | |
53410 | {{ int32_t src = m68k_read_memory_32(srca); | |
53411 | { int32_t dst = m68k_areg(regs, dstreg); | |
53412 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
53413 | { int flgs = ((int32_t)(src)) < 0; | |
53414 | int flgo = ((int32_t)(dst)) < 0; | |
53415 | int flgn = ((int32_t)(newv)) < 0; | |
53416 | SET_ZFLG (((int32_t)(newv)) == 0); | |
53417 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
53418 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
53419 | SET_NFLG (flgn != 0); | |
53420 | }}}}}}}}m68k_incpc(4); | |
53421 | fill_prefetch_0 (); | |
53422 | endlabel2884: ; | |
53423 | return 20; | |
53424 | } | |
53425 | unsigned long CPUFUNC(op_b1f8_5)(uint32_t opcode) /* CMPA */ | |
53426 | { | |
53427 | uint32_t dstreg = (opcode >> 9) & 7; | |
53428 | OpcodeFamily = 27; CurrentInstrCycles = 18; | |
53429 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
53430 | if ((srca & 1) != 0) { | |
53431 | last_fault_for_exception_3 = srca; | |
53432 | last_op_for_exception_3 = opcode; | |
53433 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
53434 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
53435 | goto endlabel2885; | |
53436 | } | |
53437 | {{ int32_t src = m68k_read_memory_32(srca); | |
53438 | { int32_t dst = m68k_areg(regs, dstreg); | |
53439 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
53440 | { int flgs = ((int32_t)(src)) < 0; | |
53441 | int flgo = ((int32_t)(dst)) < 0; | |
53442 | int flgn = ((int32_t)(newv)) < 0; | |
53443 | SET_ZFLG (((int32_t)(newv)) == 0); | |
53444 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
53445 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
53446 | SET_NFLG (flgn != 0); | |
53447 | }}}}}}}}m68k_incpc(4); | |
53448 | fill_prefetch_0 (); | |
53449 | endlabel2885: ; | |
53450 | return 18; | |
53451 | } | |
53452 | unsigned long CPUFUNC(op_b1f9_5)(uint32_t opcode) /* CMPA */ | |
53453 | { | |
53454 | uint32_t dstreg = (opcode >> 9) & 7; | |
53455 | OpcodeFamily = 27; CurrentInstrCycles = 22; | |
53456 | {{ uint32_t srca = get_ilong_prefetch(2); | |
53457 | if ((srca & 1) != 0) { | |
53458 | last_fault_for_exception_3 = srca; | |
53459 | last_op_for_exception_3 = opcode; | |
53460 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
53461 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
53462 | goto endlabel2886; | |
53463 | } | |
53464 | {{ int32_t src = m68k_read_memory_32(srca); | |
53465 | { int32_t dst = m68k_areg(regs, dstreg); | |
53466 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
53467 | { int flgs = ((int32_t)(src)) < 0; | |
53468 | int flgo = ((int32_t)(dst)) < 0; | |
53469 | int flgn = ((int32_t)(newv)) < 0; | |
53470 | SET_ZFLG (((int32_t)(newv)) == 0); | |
53471 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
53472 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
53473 | SET_NFLG (flgn != 0); | |
53474 | }}}}}}}}m68k_incpc(6); | |
53475 | fill_prefetch_0 (); | |
53476 | endlabel2886: ; | |
53477 | return 22; | |
53478 | } | |
53479 | unsigned long CPUFUNC(op_b1fa_5)(uint32_t opcode) /* CMPA */ | |
53480 | { | |
53481 | uint32_t dstreg = (opcode >> 9) & 7; | |
53482 | OpcodeFamily = 27; CurrentInstrCycles = 18; | |
53483 | {{ uint32_t srca = m68k_getpc () + 2; | |
53484 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
53485 | if ((srca & 1) != 0) { | |
53486 | last_fault_for_exception_3 = srca; | |
53487 | last_op_for_exception_3 = opcode; | |
53488 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
53489 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
53490 | goto endlabel2887; | |
53491 | } | |
53492 | {{ int32_t src = m68k_read_memory_32(srca); | |
53493 | { int32_t dst = m68k_areg(regs, dstreg); | |
53494 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
53495 | { int flgs = ((int32_t)(src)) < 0; | |
53496 | int flgo = ((int32_t)(dst)) < 0; | |
53497 | int flgn = ((int32_t)(newv)) < 0; | |
53498 | SET_ZFLG (((int32_t)(newv)) == 0); | |
53499 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
53500 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
53501 | SET_NFLG (flgn != 0); | |
53502 | }}}}}}}}m68k_incpc(4); | |
53503 | fill_prefetch_0 (); | |
53504 | endlabel2887: ; | |
53505 | return 18; | |
53506 | } | |
53507 | unsigned long CPUFUNC(op_b1fb_5)(uint32_t opcode) /* CMPA */ | |
53508 | { | |
53509 | uint32_t dstreg = (opcode >> 9) & 7; | |
53510 | OpcodeFamily = 27; CurrentInstrCycles = 20; | |
53511 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
53512 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
53513 | BusCyclePenalty += 2; | |
53514 | if ((srca & 1) != 0) { | |
53515 | last_fault_for_exception_3 = srca; | |
53516 | last_op_for_exception_3 = opcode; | |
53517 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
53518 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
53519 | goto endlabel2888; | |
53520 | } | |
53521 | {{ int32_t src = m68k_read_memory_32(srca); | |
53522 | { int32_t dst = m68k_areg(regs, dstreg); | |
53523 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
53524 | { int flgs = ((int32_t)(src)) < 0; | |
53525 | int flgo = ((int32_t)(dst)) < 0; | |
53526 | int flgn = ((int32_t)(newv)) < 0; | |
53527 | SET_ZFLG (((int32_t)(newv)) == 0); | |
53528 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
53529 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
53530 | SET_NFLG (flgn != 0); | |
53531 | }}}}}}}}m68k_incpc(4); | |
53532 | fill_prefetch_0 (); | |
53533 | endlabel2888: ; | |
53534 | return 20; | |
53535 | } | |
53536 | unsigned long CPUFUNC(op_b1fc_5)(uint32_t opcode) /* CMPA */ | |
53537 | { | |
53538 | uint32_t dstreg = (opcode >> 9) & 7; | |
53539 | OpcodeFamily = 27; CurrentInstrCycles = 14; | |
53540 | {{ int32_t src = get_ilong_prefetch(2); | |
53541 | { int32_t dst = m68k_areg(regs, dstreg); | |
53542 | {{uint32_t newv = ((int32_t)(dst)) - ((int32_t)(src)); | |
53543 | { int flgs = ((int32_t)(src)) < 0; | |
53544 | int flgo = ((int32_t)(dst)) < 0; | |
53545 | int flgn = ((int32_t)(newv)) < 0; | |
53546 | SET_ZFLG (((int32_t)(newv)) == 0); | |
53547 | SET_VFLG ((flgs != flgo) && (flgn != flgo)); | |
53548 | SET_CFLG (((uint32_t)(src)) > ((uint32_t)(dst))); | |
53549 | SET_NFLG (flgn != 0); | |
53550 | }}}}}}m68k_incpc(6); | |
53551 | fill_prefetch_0 (); | |
53552 | return 14; | |
53553 | } | |
53554 | unsigned long CPUFUNC(op_c000_5)(uint32_t opcode) /* AND */ | |
53555 | { | |
53556 | uint32_t srcreg = (opcode & 7); | |
53557 | uint32_t dstreg = (opcode >> 9) & 7; | |
53558 | OpcodeFamily = 2; CurrentInstrCycles = 4; | |
53559 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
53560 | { int8_t dst = m68k_dreg(regs, dstreg); | |
53561 | src &= dst; | |
53562 | CLEAR_CZNV; | |
53563 | SET_ZFLG (((int8_t)(src)) == 0); | |
53564 | SET_NFLG (((int8_t)(src)) < 0); | |
53565 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
53566 | }}}m68k_incpc(2); | |
53567 | fill_prefetch_2 (); | |
53568 | return 4; | |
53569 | } | |
53570 | unsigned long CPUFUNC(op_c010_5)(uint32_t opcode) /* AND */ | |
53571 | { | |
53572 | uint32_t srcreg = (opcode & 7); | |
53573 | uint32_t dstreg = (opcode >> 9) & 7; | |
53574 | OpcodeFamily = 2; CurrentInstrCycles = 8; | |
53575 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
53576 | { int8_t src = m68k_read_memory_8(srca); | |
53577 | { int8_t dst = m68k_dreg(regs, dstreg); | |
53578 | src &= dst; | |
53579 | CLEAR_CZNV; | |
53580 | SET_ZFLG (((int8_t)(src)) == 0); | |
53581 | SET_NFLG (((int8_t)(src)) < 0); | |
53582 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
53583 | }}}}m68k_incpc(2); | |
53584 | fill_prefetch_2 (); | |
53585 | return 8; | |
53586 | } | |
53587 | unsigned long CPUFUNC(op_c018_5)(uint32_t opcode) /* AND */ | |
53588 | { | |
53589 | uint32_t srcreg = (opcode & 7); | |
53590 | uint32_t dstreg = (opcode >> 9) & 7; | |
53591 | OpcodeFamily = 2; CurrentInstrCycles = 8; | |
53592 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
53593 | { int8_t src = m68k_read_memory_8(srca); | |
53594 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
53595 | { int8_t dst = m68k_dreg(regs, dstreg); | |
53596 | src &= dst; | |
53597 | CLEAR_CZNV; | |
53598 | SET_ZFLG (((int8_t)(src)) == 0); | |
53599 | SET_NFLG (((int8_t)(src)) < 0); | |
53600 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
53601 | }}}}m68k_incpc(2); | |
53602 | fill_prefetch_2 (); | |
53603 | return 8; | |
53604 | } | |
53605 | unsigned long CPUFUNC(op_c020_5)(uint32_t opcode) /* AND */ | |
53606 | { | |
53607 | uint32_t srcreg = (opcode & 7); | |
53608 | uint32_t dstreg = (opcode >> 9) & 7; | |
53609 | OpcodeFamily = 2; CurrentInstrCycles = 10; | |
53610 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
53611 | { int8_t src = m68k_read_memory_8(srca); | |
53612 | m68k_areg (regs, srcreg) = srca; | |
53613 | { int8_t dst = m68k_dreg(regs, dstreg); | |
53614 | src &= dst; | |
53615 | CLEAR_CZNV; | |
53616 | SET_ZFLG (((int8_t)(src)) == 0); | |
53617 | SET_NFLG (((int8_t)(src)) < 0); | |
53618 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
53619 | }}}}m68k_incpc(2); | |
53620 | fill_prefetch_2 (); | |
53621 | return 10; | |
53622 | } | |
53623 | unsigned long CPUFUNC(op_c028_5)(uint32_t opcode) /* AND */ | |
53624 | { | |
53625 | uint32_t srcreg = (opcode & 7); | |
53626 | uint32_t dstreg = (opcode >> 9) & 7; | |
53627 | OpcodeFamily = 2; CurrentInstrCycles = 12; | |
53628 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
53629 | { int8_t src = m68k_read_memory_8(srca); | |
53630 | { int8_t dst = m68k_dreg(regs, dstreg); | |
53631 | src &= dst; | |
53632 | CLEAR_CZNV; | |
53633 | SET_ZFLG (((int8_t)(src)) == 0); | |
53634 | SET_NFLG (((int8_t)(src)) < 0); | |
53635 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
53636 | }}}}m68k_incpc(4); | |
53637 | fill_prefetch_0 (); | |
53638 | return 12; | |
53639 | } | |
53640 | unsigned long CPUFUNC(op_c030_5)(uint32_t opcode) /* AND */ | |
53641 | { | |
53642 | uint32_t srcreg = (opcode & 7); | |
53643 | uint32_t dstreg = (opcode >> 9) & 7; | |
53644 | OpcodeFamily = 2; CurrentInstrCycles = 14; | |
53645 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
53646 | BusCyclePenalty += 2; | |
53647 | { int8_t src = m68k_read_memory_8(srca); | |
53648 | { int8_t dst = m68k_dreg(regs, dstreg); | |
53649 | src &= dst; | |
53650 | CLEAR_CZNV; | |
53651 | SET_ZFLG (((int8_t)(src)) == 0); | |
53652 | SET_NFLG (((int8_t)(src)) < 0); | |
53653 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
53654 | }}}}m68k_incpc(4); | |
53655 | fill_prefetch_0 (); | |
53656 | return 14; | |
53657 | } | |
53658 | unsigned long CPUFUNC(op_c038_5)(uint32_t opcode) /* AND */ | |
53659 | { | |
53660 | uint32_t dstreg = (opcode >> 9) & 7; | |
53661 | OpcodeFamily = 2; CurrentInstrCycles = 12; | |
53662 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
53663 | { int8_t src = m68k_read_memory_8(srca); | |
53664 | { int8_t dst = m68k_dreg(regs, dstreg); | |
53665 | src &= dst; | |
53666 | CLEAR_CZNV; | |
53667 | SET_ZFLG (((int8_t)(src)) == 0); | |
53668 | SET_NFLG (((int8_t)(src)) < 0); | |
53669 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
53670 | }}}}m68k_incpc(4); | |
53671 | fill_prefetch_0 (); | |
53672 | return 12; | |
53673 | } | |
53674 | unsigned long CPUFUNC(op_c039_5)(uint32_t opcode) /* AND */ | |
53675 | { | |
53676 | uint32_t dstreg = (opcode >> 9) & 7; | |
53677 | OpcodeFamily = 2; CurrentInstrCycles = 16; | |
53678 | {{ uint32_t srca = get_ilong_prefetch(2); | |
53679 | { int8_t src = m68k_read_memory_8(srca); | |
53680 | { int8_t dst = m68k_dreg(regs, dstreg); | |
53681 | src &= dst; | |
53682 | CLEAR_CZNV; | |
53683 | SET_ZFLG (((int8_t)(src)) == 0); | |
53684 | SET_NFLG (((int8_t)(src)) < 0); | |
53685 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
53686 | }}}}m68k_incpc(6); | |
53687 | fill_prefetch_0 (); | |
53688 | return 16; | |
53689 | } | |
53690 | unsigned long CPUFUNC(op_c03a_5)(uint32_t opcode) /* AND */ | |
53691 | { | |
53692 | uint32_t dstreg = (opcode >> 9) & 7; | |
53693 | OpcodeFamily = 2; CurrentInstrCycles = 12; | |
53694 | {{ uint32_t srca = m68k_getpc () + 2; | |
53695 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
53696 | { int8_t src = m68k_read_memory_8(srca); | |
53697 | { int8_t dst = m68k_dreg(regs, dstreg); | |
53698 | src &= dst; | |
53699 | CLEAR_CZNV; | |
53700 | SET_ZFLG (((int8_t)(src)) == 0); | |
53701 | SET_NFLG (((int8_t)(src)) < 0); | |
53702 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
53703 | }}}}m68k_incpc(4); | |
53704 | fill_prefetch_0 (); | |
53705 | return 12; | |
53706 | } | |
53707 | unsigned long CPUFUNC(op_c03b_5)(uint32_t opcode) /* AND */ | |
53708 | { | |
53709 | uint32_t dstreg = (opcode >> 9) & 7; | |
53710 | OpcodeFamily = 2; CurrentInstrCycles = 14; | |
53711 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
53712 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
53713 | BusCyclePenalty += 2; | |
53714 | { int8_t src = m68k_read_memory_8(srca); | |
53715 | { int8_t dst = m68k_dreg(regs, dstreg); | |
53716 | src &= dst; | |
53717 | CLEAR_CZNV; | |
53718 | SET_ZFLG (((int8_t)(src)) == 0); | |
53719 | SET_NFLG (((int8_t)(src)) < 0); | |
53720 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
53721 | }}}}m68k_incpc(4); | |
53722 | fill_prefetch_0 (); | |
53723 | return 14; | |
53724 | } | |
53725 | unsigned long CPUFUNC(op_c03c_5)(uint32_t opcode) /* AND */ | |
53726 | { | |
53727 | uint32_t dstreg = (opcode >> 9) & 7; | |
53728 | OpcodeFamily = 2; CurrentInstrCycles = 8; | |
53729 | {{ int8_t src = get_ibyte_prefetch(2); | |
53730 | { int8_t dst = m68k_dreg(regs, dstreg); | |
53731 | src &= dst; | |
53732 | CLEAR_CZNV; | |
53733 | SET_ZFLG (((int8_t)(src)) == 0); | |
53734 | SET_NFLG (((int8_t)(src)) < 0); | |
53735 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((src) & 0xff); | |
53736 | }}}m68k_incpc(4); | |
53737 | fill_prefetch_0 (); | |
53738 | return 8; | |
53739 | } | |
53740 | unsigned long CPUFUNC(op_c040_5)(uint32_t opcode) /* AND */ | |
53741 | { | |
53742 | uint32_t srcreg = (opcode & 7); | |
53743 | uint32_t dstreg = (opcode >> 9) & 7; | |
53744 | OpcodeFamily = 2; CurrentInstrCycles = 4; | |
53745 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
53746 | { int16_t dst = m68k_dreg(regs, dstreg); | |
53747 | src &= dst; | |
53748 | CLEAR_CZNV; | |
53749 | SET_ZFLG (((int16_t)(src)) == 0); | |
53750 | SET_NFLG (((int16_t)(src)) < 0); | |
53751 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
53752 | }}}m68k_incpc(2); | |
53753 | fill_prefetch_2 (); | |
53754 | return 4; | |
53755 | } | |
53756 | unsigned long CPUFUNC(op_c050_5)(uint32_t opcode) /* AND */ | |
53757 | { | |
53758 | uint32_t srcreg = (opcode & 7); | |
53759 | uint32_t dstreg = (opcode >> 9) & 7; | |
53760 | OpcodeFamily = 2; CurrentInstrCycles = 8; | |
53761 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
53762 | if ((srca & 1) != 0) { | |
53763 | last_fault_for_exception_3 = srca; | |
53764 | last_op_for_exception_3 = opcode; | |
53765 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
53766 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
53767 | goto endlabel2902; | |
53768 | } | |
53769 | {{ int16_t src = m68k_read_memory_16(srca); | |
53770 | { int16_t dst = m68k_dreg(regs, dstreg); | |
53771 | src &= dst; | |
53772 | CLEAR_CZNV; | |
53773 | SET_ZFLG (((int16_t)(src)) == 0); | |
53774 | SET_NFLG (((int16_t)(src)) < 0); | |
53775 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
53776 | }}}}}m68k_incpc(2); | |
53777 | fill_prefetch_2 (); | |
53778 | endlabel2902: ; | |
53779 | return 8; | |
53780 | } | |
53781 | unsigned long CPUFUNC(op_c058_5)(uint32_t opcode) /* AND */ | |
53782 | { | |
53783 | uint32_t srcreg = (opcode & 7); | |
53784 | uint32_t dstreg = (opcode >> 9) & 7; | |
53785 | OpcodeFamily = 2; CurrentInstrCycles = 8; | |
53786 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
53787 | if ((srca & 1) != 0) { | |
53788 | last_fault_for_exception_3 = srca; | |
53789 | last_op_for_exception_3 = opcode; | |
53790 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
53791 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
53792 | goto endlabel2903; | |
53793 | } | |
53794 | {{ int16_t src = m68k_read_memory_16(srca); | |
53795 | m68k_areg(regs, srcreg) += 2; | |
53796 | { int16_t dst = m68k_dreg(regs, dstreg); | |
53797 | src &= dst; | |
53798 | CLEAR_CZNV; | |
53799 | SET_ZFLG (((int16_t)(src)) == 0); | |
53800 | SET_NFLG (((int16_t)(src)) < 0); | |
53801 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
53802 | }}}}}m68k_incpc(2); | |
53803 | fill_prefetch_2 (); | |
53804 | endlabel2903: ; | |
53805 | return 8; | |
53806 | } | |
53807 | unsigned long CPUFUNC(op_c060_5)(uint32_t opcode) /* AND */ | |
53808 | { | |
53809 | uint32_t srcreg = (opcode & 7); | |
53810 | uint32_t dstreg = (opcode >> 9) & 7; | |
53811 | OpcodeFamily = 2; CurrentInstrCycles = 10; | |
53812 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
53813 | if ((srca & 1) != 0) { | |
53814 | last_fault_for_exception_3 = srca; | |
53815 | last_op_for_exception_3 = opcode; | |
53816 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
53817 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
53818 | goto endlabel2904; | |
53819 | } | |
53820 | {{ int16_t src = m68k_read_memory_16(srca); | |
53821 | m68k_areg (regs, srcreg) = srca; | |
53822 | { int16_t dst = m68k_dreg(regs, dstreg); | |
53823 | src &= dst; | |
53824 | CLEAR_CZNV; | |
53825 | SET_ZFLG (((int16_t)(src)) == 0); | |
53826 | SET_NFLG (((int16_t)(src)) < 0); | |
53827 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
53828 | }}}}}m68k_incpc(2); | |
53829 | fill_prefetch_2 (); | |
53830 | endlabel2904: ; | |
53831 | return 10; | |
53832 | } | |
53833 | unsigned long CPUFUNC(op_c068_5)(uint32_t opcode) /* AND */ | |
53834 | { | |
53835 | uint32_t srcreg = (opcode & 7); | |
53836 | uint32_t dstreg = (opcode >> 9) & 7; | |
53837 | OpcodeFamily = 2; CurrentInstrCycles = 12; | |
53838 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
53839 | if ((srca & 1) != 0) { | |
53840 | last_fault_for_exception_3 = srca; | |
53841 | last_op_for_exception_3 = opcode; | |
53842 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
53843 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
53844 | goto endlabel2905; | |
53845 | } | |
53846 | {{ int16_t src = m68k_read_memory_16(srca); | |
53847 | { int16_t dst = m68k_dreg(regs, dstreg); | |
53848 | src &= dst; | |
53849 | CLEAR_CZNV; | |
53850 | SET_ZFLG (((int16_t)(src)) == 0); | |
53851 | SET_NFLG (((int16_t)(src)) < 0); | |
53852 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
53853 | }}}}}m68k_incpc(4); | |
53854 | fill_prefetch_0 (); | |
53855 | endlabel2905: ; | |
53856 | return 12; | |
53857 | } | |
53858 | unsigned long CPUFUNC(op_c070_5)(uint32_t opcode) /* AND */ | |
53859 | { | |
53860 | uint32_t srcreg = (opcode & 7); | |
53861 | uint32_t dstreg = (opcode >> 9) & 7; | |
53862 | OpcodeFamily = 2; CurrentInstrCycles = 14; | |
53863 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
53864 | BusCyclePenalty += 2; | |
53865 | if ((srca & 1) != 0) { | |
53866 | last_fault_for_exception_3 = srca; | |
53867 | last_op_for_exception_3 = opcode; | |
53868 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
53869 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
53870 | goto endlabel2906; | |
53871 | } | |
53872 | {{ int16_t src = m68k_read_memory_16(srca); | |
53873 | { int16_t dst = m68k_dreg(regs, dstreg); | |
53874 | src &= dst; | |
53875 | CLEAR_CZNV; | |
53876 | SET_ZFLG (((int16_t)(src)) == 0); | |
53877 | SET_NFLG (((int16_t)(src)) < 0); | |
53878 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
53879 | }}}}}m68k_incpc(4); | |
53880 | fill_prefetch_0 (); | |
53881 | endlabel2906: ; | |
53882 | return 14; | |
53883 | } | |
53884 | unsigned long CPUFUNC(op_c078_5)(uint32_t opcode) /* AND */ | |
53885 | { | |
53886 | uint32_t dstreg = (opcode >> 9) & 7; | |
53887 | OpcodeFamily = 2; CurrentInstrCycles = 12; | |
53888 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
53889 | if ((srca & 1) != 0) { | |
53890 | last_fault_for_exception_3 = srca; | |
53891 | last_op_for_exception_3 = opcode; | |
53892 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
53893 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
53894 | goto endlabel2907; | |
53895 | } | |
53896 | {{ int16_t src = m68k_read_memory_16(srca); | |
53897 | { int16_t dst = m68k_dreg(regs, dstreg); | |
53898 | src &= dst; | |
53899 | CLEAR_CZNV; | |
53900 | SET_ZFLG (((int16_t)(src)) == 0); | |
53901 | SET_NFLG (((int16_t)(src)) < 0); | |
53902 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
53903 | }}}}}m68k_incpc(4); | |
53904 | fill_prefetch_0 (); | |
53905 | endlabel2907: ; | |
53906 | return 12; | |
53907 | } | |
53908 | unsigned long CPUFUNC(op_c079_5)(uint32_t opcode) /* AND */ | |
53909 | { | |
53910 | uint32_t dstreg = (opcode >> 9) & 7; | |
53911 | OpcodeFamily = 2; CurrentInstrCycles = 16; | |
53912 | {{ uint32_t srca = get_ilong_prefetch(2); | |
53913 | if ((srca & 1) != 0) { | |
53914 | last_fault_for_exception_3 = srca; | |
53915 | last_op_for_exception_3 = opcode; | |
53916 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
53917 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
53918 | goto endlabel2908; | |
53919 | } | |
53920 | {{ int16_t src = m68k_read_memory_16(srca); | |
53921 | { int16_t dst = m68k_dreg(regs, dstreg); | |
53922 | src &= dst; | |
53923 | CLEAR_CZNV; | |
53924 | SET_ZFLG (((int16_t)(src)) == 0); | |
53925 | SET_NFLG (((int16_t)(src)) < 0); | |
53926 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
53927 | }}}}}m68k_incpc(6); | |
53928 | fill_prefetch_0 (); | |
53929 | endlabel2908: ; | |
53930 | return 16; | |
53931 | } | |
53932 | unsigned long CPUFUNC(op_c07a_5)(uint32_t opcode) /* AND */ | |
53933 | { | |
53934 | uint32_t dstreg = (opcode >> 9) & 7; | |
53935 | OpcodeFamily = 2; CurrentInstrCycles = 12; | |
53936 | {{ uint32_t srca = m68k_getpc () + 2; | |
53937 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
53938 | if ((srca & 1) != 0) { | |
53939 | last_fault_for_exception_3 = srca; | |
53940 | last_op_for_exception_3 = opcode; | |
53941 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
53942 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
53943 | goto endlabel2909; | |
53944 | } | |
53945 | {{ int16_t src = m68k_read_memory_16(srca); | |
53946 | { int16_t dst = m68k_dreg(regs, dstreg); | |
53947 | src &= dst; | |
53948 | CLEAR_CZNV; | |
53949 | SET_ZFLG (((int16_t)(src)) == 0); | |
53950 | SET_NFLG (((int16_t)(src)) < 0); | |
53951 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
53952 | }}}}}m68k_incpc(4); | |
53953 | fill_prefetch_0 (); | |
53954 | endlabel2909: ; | |
53955 | return 12; | |
53956 | } | |
53957 | unsigned long CPUFUNC(op_c07b_5)(uint32_t opcode) /* AND */ | |
53958 | { | |
53959 | uint32_t dstreg = (opcode >> 9) & 7; | |
53960 | OpcodeFamily = 2; CurrentInstrCycles = 14; | |
53961 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
53962 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
53963 | BusCyclePenalty += 2; | |
53964 | if ((srca & 1) != 0) { | |
53965 | last_fault_for_exception_3 = srca; | |
53966 | last_op_for_exception_3 = opcode; | |
53967 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
53968 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
53969 | goto endlabel2910; | |
53970 | } | |
53971 | {{ int16_t src = m68k_read_memory_16(srca); | |
53972 | { int16_t dst = m68k_dreg(regs, dstreg); | |
53973 | src &= dst; | |
53974 | CLEAR_CZNV; | |
53975 | SET_ZFLG (((int16_t)(src)) == 0); | |
53976 | SET_NFLG (((int16_t)(src)) < 0); | |
53977 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
53978 | }}}}}m68k_incpc(4); | |
53979 | fill_prefetch_0 (); | |
53980 | endlabel2910: ; | |
53981 | return 14; | |
53982 | } | |
53983 | unsigned long CPUFUNC(op_c07c_5)(uint32_t opcode) /* AND */ | |
53984 | { | |
53985 | uint32_t dstreg = (opcode >> 9) & 7; | |
53986 | OpcodeFamily = 2; CurrentInstrCycles = 8; | |
53987 | {{ int16_t src = get_iword_prefetch(2); | |
53988 | { int16_t dst = m68k_dreg(regs, dstreg); | |
53989 | src &= dst; | |
53990 | CLEAR_CZNV; | |
53991 | SET_ZFLG (((int16_t)(src)) == 0); | |
53992 | SET_NFLG (((int16_t)(src)) < 0); | |
53993 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((src) & 0xffff); | |
53994 | }}}m68k_incpc(4); | |
53995 | fill_prefetch_0 (); | |
53996 | return 8; | |
53997 | } | |
53998 | unsigned long CPUFUNC(op_c080_5)(uint32_t opcode) /* AND */ | |
53999 | { | |
54000 | uint32_t srcreg = (opcode & 7); | |
54001 | uint32_t dstreg = (opcode >> 9) & 7; | |
54002 | OpcodeFamily = 2; CurrentInstrCycles = 8; | |
54003 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
54004 | { int32_t dst = m68k_dreg(regs, dstreg); | |
54005 | src &= dst; | |
54006 | CLEAR_CZNV; | |
54007 | SET_ZFLG (((int32_t)(src)) == 0); | |
54008 | SET_NFLG (((int32_t)(src)) < 0); | |
54009 | m68k_dreg(regs, dstreg) = (src); | |
54010 | }}}m68k_incpc(2); | |
54011 | fill_prefetch_2 (); | |
54012 | return 8; | |
54013 | } | |
54014 | unsigned long CPUFUNC(op_c090_5)(uint32_t opcode) /* AND */ | |
54015 | { | |
54016 | uint32_t srcreg = (opcode & 7); | |
54017 | uint32_t dstreg = (opcode >> 9) & 7; | |
54018 | OpcodeFamily = 2; CurrentInstrCycles = 14; | |
54019 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
54020 | if ((srca & 1) != 0) { | |
54021 | last_fault_for_exception_3 = srca; | |
54022 | last_op_for_exception_3 = opcode; | |
54023 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
54024 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
54025 | goto endlabel2913; | |
54026 | } | |
54027 | {{ int32_t src = m68k_read_memory_32(srca); | |
54028 | { int32_t dst = m68k_dreg(regs, dstreg); | |
54029 | src &= dst; | |
54030 | CLEAR_CZNV; | |
54031 | SET_ZFLG (((int32_t)(src)) == 0); | |
54032 | SET_NFLG (((int32_t)(src)) < 0); | |
54033 | m68k_dreg(regs, dstreg) = (src); | |
54034 | }}}}}m68k_incpc(2); | |
54035 | fill_prefetch_2 (); | |
54036 | endlabel2913: ; | |
54037 | return 14; | |
54038 | } | |
54039 | unsigned long CPUFUNC(op_c098_5)(uint32_t opcode) /* AND */ | |
54040 | { | |
54041 | uint32_t srcreg = (opcode & 7); | |
54042 | uint32_t dstreg = (opcode >> 9) & 7; | |
54043 | OpcodeFamily = 2; CurrentInstrCycles = 14; | |
54044 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
54045 | if ((srca & 1) != 0) { | |
54046 | last_fault_for_exception_3 = srca; | |
54047 | last_op_for_exception_3 = opcode; | |
54048 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
54049 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
54050 | goto endlabel2914; | |
54051 | } | |
54052 | {{ int32_t src = m68k_read_memory_32(srca); | |
54053 | m68k_areg(regs, srcreg) += 4; | |
54054 | { int32_t dst = m68k_dreg(regs, dstreg); | |
54055 | src &= dst; | |
54056 | CLEAR_CZNV; | |
54057 | SET_ZFLG (((int32_t)(src)) == 0); | |
54058 | SET_NFLG (((int32_t)(src)) < 0); | |
54059 | m68k_dreg(regs, dstreg) = (src); | |
54060 | }}}}}m68k_incpc(2); | |
54061 | fill_prefetch_2 (); | |
54062 | endlabel2914: ; | |
54063 | return 14; | |
54064 | } | |
54065 | unsigned long CPUFUNC(op_c0a0_5)(uint32_t opcode) /* AND */ | |
54066 | { | |
54067 | uint32_t srcreg = (opcode & 7); | |
54068 | uint32_t dstreg = (opcode >> 9) & 7; | |
54069 | OpcodeFamily = 2; CurrentInstrCycles = 16; | |
54070 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 4; | |
54071 | if ((srca & 1) != 0) { | |
54072 | last_fault_for_exception_3 = srca; | |
54073 | last_op_for_exception_3 = opcode; | |
54074 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
54075 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
54076 | goto endlabel2915; | |
54077 | } | |
54078 | {{ int32_t src = m68k_read_memory_32(srca); | |
54079 | m68k_areg (regs, srcreg) = srca; | |
54080 | { int32_t dst = m68k_dreg(regs, dstreg); | |
54081 | src &= dst; | |
54082 | CLEAR_CZNV; | |
54083 | SET_ZFLG (((int32_t)(src)) == 0); | |
54084 | SET_NFLG (((int32_t)(src)) < 0); | |
54085 | m68k_dreg(regs, dstreg) = (src); | |
54086 | }}}}}m68k_incpc(2); | |
54087 | fill_prefetch_2 (); | |
54088 | endlabel2915: ; | |
54089 | return 16; | |
54090 | } | |
54091 | unsigned long CPUFUNC(op_c0a8_5)(uint32_t opcode) /* AND */ | |
54092 | { | |
54093 | uint32_t srcreg = (opcode & 7); | |
54094 | uint32_t dstreg = (opcode >> 9) & 7; | |
54095 | OpcodeFamily = 2; CurrentInstrCycles = 18; | |
54096 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
54097 | if ((srca & 1) != 0) { | |
54098 | last_fault_for_exception_3 = srca; | |
54099 | last_op_for_exception_3 = opcode; | |
54100 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
54101 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
54102 | goto endlabel2916; | |
54103 | } | |
54104 | {{ int32_t src = m68k_read_memory_32(srca); | |
54105 | { int32_t dst = m68k_dreg(regs, dstreg); | |
54106 | src &= dst; | |
54107 | CLEAR_CZNV; | |
54108 | SET_ZFLG (((int32_t)(src)) == 0); | |
54109 | SET_NFLG (((int32_t)(src)) < 0); | |
54110 | m68k_dreg(regs, dstreg) = (src); | |
54111 | }}}}}m68k_incpc(4); | |
54112 | fill_prefetch_0 (); | |
54113 | endlabel2916: ; | |
54114 | return 18; | |
54115 | } | |
54116 | unsigned long CPUFUNC(op_c0b0_5)(uint32_t opcode) /* AND */ | |
54117 | { | |
54118 | uint32_t srcreg = (opcode & 7); | |
54119 | uint32_t dstreg = (opcode >> 9) & 7; | |
54120 | OpcodeFamily = 2; CurrentInstrCycles = 20; | |
54121 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
54122 | BusCyclePenalty += 2; | |
54123 | if ((srca & 1) != 0) { | |
54124 | last_fault_for_exception_3 = srca; | |
54125 | last_op_for_exception_3 = opcode; | |
54126 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
54127 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
54128 | goto endlabel2917; | |
54129 | } | |
54130 | {{ int32_t src = m68k_read_memory_32(srca); | |
54131 | { int32_t dst = m68k_dreg(regs, dstreg); | |
54132 | src &= dst; | |
54133 | CLEAR_CZNV; | |
54134 | SET_ZFLG (((int32_t)(src)) == 0); | |
54135 | SET_NFLG (((int32_t)(src)) < 0); | |
54136 | m68k_dreg(regs, dstreg) = (src); | |
54137 | }}}}}m68k_incpc(4); | |
54138 | fill_prefetch_0 (); | |
54139 | endlabel2917: ; | |
54140 | return 20; | |
54141 | } | |
54142 | unsigned long CPUFUNC(op_c0b8_5)(uint32_t opcode) /* AND */ | |
54143 | { | |
54144 | uint32_t dstreg = (opcode >> 9) & 7; | |
54145 | OpcodeFamily = 2; CurrentInstrCycles = 18; | |
54146 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
54147 | if ((srca & 1) != 0) { | |
54148 | last_fault_for_exception_3 = srca; | |
54149 | last_op_for_exception_3 = opcode; | |
54150 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
54151 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
54152 | goto endlabel2918; | |
54153 | } | |
54154 | {{ int32_t src = m68k_read_memory_32(srca); | |
54155 | { int32_t dst = m68k_dreg(regs, dstreg); | |
54156 | src &= dst; | |
54157 | CLEAR_CZNV; | |
54158 | SET_ZFLG (((int32_t)(src)) == 0); | |
54159 | SET_NFLG (((int32_t)(src)) < 0); | |
54160 | m68k_dreg(regs, dstreg) = (src); | |
54161 | }}}}}m68k_incpc(4); | |
54162 | fill_prefetch_0 (); | |
54163 | endlabel2918: ; | |
54164 | return 18; | |
54165 | } | |
54166 | unsigned long CPUFUNC(op_c0b9_5)(uint32_t opcode) /* AND */ | |
54167 | { | |
54168 | uint32_t dstreg = (opcode >> 9) & 7; | |
54169 | OpcodeFamily = 2; CurrentInstrCycles = 22; | |
54170 | {{ uint32_t srca = get_ilong_prefetch(2); | |
54171 | if ((srca & 1) != 0) { | |
54172 | last_fault_for_exception_3 = srca; | |
54173 | last_op_for_exception_3 = opcode; | |
54174 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
54175 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
54176 | goto endlabel2919; | |
54177 | } | |
54178 | {{ int32_t src = m68k_read_memory_32(srca); | |
54179 | { int32_t dst = m68k_dreg(regs, dstreg); | |
54180 | src &= dst; | |
54181 | CLEAR_CZNV; | |
54182 | SET_ZFLG (((int32_t)(src)) == 0); | |
54183 | SET_NFLG (((int32_t)(src)) < 0); | |
54184 | m68k_dreg(regs, dstreg) = (src); | |
54185 | }}}}}m68k_incpc(6); | |
54186 | fill_prefetch_0 (); | |
54187 | endlabel2919: ; | |
54188 | return 22; | |
54189 | } | |
54190 | unsigned long CPUFUNC(op_c0ba_5)(uint32_t opcode) /* AND */ | |
54191 | { | |
54192 | uint32_t dstreg = (opcode >> 9) & 7; | |
54193 | OpcodeFamily = 2; CurrentInstrCycles = 18; | |
54194 | {{ uint32_t srca = m68k_getpc () + 2; | |
54195 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
54196 | if ((srca & 1) != 0) { | |
54197 | last_fault_for_exception_3 = srca; | |
54198 | last_op_for_exception_3 = opcode; | |
54199 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
54200 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
54201 | goto endlabel2920; | |
54202 | } | |
54203 | {{ int32_t src = m68k_read_memory_32(srca); | |
54204 | { int32_t dst = m68k_dreg(regs, dstreg); | |
54205 | src &= dst; | |
54206 | CLEAR_CZNV; | |
54207 | SET_ZFLG (((int32_t)(src)) == 0); | |
54208 | SET_NFLG (((int32_t)(src)) < 0); | |
54209 | m68k_dreg(regs, dstreg) = (src); | |
54210 | }}}}}m68k_incpc(4); | |
54211 | fill_prefetch_0 (); | |
54212 | endlabel2920: ; | |
54213 | return 18; | |
54214 | } | |
54215 | unsigned long CPUFUNC(op_c0bb_5)(uint32_t opcode) /* AND */ | |
54216 | { | |
54217 | uint32_t dstreg = (opcode >> 9) & 7; | |
54218 | OpcodeFamily = 2; CurrentInstrCycles = 20; | |
54219 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
54220 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
54221 | BusCyclePenalty += 2; | |
54222 | if ((srca & 1) != 0) { | |
54223 | last_fault_for_exception_3 = srca; | |
54224 | last_op_for_exception_3 = opcode; | |
54225 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
54226 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
54227 | goto endlabel2921; | |
54228 | } | |
54229 | {{ int32_t src = m68k_read_memory_32(srca); | |
54230 | { int32_t dst = m68k_dreg(regs, dstreg); | |
54231 | src &= dst; | |
54232 | CLEAR_CZNV; | |
54233 | SET_ZFLG (((int32_t)(src)) == 0); | |
54234 | SET_NFLG (((int32_t)(src)) < 0); | |
54235 | m68k_dreg(regs, dstreg) = (src); | |
54236 | }}}}}m68k_incpc(4); | |
54237 | fill_prefetch_0 (); | |
54238 | endlabel2921: ; | |
54239 | return 20; | |
54240 | } | |
54241 | unsigned long CPUFUNC(op_c0bc_5)(uint32_t opcode) /* AND */ | |
54242 | { | |
54243 | uint32_t dstreg = (opcode >> 9) & 7; | |
54244 | OpcodeFamily = 2; CurrentInstrCycles = 16; | |
54245 | {{ int32_t src = get_ilong_prefetch(2); | |
54246 | { int32_t dst = m68k_dreg(regs, dstreg); | |
54247 | src &= dst; | |
54248 | CLEAR_CZNV; | |
54249 | SET_ZFLG (((int32_t)(src)) == 0); | |
54250 | SET_NFLG (((int32_t)(src)) < 0); | |
54251 | m68k_dreg(regs, dstreg) = (src); | |
54252 | }}}m68k_incpc(6); | |
54253 | fill_prefetch_0 (); | |
54254 | return 16; | |
54255 | } | |
54256 | unsigned long CPUFUNC(op_c0c0_5)(uint32_t opcode) /* MULU */ | |
54257 | { | |
54258 | uint32_t srcreg = (opcode & 7); | |
54259 | uint32_t dstreg = (opcode >> 9) & 7; | |
54260 | unsigned int retcycles = 0; | |
54261 | OpcodeFamily = 62; CurrentInstrCycles = 38; | |
54262 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
54263 | { int16_t dst = m68k_dreg(regs, dstreg); | |
54264 | { uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src; | |
54265 | CLEAR_CZNV; | |
54266 | SET_ZFLG (((int32_t)(newv)) == 0); | |
54267 | SET_NFLG (((int32_t)(newv)) < 0); | |
54268 | m68k_dreg(regs, dstreg) = (newv); | |
54269 | while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; } | |
54270 | }}}}m68k_incpc(2); | |
54271 | fill_prefetch_2 (); | |
54272 | return (38+retcycles*2); | |
54273 | } | |
54274 | unsigned long CPUFUNC(op_c0d0_5)(uint32_t opcode) /* MULU */ | |
54275 | { | |
54276 | uint32_t srcreg = (opcode & 7); | |
54277 | uint32_t dstreg = (opcode >> 9) & 7; | |
54278 | unsigned int retcycles = 0; | |
54279 | OpcodeFamily = 62; CurrentInstrCycles = 42; | |
54280 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
54281 | if ((srca & 1) != 0) { | |
54282 | last_fault_for_exception_3 = srca; | |
54283 | last_op_for_exception_3 = opcode; | |
54284 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
54285 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
54286 | goto endlabel2924; | |
54287 | } | |
54288 | {{ int16_t src = m68k_read_memory_16(srca); | |
54289 | { int16_t dst = m68k_dreg(regs, dstreg); | |
54290 | { uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src; | |
54291 | CLEAR_CZNV; | |
54292 | SET_ZFLG (((int32_t)(newv)) == 0); | |
54293 | SET_NFLG (((int32_t)(newv)) < 0); | |
54294 | m68k_dreg(regs, dstreg) = (newv); | |
54295 | while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; } | |
54296 | }}}}}}m68k_incpc(2); | |
54297 | fill_prefetch_2 (); | |
54298 | endlabel2924: ; | |
54299 | return (42+retcycles*2); | |
54300 | } | |
54301 | unsigned long CPUFUNC(op_c0d8_5)(uint32_t opcode) /* MULU */ | |
54302 | { | |
54303 | uint32_t srcreg = (opcode & 7); | |
54304 | uint32_t dstreg = (opcode >> 9) & 7; | |
54305 | unsigned int retcycles = 0; | |
54306 | OpcodeFamily = 62; CurrentInstrCycles = 42; | |
54307 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
54308 | if ((srca & 1) != 0) { | |
54309 | last_fault_for_exception_3 = srca; | |
54310 | last_op_for_exception_3 = opcode; | |
54311 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
54312 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
54313 | goto endlabel2925; | |
54314 | } | |
54315 | {{ int16_t src = m68k_read_memory_16(srca); | |
54316 | m68k_areg(regs, srcreg) += 2; | |
54317 | { int16_t dst = m68k_dreg(regs, dstreg); | |
54318 | { uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src; | |
54319 | CLEAR_CZNV; | |
54320 | SET_ZFLG (((int32_t)(newv)) == 0); | |
54321 | SET_NFLG (((int32_t)(newv)) < 0); | |
54322 | m68k_dreg(regs, dstreg) = (newv); | |
54323 | while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; } | |
54324 | }}}}}}m68k_incpc(2); | |
54325 | fill_prefetch_2 (); | |
54326 | endlabel2925: ; | |
54327 | return (42+retcycles*2); | |
54328 | } | |
54329 | unsigned long CPUFUNC(op_c0e0_5)(uint32_t opcode) /* MULU */ | |
54330 | { | |
54331 | uint32_t srcreg = (opcode & 7); | |
54332 | uint32_t dstreg = (opcode >> 9) & 7; | |
54333 | unsigned int retcycles = 0; | |
54334 | OpcodeFamily = 62; CurrentInstrCycles = 44; | |
54335 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
54336 | if ((srca & 1) != 0) { | |
54337 | last_fault_for_exception_3 = srca; | |
54338 | last_op_for_exception_3 = opcode; | |
54339 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
54340 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
54341 | goto endlabel2926; | |
54342 | } | |
54343 | {{ int16_t src = m68k_read_memory_16(srca); | |
54344 | m68k_areg (regs, srcreg) = srca; | |
54345 | { int16_t dst = m68k_dreg(regs, dstreg); | |
54346 | { uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src; | |
54347 | CLEAR_CZNV; | |
54348 | SET_ZFLG (((int32_t)(newv)) == 0); | |
54349 | SET_NFLG (((int32_t)(newv)) < 0); | |
54350 | m68k_dreg(regs, dstreg) = (newv); | |
54351 | while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; } | |
54352 | }}}}}}m68k_incpc(2); | |
54353 | fill_prefetch_2 (); | |
54354 | endlabel2926: ; | |
54355 | return (44+retcycles*2); | |
54356 | } | |
54357 | unsigned long CPUFUNC(op_c0e8_5)(uint32_t opcode) /* MULU */ | |
54358 | { | |
54359 | uint32_t srcreg = (opcode & 7); | |
54360 | uint32_t dstreg = (opcode >> 9) & 7; | |
54361 | unsigned int retcycles = 0; | |
54362 | OpcodeFamily = 62; CurrentInstrCycles = 46; | |
54363 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
54364 | if ((srca & 1) != 0) { | |
54365 | last_fault_for_exception_3 = srca; | |
54366 | last_op_for_exception_3 = opcode; | |
54367 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
54368 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
54369 | goto endlabel2927; | |
54370 | } | |
54371 | {{ int16_t src = m68k_read_memory_16(srca); | |
54372 | { int16_t dst = m68k_dreg(regs, dstreg); | |
54373 | { uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src; | |
54374 | CLEAR_CZNV; | |
54375 | SET_ZFLG (((int32_t)(newv)) == 0); | |
54376 | SET_NFLG (((int32_t)(newv)) < 0); | |
54377 | m68k_dreg(regs, dstreg) = (newv); | |
54378 | while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; } | |
54379 | }}}}}}m68k_incpc(4); | |
54380 | fill_prefetch_0 (); | |
54381 | endlabel2927: ; | |
54382 | return (46+retcycles*2); | |
54383 | } | |
54384 | unsigned long CPUFUNC(op_c0f0_5)(uint32_t opcode) /* MULU */ | |
54385 | { | |
54386 | uint32_t srcreg = (opcode & 7); | |
54387 | uint32_t dstreg = (opcode >> 9) & 7; | |
54388 | unsigned int retcycles = 0; | |
54389 | OpcodeFamily = 62; CurrentInstrCycles = 48; | |
54390 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
54391 | BusCyclePenalty += 2; | |
54392 | if ((srca & 1) != 0) { | |
54393 | last_fault_for_exception_3 = srca; | |
54394 | last_op_for_exception_3 = opcode; | |
54395 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
54396 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
54397 | goto endlabel2928; | |
54398 | } | |
54399 | {{ int16_t src = m68k_read_memory_16(srca); | |
54400 | { int16_t dst = m68k_dreg(regs, dstreg); | |
54401 | { uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src; | |
54402 | CLEAR_CZNV; | |
54403 | SET_ZFLG (((int32_t)(newv)) == 0); | |
54404 | SET_NFLG (((int32_t)(newv)) < 0); | |
54405 | m68k_dreg(regs, dstreg) = (newv); | |
54406 | while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; } | |
54407 | }}}}}}m68k_incpc(4); | |
54408 | fill_prefetch_0 (); | |
54409 | endlabel2928: ; | |
54410 | return (48+retcycles*2); | |
54411 | } | |
54412 | unsigned long CPUFUNC(op_c0f8_5)(uint32_t opcode) /* MULU */ | |
54413 | { | |
54414 | uint32_t dstreg = (opcode >> 9) & 7; | |
54415 | unsigned int retcycles = 0; | |
54416 | OpcodeFamily = 62; CurrentInstrCycles = 46; | |
54417 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
54418 | if ((srca & 1) != 0) { | |
54419 | last_fault_for_exception_3 = srca; | |
54420 | last_op_for_exception_3 = opcode; | |
54421 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
54422 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
54423 | goto endlabel2929; | |
54424 | } | |
54425 | {{ int16_t src = m68k_read_memory_16(srca); | |
54426 | { int16_t dst = m68k_dreg(regs, dstreg); | |
54427 | { uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src; | |
54428 | CLEAR_CZNV; | |
54429 | SET_ZFLG (((int32_t)(newv)) == 0); | |
54430 | SET_NFLG (((int32_t)(newv)) < 0); | |
54431 | m68k_dreg(regs, dstreg) = (newv); | |
54432 | while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; } | |
54433 | }}}}}}m68k_incpc(4); | |
54434 | fill_prefetch_0 (); | |
54435 | endlabel2929: ; | |
54436 | return (46+retcycles*2); | |
54437 | } | |
54438 | unsigned long CPUFUNC(op_c0f9_5)(uint32_t opcode) /* MULU */ | |
54439 | { | |
54440 | uint32_t dstreg = (opcode >> 9) & 7; | |
54441 | unsigned int retcycles = 0; | |
54442 | OpcodeFamily = 62; CurrentInstrCycles = 50; | |
54443 | {{ uint32_t srca = get_ilong_prefetch(2); | |
54444 | if ((srca & 1) != 0) { | |
54445 | last_fault_for_exception_3 = srca; | |
54446 | last_op_for_exception_3 = opcode; | |
54447 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
54448 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
54449 | goto endlabel2930; | |
54450 | } | |
54451 | {{ int16_t src = m68k_read_memory_16(srca); | |
54452 | { int16_t dst = m68k_dreg(regs, dstreg); | |
54453 | { uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src; | |
54454 | CLEAR_CZNV; | |
54455 | SET_ZFLG (((int32_t)(newv)) == 0); | |
54456 | SET_NFLG (((int32_t)(newv)) < 0); | |
54457 | m68k_dreg(regs, dstreg) = (newv); | |
54458 | while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; } | |
54459 | }}}}}}m68k_incpc(6); | |
54460 | fill_prefetch_0 (); | |
54461 | endlabel2930: ; | |
54462 | return (50+retcycles*2); | |
54463 | } | |
54464 | unsigned long CPUFUNC(op_c0fa_5)(uint32_t opcode) /* MULU */ | |
54465 | { | |
54466 | uint32_t dstreg = (opcode >> 9) & 7; | |
54467 | unsigned int retcycles = 0; | |
54468 | OpcodeFamily = 62; CurrentInstrCycles = 46; | |
54469 | {{ uint32_t srca = m68k_getpc () + 2; | |
54470 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
54471 | if ((srca & 1) != 0) { | |
54472 | last_fault_for_exception_3 = srca; | |
54473 | last_op_for_exception_3 = opcode; | |
54474 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
54475 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
54476 | goto endlabel2931; | |
54477 | } | |
54478 | {{ int16_t src = m68k_read_memory_16(srca); | |
54479 | { int16_t dst = m68k_dreg(regs, dstreg); | |
54480 | { uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src; | |
54481 | CLEAR_CZNV; | |
54482 | SET_ZFLG (((int32_t)(newv)) == 0); | |
54483 | SET_NFLG (((int32_t)(newv)) < 0); | |
54484 | m68k_dreg(regs, dstreg) = (newv); | |
54485 | while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; } | |
54486 | }}}}}}m68k_incpc(4); | |
54487 | fill_prefetch_0 (); | |
54488 | endlabel2931: ; | |
54489 | return (46+retcycles*2); | |
54490 | } | |
54491 | unsigned long CPUFUNC(op_c0fb_5)(uint32_t opcode) /* MULU */ | |
54492 | { | |
54493 | uint32_t dstreg = (opcode >> 9) & 7; | |
54494 | unsigned int retcycles = 0; | |
54495 | OpcodeFamily = 62; CurrentInstrCycles = 48; | |
54496 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
54497 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
54498 | BusCyclePenalty += 2; | |
54499 | if ((srca & 1) != 0) { | |
54500 | last_fault_for_exception_3 = srca; | |
54501 | last_op_for_exception_3 = opcode; | |
54502 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
54503 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
54504 | goto endlabel2932; | |
54505 | } | |
54506 | {{ int16_t src = m68k_read_memory_16(srca); | |
54507 | { int16_t dst = m68k_dreg(regs, dstreg); | |
54508 | { uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src; | |
54509 | CLEAR_CZNV; | |
54510 | SET_ZFLG (((int32_t)(newv)) == 0); | |
54511 | SET_NFLG (((int32_t)(newv)) < 0); | |
54512 | m68k_dreg(regs, dstreg) = (newv); | |
54513 | while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; } | |
54514 | }}}}}}m68k_incpc(4); | |
54515 | fill_prefetch_0 (); | |
54516 | endlabel2932: ; | |
54517 | return (48+retcycles*2); | |
54518 | } | |
54519 | unsigned long CPUFUNC(op_c0fc_5)(uint32_t opcode) /* MULU */ | |
54520 | { | |
54521 | uint32_t dstreg = (opcode >> 9) & 7; | |
54522 | unsigned int retcycles = 0; | |
54523 | OpcodeFamily = 62; CurrentInstrCycles = 42; | |
54524 | {{ int16_t src = get_iword_prefetch(2); | |
54525 | { int16_t dst = m68k_dreg(regs, dstreg); | |
54526 | { uint32_t newv = (uint32_t)(uint16_t)dst * (uint32_t)(uint16_t)src; | |
54527 | CLEAR_CZNV; | |
54528 | SET_ZFLG (((int32_t)(newv)) == 0); | |
54529 | SET_NFLG (((int32_t)(newv)) < 0); | |
54530 | m68k_dreg(regs, dstreg) = (newv); | |
54531 | while (src) { if (src & 1) retcycles++; src = (uint16_t)src >> 1; } | |
54532 | }}}}m68k_incpc(4); | |
54533 | fill_prefetch_0 (); | |
54534 | return (42+retcycles*2); | |
54535 | } | |
54536 | unsigned long CPUFUNC(op_c100_5)(uint32_t opcode) /* ABCD */ | |
54537 | { | |
54538 | uint32_t srcreg = (opcode & 7); | |
54539 | uint32_t dstreg = (opcode >> 9) & 7; | |
54540 | OpcodeFamily = 14; CurrentInstrCycles = 6; | |
54541 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
54542 | { int8_t dst = m68k_dreg(regs, dstreg); | |
54543 | { uint16_t newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG ? 1 : 0); | |
54544 | uint16_t newv_hi = (src & 0xF0) + (dst & 0xF0); | |
54545 | uint16_t newv, tmp_newv; | |
54546 | int cflg; | |
54547 | newv = tmp_newv = newv_hi + newv_lo; if (newv_lo > 9) { newv += 6; } | |
54548 | cflg = (newv & 0x3F0) > 0x90; | |
54549 | if (cflg) newv += 0x60; | |
54550 | SET_CFLG (cflg); | |
54551 | COPY_CARRY; | |
54552 | SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); | |
54553 | SET_NFLG (((int8_t)(newv)) < 0); | |
54554 | SET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0); | |
54555 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
54556 | }}}}m68k_incpc(2); | |
54557 | fill_prefetch_2 (); | |
54558 | return 6; | |
54559 | } | |
54560 | unsigned long CPUFUNC(op_c108_5)(uint32_t opcode) /* ABCD */ | |
54561 | { | |
54562 | uint32_t srcreg = (opcode & 7); | |
54563 | uint32_t dstreg = (opcode >> 9) & 7; | |
54564 | OpcodeFamily = 14; CurrentInstrCycles = 18; | |
54565 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
54566 | { int8_t src = m68k_read_memory_8(srca); | |
54567 | m68k_areg (regs, srcreg) = srca; | |
54568 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
54569 | { int8_t dst = m68k_read_memory_8(dsta); | |
54570 | m68k_areg (regs, dstreg) = dsta; | |
54571 | { uint16_t newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG ? 1 : 0); | |
54572 | uint16_t newv_hi = (src & 0xF0) + (dst & 0xF0); | |
54573 | uint16_t newv, tmp_newv; | |
54574 | int cflg; | |
54575 | newv = tmp_newv = newv_hi + newv_lo; if (newv_lo > 9) { newv += 6; } | |
54576 | cflg = (newv & 0x3F0) > 0x90; | |
54577 | if (cflg) newv += 0x60; | |
54578 | SET_CFLG (cflg); | |
54579 | COPY_CARRY; | |
54580 | SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); | |
54581 | SET_NFLG (((int8_t)(newv)) < 0); | |
54582 | SET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0); | |
54583 | m68k_incpc(2); | |
54584 | fill_prefetch_2 (); | |
54585 | m68k_write_memory_8(dsta,newv); | |
54586 | }}}}}}return 18; | |
54587 | } | |
54588 | unsigned long CPUFUNC(op_c110_5)(uint32_t opcode) /* AND */ | |
54589 | { | |
54590 | uint32_t srcreg = ((opcode >> 9) & 7); | |
54591 | uint32_t dstreg = opcode & 7; | |
54592 | OpcodeFamily = 2; CurrentInstrCycles = 12; | |
54593 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
54594 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
54595 | { int8_t dst = m68k_read_memory_8(dsta); | |
54596 | src &= dst; | |
54597 | CLEAR_CZNV; | |
54598 | SET_ZFLG (((int8_t)(src)) == 0); | |
54599 | SET_NFLG (((int8_t)(src)) < 0); | |
54600 | m68k_incpc(2); | |
54601 | fill_prefetch_2 (); | |
54602 | m68k_write_memory_8(dsta,src); | |
54603 | }}}}return 12; | |
54604 | } | |
54605 | unsigned long CPUFUNC(op_c118_5)(uint32_t opcode) /* AND */ | |
54606 | { | |
54607 | uint32_t srcreg = ((opcode >> 9) & 7); | |
54608 | uint32_t dstreg = opcode & 7; | |
54609 | OpcodeFamily = 2; CurrentInstrCycles = 12; | |
54610 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
54611 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
54612 | { int8_t dst = m68k_read_memory_8(dsta); | |
54613 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
54614 | src &= dst; | |
54615 | CLEAR_CZNV; | |
54616 | SET_ZFLG (((int8_t)(src)) == 0); | |
54617 | SET_NFLG (((int8_t)(src)) < 0); | |
54618 | m68k_incpc(2); | |
54619 | fill_prefetch_2 (); | |
54620 | m68k_write_memory_8(dsta,src); | |
54621 | }}}}return 12; | |
54622 | } | |
54623 | unsigned long CPUFUNC(op_c120_5)(uint32_t opcode) /* AND */ | |
54624 | { | |
54625 | uint32_t srcreg = ((opcode >> 9) & 7); | |
54626 | uint32_t dstreg = opcode & 7; | |
54627 | OpcodeFamily = 2; CurrentInstrCycles = 14; | |
54628 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
54629 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
54630 | { int8_t dst = m68k_read_memory_8(dsta); | |
54631 | m68k_areg (regs, dstreg) = dsta; | |
54632 | src &= dst; | |
54633 | CLEAR_CZNV; | |
54634 | SET_ZFLG (((int8_t)(src)) == 0); | |
54635 | SET_NFLG (((int8_t)(src)) < 0); | |
54636 | m68k_incpc(2); | |
54637 | fill_prefetch_2 (); | |
54638 | m68k_write_memory_8(dsta,src); | |
54639 | }}}}return 14; | |
54640 | } | |
54641 | unsigned long CPUFUNC(op_c128_5)(uint32_t opcode) /* AND */ | |
54642 | { | |
54643 | uint32_t srcreg = ((opcode >> 9) & 7); | |
54644 | uint32_t dstreg = opcode & 7; | |
54645 | OpcodeFamily = 2; CurrentInstrCycles = 16; | |
54646 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
54647 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
54648 | { int8_t dst = m68k_read_memory_8(dsta); | |
54649 | src &= dst; | |
54650 | CLEAR_CZNV; | |
54651 | SET_ZFLG (((int8_t)(src)) == 0); | |
54652 | SET_NFLG (((int8_t)(src)) < 0); | |
54653 | m68k_incpc(4); | |
54654 | fill_prefetch_0 (); | |
54655 | m68k_write_memory_8(dsta,src); | |
54656 | }}}}return 16; | |
54657 | } | |
54658 | unsigned long CPUFUNC(op_c130_5)(uint32_t opcode) /* AND */ | |
54659 | { | |
54660 | uint32_t srcreg = ((opcode >> 9) & 7); | |
54661 | uint32_t dstreg = opcode & 7; | |
54662 | OpcodeFamily = 2; CurrentInstrCycles = 18; | |
54663 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
54664 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); | |
54665 | BusCyclePenalty += 2; | |
54666 | { int8_t dst = m68k_read_memory_8(dsta); | |
54667 | src &= dst; | |
54668 | CLEAR_CZNV; | |
54669 | SET_ZFLG (((int8_t)(src)) == 0); | |
54670 | SET_NFLG (((int8_t)(src)) < 0); | |
54671 | m68k_incpc(4); | |
54672 | fill_prefetch_0 (); | |
54673 | m68k_write_memory_8(dsta,src); | |
54674 | }}}}return 18; | |
54675 | } | |
54676 | unsigned long CPUFUNC(op_c138_5)(uint32_t opcode) /* AND */ | |
54677 | { | |
54678 | uint32_t srcreg = ((opcode >> 9) & 7); | |
54679 | OpcodeFamily = 2; CurrentInstrCycles = 16; | |
54680 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
54681 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); | |
54682 | { int8_t dst = m68k_read_memory_8(dsta); | |
54683 | src &= dst; | |
54684 | CLEAR_CZNV; | |
54685 | SET_ZFLG (((int8_t)(src)) == 0); | |
54686 | SET_NFLG (((int8_t)(src)) < 0); | |
54687 | m68k_incpc(4); | |
54688 | fill_prefetch_0 (); | |
54689 | m68k_write_memory_8(dsta,src); | |
54690 | }}}}return 16; | |
54691 | } | |
54692 | unsigned long CPUFUNC(op_c139_5)(uint32_t opcode) /* AND */ | |
54693 | { | |
54694 | uint32_t srcreg = ((opcode >> 9) & 7); | |
54695 | OpcodeFamily = 2; CurrentInstrCycles = 20; | |
54696 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
54697 | { uint32_t dsta = get_ilong_prefetch(2); | |
54698 | { int8_t dst = m68k_read_memory_8(dsta); | |
54699 | src &= dst; | |
54700 | CLEAR_CZNV; | |
54701 | SET_ZFLG (((int8_t)(src)) == 0); | |
54702 | SET_NFLG (((int8_t)(src)) < 0); | |
54703 | m68k_incpc(6); | |
54704 | fill_prefetch_0 (); | |
54705 | m68k_write_memory_8(dsta,src); | |
54706 | }}}}return 20; | |
54707 | } | |
54708 | unsigned long CPUFUNC(op_c140_5)(uint32_t opcode) /* EXG */ | |
54709 | { | |
54710 | uint32_t srcreg = ((opcode >> 9) & 7); | |
54711 | uint32_t dstreg = opcode & 7; | |
54712 | OpcodeFamily = 35; CurrentInstrCycles = 6; | |
54713 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
54714 | { int32_t dst = m68k_dreg(regs, dstreg); | |
54715 | m68k_dreg(regs, srcreg) = (dst); | |
54716 | m68k_dreg(regs, dstreg) = (src); | |
54717 | }}}m68k_incpc(2); | |
54718 | fill_prefetch_2 (); | |
54719 | return 6; | |
54720 | } | |
54721 | unsigned long CPUFUNC(op_c148_5)(uint32_t opcode) /* EXG */ | |
54722 | { | |
54723 | uint32_t srcreg = ((opcode >> 9) & 7); | |
54724 | uint32_t dstreg = opcode & 7; | |
54725 | OpcodeFamily = 35; CurrentInstrCycles = 6; | |
54726 | {{ int32_t src = m68k_areg(regs, srcreg); | |
54727 | { int32_t dst = m68k_areg(regs, dstreg); | |
54728 | m68k_areg(regs, srcreg) = (dst); | |
54729 | m68k_areg(regs, dstreg) = (src); | |
54730 | }}}m68k_incpc(2); | |
54731 | fill_prefetch_2 (); | |
54732 | return 6; | |
54733 | } | |
54734 | unsigned long CPUFUNC(op_c150_5)(uint32_t opcode) /* AND */ | |
54735 | { | |
54736 | uint32_t srcreg = ((opcode >> 9) & 7); | |
54737 | uint32_t dstreg = opcode & 7; | |
54738 | OpcodeFamily = 2; CurrentInstrCycles = 12; | |
54739 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
54740 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
54741 | if ((dsta & 1) != 0) { | |
54742 | last_fault_for_exception_3 = dsta; | |
54743 | last_op_for_exception_3 = opcode; | |
54744 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
54745 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
54746 | goto endlabel2945; | |
54747 | } | |
54748 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
54749 | src &= dst; | |
54750 | CLEAR_CZNV; | |
54751 | SET_ZFLG (((int16_t)(src)) == 0); | |
54752 | SET_NFLG (((int16_t)(src)) < 0); | |
54753 | m68k_incpc(2); | |
54754 | fill_prefetch_2 (); | |
54755 | m68k_write_memory_16(dsta,src); | |
54756 | }}}}}endlabel2945: ; | |
54757 | return 12; | |
54758 | } | |
54759 | unsigned long CPUFUNC(op_c158_5)(uint32_t opcode) /* AND */ | |
54760 | { | |
54761 | uint32_t srcreg = ((opcode >> 9) & 7); | |
54762 | uint32_t dstreg = opcode & 7; | |
54763 | OpcodeFamily = 2; CurrentInstrCycles = 12; | |
54764 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
54765 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
54766 | if ((dsta & 1) != 0) { | |
54767 | last_fault_for_exception_3 = dsta; | |
54768 | last_op_for_exception_3 = opcode; | |
54769 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
54770 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
54771 | goto endlabel2946; | |
54772 | } | |
54773 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
54774 | m68k_areg(regs, dstreg) += 2; | |
54775 | src &= dst; | |
54776 | CLEAR_CZNV; | |
54777 | SET_ZFLG (((int16_t)(src)) == 0); | |
54778 | SET_NFLG (((int16_t)(src)) < 0); | |
54779 | m68k_incpc(2); | |
54780 | fill_prefetch_2 (); | |
54781 | m68k_write_memory_16(dsta,src); | |
54782 | }}}}}endlabel2946: ; | |
54783 | return 12; | |
54784 | } | |
54785 | unsigned long CPUFUNC(op_c160_5)(uint32_t opcode) /* AND */ | |
54786 | { | |
54787 | uint32_t srcreg = ((opcode >> 9) & 7); | |
54788 | uint32_t dstreg = opcode & 7; | |
54789 | OpcodeFamily = 2; CurrentInstrCycles = 14; | |
54790 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
54791 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
54792 | if ((dsta & 1) != 0) { | |
54793 | last_fault_for_exception_3 = dsta; | |
54794 | last_op_for_exception_3 = opcode; | |
54795 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
54796 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
54797 | goto endlabel2947; | |
54798 | } | |
54799 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
54800 | m68k_areg (regs, dstreg) = dsta; | |
54801 | src &= dst; | |
54802 | CLEAR_CZNV; | |
54803 | SET_ZFLG (((int16_t)(src)) == 0); | |
54804 | SET_NFLG (((int16_t)(src)) < 0); | |
54805 | m68k_incpc(2); | |
54806 | fill_prefetch_2 (); | |
54807 | m68k_write_memory_16(dsta,src); | |
54808 | }}}}}endlabel2947: ; | |
54809 | return 14; | |
54810 | } | |
54811 | unsigned long CPUFUNC(op_c168_5)(uint32_t opcode) /* AND */ | |
54812 | { | |
54813 | uint32_t srcreg = ((opcode >> 9) & 7); | |
54814 | uint32_t dstreg = opcode & 7; | |
54815 | OpcodeFamily = 2; CurrentInstrCycles = 16; | |
54816 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
54817 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
54818 | if ((dsta & 1) != 0) { | |
54819 | last_fault_for_exception_3 = dsta; | |
54820 | last_op_for_exception_3 = opcode; | |
54821 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
54822 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
54823 | goto endlabel2948; | |
54824 | } | |
54825 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
54826 | src &= dst; | |
54827 | CLEAR_CZNV; | |
54828 | SET_ZFLG (((int16_t)(src)) == 0); | |
54829 | SET_NFLG (((int16_t)(src)) < 0); | |
54830 | m68k_incpc(4); | |
54831 | fill_prefetch_0 (); | |
54832 | m68k_write_memory_16(dsta,src); | |
54833 | }}}}}endlabel2948: ; | |
54834 | return 16; | |
54835 | } | |
54836 | unsigned long CPUFUNC(op_c170_5)(uint32_t opcode) /* AND */ | |
54837 | { | |
54838 | uint32_t srcreg = ((opcode >> 9) & 7); | |
54839 | uint32_t dstreg = opcode & 7; | |
54840 | OpcodeFamily = 2; CurrentInstrCycles = 18; | |
54841 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
54842 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); | |
54843 | BusCyclePenalty += 2; | |
54844 | if ((dsta & 1) != 0) { | |
54845 | last_fault_for_exception_3 = dsta; | |
54846 | last_op_for_exception_3 = opcode; | |
54847 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
54848 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
54849 | goto endlabel2949; | |
54850 | } | |
54851 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
54852 | src &= dst; | |
54853 | CLEAR_CZNV; | |
54854 | SET_ZFLG (((int16_t)(src)) == 0); | |
54855 | SET_NFLG (((int16_t)(src)) < 0); | |
54856 | m68k_incpc(4); | |
54857 | fill_prefetch_0 (); | |
54858 | m68k_write_memory_16(dsta,src); | |
54859 | }}}}}endlabel2949: ; | |
54860 | return 18; | |
54861 | } | |
54862 | unsigned long CPUFUNC(op_c178_5)(uint32_t opcode) /* AND */ | |
54863 | { | |
54864 | uint32_t srcreg = ((opcode >> 9) & 7); | |
54865 | OpcodeFamily = 2; CurrentInstrCycles = 16; | |
54866 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
54867 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); | |
54868 | if ((dsta & 1) != 0) { | |
54869 | last_fault_for_exception_3 = dsta; | |
54870 | last_op_for_exception_3 = opcode; | |
54871 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
54872 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
54873 | goto endlabel2950; | |
54874 | } | |
54875 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
54876 | src &= dst; | |
54877 | CLEAR_CZNV; | |
54878 | SET_ZFLG (((int16_t)(src)) == 0); | |
54879 | SET_NFLG (((int16_t)(src)) < 0); | |
54880 | m68k_incpc(4); | |
54881 | fill_prefetch_0 (); | |
54882 | m68k_write_memory_16(dsta,src); | |
54883 | }}}}}endlabel2950: ; | |
54884 | return 16; | |
54885 | } | |
54886 | unsigned long CPUFUNC(op_c179_5)(uint32_t opcode) /* AND */ | |
54887 | { | |
54888 | uint32_t srcreg = ((opcode >> 9) & 7); | |
54889 | OpcodeFamily = 2; CurrentInstrCycles = 20; | |
54890 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
54891 | { uint32_t dsta = get_ilong_prefetch(2); | |
54892 | if ((dsta & 1) != 0) { | |
54893 | last_fault_for_exception_3 = dsta; | |
54894 | last_op_for_exception_3 = opcode; | |
54895 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
54896 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
54897 | goto endlabel2951; | |
54898 | } | |
54899 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
54900 | src &= dst; | |
54901 | CLEAR_CZNV; | |
54902 | SET_ZFLG (((int16_t)(src)) == 0); | |
54903 | SET_NFLG (((int16_t)(src)) < 0); | |
54904 | m68k_incpc(6); | |
54905 | fill_prefetch_0 (); | |
54906 | m68k_write_memory_16(dsta,src); | |
54907 | }}}}}endlabel2951: ; | |
54908 | return 20; | |
54909 | } | |
54910 | unsigned long CPUFUNC(op_c188_5)(uint32_t opcode) /* EXG */ | |
54911 | { | |
54912 | uint32_t srcreg = ((opcode >> 9) & 7); | |
54913 | uint32_t dstreg = opcode & 7; | |
54914 | OpcodeFamily = 35; CurrentInstrCycles = 6; | |
54915 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
54916 | { int32_t dst = m68k_areg(regs, dstreg); | |
54917 | m68k_dreg(regs, srcreg) = (dst); | |
54918 | m68k_areg(regs, dstreg) = (src); | |
54919 | }}}m68k_incpc(2); | |
54920 | fill_prefetch_2 (); | |
54921 | return 6; | |
54922 | } | |
54923 | unsigned long CPUFUNC(op_c190_5)(uint32_t opcode) /* AND */ | |
54924 | { | |
54925 | uint32_t srcreg = ((opcode >> 9) & 7); | |
54926 | uint32_t dstreg = opcode & 7; | |
54927 | OpcodeFamily = 2; CurrentInstrCycles = 20; | |
54928 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
54929 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
54930 | if ((dsta & 1) != 0) { | |
54931 | last_fault_for_exception_3 = dsta; | |
54932 | last_op_for_exception_3 = opcode; | |
54933 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
54934 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
54935 | goto endlabel2953; | |
54936 | } | |
54937 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
54938 | src &= dst; | |
54939 | CLEAR_CZNV; | |
54940 | SET_ZFLG (((int32_t)(src)) == 0); | |
54941 | SET_NFLG (((int32_t)(src)) < 0); | |
54942 | m68k_incpc(2); | |
54943 | fill_prefetch_2 (); | |
54944 | m68k_write_memory_32(dsta,src); | |
54945 | }}}}}endlabel2953: ; | |
54946 | return 20; | |
54947 | } | |
54948 | unsigned long CPUFUNC(op_c198_5)(uint32_t opcode) /* AND */ | |
54949 | { | |
54950 | uint32_t srcreg = ((opcode >> 9) & 7); | |
54951 | uint32_t dstreg = opcode & 7; | |
54952 | OpcodeFamily = 2; CurrentInstrCycles = 20; | |
54953 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
54954 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
54955 | if ((dsta & 1) != 0) { | |
54956 | last_fault_for_exception_3 = dsta; | |
54957 | last_op_for_exception_3 = opcode; | |
54958 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
54959 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
54960 | goto endlabel2954; | |
54961 | } | |
54962 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
54963 | m68k_areg(regs, dstreg) += 4; | |
54964 | src &= dst; | |
54965 | CLEAR_CZNV; | |
54966 | SET_ZFLG (((int32_t)(src)) == 0); | |
54967 | SET_NFLG (((int32_t)(src)) < 0); | |
54968 | m68k_incpc(2); | |
54969 | fill_prefetch_2 (); | |
54970 | m68k_write_memory_32(dsta,src); | |
54971 | }}}}}endlabel2954: ; | |
54972 | return 20; | |
54973 | } | |
54974 | unsigned long CPUFUNC(op_c1a0_5)(uint32_t opcode) /* AND */ | |
54975 | { | |
54976 | uint32_t srcreg = ((opcode >> 9) & 7); | |
54977 | uint32_t dstreg = opcode & 7; | |
54978 | OpcodeFamily = 2; CurrentInstrCycles = 22; | |
54979 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
54980 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
54981 | if ((dsta & 1) != 0) { | |
54982 | last_fault_for_exception_3 = dsta; | |
54983 | last_op_for_exception_3 = opcode; | |
54984 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
54985 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
54986 | goto endlabel2955; | |
54987 | } | |
54988 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
54989 | m68k_areg (regs, dstreg) = dsta; | |
54990 | src &= dst; | |
54991 | CLEAR_CZNV; | |
54992 | SET_ZFLG (((int32_t)(src)) == 0); | |
54993 | SET_NFLG (((int32_t)(src)) < 0); | |
54994 | m68k_incpc(2); | |
54995 | fill_prefetch_2 (); | |
54996 | m68k_write_memory_32(dsta,src); | |
54997 | }}}}}endlabel2955: ; | |
54998 | return 22; | |
54999 | } | |
55000 | unsigned long CPUFUNC(op_c1a8_5)(uint32_t opcode) /* AND */ | |
55001 | { | |
55002 | uint32_t srcreg = ((opcode >> 9) & 7); | |
55003 | uint32_t dstreg = opcode & 7; | |
55004 | OpcodeFamily = 2; CurrentInstrCycles = 24; | |
55005 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
55006 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
55007 | if ((dsta & 1) != 0) { | |
55008 | last_fault_for_exception_3 = dsta; | |
55009 | last_op_for_exception_3 = opcode; | |
55010 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
55011 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
55012 | goto endlabel2956; | |
55013 | } | |
55014 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
55015 | src &= dst; | |
55016 | CLEAR_CZNV; | |
55017 | SET_ZFLG (((int32_t)(src)) == 0); | |
55018 | SET_NFLG (((int32_t)(src)) < 0); | |
55019 | m68k_incpc(4); | |
55020 | fill_prefetch_0 (); | |
55021 | m68k_write_memory_32(dsta,src); | |
55022 | }}}}}endlabel2956: ; | |
55023 | return 24; | |
55024 | } | |
55025 | unsigned long CPUFUNC(op_c1b0_5)(uint32_t opcode) /* AND */ | |
55026 | { | |
55027 | uint32_t srcreg = ((opcode >> 9) & 7); | |
55028 | uint32_t dstreg = opcode & 7; | |
55029 | OpcodeFamily = 2; CurrentInstrCycles = 26; | |
55030 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
55031 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); | |
55032 | BusCyclePenalty += 2; | |
55033 | if ((dsta & 1) != 0) { | |
55034 | last_fault_for_exception_3 = dsta; | |
55035 | last_op_for_exception_3 = opcode; | |
55036 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
55037 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
55038 | goto endlabel2957; | |
55039 | } | |
55040 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
55041 | src &= dst; | |
55042 | CLEAR_CZNV; | |
55043 | SET_ZFLG (((int32_t)(src)) == 0); | |
55044 | SET_NFLG (((int32_t)(src)) < 0); | |
55045 | m68k_incpc(4); | |
55046 | fill_prefetch_0 (); | |
55047 | m68k_write_memory_32(dsta,src); | |
55048 | }}}}}endlabel2957: ; | |
55049 | return 26; | |
55050 | } | |
55051 | unsigned long CPUFUNC(op_c1b8_5)(uint32_t opcode) /* AND */ | |
55052 | { | |
55053 | uint32_t srcreg = ((opcode >> 9) & 7); | |
55054 | OpcodeFamily = 2; CurrentInstrCycles = 24; | |
55055 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
55056 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); | |
55057 | if ((dsta & 1) != 0) { | |
55058 | last_fault_for_exception_3 = dsta; | |
55059 | last_op_for_exception_3 = opcode; | |
55060 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
55061 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
55062 | goto endlabel2958; | |
55063 | } | |
55064 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
55065 | src &= dst; | |
55066 | CLEAR_CZNV; | |
55067 | SET_ZFLG (((int32_t)(src)) == 0); | |
55068 | SET_NFLG (((int32_t)(src)) < 0); | |
55069 | m68k_incpc(4); | |
55070 | fill_prefetch_0 (); | |
55071 | m68k_write_memory_32(dsta,src); | |
55072 | }}}}}endlabel2958: ; | |
55073 | return 24; | |
55074 | } | |
55075 | unsigned long CPUFUNC(op_c1b9_5)(uint32_t opcode) /* AND */ | |
55076 | { | |
55077 | uint32_t srcreg = ((opcode >> 9) & 7); | |
55078 | OpcodeFamily = 2; CurrentInstrCycles = 28; | |
55079 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
55080 | { uint32_t dsta = get_ilong_prefetch(2); | |
55081 | if ((dsta & 1) != 0) { | |
55082 | last_fault_for_exception_3 = dsta; | |
55083 | last_op_for_exception_3 = opcode; | |
55084 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
55085 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
55086 | goto endlabel2959; | |
55087 | } | |
55088 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
55089 | src &= dst; | |
55090 | CLEAR_CZNV; | |
55091 | SET_ZFLG (((int32_t)(src)) == 0); | |
55092 | SET_NFLG (((int32_t)(src)) < 0); | |
55093 | m68k_incpc(6); | |
55094 | fill_prefetch_0 (); | |
55095 | m68k_write_memory_32(dsta,src); | |
55096 | }}}}}endlabel2959: ; | |
55097 | return 28; | |
55098 | } | |
55099 | unsigned long CPUFUNC(op_c1c0_5)(uint32_t opcode) /* MULS */ | |
55100 | { | |
55101 | uint32_t srcreg = (opcode & 7); | |
55102 | uint32_t dstreg = (opcode >> 9) & 7; | |
55103 | unsigned int retcycles = 0; | |
55104 | OpcodeFamily = 63; CurrentInstrCycles = 38; | |
55105 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
55106 | { int16_t dst = m68k_dreg(regs, dstreg); | |
55107 | { uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src; | |
55108 | uint32_t src2; | |
55109 | CLEAR_CZNV; | |
55110 | SET_ZFLG (((int32_t)(newv)) == 0); | |
55111 | SET_NFLG (((int32_t)(newv)) < 0); | |
55112 | m68k_dreg(regs, dstreg) = (newv); | |
55113 | src2 = ((uint32_t)src) << 1; | |
55114 | while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; } | |
55115 | }}}}m68k_incpc(2); | |
55116 | fill_prefetch_2 (); | |
55117 | return (38+retcycles*2); | |
55118 | } | |
55119 | unsigned long CPUFUNC(op_c1d0_5)(uint32_t opcode) /* MULS */ | |
55120 | { | |
55121 | uint32_t srcreg = (opcode & 7); | |
55122 | uint32_t dstreg = (opcode >> 9) & 7; | |
55123 | unsigned int retcycles = 0; | |
55124 | OpcodeFamily = 63; CurrentInstrCycles = 42; | |
55125 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
55126 | if ((srca & 1) != 0) { | |
55127 | last_fault_for_exception_3 = srca; | |
55128 | last_op_for_exception_3 = opcode; | |
55129 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
55130 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
55131 | goto endlabel2961; | |
55132 | } | |
55133 | {{ int16_t src = m68k_read_memory_16(srca); | |
55134 | { int16_t dst = m68k_dreg(regs, dstreg); | |
55135 | { uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src; | |
55136 | uint32_t src2; | |
55137 | CLEAR_CZNV; | |
55138 | SET_ZFLG (((int32_t)(newv)) == 0); | |
55139 | SET_NFLG (((int32_t)(newv)) < 0); | |
55140 | m68k_dreg(regs, dstreg) = (newv); | |
55141 | src2 = ((uint32_t)src) << 1; | |
55142 | while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; } | |
55143 | }}}}}}m68k_incpc(2); | |
55144 | fill_prefetch_2 (); | |
55145 | endlabel2961: ; | |
55146 | return (42+retcycles*2); | |
55147 | } | |
55148 | unsigned long CPUFUNC(op_c1d8_5)(uint32_t opcode) /* MULS */ | |
55149 | { | |
55150 | uint32_t srcreg = (opcode & 7); | |
55151 | uint32_t dstreg = (opcode >> 9) & 7; | |
55152 | unsigned int retcycles = 0; | |
55153 | OpcodeFamily = 63; CurrentInstrCycles = 42; | |
55154 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
55155 | if ((srca & 1) != 0) { | |
55156 | last_fault_for_exception_3 = srca; | |
55157 | last_op_for_exception_3 = opcode; | |
55158 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
55159 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
55160 | goto endlabel2962; | |
55161 | } | |
55162 | {{ int16_t src = m68k_read_memory_16(srca); | |
55163 | m68k_areg(regs, srcreg) += 2; | |
55164 | { int16_t dst = m68k_dreg(regs, dstreg); | |
55165 | { uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src; | |
55166 | uint32_t src2; | |
55167 | CLEAR_CZNV; | |
55168 | SET_ZFLG (((int32_t)(newv)) == 0); | |
55169 | SET_NFLG (((int32_t)(newv)) < 0); | |
55170 | m68k_dreg(regs, dstreg) = (newv); | |
55171 | src2 = ((uint32_t)src) << 1; | |
55172 | while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; } | |
55173 | }}}}}}m68k_incpc(2); | |
55174 | fill_prefetch_2 (); | |
55175 | endlabel2962: ; | |
55176 | return (42+retcycles*2); | |
55177 | } | |
55178 | unsigned long CPUFUNC(op_c1e0_5)(uint32_t opcode) /* MULS */ | |
55179 | { | |
55180 | uint32_t srcreg = (opcode & 7); | |
55181 | uint32_t dstreg = (opcode >> 9) & 7; | |
55182 | unsigned int retcycles = 0; | |
55183 | OpcodeFamily = 63; CurrentInstrCycles = 44; | |
55184 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
55185 | if ((srca & 1) != 0) { | |
55186 | last_fault_for_exception_3 = srca; | |
55187 | last_op_for_exception_3 = opcode; | |
55188 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
55189 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
55190 | goto endlabel2963; | |
55191 | } | |
55192 | {{ int16_t src = m68k_read_memory_16(srca); | |
55193 | m68k_areg (regs, srcreg) = srca; | |
55194 | { int16_t dst = m68k_dreg(regs, dstreg); | |
55195 | { uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src; | |
55196 | uint32_t src2; | |
55197 | CLEAR_CZNV; | |
55198 | SET_ZFLG (((int32_t)(newv)) == 0); | |
55199 | SET_NFLG (((int32_t)(newv)) < 0); | |
55200 | m68k_dreg(regs, dstreg) = (newv); | |
55201 | src2 = ((uint32_t)src) << 1; | |
55202 | while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; } | |
55203 | }}}}}}m68k_incpc(2); | |
55204 | fill_prefetch_2 (); | |
55205 | endlabel2963: ; | |
55206 | return (44+retcycles*2); | |
55207 | } | |
55208 | unsigned long CPUFUNC(op_c1e8_5)(uint32_t opcode) /* MULS */ | |
55209 | { | |
55210 | uint32_t srcreg = (opcode & 7); | |
55211 | uint32_t dstreg = (opcode >> 9) & 7; | |
55212 | unsigned int retcycles = 0; | |
55213 | OpcodeFamily = 63; CurrentInstrCycles = 46; | |
55214 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
55215 | if ((srca & 1) != 0) { | |
55216 | last_fault_for_exception_3 = srca; | |
55217 | last_op_for_exception_3 = opcode; | |
55218 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
55219 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
55220 | goto endlabel2964; | |
55221 | } | |
55222 | {{ int16_t src = m68k_read_memory_16(srca); | |
55223 | { int16_t dst = m68k_dreg(regs, dstreg); | |
55224 | { uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src; | |
55225 | uint32_t src2; | |
55226 | CLEAR_CZNV; | |
55227 | SET_ZFLG (((int32_t)(newv)) == 0); | |
55228 | SET_NFLG (((int32_t)(newv)) < 0); | |
55229 | m68k_dreg(regs, dstreg) = (newv); | |
55230 | src2 = ((uint32_t)src) << 1; | |
55231 | while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; } | |
55232 | }}}}}}m68k_incpc(4); | |
55233 | fill_prefetch_0 (); | |
55234 | endlabel2964: ; | |
55235 | return (46+retcycles*2); | |
55236 | } | |
55237 | unsigned long CPUFUNC(op_c1f0_5)(uint32_t opcode) /* MULS */ | |
55238 | { | |
55239 | uint32_t srcreg = (opcode & 7); | |
55240 | uint32_t dstreg = (opcode >> 9) & 7; | |
55241 | unsigned int retcycles = 0; | |
55242 | OpcodeFamily = 63; CurrentInstrCycles = 48; | |
55243 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
55244 | BusCyclePenalty += 2; | |
55245 | if ((srca & 1) != 0) { | |
55246 | last_fault_for_exception_3 = srca; | |
55247 | last_op_for_exception_3 = opcode; | |
55248 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
55249 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
55250 | goto endlabel2965; | |
55251 | } | |
55252 | {{ int16_t src = m68k_read_memory_16(srca); | |
55253 | { int16_t dst = m68k_dreg(regs, dstreg); | |
55254 | { uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src; | |
55255 | uint32_t src2; | |
55256 | CLEAR_CZNV; | |
55257 | SET_ZFLG (((int32_t)(newv)) == 0); | |
55258 | SET_NFLG (((int32_t)(newv)) < 0); | |
55259 | m68k_dreg(regs, dstreg) = (newv); | |
55260 | src2 = ((uint32_t)src) << 1; | |
55261 | while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; } | |
55262 | }}}}}}m68k_incpc(4); | |
55263 | fill_prefetch_0 (); | |
55264 | endlabel2965: ; | |
55265 | return (48+retcycles*2); | |
55266 | } | |
55267 | unsigned long CPUFUNC(op_c1f8_5)(uint32_t opcode) /* MULS */ | |
55268 | { | |
55269 | uint32_t dstreg = (opcode >> 9) & 7; | |
55270 | unsigned int retcycles = 0; | |
55271 | OpcodeFamily = 63; CurrentInstrCycles = 46; | |
55272 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
55273 | if ((srca & 1) != 0) { | |
55274 | last_fault_for_exception_3 = srca; | |
55275 | last_op_for_exception_3 = opcode; | |
55276 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
55277 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
55278 | goto endlabel2966; | |
55279 | } | |
55280 | {{ int16_t src = m68k_read_memory_16(srca); | |
55281 | { int16_t dst = m68k_dreg(regs, dstreg); | |
55282 | { uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src; | |
55283 | uint32_t src2; | |
55284 | CLEAR_CZNV; | |
55285 | SET_ZFLG (((int32_t)(newv)) == 0); | |
55286 | SET_NFLG (((int32_t)(newv)) < 0); | |
55287 | m68k_dreg(regs, dstreg) = (newv); | |
55288 | src2 = ((uint32_t)src) << 1; | |
55289 | while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; } | |
55290 | }}}}}}m68k_incpc(4); | |
55291 | fill_prefetch_0 (); | |
55292 | endlabel2966: ; | |
55293 | return (46+retcycles*2); | |
55294 | } | |
55295 | unsigned long CPUFUNC(op_c1f9_5)(uint32_t opcode) /* MULS */ | |
55296 | { | |
55297 | uint32_t dstreg = (opcode >> 9) & 7; | |
55298 | unsigned int retcycles = 0; | |
55299 | OpcodeFamily = 63; CurrentInstrCycles = 50; | |
55300 | {{ uint32_t srca = get_ilong_prefetch(2); | |
55301 | if ((srca & 1) != 0) { | |
55302 | last_fault_for_exception_3 = srca; | |
55303 | last_op_for_exception_3 = opcode; | |
55304 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
55305 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
55306 | goto endlabel2967; | |
55307 | } | |
55308 | {{ int16_t src = m68k_read_memory_16(srca); | |
55309 | { int16_t dst = m68k_dreg(regs, dstreg); | |
55310 | { uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src; | |
55311 | uint32_t src2; | |
55312 | CLEAR_CZNV; | |
55313 | SET_ZFLG (((int32_t)(newv)) == 0); | |
55314 | SET_NFLG (((int32_t)(newv)) < 0); | |
55315 | m68k_dreg(regs, dstreg) = (newv); | |
55316 | src2 = ((uint32_t)src) << 1; | |
55317 | while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; } | |
55318 | }}}}}}m68k_incpc(6); | |
55319 | fill_prefetch_0 (); | |
55320 | endlabel2967: ; | |
55321 | return (50+retcycles*2); | |
55322 | } | |
55323 | unsigned long CPUFUNC(op_c1fa_5)(uint32_t opcode) /* MULS */ | |
55324 | { | |
55325 | uint32_t dstreg = (opcode >> 9) & 7; | |
55326 | unsigned int retcycles = 0; | |
55327 | OpcodeFamily = 63; CurrentInstrCycles = 46; | |
55328 | {{ uint32_t srca = m68k_getpc () + 2; | |
55329 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
55330 | if ((srca & 1) != 0) { | |
55331 | last_fault_for_exception_3 = srca; | |
55332 | last_op_for_exception_3 = opcode; | |
55333 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
55334 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
55335 | goto endlabel2968; | |
55336 | } | |
55337 | {{ int16_t src = m68k_read_memory_16(srca); | |
55338 | { int16_t dst = m68k_dreg(regs, dstreg); | |
55339 | { uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src; | |
55340 | uint32_t src2; | |
55341 | CLEAR_CZNV; | |
55342 | SET_ZFLG (((int32_t)(newv)) == 0); | |
55343 | SET_NFLG (((int32_t)(newv)) < 0); | |
55344 | m68k_dreg(regs, dstreg) = (newv); | |
55345 | src2 = ((uint32_t)src) << 1; | |
55346 | while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; } | |
55347 | }}}}}}m68k_incpc(4); | |
55348 | fill_prefetch_0 (); | |
55349 | endlabel2968: ; | |
55350 | return (46+retcycles*2); | |
55351 | } | |
55352 | unsigned long CPUFUNC(op_c1fb_5)(uint32_t opcode) /* MULS */ | |
55353 | { | |
55354 | uint32_t dstreg = (opcode >> 9) & 7; | |
55355 | unsigned int retcycles = 0; | |
55356 | OpcodeFamily = 63; CurrentInstrCycles = 48; | |
55357 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
55358 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
55359 | BusCyclePenalty += 2; | |
55360 | if ((srca & 1) != 0) { | |
55361 | last_fault_for_exception_3 = srca; | |
55362 | last_op_for_exception_3 = opcode; | |
55363 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
55364 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
55365 | goto endlabel2969; | |
55366 | } | |
55367 | {{ int16_t src = m68k_read_memory_16(srca); | |
55368 | { int16_t dst = m68k_dreg(regs, dstreg); | |
55369 | { uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src; | |
55370 | uint32_t src2; | |
55371 | CLEAR_CZNV; | |
55372 | SET_ZFLG (((int32_t)(newv)) == 0); | |
55373 | SET_NFLG (((int32_t)(newv)) < 0); | |
55374 | m68k_dreg(regs, dstreg) = (newv); | |
55375 | src2 = ((uint32_t)src) << 1; | |
55376 | while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; } | |
55377 | }}}}}}m68k_incpc(4); | |
55378 | fill_prefetch_0 (); | |
55379 | endlabel2969: ; | |
55380 | return (48+retcycles*2); | |
55381 | } | |
55382 | unsigned long CPUFUNC(op_c1fc_5)(uint32_t opcode) /* MULS */ | |
55383 | { | |
55384 | uint32_t dstreg = (opcode >> 9) & 7; | |
55385 | unsigned int retcycles = 0; | |
55386 | OpcodeFamily = 63; CurrentInstrCycles = 42; | |
55387 | {{ int16_t src = get_iword_prefetch(2); | |
55388 | { int16_t dst = m68k_dreg(regs, dstreg); | |
55389 | { uint32_t newv = (int32_t)(int16_t)dst * (int32_t)(int16_t)src; | |
55390 | uint32_t src2; | |
55391 | CLEAR_CZNV; | |
55392 | SET_ZFLG (((int32_t)(newv)) == 0); | |
55393 | SET_NFLG (((int32_t)(newv)) < 0); | |
55394 | m68k_dreg(regs, dstreg) = (newv); | |
55395 | src2 = ((uint32_t)src) << 1; | |
55396 | while (src2) { if ( ( (src2 & 3) == 1 ) || ( (src2 & 3) == 2 ) ) retcycles++; src2 >>= 1; } | |
55397 | }}}}m68k_incpc(4); | |
55398 | fill_prefetch_0 (); | |
55399 | return (42+retcycles*2); | |
55400 | } | |
55401 | unsigned long CPUFUNC(op_d000_5)(uint32_t opcode) /* ADD */ | |
55402 | { | |
55403 | uint32_t srcreg = (opcode & 7); | |
55404 | uint32_t dstreg = (opcode >> 9) & 7; | |
55405 | OpcodeFamily = 11; CurrentInstrCycles = 4; | |
55406 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
55407 | { int8_t dst = m68k_dreg(regs, dstreg); | |
55408 | { refill_prefetch (m68k_getpc(), 2); | |
55409 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
55410 | { int flgs = ((int8_t)(src)) < 0; | |
55411 | int flgo = ((int8_t)(dst)) < 0; | |
55412 | int flgn = ((int8_t)(newv)) < 0; | |
55413 | SET_ZFLG (((int8_t)(newv)) == 0); | |
55414 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
55415 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
55416 | COPY_CARRY; | |
55417 | SET_NFLG (flgn != 0); | |
55418 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
55419 | }}}}}}m68k_incpc(2); | |
55420 | fill_prefetch_2 (); | |
55421 | return 4; | |
55422 | } | |
55423 | unsigned long CPUFUNC(op_d010_5)(uint32_t opcode) /* ADD */ | |
55424 | { | |
55425 | uint32_t srcreg = (opcode & 7); | |
55426 | uint32_t dstreg = (opcode >> 9) & 7; | |
55427 | OpcodeFamily = 11; CurrentInstrCycles = 8; | |
55428 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
55429 | { int8_t src = m68k_read_memory_8(srca); | |
55430 | { int8_t dst = m68k_dreg(regs, dstreg); | |
55431 | { refill_prefetch (m68k_getpc(), 2); | |
55432 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
55433 | { int flgs = ((int8_t)(src)) < 0; | |
55434 | int flgo = ((int8_t)(dst)) < 0; | |
55435 | int flgn = ((int8_t)(newv)) < 0; | |
55436 | SET_ZFLG (((int8_t)(newv)) == 0); | |
55437 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
55438 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
55439 | COPY_CARRY; | |
55440 | SET_NFLG (flgn != 0); | |
55441 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
55442 | }}}}}}}m68k_incpc(2); | |
55443 | fill_prefetch_2 (); | |
55444 | return 8; | |
55445 | } | |
55446 | unsigned long CPUFUNC(op_d018_5)(uint32_t opcode) /* ADD */ | |
55447 | { | |
55448 | uint32_t srcreg = (opcode & 7); | |
55449 | uint32_t dstreg = (opcode >> 9) & 7; | |
55450 | OpcodeFamily = 11; CurrentInstrCycles = 8; | |
55451 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
55452 | { int8_t src = m68k_read_memory_8(srca); | |
55453 | m68k_areg(regs, srcreg) += areg_byteinc[srcreg]; | |
55454 | { int8_t dst = m68k_dreg(regs, dstreg); | |
55455 | { refill_prefetch (m68k_getpc(), 2); | |
55456 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
55457 | { int flgs = ((int8_t)(src)) < 0; | |
55458 | int flgo = ((int8_t)(dst)) < 0; | |
55459 | int flgn = ((int8_t)(newv)) < 0; | |
55460 | SET_ZFLG (((int8_t)(newv)) == 0); | |
55461 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
55462 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
55463 | COPY_CARRY; | |
55464 | SET_NFLG (flgn != 0); | |
55465 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
55466 | }}}}}}}m68k_incpc(2); | |
55467 | fill_prefetch_2 (); | |
55468 | return 8; | |
55469 | } | |
55470 | unsigned long CPUFUNC(op_d020_5)(uint32_t opcode) /* ADD */ | |
55471 | { | |
55472 | uint32_t srcreg = (opcode & 7); | |
55473 | uint32_t dstreg = (opcode >> 9) & 7; | |
55474 | OpcodeFamily = 11; CurrentInstrCycles = 10; | |
55475 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
55476 | { int8_t src = m68k_read_memory_8(srca); | |
55477 | m68k_areg (regs, srcreg) = srca; | |
55478 | { int8_t dst = m68k_dreg(regs, dstreg); | |
55479 | { refill_prefetch (m68k_getpc(), 2); | |
55480 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
55481 | { int flgs = ((int8_t)(src)) < 0; | |
55482 | int flgo = ((int8_t)(dst)) < 0; | |
55483 | int flgn = ((int8_t)(newv)) < 0; | |
55484 | SET_ZFLG (((int8_t)(newv)) == 0); | |
55485 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
55486 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
55487 | COPY_CARRY; | |
55488 | SET_NFLG (flgn != 0); | |
55489 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
55490 | }}}}}}}m68k_incpc(2); | |
55491 | fill_prefetch_2 (); | |
55492 | return 10; | |
55493 | } | |
55494 | unsigned long CPUFUNC(op_d028_5)(uint32_t opcode) /* ADD */ | |
55495 | { | |
55496 | uint32_t srcreg = (opcode & 7); | |
55497 | uint32_t dstreg = (opcode >> 9) & 7; | |
55498 | OpcodeFamily = 11; CurrentInstrCycles = 12; | |
55499 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
55500 | { int8_t src = m68k_read_memory_8(srca); | |
55501 | { int8_t dst = m68k_dreg(regs, dstreg); | |
55502 | { refill_prefetch (m68k_getpc(), 2); | |
55503 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
55504 | { int flgs = ((int8_t)(src)) < 0; | |
55505 | int flgo = ((int8_t)(dst)) < 0; | |
55506 | int flgn = ((int8_t)(newv)) < 0; | |
55507 | SET_ZFLG (((int8_t)(newv)) == 0); | |
55508 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
55509 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
55510 | COPY_CARRY; | |
55511 | SET_NFLG (flgn != 0); | |
55512 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
55513 | }}}}}}}m68k_incpc(4); | |
55514 | fill_prefetch_0 (); | |
55515 | return 12; | |
55516 | } | |
55517 | unsigned long CPUFUNC(op_d030_5)(uint32_t opcode) /* ADD */ | |
55518 | { | |
55519 | uint32_t srcreg = (opcode & 7); | |
55520 | uint32_t dstreg = (opcode >> 9) & 7; | |
55521 | OpcodeFamily = 11; CurrentInstrCycles = 14; | |
55522 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
55523 | BusCyclePenalty += 2; | |
55524 | { int8_t src = m68k_read_memory_8(srca); | |
55525 | { int8_t dst = m68k_dreg(regs, dstreg); | |
55526 | { refill_prefetch (m68k_getpc(), 2); | |
55527 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
55528 | { int flgs = ((int8_t)(src)) < 0; | |
55529 | int flgo = ((int8_t)(dst)) < 0; | |
55530 | int flgn = ((int8_t)(newv)) < 0; | |
55531 | SET_ZFLG (((int8_t)(newv)) == 0); | |
55532 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
55533 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
55534 | COPY_CARRY; | |
55535 | SET_NFLG (flgn != 0); | |
55536 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
55537 | }}}}}}}m68k_incpc(4); | |
55538 | fill_prefetch_0 (); | |
55539 | return 14; | |
55540 | } | |
55541 | unsigned long CPUFUNC(op_d038_5)(uint32_t opcode) /* ADD */ | |
55542 | { | |
55543 | uint32_t dstreg = (opcode >> 9) & 7; | |
55544 | OpcodeFamily = 11; CurrentInstrCycles = 12; | |
55545 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
55546 | { int8_t src = m68k_read_memory_8(srca); | |
55547 | { int8_t dst = m68k_dreg(regs, dstreg); | |
55548 | { refill_prefetch (m68k_getpc(), 2); | |
55549 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
55550 | { int flgs = ((int8_t)(src)) < 0; | |
55551 | int flgo = ((int8_t)(dst)) < 0; | |
55552 | int flgn = ((int8_t)(newv)) < 0; | |
55553 | SET_ZFLG (((int8_t)(newv)) == 0); | |
55554 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
55555 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
55556 | COPY_CARRY; | |
55557 | SET_NFLG (flgn != 0); | |
55558 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
55559 | }}}}}}}m68k_incpc(4); | |
55560 | fill_prefetch_0 (); | |
55561 | return 12; | |
55562 | } | |
55563 | unsigned long CPUFUNC(op_d039_5)(uint32_t opcode) /* ADD */ | |
55564 | { | |
55565 | uint32_t dstreg = (opcode >> 9) & 7; | |
55566 | OpcodeFamily = 11; CurrentInstrCycles = 16; | |
55567 | {{ uint32_t srca = get_ilong_prefetch(2); | |
55568 | { int8_t src = m68k_read_memory_8(srca); | |
55569 | { int8_t dst = m68k_dreg(regs, dstreg); | |
55570 | { refill_prefetch (m68k_getpc(), 2); | |
55571 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
55572 | { int flgs = ((int8_t)(src)) < 0; | |
55573 | int flgo = ((int8_t)(dst)) < 0; | |
55574 | int flgn = ((int8_t)(newv)) < 0; | |
55575 | SET_ZFLG (((int8_t)(newv)) == 0); | |
55576 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
55577 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
55578 | COPY_CARRY; | |
55579 | SET_NFLG (flgn != 0); | |
55580 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
55581 | }}}}}}}m68k_incpc(6); | |
55582 | fill_prefetch_0 (); | |
55583 | return 16; | |
55584 | } | |
55585 | unsigned long CPUFUNC(op_d03a_5)(uint32_t opcode) /* ADD */ | |
55586 | { | |
55587 | uint32_t dstreg = (opcode >> 9) & 7; | |
55588 | OpcodeFamily = 11; CurrentInstrCycles = 12; | |
55589 | {{ uint32_t srca = m68k_getpc () + 2; | |
55590 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
55591 | { int8_t src = m68k_read_memory_8(srca); | |
55592 | { int8_t dst = m68k_dreg(regs, dstreg); | |
55593 | { refill_prefetch (m68k_getpc(), 2); | |
55594 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
55595 | { int flgs = ((int8_t)(src)) < 0; | |
55596 | int flgo = ((int8_t)(dst)) < 0; | |
55597 | int flgn = ((int8_t)(newv)) < 0; | |
55598 | SET_ZFLG (((int8_t)(newv)) == 0); | |
55599 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
55600 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
55601 | COPY_CARRY; | |
55602 | SET_NFLG (flgn != 0); | |
55603 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
55604 | }}}}}}}m68k_incpc(4); | |
55605 | fill_prefetch_0 (); | |
55606 | return 12; | |
55607 | } | |
55608 | unsigned long CPUFUNC(op_d03b_5)(uint32_t opcode) /* ADD */ | |
55609 | { | |
55610 | uint32_t dstreg = (opcode >> 9) & 7; | |
55611 | OpcodeFamily = 11; CurrentInstrCycles = 14; | |
55612 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
55613 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
55614 | BusCyclePenalty += 2; | |
55615 | { int8_t src = m68k_read_memory_8(srca); | |
55616 | { int8_t dst = m68k_dreg(regs, dstreg); | |
55617 | { refill_prefetch (m68k_getpc(), 2); | |
55618 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
55619 | { int flgs = ((int8_t)(src)) < 0; | |
55620 | int flgo = ((int8_t)(dst)) < 0; | |
55621 | int flgn = ((int8_t)(newv)) < 0; | |
55622 | SET_ZFLG (((int8_t)(newv)) == 0); | |
55623 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
55624 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
55625 | COPY_CARRY; | |
55626 | SET_NFLG (flgn != 0); | |
55627 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
55628 | }}}}}}}m68k_incpc(4); | |
55629 | fill_prefetch_0 (); | |
55630 | return 14; | |
55631 | } | |
55632 | unsigned long CPUFUNC(op_d03c_5)(uint32_t opcode) /* ADD */ | |
55633 | { | |
55634 | uint32_t dstreg = (opcode >> 9) & 7; | |
55635 | OpcodeFamily = 11; CurrentInstrCycles = 8; | |
55636 | {{ int8_t src = get_ibyte_prefetch(2); | |
55637 | { int8_t dst = m68k_dreg(regs, dstreg); | |
55638 | { refill_prefetch (m68k_getpc(), 2); | |
55639 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
55640 | { int flgs = ((int8_t)(src)) < 0; | |
55641 | int flgo = ((int8_t)(dst)) < 0; | |
55642 | int flgn = ((int8_t)(newv)) < 0; | |
55643 | SET_ZFLG (((int8_t)(newv)) == 0); | |
55644 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
55645 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
55646 | COPY_CARRY; | |
55647 | SET_NFLG (flgn != 0); | |
55648 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
55649 | }}}}}}m68k_incpc(4); | |
55650 | fill_prefetch_0 (); | |
55651 | return 8; | |
55652 | } | |
55653 | unsigned long CPUFUNC(op_d040_5)(uint32_t opcode) /* ADD */ | |
55654 | { | |
55655 | uint32_t srcreg = (opcode & 7); | |
55656 | uint32_t dstreg = (opcode >> 9) & 7; | |
55657 | OpcodeFamily = 11; CurrentInstrCycles = 4; | |
55658 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
55659 | { int16_t dst = m68k_dreg(regs, dstreg); | |
55660 | { refill_prefetch (m68k_getpc(), 2); | |
55661 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
55662 | { int flgs = ((int16_t)(src)) < 0; | |
55663 | int flgo = ((int16_t)(dst)) < 0; | |
55664 | int flgn = ((int16_t)(newv)) < 0; | |
55665 | SET_ZFLG (((int16_t)(newv)) == 0); | |
55666 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
55667 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
55668 | COPY_CARRY; | |
55669 | SET_NFLG (flgn != 0); | |
55670 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
55671 | }}}}}}m68k_incpc(2); | |
55672 | fill_prefetch_2 (); | |
55673 | return 4; | |
55674 | } | |
55675 | unsigned long CPUFUNC(op_d048_5)(uint32_t opcode) /* ADD */ | |
55676 | { | |
55677 | uint32_t srcreg = (opcode & 7); | |
55678 | uint32_t dstreg = (opcode >> 9) & 7; | |
55679 | OpcodeFamily = 11; CurrentInstrCycles = 4; | |
55680 | {{ int16_t src = m68k_areg(regs, srcreg); | |
55681 | { int16_t dst = m68k_dreg(regs, dstreg); | |
55682 | { refill_prefetch (m68k_getpc(), 2); | |
55683 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
55684 | { int flgs = ((int16_t)(src)) < 0; | |
55685 | int flgo = ((int16_t)(dst)) < 0; | |
55686 | int flgn = ((int16_t)(newv)) < 0; | |
55687 | SET_ZFLG (((int16_t)(newv)) == 0); | |
55688 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
55689 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
55690 | COPY_CARRY; | |
55691 | SET_NFLG (flgn != 0); | |
55692 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
55693 | }}}}}}m68k_incpc(2); | |
55694 | fill_prefetch_2 (); | |
55695 | return 4; | |
55696 | } | |
55697 | unsigned long CPUFUNC(op_d050_5)(uint32_t opcode) /* ADD */ | |
55698 | { | |
55699 | uint32_t srcreg = (opcode & 7); | |
55700 | uint32_t dstreg = (opcode >> 9) & 7; | |
55701 | OpcodeFamily = 11; CurrentInstrCycles = 8; | |
55702 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
55703 | if ((srca & 1) != 0) { | |
55704 | last_fault_for_exception_3 = srca; | |
55705 | last_op_for_exception_3 = opcode; | |
55706 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
55707 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
55708 | goto endlabel2984; | |
55709 | } | |
55710 | {{ int16_t src = m68k_read_memory_16(srca); | |
55711 | { int16_t dst = m68k_dreg(regs, dstreg); | |
55712 | { refill_prefetch (m68k_getpc(), 2); | |
55713 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
55714 | { int flgs = ((int16_t)(src)) < 0; | |
55715 | int flgo = ((int16_t)(dst)) < 0; | |
55716 | int flgn = ((int16_t)(newv)) < 0; | |
55717 | SET_ZFLG (((int16_t)(newv)) == 0); | |
55718 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
55719 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
55720 | COPY_CARRY; | |
55721 | SET_NFLG (flgn != 0); | |
55722 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
55723 | }}}}}}}}m68k_incpc(2); | |
55724 | fill_prefetch_2 (); | |
55725 | endlabel2984: ; | |
55726 | return 8; | |
55727 | } | |
55728 | unsigned long CPUFUNC(op_d058_5)(uint32_t opcode) /* ADD */ | |
55729 | { | |
55730 | uint32_t srcreg = (opcode & 7); | |
55731 | uint32_t dstreg = (opcode >> 9) & 7; | |
55732 | OpcodeFamily = 11; CurrentInstrCycles = 8; | |
55733 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
55734 | if ((srca & 1) != 0) { | |
55735 | last_fault_for_exception_3 = srca; | |
55736 | last_op_for_exception_3 = opcode; | |
55737 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
55738 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
55739 | goto endlabel2985; | |
55740 | } | |
55741 | {{ int16_t src = m68k_read_memory_16(srca); | |
55742 | m68k_areg(regs, srcreg) += 2; | |
55743 | { int16_t dst = m68k_dreg(regs, dstreg); | |
55744 | { refill_prefetch (m68k_getpc(), 2); | |
55745 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
55746 | { int flgs = ((int16_t)(src)) < 0; | |
55747 | int flgo = ((int16_t)(dst)) < 0; | |
55748 | int flgn = ((int16_t)(newv)) < 0; | |
55749 | SET_ZFLG (((int16_t)(newv)) == 0); | |
55750 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
55751 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
55752 | COPY_CARRY; | |
55753 | SET_NFLG (flgn != 0); | |
55754 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
55755 | }}}}}}}}m68k_incpc(2); | |
55756 | fill_prefetch_2 (); | |
55757 | endlabel2985: ; | |
55758 | return 8; | |
55759 | } | |
55760 | unsigned long CPUFUNC(op_d060_5)(uint32_t opcode) /* ADD */ | |
55761 | { | |
55762 | uint32_t srcreg = (opcode & 7); | |
55763 | uint32_t dstreg = (opcode >> 9) & 7; | |
55764 | OpcodeFamily = 11; CurrentInstrCycles = 10; | |
55765 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
55766 | if ((srca & 1) != 0) { | |
55767 | last_fault_for_exception_3 = srca; | |
55768 | last_op_for_exception_3 = opcode; | |
55769 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
55770 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
55771 | goto endlabel2986; | |
55772 | } | |
55773 | {{ int16_t src = m68k_read_memory_16(srca); | |
55774 | m68k_areg (regs, srcreg) = srca; | |
55775 | { int16_t dst = m68k_dreg(regs, dstreg); | |
55776 | { refill_prefetch (m68k_getpc(), 2); | |
55777 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
55778 | { int flgs = ((int16_t)(src)) < 0; | |
55779 | int flgo = ((int16_t)(dst)) < 0; | |
55780 | int flgn = ((int16_t)(newv)) < 0; | |
55781 | SET_ZFLG (((int16_t)(newv)) == 0); | |
55782 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
55783 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
55784 | COPY_CARRY; | |
55785 | SET_NFLG (flgn != 0); | |
55786 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
55787 | }}}}}}}}m68k_incpc(2); | |
55788 | fill_prefetch_2 (); | |
55789 | endlabel2986: ; | |
55790 | return 10; | |
55791 | } | |
55792 | unsigned long CPUFUNC(op_d068_5)(uint32_t opcode) /* ADD */ | |
55793 | { | |
55794 | uint32_t srcreg = (opcode & 7); | |
55795 | uint32_t dstreg = (opcode >> 9) & 7; | |
55796 | OpcodeFamily = 11; CurrentInstrCycles = 12; | |
55797 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
55798 | if ((srca & 1) != 0) { | |
55799 | last_fault_for_exception_3 = srca; | |
55800 | last_op_for_exception_3 = opcode; | |
55801 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
55802 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
55803 | goto endlabel2987; | |
55804 | } | |
55805 | {{ int16_t src = m68k_read_memory_16(srca); | |
55806 | { int16_t dst = m68k_dreg(regs, dstreg); | |
55807 | { refill_prefetch (m68k_getpc(), 2); | |
55808 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
55809 | { int flgs = ((int16_t)(src)) < 0; | |
55810 | int flgo = ((int16_t)(dst)) < 0; | |
55811 | int flgn = ((int16_t)(newv)) < 0; | |
55812 | SET_ZFLG (((int16_t)(newv)) == 0); | |
55813 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
55814 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
55815 | COPY_CARRY; | |
55816 | SET_NFLG (flgn != 0); | |
55817 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
55818 | }}}}}}}}m68k_incpc(4); | |
55819 | fill_prefetch_0 (); | |
55820 | endlabel2987: ; | |
55821 | return 12; | |
55822 | } | |
55823 | unsigned long CPUFUNC(op_d070_5)(uint32_t opcode) /* ADD */ | |
55824 | { | |
55825 | uint32_t srcreg = (opcode & 7); | |
55826 | uint32_t dstreg = (opcode >> 9) & 7; | |
55827 | OpcodeFamily = 11; CurrentInstrCycles = 14; | |
55828 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
55829 | BusCyclePenalty += 2; | |
55830 | if ((srca & 1) != 0) { | |
55831 | last_fault_for_exception_3 = srca; | |
55832 | last_op_for_exception_3 = opcode; | |
55833 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
55834 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
55835 | goto endlabel2988; | |
55836 | } | |
55837 | {{ int16_t src = m68k_read_memory_16(srca); | |
55838 | { int16_t dst = m68k_dreg(regs, dstreg); | |
55839 | { refill_prefetch (m68k_getpc(), 2); | |
55840 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
55841 | { int flgs = ((int16_t)(src)) < 0; | |
55842 | int flgo = ((int16_t)(dst)) < 0; | |
55843 | int flgn = ((int16_t)(newv)) < 0; | |
55844 | SET_ZFLG (((int16_t)(newv)) == 0); | |
55845 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
55846 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
55847 | COPY_CARRY; | |
55848 | SET_NFLG (flgn != 0); | |
55849 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
55850 | }}}}}}}}m68k_incpc(4); | |
55851 | fill_prefetch_0 (); | |
55852 | endlabel2988: ; | |
55853 | return 14; | |
55854 | } | |
55855 | unsigned long CPUFUNC(op_d078_5)(uint32_t opcode) /* ADD */ | |
55856 | { | |
55857 | uint32_t dstreg = (opcode >> 9) & 7; | |
55858 | OpcodeFamily = 11; CurrentInstrCycles = 12; | |
55859 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
55860 | if ((srca & 1) != 0) { | |
55861 | last_fault_for_exception_3 = srca; | |
55862 | last_op_for_exception_3 = opcode; | |
55863 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
55864 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
55865 | goto endlabel2989; | |
55866 | } | |
55867 | {{ int16_t src = m68k_read_memory_16(srca); | |
55868 | { int16_t dst = m68k_dreg(regs, dstreg); | |
55869 | { refill_prefetch (m68k_getpc(), 2); | |
55870 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
55871 | { int flgs = ((int16_t)(src)) < 0; | |
55872 | int flgo = ((int16_t)(dst)) < 0; | |
55873 | int flgn = ((int16_t)(newv)) < 0; | |
55874 | SET_ZFLG (((int16_t)(newv)) == 0); | |
55875 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
55876 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
55877 | COPY_CARRY; | |
55878 | SET_NFLG (flgn != 0); | |
55879 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
55880 | }}}}}}}}m68k_incpc(4); | |
55881 | fill_prefetch_0 (); | |
55882 | endlabel2989: ; | |
55883 | return 12; | |
55884 | } | |
55885 | unsigned long CPUFUNC(op_d079_5)(uint32_t opcode) /* ADD */ | |
55886 | { | |
55887 | uint32_t dstreg = (opcode >> 9) & 7; | |
55888 | OpcodeFamily = 11; CurrentInstrCycles = 16; | |
55889 | {{ uint32_t srca = get_ilong_prefetch(2); | |
55890 | if ((srca & 1) != 0) { | |
55891 | last_fault_for_exception_3 = srca; | |
55892 | last_op_for_exception_3 = opcode; | |
55893 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
55894 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
55895 | goto endlabel2990; | |
55896 | } | |
55897 | {{ int16_t src = m68k_read_memory_16(srca); | |
55898 | { int16_t dst = m68k_dreg(regs, dstreg); | |
55899 | { refill_prefetch (m68k_getpc(), 2); | |
55900 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
55901 | { int flgs = ((int16_t)(src)) < 0; | |
55902 | int flgo = ((int16_t)(dst)) < 0; | |
55903 | int flgn = ((int16_t)(newv)) < 0; | |
55904 | SET_ZFLG (((int16_t)(newv)) == 0); | |
55905 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
55906 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
55907 | COPY_CARRY; | |
55908 | SET_NFLG (flgn != 0); | |
55909 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
55910 | }}}}}}}}m68k_incpc(6); | |
55911 | fill_prefetch_0 (); | |
55912 | endlabel2990: ; | |
55913 | return 16; | |
55914 | } | |
55915 | unsigned long CPUFUNC(op_d07a_5)(uint32_t opcode) /* ADD */ | |
55916 | { | |
55917 | uint32_t dstreg = (opcode >> 9) & 7; | |
55918 | OpcodeFamily = 11; CurrentInstrCycles = 12; | |
55919 | {{ uint32_t srca = m68k_getpc () + 2; | |
55920 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
55921 | if ((srca & 1) != 0) { | |
55922 | last_fault_for_exception_3 = srca; | |
55923 | last_op_for_exception_3 = opcode; | |
55924 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
55925 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
55926 | goto endlabel2991; | |
55927 | } | |
55928 | {{ int16_t src = m68k_read_memory_16(srca); | |
55929 | { int16_t dst = m68k_dreg(regs, dstreg); | |
55930 | { refill_prefetch (m68k_getpc(), 2); | |
55931 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
55932 | { int flgs = ((int16_t)(src)) < 0; | |
55933 | int flgo = ((int16_t)(dst)) < 0; | |
55934 | int flgn = ((int16_t)(newv)) < 0; | |
55935 | SET_ZFLG (((int16_t)(newv)) == 0); | |
55936 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
55937 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
55938 | COPY_CARRY; | |
55939 | SET_NFLG (flgn != 0); | |
55940 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
55941 | }}}}}}}}m68k_incpc(4); | |
55942 | fill_prefetch_0 (); | |
55943 | endlabel2991: ; | |
55944 | return 12; | |
55945 | } | |
55946 | unsigned long CPUFUNC(op_d07b_5)(uint32_t opcode) /* ADD */ | |
55947 | { | |
55948 | uint32_t dstreg = (opcode >> 9) & 7; | |
55949 | OpcodeFamily = 11; CurrentInstrCycles = 14; | |
55950 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
55951 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
55952 | BusCyclePenalty += 2; | |
55953 | if ((srca & 1) != 0) { | |
55954 | last_fault_for_exception_3 = srca; | |
55955 | last_op_for_exception_3 = opcode; | |
55956 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
55957 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
55958 | goto endlabel2992; | |
55959 | } | |
55960 | {{ int16_t src = m68k_read_memory_16(srca); | |
55961 | { int16_t dst = m68k_dreg(regs, dstreg); | |
55962 | { refill_prefetch (m68k_getpc(), 2); | |
55963 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
55964 | { int flgs = ((int16_t)(src)) < 0; | |
55965 | int flgo = ((int16_t)(dst)) < 0; | |
55966 | int flgn = ((int16_t)(newv)) < 0; | |
55967 | SET_ZFLG (((int16_t)(newv)) == 0); | |
55968 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
55969 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
55970 | COPY_CARRY; | |
55971 | SET_NFLG (flgn != 0); | |
55972 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
55973 | }}}}}}}}m68k_incpc(4); | |
55974 | fill_prefetch_0 (); | |
55975 | endlabel2992: ; | |
55976 | return 14; | |
55977 | } | |
55978 | unsigned long CPUFUNC(op_d07c_5)(uint32_t opcode) /* ADD */ | |
55979 | { | |
55980 | uint32_t dstreg = (opcode >> 9) & 7; | |
55981 | OpcodeFamily = 11; CurrentInstrCycles = 8; | |
55982 | {{ int16_t src = get_iword_prefetch(2); | |
55983 | { int16_t dst = m68k_dreg(regs, dstreg); | |
55984 | { refill_prefetch (m68k_getpc(), 2); | |
55985 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
55986 | { int flgs = ((int16_t)(src)) < 0; | |
55987 | int flgo = ((int16_t)(dst)) < 0; | |
55988 | int flgn = ((int16_t)(newv)) < 0; | |
55989 | SET_ZFLG (((int16_t)(newv)) == 0); | |
55990 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
55991 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
55992 | COPY_CARRY; | |
55993 | SET_NFLG (flgn != 0); | |
55994 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
55995 | }}}}}}m68k_incpc(4); | |
55996 | fill_prefetch_0 (); | |
55997 | return 8; | |
55998 | } | |
55999 | unsigned long CPUFUNC(op_d080_5)(uint32_t opcode) /* ADD */ | |
56000 | { | |
56001 | uint32_t srcreg = (opcode & 7); | |
56002 | uint32_t dstreg = (opcode >> 9) & 7; | |
56003 | OpcodeFamily = 11; CurrentInstrCycles = 8; | |
56004 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
56005 | { int32_t dst = m68k_dreg(regs, dstreg); | |
56006 | { refill_prefetch (m68k_getpc(), 2); | |
56007 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
56008 | { int flgs = ((int32_t)(src)) < 0; | |
56009 | int flgo = ((int32_t)(dst)) < 0; | |
56010 | int flgn = ((int32_t)(newv)) < 0; | |
56011 | SET_ZFLG (((int32_t)(newv)) == 0); | |
56012 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
56013 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
56014 | COPY_CARRY; | |
56015 | SET_NFLG (flgn != 0); | |
56016 | m68k_dreg(regs, dstreg) = (newv); | |
56017 | }}}}}}m68k_incpc(2); | |
56018 | fill_prefetch_2 (); | |
56019 | return 8; | |
56020 | } | |
56021 | unsigned long CPUFUNC(op_d088_5)(uint32_t opcode) /* ADD */ | |
56022 | { | |
56023 | uint32_t srcreg = (opcode & 7); | |
56024 | uint32_t dstreg = (opcode >> 9) & 7; | |
56025 | OpcodeFamily = 11; CurrentInstrCycles = 8; | |
56026 | {{ int32_t src = m68k_areg(regs, srcreg); | |
56027 | { int32_t dst = m68k_dreg(regs, dstreg); | |
56028 | { refill_prefetch (m68k_getpc(), 2); | |
56029 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
56030 | { int flgs = ((int32_t)(src)) < 0; | |
56031 | int flgo = ((int32_t)(dst)) < 0; | |
56032 | int flgn = ((int32_t)(newv)) < 0; | |
56033 | SET_ZFLG (((int32_t)(newv)) == 0); | |
56034 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
56035 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
56036 | COPY_CARRY; | |
56037 | SET_NFLG (flgn != 0); | |
56038 | m68k_dreg(regs, dstreg) = (newv); | |
56039 | }}}}}}m68k_incpc(2); | |
56040 | fill_prefetch_2 (); | |
56041 | return 8; | |
56042 | } | |
56043 | unsigned long CPUFUNC(op_d090_5)(uint32_t opcode) /* ADD */ | |
56044 | { | |
56045 | uint32_t srcreg = (opcode & 7); | |
56046 | uint32_t dstreg = (opcode >> 9) & 7; | |
56047 | OpcodeFamily = 11; CurrentInstrCycles = 14; | |
56048 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
56049 | if ((srca & 1) != 0) { | |
56050 | last_fault_for_exception_3 = srca; | |
56051 | last_op_for_exception_3 = opcode; | |
56052 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
56053 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
56054 | goto endlabel2996; | |
56055 | } | |
56056 | {{ int32_t src = m68k_read_memory_32(srca); | |
56057 | { int32_t dst = m68k_dreg(regs, dstreg); | |
56058 | { refill_prefetch (m68k_getpc(), 2); | |
56059 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
56060 | { int flgs = ((int32_t)(src)) < 0; | |
56061 | int flgo = ((int32_t)(dst)) < 0; | |
56062 | int flgn = ((int32_t)(newv)) < 0; | |
56063 | SET_ZFLG (((int32_t)(newv)) == 0); | |
56064 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
56065 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
56066 | COPY_CARRY; | |
56067 | SET_NFLG (flgn != 0); | |
56068 | m68k_dreg(regs, dstreg) = (newv); | |
56069 | }}}}}}}}m68k_incpc(2); | |
56070 | fill_prefetch_2 (); | |
56071 | endlabel2996: ; | |
56072 | return 14; | |
56073 | } | |
56074 | unsigned long CPUFUNC(op_d098_5)(uint32_t opcode) /* ADD */ | |
56075 | { | |
56076 | uint32_t srcreg = (opcode & 7); | |
56077 | uint32_t dstreg = (opcode >> 9) & 7; | |
56078 | OpcodeFamily = 11; CurrentInstrCycles = 14; | |
56079 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
56080 | if ((srca & 1) != 0) { | |
56081 | last_fault_for_exception_3 = srca; | |
56082 | last_op_for_exception_3 = opcode; | |
56083 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
56084 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
56085 | goto endlabel2997; | |
56086 | } | |
56087 | {{ int32_t src = m68k_read_memory_32(srca); | |
56088 | m68k_areg(regs, srcreg) += 4; | |
56089 | { int32_t dst = m68k_dreg(regs, dstreg); | |
56090 | { refill_prefetch (m68k_getpc(), 2); | |
56091 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
56092 | { int flgs = ((int32_t)(src)) < 0; | |
56093 | int flgo = ((int32_t)(dst)) < 0; | |
56094 | int flgn = ((int32_t)(newv)) < 0; | |
56095 | SET_ZFLG (((int32_t)(newv)) == 0); | |
56096 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
56097 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
56098 | COPY_CARRY; | |
56099 | SET_NFLG (flgn != 0); | |
56100 | m68k_dreg(regs, dstreg) = (newv); | |
56101 | }}}}}}}}m68k_incpc(2); | |
56102 | fill_prefetch_2 (); | |
56103 | endlabel2997: ; | |
56104 | return 14; | |
56105 | } | |
56106 | unsigned long CPUFUNC(op_d0a0_5)(uint32_t opcode) /* ADD */ | |
56107 | { | |
56108 | uint32_t srcreg = (opcode & 7); | |
56109 | uint32_t dstreg = (opcode >> 9) & 7; | |
56110 | OpcodeFamily = 11; CurrentInstrCycles = 16; | |
56111 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 4; | |
56112 | if ((srca & 1) != 0) { | |
56113 | last_fault_for_exception_3 = srca; | |
56114 | last_op_for_exception_3 = opcode; | |
56115 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
56116 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
56117 | goto endlabel2998; | |
56118 | } | |
56119 | {{ int32_t src = m68k_read_memory_32(srca); | |
56120 | m68k_areg (regs, srcreg) = srca; | |
56121 | { int32_t dst = m68k_dreg(regs, dstreg); | |
56122 | { refill_prefetch (m68k_getpc(), 2); | |
56123 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
56124 | { int flgs = ((int32_t)(src)) < 0; | |
56125 | int flgo = ((int32_t)(dst)) < 0; | |
56126 | int flgn = ((int32_t)(newv)) < 0; | |
56127 | SET_ZFLG (((int32_t)(newv)) == 0); | |
56128 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
56129 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
56130 | COPY_CARRY; | |
56131 | SET_NFLG (flgn != 0); | |
56132 | m68k_dreg(regs, dstreg) = (newv); | |
56133 | }}}}}}}}m68k_incpc(2); | |
56134 | fill_prefetch_2 (); | |
56135 | endlabel2998: ; | |
56136 | return 16; | |
56137 | } | |
56138 | unsigned long CPUFUNC(op_d0a8_5)(uint32_t opcode) /* ADD */ | |
56139 | { | |
56140 | uint32_t srcreg = (opcode & 7); | |
56141 | uint32_t dstreg = (opcode >> 9) & 7; | |
56142 | OpcodeFamily = 11; CurrentInstrCycles = 18; | |
56143 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
56144 | if ((srca & 1) != 0) { | |
56145 | last_fault_for_exception_3 = srca; | |
56146 | last_op_for_exception_3 = opcode; | |
56147 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
56148 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
56149 | goto endlabel2999; | |
56150 | } | |
56151 | {{ int32_t src = m68k_read_memory_32(srca); | |
56152 | { int32_t dst = m68k_dreg(regs, dstreg); | |
56153 | { refill_prefetch (m68k_getpc(), 2); | |
56154 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
56155 | { int flgs = ((int32_t)(src)) < 0; | |
56156 | int flgo = ((int32_t)(dst)) < 0; | |
56157 | int flgn = ((int32_t)(newv)) < 0; | |
56158 | SET_ZFLG (((int32_t)(newv)) == 0); | |
56159 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
56160 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
56161 | COPY_CARRY; | |
56162 | SET_NFLG (flgn != 0); | |
56163 | m68k_dreg(regs, dstreg) = (newv); | |
56164 | }}}}}}}}m68k_incpc(4); | |
56165 | fill_prefetch_0 (); | |
56166 | endlabel2999: ; | |
56167 | return 18; | |
56168 | } | |
56169 | unsigned long CPUFUNC(op_d0b0_5)(uint32_t opcode) /* ADD */ | |
56170 | { | |
56171 | uint32_t srcreg = (opcode & 7); | |
56172 | uint32_t dstreg = (opcode >> 9) & 7; | |
56173 | OpcodeFamily = 11; CurrentInstrCycles = 20; | |
56174 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
56175 | BusCyclePenalty += 2; | |
56176 | if ((srca & 1) != 0) { | |
56177 | last_fault_for_exception_3 = srca; | |
56178 | last_op_for_exception_3 = opcode; | |
56179 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
56180 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
56181 | goto endlabel3000; | |
56182 | } | |
56183 | {{ int32_t src = m68k_read_memory_32(srca); | |
56184 | { int32_t dst = m68k_dreg(regs, dstreg); | |
56185 | { refill_prefetch (m68k_getpc(), 2); | |
56186 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
56187 | { int flgs = ((int32_t)(src)) < 0; | |
56188 | int flgo = ((int32_t)(dst)) < 0; | |
56189 | int flgn = ((int32_t)(newv)) < 0; | |
56190 | SET_ZFLG (((int32_t)(newv)) == 0); | |
56191 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
56192 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
56193 | COPY_CARRY; | |
56194 | SET_NFLG (flgn != 0); | |
56195 | m68k_dreg(regs, dstreg) = (newv); | |
56196 | }}}}}}}}m68k_incpc(4); | |
56197 | fill_prefetch_0 (); | |
56198 | endlabel3000: ; | |
56199 | return 20; | |
56200 | } | |
56201 | unsigned long CPUFUNC(op_d0b8_5)(uint32_t opcode) /* ADD */ | |
56202 | { | |
56203 | uint32_t dstreg = (opcode >> 9) & 7; | |
56204 | OpcodeFamily = 11; CurrentInstrCycles = 18; | |
56205 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
56206 | if ((srca & 1) != 0) { | |
56207 | last_fault_for_exception_3 = srca; | |
56208 | last_op_for_exception_3 = opcode; | |
56209 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
56210 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
56211 | goto endlabel3001; | |
56212 | } | |
56213 | {{ int32_t src = m68k_read_memory_32(srca); | |
56214 | { int32_t dst = m68k_dreg(regs, dstreg); | |
56215 | { refill_prefetch (m68k_getpc(), 2); | |
56216 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
56217 | { int flgs = ((int32_t)(src)) < 0; | |
56218 | int flgo = ((int32_t)(dst)) < 0; | |
56219 | int flgn = ((int32_t)(newv)) < 0; | |
56220 | SET_ZFLG (((int32_t)(newv)) == 0); | |
56221 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
56222 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
56223 | COPY_CARRY; | |
56224 | SET_NFLG (flgn != 0); | |
56225 | m68k_dreg(regs, dstreg) = (newv); | |
56226 | }}}}}}}}m68k_incpc(4); | |
56227 | fill_prefetch_0 (); | |
56228 | endlabel3001: ; | |
56229 | return 18; | |
56230 | } | |
56231 | unsigned long CPUFUNC(op_d0b9_5)(uint32_t opcode) /* ADD */ | |
56232 | { | |
56233 | uint32_t dstreg = (opcode >> 9) & 7; | |
56234 | OpcodeFamily = 11; CurrentInstrCycles = 22; | |
56235 | {{ uint32_t srca = get_ilong_prefetch(2); | |
56236 | if ((srca & 1) != 0) { | |
56237 | last_fault_for_exception_3 = srca; | |
56238 | last_op_for_exception_3 = opcode; | |
56239 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
56240 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
56241 | goto endlabel3002; | |
56242 | } | |
56243 | {{ int32_t src = m68k_read_memory_32(srca); | |
56244 | { int32_t dst = m68k_dreg(regs, dstreg); | |
56245 | { refill_prefetch (m68k_getpc(), 2); | |
56246 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
56247 | { int flgs = ((int32_t)(src)) < 0; | |
56248 | int flgo = ((int32_t)(dst)) < 0; | |
56249 | int flgn = ((int32_t)(newv)) < 0; | |
56250 | SET_ZFLG (((int32_t)(newv)) == 0); | |
56251 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
56252 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
56253 | COPY_CARRY; | |
56254 | SET_NFLG (flgn != 0); | |
56255 | m68k_dreg(regs, dstreg) = (newv); | |
56256 | }}}}}}}}m68k_incpc(6); | |
56257 | fill_prefetch_0 (); | |
56258 | endlabel3002: ; | |
56259 | return 22; | |
56260 | } | |
56261 | unsigned long CPUFUNC(op_d0ba_5)(uint32_t opcode) /* ADD */ | |
56262 | { | |
56263 | uint32_t dstreg = (opcode >> 9) & 7; | |
56264 | OpcodeFamily = 11; CurrentInstrCycles = 18; | |
56265 | {{ uint32_t srca = m68k_getpc () + 2; | |
56266 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
56267 | if ((srca & 1) != 0) { | |
56268 | last_fault_for_exception_3 = srca; | |
56269 | last_op_for_exception_3 = opcode; | |
56270 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
56271 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
56272 | goto endlabel3003; | |
56273 | } | |
56274 | {{ int32_t src = m68k_read_memory_32(srca); | |
56275 | { int32_t dst = m68k_dreg(regs, dstreg); | |
56276 | { refill_prefetch (m68k_getpc(), 2); | |
56277 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
56278 | { int flgs = ((int32_t)(src)) < 0; | |
56279 | int flgo = ((int32_t)(dst)) < 0; | |
56280 | int flgn = ((int32_t)(newv)) < 0; | |
56281 | SET_ZFLG (((int32_t)(newv)) == 0); | |
56282 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
56283 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
56284 | COPY_CARRY; | |
56285 | SET_NFLG (flgn != 0); | |
56286 | m68k_dreg(regs, dstreg) = (newv); | |
56287 | }}}}}}}}m68k_incpc(4); | |
56288 | fill_prefetch_0 (); | |
56289 | endlabel3003: ; | |
56290 | return 18; | |
56291 | } | |
56292 | unsigned long CPUFUNC(op_d0bb_5)(uint32_t opcode) /* ADD */ | |
56293 | { | |
56294 | uint32_t dstreg = (opcode >> 9) & 7; | |
56295 | OpcodeFamily = 11; CurrentInstrCycles = 20; | |
56296 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
56297 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
56298 | BusCyclePenalty += 2; | |
56299 | if ((srca & 1) != 0) { | |
56300 | last_fault_for_exception_3 = srca; | |
56301 | last_op_for_exception_3 = opcode; | |
56302 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
56303 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
56304 | goto endlabel3004; | |
56305 | } | |
56306 | {{ int32_t src = m68k_read_memory_32(srca); | |
56307 | { int32_t dst = m68k_dreg(regs, dstreg); | |
56308 | { refill_prefetch (m68k_getpc(), 2); | |
56309 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
56310 | { int flgs = ((int32_t)(src)) < 0; | |
56311 | int flgo = ((int32_t)(dst)) < 0; | |
56312 | int flgn = ((int32_t)(newv)) < 0; | |
56313 | SET_ZFLG (((int32_t)(newv)) == 0); | |
56314 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
56315 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
56316 | COPY_CARRY; | |
56317 | SET_NFLG (flgn != 0); | |
56318 | m68k_dreg(regs, dstreg) = (newv); | |
56319 | }}}}}}}}m68k_incpc(4); | |
56320 | fill_prefetch_0 (); | |
56321 | endlabel3004: ; | |
56322 | return 20; | |
56323 | } | |
56324 | unsigned long CPUFUNC(op_d0bc_5)(uint32_t opcode) /* ADD */ | |
56325 | { | |
56326 | uint32_t dstreg = (opcode >> 9) & 7; | |
56327 | OpcodeFamily = 11; CurrentInstrCycles = 16; | |
56328 | {{ int32_t src = get_ilong_prefetch(2); | |
56329 | { int32_t dst = m68k_dreg(regs, dstreg); | |
56330 | { refill_prefetch (m68k_getpc(), 2); | |
56331 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
56332 | { int flgs = ((int32_t)(src)) < 0; | |
56333 | int flgo = ((int32_t)(dst)) < 0; | |
56334 | int flgn = ((int32_t)(newv)) < 0; | |
56335 | SET_ZFLG (((int32_t)(newv)) == 0); | |
56336 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
56337 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
56338 | COPY_CARRY; | |
56339 | SET_NFLG (flgn != 0); | |
56340 | m68k_dreg(regs, dstreg) = (newv); | |
56341 | }}}}}}m68k_incpc(6); | |
56342 | fill_prefetch_0 (); | |
56343 | return 16; | |
56344 | } | |
56345 | unsigned long CPUFUNC(op_d0c0_5)(uint32_t opcode) /* ADDA */ | |
56346 | { | |
56347 | uint32_t srcreg = (opcode & 7); | |
56348 | uint32_t dstreg = (opcode >> 9) & 7; | |
56349 | OpcodeFamily = 12; CurrentInstrCycles = 8; | |
56350 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
56351 | { int32_t dst = m68k_areg(regs, dstreg); | |
56352 | { uint32_t newv = dst + src; | |
56353 | m68k_areg(regs, dstreg) = (newv); | |
56354 | }}}}m68k_incpc(2); | |
56355 | fill_prefetch_2 (); | |
56356 | return 8; | |
56357 | } | |
56358 | unsigned long CPUFUNC(op_d0c8_5)(uint32_t opcode) /* ADDA */ | |
56359 | { | |
56360 | uint32_t srcreg = (opcode & 7); | |
56361 | uint32_t dstreg = (opcode >> 9) & 7; | |
56362 | OpcodeFamily = 12; CurrentInstrCycles = 8; | |
56363 | {{ int16_t src = m68k_areg(regs, srcreg); | |
56364 | { int32_t dst = m68k_areg(regs, dstreg); | |
56365 | { uint32_t newv = dst + src; | |
56366 | m68k_areg(regs, dstreg) = (newv); | |
56367 | }}}}m68k_incpc(2); | |
56368 | fill_prefetch_2 (); | |
56369 | return 8; | |
56370 | } | |
56371 | unsigned long CPUFUNC(op_d0d0_5)(uint32_t opcode) /* ADDA */ | |
56372 | { | |
56373 | uint32_t srcreg = (opcode & 7); | |
56374 | uint32_t dstreg = (opcode >> 9) & 7; | |
56375 | OpcodeFamily = 12; CurrentInstrCycles = 12; | |
56376 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
56377 | if ((srca & 1) != 0) { | |
56378 | last_fault_for_exception_3 = srca; | |
56379 | last_op_for_exception_3 = opcode; | |
56380 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
56381 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
56382 | goto endlabel3008; | |
56383 | } | |
56384 | {{ int16_t src = m68k_read_memory_16(srca); | |
56385 | { int32_t dst = m68k_areg(regs, dstreg); | |
56386 | { uint32_t newv = dst + src; | |
56387 | m68k_areg(regs, dstreg) = (newv); | |
56388 | }}}}}}m68k_incpc(2); | |
56389 | fill_prefetch_2 (); | |
56390 | endlabel3008: ; | |
56391 | return 12; | |
56392 | } | |
56393 | unsigned long CPUFUNC(op_d0d8_5)(uint32_t opcode) /* ADDA */ | |
56394 | { | |
56395 | uint32_t srcreg = (opcode & 7); | |
56396 | uint32_t dstreg = (opcode >> 9) & 7; | |
56397 | OpcodeFamily = 12; CurrentInstrCycles = 12; | |
56398 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
56399 | if ((srca & 1) != 0) { | |
56400 | last_fault_for_exception_3 = srca; | |
56401 | last_op_for_exception_3 = opcode; | |
56402 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
56403 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
56404 | goto endlabel3009; | |
56405 | } | |
56406 | {{ int16_t src = m68k_read_memory_16(srca); | |
56407 | m68k_areg(regs, srcreg) += 2; | |
56408 | { int32_t dst = m68k_areg(regs, dstreg); | |
56409 | { uint32_t newv = dst + src; | |
56410 | m68k_areg(regs, dstreg) = (newv); | |
56411 | }}}}}}m68k_incpc(2); | |
56412 | fill_prefetch_2 (); | |
56413 | endlabel3009: ; | |
56414 | return 12; | |
56415 | } | |
56416 | unsigned long CPUFUNC(op_d0e0_5)(uint32_t opcode) /* ADDA */ | |
56417 | { | |
56418 | uint32_t srcreg = (opcode & 7); | |
56419 | uint32_t dstreg = (opcode >> 9) & 7; | |
56420 | OpcodeFamily = 12; CurrentInstrCycles = 14; | |
56421 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
56422 | if ((srca & 1) != 0) { | |
56423 | last_fault_for_exception_3 = srca; | |
56424 | last_op_for_exception_3 = opcode; | |
56425 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
56426 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
56427 | goto endlabel3010; | |
56428 | } | |
56429 | {{ int16_t src = m68k_read_memory_16(srca); | |
56430 | m68k_areg (regs, srcreg) = srca; | |
56431 | { int32_t dst = m68k_areg(regs, dstreg); | |
56432 | { uint32_t newv = dst + src; | |
56433 | m68k_areg(regs, dstreg) = (newv); | |
56434 | }}}}}}m68k_incpc(2); | |
56435 | fill_prefetch_2 (); | |
56436 | endlabel3010: ; | |
56437 | return 14; | |
56438 | } | |
56439 | unsigned long CPUFUNC(op_d0e8_5)(uint32_t opcode) /* ADDA */ | |
56440 | { | |
56441 | uint32_t srcreg = (opcode & 7); | |
56442 | uint32_t dstreg = (opcode >> 9) & 7; | |
56443 | OpcodeFamily = 12; CurrentInstrCycles = 16; | |
56444 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
56445 | if ((srca & 1) != 0) { | |
56446 | last_fault_for_exception_3 = srca; | |
56447 | last_op_for_exception_3 = opcode; | |
56448 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
56449 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
56450 | goto endlabel3011; | |
56451 | } | |
56452 | {{ int16_t src = m68k_read_memory_16(srca); | |
56453 | { int32_t dst = m68k_areg(regs, dstreg); | |
56454 | { uint32_t newv = dst + src; | |
56455 | m68k_areg(regs, dstreg) = (newv); | |
56456 | }}}}}}m68k_incpc(4); | |
56457 | fill_prefetch_0 (); | |
56458 | endlabel3011: ; | |
56459 | return 16; | |
56460 | } | |
56461 | unsigned long CPUFUNC(op_d0f0_5)(uint32_t opcode) /* ADDA */ | |
56462 | { | |
56463 | uint32_t srcreg = (opcode & 7); | |
56464 | uint32_t dstreg = (opcode >> 9) & 7; | |
56465 | OpcodeFamily = 12; CurrentInstrCycles = 18; | |
56466 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
56467 | BusCyclePenalty += 2; | |
56468 | if ((srca & 1) != 0) { | |
56469 | last_fault_for_exception_3 = srca; | |
56470 | last_op_for_exception_3 = opcode; | |
56471 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
56472 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
56473 | goto endlabel3012; | |
56474 | } | |
56475 | {{ int16_t src = m68k_read_memory_16(srca); | |
56476 | { int32_t dst = m68k_areg(regs, dstreg); | |
56477 | { uint32_t newv = dst + src; | |
56478 | m68k_areg(regs, dstreg) = (newv); | |
56479 | }}}}}}m68k_incpc(4); | |
56480 | fill_prefetch_0 (); | |
56481 | endlabel3012: ; | |
56482 | return 18; | |
56483 | } | |
56484 | unsigned long CPUFUNC(op_d0f8_5)(uint32_t opcode) /* ADDA */ | |
56485 | { | |
56486 | uint32_t dstreg = (opcode >> 9) & 7; | |
56487 | OpcodeFamily = 12; CurrentInstrCycles = 16; | |
56488 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
56489 | if ((srca & 1) != 0) { | |
56490 | last_fault_for_exception_3 = srca; | |
56491 | last_op_for_exception_3 = opcode; | |
56492 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
56493 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
56494 | goto endlabel3013; | |
56495 | } | |
56496 | {{ int16_t src = m68k_read_memory_16(srca); | |
56497 | { int32_t dst = m68k_areg(regs, dstreg); | |
56498 | { uint32_t newv = dst + src; | |
56499 | m68k_areg(regs, dstreg) = (newv); | |
56500 | }}}}}}m68k_incpc(4); | |
56501 | fill_prefetch_0 (); | |
56502 | endlabel3013: ; | |
56503 | return 16; | |
56504 | } | |
56505 | unsigned long CPUFUNC(op_d0f9_5)(uint32_t opcode) /* ADDA */ | |
56506 | { | |
56507 | uint32_t dstreg = (opcode >> 9) & 7; | |
56508 | OpcodeFamily = 12; CurrentInstrCycles = 20; | |
56509 | {{ uint32_t srca = get_ilong_prefetch(2); | |
56510 | if ((srca & 1) != 0) { | |
56511 | last_fault_for_exception_3 = srca; | |
56512 | last_op_for_exception_3 = opcode; | |
56513 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
56514 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
56515 | goto endlabel3014; | |
56516 | } | |
56517 | {{ int16_t src = m68k_read_memory_16(srca); | |
56518 | { int32_t dst = m68k_areg(regs, dstreg); | |
56519 | { uint32_t newv = dst + src; | |
56520 | m68k_areg(regs, dstreg) = (newv); | |
56521 | }}}}}}m68k_incpc(6); | |
56522 | fill_prefetch_0 (); | |
56523 | endlabel3014: ; | |
56524 | return 20; | |
56525 | } | |
56526 | unsigned long CPUFUNC(op_d0fa_5)(uint32_t opcode) /* ADDA */ | |
56527 | { | |
56528 | uint32_t dstreg = (opcode >> 9) & 7; | |
56529 | OpcodeFamily = 12; CurrentInstrCycles = 16; | |
56530 | {{ uint32_t srca = m68k_getpc () + 2; | |
56531 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
56532 | if ((srca & 1) != 0) { | |
56533 | last_fault_for_exception_3 = srca; | |
56534 | last_op_for_exception_3 = opcode; | |
56535 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
56536 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
56537 | goto endlabel3015; | |
56538 | } | |
56539 | {{ int16_t src = m68k_read_memory_16(srca); | |
56540 | { int32_t dst = m68k_areg(regs, dstreg); | |
56541 | { uint32_t newv = dst + src; | |
56542 | m68k_areg(regs, dstreg) = (newv); | |
56543 | }}}}}}m68k_incpc(4); | |
56544 | fill_prefetch_0 (); | |
56545 | endlabel3015: ; | |
56546 | return 16; | |
56547 | } | |
56548 | unsigned long CPUFUNC(op_d0fb_5)(uint32_t opcode) /* ADDA */ | |
56549 | { | |
56550 | uint32_t dstreg = (opcode >> 9) & 7; | |
56551 | OpcodeFamily = 12; CurrentInstrCycles = 18; | |
56552 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
56553 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
56554 | BusCyclePenalty += 2; | |
56555 | if ((srca & 1) != 0) { | |
56556 | last_fault_for_exception_3 = srca; | |
56557 | last_op_for_exception_3 = opcode; | |
56558 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
56559 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
56560 | goto endlabel3016; | |
56561 | } | |
56562 | {{ int16_t src = m68k_read_memory_16(srca); | |
56563 | { int32_t dst = m68k_areg(regs, dstreg); | |
56564 | { uint32_t newv = dst + src; | |
56565 | m68k_areg(regs, dstreg) = (newv); | |
56566 | }}}}}}m68k_incpc(4); | |
56567 | fill_prefetch_0 (); | |
56568 | endlabel3016: ; | |
56569 | return 18; | |
56570 | } | |
56571 | unsigned long CPUFUNC(op_d0fc_5)(uint32_t opcode) /* ADDA */ | |
56572 | { | |
56573 | uint32_t dstreg = (opcode >> 9) & 7; | |
56574 | OpcodeFamily = 12; CurrentInstrCycles = 12; | |
56575 | {{ int16_t src = get_iword_prefetch(2); | |
56576 | { int32_t dst = m68k_areg(regs, dstreg); | |
56577 | { uint32_t newv = dst + src; | |
56578 | m68k_areg(regs, dstreg) = (newv); | |
56579 | }}}}m68k_incpc(4); | |
56580 | fill_prefetch_0 (); | |
56581 | return 12; | |
56582 | } | |
56583 | unsigned long CPUFUNC(op_d100_5)(uint32_t opcode) /* ADDX */ | |
56584 | { | |
56585 | uint32_t srcreg = (opcode & 7); | |
56586 | uint32_t dstreg = (opcode >> 9) & 7; | |
56587 | OpcodeFamily = 13; CurrentInstrCycles = 4; | |
56588 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
56589 | { int8_t dst = m68k_dreg(regs, dstreg); | |
56590 | { uint32_t newv = dst + src + (GET_XFLG ? 1 : 0); | |
56591 | { int flgs = ((int8_t)(src)) < 0; | |
56592 | int flgo = ((int8_t)(dst)) < 0; | |
56593 | int flgn = ((int8_t)(newv)) < 0; | |
56594 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
56595 | SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn))); | |
56596 | COPY_CARRY; | |
56597 | SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); | |
56598 | SET_NFLG (((int8_t)(newv)) < 0); | |
56599 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((newv) & 0xff); | |
56600 | }}}}}m68k_incpc(2); | |
56601 | fill_prefetch_2 (); | |
56602 | return 4; | |
56603 | } | |
56604 | unsigned long CPUFUNC(op_d108_5)(uint32_t opcode) /* ADDX */ | |
56605 | { | |
56606 | uint32_t srcreg = (opcode & 7); | |
56607 | uint32_t dstreg = (opcode >> 9) & 7; | |
56608 | OpcodeFamily = 13; CurrentInstrCycles = 18; | |
56609 | {{ uint32_t srca = m68k_areg(regs, srcreg) - areg_byteinc[srcreg]; | |
56610 | { int8_t src = m68k_read_memory_8(srca); | |
56611 | m68k_areg (regs, srcreg) = srca; | |
56612 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
56613 | { int8_t dst = m68k_read_memory_8(dsta); | |
56614 | m68k_areg (regs, dstreg) = dsta; | |
56615 | { uint32_t newv = dst + src + (GET_XFLG ? 1 : 0); | |
56616 | { int flgs = ((int8_t)(src)) < 0; | |
56617 | int flgo = ((int8_t)(dst)) < 0; | |
56618 | int flgn = ((int8_t)(newv)) < 0; | |
56619 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
56620 | SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn))); | |
56621 | COPY_CARRY; | |
56622 | SET_ZFLG (GET_ZFLG & (((int8_t)(newv)) == 0)); | |
56623 | SET_NFLG (((int8_t)(newv)) < 0); | |
56624 | m68k_incpc(2); | |
56625 | fill_prefetch_2 (); | |
56626 | m68k_write_memory_8(dsta,newv); | |
56627 | }}}}}}}return 18; | |
56628 | } | |
56629 | unsigned long CPUFUNC(op_d110_5)(uint32_t opcode) /* ADD */ | |
56630 | { | |
56631 | uint32_t srcreg = ((opcode >> 9) & 7); | |
56632 | uint32_t dstreg = opcode & 7; | |
56633 | OpcodeFamily = 11; CurrentInstrCycles = 12; | |
56634 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
56635 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
56636 | { int8_t dst = m68k_read_memory_8(dsta); | |
56637 | { refill_prefetch (m68k_getpc(), 2); | |
56638 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
56639 | { int flgs = ((int8_t)(src)) < 0; | |
56640 | int flgo = ((int8_t)(dst)) < 0; | |
56641 | int flgn = ((int8_t)(newv)) < 0; | |
56642 | SET_ZFLG (((int8_t)(newv)) == 0); | |
56643 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
56644 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
56645 | COPY_CARRY; | |
56646 | SET_NFLG (flgn != 0); | |
56647 | m68k_incpc(2); | |
56648 | fill_prefetch_2 (); | |
56649 | m68k_write_memory_8(dsta,newv); | |
56650 | }}}}}}}return 12; | |
56651 | } | |
56652 | unsigned long CPUFUNC(op_d118_5)(uint32_t opcode) /* ADD */ | |
56653 | { | |
56654 | uint32_t srcreg = ((opcode >> 9) & 7); | |
56655 | uint32_t dstreg = opcode & 7; | |
56656 | OpcodeFamily = 11; CurrentInstrCycles = 12; | |
56657 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
56658 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
56659 | { int8_t dst = m68k_read_memory_8(dsta); | |
56660 | m68k_areg(regs, dstreg) += areg_byteinc[dstreg]; | |
56661 | { refill_prefetch (m68k_getpc(), 2); | |
56662 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
56663 | { int flgs = ((int8_t)(src)) < 0; | |
56664 | int flgo = ((int8_t)(dst)) < 0; | |
56665 | int flgn = ((int8_t)(newv)) < 0; | |
56666 | SET_ZFLG (((int8_t)(newv)) == 0); | |
56667 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
56668 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
56669 | COPY_CARRY; | |
56670 | SET_NFLG (flgn != 0); | |
56671 | m68k_incpc(2); | |
56672 | fill_prefetch_2 (); | |
56673 | m68k_write_memory_8(dsta,newv); | |
56674 | }}}}}}}return 12; | |
56675 | } | |
56676 | unsigned long CPUFUNC(op_d120_5)(uint32_t opcode) /* ADD */ | |
56677 | { | |
56678 | uint32_t srcreg = ((opcode >> 9) & 7); | |
56679 | uint32_t dstreg = opcode & 7; | |
56680 | OpcodeFamily = 11; CurrentInstrCycles = 14; | |
56681 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
56682 | { uint32_t dsta = m68k_areg(regs, dstreg) - areg_byteinc[dstreg]; | |
56683 | { int8_t dst = m68k_read_memory_8(dsta); | |
56684 | m68k_areg (regs, dstreg) = dsta; | |
56685 | { refill_prefetch (m68k_getpc(), 2); | |
56686 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
56687 | { int flgs = ((int8_t)(src)) < 0; | |
56688 | int flgo = ((int8_t)(dst)) < 0; | |
56689 | int flgn = ((int8_t)(newv)) < 0; | |
56690 | SET_ZFLG (((int8_t)(newv)) == 0); | |
56691 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
56692 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
56693 | COPY_CARRY; | |
56694 | SET_NFLG (flgn != 0); | |
56695 | m68k_incpc(2); | |
56696 | fill_prefetch_2 (); | |
56697 | m68k_write_memory_8(dsta,newv); | |
56698 | }}}}}}}return 14; | |
56699 | } | |
56700 | unsigned long CPUFUNC(op_d128_5)(uint32_t opcode) /* ADD */ | |
56701 | { | |
56702 | uint32_t srcreg = ((opcode >> 9) & 7); | |
56703 | uint32_t dstreg = opcode & 7; | |
56704 | OpcodeFamily = 11; CurrentInstrCycles = 16; | |
56705 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
56706 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
56707 | { int8_t dst = m68k_read_memory_8(dsta); | |
56708 | { refill_prefetch (m68k_getpc(), 2); | |
56709 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
56710 | { int flgs = ((int8_t)(src)) < 0; | |
56711 | int flgo = ((int8_t)(dst)) < 0; | |
56712 | int flgn = ((int8_t)(newv)) < 0; | |
56713 | SET_ZFLG (((int8_t)(newv)) == 0); | |
56714 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
56715 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
56716 | COPY_CARRY; | |
56717 | SET_NFLG (flgn != 0); | |
56718 | m68k_incpc(4); | |
56719 | fill_prefetch_0 (); | |
56720 | m68k_write_memory_8(dsta,newv); | |
56721 | }}}}}}}return 16; | |
56722 | } | |
56723 | unsigned long CPUFUNC(op_d130_5)(uint32_t opcode) /* ADD */ | |
56724 | { | |
56725 | uint32_t srcreg = ((opcode >> 9) & 7); | |
56726 | uint32_t dstreg = opcode & 7; | |
56727 | OpcodeFamily = 11; CurrentInstrCycles = 18; | |
56728 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
56729 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); | |
56730 | BusCyclePenalty += 2; | |
56731 | { int8_t dst = m68k_read_memory_8(dsta); | |
56732 | { refill_prefetch (m68k_getpc(), 2); | |
56733 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
56734 | { int flgs = ((int8_t)(src)) < 0; | |
56735 | int flgo = ((int8_t)(dst)) < 0; | |
56736 | int flgn = ((int8_t)(newv)) < 0; | |
56737 | SET_ZFLG (((int8_t)(newv)) == 0); | |
56738 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
56739 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
56740 | COPY_CARRY; | |
56741 | SET_NFLG (flgn != 0); | |
56742 | m68k_incpc(4); | |
56743 | fill_prefetch_0 (); | |
56744 | m68k_write_memory_8(dsta,newv); | |
56745 | }}}}}}}return 18; | |
56746 | } | |
56747 | unsigned long CPUFUNC(op_d138_5)(uint32_t opcode) /* ADD */ | |
56748 | { | |
56749 | uint32_t srcreg = ((opcode >> 9) & 7); | |
56750 | OpcodeFamily = 11; CurrentInstrCycles = 16; | |
56751 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
56752 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); | |
56753 | { int8_t dst = m68k_read_memory_8(dsta); | |
56754 | { refill_prefetch (m68k_getpc(), 2); | |
56755 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
56756 | { int flgs = ((int8_t)(src)) < 0; | |
56757 | int flgo = ((int8_t)(dst)) < 0; | |
56758 | int flgn = ((int8_t)(newv)) < 0; | |
56759 | SET_ZFLG (((int8_t)(newv)) == 0); | |
56760 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
56761 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
56762 | COPY_CARRY; | |
56763 | SET_NFLG (flgn != 0); | |
56764 | m68k_incpc(4); | |
56765 | fill_prefetch_0 (); | |
56766 | m68k_write_memory_8(dsta,newv); | |
56767 | }}}}}}}return 16; | |
56768 | } | |
56769 | unsigned long CPUFUNC(op_d139_5)(uint32_t opcode) /* ADD */ | |
56770 | { | |
56771 | uint32_t srcreg = ((opcode >> 9) & 7); | |
56772 | OpcodeFamily = 11; CurrentInstrCycles = 20; | |
56773 | {{ int8_t src = m68k_dreg(regs, srcreg); | |
56774 | { uint32_t dsta = get_ilong_prefetch(2); | |
56775 | { int8_t dst = m68k_read_memory_8(dsta); | |
56776 | { refill_prefetch (m68k_getpc(), 2); | |
56777 | {uint32_t newv = ((int8_t)(dst)) + ((int8_t)(src)); | |
56778 | { int flgs = ((int8_t)(src)) < 0; | |
56779 | int flgo = ((int8_t)(dst)) < 0; | |
56780 | int flgn = ((int8_t)(newv)) < 0; | |
56781 | SET_ZFLG (((int8_t)(newv)) == 0); | |
56782 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
56783 | SET_CFLG (((uint8_t)(~dst)) < ((uint8_t)(src))); | |
56784 | COPY_CARRY; | |
56785 | SET_NFLG (flgn != 0); | |
56786 | m68k_incpc(6); | |
56787 | fill_prefetch_0 (); | |
56788 | m68k_write_memory_8(dsta,newv); | |
56789 | }}}}}}}return 20; | |
56790 | } | |
56791 | unsigned long CPUFUNC(op_d140_5)(uint32_t opcode) /* ADDX */ | |
56792 | { | |
56793 | uint32_t srcreg = (opcode & 7); | |
56794 | uint32_t dstreg = (opcode >> 9) & 7; | |
56795 | OpcodeFamily = 13; CurrentInstrCycles = 4; | |
56796 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
56797 | { int16_t dst = m68k_dreg(regs, dstreg); | |
56798 | { uint32_t newv = dst + src + (GET_XFLG ? 1 : 0); | |
56799 | { int flgs = ((int16_t)(src)) < 0; | |
56800 | int flgo = ((int16_t)(dst)) < 0; | |
56801 | int flgn = ((int16_t)(newv)) < 0; | |
56802 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
56803 | SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn))); | |
56804 | COPY_CARRY; | |
56805 | SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0)); | |
56806 | SET_NFLG (((int16_t)(newv)) < 0); | |
56807 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((newv) & 0xffff); | |
56808 | }}}}}m68k_incpc(2); | |
56809 | fill_prefetch_2 (); | |
56810 | return 4; | |
56811 | } | |
56812 | unsigned long CPUFUNC(op_d148_5)(uint32_t opcode) /* ADDX */ | |
56813 | { | |
56814 | uint32_t srcreg = (opcode & 7); | |
56815 | uint32_t dstreg = (opcode >> 9) & 7; | |
56816 | OpcodeFamily = 13; CurrentInstrCycles = 18; | |
56817 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 2; | |
56818 | if ((srca & 1) != 0) { | |
56819 | last_fault_for_exception_3 = srca; | |
56820 | last_op_for_exception_3 = opcode; | |
56821 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
56822 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
56823 | goto endlabel3028; | |
56824 | } | |
56825 | {{ int16_t src = m68k_read_memory_16(srca); | |
56826 | m68k_areg (regs, srcreg) = srca; | |
56827 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
56828 | if ((dsta & 1) != 0) { | |
56829 | last_fault_for_exception_3 = dsta; | |
56830 | last_op_for_exception_3 = opcode; | |
56831 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
56832 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
56833 | goto endlabel3028; | |
56834 | } | |
56835 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
56836 | m68k_areg (regs, dstreg) = dsta; | |
56837 | { uint32_t newv = dst + src + (GET_XFLG ? 1 : 0); | |
56838 | { int flgs = ((int16_t)(src)) < 0; | |
56839 | int flgo = ((int16_t)(dst)) < 0; | |
56840 | int flgn = ((int16_t)(newv)) < 0; | |
56841 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
56842 | SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn))); | |
56843 | COPY_CARRY; | |
56844 | SET_ZFLG (GET_ZFLG & (((int16_t)(newv)) == 0)); | |
56845 | SET_NFLG (((int16_t)(newv)) < 0); | |
56846 | m68k_incpc(2); | |
56847 | fill_prefetch_2 (); | |
56848 | m68k_write_memory_16(dsta,newv); | |
56849 | }}}}}}}}}endlabel3028: ; | |
56850 | return 18; | |
56851 | } | |
56852 | unsigned long CPUFUNC(op_d150_5)(uint32_t opcode) /* ADD */ | |
56853 | { | |
56854 | uint32_t srcreg = ((opcode >> 9) & 7); | |
56855 | uint32_t dstreg = opcode & 7; | |
56856 | OpcodeFamily = 11; CurrentInstrCycles = 12; | |
56857 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
56858 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
56859 | if ((dsta & 1) != 0) { | |
56860 | last_fault_for_exception_3 = dsta; | |
56861 | last_op_for_exception_3 = opcode; | |
56862 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
56863 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
56864 | goto endlabel3029; | |
56865 | } | |
56866 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
56867 | { refill_prefetch (m68k_getpc(), 2); | |
56868 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
56869 | { int flgs = ((int16_t)(src)) < 0; | |
56870 | int flgo = ((int16_t)(dst)) < 0; | |
56871 | int flgn = ((int16_t)(newv)) < 0; | |
56872 | SET_ZFLG (((int16_t)(newv)) == 0); | |
56873 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
56874 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
56875 | COPY_CARRY; | |
56876 | SET_NFLG (flgn != 0); | |
56877 | m68k_incpc(2); | |
56878 | fill_prefetch_2 (); | |
56879 | m68k_write_memory_16(dsta,newv); | |
56880 | }}}}}}}}endlabel3029: ; | |
56881 | return 12; | |
56882 | } | |
56883 | unsigned long CPUFUNC(op_d158_5)(uint32_t opcode) /* ADD */ | |
56884 | { | |
56885 | uint32_t srcreg = ((opcode >> 9) & 7); | |
56886 | uint32_t dstreg = opcode & 7; | |
56887 | OpcodeFamily = 11; CurrentInstrCycles = 12; | |
56888 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
56889 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
56890 | if ((dsta & 1) != 0) { | |
56891 | last_fault_for_exception_3 = dsta; | |
56892 | last_op_for_exception_3 = opcode; | |
56893 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
56894 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
56895 | goto endlabel3030; | |
56896 | } | |
56897 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
56898 | m68k_areg(regs, dstreg) += 2; | |
56899 | { refill_prefetch (m68k_getpc(), 2); | |
56900 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
56901 | { int flgs = ((int16_t)(src)) < 0; | |
56902 | int flgo = ((int16_t)(dst)) < 0; | |
56903 | int flgn = ((int16_t)(newv)) < 0; | |
56904 | SET_ZFLG (((int16_t)(newv)) == 0); | |
56905 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
56906 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
56907 | COPY_CARRY; | |
56908 | SET_NFLG (flgn != 0); | |
56909 | m68k_incpc(2); | |
56910 | fill_prefetch_2 (); | |
56911 | m68k_write_memory_16(dsta,newv); | |
56912 | }}}}}}}}endlabel3030: ; | |
56913 | return 12; | |
56914 | } | |
56915 | unsigned long CPUFUNC(op_d160_5)(uint32_t opcode) /* ADD */ | |
56916 | { | |
56917 | uint32_t srcreg = ((opcode >> 9) & 7); | |
56918 | uint32_t dstreg = opcode & 7; | |
56919 | OpcodeFamily = 11; CurrentInstrCycles = 14; | |
56920 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
56921 | { uint32_t dsta = m68k_areg(regs, dstreg) - 2; | |
56922 | if ((dsta & 1) != 0) { | |
56923 | last_fault_for_exception_3 = dsta; | |
56924 | last_op_for_exception_3 = opcode; | |
56925 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
56926 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
56927 | goto endlabel3031; | |
56928 | } | |
56929 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
56930 | m68k_areg (regs, dstreg) = dsta; | |
56931 | { refill_prefetch (m68k_getpc(), 2); | |
56932 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
56933 | { int flgs = ((int16_t)(src)) < 0; | |
56934 | int flgo = ((int16_t)(dst)) < 0; | |
56935 | int flgn = ((int16_t)(newv)) < 0; | |
56936 | SET_ZFLG (((int16_t)(newv)) == 0); | |
56937 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
56938 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
56939 | COPY_CARRY; | |
56940 | SET_NFLG (flgn != 0); | |
56941 | m68k_incpc(2); | |
56942 | fill_prefetch_2 (); | |
56943 | m68k_write_memory_16(dsta,newv); | |
56944 | }}}}}}}}endlabel3031: ; | |
56945 | return 14; | |
56946 | } | |
56947 | unsigned long CPUFUNC(op_d168_5)(uint32_t opcode) /* ADD */ | |
56948 | { | |
56949 | uint32_t srcreg = ((opcode >> 9) & 7); | |
56950 | uint32_t dstreg = opcode & 7; | |
56951 | OpcodeFamily = 11; CurrentInstrCycles = 16; | |
56952 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
56953 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
56954 | if ((dsta & 1) != 0) { | |
56955 | last_fault_for_exception_3 = dsta; | |
56956 | last_op_for_exception_3 = opcode; | |
56957 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
56958 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
56959 | goto endlabel3032; | |
56960 | } | |
56961 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
56962 | { refill_prefetch (m68k_getpc(), 2); | |
56963 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
56964 | { int flgs = ((int16_t)(src)) < 0; | |
56965 | int flgo = ((int16_t)(dst)) < 0; | |
56966 | int flgn = ((int16_t)(newv)) < 0; | |
56967 | SET_ZFLG (((int16_t)(newv)) == 0); | |
56968 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
56969 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
56970 | COPY_CARRY; | |
56971 | SET_NFLG (flgn != 0); | |
56972 | m68k_incpc(4); | |
56973 | fill_prefetch_0 (); | |
56974 | m68k_write_memory_16(dsta,newv); | |
56975 | }}}}}}}}endlabel3032: ; | |
56976 | return 16; | |
56977 | } | |
56978 | unsigned long CPUFUNC(op_d170_5)(uint32_t opcode) /* ADD */ | |
56979 | { | |
56980 | uint32_t srcreg = ((opcode >> 9) & 7); | |
56981 | uint32_t dstreg = opcode & 7; | |
56982 | OpcodeFamily = 11; CurrentInstrCycles = 18; | |
56983 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
56984 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); | |
56985 | BusCyclePenalty += 2; | |
56986 | if ((dsta & 1) != 0) { | |
56987 | last_fault_for_exception_3 = dsta; | |
56988 | last_op_for_exception_3 = opcode; | |
56989 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
56990 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
56991 | goto endlabel3033; | |
56992 | } | |
56993 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
56994 | { refill_prefetch (m68k_getpc(), 2); | |
56995 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
56996 | { int flgs = ((int16_t)(src)) < 0; | |
56997 | int flgo = ((int16_t)(dst)) < 0; | |
56998 | int flgn = ((int16_t)(newv)) < 0; | |
56999 | SET_ZFLG (((int16_t)(newv)) == 0); | |
57000 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
57001 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
57002 | COPY_CARRY; | |
57003 | SET_NFLG (flgn != 0); | |
57004 | m68k_incpc(4); | |
57005 | fill_prefetch_0 (); | |
57006 | m68k_write_memory_16(dsta,newv); | |
57007 | }}}}}}}}endlabel3033: ; | |
57008 | return 18; | |
57009 | } | |
57010 | unsigned long CPUFUNC(op_d178_5)(uint32_t opcode) /* ADD */ | |
57011 | { | |
57012 | uint32_t srcreg = ((opcode >> 9) & 7); | |
57013 | OpcodeFamily = 11; CurrentInstrCycles = 16; | |
57014 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
57015 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); | |
57016 | if ((dsta & 1) != 0) { | |
57017 | last_fault_for_exception_3 = dsta; | |
57018 | last_op_for_exception_3 = opcode; | |
57019 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
57020 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
57021 | goto endlabel3034; | |
57022 | } | |
57023 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
57024 | { refill_prefetch (m68k_getpc(), 2); | |
57025 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
57026 | { int flgs = ((int16_t)(src)) < 0; | |
57027 | int flgo = ((int16_t)(dst)) < 0; | |
57028 | int flgn = ((int16_t)(newv)) < 0; | |
57029 | SET_ZFLG (((int16_t)(newv)) == 0); | |
57030 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
57031 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
57032 | COPY_CARRY; | |
57033 | SET_NFLG (flgn != 0); | |
57034 | m68k_incpc(4); | |
57035 | fill_prefetch_0 (); | |
57036 | m68k_write_memory_16(dsta,newv); | |
57037 | }}}}}}}}endlabel3034: ; | |
57038 | return 16; | |
57039 | } | |
57040 | unsigned long CPUFUNC(op_d179_5)(uint32_t opcode) /* ADD */ | |
57041 | { | |
57042 | uint32_t srcreg = ((opcode >> 9) & 7); | |
57043 | OpcodeFamily = 11; CurrentInstrCycles = 20; | |
57044 | {{ int16_t src = m68k_dreg(regs, srcreg); | |
57045 | { uint32_t dsta = get_ilong_prefetch(2); | |
57046 | if ((dsta & 1) != 0) { | |
57047 | last_fault_for_exception_3 = dsta; | |
57048 | last_op_for_exception_3 = opcode; | |
57049 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
57050 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
57051 | goto endlabel3035; | |
57052 | } | |
57053 | {{ int16_t dst = m68k_read_memory_16(dsta); | |
57054 | { refill_prefetch (m68k_getpc(), 2); | |
57055 | {uint32_t newv = ((int16_t)(dst)) + ((int16_t)(src)); | |
57056 | { int flgs = ((int16_t)(src)) < 0; | |
57057 | int flgo = ((int16_t)(dst)) < 0; | |
57058 | int flgn = ((int16_t)(newv)) < 0; | |
57059 | SET_ZFLG (((int16_t)(newv)) == 0); | |
57060 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
57061 | SET_CFLG (((uint16_t)(~dst)) < ((uint16_t)(src))); | |
57062 | COPY_CARRY; | |
57063 | SET_NFLG (flgn != 0); | |
57064 | m68k_incpc(6); | |
57065 | fill_prefetch_0 (); | |
57066 | m68k_write_memory_16(dsta,newv); | |
57067 | }}}}}}}}endlabel3035: ; | |
57068 | return 20; | |
57069 | } | |
57070 | unsigned long CPUFUNC(op_d180_5)(uint32_t opcode) /* ADDX */ | |
57071 | { | |
57072 | uint32_t srcreg = (opcode & 7); | |
57073 | uint32_t dstreg = (opcode >> 9) & 7; | |
57074 | OpcodeFamily = 13; CurrentInstrCycles = 8; | |
57075 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
57076 | { int32_t dst = m68k_dreg(regs, dstreg); | |
57077 | { uint32_t newv = dst + src + (GET_XFLG ? 1 : 0); | |
57078 | { int flgs = ((int32_t)(src)) < 0; | |
57079 | int flgo = ((int32_t)(dst)) < 0; | |
57080 | int flgn = ((int32_t)(newv)) < 0; | |
57081 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
57082 | SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn))); | |
57083 | COPY_CARRY; | |
57084 | SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0)); | |
57085 | SET_NFLG (((int32_t)(newv)) < 0); | |
57086 | m68k_dreg(regs, dstreg) = (newv); | |
57087 | }}}}}m68k_incpc(2); | |
57088 | fill_prefetch_2 (); | |
57089 | return 8; | |
57090 | } | |
57091 | unsigned long CPUFUNC(op_d188_5)(uint32_t opcode) /* ADDX */ | |
57092 | { | |
57093 | uint32_t srcreg = (opcode & 7); | |
57094 | uint32_t dstreg = (opcode >> 9) & 7; | |
57095 | OpcodeFamily = 13; CurrentInstrCycles = 30; | |
57096 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 4; | |
57097 | if ((srca & 1) != 0) { | |
57098 | last_fault_for_exception_3 = srca; | |
57099 | last_op_for_exception_3 = opcode; | |
57100 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
57101 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
57102 | goto endlabel3037; | |
57103 | } | |
57104 | {{ int32_t src = m68k_read_memory_32(srca); | |
57105 | m68k_areg (regs, srcreg) = srca; | |
57106 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
57107 | if ((dsta & 1) != 0) { | |
57108 | last_fault_for_exception_3 = dsta; | |
57109 | last_op_for_exception_3 = opcode; | |
57110 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
57111 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
57112 | goto endlabel3037; | |
57113 | } | |
57114 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
57115 | m68k_areg (regs, dstreg) = dsta; | |
57116 | { uint32_t newv = dst + src + (GET_XFLG ? 1 : 0); | |
57117 | { int flgs = ((int32_t)(src)) < 0; | |
57118 | int flgo = ((int32_t)(dst)) < 0; | |
57119 | int flgn = ((int32_t)(newv)) < 0; | |
57120 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
57121 | SET_CFLG (flgs ^ ((flgs ^ flgo) & (flgo ^ flgn))); | |
57122 | COPY_CARRY; | |
57123 | SET_ZFLG (GET_ZFLG & (((int32_t)(newv)) == 0)); | |
57124 | SET_NFLG (((int32_t)(newv)) < 0); | |
57125 | m68k_incpc(2); | |
57126 | fill_prefetch_2 (); | |
57127 | m68k_write_memory_32(dsta,newv); | |
57128 | }}}}}}}}}endlabel3037: ; | |
57129 | return 30; | |
57130 | } | |
57131 | unsigned long CPUFUNC(op_d190_5)(uint32_t opcode) /* ADD */ | |
57132 | { | |
57133 | uint32_t srcreg = ((opcode >> 9) & 7); | |
57134 | uint32_t dstreg = opcode & 7; | |
57135 | OpcodeFamily = 11; CurrentInstrCycles = 20; | |
57136 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
57137 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
57138 | if ((dsta & 1) != 0) { | |
57139 | last_fault_for_exception_3 = dsta; | |
57140 | last_op_for_exception_3 = opcode; | |
57141 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
57142 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
57143 | goto endlabel3038; | |
57144 | } | |
57145 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
57146 | { refill_prefetch (m68k_getpc(), 2); | |
57147 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
57148 | { int flgs = ((int32_t)(src)) < 0; | |
57149 | int flgo = ((int32_t)(dst)) < 0; | |
57150 | int flgn = ((int32_t)(newv)) < 0; | |
57151 | SET_ZFLG (((int32_t)(newv)) == 0); | |
57152 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
57153 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
57154 | COPY_CARRY; | |
57155 | SET_NFLG (flgn != 0); | |
57156 | m68k_incpc(2); | |
57157 | fill_prefetch_2 (); | |
57158 | m68k_write_memory_32(dsta,newv); | |
57159 | }}}}}}}}endlabel3038: ; | |
57160 | return 20; | |
57161 | } | |
57162 | unsigned long CPUFUNC(op_d198_5)(uint32_t opcode) /* ADD */ | |
57163 | { | |
57164 | uint32_t srcreg = ((opcode >> 9) & 7); | |
57165 | uint32_t dstreg = opcode & 7; | |
57166 | OpcodeFamily = 11; CurrentInstrCycles = 20; | |
57167 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
57168 | { uint32_t dsta = m68k_areg(regs, dstreg); | |
57169 | if ((dsta & 1) != 0) { | |
57170 | last_fault_for_exception_3 = dsta; | |
57171 | last_op_for_exception_3 = opcode; | |
57172 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
57173 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
57174 | goto endlabel3039; | |
57175 | } | |
57176 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
57177 | m68k_areg(regs, dstreg) += 4; | |
57178 | { refill_prefetch (m68k_getpc(), 2); | |
57179 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
57180 | { int flgs = ((int32_t)(src)) < 0; | |
57181 | int flgo = ((int32_t)(dst)) < 0; | |
57182 | int flgn = ((int32_t)(newv)) < 0; | |
57183 | SET_ZFLG (((int32_t)(newv)) == 0); | |
57184 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
57185 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
57186 | COPY_CARRY; | |
57187 | SET_NFLG (flgn != 0); | |
57188 | m68k_incpc(2); | |
57189 | fill_prefetch_2 (); | |
57190 | m68k_write_memory_32(dsta,newv); | |
57191 | }}}}}}}}endlabel3039: ; | |
57192 | return 20; | |
57193 | } | |
57194 | unsigned long CPUFUNC(op_d1a0_5)(uint32_t opcode) /* ADD */ | |
57195 | { | |
57196 | uint32_t srcreg = ((opcode >> 9) & 7); | |
57197 | uint32_t dstreg = opcode & 7; | |
57198 | OpcodeFamily = 11; CurrentInstrCycles = 22; | |
57199 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
57200 | { uint32_t dsta = m68k_areg(regs, dstreg) - 4; | |
57201 | if ((dsta & 1) != 0) { | |
57202 | last_fault_for_exception_3 = dsta; | |
57203 | last_op_for_exception_3 = opcode; | |
57204 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
57205 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
57206 | goto endlabel3040; | |
57207 | } | |
57208 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
57209 | m68k_areg (regs, dstreg) = dsta; | |
57210 | { refill_prefetch (m68k_getpc(), 2); | |
57211 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
57212 | { int flgs = ((int32_t)(src)) < 0; | |
57213 | int flgo = ((int32_t)(dst)) < 0; | |
57214 | int flgn = ((int32_t)(newv)) < 0; | |
57215 | SET_ZFLG (((int32_t)(newv)) == 0); | |
57216 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
57217 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
57218 | COPY_CARRY; | |
57219 | SET_NFLG (flgn != 0); | |
57220 | m68k_incpc(2); | |
57221 | fill_prefetch_2 (); | |
57222 | m68k_write_memory_32(dsta,newv); | |
57223 | }}}}}}}}endlabel3040: ; | |
57224 | return 22; | |
57225 | } | |
57226 | unsigned long CPUFUNC(op_d1a8_5)(uint32_t opcode) /* ADD */ | |
57227 | { | |
57228 | uint32_t srcreg = ((opcode >> 9) & 7); | |
57229 | uint32_t dstreg = opcode & 7; | |
57230 | OpcodeFamily = 11; CurrentInstrCycles = 24; | |
57231 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
57232 | { uint32_t dsta = m68k_areg(regs, dstreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
57233 | if ((dsta & 1) != 0) { | |
57234 | last_fault_for_exception_3 = dsta; | |
57235 | last_op_for_exception_3 = opcode; | |
57236 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
57237 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
57238 | goto endlabel3041; | |
57239 | } | |
57240 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
57241 | { refill_prefetch (m68k_getpc(), 2); | |
57242 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
57243 | { int flgs = ((int32_t)(src)) < 0; | |
57244 | int flgo = ((int32_t)(dst)) < 0; | |
57245 | int flgn = ((int32_t)(newv)) < 0; | |
57246 | SET_ZFLG (((int32_t)(newv)) == 0); | |
57247 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
57248 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
57249 | COPY_CARRY; | |
57250 | SET_NFLG (flgn != 0); | |
57251 | m68k_incpc(4); | |
57252 | fill_prefetch_0 (); | |
57253 | m68k_write_memory_32(dsta,newv); | |
57254 | }}}}}}}}endlabel3041: ; | |
57255 | return 24; | |
57256 | } | |
57257 | unsigned long CPUFUNC(op_d1b0_5)(uint32_t opcode) /* ADD */ | |
57258 | { | |
57259 | uint32_t srcreg = ((opcode >> 9) & 7); | |
57260 | uint32_t dstreg = opcode & 7; | |
57261 | OpcodeFamily = 11; CurrentInstrCycles = 26; | |
57262 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
57263 | { uint32_t dsta = get_disp_ea_000(m68k_areg(regs, dstreg), get_iword_prefetch(2)); | |
57264 | BusCyclePenalty += 2; | |
57265 | if ((dsta & 1) != 0) { | |
57266 | last_fault_for_exception_3 = dsta; | |
57267 | last_op_for_exception_3 = opcode; | |
57268 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
57269 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
57270 | goto endlabel3042; | |
57271 | } | |
57272 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
57273 | { refill_prefetch (m68k_getpc(), 2); | |
57274 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
57275 | { int flgs = ((int32_t)(src)) < 0; | |
57276 | int flgo = ((int32_t)(dst)) < 0; | |
57277 | int flgn = ((int32_t)(newv)) < 0; | |
57278 | SET_ZFLG (((int32_t)(newv)) == 0); | |
57279 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
57280 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
57281 | COPY_CARRY; | |
57282 | SET_NFLG (flgn != 0); | |
57283 | m68k_incpc(4); | |
57284 | fill_prefetch_0 (); | |
57285 | m68k_write_memory_32(dsta,newv); | |
57286 | }}}}}}}}endlabel3042: ; | |
57287 | return 26; | |
57288 | } | |
57289 | unsigned long CPUFUNC(op_d1b8_5)(uint32_t opcode) /* ADD */ | |
57290 | { | |
57291 | uint32_t srcreg = ((opcode >> 9) & 7); | |
57292 | OpcodeFamily = 11; CurrentInstrCycles = 24; | |
57293 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
57294 | { uint32_t dsta = (int32_t)(int16_t)get_iword_prefetch(2); | |
57295 | if ((dsta & 1) != 0) { | |
57296 | last_fault_for_exception_3 = dsta; | |
57297 | last_op_for_exception_3 = opcode; | |
57298 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
57299 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
57300 | goto endlabel3043; | |
57301 | } | |
57302 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
57303 | { refill_prefetch (m68k_getpc(), 2); | |
57304 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
57305 | { int flgs = ((int32_t)(src)) < 0; | |
57306 | int flgo = ((int32_t)(dst)) < 0; | |
57307 | int flgn = ((int32_t)(newv)) < 0; | |
57308 | SET_ZFLG (((int32_t)(newv)) == 0); | |
57309 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
57310 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
57311 | COPY_CARRY; | |
57312 | SET_NFLG (flgn != 0); | |
57313 | m68k_incpc(4); | |
57314 | fill_prefetch_0 (); | |
57315 | m68k_write_memory_32(dsta,newv); | |
57316 | }}}}}}}}endlabel3043: ; | |
57317 | return 24; | |
57318 | } | |
57319 | unsigned long CPUFUNC(op_d1b9_5)(uint32_t opcode) /* ADD */ | |
57320 | { | |
57321 | uint32_t srcreg = ((opcode >> 9) & 7); | |
57322 | OpcodeFamily = 11; CurrentInstrCycles = 28; | |
57323 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
57324 | { uint32_t dsta = get_ilong_prefetch(2); | |
57325 | if ((dsta & 1) != 0) { | |
57326 | last_fault_for_exception_3 = dsta; | |
57327 | last_op_for_exception_3 = opcode; | |
57328 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
57329 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
57330 | goto endlabel3044; | |
57331 | } | |
57332 | {{ int32_t dst = m68k_read_memory_32(dsta); | |
57333 | { refill_prefetch (m68k_getpc(), 2); | |
57334 | {uint32_t newv = ((int32_t)(dst)) + ((int32_t)(src)); | |
57335 | { int flgs = ((int32_t)(src)) < 0; | |
57336 | int flgo = ((int32_t)(dst)) < 0; | |
57337 | int flgn = ((int32_t)(newv)) < 0; | |
57338 | SET_ZFLG (((int32_t)(newv)) == 0); | |
57339 | SET_VFLG ((flgs ^ flgn) & (flgo ^ flgn)); | |
57340 | SET_CFLG (((uint32_t)(~dst)) < ((uint32_t)(src))); | |
57341 | COPY_CARRY; | |
57342 | SET_NFLG (flgn != 0); | |
57343 | m68k_incpc(6); | |
57344 | fill_prefetch_0 (); | |
57345 | m68k_write_memory_32(dsta,newv); | |
57346 | }}}}}}}}endlabel3044: ; | |
57347 | return 28; | |
57348 | } | |
57349 | unsigned long CPUFUNC(op_d1c0_5)(uint32_t opcode) /* ADDA */ | |
57350 | { | |
57351 | uint32_t srcreg = (opcode & 7); | |
57352 | uint32_t dstreg = (opcode >> 9) & 7; | |
57353 | OpcodeFamily = 12; CurrentInstrCycles = 8; | |
57354 | {{ int32_t src = m68k_dreg(regs, srcreg); | |
57355 | { int32_t dst = m68k_areg(regs, dstreg); | |
57356 | { uint32_t newv = dst + src; | |
57357 | m68k_areg(regs, dstreg) = (newv); | |
57358 | }}}}m68k_incpc(2); | |
57359 | fill_prefetch_2 (); | |
57360 | return 8; | |
57361 | } | |
57362 | unsigned long CPUFUNC(op_d1c8_5)(uint32_t opcode) /* ADDA */ | |
57363 | { | |
57364 | uint32_t srcreg = (opcode & 7); | |
57365 | uint32_t dstreg = (opcode >> 9) & 7; | |
57366 | OpcodeFamily = 12; CurrentInstrCycles = 8; | |
57367 | {{ int32_t src = m68k_areg(regs, srcreg); | |
57368 | { int32_t dst = m68k_areg(regs, dstreg); | |
57369 | { uint32_t newv = dst + src; | |
57370 | m68k_areg(regs, dstreg) = (newv); | |
57371 | }}}}m68k_incpc(2); | |
57372 | fill_prefetch_2 (); | |
57373 | return 8; | |
57374 | } | |
57375 | unsigned long CPUFUNC(op_d1d0_5)(uint32_t opcode) /* ADDA */ | |
57376 | { | |
57377 | uint32_t srcreg = (opcode & 7); | |
57378 | uint32_t dstreg = (opcode >> 9) & 7; | |
57379 | OpcodeFamily = 12; CurrentInstrCycles = 14; | |
57380 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
57381 | if ((srca & 1) != 0) { | |
57382 | last_fault_for_exception_3 = srca; | |
57383 | last_op_for_exception_3 = opcode; | |
57384 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
57385 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
57386 | goto endlabel3047; | |
57387 | } | |
57388 | {{ int32_t src = m68k_read_memory_32(srca); | |
57389 | { int32_t dst = m68k_areg(regs, dstreg); | |
57390 | { uint32_t newv = dst + src; | |
57391 | m68k_areg(regs, dstreg) = (newv); | |
57392 | }}}}}}m68k_incpc(2); | |
57393 | fill_prefetch_2 (); | |
57394 | endlabel3047: ; | |
57395 | return 14; | |
57396 | } | |
57397 | #endif | |
57398 | ||
57399 | #ifdef PART_8 | |
57400 | unsigned long CPUFUNC(op_d1d8_5)(uint32_t opcode) /* ADDA */ | |
57401 | { | |
57402 | uint32_t srcreg = (opcode & 7); | |
57403 | uint32_t dstreg = (opcode >> 9) & 7; | |
57404 | OpcodeFamily = 12; CurrentInstrCycles = 14; | |
57405 | {{ uint32_t srca = m68k_areg(regs, srcreg); | |
57406 | if ((srca & 1) != 0) { | |
57407 | last_fault_for_exception_3 = srca; | |
57408 | last_op_for_exception_3 = opcode; | |
57409 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
57410 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
57411 | goto endlabel3048; | |
57412 | } | |
57413 | {{ int32_t src = m68k_read_memory_32(srca); | |
57414 | m68k_areg(regs, srcreg) += 4; | |
57415 | { int32_t dst = m68k_areg(regs, dstreg); | |
57416 | { uint32_t newv = dst + src; | |
57417 | m68k_areg(regs, dstreg) = (newv); | |
57418 | }}}}}}m68k_incpc(2); | |
57419 | fill_prefetch_2 (); | |
57420 | endlabel3048: ; | |
57421 | return 14; | |
57422 | } | |
57423 | unsigned long CPUFUNC(op_d1e0_5)(uint32_t opcode) /* ADDA */ | |
57424 | { | |
57425 | uint32_t srcreg = (opcode & 7); | |
57426 | uint32_t dstreg = (opcode >> 9) & 7; | |
57427 | OpcodeFamily = 12; CurrentInstrCycles = 16; | |
57428 | {{ uint32_t srca = m68k_areg(regs, srcreg) - 4; | |
57429 | if ((srca & 1) != 0) { | |
57430 | last_fault_for_exception_3 = srca; | |
57431 | last_op_for_exception_3 = opcode; | |
57432 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
57433 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
57434 | goto endlabel3049; | |
57435 | } | |
57436 | {{ int32_t src = m68k_read_memory_32(srca); | |
57437 | m68k_areg (regs, srcreg) = srca; | |
57438 | { int32_t dst = m68k_areg(regs, dstreg); | |
57439 | { uint32_t newv = dst + src; | |
57440 | m68k_areg(regs, dstreg) = (newv); | |
57441 | }}}}}}m68k_incpc(2); | |
57442 | fill_prefetch_2 (); | |
57443 | endlabel3049: ; | |
57444 | return 16; | |
57445 | } | |
57446 | unsigned long CPUFUNC(op_d1e8_5)(uint32_t opcode) /* ADDA */ | |
57447 | { | |
57448 | uint32_t srcreg = (opcode & 7); | |
57449 | uint32_t dstreg = (opcode >> 9) & 7; | |
57450 | OpcodeFamily = 12; CurrentInstrCycles = 18; | |
57451 | {{ uint32_t srca = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
57452 | if ((srca & 1) != 0) { | |
57453 | last_fault_for_exception_3 = srca; | |
57454 | last_op_for_exception_3 = opcode; | |
57455 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
57456 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
57457 | goto endlabel3050; | |
57458 | } | |
57459 | {{ int32_t src = m68k_read_memory_32(srca); | |
57460 | { int32_t dst = m68k_areg(regs, dstreg); | |
57461 | { uint32_t newv = dst + src; | |
57462 | m68k_areg(regs, dstreg) = (newv); | |
57463 | }}}}}}m68k_incpc(4); | |
57464 | fill_prefetch_0 (); | |
57465 | endlabel3050: ; | |
57466 | return 18; | |
57467 | } | |
57468 | unsigned long CPUFUNC(op_d1f0_5)(uint32_t opcode) /* ADDA */ | |
57469 | { | |
57470 | uint32_t srcreg = (opcode & 7); | |
57471 | uint32_t dstreg = (opcode >> 9) & 7; | |
57472 | OpcodeFamily = 12; CurrentInstrCycles = 20; | |
57473 | {{ uint32_t srca = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
57474 | BusCyclePenalty += 2; | |
57475 | if ((srca & 1) != 0) { | |
57476 | last_fault_for_exception_3 = srca; | |
57477 | last_op_for_exception_3 = opcode; | |
57478 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
57479 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
57480 | goto endlabel3051; | |
57481 | } | |
57482 | {{ int32_t src = m68k_read_memory_32(srca); | |
57483 | { int32_t dst = m68k_areg(regs, dstreg); | |
57484 | { uint32_t newv = dst + src; | |
57485 | m68k_areg(regs, dstreg) = (newv); | |
57486 | }}}}}}m68k_incpc(4); | |
57487 | fill_prefetch_0 (); | |
57488 | endlabel3051: ; | |
57489 | return 20; | |
57490 | } | |
57491 | unsigned long CPUFUNC(op_d1f8_5)(uint32_t opcode) /* ADDA */ | |
57492 | { | |
57493 | uint32_t dstreg = (opcode >> 9) & 7; | |
57494 | OpcodeFamily = 12; CurrentInstrCycles = 18; | |
57495 | {{ uint32_t srca = (int32_t)(int16_t)get_iword_prefetch(2); | |
57496 | if ((srca & 1) != 0) { | |
57497 | last_fault_for_exception_3 = srca; | |
57498 | last_op_for_exception_3 = opcode; | |
57499 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
57500 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
57501 | goto endlabel3052; | |
57502 | } | |
57503 | {{ int32_t src = m68k_read_memory_32(srca); | |
57504 | { int32_t dst = m68k_areg(regs, dstreg); | |
57505 | { uint32_t newv = dst + src; | |
57506 | m68k_areg(regs, dstreg) = (newv); | |
57507 | }}}}}}m68k_incpc(4); | |
57508 | fill_prefetch_0 (); | |
57509 | endlabel3052: ; | |
57510 | return 18; | |
57511 | } | |
57512 | unsigned long CPUFUNC(op_d1f9_5)(uint32_t opcode) /* ADDA */ | |
57513 | { | |
57514 | uint32_t dstreg = (opcode >> 9) & 7; | |
57515 | OpcodeFamily = 12; CurrentInstrCycles = 22; | |
57516 | {{ uint32_t srca = get_ilong_prefetch(2); | |
57517 | if ((srca & 1) != 0) { | |
57518 | last_fault_for_exception_3 = srca; | |
57519 | last_op_for_exception_3 = opcode; | |
57520 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
57521 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
57522 | goto endlabel3053; | |
57523 | } | |
57524 | {{ int32_t src = m68k_read_memory_32(srca); | |
57525 | { int32_t dst = m68k_areg(regs, dstreg); | |
57526 | { uint32_t newv = dst + src; | |
57527 | m68k_areg(regs, dstreg) = (newv); | |
57528 | }}}}}}m68k_incpc(6); | |
57529 | fill_prefetch_0 (); | |
57530 | endlabel3053: ; | |
57531 | return 22; | |
57532 | } | |
57533 | unsigned long CPUFUNC(op_d1fa_5)(uint32_t opcode) /* ADDA */ | |
57534 | { | |
57535 | uint32_t dstreg = (opcode >> 9) & 7; | |
57536 | OpcodeFamily = 12; CurrentInstrCycles = 18; | |
57537 | {{ uint32_t srca = m68k_getpc () + 2; | |
57538 | srca += (int32_t)(int16_t)get_iword_prefetch(2); | |
57539 | if ((srca & 1) != 0) { | |
57540 | last_fault_for_exception_3 = srca; | |
57541 | last_op_for_exception_3 = opcode; | |
57542 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
57543 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
57544 | goto endlabel3054; | |
57545 | } | |
57546 | {{ int32_t src = m68k_read_memory_32(srca); | |
57547 | { int32_t dst = m68k_areg(regs, dstreg); | |
57548 | { uint32_t newv = dst + src; | |
57549 | m68k_areg(regs, dstreg) = (newv); | |
57550 | }}}}}}m68k_incpc(4); | |
57551 | fill_prefetch_0 (); | |
57552 | endlabel3054: ; | |
57553 | return 18; | |
57554 | } | |
57555 | unsigned long CPUFUNC(op_d1fb_5)(uint32_t opcode) /* ADDA */ | |
57556 | { | |
57557 | uint32_t dstreg = (opcode >> 9) & 7; | |
57558 | OpcodeFamily = 12; CurrentInstrCycles = 20; | |
57559 | {{ uint32_t tmppc = m68k_getpc() + 2; | |
57560 | uint32_t srca = get_disp_ea_000(tmppc, get_iword_prefetch(2)); | |
57561 | BusCyclePenalty += 2; | |
57562 | if ((srca & 1) != 0) { | |
57563 | last_fault_for_exception_3 = srca; | |
57564 | last_op_for_exception_3 = opcode; | |
57565 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
57566 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
57567 | goto endlabel3055; | |
57568 | } | |
57569 | {{ int32_t src = m68k_read_memory_32(srca); | |
57570 | { int32_t dst = m68k_areg(regs, dstreg); | |
57571 | { uint32_t newv = dst + src; | |
57572 | m68k_areg(regs, dstreg) = (newv); | |
57573 | }}}}}}m68k_incpc(4); | |
57574 | fill_prefetch_0 (); | |
57575 | endlabel3055: ; | |
57576 | return 20; | |
57577 | } | |
57578 | unsigned long CPUFUNC(op_d1fc_5)(uint32_t opcode) /* ADDA */ | |
57579 | { | |
57580 | uint32_t dstreg = (opcode >> 9) & 7; | |
57581 | OpcodeFamily = 12; CurrentInstrCycles = 16; | |
57582 | {{ int32_t src = get_ilong_prefetch(2); | |
57583 | { int32_t dst = m68k_areg(regs, dstreg); | |
57584 | { uint32_t newv = dst + src; | |
57585 | m68k_areg(regs, dstreg) = (newv); | |
57586 | }}}}m68k_incpc(6); | |
57587 | fill_prefetch_0 (); | |
57588 | return 16; | |
57589 | } | |
57590 | unsigned long CPUFUNC(op_e000_5)(uint32_t opcode) /* ASR */ | |
57591 | { | |
57592 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
57593 | uint32_t dstreg = opcode & 7; | |
57594 | unsigned int retcycles = 0; | |
57595 | OpcodeFamily = 64; CurrentInstrCycles = 4; | |
57596 | {{ uint32_t cnt = srcreg; | |
57597 | { int8_t data = m68k_dreg(regs, dstreg); | |
57598 | { uint32_t val = (uint8_t)data; | |
57599 | uint32_t sign = (0x80 & val) >> 7; | |
57600 | cnt &= 63; | |
57601 | retcycles = cnt; | |
57602 | CLEAR_CZNV; | |
57603 | if (cnt >= 8) { | |
57604 | val = 0xff & (uint32_t)-sign; | |
57605 | SET_CFLG (sign); | |
57606 | COPY_CARRY; | |
57607 | } else { | |
57608 | val >>= cnt - 1; | |
57609 | SET_CFLG (val & 1); | |
57610 | COPY_CARRY; | |
57611 | val >>= 1; | |
57612 | val |= (0xff << (8 - cnt)) & (uint32_t)-sign; | |
57613 | val &= 0xff; | |
57614 | } | |
57615 | SET_ZFLG (((int8_t)(val)) == 0); | |
57616 | SET_NFLG (((int8_t)(val)) < 0); | |
57617 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); | |
57618 | }}}}m68k_incpc(2); | |
57619 | fill_prefetch_2 (); | |
57620 | return (6+retcycles*2); | |
57621 | } | |
57622 | unsigned long CPUFUNC(op_e008_5)(uint32_t opcode) /* LSR */ | |
57623 | { | |
57624 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
57625 | uint32_t dstreg = opcode & 7; | |
57626 | unsigned int retcycles = 0; | |
57627 | OpcodeFamily = 66; CurrentInstrCycles = 4; | |
57628 | {{ uint32_t cnt = srcreg; | |
57629 | { int8_t data = m68k_dreg(regs, dstreg); | |
57630 | { uint32_t val = (uint8_t)data; | |
57631 | cnt &= 63; | |
57632 | retcycles = cnt; | |
57633 | CLEAR_CZNV; | |
57634 | if (cnt >= 8) { | |
57635 | SET_CFLG ((cnt == 8) & (val >> 7)); | |
57636 | COPY_CARRY; | |
57637 | val = 0; | |
57638 | } else { | |
57639 | val >>= cnt - 1; | |
57640 | SET_CFLG (val & 1); | |
57641 | COPY_CARRY; | |
57642 | val >>= 1; | |
57643 | } | |
57644 | SET_ZFLG (((int8_t)(val)) == 0); | |
57645 | SET_NFLG (((int8_t)(val)) < 0); | |
57646 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); | |
57647 | }}}}m68k_incpc(2); | |
57648 | fill_prefetch_2 (); | |
57649 | return (6+retcycles*2); | |
57650 | } | |
57651 | unsigned long CPUFUNC(op_e010_5)(uint32_t opcode) /* ROXR */ | |
57652 | { | |
57653 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
57654 | uint32_t dstreg = opcode & 7; | |
57655 | unsigned int retcycles = 0; | |
57656 | OpcodeFamily = 71; CurrentInstrCycles = 4; | |
57657 | {{ uint32_t cnt = srcreg; | |
57658 | { int8_t data = m68k_dreg(regs, dstreg); | |
57659 | { uint32_t val = (uint8_t)data; | |
57660 | cnt &= 63; | |
57661 | retcycles = cnt; | |
57662 | CLEAR_CZNV; | |
57663 | { cnt--; | |
57664 | { | |
57665 | uint32_t carry; | |
57666 | uint32_t hival = (val << 1) | GET_XFLG; | |
57667 | hival <<= (7 - cnt); | |
57668 | val >>= cnt; | |
57669 | carry = val & 1; | |
57670 | val >>= 1; | |
57671 | val |= hival; | |
57672 | SET_XFLG (carry); | |
57673 | val &= 0xff; | |
57674 | } } | |
57675 | SET_CFLG (GET_XFLG); | |
57676 | SET_ZFLG (((int8_t)(val)) == 0); | |
57677 | SET_NFLG (((int8_t)(val)) < 0); | |
57678 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); | |
57679 | }}}}m68k_incpc(2); | |
57680 | fill_prefetch_2 (); | |
57681 | return (6+retcycles*2); | |
57682 | } | |
57683 | unsigned long CPUFUNC(op_e018_5)(uint32_t opcode) /* ROR */ | |
57684 | { | |
57685 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
57686 | uint32_t dstreg = opcode & 7; | |
57687 | unsigned int retcycles = 0; | |
57688 | OpcodeFamily = 69; CurrentInstrCycles = 4; | |
57689 | {{ uint32_t cnt = srcreg; | |
57690 | { int8_t data = m68k_dreg(regs, dstreg); | |
57691 | { uint32_t val = (uint8_t)data; | |
57692 | cnt &= 63; | |
57693 | retcycles = cnt; | |
57694 | CLEAR_CZNV; | |
57695 | { uint32_t hival; | |
57696 | cnt &= 7; | |
57697 | hival = val << (8 - cnt); | |
57698 | val >>= cnt; | |
57699 | val |= hival; | |
57700 | val &= 0xff; | |
57701 | SET_CFLG ((val & 0x80) >> 7); | |
57702 | } | |
57703 | SET_ZFLG (((int8_t)(val)) == 0); | |
57704 | SET_NFLG (((int8_t)(val)) < 0); | |
57705 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); | |
57706 | }}}}m68k_incpc(2); | |
57707 | fill_prefetch_2 (); | |
57708 | return (6+retcycles*2); | |
57709 | } | |
57710 | unsigned long CPUFUNC(op_e020_5)(uint32_t opcode) /* ASR */ | |
57711 | { | |
57712 | uint32_t srcreg = ((opcode >> 9) & 7); | |
57713 | uint32_t dstreg = opcode & 7; | |
57714 | unsigned int retcycles = 0; | |
57715 | OpcodeFamily = 64; CurrentInstrCycles = 4; | |
57716 | {{ int8_t cnt = m68k_dreg(regs, srcreg); | |
57717 | { int8_t data = m68k_dreg(regs, dstreg); | |
57718 | { uint32_t val = (uint8_t)data; | |
57719 | uint32_t sign = (0x80 & val) >> 7; | |
57720 | cnt &= 63; | |
57721 | retcycles = cnt; | |
57722 | CLEAR_CZNV; | |
57723 | if (cnt >= 8) { | |
57724 | val = 0xff & (uint32_t)-sign; | |
57725 | SET_CFLG (sign); | |
57726 | COPY_CARRY; | |
57727 | } else if (cnt > 0) { | |
57728 | val >>= cnt - 1; | |
57729 | SET_CFLG (val & 1); | |
57730 | COPY_CARRY; | |
57731 | val >>= 1; | |
57732 | val |= (0xff << (8 - cnt)) & (uint32_t)-sign; | |
57733 | val &= 0xff; | |
57734 | } | |
57735 | SET_ZFLG (((int8_t)(val)) == 0); | |
57736 | SET_NFLG (((int8_t)(val)) < 0); | |
57737 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); | |
57738 | }}}}m68k_incpc(2); | |
57739 | fill_prefetch_2 (); | |
57740 | return (6+retcycles*2); | |
57741 | } | |
57742 | unsigned long CPUFUNC(op_e028_5)(uint32_t opcode) /* LSR */ | |
57743 | { | |
57744 | uint32_t srcreg = ((opcode >> 9) & 7); | |
57745 | uint32_t dstreg = opcode & 7; | |
57746 | unsigned int retcycles = 0; | |
57747 | OpcodeFamily = 66; CurrentInstrCycles = 4; | |
57748 | {{ int8_t cnt = m68k_dreg(regs, srcreg); | |
57749 | { int8_t data = m68k_dreg(regs, dstreg); | |
57750 | { uint32_t val = (uint8_t)data; | |
57751 | cnt &= 63; | |
57752 | retcycles = cnt; | |
57753 | CLEAR_CZNV; | |
57754 | if (cnt >= 8) { | |
57755 | SET_CFLG ((cnt == 8) & (val >> 7)); | |
57756 | COPY_CARRY; | |
57757 | val = 0; | |
57758 | } else if (cnt > 0) { | |
57759 | val >>= cnt - 1; | |
57760 | SET_CFLG (val & 1); | |
57761 | COPY_CARRY; | |
57762 | val >>= 1; | |
57763 | } | |
57764 | SET_ZFLG (((int8_t)(val)) == 0); | |
57765 | SET_NFLG (((int8_t)(val)) < 0); | |
57766 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); | |
57767 | }}}}m68k_incpc(2); | |
57768 | fill_prefetch_2 (); | |
57769 | return (6+retcycles*2); | |
57770 | } | |
57771 | unsigned long CPUFUNC(op_e030_5)(uint32_t opcode) /* ROXR */ | |
57772 | { | |
57773 | uint32_t srcreg = ((opcode >> 9) & 7); | |
57774 | uint32_t dstreg = opcode & 7; | |
57775 | unsigned int retcycles = 0; | |
57776 | OpcodeFamily = 71; CurrentInstrCycles = 4; | |
57777 | {{ int8_t cnt = m68k_dreg(regs, srcreg); | |
57778 | { int8_t data = m68k_dreg(regs, dstreg); | |
57779 | { uint32_t val = (uint8_t)data; | |
57780 | cnt &= 63; | |
57781 | retcycles = cnt; | |
57782 | CLEAR_CZNV; | |
57783 | if (cnt >= 36) cnt -= 36; | |
57784 | if (cnt >= 18) cnt -= 18; | |
57785 | if (cnt >= 9) cnt -= 9; | |
57786 | if (cnt > 0) { | |
57787 | cnt--; | |
57788 | { | |
57789 | uint32_t carry; | |
57790 | uint32_t hival = (val << 1) | GET_XFLG; | |
57791 | hival <<= (7 - cnt); | |
57792 | val >>= cnt; | |
57793 | carry = val & 1; | |
57794 | val >>= 1; | |
57795 | val |= hival; | |
57796 | SET_XFLG (carry); | |
57797 | val &= 0xff; | |
57798 | } } | |
57799 | SET_CFLG (GET_XFLG); | |
57800 | SET_ZFLG (((int8_t)(val)) == 0); | |
57801 | SET_NFLG (((int8_t)(val)) < 0); | |
57802 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); | |
57803 | }}}}m68k_incpc(2); | |
57804 | fill_prefetch_2 (); | |
57805 | return (6+retcycles*2); | |
57806 | } | |
57807 | unsigned long CPUFUNC(op_e038_5)(uint32_t opcode) /* ROR */ | |
57808 | { | |
57809 | uint32_t srcreg = ((opcode >> 9) & 7); | |
57810 | uint32_t dstreg = opcode & 7; | |
57811 | unsigned int retcycles = 0; | |
57812 | OpcodeFamily = 69; CurrentInstrCycles = 4; | |
57813 | {{ int8_t cnt = m68k_dreg(regs, srcreg); | |
57814 | { int8_t data = m68k_dreg(regs, dstreg); | |
57815 | { uint32_t val = (uint8_t)data; | |
57816 | cnt &= 63; | |
57817 | retcycles = cnt; | |
57818 | CLEAR_CZNV; | |
57819 | if (cnt > 0) { uint32_t hival; | |
57820 | cnt &= 7; | |
57821 | hival = val << (8 - cnt); | |
57822 | val >>= cnt; | |
57823 | val |= hival; | |
57824 | val &= 0xff; | |
57825 | SET_CFLG ((val & 0x80) >> 7); | |
57826 | } | |
57827 | SET_ZFLG (((int8_t)(val)) == 0); | |
57828 | SET_NFLG (((int8_t)(val)) < 0); | |
57829 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); | |
57830 | }}}}m68k_incpc(2); | |
57831 | fill_prefetch_2 (); | |
57832 | return (6+retcycles*2); | |
57833 | } | |
57834 | unsigned long CPUFUNC(op_e040_5)(uint32_t opcode) /* ASR */ | |
57835 | { | |
57836 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
57837 | uint32_t dstreg = opcode & 7; | |
57838 | unsigned int retcycles = 0; | |
57839 | OpcodeFamily = 64; CurrentInstrCycles = 4; | |
57840 | {{ uint32_t cnt = srcreg; | |
57841 | { int16_t data = m68k_dreg(regs, dstreg); | |
57842 | { uint32_t val = (uint16_t)data; | |
57843 | uint32_t sign = (0x8000 & val) >> 15; | |
57844 | cnt &= 63; | |
57845 | retcycles = cnt; | |
57846 | CLEAR_CZNV; | |
57847 | if (cnt >= 16) { | |
57848 | val = 0xffff & (uint32_t)-sign; | |
57849 | SET_CFLG (sign); | |
57850 | COPY_CARRY; | |
57851 | } else { | |
57852 | val >>= cnt - 1; | |
57853 | SET_CFLG (val & 1); | |
57854 | COPY_CARRY; | |
57855 | val >>= 1; | |
57856 | val |= (0xffff << (16 - cnt)) & (uint32_t)-sign; | |
57857 | val &= 0xffff; | |
57858 | } | |
57859 | SET_ZFLG (((int16_t)(val)) == 0); | |
57860 | SET_NFLG (((int16_t)(val)) < 0); | |
57861 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); | |
57862 | }}}}m68k_incpc(2); | |
57863 | fill_prefetch_2 (); | |
57864 | return (6+retcycles*2); | |
57865 | } | |
57866 | unsigned long CPUFUNC(op_e048_5)(uint32_t opcode) /* LSR */ | |
57867 | { | |
57868 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
57869 | uint32_t dstreg = opcode & 7; | |
57870 | unsigned int retcycles = 0; | |
57871 | OpcodeFamily = 66; CurrentInstrCycles = 4; | |
57872 | {{ uint32_t cnt = srcreg; | |
57873 | { int16_t data = m68k_dreg(regs, dstreg); | |
57874 | { uint32_t val = (uint16_t)data; | |
57875 | cnt &= 63; | |
57876 | retcycles = cnt; | |
57877 | CLEAR_CZNV; | |
57878 | if (cnt >= 16) { | |
57879 | SET_CFLG ((cnt == 16) & (val >> 15)); | |
57880 | COPY_CARRY; | |
57881 | val = 0; | |
57882 | } else { | |
57883 | val >>= cnt - 1; | |
57884 | SET_CFLG (val & 1); | |
57885 | COPY_CARRY; | |
57886 | val >>= 1; | |
57887 | } | |
57888 | SET_ZFLG (((int16_t)(val)) == 0); | |
57889 | SET_NFLG (((int16_t)(val)) < 0); | |
57890 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); | |
57891 | }}}}m68k_incpc(2); | |
57892 | fill_prefetch_2 (); | |
57893 | return (6+retcycles*2); | |
57894 | } | |
57895 | unsigned long CPUFUNC(op_e050_5)(uint32_t opcode) /* ROXR */ | |
57896 | { | |
57897 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
57898 | uint32_t dstreg = opcode & 7; | |
57899 | unsigned int retcycles = 0; | |
57900 | OpcodeFamily = 71; CurrentInstrCycles = 4; | |
57901 | {{ uint32_t cnt = srcreg; | |
57902 | { int16_t data = m68k_dreg(regs, dstreg); | |
57903 | { uint32_t val = (uint16_t)data; | |
57904 | cnt &= 63; | |
57905 | retcycles = cnt; | |
57906 | CLEAR_CZNV; | |
57907 | { cnt--; | |
57908 | { | |
57909 | uint32_t carry; | |
57910 | uint32_t hival = (val << 1) | GET_XFLG; | |
57911 | hival <<= (15 - cnt); | |
57912 | val >>= cnt; | |
57913 | carry = val & 1; | |
57914 | val >>= 1; | |
57915 | val |= hival; | |
57916 | SET_XFLG (carry); | |
57917 | val &= 0xffff; | |
57918 | } } | |
57919 | SET_CFLG (GET_XFLG); | |
57920 | SET_ZFLG (((int16_t)(val)) == 0); | |
57921 | SET_NFLG (((int16_t)(val)) < 0); | |
57922 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); | |
57923 | }}}}m68k_incpc(2); | |
57924 | fill_prefetch_2 (); | |
57925 | return (6+retcycles*2); | |
57926 | } | |
57927 | unsigned long CPUFUNC(op_e058_5)(uint32_t opcode) /* ROR */ | |
57928 | { | |
57929 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
57930 | uint32_t dstreg = opcode & 7; | |
57931 | unsigned int retcycles = 0; | |
57932 | OpcodeFamily = 69; CurrentInstrCycles = 4; | |
57933 | {{ uint32_t cnt = srcreg; | |
57934 | { int16_t data = m68k_dreg(regs, dstreg); | |
57935 | { uint32_t val = (uint16_t)data; | |
57936 | cnt &= 63; | |
57937 | retcycles = cnt; | |
57938 | CLEAR_CZNV; | |
57939 | { uint32_t hival; | |
57940 | cnt &= 15; | |
57941 | hival = val << (16 - cnt); | |
57942 | val >>= cnt; | |
57943 | val |= hival; | |
57944 | val &= 0xffff; | |
57945 | SET_CFLG ((val & 0x8000) >> 15); | |
57946 | } | |
57947 | SET_ZFLG (((int16_t)(val)) == 0); | |
57948 | SET_NFLG (((int16_t)(val)) < 0); | |
57949 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); | |
57950 | }}}}m68k_incpc(2); | |
57951 | fill_prefetch_2 (); | |
57952 | return (6+retcycles*2); | |
57953 | } | |
57954 | unsigned long CPUFUNC(op_e060_5)(uint32_t opcode) /* ASR */ | |
57955 | { | |
57956 | uint32_t srcreg = ((opcode >> 9) & 7); | |
57957 | uint32_t dstreg = opcode & 7; | |
57958 | unsigned int retcycles = 0; | |
57959 | OpcodeFamily = 64; CurrentInstrCycles = 4; | |
57960 | {{ int16_t cnt = m68k_dreg(regs, srcreg); | |
57961 | { int16_t data = m68k_dreg(regs, dstreg); | |
57962 | { uint32_t val = (uint16_t)data; | |
57963 | uint32_t sign = (0x8000 & val) >> 15; | |
57964 | cnt &= 63; | |
57965 | retcycles = cnt; | |
57966 | CLEAR_CZNV; | |
57967 | if (cnt >= 16) { | |
57968 | val = 0xffff & (uint32_t)-sign; | |
57969 | SET_CFLG (sign); | |
57970 | COPY_CARRY; | |
57971 | } else if (cnt > 0) { | |
57972 | val >>= cnt - 1; | |
57973 | SET_CFLG (val & 1); | |
57974 | COPY_CARRY; | |
57975 | val >>= 1; | |
57976 | val |= (0xffff << (16 - cnt)) & (uint32_t)-sign; | |
57977 | val &= 0xffff; | |
57978 | } | |
57979 | SET_ZFLG (((int16_t)(val)) == 0); | |
57980 | SET_NFLG (((int16_t)(val)) < 0); | |
57981 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); | |
57982 | }}}}m68k_incpc(2); | |
57983 | fill_prefetch_2 (); | |
57984 | return (6+retcycles*2); | |
57985 | } | |
57986 | unsigned long CPUFUNC(op_e068_5)(uint32_t opcode) /* LSR */ | |
57987 | { | |
57988 | uint32_t srcreg = ((opcode >> 9) & 7); | |
57989 | uint32_t dstreg = opcode & 7; | |
57990 | unsigned int retcycles = 0; | |
57991 | OpcodeFamily = 66; CurrentInstrCycles = 4; | |
57992 | {{ int16_t cnt = m68k_dreg(regs, srcreg); | |
57993 | { int16_t data = m68k_dreg(regs, dstreg); | |
57994 | { uint32_t val = (uint16_t)data; | |
57995 | cnt &= 63; | |
57996 | retcycles = cnt; | |
57997 | CLEAR_CZNV; | |
57998 | if (cnt >= 16) { | |
57999 | SET_CFLG ((cnt == 16) & (val >> 15)); | |
58000 | COPY_CARRY; | |
58001 | val = 0; | |
58002 | } else if (cnt > 0) { | |
58003 | val >>= cnt - 1; | |
58004 | SET_CFLG (val & 1); | |
58005 | COPY_CARRY; | |
58006 | val >>= 1; | |
58007 | } | |
58008 | SET_ZFLG (((int16_t)(val)) == 0); | |
58009 | SET_NFLG (((int16_t)(val)) < 0); | |
58010 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); | |
58011 | }}}}m68k_incpc(2); | |
58012 | fill_prefetch_2 (); | |
58013 | return (6+retcycles*2); | |
58014 | } | |
58015 | unsigned long CPUFUNC(op_e070_5)(uint32_t opcode) /* ROXR */ | |
58016 | { | |
58017 | uint32_t srcreg = ((opcode >> 9) & 7); | |
58018 | uint32_t dstreg = opcode & 7; | |
58019 | unsigned int retcycles = 0; | |
58020 | OpcodeFamily = 71; CurrentInstrCycles = 4; | |
58021 | {{ int16_t cnt = m68k_dreg(regs, srcreg); | |
58022 | { int16_t data = m68k_dreg(regs, dstreg); | |
58023 | { uint32_t val = (uint16_t)data; | |
58024 | cnt &= 63; | |
58025 | retcycles = cnt; | |
58026 | CLEAR_CZNV; | |
58027 | if (cnt >= 34) cnt -= 34; | |
58028 | if (cnt >= 17) cnt -= 17; | |
58029 | if (cnt > 0) { | |
58030 | cnt--; | |
58031 | { | |
58032 | uint32_t carry; | |
58033 | uint32_t hival = (val << 1) | GET_XFLG; | |
58034 | hival <<= (15 - cnt); | |
58035 | val >>= cnt; | |
58036 | carry = val & 1; | |
58037 | val >>= 1; | |
58038 | val |= hival; | |
58039 | SET_XFLG (carry); | |
58040 | val &= 0xffff; | |
58041 | } } | |
58042 | SET_CFLG (GET_XFLG); | |
58043 | SET_ZFLG (((int16_t)(val)) == 0); | |
58044 | SET_NFLG (((int16_t)(val)) < 0); | |
58045 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); | |
58046 | }}}}m68k_incpc(2); | |
58047 | fill_prefetch_2 (); | |
58048 | return (6+retcycles*2); | |
58049 | } | |
58050 | unsigned long CPUFUNC(op_e078_5)(uint32_t opcode) /* ROR */ | |
58051 | { | |
58052 | uint32_t srcreg = ((opcode >> 9) & 7); | |
58053 | uint32_t dstreg = opcode & 7; | |
58054 | unsigned int retcycles = 0; | |
58055 | OpcodeFamily = 69; CurrentInstrCycles = 4; | |
58056 | {{ int16_t cnt = m68k_dreg(regs, srcreg); | |
58057 | { int16_t data = m68k_dreg(regs, dstreg); | |
58058 | { uint32_t val = (uint16_t)data; | |
58059 | cnt &= 63; | |
58060 | retcycles = cnt; | |
58061 | CLEAR_CZNV; | |
58062 | if (cnt > 0) { uint32_t hival; | |
58063 | cnt &= 15; | |
58064 | hival = val << (16 - cnt); | |
58065 | val >>= cnt; | |
58066 | val |= hival; | |
58067 | val &= 0xffff; | |
58068 | SET_CFLG ((val & 0x8000) >> 15); | |
58069 | } | |
58070 | SET_ZFLG (((int16_t)(val)) == 0); | |
58071 | SET_NFLG (((int16_t)(val)) < 0); | |
58072 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); | |
58073 | }}}}m68k_incpc(2); | |
58074 | fill_prefetch_2 (); | |
58075 | return (6+retcycles*2); | |
58076 | } | |
58077 | unsigned long CPUFUNC(op_e080_5)(uint32_t opcode) /* ASR */ | |
58078 | { | |
58079 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
58080 | uint32_t dstreg = opcode & 7; | |
58081 | unsigned int retcycles = 0; | |
58082 | OpcodeFamily = 64; CurrentInstrCycles = 4; | |
58083 | {{ uint32_t cnt = srcreg; | |
58084 | { int32_t data = m68k_dreg(regs, dstreg); | |
58085 | { uint32_t val = data; | |
58086 | uint32_t sign = (0x80000000 & val) >> 31; | |
58087 | cnt &= 63; | |
58088 | retcycles = cnt; | |
58089 | CLEAR_CZNV; | |
58090 | if (cnt >= 32) { | |
58091 | val = 0xffffffff & (uint32_t)-sign; | |
58092 | SET_CFLG (sign); | |
58093 | COPY_CARRY; | |
58094 | } else { | |
58095 | val >>= cnt - 1; | |
58096 | SET_CFLG (val & 1); | |
58097 | COPY_CARRY; | |
58098 | val >>= 1; | |
58099 | val |= (0xffffffff << (32 - cnt)) & (uint32_t)-sign; | |
58100 | val &= 0xffffffff; | |
58101 | } | |
58102 | SET_ZFLG (((int32_t)(val)) == 0); | |
58103 | SET_NFLG (((int32_t)(val)) < 0); | |
58104 | m68k_dreg(regs, dstreg) = (val); | |
58105 | }}}}m68k_incpc(2); | |
58106 | fill_prefetch_2 (); | |
58107 | return (8+retcycles*2); | |
58108 | } | |
58109 | unsigned long CPUFUNC(op_e088_5)(uint32_t opcode) /* LSR */ | |
58110 | { | |
58111 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
58112 | uint32_t dstreg = opcode & 7; | |
58113 | unsigned int retcycles = 0; | |
58114 | OpcodeFamily = 66; CurrentInstrCycles = 4; | |
58115 | {{ uint32_t cnt = srcreg; | |
58116 | { int32_t data = m68k_dreg(regs, dstreg); | |
58117 | { uint32_t val = data; | |
58118 | cnt &= 63; | |
58119 | retcycles = cnt; | |
58120 | CLEAR_CZNV; | |
58121 | if (cnt >= 32) { | |
58122 | SET_CFLG ((cnt == 32) & (val >> 31)); | |
58123 | COPY_CARRY; | |
58124 | val = 0; | |
58125 | } else { | |
58126 | val >>= cnt - 1; | |
58127 | SET_CFLG (val & 1); | |
58128 | COPY_CARRY; | |
58129 | val >>= 1; | |
58130 | } | |
58131 | SET_ZFLG (((int32_t)(val)) == 0); | |
58132 | SET_NFLG (((int32_t)(val)) < 0); | |
58133 | m68k_dreg(regs, dstreg) = (val); | |
58134 | }}}}m68k_incpc(2); | |
58135 | fill_prefetch_2 (); | |
58136 | return (8+retcycles*2); | |
58137 | } | |
58138 | unsigned long CPUFUNC(op_e090_5)(uint32_t opcode) /* ROXR */ | |
58139 | { | |
58140 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
58141 | uint32_t dstreg = opcode & 7; | |
58142 | unsigned int retcycles = 0; | |
58143 | OpcodeFamily = 71; CurrentInstrCycles = 4; | |
58144 | {{ uint32_t cnt = srcreg; | |
58145 | { int32_t data = m68k_dreg(regs, dstreg); | |
58146 | { uint32_t val = data; | |
58147 | cnt &= 63; | |
58148 | retcycles = cnt; | |
58149 | CLEAR_CZNV; | |
58150 | { cnt--; | |
58151 | { | |
58152 | uint32_t carry; | |
58153 | uint32_t hival = (val << 1) | GET_XFLG; | |
58154 | hival <<= (31 - cnt); | |
58155 | val >>= cnt; | |
58156 | carry = val & 1; | |
58157 | val >>= 1; | |
58158 | val |= hival; | |
58159 | SET_XFLG (carry); | |
58160 | val &= 0xffffffff; | |
58161 | } } | |
58162 | SET_CFLG (GET_XFLG); | |
58163 | SET_ZFLG (((int32_t)(val)) == 0); | |
58164 | SET_NFLG (((int32_t)(val)) < 0); | |
58165 | m68k_dreg(regs, dstreg) = (val); | |
58166 | }}}}m68k_incpc(2); | |
58167 | fill_prefetch_2 (); | |
58168 | return (8+retcycles*2); | |
58169 | } | |
58170 | unsigned long CPUFUNC(op_e098_5)(uint32_t opcode) /* ROR */ | |
58171 | { | |
58172 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
58173 | uint32_t dstreg = opcode & 7; | |
58174 | unsigned int retcycles = 0; | |
58175 | OpcodeFamily = 69; CurrentInstrCycles = 4; | |
58176 | {{ uint32_t cnt = srcreg; | |
58177 | { int32_t data = m68k_dreg(regs, dstreg); | |
58178 | { uint32_t val = data; | |
58179 | cnt &= 63; | |
58180 | retcycles = cnt; | |
58181 | CLEAR_CZNV; | |
58182 | { uint32_t hival; | |
58183 | cnt &= 31; | |
58184 | hival = val << (32 - cnt); | |
58185 | val >>= cnt; | |
58186 | val |= hival; | |
58187 | val &= 0xffffffff; | |
58188 | SET_CFLG ((val & 0x80000000) >> 31); | |
58189 | } | |
58190 | SET_ZFLG (((int32_t)(val)) == 0); | |
58191 | SET_NFLG (((int32_t)(val)) < 0); | |
58192 | m68k_dreg(regs, dstreg) = (val); | |
58193 | }}}}m68k_incpc(2); | |
58194 | fill_prefetch_2 (); | |
58195 | return (8+retcycles*2); | |
58196 | } | |
58197 | unsigned long CPUFUNC(op_e0a0_5)(uint32_t opcode) /* ASR */ | |
58198 | { | |
58199 | uint32_t srcreg = ((opcode >> 9) & 7); | |
58200 | uint32_t dstreg = opcode & 7; | |
58201 | unsigned int retcycles = 0; | |
58202 | OpcodeFamily = 64; CurrentInstrCycles = 4; | |
58203 | {{ int32_t cnt = m68k_dreg(regs, srcreg); | |
58204 | { int32_t data = m68k_dreg(regs, dstreg); | |
58205 | { uint32_t val = data; | |
58206 | uint32_t sign = (0x80000000 & val) >> 31; | |
58207 | cnt &= 63; | |
58208 | retcycles = cnt; | |
58209 | CLEAR_CZNV; | |
58210 | if (cnt >= 32) { | |
58211 | val = 0xffffffff & (uint32_t)-sign; | |
58212 | SET_CFLG (sign); | |
58213 | COPY_CARRY; | |
58214 | } else if (cnt > 0) { | |
58215 | val >>= cnt - 1; | |
58216 | SET_CFLG (val & 1); | |
58217 | COPY_CARRY; | |
58218 | val >>= 1; | |
58219 | val |= (0xffffffff << (32 - cnt)) & (uint32_t)-sign; | |
58220 | val &= 0xffffffff; | |
58221 | } | |
58222 | SET_ZFLG (((int32_t)(val)) == 0); | |
58223 | SET_NFLG (((int32_t)(val)) < 0); | |
58224 | m68k_dreg(regs, dstreg) = (val); | |
58225 | }}}}m68k_incpc(2); | |
58226 | fill_prefetch_2 (); | |
58227 | return (8+retcycles*2); | |
58228 | } | |
58229 | unsigned long CPUFUNC(op_e0a8_5)(uint32_t opcode) /* LSR */ | |
58230 | { | |
58231 | uint32_t srcreg = ((opcode >> 9) & 7); | |
58232 | uint32_t dstreg = opcode & 7; | |
58233 | unsigned int retcycles = 0; | |
58234 | OpcodeFamily = 66; CurrentInstrCycles = 4; | |
58235 | {{ int32_t cnt = m68k_dreg(regs, srcreg); | |
58236 | { int32_t data = m68k_dreg(regs, dstreg); | |
58237 | { uint32_t val = data; | |
58238 | cnt &= 63; | |
58239 | retcycles = cnt; | |
58240 | CLEAR_CZNV; | |
58241 | if (cnt >= 32) { | |
58242 | SET_CFLG ((cnt == 32) & (val >> 31)); | |
58243 | COPY_CARRY; | |
58244 | val = 0; | |
58245 | } else if (cnt > 0) { | |
58246 | val >>= cnt - 1; | |
58247 | SET_CFLG (val & 1); | |
58248 | COPY_CARRY; | |
58249 | val >>= 1; | |
58250 | } | |
58251 | SET_ZFLG (((int32_t)(val)) == 0); | |
58252 | SET_NFLG (((int32_t)(val)) < 0); | |
58253 | m68k_dreg(regs, dstreg) = (val); | |
58254 | }}}}m68k_incpc(2); | |
58255 | fill_prefetch_2 (); | |
58256 | return (8+retcycles*2); | |
58257 | } | |
58258 | unsigned long CPUFUNC(op_e0b0_5)(uint32_t opcode) /* ROXR */ | |
58259 | { | |
58260 | uint32_t srcreg = ((opcode >> 9) & 7); | |
58261 | uint32_t dstreg = opcode & 7; | |
58262 | unsigned int retcycles = 0; | |
58263 | OpcodeFamily = 71; CurrentInstrCycles = 4; | |
58264 | {{ int32_t cnt = m68k_dreg(regs, srcreg); | |
58265 | { int32_t data = m68k_dreg(regs, dstreg); | |
58266 | { uint32_t val = data; | |
58267 | cnt &= 63; | |
58268 | retcycles = cnt; | |
58269 | CLEAR_CZNV; | |
58270 | if (cnt >= 33) cnt -= 33; | |
58271 | if (cnt > 0) { | |
58272 | cnt--; | |
58273 | { | |
58274 | uint32_t carry; | |
58275 | uint32_t hival = (val << 1) | GET_XFLG; | |
58276 | hival <<= (31 - cnt); | |
58277 | val >>= cnt; | |
58278 | carry = val & 1; | |
58279 | val >>= 1; | |
58280 | val |= hival; | |
58281 | SET_XFLG (carry); | |
58282 | val &= 0xffffffff; | |
58283 | } } | |
58284 | SET_CFLG (GET_XFLG); | |
58285 | SET_ZFLG (((int32_t)(val)) == 0); | |
58286 | SET_NFLG (((int32_t)(val)) < 0); | |
58287 | m68k_dreg(regs, dstreg) = (val); | |
58288 | }}}}m68k_incpc(2); | |
58289 | fill_prefetch_2 (); | |
58290 | return (8+retcycles*2); | |
58291 | } | |
58292 | unsigned long CPUFUNC(op_e0b8_5)(uint32_t opcode) /* ROR */ | |
58293 | { | |
58294 | uint32_t srcreg = ((opcode >> 9) & 7); | |
58295 | uint32_t dstreg = opcode & 7; | |
58296 | unsigned int retcycles = 0; | |
58297 | OpcodeFamily = 69; CurrentInstrCycles = 4; | |
58298 | {{ int32_t cnt = m68k_dreg(regs, srcreg); | |
58299 | { int32_t data = m68k_dreg(regs, dstreg); | |
58300 | { uint32_t val = data; | |
58301 | cnt &= 63; | |
58302 | retcycles = cnt; | |
58303 | CLEAR_CZNV; | |
58304 | if (cnt > 0) { uint32_t hival; | |
58305 | cnt &= 31; | |
58306 | hival = val << (32 - cnt); | |
58307 | val >>= cnt; | |
58308 | val |= hival; | |
58309 | val &= 0xffffffff; | |
58310 | SET_CFLG ((val & 0x80000000) >> 31); | |
58311 | } | |
58312 | SET_ZFLG (((int32_t)(val)) == 0); | |
58313 | SET_NFLG (((int32_t)(val)) < 0); | |
58314 | m68k_dreg(regs, dstreg) = (val); | |
58315 | }}}}m68k_incpc(2); | |
58316 | fill_prefetch_2 (); | |
58317 | return (8+retcycles*2); | |
58318 | } | |
58319 | unsigned long CPUFUNC(op_e0d0_5)(uint32_t opcode) /* ASRW */ | |
58320 | { | |
58321 | uint32_t srcreg = (opcode & 7); | |
58322 | OpcodeFamily = 72; CurrentInstrCycles = 12; | |
58323 | {{ uint32_t dataa = m68k_areg(regs, srcreg); | |
58324 | if ((dataa & 1) != 0) { | |
58325 | last_fault_for_exception_3 = dataa; | |
58326 | last_op_for_exception_3 = opcode; | |
58327 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
58328 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
58329 | goto endlabel3081; | |
58330 | } | |
58331 | {{ int16_t data = m68k_read_memory_16(dataa); | |
58332 | { uint32_t val = (uint16_t)data; | |
58333 | uint32_t sign = 0x8000 & val; | |
58334 | uint32_t cflg = val & 1; | |
58335 | val = (val >> 1) | sign; | |
58336 | CLEAR_CZNV; | |
58337 | SET_ZFLG (((int16_t)(val)) == 0); | |
58338 | SET_NFLG (((int16_t)(val)) < 0); | |
58339 | SET_CFLG (cflg); | |
58340 | COPY_CARRY; | |
58341 | m68k_incpc(2); | |
58342 | fill_prefetch_2 (); | |
58343 | m68k_write_memory_16(dataa,val); | |
58344 | }}}}}endlabel3081: ; | |
58345 | return 12; | |
58346 | } | |
58347 | unsigned long CPUFUNC(op_e0d8_5)(uint32_t opcode) /* ASRW */ | |
58348 | { | |
58349 | uint32_t srcreg = (opcode & 7); | |
58350 | OpcodeFamily = 72; CurrentInstrCycles = 12; | |
58351 | {{ uint32_t dataa = m68k_areg(regs, srcreg); | |
58352 | if ((dataa & 1) != 0) { | |
58353 | last_fault_for_exception_3 = dataa; | |
58354 | last_op_for_exception_3 = opcode; | |
58355 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
58356 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
58357 | goto endlabel3082; | |
58358 | } | |
58359 | {{ int16_t data = m68k_read_memory_16(dataa); | |
58360 | m68k_areg(regs, srcreg) += 2; | |
58361 | { uint32_t val = (uint16_t)data; | |
58362 | uint32_t sign = 0x8000 & val; | |
58363 | uint32_t cflg = val & 1; | |
58364 | val = (val >> 1) | sign; | |
58365 | CLEAR_CZNV; | |
58366 | SET_ZFLG (((int16_t)(val)) == 0); | |
58367 | SET_NFLG (((int16_t)(val)) < 0); | |
58368 | SET_CFLG (cflg); | |
58369 | COPY_CARRY; | |
58370 | m68k_incpc(2); | |
58371 | fill_prefetch_2 (); | |
58372 | m68k_write_memory_16(dataa,val); | |
58373 | }}}}}endlabel3082: ; | |
58374 | return 12; | |
58375 | } | |
58376 | unsigned long CPUFUNC(op_e0e0_5)(uint32_t opcode) /* ASRW */ | |
58377 | { | |
58378 | uint32_t srcreg = (opcode & 7); | |
58379 | OpcodeFamily = 72; CurrentInstrCycles = 14; | |
58380 | {{ uint32_t dataa = m68k_areg(regs, srcreg) - 2; | |
58381 | if ((dataa & 1) != 0) { | |
58382 | last_fault_for_exception_3 = dataa; | |
58383 | last_op_for_exception_3 = opcode; | |
58384 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
58385 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
58386 | goto endlabel3083; | |
58387 | } | |
58388 | {{ int16_t data = m68k_read_memory_16(dataa); | |
58389 | m68k_areg (regs, srcreg) = dataa; | |
58390 | { uint32_t val = (uint16_t)data; | |
58391 | uint32_t sign = 0x8000 & val; | |
58392 | uint32_t cflg = val & 1; | |
58393 | val = (val >> 1) | sign; | |
58394 | CLEAR_CZNV; | |
58395 | SET_ZFLG (((int16_t)(val)) == 0); | |
58396 | SET_NFLG (((int16_t)(val)) < 0); | |
58397 | SET_CFLG (cflg); | |
58398 | COPY_CARRY; | |
58399 | m68k_incpc(2); | |
58400 | fill_prefetch_2 (); | |
58401 | m68k_write_memory_16(dataa,val); | |
58402 | }}}}}endlabel3083: ; | |
58403 | return 14; | |
58404 | } | |
58405 | unsigned long CPUFUNC(op_e0e8_5)(uint32_t opcode) /* ASRW */ | |
58406 | { | |
58407 | uint32_t srcreg = (opcode & 7); | |
58408 | OpcodeFamily = 72; CurrentInstrCycles = 16; | |
58409 | {{ uint32_t dataa = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
58410 | if ((dataa & 1) != 0) { | |
58411 | last_fault_for_exception_3 = dataa; | |
58412 | last_op_for_exception_3 = opcode; | |
58413 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
58414 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
58415 | goto endlabel3084; | |
58416 | } | |
58417 | {{ int16_t data = m68k_read_memory_16(dataa); | |
58418 | { uint32_t val = (uint16_t)data; | |
58419 | uint32_t sign = 0x8000 & val; | |
58420 | uint32_t cflg = val & 1; | |
58421 | val = (val >> 1) | sign; | |
58422 | CLEAR_CZNV; | |
58423 | SET_ZFLG (((int16_t)(val)) == 0); | |
58424 | SET_NFLG (((int16_t)(val)) < 0); | |
58425 | SET_CFLG (cflg); | |
58426 | COPY_CARRY; | |
58427 | m68k_incpc(4); | |
58428 | fill_prefetch_0 (); | |
58429 | m68k_write_memory_16(dataa,val); | |
58430 | }}}}}endlabel3084: ; | |
58431 | return 16; | |
58432 | } | |
58433 | unsigned long CPUFUNC(op_e0f0_5)(uint32_t opcode) /* ASRW */ | |
58434 | { | |
58435 | uint32_t srcreg = (opcode & 7); | |
58436 | OpcodeFamily = 72; CurrentInstrCycles = 18; | |
58437 | {{ uint32_t dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
58438 | BusCyclePenalty += 2; | |
58439 | if ((dataa & 1) != 0) { | |
58440 | last_fault_for_exception_3 = dataa; | |
58441 | last_op_for_exception_3 = opcode; | |
58442 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
58443 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
58444 | goto endlabel3085; | |
58445 | } | |
58446 | {{ int16_t data = m68k_read_memory_16(dataa); | |
58447 | { uint32_t val = (uint16_t)data; | |
58448 | uint32_t sign = 0x8000 & val; | |
58449 | uint32_t cflg = val & 1; | |
58450 | val = (val >> 1) | sign; | |
58451 | CLEAR_CZNV; | |
58452 | SET_ZFLG (((int16_t)(val)) == 0); | |
58453 | SET_NFLG (((int16_t)(val)) < 0); | |
58454 | SET_CFLG (cflg); | |
58455 | COPY_CARRY; | |
58456 | m68k_incpc(4); | |
58457 | fill_prefetch_0 (); | |
58458 | m68k_write_memory_16(dataa,val); | |
58459 | }}}}}endlabel3085: ; | |
58460 | return 18; | |
58461 | } | |
58462 | unsigned long CPUFUNC(op_e0f8_5)(uint32_t opcode) /* ASRW */ | |
58463 | { | |
58464 | OpcodeFamily = 72; CurrentInstrCycles = 16; | |
58465 | {{ uint32_t dataa = (int32_t)(int16_t)get_iword_prefetch(2); | |
58466 | if ((dataa & 1) != 0) { | |
58467 | last_fault_for_exception_3 = dataa; | |
58468 | last_op_for_exception_3 = opcode; | |
58469 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
58470 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
58471 | goto endlabel3086; | |
58472 | } | |
58473 | {{ int16_t data = m68k_read_memory_16(dataa); | |
58474 | { uint32_t val = (uint16_t)data; | |
58475 | uint32_t sign = 0x8000 & val; | |
58476 | uint32_t cflg = val & 1; | |
58477 | val = (val >> 1) | sign; | |
58478 | CLEAR_CZNV; | |
58479 | SET_ZFLG (((int16_t)(val)) == 0); | |
58480 | SET_NFLG (((int16_t)(val)) < 0); | |
58481 | SET_CFLG (cflg); | |
58482 | COPY_CARRY; | |
58483 | m68k_incpc(4); | |
58484 | fill_prefetch_0 (); | |
58485 | m68k_write_memory_16(dataa,val); | |
58486 | }}}}}endlabel3086: ; | |
58487 | return 16; | |
58488 | } | |
58489 | unsigned long CPUFUNC(op_e0f9_5)(uint32_t opcode) /* ASRW */ | |
58490 | { | |
58491 | OpcodeFamily = 72; CurrentInstrCycles = 20; | |
58492 | {{ uint32_t dataa = get_ilong_prefetch(2); | |
58493 | if ((dataa & 1) != 0) { | |
58494 | last_fault_for_exception_3 = dataa; | |
58495 | last_op_for_exception_3 = opcode; | |
58496 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
58497 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
58498 | goto endlabel3087; | |
58499 | } | |
58500 | {{ int16_t data = m68k_read_memory_16(dataa); | |
58501 | { uint32_t val = (uint16_t)data; | |
58502 | uint32_t sign = 0x8000 & val; | |
58503 | uint32_t cflg = val & 1; | |
58504 | val = (val >> 1) | sign; | |
58505 | CLEAR_CZNV; | |
58506 | SET_ZFLG (((int16_t)(val)) == 0); | |
58507 | SET_NFLG (((int16_t)(val)) < 0); | |
58508 | SET_CFLG (cflg); | |
58509 | COPY_CARRY; | |
58510 | m68k_incpc(6); | |
58511 | fill_prefetch_0 (); | |
58512 | m68k_write_memory_16(dataa,val); | |
58513 | }}}}}endlabel3087: ; | |
58514 | return 20; | |
58515 | } | |
58516 | unsigned long CPUFUNC(op_e100_5)(uint32_t opcode) /* ASL */ | |
58517 | { | |
58518 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
58519 | uint32_t dstreg = opcode & 7; | |
58520 | unsigned int retcycles = 0; | |
58521 | OpcodeFamily = 65; CurrentInstrCycles = 4; | |
58522 | {{ uint32_t cnt = srcreg; | |
58523 | { int8_t data = m68k_dreg(regs, dstreg); | |
58524 | { uint32_t val = (uint8_t)data; | |
58525 | cnt &= 63; | |
58526 | retcycles = cnt; | |
58527 | CLEAR_CZNV; | |
58528 | if (cnt >= 8) { | |
58529 | SET_VFLG (val != 0); | |
58530 | SET_CFLG (cnt == 8 ? val & 1 : 0); | |
58531 | COPY_CARRY; | |
58532 | val = 0; | |
58533 | } else { | |
58534 | uint32_t mask = (0xff << (7 - cnt)) & 0xff; | |
58535 | SET_VFLG ((val & mask) != mask && (val & mask) != 0); | |
58536 | val <<= cnt - 1; | |
58537 | SET_CFLG ((val & 0x80) >> 7); | |
58538 | COPY_CARRY; | |
58539 | val <<= 1; | |
58540 | val &= 0xff; | |
58541 | } | |
58542 | SET_ZFLG (((int8_t)(val)) == 0); | |
58543 | SET_NFLG (((int8_t)(val)) < 0); | |
58544 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); | |
58545 | }}}}m68k_incpc(2); | |
58546 | fill_prefetch_2 (); | |
58547 | return (6+retcycles*2); | |
58548 | } | |
58549 | unsigned long CPUFUNC(op_e108_5)(uint32_t opcode) /* LSL */ | |
58550 | { | |
58551 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
58552 | uint32_t dstreg = opcode & 7; | |
58553 | unsigned int retcycles = 0; | |
58554 | OpcodeFamily = 67; CurrentInstrCycles = 4; | |
58555 | {{ uint32_t cnt = srcreg; | |
58556 | { int8_t data = m68k_dreg(regs, dstreg); | |
58557 | { uint32_t val = (uint8_t)data; | |
58558 | cnt &= 63; | |
58559 | retcycles = cnt; | |
58560 | CLEAR_CZNV; | |
58561 | if (cnt >= 8) { | |
58562 | SET_CFLG (cnt == 8 ? val & 1 : 0); | |
58563 | COPY_CARRY; | |
58564 | val = 0; | |
58565 | } else { | |
58566 | val <<= (cnt - 1); | |
58567 | SET_CFLG ((val & 0x80) >> 7); | |
58568 | COPY_CARRY; | |
58569 | val <<= 1; | |
58570 | val &= 0xff; | |
58571 | } | |
58572 | SET_ZFLG (((int8_t)(val)) == 0); | |
58573 | SET_NFLG (((int8_t)(val)) < 0); | |
58574 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); | |
58575 | }}}}m68k_incpc(2); | |
58576 | fill_prefetch_2 (); | |
58577 | return (6+retcycles*2); | |
58578 | } | |
58579 | unsigned long CPUFUNC(op_e110_5)(uint32_t opcode) /* ROXL */ | |
58580 | { | |
58581 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
58582 | uint32_t dstreg = opcode & 7; | |
58583 | unsigned int retcycles = 0; | |
58584 | OpcodeFamily = 70; CurrentInstrCycles = 4; | |
58585 | {{ uint32_t cnt = srcreg; | |
58586 | { int8_t data = m68k_dreg(regs, dstreg); | |
58587 | { uint32_t val = (uint8_t)data; | |
58588 | cnt &= 63; | |
58589 | retcycles = cnt; | |
58590 | CLEAR_CZNV; | |
58591 | { cnt--; | |
58592 | { | |
58593 | uint32_t carry; | |
58594 | uint32_t loval = val >> (7 - cnt); | |
58595 | carry = loval & 1; | |
58596 | val = (((val << 1) | GET_XFLG) << cnt) | (loval >> 1); | |
58597 | SET_XFLG (carry); | |
58598 | val &= 0xff; | |
58599 | } } | |
58600 | SET_CFLG (GET_XFLG); | |
58601 | SET_ZFLG (((int8_t)(val)) == 0); | |
58602 | SET_NFLG (((int8_t)(val)) < 0); | |
58603 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); | |
58604 | }}}}m68k_incpc(2); | |
58605 | fill_prefetch_2 (); | |
58606 | return (6+retcycles*2); | |
58607 | } | |
58608 | unsigned long CPUFUNC(op_e118_5)(uint32_t opcode) /* ROL */ | |
58609 | { | |
58610 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
58611 | uint32_t dstreg = opcode & 7; | |
58612 | unsigned int retcycles = 0; | |
58613 | OpcodeFamily = 68; CurrentInstrCycles = 4; | |
58614 | {{ uint32_t cnt = srcreg; | |
58615 | { int8_t data = m68k_dreg(regs, dstreg); | |
58616 | { uint32_t val = (uint8_t)data; | |
58617 | cnt &= 63; | |
58618 | retcycles = cnt; | |
58619 | CLEAR_CZNV; | |
58620 | { uint32_t loval; | |
58621 | cnt &= 7; | |
58622 | loval = val >> (8 - cnt); | |
58623 | val <<= cnt; | |
58624 | val |= loval; | |
58625 | val &= 0xff; | |
58626 | SET_CFLG (val & 1); | |
58627 | } | |
58628 | SET_ZFLG (((int8_t)(val)) == 0); | |
58629 | SET_NFLG (((int8_t)(val)) < 0); | |
58630 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); | |
58631 | }}}}m68k_incpc(2); | |
58632 | fill_prefetch_2 (); | |
58633 | return (6+retcycles*2); | |
58634 | } | |
58635 | unsigned long CPUFUNC(op_e120_5)(uint32_t opcode) /* ASL */ | |
58636 | { | |
58637 | uint32_t srcreg = ((opcode >> 9) & 7); | |
58638 | uint32_t dstreg = opcode & 7; | |
58639 | unsigned int retcycles = 0; | |
58640 | OpcodeFamily = 65; CurrentInstrCycles = 4; | |
58641 | {{ int8_t cnt = m68k_dreg(regs, srcreg); | |
58642 | { int8_t data = m68k_dreg(regs, dstreg); | |
58643 | { uint32_t val = (uint8_t)data; | |
58644 | cnt &= 63; | |
58645 | retcycles = cnt; | |
58646 | CLEAR_CZNV; | |
58647 | if (cnt >= 8) { | |
58648 | SET_VFLG (val != 0); | |
58649 | SET_CFLG (cnt == 8 ? val & 1 : 0); | |
58650 | COPY_CARRY; | |
58651 | val = 0; | |
58652 | } else if (cnt > 0) { | |
58653 | uint32_t mask = (0xff << (7 - cnt)) & 0xff; | |
58654 | SET_VFLG ((val & mask) != mask && (val & mask) != 0); | |
58655 | val <<= cnt - 1; | |
58656 | SET_CFLG ((val & 0x80) >> 7); | |
58657 | COPY_CARRY; | |
58658 | val <<= 1; | |
58659 | val &= 0xff; | |
58660 | } | |
58661 | SET_ZFLG (((int8_t)(val)) == 0); | |
58662 | SET_NFLG (((int8_t)(val)) < 0); | |
58663 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); | |
58664 | }}}}m68k_incpc(2); | |
58665 | fill_prefetch_2 (); | |
58666 | return (6+retcycles*2); | |
58667 | } | |
58668 | unsigned long CPUFUNC(op_e128_5)(uint32_t opcode) /* LSL */ | |
58669 | { | |
58670 | uint32_t srcreg = ((opcode >> 9) & 7); | |
58671 | uint32_t dstreg = opcode & 7; | |
58672 | unsigned int retcycles = 0; | |
58673 | OpcodeFamily = 67; CurrentInstrCycles = 4; | |
58674 | {{ int8_t cnt = m68k_dreg(regs, srcreg); | |
58675 | { int8_t data = m68k_dreg(regs, dstreg); | |
58676 | { uint32_t val = (uint8_t)data; | |
58677 | cnt &= 63; | |
58678 | retcycles = cnt; | |
58679 | CLEAR_CZNV; | |
58680 | if (cnt >= 8) { | |
58681 | SET_CFLG (cnt == 8 ? val & 1 : 0); | |
58682 | COPY_CARRY; | |
58683 | val = 0; | |
58684 | } else if (cnt > 0) { | |
58685 | val <<= (cnt - 1); | |
58686 | SET_CFLG ((val & 0x80) >> 7); | |
58687 | COPY_CARRY; | |
58688 | val <<= 1; | |
58689 | val &= 0xff; | |
58690 | } | |
58691 | SET_ZFLG (((int8_t)(val)) == 0); | |
58692 | SET_NFLG (((int8_t)(val)) < 0); | |
58693 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); | |
58694 | }}}}m68k_incpc(2); | |
58695 | fill_prefetch_2 (); | |
58696 | return (6+retcycles*2); | |
58697 | } | |
58698 | unsigned long CPUFUNC(op_e130_5)(uint32_t opcode) /* ROXL */ | |
58699 | { | |
58700 | uint32_t srcreg = ((opcode >> 9) & 7); | |
58701 | uint32_t dstreg = opcode & 7; | |
58702 | unsigned int retcycles = 0; | |
58703 | OpcodeFamily = 70; CurrentInstrCycles = 4; | |
58704 | {{ int8_t cnt = m68k_dreg(regs, srcreg); | |
58705 | { int8_t data = m68k_dreg(regs, dstreg); | |
58706 | { uint32_t val = (uint8_t)data; | |
58707 | cnt &= 63; | |
58708 | retcycles = cnt; | |
58709 | CLEAR_CZNV; | |
58710 | if (cnt >= 36) cnt -= 36; | |
58711 | if (cnt >= 18) cnt -= 18; | |
58712 | if (cnt >= 9) cnt -= 9; | |
58713 | if (cnt > 0) { | |
58714 | cnt--; | |
58715 | { | |
58716 | uint32_t carry; | |
58717 | uint32_t loval = val >> (7 - cnt); | |
58718 | carry = loval & 1; | |
58719 | val = (((val << 1) | GET_XFLG) << cnt) | (loval >> 1); | |
58720 | SET_XFLG (carry); | |
58721 | val &= 0xff; | |
58722 | } } | |
58723 | SET_CFLG (GET_XFLG); | |
58724 | SET_ZFLG (((int8_t)(val)) == 0); | |
58725 | SET_NFLG (((int8_t)(val)) < 0); | |
58726 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); | |
58727 | }}}}m68k_incpc(2); | |
58728 | fill_prefetch_2 (); | |
58729 | return (6+retcycles*2); | |
58730 | } | |
58731 | unsigned long CPUFUNC(op_e138_5)(uint32_t opcode) /* ROL */ | |
58732 | { | |
58733 | uint32_t srcreg = ((opcode >> 9) & 7); | |
58734 | uint32_t dstreg = opcode & 7; | |
58735 | unsigned int retcycles = 0; | |
58736 | OpcodeFamily = 68; CurrentInstrCycles = 4; | |
58737 | {{ int8_t cnt = m68k_dreg(regs, srcreg); | |
58738 | { int8_t data = m68k_dreg(regs, dstreg); | |
58739 | { uint32_t val = (uint8_t)data; | |
58740 | cnt &= 63; | |
58741 | retcycles = cnt; | |
58742 | CLEAR_CZNV; | |
58743 | if (cnt > 0) { | |
58744 | uint32_t loval; | |
58745 | cnt &= 7; | |
58746 | loval = val >> (8 - cnt); | |
58747 | val <<= cnt; | |
58748 | val |= loval; | |
58749 | val &= 0xff; | |
58750 | SET_CFLG (val & 1); | |
58751 | } | |
58752 | SET_ZFLG (((int8_t)(val)) == 0); | |
58753 | SET_NFLG (((int8_t)(val)) < 0); | |
58754 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xff) | ((val) & 0xff); | |
58755 | }}}}m68k_incpc(2); | |
58756 | fill_prefetch_2 (); | |
58757 | return (6+retcycles*2); | |
58758 | } | |
58759 | unsigned long CPUFUNC(op_e140_5)(uint32_t opcode) /* ASL */ | |
58760 | { | |
58761 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
58762 | uint32_t dstreg = opcode & 7; | |
58763 | unsigned int retcycles = 0; | |
58764 | OpcodeFamily = 65; CurrentInstrCycles = 4; | |
58765 | {{ uint32_t cnt = srcreg; | |
58766 | { int16_t data = m68k_dreg(regs, dstreg); | |
58767 | { uint32_t val = (uint16_t)data; | |
58768 | cnt &= 63; | |
58769 | retcycles = cnt; | |
58770 | CLEAR_CZNV; | |
58771 | if (cnt >= 16) { | |
58772 | SET_VFLG (val != 0); | |
58773 | SET_CFLG (cnt == 16 ? val & 1 : 0); | |
58774 | COPY_CARRY; | |
58775 | val = 0; | |
58776 | } else { | |
58777 | uint32_t mask = (0xffff << (15 - cnt)) & 0xffff; | |
58778 | SET_VFLG ((val & mask) != mask && (val & mask) != 0); | |
58779 | val <<= cnt - 1; | |
58780 | SET_CFLG ((val & 0x8000) >> 15); | |
58781 | COPY_CARRY; | |
58782 | val <<= 1; | |
58783 | val &= 0xffff; | |
58784 | } | |
58785 | SET_ZFLG (((int16_t)(val)) == 0); | |
58786 | SET_NFLG (((int16_t)(val)) < 0); | |
58787 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); | |
58788 | }}}}m68k_incpc(2); | |
58789 | fill_prefetch_2 (); | |
58790 | return (6+retcycles*2); | |
58791 | } | |
58792 | unsigned long CPUFUNC(op_e148_5)(uint32_t opcode) /* LSL */ | |
58793 | { | |
58794 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
58795 | uint32_t dstreg = opcode & 7; | |
58796 | unsigned int retcycles = 0; | |
58797 | OpcodeFamily = 67; CurrentInstrCycles = 4; | |
58798 | {{ uint32_t cnt = srcreg; | |
58799 | { int16_t data = m68k_dreg(regs, dstreg); | |
58800 | { uint32_t val = (uint16_t)data; | |
58801 | cnt &= 63; | |
58802 | retcycles = cnt; | |
58803 | CLEAR_CZNV; | |
58804 | if (cnt >= 16) { | |
58805 | SET_CFLG (cnt == 16 ? val & 1 : 0); | |
58806 | COPY_CARRY; | |
58807 | val = 0; | |
58808 | } else { | |
58809 | val <<= (cnt - 1); | |
58810 | SET_CFLG ((val & 0x8000) >> 15); | |
58811 | COPY_CARRY; | |
58812 | val <<= 1; | |
58813 | val &= 0xffff; | |
58814 | } | |
58815 | SET_ZFLG (((int16_t)(val)) == 0); | |
58816 | SET_NFLG (((int16_t)(val)) < 0); | |
58817 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); | |
58818 | }}}}m68k_incpc(2); | |
58819 | fill_prefetch_2 (); | |
58820 | return (6+retcycles*2); | |
58821 | } | |
58822 | unsigned long CPUFUNC(op_e150_5)(uint32_t opcode) /* ROXL */ | |
58823 | { | |
58824 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
58825 | uint32_t dstreg = opcode & 7; | |
58826 | unsigned int retcycles = 0; | |
58827 | OpcodeFamily = 70; CurrentInstrCycles = 4; | |
58828 | {{ uint32_t cnt = srcreg; | |
58829 | { int16_t data = m68k_dreg(regs, dstreg); | |
58830 | { uint32_t val = (uint16_t)data; | |
58831 | cnt &= 63; | |
58832 | retcycles = cnt; | |
58833 | CLEAR_CZNV; | |
58834 | { cnt--; | |
58835 | { | |
58836 | uint32_t carry; | |
58837 | uint32_t loval = val >> (15 - cnt); | |
58838 | carry = loval & 1; | |
58839 | val = (((val << 1) | GET_XFLG) << cnt) | (loval >> 1); | |
58840 | SET_XFLG (carry); | |
58841 | val &= 0xffff; | |
58842 | } } | |
58843 | SET_CFLG (GET_XFLG); | |
58844 | SET_ZFLG (((int16_t)(val)) == 0); | |
58845 | SET_NFLG (((int16_t)(val)) < 0); | |
58846 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); | |
58847 | }}}}m68k_incpc(2); | |
58848 | fill_prefetch_2 (); | |
58849 | return (6+retcycles*2); | |
58850 | } | |
58851 | unsigned long CPUFUNC(op_e158_5)(uint32_t opcode) /* ROL */ | |
58852 | { | |
58853 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
58854 | uint32_t dstreg = opcode & 7; | |
58855 | unsigned int retcycles = 0; | |
58856 | OpcodeFamily = 68; CurrentInstrCycles = 4; | |
58857 | {{ uint32_t cnt = srcreg; | |
58858 | { int16_t data = m68k_dreg(regs, dstreg); | |
58859 | { uint32_t val = (uint16_t)data; | |
58860 | cnt &= 63; | |
58861 | retcycles = cnt; | |
58862 | CLEAR_CZNV; | |
58863 | { uint32_t loval; | |
58864 | cnt &= 15; | |
58865 | loval = val >> (16 - cnt); | |
58866 | val <<= cnt; | |
58867 | val |= loval; | |
58868 | val &= 0xffff; | |
58869 | SET_CFLG (val & 1); | |
58870 | } | |
58871 | SET_ZFLG (((int16_t)(val)) == 0); | |
58872 | SET_NFLG (((int16_t)(val)) < 0); | |
58873 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); | |
58874 | }}}}m68k_incpc(2); | |
58875 | fill_prefetch_2 (); | |
58876 | return (6+retcycles*2); | |
58877 | } | |
58878 | unsigned long CPUFUNC(op_e160_5)(uint32_t opcode) /* ASL */ | |
58879 | { | |
58880 | uint32_t srcreg = ((opcode >> 9) & 7); | |
58881 | uint32_t dstreg = opcode & 7; | |
58882 | unsigned int retcycles = 0; | |
58883 | OpcodeFamily = 65; CurrentInstrCycles = 4; | |
58884 | {{ int16_t cnt = m68k_dreg(regs, srcreg); | |
58885 | { int16_t data = m68k_dreg(regs, dstreg); | |
58886 | { uint32_t val = (uint16_t)data; | |
58887 | cnt &= 63; | |
58888 | retcycles = cnt; | |
58889 | CLEAR_CZNV; | |
58890 | if (cnt >= 16) { | |
58891 | SET_VFLG (val != 0); | |
58892 | SET_CFLG (cnt == 16 ? val & 1 : 0); | |
58893 | COPY_CARRY; | |
58894 | val = 0; | |
58895 | } else if (cnt > 0) { | |
58896 | uint32_t mask = (0xffff << (15 - cnt)) & 0xffff; | |
58897 | SET_VFLG ((val & mask) != mask && (val & mask) != 0); | |
58898 | val <<= cnt - 1; | |
58899 | SET_CFLG ((val & 0x8000) >> 15); | |
58900 | COPY_CARRY; | |
58901 | val <<= 1; | |
58902 | val &= 0xffff; | |
58903 | } | |
58904 | SET_ZFLG (((int16_t)(val)) == 0); | |
58905 | SET_NFLG (((int16_t)(val)) < 0); | |
58906 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); | |
58907 | }}}}m68k_incpc(2); | |
58908 | fill_prefetch_2 (); | |
58909 | return (6+retcycles*2); | |
58910 | } | |
58911 | unsigned long CPUFUNC(op_e168_5)(uint32_t opcode) /* LSL */ | |
58912 | { | |
58913 | uint32_t srcreg = ((opcode >> 9) & 7); | |
58914 | uint32_t dstreg = opcode & 7; | |
58915 | unsigned int retcycles = 0; | |
58916 | OpcodeFamily = 67; CurrentInstrCycles = 4; | |
58917 | {{ int16_t cnt = m68k_dreg(regs, srcreg); | |
58918 | { int16_t data = m68k_dreg(regs, dstreg); | |
58919 | { uint32_t val = (uint16_t)data; | |
58920 | cnt &= 63; | |
58921 | retcycles = cnt; | |
58922 | CLEAR_CZNV; | |
58923 | if (cnt >= 16) { | |
58924 | SET_CFLG (cnt == 16 ? val & 1 : 0); | |
58925 | COPY_CARRY; | |
58926 | val = 0; | |
58927 | } else if (cnt > 0) { | |
58928 | val <<= (cnt - 1); | |
58929 | SET_CFLG ((val & 0x8000) >> 15); | |
58930 | COPY_CARRY; | |
58931 | val <<= 1; | |
58932 | val &= 0xffff; | |
58933 | } | |
58934 | SET_ZFLG (((int16_t)(val)) == 0); | |
58935 | SET_NFLG (((int16_t)(val)) < 0); | |
58936 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); | |
58937 | }}}}m68k_incpc(2); | |
58938 | fill_prefetch_2 (); | |
58939 | return (6+retcycles*2); | |
58940 | } | |
58941 | unsigned long CPUFUNC(op_e170_5)(uint32_t opcode) /* ROXL */ | |
58942 | { | |
58943 | uint32_t srcreg = ((opcode >> 9) & 7); | |
58944 | uint32_t dstreg = opcode & 7; | |
58945 | unsigned int retcycles = 0; | |
58946 | OpcodeFamily = 70; CurrentInstrCycles = 4; | |
58947 | {{ int16_t cnt = m68k_dreg(regs, srcreg); | |
58948 | { int16_t data = m68k_dreg(regs, dstreg); | |
58949 | { uint32_t val = (uint16_t)data; | |
58950 | cnt &= 63; | |
58951 | retcycles = cnt; | |
58952 | CLEAR_CZNV; | |
58953 | if (cnt >= 34) cnt -= 34; | |
58954 | if (cnt >= 17) cnt -= 17; | |
58955 | if (cnt > 0) { | |
58956 | cnt--; | |
58957 | { | |
58958 | uint32_t carry; | |
58959 | uint32_t loval = val >> (15 - cnt); | |
58960 | carry = loval & 1; | |
58961 | val = (((val << 1) | GET_XFLG) << cnt) | (loval >> 1); | |
58962 | SET_XFLG (carry); | |
58963 | val &= 0xffff; | |
58964 | } } | |
58965 | SET_CFLG (GET_XFLG); | |
58966 | SET_ZFLG (((int16_t)(val)) == 0); | |
58967 | SET_NFLG (((int16_t)(val)) < 0); | |
58968 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); | |
58969 | }}}}m68k_incpc(2); | |
58970 | fill_prefetch_2 (); | |
58971 | return (6+retcycles*2); | |
58972 | } | |
58973 | unsigned long CPUFUNC(op_e178_5)(uint32_t opcode) /* ROL */ | |
58974 | { | |
58975 | uint32_t srcreg = ((opcode >> 9) & 7); | |
58976 | uint32_t dstreg = opcode & 7; | |
58977 | unsigned int retcycles = 0; | |
58978 | OpcodeFamily = 68; CurrentInstrCycles = 4; | |
58979 | {{ int16_t cnt = m68k_dreg(regs, srcreg); | |
58980 | { int16_t data = m68k_dreg(regs, dstreg); | |
58981 | { uint32_t val = (uint16_t)data; | |
58982 | cnt &= 63; | |
58983 | retcycles = cnt; | |
58984 | CLEAR_CZNV; | |
58985 | if (cnt > 0) { | |
58986 | uint32_t loval; | |
58987 | cnt &= 15; | |
58988 | loval = val >> (16 - cnt); | |
58989 | val <<= cnt; | |
58990 | val |= loval; | |
58991 | val &= 0xffff; | |
58992 | SET_CFLG (val & 1); | |
58993 | } | |
58994 | SET_ZFLG (((int16_t)(val)) == 0); | |
58995 | SET_NFLG (((int16_t)(val)) < 0); | |
58996 | m68k_dreg(regs, dstreg) = (m68k_dreg(regs, dstreg) & ~0xffff) | ((val) & 0xffff); | |
58997 | }}}}m68k_incpc(2); | |
58998 | fill_prefetch_2 (); | |
58999 | return (6+retcycles*2); | |
59000 | } | |
59001 | unsigned long CPUFUNC(op_e180_5)(uint32_t opcode) /* ASL */ | |
59002 | { | |
59003 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
59004 | uint32_t dstreg = opcode & 7; | |
59005 | unsigned int retcycles = 0; | |
59006 | OpcodeFamily = 65; CurrentInstrCycles = 4; | |
59007 | {{ uint32_t cnt = srcreg; | |
59008 | { int32_t data = m68k_dreg(regs, dstreg); | |
59009 | { uint32_t val = data; | |
59010 | cnt &= 63; | |
59011 | retcycles = cnt; | |
59012 | CLEAR_CZNV; | |
59013 | if (cnt >= 32) { | |
59014 | SET_VFLG (val != 0); | |
59015 | SET_CFLG (cnt == 32 ? val & 1 : 0); | |
59016 | COPY_CARRY; | |
59017 | val = 0; | |
59018 | } else { | |
59019 | uint32_t mask = (0xffffffff << (31 - cnt)) & 0xffffffff; | |
59020 | SET_VFLG ((val & mask) != mask && (val & mask) != 0); | |
59021 | val <<= cnt - 1; | |
59022 | SET_CFLG ((val & 0x80000000) >> 31); | |
59023 | COPY_CARRY; | |
59024 | val <<= 1; | |
59025 | val &= 0xffffffff; | |
59026 | } | |
59027 | SET_ZFLG (((int32_t)(val)) == 0); | |
59028 | SET_NFLG (((int32_t)(val)) < 0); | |
59029 | m68k_dreg(regs, dstreg) = (val); | |
59030 | }}}}m68k_incpc(2); | |
59031 | fill_prefetch_2 (); | |
59032 | return (8+retcycles*2); | |
59033 | } | |
59034 | unsigned long CPUFUNC(op_e188_5)(uint32_t opcode) /* LSL */ | |
59035 | { | |
59036 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
59037 | uint32_t dstreg = opcode & 7; | |
59038 | unsigned int retcycles = 0; | |
59039 | OpcodeFamily = 67; CurrentInstrCycles = 4; | |
59040 | {{ uint32_t cnt = srcreg; | |
59041 | { int32_t data = m68k_dreg(regs, dstreg); | |
59042 | { uint32_t val = data; | |
59043 | cnt &= 63; | |
59044 | retcycles = cnt; | |
59045 | CLEAR_CZNV; | |
59046 | if (cnt >= 32) { | |
59047 | SET_CFLG (cnt == 32 ? val & 1 : 0); | |
59048 | COPY_CARRY; | |
59049 | val = 0; | |
59050 | } else { | |
59051 | val <<= (cnt - 1); | |
59052 | SET_CFLG ((val & 0x80000000) >> 31); | |
59053 | COPY_CARRY; | |
59054 | val <<= 1; | |
59055 | val &= 0xffffffff; | |
59056 | } | |
59057 | SET_ZFLG (((int32_t)(val)) == 0); | |
59058 | SET_NFLG (((int32_t)(val)) < 0); | |
59059 | m68k_dreg(regs, dstreg) = (val); | |
59060 | }}}}m68k_incpc(2); | |
59061 | fill_prefetch_2 (); | |
59062 | return (8+retcycles*2); | |
59063 | } | |
59064 | unsigned long CPUFUNC(op_e190_5)(uint32_t opcode) /* ROXL */ | |
59065 | { | |
59066 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
59067 | uint32_t dstreg = opcode & 7; | |
59068 | unsigned int retcycles = 0; | |
59069 | OpcodeFamily = 70; CurrentInstrCycles = 4; | |
59070 | {{ uint32_t cnt = srcreg; | |
59071 | { int32_t data = m68k_dreg(regs, dstreg); | |
59072 | { uint32_t val = data; | |
59073 | cnt &= 63; | |
59074 | retcycles = cnt; | |
59075 | CLEAR_CZNV; | |
59076 | { cnt--; | |
59077 | { | |
59078 | uint32_t carry; | |
59079 | uint32_t loval = val >> (31 - cnt); | |
59080 | carry = loval & 1; | |
59081 | val = (((val << 1) | GET_XFLG) << cnt) | (loval >> 1); | |
59082 | SET_XFLG (carry); | |
59083 | val &= 0xffffffff; | |
59084 | } } | |
59085 | SET_CFLG (GET_XFLG); | |
59086 | SET_ZFLG (((int32_t)(val)) == 0); | |
59087 | SET_NFLG (((int32_t)(val)) < 0); | |
59088 | m68k_dreg(regs, dstreg) = (val); | |
59089 | }}}}m68k_incpc(2); | |
59090 | fill_prefetch_2 (); | |
59091 | return (8+retcycles*2); | |
59092 | } | |
59093 | unsigned long CPUFUNC(op_e198_5)(uint32_t opcode) /* ROL */ | |
59094 | { | |
59095 | uint32_t srcreg = imm8_table[((opcode >> 9) & 7)]; | |
59096 | uint32_t dstreg = opcode & 7; | |
59097 | unsigned int retcycles = 0; | |
59098 | OpcodeFamily = 68; CurrentInstrCycles = 4; | |
59099 | {{ uint32_t cnt = srcreg; | |
59100 | { int32_t data = m68k_dreg(regs, dstreg); | |
59101 | { uint32_t val = data; | |
59102 | cnt &= 63; | |
59103 | retcycles = cnt; | |
59104 | CLEAR_CZNV; | |
59105 | { uint32_t loval; | |
59106 | cnt &= 31; | |
59107 | loval = val >> (32 - cnt); | |
59108 | val <<= cnt; | |
59109 | val |= loval; | |
59110 | val &= 0xffffffff; | |
59111 | SET_CFLG (val & 1); | |
59112 | } | |
59113 | SET_ZFLG (((int32_t)(val)) == 0); | |
59114 | SET_NFLG (((int32_t)(val)) < 0); | |
59115 | m68k_dreg(regs, dstreg) = (val); | |
59116 | }}}}m68k_incpc(2); | |
59117 | fill_prefetch_2 (); | |
59118 | return (8+retcycles*2); | |
59119 | } | |
59120 | unsigned long CPUFUNC(op_e1a0_5)(uint32_t opcode) /* ASL */ | |
59121 | { | |
59122 | uint32_t srcreg = ((opcode >> 9) & 7); | |
59123 | uint32_t dstreg = opcode & 7; | |
59124 | unsigned int retcycles = 0; | |
59125 | OpcodeFamily = 65; CurrentInstrCycles = 4; | |
59126 | {{ int32_t cnt = m68k_dreg(regs, srcreg); | |
59127 | { int32_t data = m68k_dreg(regs, dstreg); | |
59128 | { uint32_t val = data; | |
59129 | cnt &= 63; | |
59130 | retcycles = cnt; | |
59131 | CLEAR_CZNV; | |
59132 | if (cnt >= 32) { | |
59133 | SET_VFLG (val != 0); | |
59134 | SET_CFLG (cnt == 32 ? val & 1 : 0); | |
59135 | COPY_CARRY; | |
59136 | val = 0; | |
59137 | } else if (cnt > 0) { | |
59138 | uint32_t mask = (0xffffffff << (31 - cnt)) & 0xffffffff; | |
59139 | SET_VFLG ((val & mask) != mask && (val & mask) != 0); | |
59140 | val <<= cnt - 1; | |
59141 | SET_CFLG ((val & 0x80000000) >> 31); | |
59142 | COPY_CARRY; | |
59143 | val <<= 1; | |
59144 | val &= 0xffffffff; | |
59145 | } | |
59146 | SET_ZFLG (((int32_t)(val)) == 0); | |
59147 | SET_NFLG (((int32_t)(val)) < 0); | |
59148 | m68k_dreg(regs, dstreg) = (val); | |
59149 | }}}}m68k_incpc(2); | |
59150 | fill_prefetch_2 (); | |
59151 | return (8+retcycles*2); | |
59152 | } | |
59153 | unsigned long CPUFUNC(op_e1a8_5)(uint32_t opcode) /* LSL */ | |
59154 | { | |
59155 | uint32_t srcreg = ((opcode >> 9) & 7); | |
59156 | uint32_t dstreg = opcode & 7; | |
59157 | unsigned int retcycles = 0; | |
59158 | OpcodeFamily = 67; CurrentInstrCycles = 4; | |
59159 | {{ int32_t cnt = m68k_dreg(regs, srcreg); | |
59160 | { int32_t data = m68k_dreg(regs, dstreg); | |
59161 | { uint32_t val = data; | |
59162 | cnt &= 63; | |
59163 | retcycles = cnt; | |
59164 | CLEAR_CZNV; | |
59165 | if (cnt >= 32) { | |
59166 | SET_CFLG (cnt == 32 ? val & 1 : 0); | |
59167 | COPY_CARRY; | |
59168 | val = 0; | |
59169 | } else if (cnt > 0) { | |
59170 | val <<= (cnt - 1); | |
59171 | SET_CFLG ((val & 0x80000000) >> 31); | |
59172 | COPY_CARRY; | |
59173 | val <<= 1; | |
59174 | val &= 0xffffffff; | |
59175 | } | |
59176 | SET_ZFLG (((int32_t)(val)) == 0); | |
59177 | SET_NFLG (((int32_t)(val)) < 0); | |
59178 | m68k_dreg(regs, dstreg) = (val); | |
59179 | }}}}m68k_incpc(2); | |
59180 | fill_prefetch_2 (); | |
59181 | return (8+retcycles*2); | |
59182 | } | |
59183 | unsigned long CPUFUNC(op_e1b0_5)(uint32_t opcode) /* ROXL */ | |
59184 | { | |
59185 | uint32_t srcreg = ((opcode >> 9) & 7); | |
59186 | uint32_t dstreg = opcode & 7; | |
59187 | unsigned int retcycles = 0; | |
59188 | OpcodeFamily = 70; CurrentInstrCycles = 4; | |
59189 | {{ int32_t cnt = m68k_dreg(regs, srcreg); | |
59190 | { int32_t data = m68k_dreg(regs, dstreg); | |
59191 | { uint32_t val = data; | |
59192 | cnt &= 63; | |
59193 | retcycles = cnt; | |
59194 | CLEAR_CZNV; | |
59195 | if (cnt >= 33) cnt -= 33; | |
59196 | if (cnt > 0) { | |
59197 | cnt--; | |
59198 | { | |
59199 | uint32_t carry; | |
59200 | uint32_t loval = val >> (31 - cnt); | |
59201 | carry = loval & 1; | |
59202 | val = (((val << 1) | GET_XFLG) << cnt) | (loval >> 1); | |
59203 | SET_XFLG (carry); | |
59204 | val &= 0xffffffff; | |
59205 | } } | |
59206 | SET_CFLG (GET_XFLG); | |
59207 | SET_ZFLG (((int32_t)(val)) == 0); | |
59208 | SET_NFLG (((int32_t)(val)) < 0); | |
59209 | m68k_dreg(regs, dstreg) = (val); | |
59210 | }}}}m68k_incpc(2); | |
59211 | fill_prefetch_2 (); | |
59212 | return (8+retcycles*2); | |
59213 | } | |
59214 | unsigned long CPUFUNC(op_e1b8_5)(uint32_t opcode) /* ROL */ | |
59215 | { | |
59216 | uint32_t srcreg = ((opcode >> 9) & 7); | |
59217 | uint32_t dstreg = opcode & 7; | |
59218 | unsigned int retcycles = 0; | |
59219 | OpcodeFamily = 68; CurrentInstrCycles = 4; | |
59220 | {{ int32_t cnt = m68k_dreg(regs, srcreg); | |
59221 | { int32_t data = m68k_dreg(regs, dstreg); | |
59222 | { uint32_t val = data; | |
59223 | cnt &= 63; | |
59224 | retcycles = cnt; | |
59225 | CLEAR_CZNV; | |
59226 | if (cnt > 0) { | |
59227 | uint32_t loval; | |
59228 | cnt &= 31; | |
59229 | loval = val >> (32 - cnt); | |
59230 | val <<= cnt; | |
59231 | val |= loval; | |
59232 | val &= 0xffffffff; | |
59233 | SET_CFLG (val & 1); | |
59234 | } | |
59235 | SET_ZFLG (((int32_t)(val)) == 0); | |
59236 | SET_NFLG (((int32_t)(val)) < 0); | |
59237 | m68k_dreg(regs, dstreg) = (val); | |
59238 | }}}}m68k_incpc(2); | |
59239 | fill_prefetch_2 (); | |
59240 | return (8+retcycles*2); | |
59241 | } | |
59242 | unsigned long CPUFUNC(op_e1d0_5)(uint32_t opcode) /* ASLW */ | |
59243 | { | |
59244 | uint32_t srcreg = (opcode & 7); | |
59245 | OpcodeFamily = 73; CurrentInstrCycles = 12; | |
59246 | {{ uint32_t dataa = m68k_areg(regs, srcreg); | |
59247 | if ((dataa & 1) != 0) { | |
59248 | last_fault_for_exception_3 = dataa; | |
59249 | last_op_for_exception_3 = opcode; | |
59250 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
59251 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
59252 | goto endlabel3112; | |
59253 | } | |
59254 | {{ int16_t data = m68k_read_memory_16(dataa); | |
59255 | { uint32_t val = (uint16_t)data; | |
59256 | uint32_t sign = 0x8000 & val; | |
59257 | uint32_t sign2; | |
59258 | val <<= 1; | |
59259 | CLEAR_CZNV; | |
59260 | SET_ZFLG (((int16_t)(val)) == 0); | |
59261 | SET_NFLG (((int16_t)(val)) < 0); | |
59262 | sign2 = 0x8000 & val; | |
59263 | SET_CFLG (sign != 0); | |
59264 | COPY_CARRY; | |
59265 | SET_VFLG (GET_VFLG | (sign2 != sign)); | |
59266 | m68k_incpc(2); | |
59267 | fill_prefetch_2 (); | |
59268 | m68k_write_memory_16(dataa,val); | |
59269 | }}}}}endlabel3112: ; | |
59270 | return 12; | |
59271 | } | |
59272 | unsigned long CPUFUNC(op_e1d8_5)(uint32_t opcode) /* ASLW */ | |
59273 | { | |
59274 | uint32_t srcreg = (opcode & 7); | |
59275 | OpcodeFamily = 73; CurrentInstrCycles = 12; | |
59276 | {{ uint32_t dataa = m68k_areg(regs, srcreg); | |
59277 | if ((dataa & 1) != 0) { | |
59278 | last_fault_for_exception_3 = dataa; | |
59279 | last_op_for_exception_3 = opcode; | |
59280 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
59281 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
59282 | goto endlabel3113; | |
59283 | } | |
59284 | {{ int16_t data = m68k_read_memory_16(dataa); | |
59285 | m68k_areg(regs, srcreg) += 2; | |
59286 | { uint32_t val = (uint16_t)data; | |
59287 | uint32_t sign = 0x8000 & val; | |
59288 | uint32_t sign2; | |
59289 | val <<= 1; | |
59290 | CLEAR_CZNV; | |
59291 | SET_ZFLG (((int16_t)(val)) == 0); | |
59292 | SET_NFLG (((int16_t)(val)) < 0); | |
59293 | sign2 = 0x8000 & val; | |
59294 | SET_CFLG (sign != 0); | |
59295 | COPY_CARRY; | |
59296 | SET_VFLG (GET_VFLG | (sign2 != sign)); | |
59297 | m68k_incpc(2); | |
59298 | fill_prefetch_2 (); | |
59299 | m68k_write_memory_16(dataa,val); | |
59300 | }}}}}endlabel3113: ; | |
59301 | return 12; | |
59302 | } | |
59303 | unsigned long CPUFUNC(op_e1e0_5)(uint32_t opcode) /* ASLW */ | |
59304 | { | |
59305 | uint32_t srcreg = (opcode & 7); | |
59306 | OpcodeFamily = 73; CurrentInstrCycles = 14; | |
59307 | {{ uint32_t dataa = m68k_areg(regs, srcreg) - 2; | |
59308 | if ((dataa & 1) != 0) { | |
59309 | last_fault_for_exception_3 = dataa; | |
59310 | last_op_for_exception_3 = opcode; | |
59311 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
59312 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
59313 | goto endlabel3114; | |
59314 | } | |
59315 | {{ int16_t data = m68k_read_memory_16(dataa); | |
59316 | m68k_areg (regs, srcreg) = dataa; | |
59317 | { uint32_t val = (uint16_t)data; | |
59318 | uint32_t sign = 0x8000 & val; | |
59319 | uint32_t sign2; | |
59320 | val <<= 1; | |
59321 | CLEAR_CZNV; | |
59322 | SET_ZFLG (((int16_t)(val)) == 0); | |
59323 | SET_NFLG (((int16_t)(val)) < 0); | |
59324 | sign2 = 0x8000 & val; | |
59325 | SET_CFLG (sign != 0); | |
59326 | COPY_CARRY; | |
59327 | SET_VFLG (GET_VFLG | (sign2 != sign)); | |
59328 | m68k_incpc(2); | |
59329 | fill_prefetch_2 (); | |
59330 | m68k_write_memory_16(dataa,val); | |
59331 | }}}}}endlabel3114: ; | |
59332 | return 14; | |
59333 | } | |
59334 | unsigned long CPUFUNC(op_e1e8_5)(uint32_t opcode) /* ASLW */ | |
59335 | { | |
59336 | uint32_t srcreg = (opcode & 7); | |
59337 | OpcodeFamily = 73; CurrentInstrCycles = 16; | |
59338 | {{ uint32_t dataa = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
59339 | if ((dataa & 1) != 0) { | |
59340 | last_fault_for_exception_3 = dataa; | |
59341 | last_op_for_exception_3 = opcode; | |
59342 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
59343 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
59344 | goto endlabel3115; | |
59345 | } | |
59346 | {{ int16_t data = m68k_read_memory_16(dataa); | |
59347 | { uint32_t val = (uint16_t)data; | |
59348 | uint32_t sign = 0x8000 & val; | |
59349 | uint32_t sign2; | |
59350 | val <<= 1; | |
59351 | CLEAR_CZNV; | |
59352 | SET_ZFLG (((int16_t)(val)) == 0); | |
59353 | SET_NFLG (((int16_t)(val)) < 0); | |
59354 | sign2 = 0x8000 & val; | |
59355 | SET_CFLG (sign != 0); | |
59356 | COPY_CARRY; | |
59357 | SET_VFLG (GET_VFLG | (sign2 != sign)); | |
59358 | m68k_incpc(4); | |
59359 | fill_prefetch_0 (); | |
59360 | m68k_write_memory_16(dataa,val); | |
59361 | }}}}}endlabel3115: ; | |
59362 | return 16; | |
59363 | } | |
59364 | unsigned long CPUFUNC(op_e1f0_5)(uint32_t opcode) /* ASLW */ | |
59365 | { | |
59366 | uint32_t srcreg = (opcode & 7); | |
59367 | OpcodeFamily = 73; CurrentInstrCycles = 18; | |
59368 | {{ uint32_t dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
59369 | BusCyclePenalty += 2; | |
59370 | if ((dataa & 1) != 0) { | |
59371 | last_fault_for_exception_3 = dataa; | |
59372 | last_op_for_exception_3 = opcode; | |
59373 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
59374 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
59375 | goto endlabel3116; | |
59376 | } | |
59377 | {{ int16_t data = m68k_read_memory_16(dataa); | |
59378 | { uint32_t val = (uint16_t)data; | |
59379 | uint32_t sign = 0x8000 & val; | |
59380 | uint32_t sign2; | |
59381 | val <<= 1; | |
59382 | CLEAR_CZNV; | |
59383 | SET_ZFLG (((int16_t)(val)) == 0); | |
59384 | SET_NFLG (((int16_t)(val)) < 0); | |
59385 | sign2 = 0x8000 & val; | |
59386 | SET_CFLG (sign != 0); | |
59387 | COPY_CARRY; | |
59388 | SET_VFLG (GET_VFLG | (sign2 != sign)); | |
59389 | m68k_incpc(4); | |
59390 | fill_prefetch_0 (); | |
59391 | m68k_write_memory_16(dataa,val); | |
59392 | }}}}}endlabel3116: ; | |
59393 | return 18; | |
59394 | } | |
59395 | unsigned long CPUFUNC(op_e1f8_5)(uint32_t opcode) /* ASLW */ | |
59396 | { | |
59397 | OpcodeFamily = 73; CurrentInstrCycles = 16; | |
59398 | {{ uint32_t dataa = (int32_t)(int16_t)get_iword_prefetch(2); | |
59399 | if ((dataa & 1) != 0) { | |
59400 | last_fault_for_exception_3 = dataa; | |
59401 | last_op_for_exception_3 = opcode; | |
59402 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
59403 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
59404 | goto endlabel3117; | |
59405 | } | |
59406 | {{ int16_t data = m68k_read_memory_16(dataa); | |
59407 | { uint32_t val = (uint16_t)data; | |
59408 | uint32_t sign = 0x8000 & val; | |
59409 | uint32_t sign2; | |
59410 | val <<= 1; | |
59411 | CLEAR_CZNV; | |
59412 | SET_ZFLG (((int16_t)(val)) == 0); | |
59413 | SET_NFLG (((int16_t)(val)) < 0); | |
59414 | sign2 = 0x8000 & val; | |
59415 | SET_CFLG (sign != 0); | |
59416 | COPY_CARRY; | |
59417 | SET_VFLG (GET_VFLG | (sign2 != sign)); | |
59418 | m68k_incpc(4); | |
59419 | fill_prefetch_0 (); | |
59420 | m68k_write_memory_16(dataa,val); | |
59421 | }}}}}endlabel3117: ; | |
59422 | return 16; | |
59423 | } | |
59424 | unsigned long CPUFUNC(op_e1f9_5)(uint32_t opcode) /* ASLW */ | |
59425 | { | |
59426 | OpcodeFamily = 73; CurrentInstrCycles = 20; | |
59427 | {{ uint32_t dataa = get_ilong_prefetch(2); | |
59428 | if ((dataa & 1) != 0) { | |
59429 | last_fault_for_exception_3 = dataa; | |
59430 | last_op_for_exception_3 = opcode; | |
59431 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
59432 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
59433 | goto endlabel3118; | |
59434 | } | |
59435 | {{ int16_t data = m68k_read_memory_16(dataa); | |
59436 | { uint32_t val = (uint16_t)data; | |
59437 | uint32_t sign = 0x8000 & val; | |
59438 | uint32_t sign2; | |
59439 | val <<= 1; | |
59440 | CLEAR_CZNV; | |
59441 | SET_ZFLG (((int16_t)(val)) == 0); | |
59442 | SET_NFLG (((int16_t)(val)) < 0); | |
59443 | sign2 = 0x8000 & val; | |
59444 | SET_CFLG (sign != 0); | |
59445 | COPY_CARRY; | |
59446 | SET_VFLG (GET_VFLG | (sign2 != sign)); | |
59447 | m68k_incpc(6); | |
59448 | fill_prefetch_0 (); | |
59449 | m68k_write_memory_16(dataa,val); | |
59450 | }}}}}endlabel3118: ; | |
59451 | return 20; | |
59452 | } | |
59453 | unsigned long CPUFUNC(op_e2d0_5)(uint32_t opcode) /* LSRW */ | |
59454 | { | |
59455 | uint32_t srcreg = (opcode & 7); | |
59456 | OpcodeFamily = 74; CurrentInstrCycles = 12; | |
59457 | {{ uint32_t dataa = m68k_areg(regs, srcreg); | |
59458 | if ((dataa & 1) != 0) { | |
59459 | last_fault_for_exception_3 = dataa; | |
59460 | last_op_for_exception_3 = opcode; | |
59461 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
59462 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
59463 | goto endlabel3119; | |
59464 | } | |
59465 | {{ int16_t data = m68k_read_memory_16(dataa); | |
59466 | { uint32_t val = (uint16_t)data; | |
59467 | uint32_t carry = val & 1; | |
59468 | val >>= 1; | |
59469 | CLEAR_CZNV; | |
59470 | SET_ZFLG (((int16_t)(val)) == 0); | |
59471 | SET_NFLG (((int16_t)(val)) < 0); | |
59472 | SET_CFLG (carry); | |
59473 | COPY_CARRY; | |
59474 | m68k_incpc(2); | |
59475 | fill_prefetch_2 (); | |
59476 | m68k_write_memory_16(dataa,val); | |
59477 | }}}}}endlabel3119: ; | |
59478 | return 12; | |
59479 | } | |
59480 | unsigned long CPUFUNC(op_e2d8_5)(uint32_t opcode) /* LSRW */ | |
59481 | { | |
59482 | uint32_t srcreg = (opcode & 7); | |
59483 | OpcodeFamily = 74; CurrentInstrCycles = 12; | |
59484 | {{ uint32_t dataa = m68k_areg(regs, srcreg); | |
59485 | if ((dataa & 1) != 0) { | |
59486 | last_fault_for_exception_3 = dataa; | |
59487 | last_op_for_exception_3 = opcode; | |
59488 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
59489 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
59490 | goto endlabel3120; | |
59491 | } | |
59492 | {{ int16_t data = m68k_read_memory_16(dataa); | |
59493 | m68k_areg(regs, srcreg) += 2; | |
59494 | { uint32_t val = (uint16_t)data; | |
59495 | uint32_t carry = val & 1; | |
59496 | val >>= 1; | |
59497 | CLEAR_CZNV; | |
59498 | SET_ZFLG (((int16_t)(val)) == 0); | |
59499 | SET_NFLG (((int16_t)(val)) < 0); | |
59500 | SET_CFLG (carry); | |
59501 | COPY_CARRY; | |
59502 | m68k_incpc(2); | |
59503 | fill_prefetch_2 (); | |
59504 | m68k_write_memory_16(dataa,val); | |
59505 | }}}}}endlabel3120: ; | |
59506 | return 12; | |
59507 | } | |
59508 | unsigned long CPUFUNC(op_e2e0_5)(uint32_t opcode) /* LSRW */ | |
59509 | { | |
59510 | uint32_t srcreg = (opcode & 7); | |
59511 | OpcodeFamily = 74; CurrentInstrCycles = 14; | |
59512 | {{ uint32_t dataa = m68k_areg(regs, srcreg) - 2; | |
59513 | if ((dataa & 1) != 0) { | |
59514 | last_fault_for_exception_3 = dataa; | |
59515 | last_op_for_exception_3 = opcode; | |
59516 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
59517 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
59518 | goto endlabel3121; | |
59519 | } | |
59520 | {{ int16_t data = m68k_read_memory_16(dataa); | |
59521 | m68k_areg (regs, srcreg) = dataa; | |
59522 | { uint32_t val = (uint16_t)data; | |
59523 | uint32_t carry = val & 1; | |
59524 | val >>= 1; | |
59525 | CLEAR_CZNV; | |
59526 | SET_ZFLG (((int16_t)(val)) == 0); | |
59527 | SET_NFLG (((int16_t)(val)) < 0); | |
59528 | SET_CFLG (carry); | |
59529 | COPY_CARRY; | |
59530 | m68k_incpc(2); | |
59531 | fill_prefetch_2 (); | |
59532 | m68k_write_memory_16(dataa,val); | |
59533 | }}}}}endlabel3121: ; | |
59534 | return 14; | |
59535 | } | |
59536 | unsigned long CPUFUNC(op_e2e8_5)(uint32_t opcode) /* LSRW */ | |
59537 | { | |
59538 | uint32_t srcreg = (opcode & 7); | |
59539 | OpcodeFamily = 74; CurrentInstrCycles = 16; | |
59540 | {{ uint32_t dataa = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
59541 | if ((dataa & 1) != 0) { | |
59542 | last_fault_for_exception_3 = dataa; | |
59543 | last_op_for_exception_3 = opcode; | |
59544 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
59545 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
59546 | goto endlabel3122; | |
59547 | } | |
59548 | {{ int16_t data = m68k_read_memory_16(dataa); | |
59549 | { uint32_t val = (uint16_t)data; | |
59550 | uint32_t carry = val & 1; | |
59551 | val >>= 1; | |
59552 | CLEAR_CZNV; | |
59553 | SET_ZFLG (((int16_t)(val)) == 0); | |
59554 | SET_NFLG (((int16_t)(val)) < 0); | |
59555 | SET_CFLG (carry); | |
59556 | COPY_CARRY; | |
59557 | m68k_incpc(4); | |
59558 | fill_prefetch_0 (); | |
59559 | m68k_write_memory_16(dataa,val); | |
59560 | }}}}}endlabel3122: ; | |
59561 | return 16; | |
59562 | } | |
59563 | unsigned long CPUFUNC(op_e2f0_5)(uint32_t opcode) /* LSRW */ | |
59564 | { | |
59565 | uint32_t srcreg = (opcode & 7); | |
59566 | OpcodeFamily = 74; CurrentInstrCycles = 18; | |
59567 | {{ uint32_t dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
59568 | BusCyclePenalty += 2; | |
59569 | if ((dataa & 1) != 0) { | |
59570 | last_fault_for_exception_3 = dataa; | |
59571 | last_op_for_exception_3 = opcode; | |
59572 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
59573 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
59574 | goto endlabel3123; | |
59575 | } | |
59576 | {{ int16_t data = m68k_read_memory_16(dataa); | |
59577 | { uint32_t val = (uint16_t)data; | |
59578 | uint32_t carry = val & 1; | |
59579 | val >>= 1; | |
59580 | CLEAR_CZNV; | |
59581 | SET_ZFLG (((int16_t)(val)) == 0); | |
59582 | SET_NFLG (((int16_t)(val)) < 0); | |
59583 | SET_CFLG (carry); | |
59584 | COPY_CARRY; | |
59585 | m68k_incpc(4); | |
59586 | fill_prefetch_0 (); | |
59587 | m68k_write_memory_16(dataa,val); | |
59588 | }}}}}endlabel3123: ; | |
59589 | return 18; | |
59590 | } | |
59591 | unsigned long CPUFUNC(op_e2f8_5)(uint32_t opcode) /* LSRW */ | |
59592 | { | |
59593 | OpcodeFamily = 74; CurrentInstrCycles = 16; | |
59594 | {{ uint32_t dataa = (int32_t)(int16_t)get_iword_prefetch(2); | |
59595 | if ((dataa & 1) != 0) { | |
59596 | last_fault_for_exception_3 = dataa; | |
59597 | last_op_for_exception_3 = opcode; | |
59598 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
59599 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
59600 | goto endlabel3124; | |
59601 | } | |
59602 | {{ int16_t data = m68k_read_memory_16(dataa); | |
59603 | { uint32_t val = (uint16_t)data; | |
59604 | uint32_t carry = val & 1; | |
59605 | val >>= 1; | |
59606 | CLEAR_CZNV; | |
59607 | SET_ZFLG (((int16_t)(val)) == 0); | |
59608 | SET_NFLG (((int16_t)(val)) < 0); | |
59609 | SET_CFLG (carry); | |
59610 | COPY_CARRY; | |
59611 | m68k_incpc(4); | |
59612 | fill_prefetch_0 (); | |
59613 | m68k_write_memory_16(dataa,val); | |
59614 | }}}}}endlabel3124: ; | |
59615 | return 16; | |
59616 | } | |
59617 | unsigned long CPUFUNC(op_e2f9_5)(uint32_t opcode) /* LSRW */ | |
59618 | { | |
59619 | OpcodeFamily = 74; CurrentInstrCycles = 20; | |
59620 | {{ uint32_t dataa = get_ilong_prefetch(2); | |
59621 | if ((dataa & 1) != 0) { | |
59622 | last_fault_for_exception_3 = dataa; | |
59623 | last_op_for_exception_3 = opcode; | |
59624 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
59625 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
59626 | goto endlabel3125; | |
59627 | } | |
59628 | {{ int16_t data = m68k_read_memory_16(dataa); | |
59629 | { uint32_t val = (uint16_t)data; | |
59630 | uint32_t carry = val & 1; | |
59631 | val >>= 1; | |
59632 | CLEAR_CZNV; | |
59633 | SET_ZFLG (((int16_t)(val)) == 0); | |
59634 | SET_NFLG (((int16_t)(val)) < 0); | |
59635 | SET_CFLG (carry); | |
59636 | COPY_CARRY; | |
59637 | m68k_incpc(6); | |
59638 | fill_prefetch_0 (); | |
59639 | m68k_write_memory_16(dataa,val); | |
59640 | }}}}}endlabel3125: ; | |
59641 | return 20; | |
59642 | } | |
59643 | unsigned long CPUFUNC(op_e3d0_5)(uint32_t opcode) /* LSLW */ | |
59644 | { | |
59645 | uint32_t srcreg = (opcode & 7); | |
59646 | OpcodeFamily = 75; CurrentInstrCycles = 12; | |
59647 | {{ uint32_t dataa = m68k_areg(regs, srcreg); | |
59648 | if ((dataa & 1) != 0) { | |
59649 | last_fault_for_exception_3 = dataa; | |
59650 | last_op_for_exception_3 = opcode; | |
59651 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
59652 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
59653 | goto endlabel3126; | |
59654 | } | |
59655 | {{ int16_t data = m68k_read_memory_16(dataa); | |
59656 | { uint16_t val = data; | |
59657 | uint32_t carry = val & 0x8000; | |
59658 | val <<= 1; | |
59659 | CLEAR_CZNV; | |
59660 | SET_ZFLG (((int16_t)(val)) == 0); | |
59661 | SET_NFLG (((int16_t)(val)) < 0); | |
59662 | SET_CFLG (carry >> 15); | |
59663 | COPY_CARRY; | |
59664 | m68k_incpc(2); | |
59665 | fill_prefetch_2 (); | |
59666 | m68k_write_memory_16(dataa,val); | |
59667 | }}}}}endlabel3126: ; | |
59668 | return 12; | |
59669 | } | |
59670 | unsigned long CPUFUNC(op_e3d8_5)(uint32_t opcode) /* LSLW */ | |
59671 | { | |
59672 | uint32_t srcreg = (opcode & 7); | |
59673 | OpcodeFamily = 75; CurrentInstrCycles = 12; | |
59674 | {{ uint32_t dataa = m68k_areg(regs, srcreg); | |
59675 | if ((dataa & 1) != 0) { | |
59676 | last_fault_for_exception_3 = dataa; | |
59677 | last_op_for_exception_3 = opcode; | |
59678 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
59679 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
59680 | goto endlabel3127; | |
59681 | } | |
59682 | {{ int16_t data = m68k_read_memory_16(dataa); | |
59683 | m68k_areg(regs, srcreg) += 2; | |
59684 | { uint16_t val = data; | |
59685 | uint32_t carry = val & 0x8000; | |
59686 | val <<= 1; | |
59687 | CLEAR_CZNV; | |
59688 | SET_ZFLG (((int16_t)(val)) == 0); | |
59689 | SET_NFLG (((int16_t)(val)) < 0); | |
59690 | SET_CFLG (carry >> 15); | |
59691 | COPY_CARRY; | |
59692 | m68k_incpc(2); | |
59693 | fill_prefetch_2 (); | |
59694 | m68k_write_memory_16(dataa,val); | |
59695 | }}}}}endlabel3127: ; | |
59696 | return 12; | |
59697 | } | |
59698 | unsigned long CPUFUNC(op_e3e0_5)(uint32_t opcode) /* LSLW */ | |
59699 | { | |
59700 | uint32_t srcreg = (opcode & 7); | |
59701 | OpcodeFamily = 75; CurrentInstrCycles = 14; | |
59702 | {{ uint32_t dataa = m68k_areg(regs, srcreg) - 2; | |
59703 | if ((dataa & 1) != 0) { | |
59704 | last_fault_for_exception_3 = dataa; | |
59705 | last_op_for_exception_3 = opcode; | |
59706 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
59707 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
59708 | goto endlabel3128; | |
59709 | } | |
59710 | {{ int16_t data = m68k_read_memory_16(dataa); | |
59711 | m68k_areg (regs, srcreg) = dataa; | |
59712 | { uint16_t val = data; | |
59713 | uint32_t carry = val & 0x8000; | |
59714 | val <<= 1; | |
59715 | CLEAR_CZNV; | |
59716 | SET_ZFLG (((int16_t)(val)) == 0); | |
59717 | SET_NFLG (((int16_t)(val)) < 0); | |
59718 | SET_CFLG (carry >> 15); | |
59719 | COPY_CARRY; | |
59720 | m68k_incpc(2); | |
59721 | fill_prefetch_2 (); | |
59722 | m68k_write_memory_16(dataa,val); | |
59723 | }}}}}endlabel3128: ; | |
59724 | return 14; | |
59725 | } | |
59726 | unsigned long CPUFUNC(op_e3e8_5)(uint32_t opcode) /* LSLW */ | |
59727 | { | |
59728 | uint32_t srcreg = (opcode & 7); | |
59729 | OpcodeFamily = 75; CurrentInstrCycles = 16; | |
59730 | {{ uint32_t dataa = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
59731 | if ((dataa & 1) != 0) { | |
59732 | last_fault_for_exception_3 = dataa; | |
59733 | last_op_for_exception_3 = opcode; | |
59734 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
59735 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
59736 | goto endlabel3129; | |
59737 | } | |
59738 | {{ int16_t data = m68k_read_memory_16(dataa); | |
59739 | { uint16_t val = data; | |
59740 | uint32_t carry = val & 0x8000; | |
59741 | val <<= 1; | |
59742 | CLEAR_CZNV; | |
59743 | SET_ZFLG (((int16_t)(val)) == 0); | |
59744 | SET_NFLG (((int16_t)(val)) < 0); | |
59745 | SET_CFLG (carry >> 15); | |
59746 | COPY_CARRY; | |
59747 | m68k_incpc(4); | |
59748 | fill_prefetch_0 (); | |
59749 | m68k_write_memory_16(dataa,val); | |
59750 | }}}}}endlabel3129: ; | |
59751 | return 16; | |
59752 | } | |
59753 | unsigned long CPUFUNC(op_e3f0_5)(uint32_t opcode) /* LSLW */ | |
59754 | { | |
59755 | uint32_t srcreg = (opcode & 7); | |
59756 | OpcodeFamily = 75; CurrentInstrCycles = 18; | |
59757 | {{ uint32_t dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
59758 | BusCyclePenalty += 2; | |
59759 | if ((dataa & 1) != 0) { | |
59760 | last_fault_for_exception_3 = dataa; | |
59761 | last_op_for_exception_3 = opcode; | |
59762 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
59763 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
59764 | goto endlabel3130; | |
59765 | } | |
59766 | {{ int16_t data = m68k_read_memory_16(dataa); | |
59767 | { uint16_t val = data; | |
59768 | uint32_t carry = val & 0x8000; | |
59769 | val <<= 1; | |
59770 | CLEAR_CZNV; | |
59771 | SET_ZFLG (((int16_t)(val)) == 0); | |
59772 | SET_NFLG (((int16_t)(val)) < 0); | |
59773 | SET_CFLG (carry >> 15); | |
59774 | COPY_CARRY; | |
59775 | m68k_incpc(4); | |
59776 | fill_prefetch_0 (); | |
59777 | m68k_write_memory_16(dataa,val); | |
59778 | }}}}}endlabel3130: ; | |
59779 | return 18; | |
59780 | } | |
59781 | unsigned long CPUFUNC(op_e3f8_5)(uint32_t opcode) /* LSLW */ | |
59782 | { | |
59783 | OpcodeFamily = 75; CurrentInstrCycles = 16; | |
59784 | {{ uint32_t dataa = (int32_t)(int16_t)get_iword_prefetch(2); | |
59785 | if ((dataa & 1) != 0) { | |
59786 | last_fault_for_exception_3 = dataa; | |
59787 | last_op_for_exception_3 = opcode; | |
59788 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
59789 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
59790 | goto endlabel3131; | |
59791 | } | |
59792 | {{ int16_t data = m68k_read_memory_16(dataa); | |
59793 | { uint16_t val = data; | |
59794 | uint32_t carry = val & 0x8000; | |
59795 | val <<= 1; | |
59796 | CLEAR_CZNV; | |
59797 | SET_ZFLG (((int16_t)(val)) == 0); | |
59798 | SET_NFLG (((int16_t)(val)) < 0); | |
59799 | SET_CFLG (carry >> 15); | |
59800 | COPY_CARRY; | |
59801 | m68k_incpc(4); | |
59802 | fill_prefetch_0 (); | |
59803 | m68k_write_memory_16(dataa,val); | |
59804 | }}}}}endlabel3131: ; | |
59805 | return 16; | |
59806 | } | |
59807 | unsigned long CPUFUNC(op_e3f9_5)(uint32_t opcode) /* LSLW */ | |
59808 | { | |
59809 | OpcodeFamily = 75; CurrentInstrCycles = 20; | |
59810 | {{ uint32_t dataa = get_ilong_prefetch(2); | |
59811 | if ((dataa & 1) != 0) { | |
59812 | last_fault_for_exception_3 = dataa; | |
59813 | last_op_for_exception_3 = opcode; | |
59814 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
59815 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
59816 | goto endlabel3132; | |
59817 | } | |
59818 | {{ int16_t data = m68k_read_memory_16(dataa); | |
59819 | { uint16_t val = data; | |
59820 | uint32_t carry = val & 0x8000; | |
59821 | val <<= 1; | |
59822 | CLEAR_CZNV; | |
59823 | SET_ZFLG (((int16_t)(val)) == 0); | |
59824 | SET_NFLG (((int16_t)(val)) < 0); | |
59825 | SET_CFLG (carry >> 15); | |
59826 | COPY_CARRY; | |
59827 | m68k_incpc(6); | |
59828 | fill_prefetch_0 (); | |
59829 | m68k_write_memory_16(dataa,val); | |
59830 | }}}}}endlabel3132: ; | |
59831 | return 20; | |
59832 | } | |
59833 | unsigned long CPUFUNC(op_e4d0_5)(uint32_t opcode) /* ROXRW */ | |
59834 | { | |
59835 | uint32_t srcreg = (opcode & 7); | |
59836 | OpcodeFamily = 79; CurrentInstrCycles = 12; | |
59837 | {{ uint32_t dataa = m68k_areg(regs, srcreg); | |
59838 | if ((dataa & 1) != 0) { | |
59839 | last_fault_for_exception_3 = dataa; | |
59840 | last_op_for_exception_3 = opcode; | |
59841 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
59842 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
59843 | goto endlabel3133; | |
59844 | } | |
59845 | {{ int16_t data = m68k_read_memory_16(dataa); | |
59846 | { uint16_t val = data; | |
59847 | uint32_t carry = val & 1; | |
59848 | val >>= 1; | |
59849 | if (GET_XFLG) val |= 0x8000; | |
59850 | CLEAR_CZNV; | |
59851 | SET_ZFLG (((int16_t)(val)) == 0); | |
59852 | SET_NFLG (((int16_t)(val)) < 0); | |
59853 | SET_CFLG (carry); | |
59854 | COPY_CARRY; | |
59855 | m68k_incpc(2); | |
59856 | fill_prefetch_2 (); | |
59857 | m68k_write_memory_16(dataa,val); | |
59858 | }}}}}endlabel3133: ; | |
59859 | return 12; | |
59860 | } | |
59861 | unsigned long CPUFUNC(op_e4d8_5)(uint32_t opcode) /* ROXRW */ | |
59862 | { | |
59863 | uint32_t srcreg = (opcode & 7); | |
59864 | OpcodeFamily = 79; CurrentInstrCycles = 12; | |
59865 | {{ uint32_t dataa = m68k_areg(regs, srcreg); | |
59866 | if ((dataa & 1) != 0) { | |
59867 | last_fault_for_exception_3 = dataa; | |
59868 | last_op_for_exception_3 = opcode; | |
59869 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
59870 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
59871 | goto endlabel3134; | |
59872 | } | |
59873 | {{ int16_t data = m68k_read_memory_16(dataa); | |
59874 | m68k_areg(regs, srcreg) += 2; | |
59875 | { uint16_t val = data; | |
59876 | uint32_t carry = val & 1; | |
59877 | val >>= 1; | |
59878 | if (GET_XFLG) val |= 0x8000; | |
59879 | CLEAR_CZNV; | |
59880 | SET_ZFLG (((int16_t)(val)) == 0); | |
59881 | SET_NFLG (((int16_t)(val)) < 0); | |
59882 | SET_CFLG (carry); | |
59883 | COPY_CARRY; | |
59884 | m68k_incpc(2); | |
59885 | fill_prefetch_2 (); | |
59886 | m68k_write_memory_16(dataa,val); | |
59887 | }}}}}endlabel3134: ; | |
59888 | return 12; | |
59889 | } | |
59890 | unsigned long CPUFUNC(op_e4e0_5)(uint32_t opcode) /* ROXRW */ | |
59891 | { | |
59892 | uint32_t srcreg = (opcode & 7); | |
59893 | OpcodeFamily = 79; CurrentInstrCycles = 14; | |
59894 | {{ uint32_t dataa = m68k_areg(regs, srcreg) - 2; | |
59895 | if ((dataa & 1) != 0) { | |
59896 | last_fault_for_exception_3 = dataa; | |
59897 | last_op_for_exception_3 = opcode; | |
59898 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
59899 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
59900 | goto endlabel3135; | |
59901 | } | |
59902 | {{ int16_t data = m68k_read_memory_16(dataa); | |
59903 | m68k_areg (regs, srcreg) = dataa; | |
59904 | { uint16_t val = data; | |
59905 | uint32_t carry = val & 1; | |
59906 | val >>= 1; | |
59907 | if (GET_XFLG) val |= 0x8000; | |
59908 | CLEAR_CZNV; | |
59909 | SET_ZFLG (((int16_t)(val)) == 0); | |
59910 | SET_NFLG (((int16_t)(val)) < 0); | |
59911 | SET_CFLG (carry); | |
59912 | COPY_CARRY; | |
59913 | m68k_incpc(2); | |
59914 | fill_prefetch_2 (); | |
59915 | m68k_write_memory_16(dataa,val); | |
59916 | }}}}}endlabel3135: ; | |
59917 | return 14; | |
59918 | } | |
59919 | unsigned long CPUFUNC(op_e4e8_5)(uint32_t opcode) /* ROXRW */ | |
59920 | { | |
59921 | uint32_t srcreg = (opcode & 7); | |
59922 | OpcodeFamily = 79; CurrentInstrCycles = 16; | |
59923 | {{ uint32_t dataa = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
59924 | if ((dataa & 1) != 0) { | |
59925 | last_fault_for_exception_3 = dataa; | |
59926 | last_op_for_exception_3 = opcode; | |
59927 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
59928 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
59929 | goto endlabel3136; | |
59930 | } | |
59931 | {{ int16_t data = m68k_read_memory_16(dataa); | |
59932 | { uint16_t val = data; | |
59933 | uint32_t carry = val & 1; | |
59934 | val >>= 1; | |
59935 | if (GET_XFLG) val |= 0x8000; | |
59936 | CLEAR_CZNV; | |
59937 | SET_ZFLG (((int16_t)(val)) == 0); | |
59938 | SET_NFLG (((int16_t)(val)) < 0); | |
59939 | SET_CFLG (carry); | |
59940 | COPY_CARRY; | |
59941 | m68k_incpc(4); | |
59942 | fill_prefetch_0 (); | |
59943 | m68k_write_memory_16(dataa,val); | |
59944 | }}}}}endlabel3136: ; | |
59945 | return 16; | |
59946 | } | |
59947 | unsigned long CPUFUNC(op_e4f0_5)(uint32_t opcode) /* ROXRW */ | |
59948 | { | |
59949 | uint32_t srcreg = (opcode & 7); | |
59950 | OpcodeFamily = 79; CurrentInstrCycles = 18; | |
59951 | {{ uint32_t dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
59952 | BusCyclePenalty += 2; | |
59953 | if ((dataa & 1) != 0) { | |
59954 | last_fault_for_exception_3 = dataa; | |
59955 | last_op_for_exception_3 = opcode; | |
59956 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
59957 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
59958 | goto endlabel3137; | |
59959 | } | |
59960 | {{ int16_t data = m68k_read_memory_16(dataa); | |
59961 | { uint16_t val = data; | |
59962 | uint32_t carry = val & 1; | |
59963 | val >>= 1; | |
59964 | if (GET_XFLG) val |= 0x8000; | |
59965 | CLEAR_CZNV; | |
59966 | SET_ZFLG (((int16_t)(val)) == 0); | |
59967 | SET_NFLG (((int16_t)(val)) < 0); | |
59968 | SET_CFLG (carry); | |
59969 | COPY_CARRY; | |
59970 | m68k_incpc(4); | |
59971 | fill_prefetch_0 (); | |
59972 | m68k_write_memory_16(dataa,val); | |
59973 | }}}}}endlabel3137: ; | |
59974 | return 18; | |
59975 | } | |
59976 | unsigned long CPUFUNC(op_e4f8_5)(uint32_t opcode) /* ROXRW */ | |
59977 | { | |
59978 | OpcodeFamily = 79; CurrentInstrCycles = 16; | |
59979 | {{ uint32_t dataa = (int32_t)(int16_t)get_iword_prefetch(2); | |
59980 | if ((dataa & 1) != 0) { | |
59981 | last_fault_for_exception_3 = dataa; | |
59982 | last_op_for_exception_3 = opcode; | |
59983 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
59984 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
59985 | goto endlabel3138; | |
59986 | } | |
59987 | {{ int16_t data = m68k_read_memory_16(dataa); | |
59988 | { uint16_t val = data; | |
59989 | uint32_t carry = val & 1; | |
59990 | val >>= 1; | |
59991 | if (GET_XFLG) val |= 0x8000; | |
59992 | CLEAR_CZNV; | |
59993 | SET_ZFLG (((int16_t)(val)) == 0); | |
59994 | SET_NFLG (((int16_t)(val)) < 0); | |
59995 | SET_CFLG (carry); | |
59996 | COPY_CARRY; | |
59997 | m68k_incpc(4); | |
59998 | fill_prefetch_0 (); | |
59999 | m68k_write_memory_16(dataa,val); | |
60000 | }}}}}endlabel3138: ; | |
60001 | return 16; | |
60002 | } | |
60003 | unsigned long CPUFUNC(op_e4f9_5)(uint32_t opcode) /* ROXRW */ | |
60004 | { | |
60005 | OpcodeFamily = 79; CurrentInstrCycles = 20; | |
60006 | {{ uint32_t dataa = get_ilong_prefetch(2); | |
60007 | if ((dataa & 1) != 0) { | |
60008 | last_fault_for_exception_3 = dataa; | |
60009 | last_op_for_exception_3 = opcode; | |
60010 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
60011 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
60012 | goto endlabel3139; | |
60013 | } | |
60014 | {{ int16_t data = m68k_read_memory_16(dataa); | |
60015 | { uint16_t val = data; | |
60016 | uint32_t carry = val & 1; | |
60017 | val >>= 1; | |
60018 | if (GET_XFLG) val |= 0x8000; | |
60019 | CLEAR_CZNV; | |
60020 | SET_ZFLG (((int16_t)(val)) == 0); | |
60021 | SET_NFLG (((int16_t)(val)) < 0); | |
60022 | SET_CFLG (carry); | |
60023 | COPY_CARRY; | |
60024 | m68k_incpc(6); | |
60025 | fill_prefetch_0 (); | |
60026 | m68k_write_memory_16(dataa,val); | |
60027 | }}}}}endlabel3139: ; | |
60028 | return 20; | |
60029 | } | |
60030 | unsigned long CPUFUNC(op_e5d0_5)(uint32_t opcode) /* ROXLW */ | |
60031 | { | |
60032 | uint32_t srcreg = (opcode & 7); | |
60033 | OpcodeFamily = 78; CurrentInstrCycles = 12; | |
60034 | {{ uint32_t dataa = m68k_areg(regs, srcreg); | |
60035 | if ((dataa & 1) != 0) { | |
60036 | last_fault_for_exception_3 = dataa; | |
60037 | last_op_for_exception_3 = opcode; | |
60038 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
60039 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
60040 | goto endlabel3140; | |
60041 | } | |
60042 | {{ int16_t data = m68k_read_memory_16(dataa); | |
60043 | { uint16_t val = data; | |
60044 | uint32_t carry = val & 0x8000; | |
60045 | val <<= 1; | |
60046 | if (GET_XFLG) val |= 1; | |
60047 | CLEAR_CZNV; | |
60048 | SET_ZFLG (((int16_t)(val)) == 0); | |
60049 | SET_NFLG (((int16_t)(val)) < 0); | |
60050 | SET_CFLG (carry >> 15); | |
60051 | COPY_CARRY; | |
60052 | m68k_incpc(2); | |
60053 | fill_prefetch_2 (); | |
60054 | m68k_write_memory_16(dataa,val); | |
60055 | }}}}}endlabel3140: ; | |
60056 | return 12; | |
60057 | } | |
60058 | unsigned long CPUFUNC(op_e5d8_5)(uint32_t opcode) /* ROXLW */ | |
60059 | { | |
60060 | uint32_t srcreg = (opcode & 7); | |
60061 | OpcodeFamily = 78; CurrentInstrCycles = 12; | |
60062 | {{ uint32_t dataa = m68k_areg(regs, srcreg); | |
60063 | if ((dataa & 1) != 0) { | |
60064 | last_fault_for_exception_3 = dataa; | |
60065 | last_op_for_exception_3 = opcode; | |
60066 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
60067 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
60068 | goto endlabel3141; | |
60069 | } | |
60070 | {{ int16_t data = m68k_read_memory_16(dataa); | |
60071 | m68k_areg(regs, srcreg) += 2; | |
60072 | { uint16_t val = data; | |
60073 | uint32_t carry = val & 0x8000; | |
60074 | val <<= 1; | |
60075 | if (GET_XFLG) val |= 1; | |
60076 | CLEAR_CZNV; | |
60077 | SET_ZFLG (((int16_t)(val)) == 0); | |
60078 | SET_NFLG (((int16_t)(val)) < 0); | |
60079 | SET_CFLG (carry >> 15); | |
60080 | COPY_CARRY; | |
60081 | m68k_incpc(2); | |
60082 | fill_prefetch_2 (); | |
60083 | m68k_write_memory_16(dataa,val); | |
60084 | }}}}}endlabel3141: ; | |
60085 | return 12; | |
60086 | } | |
60087 | unsigned long CPUFUNC(op_e5e0_5)(uint32_t opcode) /* ROXLW */ | |
60088 | { | |
60089 | uint32_t srcreg = (opcode & 7); | |
60090 | OpcodeFamily = 78; CurrentInstrCycles = 14; | |
60091 | {{ uint32_t dataa = m68k_areg(regs, srcreg) - 2; | |
60092 | if ((dataa & 1) != 0) { | |
60093 | last_fault_for_exception_3 = dataa; | |
60094 | last_op_for_exception_3 = opcode; | |
60095 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
60096 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
60097 | goto endlabel3142; | |
60098 | } | |
60099 | {{ int16_t data = m68k_read_memory_16(dataa); | |
60100 | m68k_areg (regs, srcreg) = dataa; | |
60101 | { uint16_t val = data; | |
60102 | uint32_t carry = val & 0x8000; | |
60103 | val <<= 1; | |
60104 | if (GET_XFLG) val |= 1; | |
60105 | CLEAR_CZNV; | |
60106 | SET_ZFLG (((int16_t)(val)) == 0); | |
60107 | SET_NFLG (((int16_t)(val)) < 0); | |
60108 | SET_CFLG (carry >> 15); | |
60109 | COPY_CARRY; | |
60110 | m68k_incpc(2); | |
60111 | fill_prefetch_2 (); | |
60112 | m68k_write_memory_16(dataa,val); | |
60113 | }}}}}endlabel3142: ; | |
60114 | return 14; | |
60115 | } | |
60116 | unsigned long CPUFUNC(op_e5e8_5)(uint32_t opcode) /* ROXLW */ | |
60117 | { | |
60118 | uint32_t srcreg = (opcode & 7); | |
60119 | OpcodeFamily = 78; CurrentInstrCycles = 16; | |
60120 | {{ uint32_t dataa = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
60121 | if ((dataa & 1) != 0) { | |
60122 | last_fault_for_exception_3 = dataa; | |
60123 | last_op_for_exception_3 = opcode; | |
60124 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
60125 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
60126 | goto endlabel3143; | |
60127 | } | |
60128 | {{ int16_t data = m68k_read_memory_16(dataa); | |
60129 | { uint16_t val = data; | |
60130 | uint32_t carry = val & 0x8000; | |
60131 | val <<= 1; | |
60132 | if (GET_XFLG) val |= 1; | |
60133 | CLEAR_CZNV; | |
60134 | SET_ZFLG (((int16_t)(val)) == 0); | |
60135 | SET_NFLG (((int16_t)(val)) < 0); | |
60136 | SET_CFLG (carry >> 15); | |
60137 | COPY_CARRY; | |
60138 | m68k_incpc(4); | |
60139 | fill_prefetch_0 (); | |
60140 | m68k_write_memory_16(dataa,val); | |
60141 | }}}}}endlabel3143: ; | |
60142 | return 16; | |
60143 | } | |
60144 | unsigned long CPUFUNC(op_e5f0_5)(uint32_t opcode) /* ROXLW */ | |
60145 | { | |
60146 | uint32_t srcreg = (opcode & 7); | |
60147 | OpcodeFamily = 78; CurrentInstrCycles = 18; | |
60148 | {{ uint32_t dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
60149 | BusCyclePenalty += 2; | |
60150 | if ((dataa & 1) != 0) { | |
60151 | last_fault_for_exception_3 = dataa; | |
60152 | last_op_for_exception_3 = opcode; | |
60153 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
60154 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
60155 | goto endlabel3144; | |
60156 | } | |
60157 | {{ int16_t data = m68k_read_memory_16(dataa); | |
60158 | { uint16_t val = data; | |
60159 | uint32_t carry = val & 0x8000; | |
60160 | val <<= 1; | |
60161 | if (GET_XFLG) val |= 1; | |
60162 | CLEAR_CZNV; | |
60163 | SET_ZFLG (((int16_t)(val)) == 0); | |
60164 | SET_NFLG (((int16_t)(val)) < 0); | |
60165 | SET_CFLG (carry >> 15); | |
60166 | COPY_CARRY; | |
60167 | m68k_incpc(4); | |
60168 | fill_prefetch_0 (); | |
60169 | m68k_write_memory_16(dataa,val); | |
60170 | }}}}}endlabel3144: ; | |
60171 | return 18; | |
60172 | } | |
60173 | unsigned long CPUFUNC(op_e5f8_5)(uint32_t opcode) /* ROXLW */ | |
60174 | { | |
60175 | OpcodeFamily = 78; CurrentInstrCycles = 16; | |
60176 | {{ uint32_t dataa = (int32_t)(int16_t)get_iword_prefetch(2); | |
60177 | if ((dataa & 1) != 0) { | |
60178 | last_fault_for_exception_3 = dataa; | |
60179 | last_op_for_exception_3 = opcode; | |
60180 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
60181 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
60182 | goto endlabel3145; | |
60183 | } | |
60184 | {{ int16_t data = m68k_read_memory_16(dataa); | |
60185 | { uint16_t val = data; | |
60186 | uint32_t carry = val & 0x8000; | |
60187 | val <<= 1; | |
60188 | if (GET_XFLG) val |= 1; | |
60189 | CLEAR_CZNV; | |
60190 | SET_ZFLG (((int16_t)(val)) == 0); | |
60191 | SET_NFLG (((int16_t)(val)) < 0); | |
60192 | SET_CFLG (carry >> 15); | |
60193 | COPY_CARRY; | |
60194 | m68k_incpc(4); | |
60195 | fill_prefetch_0 (); | |
60196 | m68k_write_memory_16(dataa,val); | |
60197 | }}}}}endlabel3145: ; | |
60198 | return 16; | |
60199 | } | |
60200 | unsigned long CPUFUNC(op_e5f9_5)(uint32_t opcode) /* ROXLW */ | |
60201 | { | |
60202 | OpcodeFamily = 78; CurrentInstrCycles = 20; | |
60203 | {{ uint32_t dataa = get_ilong_prefetch(2); | |
60204 | if ((dataa & 1) != 0) { | |
60205 | last_fault_for_exception_3 = dataa; | |
60206 | last_op_for_exception_3 = opcode; | |
60207 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
60208 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
60209 | goto endlabel3146; | |
60210 | } | |
60211 | {{ int16_t data = m68k_read_memory_16(dataa); | |
60212 | { uint16_t val = data; | |
60213 | uint32_t carry = val & 0x8000; | |
60214 | val <<= 1; | |
60215 | if (GET_XFLG) val |= 1; | |
60216 | CLEAR_CZNV; | |
60217 | SET_ZFLG (((int16_t)(val)) == 0); | |
60218 | SET_NFLG (((int16_t)(val)) < 0); | |
60219 | SET_CFLG (carry >> 15); | |
60220 | COPY_CARRY; | |
60221 | m68k_incpc(6); | |
60222 | fill_prefetch_0 (); | |
60223 | m68k_write_memory_16(dataa,val); | |
60224 | }}}}}endlabel3146: ; | |
60225 | return 20; | |
60226 | } | |
60227 | unsigned long CPUFUNC(op_e6d0_5)(uint32_t opcode) /* RORW */ | |
60228 | { | |
60229 | uint32_t srcreg = (opcode & 7); | |
60230 | OpcodeFamily = 77; CurrentInstrCycles = 12; | |
60231 | {{ uint32_t dataa = m68k_areg(regs, srcreg); | |
60232 | if ((dataa & 1) != 0) { | |
60233 | last_fault_for_exception_3 = dataa; | |
60234 | last_op_for_exception_3 = opcode; | |
60235 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
60236 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
60237 | goto endlabel3147; | |
60238 | } | |
60239 | {{ int16_t data = m68k_read_memory_16(dataa); | |
60240 | { uint16_t val = data; | |
60241 | uint32_t carry = val & 1; | |
60242 | val >>= 1; | |
60243 | if (carry) val |= 0x8000; | |
60244 | CLEAR_CZNV; | |
60245 | SET_ZFLG (((int16_t)(val)) == 0); | |
60246 | SET_NFLG (((int16_t)(val)) < 0); | |
60247 | SET_CFLG (carry); | |
60248 | m68k_incpc(2); | |
60249 | fill_prefetch_2 (); | |
60250 | m68k_write_memory_16(dataa,val); | |
60251 | }}}}}endlabel3147: ; | |
60252 | return 12; | |
60253 | } | |
60254 | unsigned long CPUFUNC(op_e6d8_5)(uint32_t opcode) /* RORW */ | |
60255 | { | |
60256 | uint32_t srcreg = (opcode & 7); | |
60257 | OpcodeFamily = 77; CurrentInstrCycles = 12; | |
60258 | {{ uint32_t dataa = m68k_areg(regs, srcreg); | |
60259 | if ((dataa & 1) != 0) { | |
60260 | last_fault_for_exception_3 = dataa; | |
60261 | last_op_for_exception_3 = opcode; | |
60262 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
60263 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
60264 | goto endlabel3148; | |
60265 | } | |
60266 | {{ int16_t data = m68k_read_memory_16(dataa); | |
60267 | m68k_areg(regs, srcreg) += 2; | |
60268 | { uint16_t val = data; | |
60269 | uint32_t carry = val & 1; | |
60270 | val >>= 1; | |
60271 | if (carry) val |= 0x8000; | |
60272 | CLEAR_CZNV; | |
60273 | SET_ZFLG (((int16_t)(val)) == 0); | |
60274 | SET_NFLG (((int16_t)(val)) < 0); | |
60275 | SET_CFLG (carry); | |
60276 | m68k_incpc(2); | |
60277 | fill_prefetch_2 (); | |
60278 | m68k_write_memory_16(dataa,val); | |
60279 | }}}}}endlabel3148: ; | |
60280 | return 12; | |
60281 | } | |
60282 | unsigned long CPUFUNC(op_e6e0_5)(uint32_t opcode) /* RORW */ | |
60283 | { | |
60284 | uint32_t srcreg = (opcode & 7); | |
60285 | OpcodeFamily = 77; CurrentInstrCycles = 14; | |
60286 | {{ uint32_t dataa = m68k_areg(regs, srcreg) - 2; | |
60287 | if ((dataa & 1) != 0) { | |
60288 | last_fault_for_exception_3 = dataa; | |
60289 | last_op_for_exception_3 = opcode; | |
60290 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
60291 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
60292 | goto endlabel3149; | |
60293 | } | |
60294 | {{ int16_t data = m68k_read_memory_16(dataa); | |
60295 | m68k_areg (regs, srcreg) = dataa; | |
60296 | { uint16_t val = data; | |
60297 | uint32_t carry = val & 1; | |
60298 | val >>= 1; | |
60299 | if (carry) val |= 0x8000; | |
60300 | CLEAR_CZNV; | |
60301 | SET_ZFLG (((int16_t)(val)) == 0); | |
60302 | SET_NFLG (((int16_t)(val)) < 0); | |
60303 | SET_CFLG (carry); | |
60304 | m68k_incpc(2); | |
60305 | fill_prefetch_2 (); | |
60306 | m68k_write_memory_16(dataa,val); | |
60307 | }}}}}endlabel3149: ; | |
60308 | return 14; | |
60309 | } | |
60310 | unsigned long CPUFUNC(op_e6e8_5)(uint32_t opcode) /* RORW */ | |
60311 | { | |
60312 | uint32_t srcreg = (opcode & 7); | |
60313 | OpcodeFamily = 77; CurrentInstrCycles = 16; | |
60314 | {{ uint32_t dataa = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
60315 | if ((dataa & 1) != 0) { | |
60316 | last_fault_for_exception_3 = dataa; | |
60317 | last_op_for_exception_3 = opcode; | |
60318 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
60319 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
60320 | goto endlabel3150; | |
60321 | } | |
60322 | {{ int16_t data = m68k_read_memory_16(dataa); | |
60323 | { uint16_t val = data; | |
60324 | uint32_t carry = val & 1; | |
60325 | val >>= 1; | |
60326 | if (carry) val |= 0x8000; | |
60327 | CLEAR_CZNV; | |
60328 | SET_ZFLG (((int16_t)(val)) == 0); | |
60329 | SET_NFLG (((int16_t)(val)) < 0); | |
60330 | SET_CFLG (carry); | |
60331 | m68k_incpc(4); | |
60332 | fill_prefetch_0 (); | |
60333 | m68k_write_memory_16(dataa,val); | |
60334 | }}}}}endlabel3150: ; | |
60335 | return 16; | |
60336 | } | |
60337 | unsigned long CPUFUNC(op_e6f0_5)(uint32_t opcode) /* RORW */ | |
60338 | { | |
60339 | uint32_t srcreg = (opcode & 7); | |
60340 | OpcodeFamily = 77; CurrentInstrCycles = 18; | |
60341 | {{ uint32_t dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
60342 | BusCyclePenalty += 2; | |
60343 | if ((dataa & 1) != 0) { | |
60344 | last_fault_for_exception_3 = dataa; | |
60345 | last_op_for_exception_3 = opcode; | |
60346 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
60347 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
60348 | goto endlabel3151; | |
60349 | } | |
60350 | {{ int16_t data = m68k_read_memory_16(dataa); | |
60351 | { uint16_t val = data; | |
60352 | uint32_t carry = val & 1; | |
60353 | val >>= 1; | |
60354 | if (carry) val |= 0x8000; | |
60355 | CLEAR_CZNV; | |
60356 | SET_ZFLG (((int16_t)(val)) == 0); | |
60357 | SET_NFLG (((int16_t)(val)) < 0); | |
60358 | SET_CFLG (carry); | |
60359 | m68k_incpc(4); | |
60360 | fill_prefetch_0 (); | |
60361 | m68k_write_memory_16(dataa,val); | |
60362 | }}}}}endlabel3151: ; | |
60363 | return 18; | |
60364 | } | |
60365 | unsigned long CPUFUNC(op_e6f8_5)(uint32_t opcode) /* RORW */ | |
60366 | { | |
60367 | OpcodeFamily = 77; CurrentInstrCycles = 16; | |
60368 | {{ uint32_t dataa = (int32_t)(int16_t)get_iword_prefetch(2); | |
60369 | if ((dataa & 1) != 0) { | |
60370 | last_fault_for_exception_3 = dataa; | |
60371 | last_op_for_exception_3 = opcode; | |
60372 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
60373 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
60374 | goto endlabel3152; | |
60375 | } | |
60376 | {{ int16_t data = m68k_read_memory_16(dataa); | |
60377 | { uint16_t val = data; | |
60378 | uint32_t carry = val & 1; | |
60379 | val >>= 1; | |
60380 | if (carry) val |= 0x8000; | |
60381 | CLEAR_CZNV; | |
60382 | SET_ZFLG (((int16_t)(val)) == 0); | |
60383 | SET_NFLG (((int16_t)(val)) < 0); | |
60384 | SET_CFLG (carry); | |
60385 | m68k_incpc(4); | |
60386 | fill_prefetch_0 (); | |
60387 | m68k_write_memory_16(dataa,val); | |
60388 | }}}}}endlabel3152: ; | |
60389 | return 16; | |
60390 | } | |
60391 | unsigned long CPUFUNC(op_e6f9_5)(uint32_t opcode) /* RORW */ | |
60392 | { | |
60393 | OpcodeFamily = 77; CurrentInstrCycles = 20; | |
60394 | {{ uint32_t dataa = get_ilong_prefetch(2); | |
60395 | if ((dataa & 1) != 0) { | |
60396 | last_fault_for_exception_3 = dataa; | |
60397 | last_op_for_exception_3 = opcode; | |
60398 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
60399 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
60400 | goto endlabel3153; | |
60401 | } | |
60402 | {{ int16_t data = m68k_read_memory_16(dataa); | |
60403 | { uint16_t val = data; | |
60404 | uint32_t carry = val & 1; | |
60405 | val >>= 1; | |
60406 | if (carry) val |= 0x8000; | |
60407 | CLEAR_CZNV; | |
60408 | SET_ZFLG (((int16_t)(val)) == 0); | |
60409 | SET_NFLG (((int16_t)(val)) < 0); | |
60410 | SET_CFLG (carry); | |
60411 | m68k_incpc(6); | |
60412 | fill_prefetch_0 (); | |
60413 | m68k_write_memory_16(dataa,val); | |
60414 | }}}}}endlabel3153: ; | |
60415 | return 20; | |
60416 | } | |
60417 | unsigned long CPUFUNC(op_e7d0_5)(uint32_t opcode) /* ROLW */ | |
60418 | { | |
60419 | uint32_t srcreg = (opcode & 7); | |
60420 | OpcodeFamily = 76; CurrentInstrCycles = 12; | |
60421 | {{ uint32_t dataa = m68k_areg(regs, srcreg); | |
60422 | if ((dataa & 1) != 0) { | |
60423 | last_fault_for_exception_3 = dataa; | |
60424 | last_op_for_exception_3 = opcode; | |
60425 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
60426 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
60427 | goto endlabel3154; | |
60428 | } | |
60429 | {{ int16_t data = m68k_read_memory_16(dataa); | |
60430 | { uint16_t val = data; | |
60431 | uint32_t carry = val & 0x8000; | |
60432 | val <<= 1; | |
60433 | if (carry) val |= 1; | |
60434 | CLEAR_CZNV; | |
60435 | SET_ZFLG (((int16_t)(val)) == 0); | |
60436 | SET_NFLG (((int16_t)(val)) < 0); | |
60437 | SET_CFLG (carry >> 15); | |
60438 | m68k_incpc(2); | |
60439 | fill_prefetch_2 (); | |
60440 | m68k_write_memory_16(dataa,val); | |
60441 | }}}}}endlabel3154: ; | |
60442 | return 12; | |
60443 | } | |
60444 | unsigned long CPUFUNC(op_e7d8_5)(uint32_t opcode) /* ROLW */ | |
60445 | { | |
60446 | uint32_t srcreg = (opcode & 7); | |
60447 | OpcodeFamily = 76; CurrentInstrCycles = 12; | |
60448 | {{ uint32_t dataa = m68k_areg(regs, srcreg); | |
60449 | if ((dataa & 1) != 0) { | |
60450 | last_fault_for_exception_3 = dataa; | |
60451 | last_op_for_exception_3 = opcode; | |
60452 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
60453 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
60454 | goto endlabel3155; | |
60455 | } | |
60456 | {{ int16_t data = m68k_read_memory_16(dataa); | |
60457 | m68k_areg(regs, srcreg) += 2; | |
60458 | { uint16_t val = data; | |
60459 | uint32_t carry = val & 0x8000; | |
60460 | val <<= 1; | |
60461 | if (carry) val |= 1; | |
60462 | CLEAR_CZNV; | |
60463 | SET_ZFLG (((int16_t)(val)) == 0); | |
60464 | SET_NFLG (((int16_t)(val)) < 0); | |
60465 | SET_CFLG (carry >> 15); | |
60466 | m68k_incpc(2); | |
60467 | fill_prefetch_2 (); | |
60468 | m68k_write_memory_16(dataa,val); | |
60469 | }}}}}endlabel3155: ; | |
60470 | return 12; | |
60471 | } | |
60472 | unsigned long CPUFUNC(op_e7e0_5)(uint32_t opcode) /* ROLW */ | |
60473 | { | |
60474 | uint32_t srcreg = (opcode & 7); | |
60475 | OpcodeFamily = 76; CurrentInstrCycles = 14; | |
60476 | {{ uint32_t dataa = m68k_areg(regs, srcreg) - 2; | |
60477 | if ((dataa & 1) != 0) { | |
60478 | last_fault_for_exception_3 = dataa; | |
60479 | last_op_for_exception_3 = opcode; | |
60480 | last_addr_for_exception_3 = m68k_getpc() + 2; | |
60481 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
60482 | goto endlabel3156; | |
60483 | } | |
60484 | {{ int16_t data = m68k_read_memory_16(dataa); | |
60485 | m68k_areg (regs, srcreg) = dataa; | |
60486 | { uint16_t val = data; | |
60487 | uint32_t carry = val & 0x8000; | |
60488 | val <<= 1; | |
60489 | if (carry) val |= 1; | |
60490 | CLEAR_CZNV; | |
60491 | SET_ZFLG (((int16_t)(val)) == 0); | |
60492 | SET_NFLG (((int16_t)(val)) < 0); | |
60493 | SET_CFLG (carry >> 15); | |
60494 | m68k_incpc(2); | |
60495 | fill_prefetch_2 (); | |
60496 | m68k_write_memory_16(dataa,val); | |
60497 | }}}}}endlabel3156: ; | |
60498 | return 14; | |
60499 | } | |
60500 | unsigned long CPUFUNC(op_e7e8_5)(uint32_t opcode) /* ROLW */ | |
60501 | { | |
60502 | uint32_t srcreg = (opcode & 7); | |
60503 | OpcodeFamily = 76; CurrentInstrCycles = 16; | |
60504 | {{ uint32_t dataa = m68k_areg(regs, srcreg) + (int32_t)(int16_t)get_iword_prefetch(2); | |
60505 | if ((dataa & 1) != 0) { | |
60506 | last_fault_for_exception_3 = dataa; | |
60507 | last_op_for_exception_3 = opcode; | |
60508 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
60509 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
60510 | goto endlabel3157; | |
60511 | } | |
60512 | {{ int16_t data = m68k_read_memory_16(dataa); | |
60513 | { uint16_t val = data; | |
60514 | uint32_t carry = val & 0x8000; | |
60515 | val <<= 1; | |
60516 | if (carry) val |= 1; | |
60517 | CLEAR_CZNV; | |
60518 | SET_ZFLG (((int16_t)(val)) == 0); | |
60519 | SET_NFLG (((int16_t)(val)) < 0); | |
60520 | SET_CFLG (carry >> 15); | |
60521 | m68k_incpc(4); | |
60522 | fill_prefetch_0 (); | |
60523 | m68k_write_memory_16(dataa,val); | |
60524 | }}}}}endlabel3157: ; | |
60525 | return 16; | |
60526 | } | |
60527 | unsigned long CPUFUNC(op_e7f0_5)(uint32_t opcode) /* ROLW */ | |
60528 | { | |
60529 | uint32_t srcreg = (opcode & 7); | |
60530 | OpcodeFamily = 76; CurrentInstrCycles = 18; | |
60531 | {{ uint32_t dataa = get_disp_ea_000(m68k_areg(regs, srcreg), get_iword_prefetch(2)); | |
60532 | BusCyclePenalty += 2; | |
60533 | if ((dataa & 1) != 0) { | |
60534 | last_fault_for_exception_3 = dataa; | |
60535 | last_op_for_exception_3 = opcode; | |
60536 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
60537 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
60538 | goto endlabel3158; | |
60539 | } | |
60540 | {{ int16_t data = m68k_read_memory_16(dataa); | |
60541 | { uint16_t val = data; | |
60542 | uint32_t carry = val & 0x8000; | |
60543 | val <<= 1; | |
60544 | if (carry) val |= 1; | |
60545 | CLEAR_CZNV; | |
60546 | SET_ZFLG (((int16_t)(val)) == 0); | |
60547 | SET_NFLG (((int16_t)(val)) < 0); | |
60548 | SET_CFLG (carry >> 15); | |
60549 | m68k_incpc(4); | |
60550 | fill_prefetch_0 (); | |
60551 | m68k_write_memory_16(dataa,val); | |
60552 | }}}}}endlabel3158: ; | |
60553 | return 18; | |
60554 | } | |
60555 | unsigned long CPUFUNC(op_e7f8_5)(uint32_t opcode) /* ROLW */ | |
60556 | { | |
60557 | OpcodeFamily = 76; CurrentInstrCycles = 16; | |
60558 | {{ uint32_t dataa = (int32_t)(int16_t)get_iword_prefetch(2); | |
60559 | if ((dataa & 1) != 0) { | |
60560 | last_fault_for_exception_3 = dataa; | |
60561 | last_op_for_exception_3 = opcode; | |
60562 | last_addr_for_exception_3 = m68k_getpc() + 4; | |
60563 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
60564 | goto endlabel3159; | |
60565 | } | |
60566 | {{ int16_t data = m68k_read_memory_16(dataa); | |
60567 | { uint16_t val = data; | |
60568 | uint32_t carry = val & 0x8000; | |
60569 | val <<= 1; | |
60570 | if (carry) val |= 1; | |
60571 | CLEAR_CZNV; | |
60572 | SET_ZFLG (((int16_t)(val)) == 0); | |
60573 | SET_NFLG (((int16_t)(val)) < 0); | |
60574 | SET_CFLG (carry >> 15); | |
60575 | m68k_incpc(4); | |
60576 | fill_prefetch_0 (); | |
60577 | m68k_write_memory_16(dataa,val); | |
60578 | }}}}}endlabel3159: ; | |
60579 | return 16; | |
60580 | } | |
60581 | unsigned long CPUFUNC(op_e7f9_5)(uint32_t opcode) /* ROLW */ | |
60582 | { | |
60583 | OpcodeFamily = 76; CurrentInstrCycles = 20; | |
60584 | {{ uint32_t dataa = get_ilong_prefetch(2); | |
60585 | if ((dataa & 1) != 0) { | |
60586 | last_fault_for_exception_3 = dataa; | |
60587 | last_op_for_exception_3 = opcode; | |
60588 | last_addr_for_exception_3 = m68k_getpc() + 6; | |
60589 | Exception(3, 0, M68000_EXC_SRC_CPU); | |
60590 | goto endlabel3160; | |
60591 | } | |
60592 | {{ int16_t data = m68k_read_memory_16(dataa); | |
60593 | { uint16_t val = data; | |
60594 | uint32_t carry = val & 0x8000; | |
60595 | val <<= 1; | |
60596 | if (carry) val |= 1; | |
60597 | CLEAR_CZNV; | |
60598 | SET_ZFLG (((int16_t)(val)) == 0); | |
60599 | SET_NFLG (((int16_t)(val)) < 0); | |
60600 | SET_CFLG (carry >> 15); | |
60601 | m68k_incpc(6); | |
60602 | fill_prefetch_0 (); | |
60603 | m68k_write_memory_16(dataa,val); | |
60604 | }}}}}endlabel3160: ; | |
60605 | return 20; | |
60606 | } | |
60607 | #endif | |
60608 |