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2d0121d4 | 1 | //\r |
c4fe5864 | 2 | // HWLABELManager.cpp: HW Label manager\r |
2d0121d4 JPM |
3 | //\r |
4 | // by Jean-Paul Mari\r | |
5 | //\r | |
6 | // JPM = Jean-Paul Mari <djipi.mari@gmail.com>\r | |
c4fe5864 | 7 | // RG = Richard Goedeken\r |
2d0121d4 JPM |
8 | //\r |
9 | // WHO WHEN WHAT\r | |
10 | // --- ---------- ------------------------------------------------------------\r | |
11 | // JPM 02/08/2017 Created this file\r | |
12 | // JPM 02/08/2017 HW Label support\r | |
c4fe5864 | 13 | // RG Jan./2021 Linux build fixes\r |
2d0121d4 JPM |
14 | //\r |
15 | \r | |
16 | #include <stdlib.h>\r | |
17 | #include <string.h>\r | |
c89f8ff7 RG |
18 | #include "libelf.h"\r |
19 | #include "gelf.h"\r | |
2d0121d4 JPM |
20 | #include "log.h"\r |
21 | #include "ELFManager.h"\r | |
22 | \r | |
23 | \r | |
24 | typedef enum {\r | |
25 | HWLABEL_NO_SIZE = 0,\r | |
26 | HWLABEL_8BITS = 1,\r | |
27 | HWLABEL_16BITS = 2,\r | |
28 | HWLABEL_32BITS = 4,\r | |
29 | HWLABEL_64BITS = 8\r | |
30 | }HWLABELSIZE;\r | |
31 | \r | |
32 | typedef enum {\r | |
33 | HWLABEL_NO_ACCESS = 0,\r | |
34 | HWLABEL_R = 0x1,\r | |
35 | HWLABEL_W = 0x2,\r | |
36 | HWLABEL_O = 0x4\r | |
37 | }HWLABELACCESS;\r | |
38 | \r | |
39 | typedef struct {\r | |
40 | size_t HWLABELAdr;\r | |
41 | const char *HWLABELSymbolName;\r | |
42 | const char *HWLABELFulllName;\r | |
43 | size_t HWLABELSize;\r | |
44 | size_t HWLABELAccess;\r | |
45 | }HWLABELTab;\r | |
46 | \r | |
47 | #define NBHWLABELS (sizeof(HWLABELTabSectionType) / sizeof(HWLABELTab))\r | |
48 | \r | |
49 | \r | |
50 | // Memory map list based on the scans from the Version 2.4 - June 7, 1995\r | |
51 | HWLABELTab HWLABELTabSectionType[] = {\r | |
52 | // Internal Memory Map\r | |
53 | { 0xF00000, "MEMCON1", "Memory Configuration Register One", HWLABEL_16BITS, (HWLABEL_R | HWLABEL_W) },\r | |
54 | { 0xF00002, "MEMCON2", "Memory Configuration Register Two", HWLABEL_16BITS, (HWLABEL_R | HWLABEL_W) },\r | |
55 | { 0xF00004, "HC", "Horizontal Count", HWLABEL_16BITS, (HWLABEL_R | HWLABEL_W) },\r | |
56 | { 0xF00006, "VC", "Vertical Count", HWLABEL_16BITS, (HWLABEL_R | HWLABEL_W) },\r | |
57 | { 0xF00008, "LPH", "Horizontal Light-pen", HWLABEL_16BITS, (HWLABEL_R | HWLABEL_O) },\r | |
58 | { 0xF0000A, "LPV", "Vertical Light-pen", HWLABEL_16BITS, (HWLABEL_R | HWLABEL_O) },\r | |
59 | { 0xF00010, "OB[0]", "Object Code", HWLABEL_16BITS, (HWLABEL_R | HWLABEL_O) },\r | |
60 | { 0xF00012, "OB[1]", "Object Code", HWLABEL_16BITS, (HWLABEL_R | HWLABEL_O) },\r | |
61 | { 0xF00014, "OB[2]", "Object Code", HWLABEL_16BITS, (HWLABEL_R | HWLABEL_O) },\r | |
62 | { 0xF00016, "OB[3]", "Object Code", HWLABEL_16BITS, (HWLABEL_R | HWLABEL_O) },\r | |
63 | { 0xF00020, "OLP", "Object List Pointer", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },\r | |
64 | { 0xF00026, "OBF", "Object Processor flag", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },\r | |
65 | { 0xF00028, "VMODE", "Video Mode", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },\r | |
66 | { 0xF0002A, "BORD1", "Border Colour (Red & Green)", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },\r | |
67 | { 0xF0002C, "BORD2", "Border Colour (Blue)", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },\r | |
68 | { 0xF0002E, "HP", "Horizontal Period", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },\r | |
69 | { 0xF00030, "HBB", "Horizontal Blanking Begin", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },\r | |
70 | { 0xF00032, "HBE", "Horizontal Blanking End", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },\r | |
71 | { 0xF00034, "HS", "Horizontal Sync", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },\r | |
72 | { 0xF00036, "HVS", "Horizontal Vertical Sync", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },\r | |
73 | { 0xF00038, "HDB1", "Horizontal Display Begin 1", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },\r | |
74 | { 0xF0003A, "HDB2", "Horizontal Display Begin 2", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },\r | |
75 | { 0xF0003C, "HDE", "Horizontal Display End", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },\r | |
76 | { 0xF0003E, "VP", "Vertical Period", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },\r | |
77 | { 0xF00040, "VBB", "Vertical Blanking Begin", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },\r | |
78 | { 0xF00042, "VBE", "Vertical Blanking End", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },\r | |
79 | { 0xF00044, "VS", "Vertical Sync", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },\r | |
80 | { 0xF00046, "VDB", "Vertical Display Begin", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },\r | |
81 | { 0xF00048, "VDE", "Vertical Display End", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },\r | |
82 | { 0xF0004A, "VEB", "Vertical Equalization Begin", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },\r | |
83 | { 0xF0004C, "VEE", "Vertical Equalization End", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },\r | |
84 | { 0xF0004E, "VI", "Vertical Interrupt", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },\r | |
85 | { 0xF00050, "PIT[0]", "Programmable Interrupt Timer", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },\r | |
86 | { 0xF00052, "PIT[1]", "Programmable Interrupt Timer", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },\r | |
87 | { 0xF00054, "HEQ", "Horizontal equalization end", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },\r | |
88 | { 0xF00058, "BG", "Background Colour", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },\r | |
89 | { 0xF000E0, "INT1", "CPU Interrupt Control Register", HWLABEL_16BITS, (HWLABEL_R | HWLABEL_W) },\r | |
90 | { 0xF000E2, "INT2", "CPU Interrupt resume register", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },\r | |
91 | { 0xF00400, "CLUT", "Colour Look-Up Table", HWLABEL_16BITS, (HWLABEL_R | HWLABEL_W) },\r | |
92 | { 0xF00800, "LBUF", "Line Buffer A", HWLABEL_32BITS, (HWLABEL_R | HWLABEL_W) },\r | |
93 | { 0xF01000, "LBUF", "Line Buffer B", HWLABEL_32BITS, (HWLABEL_R | HWLABEL_W) },\r | |
94 | { 0xF01800, "LBUF", "Line Buffer selected for writing", HWLABEL_32BITS, (HWLABEL_R | HWLABEL_W) },\r | |
95 | // Internal registers of the Graphics processor\r | |
96 | { 0xF02100, "G_FLAGS", "GPU Flags Register", HWLABEL_32BITS, (HWLABEL_R | HWLABEL_W) },\r | |
97 | { 0xF02104, "G_MTXC", "Matrix Control Register", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },\r | |
98 | { 0xF02108, "G_MTXA", "Matrix Address Register", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },\r | |
99 | { 0xF0210C, "G_END", "Data Organisation Register", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },\r | |
100 | { 0xF02110, "G_PC", "GPU Program Counter", HWLABEL_32BITS, (HWLABEL_R | HWLABEL_W) },\r | |
101 | { 0xF02114, "G_CTRL", "GPU Control/Status Register", HWLABEL_32BITS, (HWLABEL_R | HWLABEL_W) },\r | |
102 | { 0xF02118, "G_HIDATA", "High Data Register", HWLABEL_32BITS, (HWLABEL_R | HWLABEL_W) },\r | |
103 | { 0xF0211C, "G_REMAIN", "Divide unit remainder", HWLABEL_32BITS, (HWLABEL_R | HWLABEL_O) },\r | |
104 | { 0xF0211C, "G_DIVCTRL", "Divide unit Control", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },\r | |
105 | // List of all the externally accessible locations within the Blitter.\r | |
106 | { 0xF02200, "A1_BASE", "A1 Base Register", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },\r | |
107 | { 0xF02204, "A1_FLAGS", "A1 Flags Register", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },\r | |
108 | { 0xF02208, "A1_CLIP", "A1 Clipping Size", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },\r | |
109 | { 0xF0220C, "A1_PIXEL", "A1 Pixel Pointer", HWLABEL_32BITS, (HWLABEL_R | HWLABEL_W) },\r | |
110 | { 0xF02210, "A1_STEP", "A1 Step Value", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },\r | |
111 | { 0xF02214, "A1_FSTEP", "A1 Step Fraction Value", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },\r | |
112 | { 0xF02218, "A1_FPIXEL", "A1 Pixel Pointer Fraction", HWLABEL_32BITS, (HWLABEL_R | HWLABEL_W) },\r | |
113 | { 0xF0221C, "A1_INC", "A1 Increment", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },\r | |
114 | { 0xF02220, "A1_FINC", "A1 Increment Fraction", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },\r | |
115 | { 0xF02224, "A2_BASE", "A2 Base Register", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },\r | |
116 | { 0xF02228, "A2_FLAGS", "A2 Flags Register", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },\r | |
117 | { 0xF0222C, "A2_MASK", "A2 Window Mask", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },\r | |
118 | { 0xF02230, "A2_PIXEL", "A2 Pixel Pointer", HWLABEL_32BITS, (HWLABEL_R | HWLABEL_W) },\r | |
119 | { 0xF02234, "A2_STEP", "A2 Step Value", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },\r | |
120 | { 0xF02238, "B_CMD", "Command Register", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },\r | |
121 | { 0xF02238, "B_CMD", "Status Register", HWLABEL_32BITS, (HWLABEL_R | HWLABEL_O) },\r | |
122 | { 0xF0223C, "B_COUNT", "Counters Register", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },\r | |
123 | { 0xF02240, "B_SRCD", "Source Data Register", HWLABEL_64BITS, (HWLABEL_W | HWLABEL_O) },\r | |
124 | { 0xF02248, "B_DSTD", "Destination Data Register", HWLABEL_64BITS, (HWLABEL_W | HWLABEL_O) },\r | |
125 | { 0xF02250, "B_DSTZ", "Destination Z Register", HWLABEL_64BITS, (HWLABEL_W | HWLABEL_O) },\r | |
126 | { 0xF02258, "B_SRCZ1", "Source Z Register 1", HWLABEL_64BITS, (HWLABEL_W | HWLABEL_O) },\r | |
127 | { 0xF02260, "B_SRCZ2", "Source Z Register 2", HWLABEL_64BITS, (HWLABEL_W | HWLABEL_O) },\r | |
128 | { 0xF02268, "B_PATD", "Pattern Data Register", HWLABEL_64BITS, (HWLABEL_W | HWLABEL_O) },\r | |
129 | { 0xF02270, "B_IINC", "Intensity Increment", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },\r | |
130 | { 0xF02274, "B_ZINC", "Z Increment", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },\r | |
131 | { 0xF02278, "B_STOP", "Collision control", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },\r | |
132 | { 0xF0227C, "B_I3", "Intensity 3", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },\r | |
133 | { 0xF02280, "B_I2", "Intensity 2", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },\r | |
134 | { 0xF02284, "B_I1", "Intensity 1", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },\r | |
135 | { 0xF02288, "B_I0", "Intensity 0", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },\r | |
136 | { 0xF0228C, "B_Z3", "Z 3", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },\r | |
137 | { 0xF02290, "B_Z2", "Z 2", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },\r | |
138 | { 0xF02294, "B_Z1", "Z 1", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },\r | |
139 | { 0xF02298, "B_Z0", "Z 0", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },\r | |
140 | // GPU Ram base\r | |
141 | //{ 0xF03000, "GPU_RAMBASE", "Local RAM base", HWLABEL_8BITS, (HWLABEL_R | HWLABEL_W) },\r | |
142 | // Frequency dividers\r | |
143 | { 0xF10010, "CLK1", "Processor clock divider", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },\r | |
144 | { 0xF10012, "CLK2", "Video clock divider", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },\r | |
145 | { 0xF10014, "CLK3", "Chroma clock divider", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },\r | |
146 | // Programmable Timers\r | |
147 | { 0xF10000, "JPIT1", "Timer 1 Pre-scaler", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },\r | |
148 | { 0xF10004, "JPIT3", "Timer 2 Pre-scaler", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },\r | |
149 | { 0xF10002, "JPIT2", "Timer 1 Divider", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },\r | |
150 | { 0xF10006, "JPIT4", "Timer 2 Divider", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },\r | |
151 | //{ 0xF10036, "JPIT1", "Timer 1 Pre-scaler", HWLABEL_16BITS, (HWLABEL_R | HWLABEL_O) },\r | |
152 | //{ 0xF10038, "JPIT2", "Timer 1 Divider", HWLABEL_16BITS, (HWLABEL_R | HWLABEL_O) },\r | |
153 | //{ 0xF1003A, "JPIT3", "Timer 2 Pre-scaler", HWLABEL_16BITS, (HWLABEL_R | HWLABEL_O) },\r | |
154 | //{ 0xF1003C, "JPIT4", "Timer 2 Divider", HWLABEL_16BITS, (HWLABEL_R | HWLABEL_O) },\r | |
155 | // Interrupts\r | |
156 | { 0xF10020, "JINTCTRL", "Interrupt Control Register", HWLABEL_16BITS, (HWLABEL_R | HWLABEL_W) },\r | |
157 | // JERRY Pulse Width Modulation DACs\r | |
158 | //{ 0xF1A140, "DAC1", "Left DAC", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },\r | |
159 | //{ 0xF1A144, "DAC2", "Right DAC", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },\r | |
160 | // Synchronous Serial Interface\r | |
161 | { 0xF1A150, "SCLK", "Serial Clock Frequency", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },\r | |
162 | { 0xF1A154, "SMODE", "Serial Mode", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },\r | |
163 | { 0xF1A148, "R_DAC", "Right transmit data (to DACs)", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },\r | |
164 | { 0xF1A14C, "L_DAC", "Left transmit data (to DACs)", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },\r | |
165 | { 0xF1A148, "LTXD", "Left transmit data (to I2S)", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },\r | |
166 | { 0xF1A14C, "RTXD", "Right transmit data (to I2S)", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },\r | |
167 | { 0xF1A148, "LRXD", "Left receive data (to I2S)", HWLABEL_32BITS, (HWLABEL_R | HWLABEL_O) },\r | |
168 | { 0xF1A14C, "RRXD", "Right receive data (to I2S)", HWLABEL_32BITS, (HWLABEL_R | HWLABEL_O) },\r | |
169 | { 0xF1A150, "SSTAT", "Serial Status", HWLABEL_32BITS, (HWLABEL_R | HWLABEL_O) },\r | |
170 | // Asynchronous Serial Interface (ComLynx and Midi)\r | |
171 | { 0xF10034, "ASICLK", "Asynchronous Serial Interface Clock", HWLABEL_16BITS, (HWLABEL_R | HWLABEL_W) },\r | |
172 | { 0xF10032, "ASICTRL", "Asynchronous Serial Control", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },\r | |
173 | { 0xF10032, "ASISTAT", "Asynchronous Serial Status", HWLABEL_16BITS, (HWLABEL_R | HWLABEL_O) },\r | |
174 | { 0xF10030, "ASIDATA", "Asynchronous Serial Data", HWLABEL_16BITS, (HWLABEL_R | HWLABEL_W) },\r | |
175 | // Joystick Interface\r | |
176 | { 0xF14000, "JOYSTICK", "Joystick register", HWLABEL_16BITS, (HWLABEL_R | HWLABEL_W) },\r | |
177 | { 0xF14002, "JOYBUTS", "Button register", HWLABEL_16BITS, (HWLABEL_R | HWLABEL_W) },\r | |
178 | // Internal Registers\r | |
179 | { 0xF1A100, "D_FLAGS", "DSP Flags Register", HWLABEL_32BITS, (HWLABEL_R | HWLABEL_W) },\r | |
180 | { 0xF1A104, "D_MTXC", "DSP Matrix Control Register", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },\r | |
181 | { 0xF1A108, "D_MTXA", "DSP Matrix Address Register", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },\r | |
182 | { 0xF1A10C, "D_END", "DSP Data Organisation Register", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },\r | |
183 | { 0xF1A110, "D_PC", "DSP Program Counter", HWLABEL_32BITS, (HWLABEL_R | HWLABEL_W) },\r | |
184 | { 0xF1A114, "D_CTRL", "DSP Control/Status Register", HWLABEL_32BITS, (HWLABEL_R | HWLABEL_W) },\r | |
185 | { 0xF1A118, "D_MOD", "Modulo instruction mask", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },\r | |
186 | { 0xF1A11C, "D_REMAIN", "Divide unit remainder", HWLABEL_32BITS, (HWLABEL_R | HWLABEL_W) },\r | |
187 | { 0xF1A11C, "D_DIVCTRL", "Divide unit Control", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },\r | |
188 | { 0xF1A120, "D_MACHI", "Multiply & Acccumulate High Bits", HWLABEL_32BITS, (HWLABEL_R | HWLABEL_O) },\r | |
189 | // End of the Memory map list\r | |
190 | // { (size_t)-1, NULL, NULL, HWLABEL_NO_SIZE, HWLABEL_NO_ACCESS }\r | |
191 | };\r | |
192 | \r | |
193 | \r | |
194 | // Get Symbol name from his address\r | |
195 | char *HWLABELManager_GetSymbolnameFromAdr(size_t Adr)\r | |
196 | {\r | |
197 | size_t i;\r | |
198 | \r | |
199 | if ((Adr >= 0xF00000) && (Adr < 0xF1A124))\r | |
200 | {\r | |
201 | for (i = 0; i < NBHWLABELS; i++)\r | |
202 | {\r | |
203 | if ((HWLABELTabSectionType[i].HWLABELAdr == Adr))\r | |
204 | {\r | |
205 | return (char *)HWLABELTabSectionType[i].HWLABELSymbolName;\r | |
206 | }\r | |
207 | }\r | |
208 | }\r | |
209 | \r | |
210 | return NULL;\r | |
211 | \r | |
212 | //while ((HWLABELTabSectionType[i].HWLABELAdr != Adr) && (HWLABELTabSectionType[i++].HWLABELAdr != (size_t)-1));\r | |
213 | //return (char *)HWLABELTabSectionType[i].HWLABELSymbolName;\r | |
214 | }\r | |
215 | \r |