gcc4mbed/external/mbed/LPC2368/LPC23xx.h

   1 /* mbed Microcontroller Library - LPC23xx CMSIS-like structs
   2  * Copyright (C) 2009 ARM Limited. All rights reserved.
   3  *
   4  * An LPC23xx header file, based on the CMSIS LPC17xx.h and old LPC23xx.h
   5  */
   6
   7 #ifndef __LPC23xx_H
   8 #define __LPC23xx_H
   9
  10 #ifdef __cplusplus
  11  extern "C" {
  12 #endif
  13
  14 /*
  15  * ==========================================================================
  16  * ---------- Interrupt Number Definition -----------------------------------
  17  * ==========================================================================
  18  */
  19
  20 typedef enum IRQn
  21 {
  22 /******  LPC23xx Specific Interrupt Numbers *******************************************************/
  23   WDT_IRQn                      = 0,        /*!< Watchdog Timer Interrupt                         */
  24
  25   TIMER0_IRQn                   = 4,        /*!< Timer0 Interrupt                                 */
  26   TIMER1_IRQn                   = 5,        /*!< Timer1 Interrupt                                 */
  27   UART0_IRQn                    = 6,        /*!< UART0 Interrupt                                  */
  28   UART1_IRQn                    = 7,        /*!< UART1 Interrupt                                  */
  29   PWM1_IRQn                     = 8,        /*!< PWM1 Interrupt                                   */
  30   I2C0_IRQn                     = 9,        /*!< I2C0 Interrupt                                   */
  31   SPI_IRQn                      = 10,       /*!< SPI Interrupt                                    */
  32   SSP0_IRQn                     = 10,       /*!< SSP0 Interrupt                                   */
  33   SSP1_IRQn                     = 11,       /*!< SSP1 Interrupt                                   */
  34   PLL0_IRQn                     = 12,       /*!< PLL0 Lock (Main PLL) Interrupt                   */
  35   RTC_IRQn                      = 13,       /*!< Real Time Clock Interrupt                        */
  36   EINT0_IRQn                    = 14,       /*!< External Interrupt 0 Interrupt                   */
  37   EINT1_IRQn                    = 15,       /*!< External Interrupt 1 Interrupt                   */
  38   EINT2_IRQn                    = 16,       /*!< External Interrupt 2 Interrupt                   */
  39   EINT3_IRQn                    = 17,       /*!< External Interrupt 3 Interrupt                   */
  40   ADC_IRQn                      = 18,       /*!< A/D Converter Interrupt                          */
  41   I2C1_IRQn                     = 19,       /*!< I2C1 Interrupt                                   */
  42   BOD_IRQn                      = 20,       /*!< Brown-Out Detect Interrupt                       */
  43   ENET_IRQn                     = 21,       /*!< Ethernet Interrupt                               */
  44   USB_IRQn                      = 22,       /*!< USB Interrupt                                    */
  45   CAN_IRQn                      = 23,       /*!< CAN Interrupt                                    */
  46   MIC_IRQn                      = 24,       /*!< Multimedia Interface Controler                   */
  47   DMA_IRQn                      = 25,       /*!< General Purpose DMA Interrupt                    */
  48   TIMER2_IRQn                   = 26,       /*!< Timer2 Interrupt                                 */
  49   TIMER3_IRQn                   = 27,       /*!< Timer3 Interrupt                                 */
  50   UART2_IRQn                    = 28,       /*!< UART2 Interrupt                                  */
  51   UART3_IRQn                    = 29,       /*!< UART3 Interrupt                                  */
  52   I2C2_IRQn                     = 30,       /*!< I2C2 Interrupt                                   */
  53   I2S_IRQn                      = 31,       /*!< I2S Interrupt                                    */
  54 } IRQn_Type;
  55
  56 /*
  57  * ==========================================================================
  58  * ----------- Processor and Core Peripheral Section ------------------------
  59  * ==========================================================================
  60  */
  61
  62 /* Configuration of the ARM7 Processor and Core Peripherals */
  63 #define __MPU_PRESENT             0         /*!< MPU present or not                               */
  64 #define __NVIC_PRIO_BITS          4         /*!< Number of Bits used for Priority Levels          */
  65 #define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used     */
  66
  67
  68 #include <core_arm7.h>
  69 #include "system_LPC23xx.h"                 /* System Header                                      */
  70
  71
  72 /******************************************************************************/
  73 /*                Device Specific Peripheral registers structures             */
  74 /******************************************************************************/
  75
  76 #pragma anon_unions
  77
  78 /*------------- Vector Interupt Controler (VIC) ------------------------------*/
  79 typedef struct
  80 {
  81   __I  uint32_t IRQStatus;
  82   __I  uint32_t FIQStatus;
  83   __I  uint32_t RawIntr;
  84   __IO uint32_t IntSelect;
  85   __IO uint32_t IntEnable;
  86   __O  uint32_t IntEnClr;
  87   __IO uint32_t SoftInt;
  88   __O  uint32_t SoftIntClr;
  89   __IO uint32_t Protection;
  90   __IO uint32_t SWPriorityMask;
  91   __IO uint32_t RESERVED0[54];
  92   __IO uint32_t VectAddr[32];
  93   __IO uint32_t RESERVED1[32];
  94   __IO uint32_t VectPriority[32];
  95   __IO uint32_t RESERVED2[800];
  96   __IO uint32_t Address;
  97 } LPC_VIC_TypeDef;
  98
  99 /*------------- System Control (SC) ------------------------------------------*/
 100 typedef struct
 101 {
 102   __IO uint32_t MAMCR;
 103   __IO uint32_t MAMTIM;
 104        uint32_t RESERVED0[14];
 105   __IO uint32_t MEMMAP;
 106        uint32_t RESERVED1[15];
 107   __IO uint32_t PLL0CON;                /* Clocking and Power Control         */
 108   __IO uint32_t PLL0CFG;
 109   __I  uint32_t PLL0STAT;
 110   __O  uint32_t PLL0FEED;
 111        uint32_t RESERVED2[12];
 112   __IO uint32_t PCON;
 113   __IO uint32_t PCONP;
 114        uint32_t RESERVED3[15];
 115   __IO uint32_t CCLKCFG;
 116   __IO uint32_t USBCLKCFG;
 117   __IO uint32_t CLKSRCSEL;
 118        uint32_t RESERVED4[12];
 119   __IO uint32_t EXTINT;                 /* External Interrupts                */
 120   __IO uint32_t INTWAKE;
 121   __IO uint32_t EXTMODE;
 122   __IO uint32_t EXTPOLAR;
 123        uint32_t RESERVED6[12];
 124   __IO uint32_t RSID;                   /* Reset                              */
 125   __IO uint32_t CSPR;
 126   __IO uint32_t AHBCFG1;
 127   __IO uint32_t AHBCFG2;
 128        uint32_t RESERVED7[4];
 129   __IO uint32_t SCS;                    /* Syscon Miscellaneous Registers     */
 130   __IO uint32_t IRCTRIM;                /* Clock Dividers                     */
 131   __IO uint32_t PCLKSEL0;
 132   __IO uint32_t PCLKSEL1;
 133        uint32_t RESERVED8[4];
 134   __IO uint32_t USBIntSt;               /* USB Device/OTG Interrupt Register  */
 135        uint32_t RESERVED9;
 136 //  __IO uint32_t CLKOUTCFG;              /* Clock Output Configuration         */
 137  } LPC_SC_TypeDef;
 138
 139 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
 140 typedef struct
 141 {
 142   __IO uint32_t PINSEL0;
 143   __IO uint32_t PINSEL1;
 144   __IO uint32_t PINSEL2;
 145   __IO uint32_t PINSEL3;
 146   __IO uint32_t PINSEL4;
 147   __IO uint32_t PINSEL5;
 148   __IO uint32_t PINSEL6;
 149   __IO uint32_t PINSEL7;
 150   __IO uint32_t PINSEL8;
 151   __IO uint32_t PINSEL9;
 152   __IO uint32_t PINSEL10;
 153        uint32_t RESERVED0[5];
 154   __IO uint32_t PINMODE0;
 155   __IO uint32_t PINMODE1;
 156   __IO uint32_t PINMODE2;
 157   __IO uint32_t PINMODE3;
 158   __IO uint32_t PINMODE4;
 159   __IO uint32_t PINMODE5;
 160   __IO uint32_t PINMODE6;
 161   __IO uint32_t PINMODE7;
 162   __IO uint32_t PINMODE8;
 163   __IO uint32_t PINMODE9;
 164   __IO uint32_t PINMODE_OD0;
 165   __IO uint32_t PINMODE_OD1;
 166   __IO uint32_t PINMODE_OD2;
 167   __IO uint32_t PINMODE_OD3;
 168   __IO uint32_t PINMODE_OD4;
 169 } LPC_PINCON_TypeDef;
 170
 171 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
 172 typedef struct
 173 {
 174   __IO uint32_t FIODIR;
 175        uint32_t RESERVED0[3];
 176   __IO uint32_t FIOMASK;
 177   __IO uint32_t FIOPIN;
 178   __IO uint32_t FIOSET;
 179   __O  uint32_t FIOCLR;
 180 } LPC_GPIO_TypeDef;
 181
 182 typedef struct
 183 {
 184   __I  uint32_t IntStatus;
 185   __I  uint32_t IO0IntStatR;
 186   __I  uint32_t IO0IntStatF;
 187   __O  uint32_t IO0IntClr;
 188   __IO uint32_t IO0IntEnR;
 189   __IO uint32_t IO0IntEnF;
 190        uint32_t RESERVED0[3];
 191   __I  uint32_t IO2IntStatR;
 192   __I  uint32_t IO2IntStatF;
 193   __O  uint32_t IO2IntClr;
 194   __IO uint32_t IO2IntEnR;
 195   __IO uint32_t IO2IntEnF;
 196 } LPC_GPIOINT_TypeDef;
 197
 198 /*------------- Timer (TIM) --------------------------------------------------*/
 199 typedef struct
 200 {
 201   __IO uint32_t IR;
 202   __IO uint32_t TCR;
 203   __IO uint32_t TC;
 204   __IO uint32_t PR;
 205   __IO uint32_t PC;
 206   __IO uint32_t MCR;
 207   __IO uint32_t MR0;
 208   __IO uint32_t MR1;
 209   __IO uint32_t MR2;
 210   __IO uint32_t MR3;
 211   __IO uint32_t CCR;
 212   __I  uint32_t CR0;
 213   __I  uint32_t CR1;
 214        uint32_t RESERVED0[2];
 215   __IO uint32_t EMR;
 216        uint32_t RESERVED1[12];
 217   __IO uint32_t CTCR;
 218 } LPC_TIM_TypeDef;
 219
 220 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
 221 typedef struct
 222 {
 223   __IO uint32_t IR;
 224   __IO uint32_t TCR;
 225   __IO uint32_t TC;
 226   __IO uint32_t PR;
 227   __IO uint32_t PC;
 228   __IO uint32_t MCR;
 229   __IO uint32_t MR0;
 230   __IO uint32_t MR1;
 231   __IO uint32_t MR2;
 232   __IO uint32_t MR3;
 233   __IO uint32_t CCR;
 234   __I  uint32_t CR0;
 235   __I  uint32_t CR1;
 236   __I  uint32_t CR2;
 237   __I  uint32_t CR3;
 238        uint32_t RESERVED0;
 239   __IO uint32_t MR4;
 240   __IO uint32_t MR5;
 241   __IO uint32_t MR6;
 242   __IO uint32_t PCR;
 243   __IO uint32_t LER;
 244        uint32_t RESERVED1[7];
 245   __IO uint32_t CTCR;
 246 } LPC_PWM_TypeDef;
 247
 248 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
 249 typedef struct
 250 {
 251   union {
 252   __I  uint8_t  RBR;
 253   __O  uint8_t  THR;
 254   __IO uint8_t  DLL;
 255        uint32_t RESERVED0;
 256   };
 257   union {
 258   __IO uint8_t  DLM;
 259   __IO uint32_t IER;
 260   };
 261   union {
 262   __I  uint32_t IIR;
 263   __O  uint8_t  FCR;
 264   };
 265   __IO uint8_t  LCR;
 266        uint8_t  RESERVED1[7];
 267   __IO uint8_t  LSR;
 268        uint8_t  RESERVED2[7];
 269   __IO uint8_t  SCR;
 270        uint8_t  RESERVED3[3];
 271   __IO uint32_t ACR;
 272   __IO uint8_t  ICR;
 273        uint8_t  RESERVED4[3];
 274   __IO uint8_t  FDR;
 275        uint8_t  RESERVED5[7];
 276   __IO uint8_t  TER;
 277        uint8_t  RESERVED6[27];
 278   __IO uint8_t  RS485CTRL;
 279        uint8_t  RESERVED7[3];
 280   __IO uint8_t  ADRMATCH;
 281 } LPC_UART_TypeDef;
 282
 283 typedef struct
 284 {
 285   union {
 286   __I  uint8_t  RBR;
 287   __O  uint8_t  THR;
 288   __IO uint8_t  DLL;
 289        uint32_t RESERVED0;
 290   };
 291   union {
 292   __IO uint8_t  DLM;
 293   __IO uint32_t IER;
 294   };
 295   union {
 296   __I  uint32_t IIR;
 297   __O  uint8_t  FCR;
 298   };
 299   __IO uint8_t  LCR;
 300        uint8_t  RESERVED1[3];
 301   __IO uint8_t  MCR;
 302        uint8_t  RESERVED2[3];
 303   __IO uint8_t  LSR;
 304        uint8_t  RESERVED3[3];
 305   __IO uint8_t  MSR;
 306        uint8_t  RESERVED4[3];
 307   __IO uint8_t  SCR;
 308        uint8_t  RESERVED5[3];
 309   __IO uint32_t ACR;
 310        uint32_t RESERVED6;
 311   __IO uint32_t FDR;
 312        uint32_t RESERVED7;
 313   __IO uint8_t  TER;
 314        uint8_t  RESERVED8[27];
 315   __IO uint8_t  RS485CTRL;
 316        uint8_t  RESERVED9[3];
 317   __IO uint8_t  ADRMATCH;
 318        uint8_t  RESERVED10[3];
 319   __IO uint8_t  RS485DLY;
 320 } LPC_UART1_TypeDef;
 321
 322 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/
 323 typedef struct
 324 {
 325   __IO uint32_t SPCR;
 326   __I  uint32_t SPSR;
 327   __IO uint32_t SPDR;
 328   __IO uint32_t SPCCR;
 329        uint32_t RESERVED0[3];
 330   __IO uint32_t SPINT;
 331 } LPC_SPI_TypeDef;
 332
 333 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
 334 typedef struct
 335 {
 336   __IO uint32_t CR0;
 337   __IO uint32_t CR1;
 338   __IO uint32_t DR;
 339   __I  uint32_t SR;
 340   __IO uint32_t CPSR;
 341   __IO uint32_t IMSC;
 342   __IO uint32_t RIS;
 343   __IO uint32_t MIS;
 344   __IO uint32_t ICR;
 345   __IO uint32_t DMACR;
 346 } LPC_SSP_TypeDef;
 347
 348 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
 349 typedef struct
 350 {
 351   __IO uint32_t I2CONSET;
 352   __I  uint32_t I2STAT;
 353   __IO uint32_t I2DAT;
 354   __IO uint32_t I2ADR0;
 355   __IO uint32_t I2SCLH;
 356   __IO uint32_t I2SCLL;
 357   __O  uint32_t I2CONCLR;
 358   __IO uint32_t MMCTRL;
 359   __IO uint32_t I2ADR1;
 360   __IO uint32_t I2ADR2;
 361   __IO uint32_t I2ADR3;
 362   __I  uint32_t I2DATA_BUFFER;
 363   __IO uint32_t I2MASK0;
 364   __IO uint32_t I2MASK1;
 365   __IO uint32_t I2MASK2;
 366   __IO uint32_t I2MASK3;
 367 } LPC_I2C_TypeDef;
 368
 369 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
 370 typedef struct
 371 {
 372   __IO uint32_t I2SDAO;
 373   __I  uint32_t I2SDAI;
 374   __O  uint32_t I2STXFIFO;
 375   __I  uint32_t I2SRXFIFO;
 376   __I  uint32_t I2SSTATE;
 377   __IO uint32_t I2SDMA1;
 378   __IO uint32_t I2SDMA2;
 379   __IO uint32_t I2SIRQ;
 380   __IO uint32_t I2STXRATE;
 381   __IO uint32_t I2SRXRATE;
 382   __IO uint32_t I2STXBITRATE;
 383   __IO uint32_t I2SRXBITRATE;
 384   __IO uint32_t I2STXMODE;
 385   __IO uint32_t I2SRXMODE;
 386 } LPC_I2S_TypeDef;
 387
 388 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
 389 typedef struct
 390 {
 391   __IO uint8_t  ILR;
 392        uint8_t  RESERVED0[3];
 393   __IO uint8_t  CTC;
 394        uint8_t  RESERVED1[3];
 395   __IO uint8_t  CCR;
 396        uint8_t  RESERVED2[3];
 397   __IO uint8_t  CIIR;
 398        uint8_t  RESERVED3[3];
 399   __IO uint8_t  AMR;
 400        uint8_t  RESERVED4[3];
 401   __I  uint32_t CTIME0;
 402   __I  uint32_t CTIME1;
 403   __I  uint32_t CTIME2;
 404   __IO uint8_t  SEC;
 405        uint8_t  RESERVED5[3];
 406   __IO uint8_t  MIN;
 407        uint8_t  RESERVED6[3];
 408   __IO uint8_t  HOUR;
 409        uint8_t  RESERVED7[3];
 410   __IO uint8_t  DOM;
 411        uint8_t  RESERVED8[3];
 412   __IO uint8_t  DOW;
 413        uint8_t  RESERVED9[3];
 414   __IO uint16_t DOY;
 415        uint16_t RESERVED10;
 416   __IO uint8_t  MONTH;
 417        uint8_t  RESERVED11[3];
 418   __IO uint16_t YEAR;
 419        uint16_t RESERVED12;
 420   __IO uint32_t CALIBRATION;
 421   __IO uint32_t GPREG0;
 422   __IO uint32_t GPREG1;
 423   __IO uint32_t GPREG2;
 424   __IO uint32_t GPREG3;
 425   __IO uint32_t GPREG4;
 426   __IO uint8_t  WAKEUPDIS;
 427        uint8_t  RESERVED13[3];
 428   __IO uint8_t  PWRCTRL;
 429        uint8_t  RESERVED14[3];
 430   __IO uint8_t  ALSEC;
 431        uint8_t  RESERVED15[3];
 432   __IO uint8_t  ALMIN;
 433        uint8_t  RESERVED16[3];
 434   __IO uint8_t  ALHOUR;
 435        uint8_t  RESERVED17[3];
 436   __IO uint8_t  ALDOM;
 437        uint8_t  RESERVED18[3];
 438   __IO uint8_t  ALDOW;
 439        uint8_t  RESERVED19[3];
 440   __IO uint16_t ALDOY;
 441        uint16_t RESERVED20;
 442   __IO uint8_t  ALMON;
 443        uint8_t  RESERVED21[3];
 444   __IO uint16_t ALYEAR;
 445        uint16_t RESERVED22;
 446 } LPC_RTC_TypeDef;
 447
 448 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
 449 typedef struct
 450 {
 451   __IO uint8_t  WDMOD;
 452        uint8_t  RESERVED0[3];
 453   __IO uint32_t WDTC;
 454   __O  uint8_t  WDFEED;
 455        uint8_t  RESERVED1[3];
 456   __I  uint32_t WDTV;
 457   __IO uint32_t WDCLKSEL;
 458 } LPC_WDT_TypeDef;
 459
 460 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
 461 typedef struct
 462 {
 463   __IO uint32_t ADCR;
 464   __IO uint32_t ADGDR;
 465        uint32_t RESERVED0;
 466   __IO uint32_t ADINTEN;
 467   __I  uint32_t ADDR0;
 468   __I  uint32_t ADDR1;
 469   __I  uint32_t ADDR2;
 470   __I  uint32_t ADDR3;
 471   __I  uint32_t ADDR4;
 472   __I  uint32_t ADDR5;
 473   __I  uint32_t ADDR6;
 474   __I  uint32_t ADDR7;
 475   __I  uint32_t ADSTAT;
 476   __IO uint32_t ADTRM;
 477 } LPC_ADC_TypeDef;
 478
 479 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
 480 typedef struct
 481 {
 482   __IO uint32_t DACR;
 483   __IO uint32_t DACCTRL;
 484   __IO uint16_t DACCNTVAL;
 485 } LPC_DAC_TypeDef;
 486
 487 /*------------- Multimedia Card Interface (MCI) ------------------------------*/
 488 typedef struct
 489 {
 490   __IO uint32_t MCIPower;               /* Power control                      */
 491   __IO uint32_t MCIClock;               /* Clock control                      */
 492   __IO uint32_t MCIArgument;
 493   __IO uint32_t MMCCommand;
 494   __I  uint32_t MCIRespCmd;
 495   __I  uint32_t MCIResponse0;
 496   __I  uint32_t MCIResponse1;
 497   __I  uint32_t MCIResponse2;
 498   __I  uint32_t MCIResponse3;
 499   __IO uint32_t MCIDataTimer;
 500   __IO uint32_t MCIDataLength;
 501   __IO uint32_t MCIDataCtrl;
 502   __I  uint32_t MCIDataCnt;
 503 } LPC_MCI_TypeDef;
 504
 505 /*------------- Controller Area Network (CAN) --------------------------------*/
 506 typedef struct
 507 {
 508   __IO uint32_t mask[512];              /* ID Masks                           */
 509 } LPC_CANAF_RAM_TypeDef;
 510
 511 typedef struct                          /* Acceptance Filter Registers        */
 512 {
 513   __IO uint32_t AFMR;
 514   __IO uint32_t SFF_sa;
 515   __IO uint32_t SFF_GRP_sa;
 516   __IO uint32_t EFF_sa;
 517   __IO uint32_t EFF_GRP_sa;
 518   __IO uint32_t ENDofTable;
 519   __I  uint32_t LUTerrAd;
 520   __I  uint32_t LUTerr;
 521 } LPC_CANAF_TypeDef;
 522
 523 typedef struct                          /* Central Registers                  */
 524 {
 525   __I  uint32_t CANTxSR;
 526   __I  uint32_t CANRxSR;
 527   __I  uint32_t CANMSR;
 528 } LPC_CANCR_TypeDef;
 529
 530 typedef struct                          /* Controller Registers               */
 531 {
 532   __IO uint32_t MOD;
 533   __O  uint32_t CMR;
 534   __IO uint32_t GSR;
 535   __I  uint32_t ICR;
 536   __IO uint32_t IER;
 537   __IO uint32_t BTR;
 538   __IO uint32_t EWL;
 539   __I  uint32_t SR;
 540   __IO uint32_t RFS;
 541   __IO uint32_t RID;
 542   __IO uint32_t RDA;
 543   __IO uint32_t RDB;
 544   __IO uint32_t TFI1;
 545   __IO uint32_t TID1;
 546   __IO uint32_t TDA1;
 547   __IO uint32_t TDB1;
 548   __IO uint32_t TFI2;
 549   __IO uint32_t TID2;
 550   __IO uint32_t TDA2;
 551   __IO uint32_t TDB2;
 552   __IO uint32_t TFI3;
 553   __IO uint32_t TID3;
 554   __IO uint32_t TDA3;
 555   __IO uint32_t TDB3;
 556 } LPC_CAN_TypeDef;
 557
 558 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
 559 typedef struct                          /* Common Registers                   */
 560 {
 561   __I  uint32_t DMACIntStat;
 562   __I  uint32_t DMACIntTCStat;
 563   __O  uint32_t DMACIntTCClear;
 564   __I  uint32_t DMACIntErrStat;
 565   __O  uint32_t DMACIntErrClr;
 566   __I  uint32_t DMACRawIntTCStat;
 567   __I  uint32_t DMACRawIntErrStat;
 568   __I  uint32_t DMACEnbldChns;
 569   __IO uint32_t DMACSoftBReq;
 570   __IO uint32_t DMACSoftSReq;
 571   __IO uint32_t DMACSoftLBReq;
 572   __IO uint32_t DMACSoftLSReq;
 573   __IO uint32_t DMACConfig;
 574   __IO uint32_t DMACSync;
 575 } LPC_GPDMA_TypeDef;
 576
 577 typedef struct                          /* Channel Registers                  */
 578 {
 579   __IO uint32_t DMACCSrcAddr;
 580   __IO uint32_t DMACCDestAddr;
 581   __IO uint32_t DMACCLLI;
 582   __IO uint32_t DMACCControl;
 583   __IO uint32_t DMACCConfig;
 584 } LPC_GPDMACH_TypeDef;
 585
 586 /*------------- Universal Serial Bus (USB) -----------------------------------*/
 587 typedef struct
 588 {
 589   __I  uint32_t HcRevision;             /* USB Host Registers                 */
 590   __IO uint32_t HcControl;
 591   __IO uint32_t HcCommandStatus;
 592   __IO uint32_t HcInterruptStatus;
 593   __IO uint32_t HcInterruptEnable;
 594   __IO uint32_t HcInterruptDisable;
 595   __IO uint32_t HcHCCA;
 596   __I  uint32_t HcPeriodCurrentED;
 597   __IO uint32_t HcControlHeadED;
 598   __IO uint32_t HcControlCurrentED;
 599   __IO uint32_t HcBulkHeadED;
 600   __IO uint32_t HcBulkCurrentED;
 601   __I  uint32_t HcDoneHead;
 602   __IO uint32_t HcFmInterval;
 603   __I  uint32_t HcFmRemaining;
 604   __I  uint32_t HcFmNumber;
 605   __IO uint32_t HcPeriodicStart;
 606   __IO uint32_t HcLSTreshold;
 607   __IO uint32_t HcRhDescriptorA;
 608   __IO uint32_t HcRhDescriptorB;
 609   __IO uint32_t HcRhStatus;
 610   __IO uint32_t HcRhPortStatus1;
 611   __IO uint32_t HcRhPortStatus2;
 612        uint32_t RESERVED0[40];
 613   __I  uint32_t Module_ID;
 614
 615   __I  uint32_t OTGIntSt;               /* USB On-The-Go Registers            */
 616   __IO uint32_t OTGIntEn;
 617   __O  uint32_t OTGIntSet;
 618   __O  uint32_t OTGIntClr;
 619   __IO uint32_t OTGStCtrl;
 620   __IO uint32_t OTGTmr;
 621        uint32_t RESERVED1[58];
 622
 623   __I  uint32_t USBDevIntSt;            /* USB Device Interrupt Registers     */
 624   __IO uint32_t USBDevIntEn;
 625   __O  uint32_t USBDevIntClr;
 626   __O  uint32_t USBDevIntSet;
 627
 628   __O  uint32_t USBCmdCode;             /* USB Device SIE Command Registers   */
 629   __I  uint32_t USBCmdData;
 630
 631   __I  uint32_t USBRxData;              /* USB Device Transfer Registers      */
 632   __O  uint32_t USBTxData;
 633   __I  uint32_t USBRxPLen;
 634   __O  uint32_t USBTxPLen;
 635   __IO uint32_t USBCtrl;
 636   __O  uint32_t USBDevIntPri;
 637
 638   __I  uint32_t USBEpIntSt;             /* USB Device Endpoint Interrupt Regs */
 639   __IO uint32_t USBEpIntEn;
 640   __O  uint32_t USBEpIntClr;
 641   __O  uint32_t USBEpIntSet;
 642   __O  uint32_t USBEpIntPri;
 643
 644   __IO uint32_t USBReEp;                /* USB Device Endpoint Realization Reg*/
 645   __O  uint32_t USBEpInd;
 646   __IO uint32_t USBMaxPSize;
 647
 648   __I  uint32_t USBDMARSt;              /* USB Device DMA Registers           */
 649   __O  uint32_t USBDMARClr;
 650   __O  uint32_t USBDMARSet;
 651        uint32_t RESERVED2[9];
 652   __IO uint32_t USBUDCAH;
 653   __I  uint32_t USBEpDMASt;
 654   __O  uint32_t USBEpDMAEn;
 655   __O  uint32_t USBEpDMADis;
 656   __I  uint32_t USBDMAIntSt;
 657   __IO uint32_t USBDMAIntEn;
 658        uint32_t RESERVED3[2];
 659   __I  uint32_t USBEoTIntSt;
 660   __O  uint32_t USBEoTIntClr;
 661   __O  uint32_t USBEoTIntSet;
 662   __I  uint32_t USBNDDRIntSt;
 663   __O  uint32_t USBNDDRIntClr;
 664   __O  uint32_t USBNDDRIntSet;
 665   __I  uint32_t USBSysErrIntSt;
 666   __O  uint32_t USBSysErrIntClr;
 667   __O  uint32_t USBSysErrIntSet;
 668        uint32_t RESERVED4[15];
 669
 670   __I  uint32_t I2C_RX;                 /* USB OTG I2C Registers              */
 671   __O  uint32_t I2C_WO;
 672   __I  uint32_t I2C_STS;
 673   __IO uint32_t I2C_CTL;
 674   __IO uint32_t I2C_CLKHI;
 675   __O  uint32_t I2C_CLKLO;
 676        uint32_t RESERVED5[823];
 677
 678   union {
 679   __IO uint32_t USBClkCtrl;             /* USB Clock Control Registers        */
 680   __IO uint32_t OTGClkCtrl;
 681   };
 682   union {
 683   __I  uint32_t USBClkSt;
 684   __I  uint32_t OTGClkSt;
 685   };
 686 } LPC_USB_TypeDef;
 687
 688 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
 689 typedef struct
 690 {
 691   __IO uint32_t MAC1;                   /* MAC Registers                      */
 692   __IO uint32_t MAC2;
 693   __IO uint32_t IPGT;
 694   __IO uint32_t IPGR;
 695   __IO uint32_t CLRT;
 696   __IO uint32_t MAXF;
 697   __IO uint32_t SUPP;
 698   __IO uint32_t TEST;
 699   __IO uint32_t MCFG;
 700   __IO uint32_t MCMD;
 701   __IO uint32_t MADR;
 702   __O  uint32_t MWTD;
 703   __I  uint32_t MRDD;
 704   __I  uint32_t MIND;
 705        uint32_t RESERVED0[2];
 706   __IO uint32_t SA0;
 707   __IO uint32_t SA1;
 708   __IO uint32_t SA2;
 709        uint32_t RESERVED1[45];
 710   __IO uint32_t Command;                /* Control Registers                  */
 711   __I  uint32_t Status;
 712   __IO uint32_t RxDescriptor;
 713   __IO uint32_t RxStatus;
 714   __IO uint32_t RxDescriptorNumber;
 715   __I  uint32_t RxProduceIndex;
 716   __IO uint32_t RxConsumeIndex;
 717   __IO uint32_t TxDescriptor;
 718   __IO uint32_t TxStatus;
 719   __IO uint32_t TxDescriptorNumber;
 720   __IO uint32_t TxProduceIndex;
 721   __I  uint32_t TxConsumeIndex;
 722        uint32_t RESERVED2[10];
 723   __I  uint32_t TSV0;
 724   __I  uint32_t TSV1;
 725   __I  uint32_t RSV;
 726        uint32_t RESERVED3[3];
 727   __IO uint32_t FlowControlCounter;
 728   __I  uint32_t FlowControlStatus;
 729        uint32_t RESERVED4[34];
 730   __IO uint32_t RxFilterCtrl;           /* Rx Filter Registers                */
 731   __IO uint32_t RxFilterWoLStatus;
 732   __IO uint32_t RxFilterWoLClear;
 733        uint32_t RESERVED5;
 734   __IO uint32_t HashFilterL;
 735   __IO uint32_t HashFilterH;
 736        uint32_t RESERVED6[882];
 737   __I  uint32_t IntStatus;              /* Module Control Registers           */
 738   __IO uint32_t IntEnable;
 739   __O  uint32_t IntClear;
 740   __O  uint32_t IntSet;
 741        uint32_t RESERVED7;
 742   __IO uint32_t PowerDown;
 743        uint32_t RESERVED8;
 744   __IO uint32_t Module_ID;
 745 } LPC_EMAC_TypeDef;
 746
 747 #pragma no_anon_unions
 748
 749
 750 /******************************************************************************/
 751 /*                         Peripheral memory map                              */
 752 /******************************************************************************/
 753 /* Base addresses                                                             */
 754
 755 /* AHB Peripheral # 0 */
 756
 757 /*
 758 #define FLASH_BASE            (0x00000000UL)
 759 #define RAM_BASE              (0x10000000UL)
 760 #define GPIO_BASE             (0x2009C000UL)
 761 #define APB0_BASE             (0x40000000UL)
 762 #define APB1_BASE             (0x40080000UL)
 763 #define AHB_BASE              (0x50000000UL)
 764 #define CM3_BASE              (0xE0000000UL)
 765 */
 766
 767 // TODO - #define VIC_BASE_ADDR 0xFFFFF000
 768
 769 #define LPC_WDT_BASE              (0xE0000000)
 770 #define LPC_TIM0_BASE             (0xE0004000)
 771 #define LPC_TIM1_BASE             (0xE0008000)
 772 #define LPC_UART0_BASE            (0xE000C000)
 773 #define LPC_UART1_BASE            (0xE0010000)
 774 #define LPC_PWM1_BASE             (0xE0018000)
 775 #define LPC_I2C0_BASE             (0xE001C000)
 776 #define LPC_SPI_BASE              (0xE0020000)
 777 #define LPC_RTC_BASE              (0xE0024000)
 778 #define LPC_GPIOINT_BASE          (0xE0028080)
 779 #define LPC_PINCON_BASE           (0xE002C000)
 780 #define LPC_SSP1_BASE             (0xE0030000)
 781 #define LPC_ADC_BASE              (0xE0034000)
 782 #define LPC_CANAF_RAM_BASE        (0xE0038000)
 783 #define LPC_CANAF_BASE            (0xE003C000)
 784 #define LPC_CANCR_BASE            (0xE0040000)
 785 #define LPC_CAN1_BASE             (0xE0044000)
 786 #define LPC_CAN2_BASE             (0xE0048000)
 787 #define LPC_I2C1_BASE             (0xE005C000)
 788 #define LPC_SSP0_BASE             (0xE0068000)
 789 #define LPC_DAC_BASE              (0xE006C000)
 790 #define LPC_TIM2_BASE             (0xE0070000)
 791 #define LPC_TIM3_BASE             (0xE0074000)
 792 #define LPC_UART2_BASE            (0xE0078000)
 793 #define LPC_UART3_BASE            (0xE007C000)
 794 #define LPC_I2C2_BASE             (0xE0080000)
 795 #define LPC_I2S_BASE              (0xE0088000)
 796 #define LPC_MCI_BASE              (0xE008C000)
 797 #define LPC_SC_BASE               (0xE01FC000)
 798 #define LPC_EMAC_BASE             (0xFFE00000)
 799 #define LPC_GPDMA_BASE            (0xFFE04000)
 800 #define LPC_GPDMACH0_BASE         (0xFFE04100)
 801 #define LPC_GPDMACH1_BASE         (0xFFE04120)
 802 #define LPC_USB_BASE              (0xFFE0C000)
 803 #define LPC_VIC_BASE              (0xFFFFF000)
 804
 805 /* GPIOs                                                                      */
 806 #define LPC_GPIO0_BASE            (0x3FFFC000)
 807 #define LPC_GPIO1_BASE            (0x3FFFC020)
 808 #define LPC_GPIO2_BASE            (0x3FFFC040)
 809 #define LPC_GPIO3_BASE            (0x3FFFC060)
 810 #define LPC_GPIO4_BASE            (0x3FFFC080)
 811
 812
 813 /******************************************************************************/
 814 /*                         Peripheral declaration                             */
 815 /******************************************************************************/
 816 #define LPC_SC                    ((       LPC_SC_TypeDef *)        LPC_SC_BASE)
 817 #define LPC_GPIO0                 ((     LPC_GPIO_TypeDef *)     LPC_GPIO0_BASE)
 818 #define LPC_GPIO1                 ((     LPC_GPIO_TypeDef *)     LPC_GPIO1_BASE)
 819 #define LPC_GPIO2                 ((     LPC_GPIO_TypeDef *)     LPC_GPIO2_BASE)
 820 #define LPC_GPIO3                 ((     LPC_GPIO_TypeDef *)     LPC_GPIO3_BASE)
 821 #define LPC_GPIO4                 ((     LPC_GPIO_TypeDef *)     LPC_GPIO4_BASE)
 822 #define LPC_WDT                   ((      LPC_WDT_TypeDef *)       LPC_WDT_BASE)
 823 #define LPC_TIM0                  ((      LPC_TIM_TypeDef *)      LPC_TIM0_BASE)
 824 #define LPC_TIM1                  ((      LPC_TIM_TypeDef *)      LPC_TIM1_BASE)
 825 #define LPC_TIM2                  ((      LPC_TIM_TypeDef *)      LPC_TIM2_BASE)
 826 #define LPC_TIM3                  ((      LPC_TIM_TypeDef *)      LPC_TIM3_BASE)
 827 #define LPC_UART0                 ((     LPC_UART_TypeDef *)     LPC_UART0_BASE)
 828 #define LPC_UART1                 ((    LPC_UART1_TypeDef *)     LPC_UART1_BASE)
 829 #define LPC_UART2                 ((     LPC_UART_TypeDef *)     LPC_UART2_BASE)
 830 #define LPC_UART3                 ((     LPC_UART_TypeDef *)     LPC_UART3_BASE)
 831 #define LPC_PWM1                  ((      LPC_PWM_TypeDef *)      LPC_PWM1_BASE)
 832 #define LPC_I2C0                  ((      LPC_I2C_TypeDef *)      LPC_I2C0_BASE)
 833 #define LPC_I2C1                  ((      LPC_I2C_TypeDef *)      LPC_I2C1_BASE)
 834 #define LPC_I2C2                  ((      LPC_I2C_TypeDef *)      LPC_I2C2_BASE)
 835 #define LPC_I2S                   ((      LPC_I2S_TypeDef *)       LPC_I2S_BASE)
 836 #define LPC_SPI                   ((      LPC_SPI_TypeDef *)       LPC_SPI_BASE)
 837 #define LPC_RTC                   ((      LPC_RTC_TypeDef *)       LPC_RTC_BASE)
 838 #define LPC_GPIOINT               ((  LPC_GPIOINT_TypeDef *)   LPC_GPIOINT_BASE)
 839 #define LPC_PINCON                ((   LPC_PINCON_TypeDef *)    LPC_PINCON_BASE)
 840 #define LPC_SSP0                  ((      LPC_SSP_TypeDef *)      LPC_SSP0_BASE)
 841 #define LPC_SSP1                  ((      LPC_SSP_TypeDef *)      LPC_SSP1_BASE)
 842 #define LPC_ADC                   ((      LPC_ADC_TypeDef *)       LPC_ADC_BASE)
 843 #define LPC_DAC                   ((      LPC_DAC_TypeDef *)       LPC_DAC_BASE)
 844 #define LPC_CANAF_RAM             ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
 845 #define LPC_CANAF                 ((    LPC_CANAF_TypeDef *)     LPC_CANAF_BASE)
 846 #define LPC_CANCR                 ((    LPC_CANCR_TypeDef *)     LPC_CANCR_BASE)
 847 #define LPC_CAN1                  ((      LPC_CAN_TypeDef *)      LPC_CAN1_BASE)
 848 #define LPC_CAN2                  ((      LPC_CAN_TypeDef *)      LPC_CAN2_BASE)
 849 #define LPC_MCI                   ((      LPC_MCI_TypeDef *)       LPC_MCI_BASE)
 850 #define LPC_EMAC                  ((     LPC_EMAC_TypeDef *)      LPC_EMAC_BASE)
 851 #define LPC_GPDMA                 ((    LPC_GPDMA_TypeDef *)     LPC_GPDMA_BASE)
 852 #define LPC_GPDMACH0              ((  LPC_GPDMACH_TypeDef *)  LPC_GPDMACH0_BASE)
 853 #define LPC_GPDMACH1              ((  LPC_GPDMACH_TypeDef *)  LPC_GPDMACH1_BASE)
 854 #define LPC_USB                   ((      LPC_USB_TypeDef *)       LPC_USB_BASE)
 855 #define LPC_VIC                   ((      LPC_VIC_TypeDef *)       LPC_VIC_BASE)
 856
 857 #ifdef __cplusplus
 858  }
 859 #endif
 860
 861 #endif  // __LPC23xx_H
 862