gcc4mbed/external/mbed/LPC2368/.svn/text-base/vector_defns.h.svn-base

   1 /* mbed Microcontroller Library - Vectors
   2  * Copyright (c) 2006-2009 ARM Limited. All rights reserved.
   3  * sford, jbrawn
   4  */
   5
   6 #ifndef MBED_VECTOR_DEFNS_H
   7 #define MBED_VECTOR_DEFNS_H
   8
   9 // Assember Macros
  10 #ifdef __ARMCC_VERSION
  11 #define EXPORT(x) EXPORT x
  12 #define WEAK_EXPORT(x) EXPORT x [WEAK]
  13 #define IMPORT(x) IMPORT x
  14 #define LABEL(x) x
  15 #else
  16 #define EXPORT(x) .global x
  17 #define WEAK_EXPORT(x) .weak x
  18 #define IMPORT(x) .global x
  19 #define LABEL(x) x:
  20 #endif
  21
  22 // RealMonitor
  23 // Requires RAM (0x40000040-0x4000011F) to be allocated by the linker
  24
  25 // RealMonitor entry points
  26 #define rm_init_entry 0x7fffff91
  27 #define rm_undef_handler 0x7fffffa0
  28 #define rm_prefetchabort_handler 0x7fffffb0
  29 #define rm_dataabort_handler 0x7fffffc0
  30 #define rm_irqhandler2 0x7fffffe0
  31 //#define rm_RunningToStopped 0x7ffff808 // ARM - MBED64
  32 #define rm_RunningToStopped 0x7ffff820 // ARM - PHAT40
  33
  34 // Unofficial RealMonitor entry points and variables
  35 #define RM_MSG_SWI 0x00940000
  36 #define StateP 0x40000040
  37
  38 // VIC register addresses
  39 #define VIC_Base 0xfffff000
  40 #define VICAddress_Offset 0xf00
  41 #define VICVectAddr2_Offset 0x108
  42 #define VICVectAddr3_Offset 0x10c
  43 #define VICIntEnClr_Offset 0x014
  44 #define VICIntEnClr    (*(volatile unsigned long *)(VIC_Base + 0x014))
  45 #define VICVectAddr2   (*(volatile unsigned long *)(VIC_Base + 0x108))
  46 #define VICVectAddr3   (*(volatile unsigned long *)(VIC_Base + 0x10C))
  47
  48 // ARM Mode bits and Interrupt flags in PSRs
  49 #define Mode_USR 0x10
  50 #define Mode_FIQ 0x11
  51 #define Mode_IRQ 0x12
  52 #define Mode_SVC 0x13
  53 #define Mode_ABT 0x17
  54 #define Mode_UND 0x1B
  55 #define Mode_SYS 0x1F
  56 #define I_Bit 0x80    // when I bit is set, IRQ is disabled
  57 #define F_Bit 0x40    // when F bit is set, FIQ is disabled
  58
  59 // MCU RAM
  60 #define LPC2368_RAM_ADDRESS 0x40000000  // RAM Base
  61 #define LPC2368_RAM_SIZE 0x8000         // 32KB
  62
  63 // ISR Stack Allocation
  64 #define UND_stack_size  0x00000040
  65 #define SVC_stack_size  0x00000040
  66 #define ABT_stack_size  0x00000040
  67 #define FIQ_stack_size  0x00000000
  68 #define IRQ_stack_size  0x00000040
  69
  70 #define ISR_stack_size  (UND_stack_size + SVC_stack_size + ABT_stack_size + FIQ_stack_size + IRQ_stack_size)
  71
  72 // Full Descending Stack, so top-most stack points to just above the top of RAM
  73 #define LPC2368_STACK_TOP (LPC2368_RAM_ADDRESS + LPC2368_RAM_SIZE)
  74 #define USR_STACK_TOP     (LPC2368_STACK_TOP - ISR_stack_size)
  75
  76 #endif