gcc4mbed/external/mbed/LPC2368/.svn/text-base/core_arm7.h.svn-base

   1 /* mbed Microcontroller Library
   2  * Copyright (C) 2008-2009 ARM Limited. All rights reserved.
   3  *
   4  * ARM7 version of CMSIS-like functionality - not advised for use outside mbed!
   5  * based on core_cm3.h, V1.20
   6  */
   7
   8 #ifndef __ARM7_CORE_H__
   9 #define __ARM7_CORE_H__
  10
  11 #ifdef __cplusplus
  12 extern "C" {
  13 #endif
  14
  15 #define __CM3_CMSIS_VERSION_MAIN  (0x01)                                                       /*!< [31:16] CMSIS HAL main version */
  16 #define __CM3_CMSIS_VERSION_SUB   (0x20)                                                       /*!< [15:0]  CMSIS HAL sub version  */
  17 #define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number       */
  18
  19 #define __CORTEX_M                (0x03)                                                       /*!< Cortex core                    */
  20
  21 /**
  22  *  Lint configuration \n
  23  *  ----------------------- \n
  24  *
  25  *  The following Lint messages will be suppressed and not shown: \n
  26  *  \n
  27  *    --- Error 10: --- \n
  28  *    register uint32_t __regBasePri         __asm("basepri"); \n
  29  *    Error 10: Expecting ';' \n
  30  *     \n
  31  *    --- Error 530: --- \n
  32  *    return(__regBasePri); \n
  33  *    Warning 530: Symbol '__regBasePri' (line 264) not initialized \n
  34  *     \n
  35  *    --- Error 550: --- \n
  36  *      __regBasePri = (basePri & 0x1ff); \n
  37  *    } \n
  38  *    Warning 550: Symbol '__regBasePri' (line 271) not accessed \n
  39  *     \n
  40  *    --- Error 754: --- \n
  41  *    uint32_t RESERVED0[24]; \n
  42  *    Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced \n
  43  *     \n
  44  *    --- Error 750: --- \n
  45  *    #define __CM3_CORE_H__ \n
  46  *    Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n
  47  *     \n
  48  *    --- Error 528: --- \n
  49  *    static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
  50  *    Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n
  51  *     \n
  52  *    --- Error 751: --- \n
  53  *    } InterruptType_Type; \n
  54  *    Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n
  55  * \n
  56  * \n
  57  *    Note:  To re-enable a Message, insert a space before 'lint' * \n
  58  *
  59  */
  60
  61 /*lint -save */
  62 /*lint -e10  */
  63 /*lint -e530 */
  64 /*lint -e550 */
  65 /*lint -e754 */
  66 /*lint -e750 */
  67 /*lint -e528 */
  68 /*lint -e751 */
  69
  70 #include <stdint.h>                           /* Include standard types */
  71
  72 /**
  73  * @brief  Return the Main Stack Pointer (current ARM7 stack)
  74  *
  75  * @param  none
  76  * @return uint32_t Main Stack Pointer
  77  *
  78  * Return the current value of the MSP (main stack pointer)
  79  * Cortex processor register
  80  */
  81 extern uint32_t __get_MSP(void);
  82
  83
  84
  85 #if defined (__ICCARM__)
  86   #include <intrinsics.h>                     /* IAR Intrinsics   */
  87 #endif
  88
  89
  90 #ifndef __NVIC_PRIO_BITS
  91   #define __NVIC_PRIO_BITS    4               /*!< standard definition for NVIC Priority Bits */
  92 #endif
  93
  94 typedef struct
  95 {
  96   uint32_t IRQStatus;
  97   uint32_t FIQStatus;
  98   uint32_t RawIntr;
  99   uint32_t IntSelect;
 100   uint32_t IntEnable;
 101   uint32_t IntEnClr;
 102   uint32_t SoftInt;
 103   uint32_t SoftIntClr;
 104   uint32_t Protection;
 105   uint32_t SWPriorityMask;
 106   uint32_t RESERVED0[54];
 107   uint32_t VectAddr[32];
 108   uint32_t RESERVED1[32];
 109   uint32_t VectPriority[32];
 110   uint32_t RESERVED2[800];
 111   uint32_t Address;
 112 } NVIC_TypeDef;
 113
 114 #define NVIC_BASE              (0xFFFFF000)
 115 #define NVIC                   ((      NVIC_TypeDef *)       NVIC_BASE)
 116
 117
 118
 119 /**
 120  * IO definitions
 121  *
 122  * define access restrictions to peripheral registers
 123  */
 124
 125 #ifdef __cplusplus
 126 #define     __I     volatile                  /*!< defines 'read only' permissions      */
 127 #else
 128 #define     __I     volatile const            /*!< defines 'read only' permissions      */
 129 #endif
 130 #define     __O     volatile                  /*!< defines 'write only' permissions     */
 131 #define     __IO    volatile                  /*!< defines 'read / write' permissions   */
 132
 133
 134
 135
 136
 137 #if defined ( __CC_ARM   )
 138   #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
 139   #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
 140
 141 #elif defined ( __ICCARM__ )
 142   #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler           */
 143   #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
 144
 145 #elif defined   (  __GNUC__  )
 146   #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
 147   #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
 148
 149 #elif defined   (  __TASKING__  )
 150   #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler          */
 151   #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler       */
 152
 153 #endif
 154
 155
 156 /* ###################  Compiler specific Intrinsics  ########################### */
 157
 158 #if defined ( __CC_ARM   ) /*------------------RealView Compiler -----------------*/
 159 /* ARM armcc specific functions */
 160
 161 #define __enable_fault_irq                __enable_fiq
 162 #define __disable_fault_irq               __disable_fiq
 163
 164 #define __NOP                             __nop
 165 //#define __WFI                             __wfi
 166 //#define __WFE                             __wfe
 167 //#define __SEV                             __sev
 168 //#define __ISB()                           __isb(0)
 169 //#define __DSB()                           __dsb(0)
 170 //#define __DMB()                           __dmb(0)
 171 //#define __REV                             __rev
 172 //#define __RBIT                            __rbit
 173 #define __LDREXB(ptr)                     ((unsigned char ) __ldrex(ptr))
 174 #define __LDREXH(ptr)                     ((unsigned short) __ldrex(ptr))
 175 #define __LDREXW(ptr)                     ((unsigned int  ) __ldrex(ptr))
 176 #define __STREXB(value, ptr)              __strex(value, ptr)
 177 #define __STREXH(value, ptr)              __strex(value, ptr)
 178 #define __STREXW(value, ptr)              __strex(value, ptr)
 179
 180
 181 #elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
 182
 183 #define __enable_irq                              __enable_interrupt        /*!< global Interrupt enable */
 184 #define __disable_irq                             __disable_interrupt       /*!< global Interrupt disable */
 185 #define __NOP                                     __no_operation()          /*!< no operation intrinsic in IAR Compiler */
 186
 187 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
 188
 189 static __INLINE void __enable_irq()               { __ASM volatile ("cpsie i"); }
 190 static __INLINE void __disable_irq()              { __ASM volatile ("cpsid i"); }
 191
 192 static __INLINE void __NOP()                      { __ASM volatile ("nop"); }
 193
 194 #elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
 195 /* TASKING carm specific functions */
 196
 197 /*
 198  * The CMSIS functions have been implemented as intrinsics in the compiler.
 199  * Please use "carm -?i" to get an up to date list of all instrinsics,
 200  * Including the CMSIS ones.
 201  */
 202
 203 #endif
 204
 205
 206 /**
 207  * @brief  Enable Interrupt in NVIC Interrupt Controller
 208  *
 209  * @param  IRQn_Type IRQn specifies the interrupt number
 210  * @return none
 211  *
 212  * Enable a device specific interupt in the NVIC interrupt controller.
 213  * The interrupt number cannot be a negative value.
 214  */
 215 static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
 216 {
 217  NVIC->IntEnable = 1 << (uint32_t)IRQn;
 218 }
 219
 220
 221 /**
 222  * @brief  Disable the interrupt line for external interrupt specified
 223  *
 224  * @param  IRQn_Type IRQn is the positive number of the external interrupt
 225  * @return none
 226  *
 227  * Disable a device specific interupt in the NVIC interrupt controller.
 228  * The interrupt number cannot be a negative value.
 229  */
 230 static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
 231 {
 232  NVIC->IntEnClr = 1 << (uint32_t)IRQn;
 233 }
 234
 235
 236 #ifdef __cplusplus
 237 }
 238 #endif
 239
 240 #endif /* __ARM7_CORE_H__ */
 241
 242 /*lint -restore */