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[clinton/Smoothieware.git] / gcc4mbed / external / mbed / LPC1768 / .svn / text-base / core_cm3.h.svn-base
1 /******************************************************************************
2 * @file: core_cm3.h
3 * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File
4 * @version: V1.30 PRE-RELEASE
5 * @date: 30. July 2009
6 *----------------------------------------------------------------------------
7 *
8 * Copyright (C) 2009 ARM Limited. All rights reserved.
9 *
10 * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
11 * processor based microcontrollers. This file can be freely distributed
12 * within development tools that are supporting such ARM based processors.
13 *
14 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
15 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
17 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
18 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
19 *
20 ******************************************************************************/
21
22 #ifndef __CM3_CORE_H__
23 #define __CM3_CORE_H__
24
25 #ifdef __cplusplus
26 extern "C" {
27 #endif
28
29 #define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */
30 #define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */
31 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
32
33 #define __CORTEX_M (0x03) /*!< Cortex core */
34
35 /**
36 * Lint configuration \n
37 * ----------------------- \n
38 *
39 * The following Lint messages will be suppressed and not shown: \n
40 * \n
41 * --- Error 10: --- \n
42 * register uint32_t __regBasePri __asm("basepri"); \n
43 * Error 10: Expecting ';' \n
44 * \n
45 * --- Error 530: --- \n
46 * return(__regBasePri); \n
47 * Warning 530: Symbol '__regBasePri' (line 264) not initialized \n
48 * \n
49 * --- Error 550: --- \n
50 * __regBasePri = (basePri & 0x1ff); \n
51 * } \n
52 * Warning 550: Symbol '__regBasePri' (line 271) not accessed \n
53 * \n
54 * --- Error 754: --- \n
55 * uint32_t RESERVED0[24]; \n
56 * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced \n
57 * \n
58 * --- Error 750: --- \n
59 * #define __CM3_CORE_H__ \n
60 * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n
61 * \n
62 * --- Error 528: --- \n
63 * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
64 * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n
65 * \n
66 * --- Error 751: --- \n
67 * } InterruptType_Type; \n
68 * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n
69 * \n
70 * \n
71 * Note: To re-enable a Message, insert a space before 'lint' * \n
72 *
73 */
74
75 /*lint -save */
76 /*lint -e10 */
77 /*lint -e530 */
78 /*lint -e550 */
79 /*lint -e754 */
80 /*lint -e750 */
81 /*lint -e528 */
82 /*lint -e751 */
83
84
85 #include <stdint.h> /* Include standard types */
86
87 #if defined (__ICCARM__)
88 #include <intrinsics.h> /* IAR Intrinsics */
89 #endif
90
91
92 #ifndef __NVIC_PRIO_BITS
93 #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */
94 #endif
95
96
97
98
99 /**
100 * IO definitions
101 *
102 * define access restrictions to peripheral registers
103 */
104
105 #ifdef __cplusplus
106 #define __I volatile /*!< defines 'read only' permissions */
107 #else
108 #define __I volatile const /*!< defines 'read only' permissions */
109 #endif
110 #define __O volatile /*!< defines 'write only' permissions */
111 #define __IO volatile /*!< defines 'read / write' permissions */
112
113
114
115 /*******************************************************************************
116 * Register Abstraction
117 ******************************************************************************/
118
119
120 /* System Reset */
121 #define NVIC_VECTRESET 0 /*!< Vector Reset Bit */
122 #define NVIC_SYSRESETREQ 2 /*!< System Reset Request */
123 #define NVIC_AIRCR_VECTKEY (0x5FA << 16) /*!< AIRCR Key for write access */
124 #define NVIC_AIRCR_ENDIANESS 15 /*!< Endianess */
125
126 /* Core Debug */
127 #define CoreDebug_DEMCR_TRCENA (1 << 24) /*!< DEMCR TRCENA enable */
128 #define ITM_TCR_ITMENA 1 /*!< ITM enable */
129
130
131
132
133 /* memory mapping struct for Nested Vectored Interrupt Controller (NVIC) */
134 typedef struct
135 {
136 __IO uint32_t ISER[8]; /*!< Interrupt Set Enable Register */
137 uint32_t RESERVED0[24];
138 __IO uint32_t ICER[8]; /*!< Interrupt Clear Enable Register */
139 uint32_t RSERVED1[24];
140 __IO uint32_t ISPR[8]; /*!< Interrupt Set Pending Register */
141 uint32_t RESERVED2[24];
142 __IO uint32_t ICPR[8]; /*!< Interrupt Clear Pending Register */
143 uint32_t RESERVED3[24];
144 __IO uint32_t IABR[8]; /*!< Interrupt Active bit Register */
145 uint32_t RESERVED4[56];
146 __IO uint8_t IP[240]; /*!< Interrupt Priority Register, 8Bit wide */
147 uint32_t RESERVED5[644];
148 __O uint32_t STIR; /*!< Software Trigger Interrupt Register */
149 } NVIC_Type;
150
151
152 /* memory mapping struct for System Control Block */
153 typedef struct
154 {
155 __I uint32_t CPUID; /*!< CPU ID Base Register */
156 __IO uint32_t ICSR; /*!< Interrupt Control State Register */
157 __IO uint32_t VTOR; /*!< Vector Table Offset Register */
158 __IO uint32_t AIRCR; /*!< Application Interrupt / Reset Control Register */
159 __IO uint32_t SCR; /*!< System Control Register */
160 __IO uint32_t CCR; /*!< Configuration Control Register */
161 __IO uint8_t SHP[12]; /*!< System Handlers Priority Registers (4-7, 8-11, 12-15) */
162 __IO uint32_t SHCSR; /*!< System Handler Control and State Register */
163 __IO uint32_t CFSR; /*!< Configurable Fault Status Register */
164 __IO uint32_t HFSR; /*!< Hard Fault Status Register */
165 __IO uint32_t DFSR; /*!< Debug Fault Status Register */
166 __IO uint32_t MMFAR; /*!< Mem Manage Address Register */
167 __IO uint32_t BFAR; /*!< Bus Fault Address Register */
168 __IO uint32_t AFSR; /*!< Auxiliary Fault Status Register */
169 __I uint32_t PFR[2]; /*!< Processor Feature Register */
170 __I uint32_t DFR; /*!< Debug Feature Register */
171 __I uint32_t ADR; /*!< Auxiliary Feature Register */
172 __I uint32_t MMFR[4]; /*!< Memory Model Feature Register */
173 __I uint32_t ISAR[5]; /*!< ISA Feature Register */
174 } SCB_Type;
175
176
177 /* memory mapping struct for SysTick */
178 typedef struct
179 {
180 __IO uint32_t CTRL; /*!< SysTick Control and Status Register */
181 __IO uint32_t LOAD; /*!< SysTick Reload Value Register */
182 __IO uint32_t VAL; /*!< SysTick Current Value Register */
183 __I uint32_t CALIB; /*!< SysTick Calibration Register */
184 } SysTick_Type;
185
186
187 /* memory mapping structur for ITM */
188 typedef struct
189 {
190 __O union
191 {
192 __O uint8_t u8; /*!< ITM Stimulus Port 8-bit */
193 __O uint16_t u16; /*!< ITM Stimulus Port 16-bit */
194 __O uint32_t u32; /*!< ITM Stimulus Port 32-bit */
195 } PORT [32]; /*!< ITM Stimulus Port Registers */
196 uint32_t RESERVED0[864];
197 __IO uint32_t TER; /*!< ITM Trace Enable Register */
198 uint32_t RESERVED1[15];
199 __IO uint32_t TPR; /*!< ITM Trace Privilege Register */
200 uint32_t RESERVED2[15];
201 __IO uint32_t TCR; /*!< ITM Trace Control Register */
202 uint32_t RESERVED3[29];
203 __IO uint32_t IWR; /*!< ITM Integration Write Register */
204 __IO uint32_t IRR; /*!< ITM Integration Read Register */
205 __IO uint32_t IMCR; /*!< ITM Integration Mode Control Register */
206 uint32_t RESERVED4[43];
207 __IO uint32_t LAR; /*!< ITM Lock Access Register */
208 __IO uint32_t LSR; /*!< ITM Lock Status Register */
209 uint32_t RESERVED5[6];
210 __I uint32_t PID4; /*!< ITM Product ID Registers */
211 __I uint32_t PID5;
212 __I uint32_t PID6;
213 __I uint32_t PID7;
214 __I uint32_t PID0;
215 __I uint32_t PID1;
216 __I uint32_t PID2;
217 __I uint32_t PID3;
218 __I uint32_t CID0;
219 __I uint32_t CID1;
220 __I uint32_t CID2;
221 __I uint32_t CID3;
222 } ITM_Type;
223
224
225 /* memory mapped struct for Interrupt Type */
226 typedef struct
227 {
228 uint32_t RESERVED0;
229 __I uint32_t ICTR; /*!< Interrupt Control Type Register */
230 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
231 __IO uint32_t ACTLR; /*!< Auxiliary Control Register */
232 #else
233 uint32_t RESERVED1;
234 #endif
235 } InterruptType_Type;
236
237
238 /* Memory Protection Unit */
239 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
240 typedef struct
241 {
242 __I uint32_t TYPE; /*!< MPU Type Register */
243 __IO uint32_t CTRL; /*!< MPU Control Register */
244 __IO uint32_t RNR; /*!< MPU Region RNRber Register */
245 __IO uint32_t RBAR; /*!< MPU Region Base Address Register */
246 __IO uint32_t RASR; /*!< MPU Region Attribute and Size Register */
247 __IO uint32_t RBAR_A1; /*!< MPU Alias 1 Region Base Address Register */
248 __IO uint32_t RASR_A1; /*!< MPU Alias 1 Region Attribute and Size Register */
249 __IO uint32_t RBAR_A2; /*!< MPU Alias 2 Region Base Address Register */
250 __IO uint32_t RASR_A2; /*!< MPU Alias 2 Region Attribute and Size Register */
251 __IO uint32_t RBAR_A3; /*!< MPU Alias 3 Region Base Address Register */
252 __IO uint32_t RASR_A3; /*!< MPU Alias 3 Region Attribute and Size Register */
253 } MPU_Type;
254 #endif
255
256
257 /* Core Debug Register */
258 typedef struct
259 {
260 __IO uint32_t DHCSR; /*!< Debug Halting Control and Status Register */
261 __O uint32_t DCRSR; /*!< Debug Core Register Selector Register */
262 __IO uint32_t DCRDR; /*!< Debug Core Register Data Register */
263 __IO uint32_t DEMCR; /*!< Debug Exception and Monitor Control Register */
264 } CoreDebug_Type;
265
266
267 /* Memory mapping of Cortex-M3 Hardware */
268 #define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */
269 #define ITM_BASE (0xE0000000) /*!< ITM Base Address */
270 #define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */
271 #define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */
272 #define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */
273 #define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */
274
275 #define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */
276 #define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */
277 #define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */
278 #define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */
279 #define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */
280 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
281
282 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
283 #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */
284 #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */
285 #endif
286
287
288 /*******************************************************************************
289 * Hardware Abstraction Layer
290 ******************************************************************************/
291
292
293 #if defined ( __CC_ARM )
294 #define __ASM __asm /*!< asm keyword for ARM Compiler */
295 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
296
297 #elif defined ( __ICCARM__ )
298 #define __ASM __asm /*!< asm keyword for IAR Compiler */
299 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
300
301 #elif defined ( __GNUC__ )
302 #define __ASM __asm /*!< asm keyword for GNU Compiler */
303 #define __INLINE inline /*!< inline keyword for GNU Compiler */
304
305 #elif defined ( __TASKING__ )
306 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
307 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
308
309 #endif
310
311
312 /* ################### Compiler specific Intrinsics ########################### */
313
314 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
315 /* ARM armcc specific functions */
316
317 #define __enable_fault_irq __enable_fiq
318 #define __disable_fault_irq __disable_fiq
319
320 #define __NOP __nop
321 #define __WFI __wfi
322 #define __WFE __wfe
323 #define __SEV __sev
324 #define __ISB() __isb(0)
325 #define __DSB() __dsb(0)
326 #define __DMB() __dmb(0)
327 #define __REV __rev
328 #define __RBIT __rbit
329 #define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))
330 #define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))
331 #define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))
332 #define __STREXB(value, ptr) __strex(value, ptr)
333 #define __STREXH(value, ptr) __strex(value, ptr)
334 #define __STREXW(value, ptr) __strex(value, ptr)
335
336
337 /* intrinsic unsigned long long __ldrexd(volatile void *ptr) */
338 /* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */
339 /* intrinsic void __enable_irq(); */
340 /* intrinsic void __disable_irq(); */
341
342
343 /**
344 * @brief Return the Process Stack Pointer
345 *
346 * @param none
347 * @return uint32_t ProcessStackPointer
348 *
349 * Return the actual process stack pointer
350 */
351 extern uint32_t __get_PSP(void);
352
353 /**
354 * @brief Set the Process Stack Pointer
355 *
356 * @param uint32_t Process Stack Pointer
357 * @return none
358 *
359 * Assign the value ProcessStackPointer to the MSP
360 * (process stack pointer) Cortex processor register
361 */
362 extern void __set_PSP(uint32_t topOfProcStack);
363
364 /**
365 * @brief Return the Main Stack Pointer
366 *
367 * @param none
368 * @return uint32_t Main Stack Pointer
369 *
370 * Return the current value of the MSP (main stack pointer)
371 * Cortex processor register
372 */
373 extern uint32_t __get_MSP(void);
374
375 /**
376 * @brief Set the Main Stack Pointer
377 *
378 * @param uint32_t Main Stack Pointer
379 * @return none
380 *
381 * Assign the value mainStackPointer to the MSP
382 * (main stack pointer) Cortex processor register
383 */
384 extern void __set_MSP(uint32_t topOfMainStack);
385
386 /**
387 * @brief Reverse byte order in unsigned short value
388 *
389 * @param uint16_t value to reverse
390 * @return uint32_t reversed value
391 *
392 * Reverse byte order in unsigned short value
393 */
394 extern uint32_t __REV16(uint16_t value);
395
396 /*
397 * @brief Reverse byte order in signed short value with sign extension to integer
398 *
399 * @param int16_t value to reverse
400 * @return int32_t reversed value
401 *
402 * Reverse byte order in signed short value with sign extension to integer
403 */
404 extern int32_t __REVSH(int16_t value);
405
406
407 #if (__ARMCC_VERSION < 400000)
408
409 /**
410 * @brief Remove the exclusive lock created by ldrex
411 *
412 * @param none
413 * @return none
414 *
415 * Removes the exclusive lock which is created by ldrex.
416 */
417 extern void __CLREX(void);
418
419 /**
420 * @brief Return the Base Priority value
421 *
422 * @param none
423 * @return uint32_t BasePriority
424 *
425 * Return the content of the base priority register
426 */
427 extern uint32_t __get_BASEPRI(void);
428
429 /**
430 * @brief Set the Base Priority value
431 *
432 * @param uint32_t BasePriority
433 * @return none
434 *
435 * Set the base priority register
436 */
437 extern void __set_BASEPRI(uint32_t basePri);
438
439 /**
440 * @brief Return the Priority Mask value
441 *
442 * @param none
443 * @return uint32_t PriMask
444 *
445 * Return the state of the priority mask bit from the priority mask
446 * register
447 */
448 extern uint32_t __get_PRIMASK(void);
449
450 /**
451 * @brief Set the Priority Mask value
452 *
453 * @param uint32_t PriMask
454 * @return none
455 *
456 * Set the priority mask bit in the priority mask register
457 */
458 extern void __set_PRIMASK(uint32_t priMask);
459
460 /**
461 * @brief Return the Fault Mask value
462 *
463 * @param none
464 * @return uint32_t FaultMask
465 *
466 * Return the content of the fault mask register
467 */
468 extern uint32_t __get_FAULTMASK(void);
469
470 /**
471 * @brief Set the Fault Mask value
472 *
473 * @param uint32_t faultMask value
474 * @return none
475 *
476 * Set the fault mask register
477 */
478 extern void __set_FAULTMASK(uint32_t faultMask);
479
480 /**
481 * @brief Return the Control Register value
482 *
483 * @param none
484 * @return uint32_t Control value
485 *
486 * Return the content of the control register
487 */
488 extern uint32_t __get_CONTROL(void);
489
490 /**
491 * @brief Set the Control Register value
492 *
493 * @param uint32_t Control value
494 * @return none
495 *
496 * Set the control register
497 */
498 extern void __set_CONTROL(uint32_t control);
499
500 #else /* (__ARMCC_VERSION >= 400000) */
501
502
503 /**
504 * @brief Remove the exclusive lock created by ldrex
505 *
506 * @param none
507 * @return none
508 *
509 * Removes the exclusive lock which is created by ldrex.
510 */
511 #define __CLREX __clrex
512
513 /**
514 * @brief Return the Base Priority value
515 *
516 * @param none
517 * @return uint32_t BasePriority
518 *
519 * Return the content of the base priority register
520 */
521 static __INLINE uint32_t __get_BASEPRI(void)
522 {
523 register uint32_t __regBasePri __ASM("basepri");
524 return(__regBasePri);
525 }
526
527 /**
528 * @brief Set the Base Priority value
529 *
530 * @param uint32_t BasePriority
531 * @return none
532 *
533 * Set the base priority register
534 */
535 static __INLINE void __set_BASEPRI(uint32_t basePri)
536 {
537 register uint32_t __regBasePri __ASM("basepri");
538 __regBasePri = (basePri & 0xff);
539 }
540
541 /**
542 * @brief Return the Priority Mask value
543 *
544 * @param none
545 * @return uint32_t PriMask
546 *
547 * Return the state of the priority mask bit from the priority mask
548 * register
549 */
550 static __INLINE uint32_t __get_PRIMASK(void)
551 {
552 register uint32_t __regPriMask __ASM("primask");
553 return(__regPriMask);
554 }
555
556 /**
557 * @brief Set the Priority Mask value
558 *
559 * @param uint32_t PriMask
560 * @return none
561 *
562 * Set the priority mask bit in the priority mask register
563 */
564 static __INLINE void __set_PRIMASK(uint32_t priMask)
565 {
566 register uint32_t __regPriMask __ASM("primask");
567 __regPriMask = (priMask);
568 }
569
570 /**
571 * @brief Return the Fault Mask value
572 *
573 * @param none
574 * @return uint32_t FaultMask
575 *
576 * Return the content of the fault mask register
577 */
578 static __INLINE uint32_t __get_FAULTMASK(void)
579 {
580 register uint32_t __regFaultMask __ASM("faultmask");
581 return(__regFaultMask);
582 }
583
584 /**
585 * @brief Set the Fault Mask value
586 *
587 * @param uint32_t faultMask value
588 * @return none
589 *
590 * Set the fault mask register
591 */
592 static __INLINE void __set_FAULTMASK(uint32_t faultMask)
593 {
594 register uint32_t __regFaultMask __ASM("faultmask");
595 __regFaultMask = (faultMask & 1);
596 }
597
598 /**
599 * @brief Return the Control Register value
600 *
601 * @param none
602 * @return uint32_t Control value
603 *
604 * Return the content of the control register
605 */
606 static __INLINE uint32_t __get_CONTROL(void)
607 {
608 register uint32_t __regControl __ASM("control");
609 return(__regControl);
610 }
611
612 /**
613 * @brief Set the Control Register value
614 *
615 * @param uint32_t Control value
616 * @return none
617 *
618 * Set the control register
619 */
620 static __INLINE void __set_CONTROL(uint32_t control)
621 {
622 register uint32_t __regControl __ASM("control");
623 __regControl = control;
624 }
625
626 #endif /* __ARMCC_VERSION */
627
628
629
630 #elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
631 /* IAR iccarm specific functions */
632
633 #define __enable_irq __enable_interrupt /*!< global Interrupt enable */
634 #define __disable_irq __disable_interrupt /*!< global Interrupt disable */
635
636 static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }
637 static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }
638
639 #define __NOP __no_operation() /*!< no operation intrinsic in IAR Compiler */
640 static __INLINE void __WFI() { __ASM ("wfi"); }
641 static __INLINE void __WFE() { __ASM ("wfe"); }
642 static __INLINE void __SEV() { __ASM ("sev"); }
643 static __INLINE void __CLREX() { __ASM ("clrex"); }
644
645 /* intrinsic void __ISB(void) */
646 /* intrinsic void __DSB(void) */
647 /* intrinsic void __DMB(void) */
648 /* intrinsic void __set_PRIMASK(); */
649 /* intrinsic void __get_PRIMASK(); */
650 /* intrinsic void __set_FAULTMASK(); */
651 /* intrinsic void __get_FAULTMASK(); */
652 /* intrinsic uint32_t __REV(uint32_t value); */
653 /* intrinsic uint32_t __REVSH(uint32_t value); */
654 /* intrinsic unsigned long __STREX(unsigned long, unsigned long); */
655 /* intrinsic unsigned long __LDREX(unsigned long *); */
656
657
658 /**
659 * @brief Return the Process Stack Pointer
660 *
661 * @param none
662 * @return uint32_t ProcessStackPointer
663 *
664 * Return the actual process stack pointer
665 */
666 extern uint32_t __get_PSP(void);
667
668 /**
669 * @brief Set the Process Stack Pointer
670 *
671 * @param uint32_t Process Stack Pointer
672 * @return none
673 *
674 * Assign the value ProcessStackPointer to the MSP
675 * (process stack pointer) Cortex processor register
676 */
677 extern void __set_PSP(uint32_t topOfProcStack);
678
679 /**
680 * @brief Return the Main Stack Pointer
681 *
682 * @param none
683 * @return uint32_t Main Stack Pointer
684 *
685 * Return the current value of the MSP (main stack pointer)
686 * Cortex processor register
687 */
688 extern uint32_t __get_MSP(void);
689
690 /**
691 * @brief Set the Main Stack Pointer
692 *
693 * @param uint32_t Main Stack Pointer
694 * @return none
695 *
696 * Assign the value mainStackPointer to the MSP
697 * (main stack pointer) Cortex processor register
698 */
699 extern void __set_MSP(uint32_t topOfMainStack);
700
701 /**
702 * @brief Reverse byte order in unsigned short value
703 *
704 * @param uint16_t value to reverse
705 * @return uint32_t reversed value
706 *
707 * Reverse byte order in unsigned short value
708 */
709 extern uint32_t __REV16(uint16_t value);
710
711 /**
712 * @brief Reverse bit order of value
713 *
714 * @param uint32_t value to reverse
715 * @return uint32_t reversed value
716 *
717 * Reverse bit order of value
718 */
719 extern uint32_t __RBIT(uint32_t value);
720
721 /**
722 * @brief LDR Exclusive
723 *
724 * @param uint8_t* address
725 * @return uint8_t value of (*address)
726 *
727 * Exclusive LDR command
728 */
729 extern uint8_t __LDREXB(uint8_t *addr);
730
731 /**
732 * @brief LDR Exclusive
733 *
734 * @param uint16_t* address
735 * @return uint16_t value of (*address)
736 *
737 * Exclusive LDR command
738 */
739 extern uint16_t __LDREXH(uint16_t *addr);
740
741 /**
742 * @brief LDR Exclusive
743 *
744 * @param uint32_t* address
745 * @return uint32_t value of (*address)
746 *
747 * Exclusive LDR command
748 */
749 extern uint32_t __LDREXW(uint32_t *addr);
750
751 /**
752 * @brief STR Exclusive
753 *
754 * @param uint8_t *address
755 * @param uint8_t value to store
756 * @return uint32_t successful / failed
757 *
758 * Exclusive STR command
759 */
760 extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
761
762 /**
763 * @brief STR Exclusive
764 *
765 * @param uint16_t *address
766 * @param uint16_t value to store
767 * @return uint32_t successful / failed
768 *
769 * Exclusive STR command
770 */
771 extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
772
773 /**
774 * @brief STR Exclusive
775 *
776 * @param uint32_t *address
777 * @param uint32_t value to store
778 * @return uint32_t successful / failed
779 *
780 * Exclusive STR command
781 */
782 extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
783
784
785
786 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
787 /* GNU gcc specific functions */
788
789 static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); }
790 static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); }
791
792 static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); }
793 static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); }
794
795 static __INLINE void __NOP() { __ASM volatile ("nop"); }
796 static __INLINE void __WFI() { __ASM volatile ("wfi"); }
797 static __INLINE void __WFE() { __ASM volatile ("wfe"); }
798 static __INLINE void __SEV() { __ASM volatile ("sev"); }
799 static __INLINE void __ISB() { __ASM volatile ("isb"); }
800 static __INLINE void __DSB() { __ASM volatile ("dsb"); }
801 static __INLINE void __DMB() { __ASM volatile ("dmb"); }
802 static __INLINE void __CLREX() { __ASM volatile ("clrex"); }
803
804
805 /**
806 * @brief Return the Process Stack Pointer
807 *
808 * @param none
809 * @return uint32_t ProcessStackPointer
810 *
811 * Return the actual process stack pointer
812 */
813 extern uint32_t __get_PSP(void);
814
815 /**
816 * @brief Set the Process Stack Pointer
817 *
818 * @param uint32_t Process Stack Pointer
819 * @return none
820 *
821 * Assign the value ProcessStackPointer to the MSP
822 * (process stack pointer) Cortex processor register
823 */
824 extern void __set_PSP(uint32_t topOfProcStack);
825
826 /**
827 * @brief Return the Main Stack Pointer
828 *
829 * @param none
830 * @return uint32_t Main Stack Pointer
831 *
832 * Return the current value of the MSP (main stack pointer)
833 * Cortex processor register
834 */
835 extern uint32_t __get_MSP(void);
836
837 /**
838 * @brief Set the Main Stack Pointer
839 *
840 * @param uint32_t Main Stack Pointer
841 * @return none
842 *
843 * Assign the value mainStackPointer to the MSP
844 * (main stack pointer) Cortex processor register
845 */
846 extern void __set_MSP(uint32_t topOfMainStack);
847
848 /**
849 * @brief Return the Base Priority value
850 *
851 * @param none
852 * @return uint32_t BasePriority
853 *
854 * Return the content of the base priority register
855 */
856 extern uint32_t __get_BASEPRI(void);
857
858 /**
859 * @brief Set the Base Priority value
860 *
861 * @param uint32_t BasePriority
862 * @return none
863 *
864 * Set the base priority register
865 */
866 extern void __set_BASEPRI(uint32_t basePri);
867
868 /**
869 * @brief Return the Priority Mask value
870 *
871 * @param none
872 * @return uint32_t PriMask
873 *
874 * Return the state of the priority mask bit from the priority mask
875 * register
876 */
877 extern uint32_t __get_PRIMASK(void);
878
879 /**
880 * @brief Set the Priority Mask value
881 *
882 * @param uint32_t PriMask
883 * @return none
884 *
885 * Set the priority mask bit in the priority mask register
886 */
887 extern void __set_PRIMASK(uint32_t priMask);
888
889 /**
890 * @brief Return the Fault Mask value
891 *
892 * @param none
893 * @return uint32_t FaultMask
894 *
895 * Return the content of the fault mask register
896 */
897 extern uint32_t __get_FAULTMASK(void);
898
899 /**
900 * @brief Set the Fault Mask value
901 *
902 * @param uint32_t faultMask value
903 * @return none
904 *
905 * Set the fault mask register
906 */
907 extern void __set_FAULTMASK(uint32_t faultMask);
908
909 /**
910 * @brief Return the Control Register value
911 *
912 * @param none
913 * @return uint32_t Control value
914 *
915 * Return the content of the control register
916 */
917 extern uint32_t __get_CONTROL(void);
918
919 /**
920 * @brief Set the Control Register value
921 *
922 * @param uint32_t Control value
923 * @return none
924 *
925 * Set the control register
926 */
927 extern void __set_CONTROL(uint32_t control);
928
929 /**
930 * @brief Reverse byte order in integer value
931 *
932 * @param uint32_t value to reverse
933 * @return uint32_t reversed value
934 *
935 * Reverse byte order in integer value
936 */
937 extern uint32_t __REV(uint32_t value);
938
939 /**
940 * @brief Reverse byte order in unsigned short value
941 *
942 * @param uint16_t value to reverse
943 * @return uint32_t reversed value
944 *
945 * Reverse byte order in unsigned short value
946 */
947 extern uint32_t __REV16(uint16_t value);
948
949 /*
950 * Reverse byte order in signed short value with sign extension to integer
951 *
952 * @param int16_t value to reverse
953 * @return int32_t reversed value
954 *
955 * @brief Reverse byte order in signed short value with sign extension to integer
956 */
957 extern int32_t __REVSH(int16_t value);
958
959 /**
960 * @brief Reverse bit order of value
961 *
962 * @param uint32_t value to reverse
963 * @return uint32_t reversed value
964 *
965 * Reverse bit order of value
966 */
967 extern uint32_t __RBIT(uint32_t value);
968
969 /**
970 * @brief LDR Exclusive
971 *
972 * @param uint8_t* address
973 * @return uint8_t value of (*address)
974 *
975 * Exclusive LDR command
976 */
977 extern uint8_t __LDREXB(uint8_t *addr);
978
979 /**
980 * @brief LDR Exclusive
981 *
982 * @param uint16_t* address
983 * @return uint16_t value of (*address)
984 *
985 * Exclusive LDR command
986 */
987 extern uint16_t __LDREXH(uint16_t *addr);
988
989 /**
990 * @brief LDR Exclusive
991 *
992 * @param uint32_t* address
993 * @return uint32_t value of (*address)
994 *
995 * Exclusive LDR command
996 */
997 extern uint32_t __LDREXW(uint32_t *addr);
998
999 /**
1000 * @brief STR Exclusive
1001 *
1002 * @param uint8_t *address
1003 * @param uint8_t value to store
1004 * @return uint32_t successful / failed
1005 *
1006 * Exclusive STR command
1007 */
1008 extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
1009
1010 /**
1011 * @brief STR Exclusive
1012 *
1013 * @param uint16_t *address
1014 * @param uint16_t value to store
1015 * @return uint32_t successful / failed
1016 *
1017 * Exclusive STR command
1018 */
1019 extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
1020
1021 /**
1022 * @brief STR Exclusive
1023 *
1024 * @param uint32_t *address
1025 * @param uint32_t value to store
1026 * @return uint32_t successful / failed
1027 *
1028 * Exclusive STR command
1029 */
1030 extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
1031
1032
1033 #elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
1034 /* TASKING carm specific functions */
1035
1036 /*
1037 * The CMSIS functions have been implemented as intrinsics in the compiler.
1038 * Please use "carm -?i" to get an up to date list of all instrinsics,
1039 * Including the CMSIS ones.
1040 */
1041
1042 #endif
1043
1044
1045
1046 /* ########################## NVIC functions #################################### */
1047
1048
1049 /**
1050 * @brief Set the Priority Grouping in NVIC Interrupt Controller
1051 *
1052 * @param uint32_t priority_grouping is priority grouping field
1053 * @return none
1054 *
1055 * Set the priority grouping field using the required unlock sequence.
1056 * The parameter priority_grouping is assigned to the field
1057 * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.
1058 * In case of a conflict between priority grouping and available
1059 * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
1060 */
1061 static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1062 {
1063 uint32_t reg_value;
1064 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
1065
1066 reg_value = SCB->AIRCR; /* read old register configuration */
1067 reg_value &= ~((0xFFFFU << 16) | (0x0F << 8)); /* clear bits to change */
1068 reg_value = ((reg_value | NVIC_AIRCR_VECTKEY | (PriorityGroupTmp << 8))); /* Insert write key and priorty group */
1069 SCB->AIRCR = reg_value;
1070 }
1071
1072 /**
1073 * @brief Get the Priority Grouping from NVIC Interrupt Controller
1074 *
1075 * @param none
1076 * @return uint32_t priority grouping field
1077 *
1078 * Get the priority grouping from NVIC Interrupt Controller.
1079 * priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
1080 */
1081 static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
1082 {
1083 return ((SCB->AIRCR >> 8) & 0x07); /* read priority grouping field */
1084 }
1085
1086 /**
1087 * @brief Enable Interrupt in NVIC Interrupt Controller
1088 *
1089 * @param IRQn_Type IRQn specifies the interrupt number
1090 * @return none
1091 *
1092 * Enable a device specific interupt in the NVIC interrupt controller.
1093 * The interrupt number cannot be a negative value.
1094 */
1095 static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
1096 {
1097 NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
1098 }
1099
1100 /**
1101 * @brief Disable the interrupt line for external interrupt specified
1102 *
1103 * @param IRQn_Type IRQn is the positive number of the external interrupt
1104 * @return none
1105 *
1106 * Disable a device specific interupt in the NVIC interrupt controller.
1107 * The interrupt number cannot be a negative value.
1108 */
1109 static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
1110 {
1111 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
1112 }
1113
1114 /**
1115 * @brief Read the interrupt pending bit for a device specific interrupt source
1116 *
1117 * @param IRQn_Type IRQn is the number of the device specifc interrupt
1118 * @return uint32_t 1 if pending interrupt else 0
1119 *
1120 * Read the pending register in NVIC and return 1 if its status is pending,
1121 * otherwise it returns 0
1122 */
1123 static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
1124 {
1125 return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
1126 }
1127
1128 /**
1129 * @brief Set the pending bit for an external interrupt
1130 *
1131 * @param IRQn_Type IRQn is the Number of the interrupt
1132 * @return none
1133 *
1134 * Set the pending bit for the specified interrupt.
1135 * The interrupt number cannot be a negative value.
1136 */
1137 static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
1138 {
1139 NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
1140 }
1141
1142 /**
1143 * @brief Clear the pending bit for an external interrupt
1144 *
1145 * @param IRQn_Type IRQn is the Number of the interrupt
1146 * @return none
1147 *
1148 * Clear the pending bit for the specified interrupt.
1149 * The interrupt number cannot be a negative value.
1150 */
1151 static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1152 {
1153 NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
1154 }
1155
1156 /**
1157 * @brief Read the active bit for an external interrupt
1158 *
1159 * @param IRQn_Type IRQn is the Number of the interrupt
1160 * @return uint32_t 1 if active else 0
1161 *
1162 * Read the active register in NVIC and returns 1 if its status is active,
1163 * otherwise it returns 0.
1164 */
1165 static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
1166 {
1167 return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
1168 }
1169
1170 /**
1171 * @brief Set the priority for an interrupt
1172 *
1173 * @param IRQn_Type IRQn is the Number of the interrupt
1174 * @param priority is the priority for the interrupt
1175 * @return none
1176 *
1177 * Set the priority for the specified interrupt. The interrupt
1178 * number can be positive to specify an external (device specific)
1179 * interrupt, or negative to specify an internal (core) interrupt. \n
1180 *
1181 * Note: The priority cannot be set for every core interrupt.
1182 */
1183 static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1184 {
1185 if(IRQn < 0) {
1186 SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */
1187 else {
1188 NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
1189 }
1190
1191 /**
1192 * @brief Read the priority for an interrupt
1193 *
1194 * @param IRQn_Type IRQn is the Number of the interrupt
1195 * @return uint32_t priority is the priority for the interrupt
1196 *
1197 * Read the priority for the specified interrupt. The interrupt
1198 * number can be positive to specify an external (device specific)
1199 * interrupt, or negative to specify an internal (core) interrupt.
1200 *
1201 * The returned priority value is automatically aligned to the implemented
1202 * priority bits of the microcontroller.
1203 *
1204 * Note: The priority cannot be set for every core interrupt.
1205 */
1206 static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
1207 {
1208
1209 if(IRQn < 0) {
1210 return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */
1211 else {
1212 return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
1213 }
1214
1215
1216 /**
1217 * @brief Encode the priority for an interrupt
1218 *
1219 * @param uint32_t PriorityGroup is the used priority group
1220 * @param uint32_t PreemptPriority is the preemptive priority value (starting from 0)
1221 * @param uint32_t SubPriority is the sub priority value (starting from 0)
1222 * @return uint32_t the priority for the interrupt
1223 *
1224 * Encode the priority for an interrupt with the given priority group,
1225 * preemptive priority value and sub priority value.
1226 * In case of a conflict between priority grouping and available
1227 * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
1228 *
1229 * The returned priority value can be used for NVIC_SetPriority(...) function
1230 */
1231 static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1232 {
1233 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
1234 uint32_t PreemptPriorityBits;
1235 uint32_t SubPriorityBits;
1236
1237 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
1238 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
1239
1240 return (
1241 ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
1242 ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
1243 );
1244 }
1245
1246
1247 /**
1248 * @brief Decode the priority of an interrupt
1249 *
1250 * @param uint32_t Priority the priority for the interrupt
1251 * @param uint32_t PrioGroup is the used priority group
1252 * @param uint32_t* pPreemptPrio is the preemptive priority value (starting from 0)
1253 * @param uint32_t* pSubPrio is the sub priority value (starting from 0)
1254 * @return none
1255 *
1256 * Decode an interrupt priority value with the given priority group to
1257 * preemptive priority value and sub priority value.
1258 * In case of a conflict between priority grouping and available
1259 * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
1260 *
1261 * The priority value can be retrieved with NVIC_GetPriority(...) function
1262 */
1263 static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
1264 {
1265 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
1266 uint32_t PreemptPriorityBits;
1267 uint32_t SubPriorityBits;
1268
1269 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
1270 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
1271
1272 *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
1273 *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
1274 }
1275
1276
1277
1278 /* ################################## SysTick function ############################################ */
1279
1280 #if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)
1281
1282 /* SysTick constants */
1283 #define SYSTICK_ENABLE 0 /* Config-Bit to start or stop the SysTick Timer */
1284 #define SYSTICK_TICKINT 1 /* Config-Bit to enable or disable the SysTick interrupt */
1285 #define SYSTICK_CLKSOURCE 2 /* Clocksource has the offset 2 in SysTick Control and Status Register */
1286 #define SYSTICK_MAXCOUNT ((1<<24) -1) /* SysTick MaxCount */
1287
1288 /**
1289 * @brief Initialize and start the SysTick counter and its interrupt.
1290 *
1291 * @param uint32_t ticks is the number of ticks between two interrupts
1292 * @return none
1293 *
1294 * Initialise the system tick timer and its interrupt and start the
1295 * system tick timer / counter in free running mode to generate
1296 * periodical interrupts.
1297 */
1298 static __INLINE uint32_t SysTick_Config(uint32_t ticks)
1299 {
1300 if (ticks > SYSTICK_MAXCOUNT) return (1); /* Reload value impossible */
1301
1302 SysTick->LOAD = (ticks & SYSTICK_MAXCOUNT) - 1; /* set reload register */
1303 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
1304 SysTick->VAL = (0x00); /* Load the SysTick Counter Value */
1305 SysTick->CTRL = (1 << SYSTICK_CLKSOURCE) | (1<<SYSTICK_ENABLE) | (1<<SYSTICK_TICKINT); /* Enable SysTick IRQ and SysTick Timer */
1306 return (0); /* Function successful */
1307 }
1308
1309 #endif
1310
1311
1312
1313
1314
1315 /* ################################## Reset function ############################################ */
1316
1317 /**
1318 * @brief Initiate a system reset request.
1319 *
1320 * @param none
1321 * @return none
1322 *
1323 * Initialize a system reset request to reset the MCU
1324 */
1325 static __INLINE void NVIC_SystemReset(void)
1326 {
1327 SCB->AIRCR = (NVIC_AIRCR_VECTKEY | (SCB->AIRCR & (0x700)) | (1<<NVIC_SYSRESETREQ)); /* Keep priority group unchanged */
1328 __DSB(); /* Ensure completion of memory access */
1329 while(1); /* wait until reset */
1330 }
1331
1332
1333 /* ##################################### Debug In/Output function ########################################### */
1334
1335 extern volatile int ITM_RxBuffer; /* variable to receive characters */
1336 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /* value identifying ITM_RxBuffer is ready for next character */
1337
1338
1339 /**
1340 * @brief Outputs a character via the ITM channel 0
1341 *
1342 * @param uint32_t character to output
1343 * @return uint32_t input character
1344 *
1345 * The function outputs a character via the ITM channel 0.
1346 * The function returns when no debugger is connected that has booked the output.
1347 * It is blocking when a debugger is connected, but the previous character send is not transmitted.
1348 */
1349 static __INLINE uint32_t ITM_SendChar (uint32_t ch)
1350 {
1351 if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &&
1352 (ITM->TCR & ITM_TCR_ITMENA) &&
1353 (ITM->TER & (1UL << 0)) )
1354 {
1355 while (ITM->PORT[0].u32 == 0);
1356 ITM->PORT[0].u8 = (uint8_t) ch;
1357 }
1358 return (ch);
1359 }
1360
1361
1362 /**
1363 * @brief Inputs a character via variable ITM_RxBuffer
1364 *
1365 * @param none
1366 * @return uint32_t input character
1367 *
1368 * The function inputs a character via variable ITM_RxBuffer.
1369 * The function returns when no debugger is connected that has booked the output.
1370 * It is blocking when a debugger is connected, but the previous character send is not transmitted.
1371 */
1372 static __INLINE int ITM_ReceiveChar (void) {
1373 int ch = -1; /* no character available */
1374
1375 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
1376 ch = ITM_RxBuffer;
1377 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
1378 }
1379
1380 return (ch);
1381 }
1382
1383
1384 /**
1385 * @brief Check if a character via variable ITM_RxBuffer is available
1386 *
1387 * @param none
1388 * @return int 1 = character available, 0 = no character available
1389 *
1390 * The function checks variable ITM_RxBuffer whether a character is available or not.
1391 * The function returns '1' if a character is available and '0' if no character is available.
1392 */
1393 static __INLINE int ITM_CheckChar (void) {
1394
1395 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
1396 return (0); /* no character available */
1397 } else {
1398 return (1); /* character available */
1399 }
1400 }
1401
1402
1403
1404 #ifdef __cplusplus
1405 }
1406 #endif
1407
1408 #endif /* __CM3_CORE_H__ */
1409
1410 /*lint -restore */
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