mbed/src/vendor/NXP/cmsis/LPC1768/system_LPC17xx.c

   1 /**************************************************************************//**
   2  * @file     system_LPC17xx.c
   3  * @brief    CMSIS Cortex-M3 Device System Source File for
   4  *           NXP LPC17xx Device Series
   5  * @version  V1.11
   6  * @date     21. June 2011
   7  *
   8  * @note
   9  * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
  10  *
  11  * @par
  12  * ARM Limited (ARM) is supplying this software for use with Cortex-M
  13  * processor based microcontrollers.  This file can be freely distributed
  14  * within development tools that are supporting such ARM based processors.
  15  *
  16  * @par
  17  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  18  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
  19  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
  20  * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
  21  * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
  22  *
  23  ******************************************************************************/
  24
  25
  26 #include <stdint.h>
  27 #include "LPC17xx.h"
  28
  29
  30 /** @addtogroup LPC17xx_System
  31  * @{
  32  */
  33
  34 /*
  35 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
  36 */
  37
  38 /*--------------------- Clock Configuration ----------------------------------
  39 //
  40 // <e> Clock Configuration
  41 //   <h> System Controls and Status Register (SCS)
  42 //     <o1.4>    OSCRANGE: Main Oscillator Range Select
  43 //                     <0=>  1 MHz to 20 MHz
  44 //                     <1=> 15 MHz to 25 MHz
  45 //     <e1.5>       OSCEN: Main Oscillator Enable
  46 //     </e>
  47 //   </h>
  48 //
  49 //   <h> Clock Source Select Register (CLKSRCSEL)
  50 //     <o2.0..1>   CLKSRC: PLL Clock Source Selection
  51 //                     <0=> Internal RC oscillator
  52 //                     <1=> Main oscillator
  53 //                     <2=> RTC oscillator
  54 //   </h>
  55 //
  56 //   <e3> PLL0 Configuration (Main PLL)
  57 //     <h> PLL0 Configuration Register (PLL0CFG)
  58 //                     <i> F_cco0 = (2 * M * F_in) / N
  59 //                     <i> F_in must be in the range of 32 kHz to 50 MHz
  60 //                     <i> F_cco0 must be in the range of 275 MHz to 550 MHz
  61 //       <o4.0..14>  MSEL: PLL Multiplier Selection
  62 //                     <6-32768><#-1>
  63 //                     <i> M Value
  64 //       <o4.16..23> NSEL: PLL Divider Selection
  65 //                     <1-256><#-1>
  66 //                     <i> N Value
  67 //     </h>
  68 //   </e>
  69 //
  70 //   <e5> PLL1 Configuration (USB PLL)
  71 //     <h> PLL1 Configuration Register (PLL1CFG)
  72 //                     <i> F_usb = M * F_osc or F_usb = F_cco1 / (2 * P)
  73 //                     <i> F_cco1 = F_osc * M * 2 * P
  74 //                     <i> F_cco1 must be in the range of 156 MHz to 320 MHz
  75 //       <o6.0..4>   MSEL: PLL Multiplier Selection
  76 //                     <1-32><#-1>
  77 //                     <i> M Value (for USB maximum value is 4)
  78 //       <o6.5..6>   PSEL: PLL Divider Selection
  79 //                     <0=> 1
  80 //                     <1=> 2
  81 //                     <2=> 4
  82 //                     <3=> 8
  83 //                     <i> P Value
  84 //     </h>
  85 //   </e>
  86 //
  87 //   <h> CPU Clock Configuration Register (CCLKCFG)
  88 //     <o7.0..7>  CCLKSEL: Divide Value for CPU Clock from PLL0
  89 //                     <1-256><#-1>
  90 //   </h>
  91 //
  92 //   <h> USB Clock Configuration Register (USBCLKCFG)
  93 //     <o8.0..3>   USBSEL: Divide Value for USB Clock from PLL0
  94 //                     <0-15>
  95 //                     <i> Divide is USBSEL + 1
  96 //   </h>
  97 //
  98 //   <h> Peripheral Clock Selection Register 0 (PCLKSEL0)
  99 //     <o9.0..1>    PCLK_WDT: Peripheral Clock Selection for WDT
 100 //                     <0=> Pclk = Cclk / 4
 101 //                     <1=> Pclk = Cclk
 102 //                     <2=> Pclk = Cclk / 2
 103 //                     <3=> Pclk = Hclk / 8
 104 //     <o9.2..3>    PCLK_TIMER0: Peripheral Clock Selection for TIMER0
 105 //                     <0=> Pclk = Cclk / 4
 106 //                     <1=> Pclk = Cclk
 107 //                     <2=> Pclk = Cclk / 2
 108 //                     <3=> Pclk = Hclk / 8
 109 //     <o9.4..5>    PCLK_TIMER1: Peripheral Clock Selection for TIMER1
 110 //                     <0=> Pclk = Cclk / 4
 111 //                     <1=> Pclk = Cclk
 112 //                     <2=> Pclk = Cclk / 2
 113 //                     <3=> Pclk = Hclk / 8
 114 //     <o9.6..7>    PCLK_UART0: Peripheral Clock Selection for UART0
 115 //                     <0=> Pclk = Cclk / 4
 116 //                     <1=> Pclk = Cclk
 117 //                     <2=> Pclk = Cclk / 2
 118 //                     <3=> Pclk = Hclk / 8
 119 //     <o9.8..9>    PCLK_UART1: Peripheral Clock Selection for UART1
 120 //                     <0=> Pclk = Cclk / 4
 121 //                     <1=> Pclk = Cclk
 122 //                     <2=> Pclk = Cclk / 2
 123 //                     <3=> Pclk = Hclk / 8
 124 //     <o9.12..13>  PCLK_PWM1: Peripheral Clock Selection for PWM1
 125 //                     <0=> Pclk = Cclk / 4
 126 //                     <1=> Pclk = Cclk
 127 //                     <2=> Pclk = Cclk / 2
 128 //                     <3=> Pclk = Hclk / 8
 129 //     <o9.14..15>  PCLK_I2C0: Peripheral Clock Selection for I2C0
 130 //                     <0=> Pclk = Cclk / 4
 131 //                     <1=> Pclk = Cclk
 132 //                     <2=> Pclk = Cclk / 2
 133 //                     <3=> Pclk = Hclk / 8
 134 //     <o9.16..17>  PCLK_SPI: Peripheral Clock Selection for SPI
 135 //                     <0=> Pclk = Cclk / 4
 136 //                     <1=> Pclk = Cclk
 137 //                     <2=> Pclk = Cclk / 2
 138 //                     <3=> Pclk = Hclk / 8
 139 //     <o9.20..21>  PCLK_SSP1: Peripheral Clock Selection for SSP1
 140 //                     <0=> Pclk = Cclk / 4
 141 //                     <1=> Pclk = Cclk
 142 //                     <2=> Pclk = Cclk / 2
 143 //                     <3=> Pclk = Hclk / 8
 144 //     <o9.22..23>  PCLK_DAC: Peripheral Clock Selection for DAC
 145 //                     <0=> Pclk = Cclk / 4
 146 //                     <1=> Pclk = Cclk
 147 //                     <2=> Pclk = Cclk / 2
 148 //                     <3=> Pclk = Hclk / 8
 149 //     <o9.24..25>  PCLK_ADC: Peripheral Clock Selection for ADC
 150 //                     <0=> Pclk = Cclk / 4
 151 //                     <1=> Pclk = Cclk
 152 //                     <2=> Pclk = Cclk / 2
 153 //                     <3=> Pclk = Hclk / 8
 154 //     <o9.26..27>  PCLK_CAN1: Peripheral Clock Selection for CAN1
 155 //                     <0=> Pclk = Cclk / 4
 156 //                     <1=> Pclk = Cclk
 157 //                     <2=> Pclk = Cclk / 2
 158 //                     <3=> Pclk = Hclk / 6
 159 //     <o9.28..29>  PCLK_CAN2: Peripheral Clock Selection for CAN2
 160 //                     <0=> Pclk = Cclk / 4
 161 //                     <1=> Pclk = Cclk
 162 //                     <2=> Pclk = Cclk / 2
 163 //                     <3=> Pclk = Hclk / 6
 164 //     <o9.30..31>  PCLK_ACF: Peripheral Clock Selection for ACF
 165 //                     <0=> Pclk = Cclk / 4
 166 //                     <1=> Pclk = Cclk
 167 //                     <2=> Pclk = Cclk / 2
 168 //                     <3=> Pclk = Hclk / 6
 169 //   </h>
 170 //
 171 //   <h> Peripheral Clock Selection Register 1 (PCLKSEL1)
 172 //     <o10.0..1>   PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface
 173 //                     <0=> Pclk = Cclk / 4
 174 //                     <1=> Pclk = Cclk
 175 //                     <2=> Pclk = Cclk / 2
 176 //                     <3=> Pclk = Hclk / 8
 177 //     <o10.2..3>   PCLK_GPIO: Peripheral Clock Selection for GPIOs
 178 //                     <0=> Pclk = Cclk / 4
 179 //                     <1=> Pclk = Cclk
 180 //                     <2=> Pclk = Cclk / 2
 181 //                     <3=> Pclk = Hclk / 8
 182 //     <o10.4..5>   PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block
 183 //                     <0=> Pclk = Cclk / 4
 184 //                     <1=> Pclk = Cclk
 185 //                     <2=> Pclk = Cclk / 2
 186 //                     <3=> Pclk = Hclk / 8
 187 //     <o10.6..7>   PCLK_I2C1: Peripheral Clock Selection for I2C1
 188 //                     <0=> Pclk = Cclk / 4
 189 //                     <1=> Pclk = Cclk
 190 //                     <2=> Pclk = Cclk / 2
 191 //                     <3=> Pclk = Hclk / 8
 192 //     <o10.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0
 193 //                     <0=> Pclk = Cclk / 4
 194 //                     <1=> Pclk = Cclk
 195 //                     <2=> Pclk = Cclk / 2
 196 //                     <3=> Pclk = Hclk / 8
 197 //     <o10.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2
 198 //                     <0=> Pclk = Cclk / 4
 199 //                     <1=> Pclk = Cclk
 200 //                     <2=> Pclk = Cclk / 2
 201 //                     <3=> Pclk = Hclk / 8
 202 //     <o10.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3
 203 //                     <0=> Pclk = Cclk / 4
 204 //                     <1=> Pclk = Cclk
 205 //                     <2=> Pclk = Cclk / 2
 206 //                     <3=> Pclk = Hclk / 8
 207 //     <o10.16..17> PCLK_UART2: Peripheral Clock Selection for UART2
 208 //                     <0=> Pclk = Cclk / 4
 209 //                     <1=> Pclk = Cclk
 210 //                     <2=> Pclk = Cclk / 2
 211 //                     <3=> Pclk = Hclk / 8
 212 //     <o10.18..19> PCLK_UART3: Peripheral Clock Selection for UART3
 213 //                     <0=> Pclk = Cclk / 4
 214 //                     <1=> Pclk = Cclk
 215 //                     <2=> Pclk = Cclk / 2
 216 //                     <3=> Pclk = Hclk / 8
 217 //     <o10.20..21> PCLK_I2C2: Peripheral Clock Selection for I2C2
 218 //                     <0=> Pclk = Cclk / 4
 219 //                     <1=> Pclk = Cclk
 220 //                     <2=> Pclk = Cclk / 2
 221 //                     <3=> Pclk = Hclk / 8
 222 //     <o10.22..23> PCLK_I2S: Peripheral Clock Selection for I2S
 223 //                     <0=> Pclk = Cclk / 4
 224 //                     <1=> Pclk = Cclk
 225 //                     <2=> Pclk = Cclk / 2
 226 //                     <3=> Pclk = Hclk / 8
 227 //     <o10.26..27> PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer
 228 //                     <0=> Pclk = Cclk / 4
 229 //                     <1=> Pclk = Cclk
 230 //                     <2=> Pclk = Cclk / 2
 231 //                     <3=> Pclk = Hclk / 8
 232 //     <o10.28..29> PCLK_SYSCON: Peripheral Clock Selection for the System Control Block
 233 //                     <0=> Pclk = Cclk / 4
 234 //                     <1=> Pclk = Cclk
 235 //                     <2=> Pclk = Cclk / 2
 236 //                     <3=> Pclk = Hclk / 8
 237 //     <o10.30..31> PCLK_MC: Peripheral Clock Selection for the Motor Control PWM
 238 //                     <0=> Pclk = Cclk / 4
 239 //                     <1=> Pclk = Cclk
 240 //                     <2=> Pclk = Cclk / 2
 241 //                     <3=> Pclk = Hclk / 8
 242 //   </h>
 243 //
 244 //   <h> Power Control for Peripherals Register (PCONP)
 245 //     <o11.1>      PCTIM0: Timer/Counter 0 power/clock enable
 246 //     <o11.2>      PCTIM1: Timer/Counter 1 power/clock enable
 247 //     <o11.3>      PCUART0: UART 0 power/clock enable
 248 //     <o11.4>      PCUART1: UART 1 power/clock enable
 249 //     <o11.6>      PCPWM1: PWM 1 power/clock enable
 250 //     <o11.7>      PCI2C0: I2C interface 0 power/clock enable
 251 //     <o11.8>      PCSPI: SPI interface power/clock enable
 252 //     <o11.9>      PCRTC: RTC power/clock enable
 253 //     <o11.10>     PCSSP1: SSP interface 1 power/clock enable
 254 //     <o11.12>     PCAD: A/D converter power/clock enable
 255 //     <o11.13>     PCCAN1: CAN controller 1 power/clock enable
 256 //     <o11.14>     PCCAN2: CAN controller 2 power/clock enable
 257 //     <o11.15>     PCGPIO: GPIOs power/clock enable
 258 //     <o11.16>     PCRIT: Repetitive interrupt timer power/clock enable
 259 //     <o11.17>     PCMC: Motor control PWM power/clock enable
 260 //     <o11.18>     PCQEI: Quadrature encoder interface power/clock enable
 261 //     <o11.19>     PCI2C1: I2C interface 1 power/clock enable
 262 //     <o11.21>     PCSSP0: SSP interface 0 power/clock enable
 263 //     <o11.22>     PCTIM2: Timer 2 power/clock enable
 264 //     <o11.23>     PCTIM3: Timer 3 power/clock enable
 265 //     <o11.24>     PCUART2: UART 2 power/clock enable
 266 //     <o11.25>     PCUART3: UART 3 power/clock enable
 267 //     <o11.26>     PCI2C2: I2C interface 2 power/clock enable
 268 //     <o11.27>     PCI2S: I2S interface power/clock enable
 269 //     <o11.29>     PCGPDMA: GP DMA function power/clock enable
 270 //     <o11.30>     PCENET: Ethernet block power/clock enable
 271 //     <o11.31>     PCUSB: USB interface power/clock enable
 272 //   </h>
 273 //
 274 //   <h> Clock Output Configuration Register (CLKOUTCFG)
 275 //     <o12.0..3>   CLKOUTSEL: Selects clock source for CLKOUT
 276 //                     <0=> CPU clock
 277 //                     <1=> Main oscillator
 278 //                     <2=> Internal RC oscillator
 279 //                     <3=> USB clock
 280 //                     <4=> RTC oscillator
 281 //     <o12.4..7>   CLKOUTDIV: Selects clock divider for CLKOUT
 282 //                     <1-16><#-1>
 283 //     <o12.8>      CLKOUT_EN: CLKOUT enable control
 284 //   </h>
 285 //
 286 // </e>
 287 */
 288
 289
 290
 291 /** @addtogroup LPC17xx_System_Defines  LPC17xx System Defines
 292   @{
 293  */
 294
 295 #define CLOCK_SETUP           1
 296 #define SCS_Val               0x00000020
 297 #define CLKSRCSEL_Val         0x00000001
 298 #define PLL0_SETUP            1
 299
 300 #ifdef MCB1700
 301 #    define PLL0CFG_Val           0x00050063
 302 #    define PLL1_SETUP            1
 303 #    define PLL1CFG_Val           0x00000023
 304 #    define CCLKCFG_Val           0x00000003
 305 #    define USBCLKCFG_Val         0x00000000
 306 #else
 307
 308 #    define PLL0CFG_Val           0x0000000B // 96Mhz
 309 #    define PLL1_SETUP            0
 310 #    define PLL1CFG_Val           0x00000000
 311 #    define CCLKCFG_Val           0x00000002
 312 #    define USBCLKCFG_Val         0x00000005
 313 #endif
 314
 315 #define PCLKSEL0_Val          0x00000000
 316 #define PCLKSEL1_Val          0x00000000
 317 #define PCONP_Val             0x042887DE
 318 #define CLKOUTCFG_Val         0x00000000
 319
 320
 321 /*--------------------- Flash Accelerator Configuration ----------------------
 322 //
 323 // <e> Flash Accelerator Configuration
 324 //   <o1.12..15> FLASHTIM: Flash Access Time
 325 //               <0=> 1 CPU clock (for CPU clock up to 20 MHz)
 326 //               <1=> 2 CPU clocks (for CPU clock up to 40 MHz)
 327 //               <2=> 3 CPU clocks (for CPU clock up to 60 MHz)
 328 //               <3=> 4 CPU clocks (for CPU clock up to 80 MHz)
 329 //               <4=> 5 CPU clocks (for CPU clock up to 100 MHz)
 330 //               <5=> 6 CPU clocks (for any CPU clock)
 331 // </e>
 332 */
 333 #define FLASH_SETUP           1
 334 #define FLASHCFG_Val          0x0000303A
 335
 336 /*
 337 //-------- <<< end of configuration section >>> ------------------------------
 338 */
 339
 340 /*----------------------------------------------------------------------------
 341   Check the register settings
 342  *----------------------------------------------------------------------------*/
 343 #define CHECK_RANGE(val, min, max)                ((val < min) || (val > max))
 344 #define CHECK_RSVD(val, mask)                     (val & mask)
 345
 346 /* Clock Configuration -------------------------------------------------------*/
 347 #if (CHECK_RSVD((SCS_Val),       ~0x00000030))
 348    #error "SCS: Invalid values of reserved bits!"
 349 #endif
 350
 351 #if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2))
 352    #error "CLKSRCSEL: Value out of range!"
 353 #endif
 354
 355 #if (CHECK_RSVD((PLL0CFG_Val),   ~0x00FF7FFF))
 356    #error "PLL0CFG: Invalid values of reserved bits!"
 357 #endif
 358
 359 #if (CHECK_RSVD((PLL1CFG_Val),   ~0x0000007F))
 360    #error "PLL1CFG: Invalid values of reserved bits!"
 361 #endif
 362
 363 #if (PLL0_SETUP)            /* if PLL0 is used */
 364   #if (CCLKCFG_Val < 2)     /* CCLKSEL must be greater then 1 */
 365     #error "CCLKCFG: CCLKSEL must be greater then 1 if PLL0 is used!"
 366   #endif
 367 #endif
 368
 369 #if (CHECK_RANGE((CCLKCFG_Val), 2, 255))
 370    #error "CCLKCFG: Value out of range!"
 371 #endif
 372
 373 #if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F))
 374    #error "USBCLKCFG: Invalid values of reserved bits!"
 375 #endif
 376
 377 #if (CHECK_RSVD((PCLKSEL0_Val),   0x000C0C00))
 378    #error "PCLKSEL0: Invalid values of reserved bits!"
 379 #endif
 380
 381 #if (CHECK_RSVD((PCLKSEL1_Val),   0x03000300))
 382    #error "PCLKSEL1: Invalid values of reserved bits!"
 383 #endif
 384
 385 #if (CHECK_RSVD((PCONP_Val),      0x10100821))
 386    #error "PCONP: Invalid values of reserved bits!"
 387 #endif
 388
 389 #if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
 390    #error "CLKOUTCFG: Invalid values of reserved bits!"
 391 #endif
 392
 393 /* Flash Accelerator Configuration -------------------------------------------*/
 394 #if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F07F))
 395    #error "FLASHCFG: Invalid values of reserved bits!"
 396 #endif
 397
 398
 399 /*----------------------------------------------------------------------------
 400   DEFINES
 401  *----------------------------------------------------------------------------*/
 402
 403 /*----------------------------------------------------------------------------
 404   Define clocks
 405  *----------------------------------------------------------------------------*/
 406 #define XTAL        (12000000UL)        /* Oscillator frequency               */
 407 #define OSC_CLK     (      XTAL)        /* Main oscillator frequency          */
 408 #define RTC_CLK     (   32000UL)        /* RTC oscillator frequency           */
 409 #define IRC_OSC     ( 4000000UL)        /* Internal RC oscillator frequency   */
 410
 411
 412 /* F_cco0 = (2 * M * F_in) / N  */
 413 #define __M               (((PLL0CFG_Val      ) & 0x7FFF) + 1)
 414 #define __N               (((PLL0CFG_Val >> 16) & 0x00FF) + 1)
 415 #define __FCCO(__F_IN)    ((2ULL * __M * __F_IN) / __N)
 416 #define __CCLK_DIV        (((CCLKCFG_Val      ) & 0x00FF) + 1)
 417
 418 /* Determine core clock frequency according to settings */
 419  #if (PLL0_SETUP)
 420     #if   ((CLKSRCSEL_Val & 0x03) == 1)
 421         #define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV)
 422     #elif ((CLKSRCSEL_Val & 0x03) == 2)
 423         #define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV)
 424     #else
 425         #define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV)
 426     #endif
 427  #else
 428     #if   ((CLKSRCSEL_Val & 0x03) == 1)
 429         #define __CORE_CLK (OSC_CLK         / __CCLK_DIV)
 430     #elif ((CLKSRCSEL_Val & 0x03) == 2)
 431         #define __CORE_CLK (RTC_CLK         / __CCLK_DIV)
 432     #else
 433         #define __CORE_CLK (IRC_OSC         / __CCLK_DIV)
 434     #endif
 435  #endif
 436
 437 /**
 438  * @}
 439  */
 440
 441
 442 /** @addtogroup LPC17xx_System_Public_Variables  LPC17xx System Public Variables
 443   @{
 444  */
 445 /*----------------------------------------------------------------------------
 446   Clock Variable definitions
 447  *----------------------------------------------------------------------------*/
 448 uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
 449
 450 /**
 451  * @}
 452  */
 453
 454
 455 /** @addtogroup LPC17xx_System_Public_Functions  LPC17xx System Public Functions
 456   @{
 457  */
 458
 459 /**
 460  * Update SystemCoreClock variable
 461  *
 462  * @param  none
 463  * @return none
 464  *
 465  * @brief  Updates the SystemCoreClock with current core Clock
 466  *         retrieved from cpu registers.
 467  */
 468
 469 void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
 470 {
 471   /* Determine clock frequency according to clock register values             */
 472   if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */
 473     switch (LPC_SC->CLKSRCSEL & 0x03) {
 474       case 0:                                /* Int. RC oscillator => PLL0    */
 475       case 3:                                /* Reserved, default to Int. RC  */
 476         SystemCoreClock = (IRC_OSC *
 477                           ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1)))  /
 478                           (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)       /
 479                           ((LPC_SC->CCLKCFG & 0xFF)+ 1));
 480         break;
 481       case 1:                                /* Main oscillator => PLL0       */
 482         SystemCoreClock = (OSC_CLK *
 483                           ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1)))  /
 484                           (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)       /
 485                           ((LPC_SC->CCLKCFG & 0xFF)+ 1));
 486         break;
 487       case 2:                                /* RTC oscillator => PLL0        */
 488         SystemCoreClock = (RTC_CLK *
 489                           ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1)))  /
 490                           (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)       /
 491                           ((LPC_SC->CCLKCFG & 0xFF)+ 1));
 492         break;
 493     }
 494   } else {
 495     switch (LPC_SC->CLKSRCSEL & 0x03) {
 496       case 0:                                /* Int. RC oscillator => PLL0    */
 497       case 3:                                /* Reserved, default to Int. RC  */
 498         SystemCoreClock = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
 499         break;
 500       case 1:                                /* Main oscillator => PLL0       */
 501         SystemCoreClock = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
 502         break;
 503       case 2:                                /* RTC oscillator => PLL0        */
 504         SystemCoreClock = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
 505         break;
 506     }
 507   }
 508
 509 }
 510
 511 // detect 1768 or 1769
 512 static int isLPC1769() {
 513     #define IAP_LOCATION 0x1FFF1FF1
 514     uint32_t command[1];
 515     uint32_t result[5];
 516     typedef void (*IAP)(uint32_t*, uint32_t*);
 517     IAP iap = (IAP) IAP_LOCATION;
 518
 519     command[0] = 54;
 520     iap(command, result);
 521
 522     return result[1] & 0x00100000;
 523 }
 524
 525
 526 // Make sure we are pulling in the retargeting module at link time
 527 extern int stdio_retargeting_module;
 528
 529 /**
 530  * Initialize the system
 531  *
 532  * @param  none
 533  * @return none
 534  *
 535  * @brief  Setup the microcontroller system.
 536  *         Initialize the System.
 537  */
 538 void SystemInit (void)
 539 {
 540 #if (CLOCK_SETUP)                       /* Clock Setup                        */
 541   LPC_SC->SCS       = SCS_Val;
 542   if (LPC_SC->SCS & (1 << 5)) {             /* If Main Oscillator is enabled  */
 543     while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready    */
 544   }
 545
 546
 547   if(isLPC1769()) {
 548     LPC_SC->CCLKCFG   = 0x00000003;      /* Setup Clock Divider                */
 549     /* Periphral clock must be selected before PLL0 enabling and connecting
 550      * - according errata.lpc1768-16.March.2010 -
 551      */
 552     LPC_SC->PCLKSEL0  = PCLKSEL0_Val;     /* Peripheral Clock Selection         */
 553     LPC_SC->PCLKSEL1  = PCLKSEL1_Val;
 554     LPC_SC->CLKSRCSEL = CLKSRCSEL_Val;    /* Select Clock Source for PLL0       */
 555
 556     LPC_SC->PLL0CFG   = 0x00000013;      /* configure PLL0                     */
 557     LPC_SC->PLL0FEED  = 0xAA;
 558     LPC_SC->PLL0FEED  = 0x55;
 559
 560     LPC_SC->PLL0CON   = 0x01;             /* PLL0 Enable                        */
 561     LPC_SC->PLL0FEED  = 0xAA;
 562     LPC_SC->PLL0FEED  = 0x55;
 563     while (!(LPC_SC->PLL0STAT & (1<<26)));/* Wait for PLOCK0                    */
 564
 565     LPC_SC->PLL0CON   = 0x03;             /* PLL0 Enable & Connect              */
 566     LPC_SC->PLL0FEED  = 0xAA;
 567     LPC_SC->PLL0FEED  = 0x55;
 568     while (!(LPC_SC->PLL0STAT & ((1<<25) | (1<<24))));/* Wait for PLLC0_STAT & PLLE0_STAT */
 569
 570     LPC_SC->PLL1CFG   = 0x00000023;
 571     LPC_SC->PLL1FEED  = 0xAA;
 572     LPC_SC->PLL1FEED  = 0x55;
 573
 574     LPC_SC->PLL1CON   = 0x01;             /* PLL1 Enable                        */
 575     LPC_SC->PLL1FEED  = 0xAA;
 576     LPC_SC->PLL1FEED  = 0x55;
 577     while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1                    */
 578
 579     LPC_SC->PLL1CON   = 0x03;             /* PLL1 Enable & Connect              */
 580     LPC_SC->PLL1FEED  = 0xAA;
 581     LPC_SC->PLL1FEED  = 0x55;
 582     while (!(LPC_SC->PLL1STAT & ((1<< 9) | (1<< 8))));/* Wait for PLLC1_STAT & PLLE1_STAT */
 583
 584     // this sets up the clock to show the new speed
 585     SystemCoreClockUpdate();
 586
 587   }else{
 588
 589   LPC_SC->CCLKCFG   = CCLKCFG_Val;      /* Setup Clock Divider                */
 590   /* Periphral clock must be selected before PLL0 enabling and connecting
 591    * - according errata.lpc1768-16.March.2010 -
 592    */
 593   LPC_SC->PCLKSEL0  = PCLKSEL0_Val;     /* Peripheral Clock Selection         */
 594   LPC_SC->PCLKSEL1  = PCLKSEL1_Val;
 595
 596 #if (PLL0_SETUP)
 597   LPC_SC->CLKSRCSEL = CLKSRCSEL_Val;    /* Select Clock Source for PLL0       */
 598
 599   LPC_SC->PLL0CFG   = PLL0CFG_Val;      /* configure PLL0                     */
 600   LPC_SC->PLL0FEED  = 0xAA;
 601   LPC_SC->PLL0FEED  = 0x55;
 602
 603   LPC_SC->PLL0CON   = 0x01;             /* PLL0 Enable                        */
 604   LPC_SC->PLL0FEED  = 0xAA;
 605   LPC_SC->PLL0FEED  = 0x55;
 606   while (!(LPC_SC->PLL0STAT & (1<<26)));/* Wait for PLOCK0                    */
 607
 608   LPC_SC->PLL0CON   = 0x03;             /* PLL0 Enable & Connect              */
 609   LPC_SC->PLL0FEED  = 0xAA;
 610   LPC_SC->PLL0FEED  = 0x55;
 611   while (!(LPC_SC->PLL0STAT & ((1<<25) | (1<<24))));/* Wait for PLLC0_STAT & PLLE0_STAT */
 612 #endif
 613
 614 #if (PLL1_SETUP)
 615   LPC_SC->PLL1CFG   = PLL1CFG_Val;
 616   LPC_SC->PLL1FEED  = 0xAA;
 617   LPC_SC->PLL1FEED  = 0x55;
 618
 619   LPC_SC->PLL1CON   = 0x01;             /* PLL1 Enable                        */
 620   LPC_SC->PLL1FEED  = 0xAA;
 621   LPC_SC->PLL1FEED  = 0x55;
 622   while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1                    */
 623
 624   LPC_SC->PLL1CON   = 0x03;             /* PLL1 Enable & Connect              */
 625   LPC_SC->PLL1FEED  = 0xAA;
 626   LPC_SC->PLL1FEED  = 0x55;
 627   while (!(LPC_SC->PLL1STAT & ((1<< 9) | (1<< 8))));/* Wait for PLLC1_STAT & PLLE1_STAT */
 628 #else
 629   LPC_SC->USBCLKCFG = USBCLKCFG_Val;    /* Setup USB Clock Divider            */
 630 #endif
 631 }
 632
 633   LPC_SC->PCONP     = PCONP_Val;        /* Power Control for Peripherals      */
 634
 635   LPC_SC->CLKOUTCFG = CLKOUTCFG_Val;    /* Clock Output Configuration         */
 636 #endif
 637
 638 #if (FLASH_SETUP == 1)                  /* Flash Accelerator Setup            */
 639   LPC_SC->FLASHCFG  = (LPC_SC->FLASHCFG & ~0x0000F000) | FLASHCFG_Val;
 640 #endif
 641
 642   stdio_retargeting_module = 1;
 643 }
 644
 645 /**
 646  * @}
 647  */
 648
 649 /**
 650  * @}
 651  */