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[clinton/Smoothieware.git] / gcc4mbed / external / mbed / LPC1768 / core_cmFunc.h

/**************************************************************************//**\r
 * @file     core_cmFunc.h\r
 * @brief    CMSIS Cortex-M Core Function Access Header File\r
 * @version  V3.00\r
 * @date     09. December 2011\r
 *\r
 * @note\r
 * Copyright (C) 2009-2011 ARM Limited. All rights reserved.\r
 *\r
 * @par\r
 * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
 * processor based microcontrollers.  This file can be freely distributed \r
 * within development tools that are supporting such ARM based processors. \r
 *\r
 * @par\r
 * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
 *\r
 ******************************************************************************/\r
\r
#ifndef __CORE_CMFUNC_H\r
#define __CORE_CMFUNC_H\r
\r
\r
/* ###########################  Core Function Access  ########################### */\r
/** \ingroup  CMSIS_Core_FunctionInterface   \r
    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
  @{\r
 */\r
\r
#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
/* ARM armcc specific functions */\r
\r
#if (__ARMCC_VERSION < 400677)\r
  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"\r
#endif\r
\r
/* intrinsic void __enable_irq();     */\r
/* intrinsic void __disable_irq();    */\r
\r
/** \brief  Get Control Register\r
\r
    This function returns the content of the Control Register.\r
\r
    \return               Control Register value\r
 */\r
static __INLINE uint32_t __get_CONTROL(void)\r
{\r
  register uint32_t __regControl         __ASM("control");\r
  return(__regControl);\r
}\r
\r
\r
/** \brief  Set Control Register\r
\r
    This function writes the given value to the Control Register.\r
\r
    \param [in]    control  Control Register value to set\r
 */\r
static __INLINE void __set_CONTROL(uint32_t control)\r
{\r
  register uint32_t __regControl         __ASM("control");\r
  __regControl = control;\r
}\r
\r
\r
/** \brief  Get IPSR Register\r
\r
    This function returns the content of the IPSR Register.\r
\r
    \return               IPSR Register value\r
 */\r
static __INLINE uint32_t __get_IPSR(void)\r
{\r
  register uint32_t __regIPSR          __ASM("ipsr");\r
  return(__regIPSR);\r
}\r
\r
\r
/** \brief  Get APSR Register\r
\r
    This function returns the content of the APSR Register.\r
\r
    \return               APSR Register value\r
 */\r
static __INLINE uint32_t __get_APSR(void)\r
{\r
  register uint32_t __regAPSR          __ASM("apsr");\r
  return(__regAPSR);\r
}\r
\r
\r
/** \brief  Get xPSR Register\r
\r
    This function returns the content of the xPSR Register.\r
\r
    \return               xPSR Register value\r
 */\r
static __INLINE uint32_t __get_xPSR(void)\r
{\r
  register uint32_t __regXPSR          __ASM("xpsr");\r
  return(__regXPSR);\r
}\r
\r
\r
/** \brief  Get Process Stack Pointer\r
\r
    This function returns the current value of the Process Stack Pointer (PSP).\r
\r
    \return               PSP Register value\r
 */\r
static __INLINE uint32_t __get_PSP(void)\r
{\r
  register uint32_t __regProcessStackPointer  __ASM("psp");\r
  return(__regProcessStackPointer);\r
}\r
\r
\r
/** \brief  Set Process Stack Pointer\r
\r
    This function assigns the given value to the Process Stack Pointer (PSP).\r
\r
    \param [in]    topOfProcStack  Process Stack Pointer value to set\r
 */\r
static __INLINE void __set_PSP(uint32_t topOfProcStack)\r
{\r
  register uint32_t __regProcessStackPointer  __ASM("psp");\r
  __regProcessStackPointer = topOfProcStack;\r
}\r
\r
\r
/** \brief  Get Main Stack Pointer\r
\r
    This function returns the current value of the Main Stack Pointer (MSP).\r
\r
    \return               MSP Register value\r
 */\r
static __INLINE uint32_t __get_MSP(void)\r
{\r
  register uint32_t __regMainStackPointer     __ASM("msp");\r
  return(__regMainStackPointer);\r
}\r
\r
\r
/** \brief  Set Main Stack Pointer\r
\r
    This function assigns the given value to the Main Stack Pointer (MSP).\r
\r
    \param [in]    topOfMainStack  Main Stack Pointer value to set\r
 */\r
static __INLINE void __set_MSP(uint32_t topOfMainStack)\r
{\r
  register uint32_t __regMainStackPointer     __ASM("msp");\r
  __regMainStackPointer = topOfMainStack;\r
}\r
\r
\r
/** \brief  Get Priority Mask\r
\r
    This function returns the current state of the priority mask bit from the Priority Mask Register.\r
\r
    \return               Priority Mask value\r
 */\r
static __INLINE uint32_t __get_PRIMASK(void)\r
{\r
  register uint32_t __regPriMask         __ASM("primask");\r
  return(__regPriMask);\r
}\r
\r
\r
/** \brief  Set Priority Mask\r
\r
    This function assigns the given value to the Priority Mask Register.\r
\r
    \param [in]    priMask  Priority Mask\r
 */\r
static __INLINE void __set_PRIMASK(uint32_t priMask)\r
{\r
  register uint32_t __regPriMask         __ASM("primask");\r
  __regPriMask = (priMask);\r
}\r
 \r
\r
#if       (__CORTEX_M >= 0x03)\r
\r
/** \brief  Enable FIQ\r
\r
    This function enables FIQ interrupts by clearing the F-bit in the CPSR.\r
    Can only be executed in Privileged modes.\r
 */\r
#define __enable_fault_irq                __enable_fiq\r
\r
\r
/** \brief  Disable FIQ\r
\r
    This function disables FIQ interrupts by setting the F-bit in the CPSR.\r
    Can only be executed in Privileged modes.\r
 */\r
#define __disable_fault_irq               __disable_fiq\r
\r
\r
/** \brief  Get Base Priority\r
\r
    This function returns the current value of the Base Priority register.\r
\r
    \return               Base Priority register value\r
 */\r
static __INLINE uint32_t  __get_BASEPRI(void)\r
{\r
  register uint32_t __regBasePri         __ASM("basepri");\r
  return(__regBasePri);\r
}\r
\r
\r
/** \brief  Set Base Priority\r
\r
    This function assigns the given value to the Base Priority register.\r
\r
    \param [in]    basePri  Base Priority value to set\r
 */\r
static __INLINE void __set_BASEPRI(uint32_t basePri)\r
{\r
  register uint32_t __regBasePri         __ASM("basepri");\r
  __regBasePri = (basePri & 0xff);\r
}\r
 \r
\r
/** \brief  Get Fault Mask\r
\r
    This function returns the current value of the Fault Mask register.\r
\r
    \return               Fault Mask register value\r
 */\r
static __INLINE uint32_t __get_FAULTMASK(void)\r
{\r
  register uint32_t __regFaultMask       __ASM("faultmask");\r
  return(__regFaultMask);\r
}\r
\r
\r
/** \brief  Set Fault Mask\r
\r
    This function assigns the given value to the Fault Mask register.\r
\r
    \param [in]    faultMask  Fault Mask value to set\r
 */\r
static __INLINE void __set_FAULTMASK(uint32_t faultMask)\r
{\r
  register uint32_t __regFaultMask       __ASM("faultmask");\r
  __regFaultMask = (faultMask & (uint32_t)1);\r
}\r
\r
#endif /* (__CORTEX_M >= 0x03) */\r
\r
\r
#if       (__CORTEX_M == 0x04)\r
\r
/** \brief  Get FPSCR\r
\r
    This function returns the current value of the Floating Point Status/Control register.\r
\r
    \return               Floating Point Status/Control register value\r
 */\r
static __INLINE uint32_t __get_FPSCR(void)\r
{\r
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
  register uint32_t __regfpscr         __ASM("fpscr");\r
  return(__regfpscr);\r
#else\r
   return(0);\r
#endif\r
}\r
\r
\r
/** \brief  Set FPSCR\r
\r
    This function assigns the given value to the Floating Point Status/Control register.\r
\r
    \param [in]    fpscr  Floating Point Status/Control value to set\r
 */\r
static __INLINE void __set_FPSCR(uint32_t fpscr)\r
{\r
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
  register uint32_t __regfpscr         __ASM("fpscr");\r
  __regfpscr = (fpscr);\r
#endif\r
}\r
\r
#endif /* (__CORTEX_M == 0x04) */\r
\r
\r
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/\r
/* IAR iccarm specific functions */\r
\r
#include <cmsis_iar.h>\r
\r
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/\r
/* GNU gcc specific functions */\r
\r
/** \brief  Enable IRQ Interrupts\r
\r
  This function enables IRQ interrupts by clearing the I-bit in the CPSR.\r
  Can only be executed in Privileged modes.\r
 */\r
__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)\r
{\r
  __ASM volatile ("cpsie i");\r
}\r
\r
\r
/** \brief  Disable IRQ Interrupts\r
\r
  This function disables IRQ interrupts by setting the I-bit in the CPSR.\r
  Can only be executed in Privileged modes.\r
 */\r
__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)\r
{\r
  __ASM volatile ("cpsid i");\r
}\r
\r
\r
/** \brief  Get Control Register\r
\r
    This function returns the content of the Control Register.\r
\r
    \return               Control Register value\r
 */\r
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)\r
{\r
  uint32_t result;\r
\r
  __ASM volatile ("MRS %0, control" : "=r" (result) );\r
  return(result);\r
}\r
\r
\r
/** \brief  Set Control Register\r
\r
    This function writes the given value to the Control Register.\r
\r
    \param [in]    control  Control Register value to set\r
 */\r
__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)\r
{\r
  __ASM volatile ("MSR control, %0" : : "r" (control) );\r
}\r
\r
\r
/** \brief  Get IPSR Register\r
\r
    This function returns the content of the IPSR Register.\r
\r
    \return               IPSR Register value\r
 */\r
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)\r
{\r
  uint32_t result;\r
\r
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );\r
  return(result);\r
}\r
\r
\r
/** \brief  Get APSR Register\r
\r
    This function returns the content of the APSR Register.\r
\r
    \return               APSR Register value\r
 */\r
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)\r
{\r
  uint32_t result;\r
\r
  __ASM volatile ("MRS %0, apsr" : "=r" (result) );\r
  return(result);\r
}\r
\r
\r
/** \brief  Get xPSR Register\r
\r
    This function returns the content of the xPSR Register.\r
\r
    \return               xPSR Register value\r
 */\r
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)\r
{\r
  uint32_t result;\r
\r
  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );\r
  return(result);\r
}\r
\r
\r
/** \brief  Get Process Stack Pointer\r
\r
    This function returns the current value of the Process Stack Pointer (PSP).\r
\r
    \return               PSP Register value\r
 */\r
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)\r
{\r
  register uint32_t result;\r
\r
  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );\r
  return(result);\r
}\r
 \r
\r
/** \brief  Set Process Stack Pointer\r
\r
    This function assigns the given value to the Process Stack Pointer (PSP).\r
\r
    \param [in]    topOfProcStack  Process Stack Pointer value to set\r
 */\r
__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)\r
{\r
  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );\r
}\r
\r
\r
/** \brief  Get Main Stack Pointer\r
\r
    This function returns the current value of the Main Stack Pointer (MSP).\r
\r
    \return               MSP Register value\r
 */\r
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)\r
{\r
  register uint32_t result;\r
\r
  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );\r
  return(result);\r
}\r
 \r
\r
/** \brief  Set Main Stack Pointer\r
\r
    This function assigns the given value to the Main Stack Pointer (MSP).\r
\r
    \param [in]    topOfMainStack  Main Stack Pointer value to set\r
 */\r
__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)\r
{\r
  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );\r
}\r
\r
\r
/** \brief  Get Priority Mask\r
\r
    This function returns the current state of the priority mask bit from the Priority Mask Register.\r
\r
    \return               Priority Mask value\r
 */\r
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)\r
{\r
  uint32_t result;\r
\r
  __ASM volatile ("MRS %0, primask" : "=r" (result) );\r
  return(result);\r
}\r
\r
\r
/** \brief  Set Priority Mask\r
\r
    This function assigns the given value to the Priority Mask Register.\r
\r
    \param [in]    priMask  Priority Mask\r
 */\r
__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)\r
{\r
  __ASM volatile ("MSR primask, %0" : : "r" (priMask) );\r
}\r
 \r
\r
#if       (__CORTEX_M >= 0x03)\r
\r
/** \brief  Enable FIQ\r
\r
    This function enables FIQ interrupts by clearing the F-bit in the CPSR.\r
    Can only be executed in Privileged modes.\r
 */\r
__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)\r
{\r
  __ASM volatile ("cpsie f");\r
}\r
\r
\r
/** \brief  Disable FIQ\r
\r
    This function disables FIQ interrupts by setting the F-bit in the CPSR.\r
    Can only be executed in Privileged modes.\r
 */\r
__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)\r
{\r
  __ASM volatile ("cpsid f");\r
}\r
\r
\r
/** \brief  Get Base Priority\r
\r
    This function returns the current value of the Base Priority register.\r
\r
    \return               Base Priority register value\r
 */\r
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)\r
{\r
  uint32_t result;\r
  \r
  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );\r
  return(result);\r
}\r
\r
\r
/** \brief  Set Base Priority\r
\r
    This function assigns the given value to the Base Priority register.\r
\r
    \param [in]    basePri  Base Priority value to set\r
 */\r
__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)\r
{\r
  __ASM volatile ("MSR basepri, %0" : : "r" (value) );\r
}\r
\r
\r
/** \brief  Get Fault Mask\r
\r
    This function returns the current value of the Fault Mask register.\r
\r
    \return               Fault Mask register value\r
 */\r
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)\r
{\r
  uint32_t result;\r
  \r
  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
  return(result);\r
}\r
\r
\r
/** \brief  Set Fault Mask\r
\r
    This function assigns the given value to the Fault Mask register.\r
\r
    \param [in]    faultMask  Fault Mask value to set\r
 */\r
__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)\r
{\r
  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );\r
}\r
\r
#endif /* (__CORTEX_M >= 0x03) */\r
\r
\r
#if       (__CORTEX_M == 0x04)\r
\r
/** \brief  Get FPSCR\r
\r
    This function returns the current value of the Floating Point Status/Control register.\r
\r
    \return               Floating Point Status/Control register value\r
 */\r
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)\r
{\r
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
  uint32_t result;\r
\r
  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );\r
  return(result);\r
#else\r
   return(0);\r
#endif\r
}\r
\r
\r
/** \brief  Set FPSCR\r
\r
    This function assigns the given value to the Floating Point Status/Control register.\r
\r
    \param [in]    fpscr  Floating Point Status/Control value to set\r
 */\r
__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)\r
{\r
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );\r
#endif\r
}\r
\r
#endif /* (__CORTEX_M == 0x04) */\r
\r
\r
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/\r
/* TASKING carm specific functions */\r
\r
/*\r
 * The CMSIS functions have been implemented as intrinsics in the compiler.\r
 * Please use "carm -?i" to get an up to date list of all instrinsics,\r
 * Including the CMSIS ones.\r
 */\r
\r
#endif\r
\r
/*@} end of CMSIS_Core_RegAccFunctions */\r
\r
\r
#endif /* __CORE_CMFUNC_H */\r