[jackhill/qmk/firmware.git] / doc / FUSE.txt

Atmega32u4 Fuse/Lock Bits for Planck/Atomic/Preonic
=========================

	Low Fuse: 0x5E
	High Fuse: 0x99
	Extended Fuse: 0xF3
	Lock Byte: 0xFF


ATMega168P Fuse/Lock Bits
=========================
This configuration is from usbasploader's Makefile.

    HFUSE   0xD6
    LFUSE   0xDF
    EFUSE   0x00
    LOCK    0x3F(intact)

#---------------------------------------------------------------------
# ATMega168P
#---------------------------------------------------------------------
# Fuse extended byte:
# 0x00 = 0 0 0 0   0 0 0 0 <-- BOOTRST (boot reset vector at 0x1800)
#                    \+/
#                     +------- BOOTSZ (00 = 2k bytes)
# Fuse high byte:
# 0xd6 = 1 1 0 1   0 1 1 0
#        ^ ^ ^ ^   ^ \-+-/
#        | | | |   |   +------ BODLEVEL 0..2 (110 = 1.8 V)
#        | | | |   + --------- EESAVE (preserve EEPROM over chip erase)
#        | | | +-------------- WDTON (if 0: watchdog always on)
#        | | +---------------- SPIEN (allow serial programming)
#        | +------------------ DWEN (debug wire enable)
#        +-------------------- RSTDISBL (reset pin is enabled)
# Fuse low byte:
# 0xdf = 1 1 0 1   1 1 1 1
#        ^ ^ \ /   \--+--/
#        | |  |       +------- CKSEL 3..0 (external >8M crystal)
#        | |  +--------------- SUT 1..0 (crystal osc, BOD enabled)
#        | +------------------ CKOUT (if 0: Clock output enabled)
#        +-------------------- CKDIV8 (if 0: divide by 8)


# Lock Bits
# 0x3f = - - 1 1   1 1 1 1
#            \ /   \-/ \-/
#             |     |   +----- LB 2..1 (No memory lock features enabled)
#             |     +--------- BLB0 2..1 (No restrictions for SPM or LPM accessing the Application section)
#             +--------------- BLB1 2..1 (No restrictions for SPM or LPM accessing the Boot Loader section)
Commit	Line	Data
e329729d JH	1	Atmega32u4 Fuse/Lock Bits for Planck/Atomic/Preonic
	2	=========================
	3
	4	Low Fuse: 0x5E
	5	High Fuse: 0x99
	6	Extended Fuse: 0xF3
	7	Lock Byte: 0xFF
	8
	9
1a02ebcc	10	ATMega168P Fuse/Lock Bits
	11	=========================
	12	This configuration is from usbasploader's Makefile.
	13
	14	HFUSE 0xD6
	15	LFUSE 0xDF
	16	EFUSE 0x00
	17	LOCK 0x3F(intact)
	18
	19	#---------------------------------------------------------------------
	20	# ATMega168P
	21	#---------------------------------------------------------------------
	22	# Fuse extended byte:
	23	# 0x00 = 0 0 0 0 0 0 0 0 <-- BOOTRST (boot reset vector at 0x1800)
	24	# \+/
	25	# +------- BOOTSZ (00 = 2k bytes)
	26	# Fuse high byte:
	27	# 0xd6 = 1 1 0 1 0 1 1 0
	28	# ^ ^ ^ ^ ^ \-+-/
	29	# \| \| \| \| \| +------ BODLEVEL 0..2 (110 = 1.8 V)
	30	# \| \| \| \| + --------- EESAVE (preserve EEPROM over chip erase)
	31	# \| \| \| +-------------- WDTON (if 0: watchdog always on)
	32	# \| \| +---------------- SPIEN (allow serial programming)
	33	# \| +------------------ DWEN (debug wire enable)
	34	# +-------------------- RSTDISBL (reset pin is enabled)
	35	# Fuse low byte:
	36	# 0xdf = 1 1 0 1 1 1 1 1
	37	# ^ ^ \ / \--+--/
	38	# \| \| \| +------- CKSEL 3..0 (external >8M crystal)
	39	# \| \| +--------------- SUT 1..0 (crystal osc, BOD enabled)
	40	# \| +------------------ CKOUT (if 0: Clock output enabled)
	41	# +-------------------- CKDIV8 (if 0: divide by 8)
	42
	43
	44	# Lock Bits
	45	# 0x3f = - - 1 1 1 1 1 1
	46	# \ / \-/ \-/
	47	# \| \| +----- LB 2..1 (No memory lock features enabled)
	48	# \| +--------- BLB0 2..1 (No restrictions for SPM or LPM accessing the Application section)
	49	# +--------------- BLB1 2..1 (No restrictions for SPM or LPM accessing the Boot Loader section)
e329729d	50