[jackhill/qmk/firmware.git] / drivers / haptic / DRV2605L.h

/* Copyright 2018 ishtob
 * Driver for DRV2605L written for QMK
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#pragma once
#include "i2c_master.h"

/* Initialization settings

 * Feedback Control Settings */
#ifndef FB_ERM_LRA
#    define FB_ERM_LRA 1 /* For ERM:0 or LRA:1*/
#endif
#ifndef FB_BRAKEFACTOR
#    define FB_BRAKEFACTOR 3 /* For 1x:0, 2x:1, 3x:2, 4x:3, 6x:4, 8x:5, 16x:6, Disable Braking:7 */
#endif
#ifndef FB_LOOPGAIN
#    define FB_LOOPGAIN 1 /* For  Low:0, Medium:1, High:2, Very High:3 */
#endif

/* LRA specific settings */
#if FB_ERM_LRA == 1
#    ifndef V_RMS
#        define V_RMS 2.0
#    endif
#    ifndef V_PEAK
#        define V_PEAK 2.1
#    endif
#    ifndef F_LRA
#        define F_LRA 205
#    endif
#    ifndef RATED_VOLTAGE
#        define RATED_VOLTAGE 2 /* 2v as safe range in case device voltage is not set */
#    endif
#endif

#ifndef RATED_VOLTAGE
#    define RATED_VOLTAGE 2 /* 2v as safe range in case device voltage is not set */
#endif
#ifndef V_PEAK
#    define V_PEAK 2.8
#endif

/* Library Selection */
#ifndef LIB_SELECTION
#    if FB_ERM_LRA == 1
#        define LIB_SELECTION 6 /* For Empty:0' TS2200 library A to D:1-5, LRA Library: 6 */
#    else
#        define LIB_SELECTION 1
#    endif
#endif

#ifndef DRV_GREETING
#    define DRV_GREETING alert_750ms
#endif
#ifndef DRV_MODE_DEFAULT
#    define DRV_MODE_DEFAULT strong_click1
#endif

/* Control 1 register settings */
#ifndef DRIVE_TIME
#    define DRIVE_TIME 25
#endif
#ifndef AC_COUPLE
#    define AC_COUPLE 0
#endif
#ifndef STARTUP_BOOST
#    define STARTUP_BOOST 1
#endif

/* Control 2 Settings */
#ifndef BIDIR_INPUT
#    define BIDIR_INPUT 1
#endif
#ifndef BRAKE_STAB
#    define BRAKE_STAB 1 /* Loopgain is reduced when braking is almost complete to improve stability */
#endif
#ifndef SAMPLE_TIME
#    define SAMPLE_TIME 3
#endif
#ifndef BLANKING_TIME
#    define BLANKING_TIME 1
#endif
#ifndef IDISS_TIME
#    define IDISS_TIME 1
#endif

/* Control 3 settings */
#ifndef NG_THRESH
#    define NG_THRESH 2
#endif
#ifndef ERM_OPEN_LOOP
#    define ERM_OPEN_LOOP 1
#endif
#ifndef SUPPLY_COMP_DIS
#    define SUPPLY_COMP_DIS 0
#endif
#ifndef DATA_FORMAT_RTO
#    define DATA_FORMAT_RTO 0
#endif
#ifndef LRA_DRIVE_MODE
#    define LRA_DRIVE_MODE 0
#endif
#ifndef N_PWM_ANALOG
#    define N_PWM_ANALOG 0
#endif
#ifndef LRA_OPEN_LOOP
#    define LRA_OPEN_LOOP 0
#endif

/* Control 4 settings */
#ifndef ZC_DET_TIME
#    define ZC_DET_TIME 0
#endif
#ifndef AUTO_CAL_TIME
#    define AUTO_CAL_TIME 3
#endif

/* register defines -------------------------------------------------------- */
#define DRV2605L_BASE_ADDRESS 0x5A /* DRV2605L Base address */
#define DRV_STATUS 0x00
#define DRV_MODE 0x01
#define DRV_RTP_INPUT 0x02
#define DRV_LIB_SELECTION 0x03
#define DRV_WAVEFORM_SEQ_1 0x04
#define DRV_WAVEFORM_SEQ_2 0x05
#define DRV_WAVEFORM_SEQ_3 0x06
#define DRV_WAVEFORM_SEQ_4 0x07
#define DRV_WAVEFORM_SEQ_5 0x08
#define DRV_WAVEFORM_SEQ_6 0x09
#define DRV_WAVEFORM_SEQ_7 0x0A
#define DRV_WAVEFORM_SEQ_8 0x0B
#define DRV_GO 0x0C
#define DRV_OVERDRIVE_TIME_OFFSET 0x0D
#define DRV_SUSTAIN_TIME_OFFSET_P 0x0E
#define DRV_SUSTAIN_TIME_OFFSET_N 0x0F
#define DRV_BRAKE_TIME_OFFSET 0x10
#define DRV_AUDIO_2_VIBE_CTRL 0x11
#define DRV_AUDIO_2_VIBE_MIN_IN 0x12
#define DRV_AUDIO_2_VIBE_MAX_IN 0x13
#define DRV_AUDIO_2_VIBE_MIN_OUTDRV 0x14
#define DRV_AUDIO_2_VIBE_MAX_OUTDRV 0x15
#define DRV_RATED_VOLT 0x16
#define DRV_OVERDRIVE_CLAMP_VOLT 0x17
#define DRV_AUTO_CALIB_COMP_RESULT 0x18
#define DRV_AUTO_CALIB_BEMF_RESULT 0x19
#define DRV_FEEDBACK_CTRL 0x1A
#define DRV_CTRL_1 0x1B
#define DRV_CTRL_2 0x1C
#define DRV_CTRL_3 0x1D
#define DRV_CTRL_4 0x1E
#define DRV_CTRL_5 0x1F
#define DRV_OPEN_LOOP_PERIOD 0x20
#define DRV_VBAT_VOLT_MONITOR 0x21
#define DRV_LRA_RESONANCE_PERIOD 0x22

void    DRV_init(void);
void    DRV_write(const uint8_t drv_register, const uint8_t settings);
uint8_t DRV_read(const uint8_t regaddress);
void    DRV_rtp_init(void);
void    DRV_amplitude(const uint8_t amplitude);
void    DRV_pulse(const uint8_t sequence);

typedef enum DRV_EFFECT {
    clear_sequence                       = 0,
    strong_click                         = 1,
    strong_click_60                      = 2,
    strong_click_30                      = 3,
    sharp_click                          = 4,
    sharp_click_60                       = 5,
    sharp_click_30                       = 6,
    soft_bump                            = 7,
    soft_bump_60                         = 8,
    soft_bump_30                         = 9,
    dbl_click                            = 10,
    dbl_click_60                         = 11,
    trp_click                            = 12,
    soft_fuzz                            = 13,
    strong_buzz                          = 14,
    alert_750ms                          = 15,
    alert_1000ms                         = 16,
    strong_click1                        = 17,
    strong_click2_80                     = 18,
    strong_click3_60                     = 19,
    strong_click4_30                     = 20,
    medium_click1                        = 21,
    medium_click2_80                     = 22,
    medium_click3_60                     = 23,
    sharp_tick1                          = 24,
    sharp_tick2_80                       = 25,
    sharp_tick3_60                       = 26,
    sh_dblclick_str                      = 27,
    sh_dblclick_str_80                   = 28,
    sh_dblclick_str_60                   = 29,
    sh_dblclick_str_30                   = 30,
    sh_dblclick_med                      = 31,
    sh_dblclick_med_80                   = 32,
    sh_dblclick_med_60                   = 33,
    sh_dblsharp_tick                     = 34,
    sh_dblsharp_tick_80                  = 35,
    sh_dblsharp_tick_60                  = 36,
    lg_dblclick_str                      = 37,
    lg_dblclick_str_80                   = 38,
    lg_dblclick_str_60                   = 39,
    lg_dblclick_str_30                   = 40,
    lg_dblclick_med                      = 41,
    lg_dblclick_med_80                   = 42,
    lg_dblclick_med_60                   = 43,
    lg_dblsharp_tick                     = 44,
    lg_dblsharp_tick_80                  = 45,
    lg_dblsharp_tick_60                  = 46,
    buzz                                 = 47,
    buzz_80                              = 48,
    buzz_60                              = 49,
    buzz_40                              = 50,
    buzz_20                              = 51,
    pulsing_strong                       = 52,
    pulsing_strong_80                    = 53,
    pulsing_medium                       = 54,
    pulsing_medium_80                    = 55,
    pulsing_sharp                        = 56,
    pulsing_sharp_80                     = 57,
    transition_click                     = 58,
    transition_click_80                  = 59,
    transition_click_60                  = 60,
    transition_click_40                  = 61,
    transition_click_20                  = 62,
    transition_click_10                  = 63,
    transition_hum                       = 64,
    transition_hum_80                    = 65,
    transition_hum_60                    = 66,
    transition_hum_40                    = 67,
    transition_hum_20                    = 68,
    transition_hum_10                    = 69,
    transition_rampdown_long_smooth1     = 70,
    transition_rampdown_long_smooth2     = 71,
    transition_rampdown_med_smooth1      = 72,
    transition_rampdown_med_smooth2      = 73,
    transition_rampdown_short_smooth1    = 74,
    transition_rampdown_short_smooth2    = 75,
    transition_rampdown_long_sharp1      = 76,
    transition_rampdown_long_sharp2      = 77,
    transition_rampdown_med_sharp1       = 78,
    transition_rampdown_med_sharp2       = 79,
    transition_rampdown_short_sharp1     = 80,
    transition_rampdown_short_sharp2     = 81,
    transition_rampup_long_smooth1       = 82,
    transition_rampup_long_smooth2       = 83,
    transition_rampup_med_smooth1        = 84,
    transition_rampup_med_smooth2        = 85,
    transition_rampup_short_smooth1      = 86,
    transition_rampup_short_smooth2      = 87,
    transition_rampup_long_sharp1        = 88,
    transition_rampup_long_sharp2        = 89,
    transition_rampup_med_sharp1         = 90,
    transition_rampup_med_sharp2         = 91,
    transition_rampup_short_sharp1       = 92,
    transition_rampup_short_sharp2       = 93,
    transition_rampdown_long_smooth1_50  = 94,
    transition_rampdown_long_smooth2_50  = 95,
    transition_rampdown_med_smooth1_50   = 96,
    transition_rampdown_med_smooth2_50   = 97,
    transition_rampdown_short_smooth1_50 = 98,
    transition_rampdown_short_smooth2_50 = 99,
    transition_rampdown_long_sharp1_50   = 100,
    transition_rampdown_long_sharp2_50   = 101,
    transition_rampdown_med_sharp1_50    = 102,
    transition_rampdown_med_sharp2_50    = 103,
    transition_rampdown_short_sharp1_50  = 104,
    transition_rampdown_short_sharp2_50  = 105,
    transition_rampup_long_smooth1_50    = 106,
    transition_rampup_long_smooth2_50    = 107,
    transition_rampup_med_smooth1_50     = 108,
    transition_rampup_med_smooth2_50     = 109,
    transition_rampup_short_smooth1_50   = 110,
    transition_rampup_short_smooth2_50   = 111,
    transition_rampup_long_sharp1_50     = 112,
    transition_rampup_long_sharp2_50     = 113,
    transition_rampup_med_sharp1_50      = 114,
    transition_rampup_med_sharp2_50      = 115,
    transition_rampup_short_sharp1_50    = 116,
    transition_rampup_short_sharp2_50    = 117,
    long_buzz_for_programmatic_stopping  = 118,
    smooth_hum1_50                       = 119,
    smooth_hum2_40                       = 120,
    smooth_hum3_30                       = 121,
    smooth_hum4_20                       = 122,
    smooth_hum5_10                       = 123,
    drv_effect_max                       = 124,
} DRV_EFFECT;

/* Register bit array unions */

typedef union DRVREG_STATUS { /* register 0x00 */
    uint8_t Byte;
    struct {
        uint8_t OC_DETECT : 1; /* set to 1 when overcurrent event is detected */
        uint8_t OVER_TEMP : 1; /* set to 1 when device exceeds temp threshold */
        uint8_t FB_STS : 1;    /* set to 1 when feedback controller has timed out */
        /* auto-calibration routine and diagnostic result
         * result  |  auto-calibation  |      diagnostic       |
         *   0     |      passed       | actuator func normal  |
         *   1     |      failed       | actuator func fault*  |
         * * actuator is not present or is shorted, timing out, or giving out–of-range back-EMF */
        uint8_t DIAG_RESULT : 1;
        uint8_t : 1;
        uint8_t DEVICE_ID : 3; /* Device IDs 3: DRV2605  4: DRV2604  5: DRV2604L  6: DRV2605L */
    } Bits;
} DRVREG_STATUS;

typedef union DRVREG_MODE { /* register 0x01 */
    uint8_t Byte;
    struct {
        uint8_t MODE : 3; /* Mode setting */
        uint8_t : 3;
        uint8_t STANDBY : 1; /* 0:standby 1:ready */
    } Bits;
} DRVREG_MODE;

typedef union DRVREG_WAIT {
    uint8_t Byte;
    struct {
        uint8_t WAIT_MODE : 1; /* Set to 1 to interpret as wait for next 7 bits x10ms */
        uint8_t WAIT_TIME : 7;
    } Bits;
} DRVREG_WAIT;

typedef union DRVREG_FBR { /* register 0x1A */
    uint8_t Byte;
    struct {
        uint8_t BEMF_GAIN : 2;
        uint8_t LOOP_GAIN : 2;
        uint8_t BRAKE_FACTOR : 3;
        uint8_t ERM_LRA : 1;
    } Bits;
} DRVREG_FBR;

typedef union DRVREG_CTRL1 { /* register 0x1B */
    uint8_t Byte;
    struct {
        uint8_t C1_DRIVE_TIME : 5;
        uint8_t C1_AC_COUPLE : 1;
        uint8_t : 1;
        uint8_t C1_STARTUP_BOOST : 1;
    } Bits;
} DRVREG_CTRL1;

typedef union DRVREG_CTRL2 { /* register 0x1C */
    uint8_t Byte;
    struct {
        uint8_t C2_IDISS_TIME : 2;
        uint8_t C2_BLANKING_TIME : 2;
        uint8_t C2_SAMPLE_TIME : 2;
        uint8_t C2_BRAKE_STAB : 1;
        uint8_t C2_BIDIR_INPUT : 1;
    } Bits;
} DRVREG_CTRL2;

typedef union DRVREG_CTRL3 { /* register 0x1D */
    uint8_t Byte;
    struct {
        uint8_t C3_LRA_OPEN_LOOP : 1;
        uint8_t C3_N_PWM_ANALOG : 1;
        uint8_t C3_LRA_DRIVE_MODE : 1;
        uint8_t C3_DATA_FORMAT_RTO : 1;
        uint8_t C3_SUPPLY_COMP_DIS : 1;
        uint8_t C3_ERM_OPEN_LOOP : 1;
        uint8_t C3_NG_THRESH : 2;
    } Bits;
} DRVREG_CTRL3;

typedef union DRVREG_CTRL4 { /* register 0x1E */
    uint8_t Byte;
    struct {
        uint8_t C4_OTP_PROGRAM : 1;
        uint8_t : 1;
        uint8_t C4_OTP_STATUS : 1;
        uint8_t : 1;
        uint8_t C4_AUTO_CAL_TIME : 2;
        uint8_t C4_ZC_DET_TIME : 2;
    } Bits;
} DRVREG_CTRL4;

typedef union DRVREG_CTRL5 { /* register 0x1F */
    uint8_t Byte;
    struct {
        uint8_t C5_IDISS_TIME : 2;
        uint8_t C5_BLANKING_TIME : 2;
        uint8_t C5_PLAYBACK_INTERVAL : 1;
        uint8_t C5_LRA_AUTO_OPEN_LOOP : 1;
        uint8_t C5_AUTO_OL_CNT : 2;
    } Bits;
} DRVREG_CTRL5;
Commit	Line	Data
4099536c	1	/* Copyright 2018 ishtob
	2	* Driver for DRV2605L written for QMK
	3	*
	4	* This program is free software: you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation, either version 2 of the License, or
	7	* (at your option) any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	16	*/
	17
	18	#pragma once
	19	#include "i2c_master.h"
	20
	21	/* Initialization settings
	22
	23	* Feedback Control Settings */
	24	#ifndef FB_ERM_LRA
b624f32f	25	# define FB_ERM_LRA 1 /* For ERM:0 or LRA:1*/
4099536c	26	#endif
4099536c	27	#ifndef FB_BRAKEFACTOR
b624f32f	28	# define FB_BRAKEFACTOR 3 /* For 1x:0, 2x:1, 3x:2, 4x:3, 6x:4, 8x:5, 16x:6, Disable Braking:7 */
4099536c	29	#endif
4099536c	30	#ifndef FB_LOOPGAIN
b624f32f	31	# define FB_LOOPGAIN 1 /* For Low:0, Medium:1, High:2, Very High:3 */
4099536c	32	#endif
4099536c	33
4099536c	34	/* LRA specific settings */
4099536c	35	#if FB_ERM_LRA == 1
b624f32f	36	# ifndef V_RMS
	37	# define V_RMS 2.0
	38	# endif
	39	# ifndef V_PEAK
	40	# define V_PEAK 2.1
	41	# endif
	42	# ifndef F_LRA
	43	# define F_LRA 205
	44	# endif
	45	# ifndef RATED_VOLTAGE
	46	# define RATED_VOLTAGE 2 /* 2v as safe range in case device voltage is not set */
	47	# endif
2cee371b	48	#endif
	49
	50	#ifndef RATED_VOLTAGE
b624f32f	51	# define RATED_VOLTAGE 2 /* 2v as safe range in case device voltage is not set */
2cee371b	52	#endif
2cee371b	53	#ifndef V_PEAK
b624f32f	54	# define V_PEAK 2.8
4099536c	55	#endif
	56
	57	/* Library Selection */
	58	#ifndef LIB_SELECTION
b624f32f	59	# if FB_ERM_LRA == 1
	60	# define LIB_SELECTION 6 /* For Empty:0' TS2200 library A to D:1-5, LRA Library: 6 */
	61	# else
	62	# define LIB_SELECTION 1
	63	# endif
4099536c	64	#endif
4099536c	65
2cee371b	66	#ifndef DRV_GREETING
b624f32f	67	# define DRV_GREETING alert_750ms
2cee371b	68	#endif
2cee371b	69	#ifndef DRV_MODE_DEFAULT
b624f32f	70	# define DRV_MODE_DEFAULT strong_click1
2cee371b	71	#endif
2cee371b	72
4099536c	73	/* Control 1 register settings */
4099536c	74	#ifndef DRIVE_TIME
b624f32f	75	# define DRIVE_TIME 25
4099536c	76	#endif
4099536c	77	#ifndef AC_COUPLE
b624f32f	78	# define AC_COUPLE 0
4099536c	79	#endif
4099536c	80	#ifndef STARTUP_BOOST
b624f32f	81	# define STARTUP_BOOST 1
4099536c	82	#endif
	83
	84	/* Control 2 Settings */
	85	#ifndef BIDIR_INPUT
b624f32f	86	# define BIDIR_INPUT 1
4099536c	87	#endif
4099536c	88	#ifndef BRAKE_STAB
b624f32f	89	# define BRAKE_STAB 1 /* Loopgain is reduced when braking is almost complete to improve stability */
4099536c	90	#endif
b624f32f	91	#ifndef SAMPLE_TIME
b624f32f	92	# define SAMPLE_TIME 3
4099536c	93	#endif
4099536c	94	#ifndef BLANKING_TIME
b624f32f	95	# define BLANKING_TIME 1
4099536c	96	#endif
4099536c	97	#ifndef IDISS_TIME
b624f32f	98	# define IDISS_TIME 1
4099536c	99	#endif
	100
	101	/* Control 3 settings */
	102	#ifndef NG_THRESH
b624f32f	103	# define NG_THRESH 2
4099536c	104	#endif
4099536c	105	#ifndef ERM_OPEN_LOOP
b624f32f	106	# define ERM_OPEN_LOOP 1
4099536c	107	#endif
4099536c	108	#ifndef SUPPLY_COMP_DIS
b624f32f	109	# define SUPPLY_COMP_DIS 0
4099536c	110	#endif
4099536c	111	#ifndef DATA_FORMAT_RTO
b624f32f	112	# define DATA_FORMAT_RTO 0
4099536c	113	#endif
4099536c	114	#ifndef LRA_DRIVE_MODE
b624f32f	115	# define LRA_DRIVE_MODE 0
4099536c	116	#endif
4099536c	117	#ifndef N_PWM_ANALOG
b624f32f	118	# define N_PWM_ANALOG 0
4099536c	119	#endif
4099536c	120	#ifndef LRA_OPEN_LOOP
b624f32f	121	# define LRA_OPEN_LOOP 0
4099536c	122	#endif
	123
	124	/* Control 4 settings */
	125	#ifndef ZC_DET_TIME
b624f32f	126	# define ZC_DET_TIME 0
4099536c	127	#endif
4099536c	128	#ifndef AUTO_CAL_TIME
b624f32f	129	# define AUTO_CAL_TIME 3
4099536c	130	#endif
	131
	132	/* register defines -------------------------------------------------------- */
b624f32f	133	#define DRV2605L_BASE_ADDRESS 0x5A /* DRV2605L Base address */
	134	#define DRV_STATUS 0x00
	135	#define DRV_MODE 0x01
	136	#define DRV_RTP_INPUT 0x02
	137	#define DRV_LIB_SELECTION 0x03
	138	#define DRV_WAVEFORM_SEQ_1 0x04
	139	#define DRV_WAVEFORM_SEQ_2 0x05
	140	#define DRV_WAVEFORM_SEQ_3 0x06
	141	#define DRV_WAVEFORM_SEQ_4 0x07
	142	#define DRV_WAVEFORM_SEQ_5 0x08
	143	#define DRV_WAVEFORM_SEQ_6 0x09
	144	#define DRV_WAVEFORM_SEQ_7 0x0A
	145	#define DRV_WAVEFORM_SEQ_8 0x0B
	146	#define DRV_GO 0x0C
	147	#define DRV_OVERDRIVE_TIME_OFFSET 0x0D
	148	#define DRV_SUSTAIN_TIME_OFFSET_P 0x0E
	149	#define DRV_SUSTAIN_TIME_OFFSET_N 0x0F
	150	#define DRV_BRAKE_TIME_OFFSET 0x10
	151	#define DRV_AUDIO_2_VIBE_CTRL 0x11
	152	#define DRV_AUDIO_2_VIBE_MIN_IN 0x12
	153	#define DRV_AUDIO_2_VIBE_MAX_IN 0x13
	154	#define DRV_AUDIO_2_VIBE_MIN_OUTDRV 0x14
	155	#define DRV_AUDIO_2_VIBE_MAX_OUTDRV 0x15
	156	#define DRV_RATED_VOLT 0x16
	157	#define DRV_OVERDRIVE_CLAMP_VOLT 0x17
	158	#define DRV_AUTO_CALIB_COMP_RESULT 0x18
	159	#define DRV_AUTO_CALIB_BEMF_RESULT 0x19
	160	#define DRV_FEEDBACK_CTRL 0x1A
	161	#define DRV_CTRL_1 0x1B
	162	#define DRV_CTRL_2 0x1C
	163	#define DRV_CTRL_3 0x1D
	164	#define DRV_CTRL_4 0x1E
	165	#define DRV_CTRL_5 0x1F
	166	#define DRV_OPEN_LOOP_PERIOD 0x20
	167	#define DRV_VBAT_VOLT_MONITOR 0x21
	168	#define DRV_LRA_RESONANCE_PERIOD 0x22
4099536c	169
b624f32f	170	void DRV_init(void);
b624f32f	171	void DRV_write(const uint8_t drv_register, const uint8_t settings);
4099536c	172	uint8_t DRV_read(const uint8_t regaddress);
911b8915 M	173	void DRV_rtp_init(void);
911b8915 M	174	void DRV_amplitude(const uint8_t amplitude);
b624f32f	175	void DRV_pulse(const uint8_t sequence);
4099536c	176
b624f32f	177	typedef enum DRV_EFFECT {
	178	clear_sequence = 0,
	179	strong_click = 1,
	180	strong_click_60 = 2,
	181	strong_click_30 = 3,
	182	sharp_click = 4,
	183	sharp_click_60 = 5,
	184	sharp_click_30 = 6,
	185	soft_bump = 7,
	186	soft_bump_60 = 8,
	187	soft_bump_30 = 9,
	188	dbl_click = 10,
	189	dbl_click_60 = 11,
	190	trp_click = 12,
	191	soft_fuzz = 13,
	192	strong_buzz = 14,
	193	alert_750ms = 15,
	194	alert_1000ms = 16,
	195	strong_click1 = 17,
	196	strong_click2_80 = 18,
	197	strong_click3_60 = 19,
	198	strong_click4_30 = 20,
	199	medium_click1 = 21,
	200	medium_click2_80 = 22,
	201	medium_click3_60 = 23,
	202	sharp_tick1 = 24,
	203	sharp_tick2_80 = 25,
	204	sharp_tick3_60 = 26,
	205	sh_dblclick_str = 27,
	206	sh_dblclick_str_80 = 28,
	207	sh_dblclick_str_60 = 29,
	208	sh_dblclick_str_30 = 30,
	209	sh_dblclick_med = 31,
	210	sh_dblclick_med_80 = 32,
	211	sh_dblclick_med_60 = 33,
	212	sh_dblsharp_tick = 34,
	213	sh_dblsharp_tick_80 = 35,
	214	sh_dblsharp_tick_60 = 36,
	215	lg_dblclick_str = 37,
	216	lg_dblclick_str_80 = 38,
	217	lg_dblclick_str_60 = 39,
	218	lg_dblclick_str_30 = 40,
	219	lg_dblclick_med = 41,
	220	lg_dblclick_med_80 = 42,
	221	lg_dblclick_med_60 = 43,
	222	lg_dblsharp_tick = 44,
	223	lg_dblsharp_tick_80 = 45,
	224	lg_dblsharp_tick_60 = 46,
	225	buzz = 47,
	226	buzz_80 = 48,
	227	buzz_60 = 49,
	228	buzz_40 = 50,
	229	buzz_20 = 51,
	230	pulsing_strong = 52,
	231	pulsing_strong_80 = 53,
	232	pulsing_medium = 54,
	233	pulsing_medium_80 = 55,
	234	pulsing_sharp = 56,
	235	pulsing_sharp_80 = 57,
	236	transition_click = 58,
	237	transition_click_80 = 59,
	238	transition_click_60 = 60,
	239	transition_click_40 = 61,
	240	transition_click_20 = 62,
241	transition_click_10 = 63,
242	transition_hum = 64,
243	transition_hum_80 = 65,
244	transition_hum_60 = 66,
245	transition_hum_40 = 67,
246	transition_hum_20 = 68,
247	transition_hum_10 = 69,
248	transition_rampdown_long_smooth1 = 70,
249	transition_rampdown_long_smooth2 = 71,
250	transition_rampdown_med_smooth1 = 72,
251	transition_rampdown_med_smooth2 = 73,
252	transition_rampdown_short_smooth1 = 74,
253	transition_rampdown_short_smooth2 = 75,
254	transition_rampdown_long_sharp1 = 76,
255	transition_rampdown_long_sharp2 = 77,
256	transition_rampdown_med_sharp1 = 78,
257	transition_rampdown_med_sharp2 = 79,
258	transition_rampdown_short_sharp1 = 80,
259	transition_rampdown_short_sharp2 = 81,
260	transition_rampup_long_smooth1 = 82,
261	transition_rampup_long_smooth2 = 83,
262	transition_rampup_med_smooth1 = 84,
263	transition_rampup_med_smooth2 = 85,
264	transition_rampup_short_smooth1 = 86,
265	transition_rampup_short_smooth2 = 87,
266	transition_rampup_long_sharp1 = 88,
267	transition_rampup_long_sharp2 = 89,
268	transition_rampup_med_sharp1 = 90,
269	transition_rampup_med_sharp2 = 91,
270	transition_rampup_short_sharp1 = 92,
271	transition_rampup_short_sharp2 = 93,
272	transition_rampdown_long_smooth1_50 = 94,
273	transition_rampdown_long_smooth2_50 = 95,
274	transition_rampdown_med_smooth1_50 = 96,
275	transition_rampdown_med_smooth2_50 = 97,
276	transition_rampdown_short_smooth1_50 = 98,
277	transition_rampdown_short_smooth2_50 = 99,
278	transition_rampdown_long_sharp1_50 = 100,
279	transition_rampdown_long_sharp2_50 = 101,
280	transition_rampdown_med_sharp1_50 = 102,
281	transition_rampdown_med_sharp2_50 = 103,
282	transition_rampdown_short_sharp1_50 = 104,
283	transition_rampdown_short_sharp2_50 = 105,
284	transition_rampup_long_smooth1_50 = 106,
285	transition_rampup_long_smooth2_50 = 107,
286	transition_rampup_med_smooth1_50 = 108,
287	transition_rampup_med_smooth2_50 = 109,
288	transition_rampup_short_smooth1_50 = 110,
289	transition_rampup_short_smooth2_50 = 111,
290	transition_rampup_long_sharp1_50 = 112,
291	transition_rampup_long_sharp2_50 = 113,
292	transition_rampup_med_sharp1_50 = 114,
293	transition_rampup_med_sharp2_50 = 115,
294	transition_rampup_short_sharp1_50 = 116,
295	transition_rampup_short_sharp2_50 = 117,
296	long_buzz_for_programmatic_stopping = 118,
297	smooth_hum1_50 = 119,
298	smooth_hum2_40 = 120,
299	smooth_hum3_30 = 121,
300	smooth_hum4_20 = 122,
301	smooth_hum5_10 = 123,
302	drv_effect_max = 124,
4099536c	303	} DRV_EFFECT;
	304
	305	/* Register bit array unions */
	306
	307	typedef union DRVREG_STATUS { /* register 0x00 */
b624f32f	308	uint8_t Byte;
	309	struct {
	310	uint8_t OC_DETECT : 1; /* set to 1 when overcurrent event is detected */
	311	uint8_t OVER_TEMP : 1; /* set to 1 when device exceeds temp threshold */
	312	uint8_t FB_STS : 1; /* set to 1 when feedback controller has timed out */
	313	/* auto-calibration routine and diagnostic result
	314	* result \| auto-calibation \| diagnostic \|
	315	* 0 \| passed \| actuator func normal \|
	316	* 1 \| failed \| actuator func fault* \|
	317	* * actuator is not present or is shorted, timing out, or giving out–of-range back-EMF */
	318	uint8_t DIAG_RESULT : 1;
	319	uint8_t : 1;
	320	uint8_t DEVICE_ID : 3; /* Device IDs 3: DRV2605 4: DRV2604 5: DRV2604L 6: DRV2605L */
	321	} Bits;
4099536c	322	} DRVREG_STATUS;
	323
	324	typedef union DRVREG_MODE { /* register 0x01 */
b624f32f	325	uint8_t Byte;
	326	struct {
	327	uint8_t MODE : 3; /* Mode setting */
	328	uint8_t : 3;
	329	uint8_t STANDBY : 1; /* 0:standby 1:ready */
	330	} Bits;
4099536c	331	} DRVREG_MODE;
	332
	333	typedef union DRVREG_WAIT {
b624f32f	334	uint8_t Byte;
	335	struct {
	336	uint8_t WAIT_MODE : 1; /* Set to 1 to interpret as wait for next 7 bits x10ms */
	337	uint8_t WAIT_TIME : 7;
	338	} Bits;
4099536c	339	} DRVREG_WAIT;
4099536c	340
b624f32f	341	typedef union DRVREG_FBR { /* register 0x1A */
	342	uint8_t Byte;
	343	struct {
	344	uint8_t BEMF_GAIN : 2;
	345	uint8_t LOOP_GAIN : 2;
	346	uint8_t BRAKE_FACTOR : 3;
	347	uint8_t ERM_LRA : 1;
	348	} Bits;
4099536c	349	} DRVREG_FBR;
4099536c	350
b624f32f	351	typedef union DRVREG_CTRL1 { /* register 0x1B */
	352	uint8_t Byte;
	353	struct {
	354	uint8_t C1_DRIVE_TIME : 5;
	355	uint8_t C1_AC_COUPLE : 1;
	356	uint8_t : 1;
	357	uint8_t C1_STARTUP_BOOST : 1;
	358	} Bits;
4099536c	359	} DRVREG_CTRL1;
4099536c	360
b624f32f	361	typedef union DRVREG_CTRL2 { /* register 0x1C */
	362	uint8_t Byte;
	363	struct {
	364	uint8_t C2_IDISS_TIME : 2;
	365	uint8_t C2_BLANKING_TIME : 2;
	366	uint8_t C2_SAMPLE_TIME : 2;
	367	uint8_t C2_BRAKE_STAB : 1;
	368	uint8_t C2_BIDIR_INPUT : 1;
	369	} Bits;
4099536c	370	} DRVREG_CTRL2;
4099536c	371
b624f32f	372	typedef union DRVREG_CTRL3 { /* register 0x1D */
	373	uint8_t Byte;
	374	struct {
	375	uint8_t C3_LRA_OPEN_LOOP : 1;
	376	uint8_t C3_N_PWM_ANALOG : 1;
	377	uint8_t C3_LRA_DRIVE_MODE : 1;
	378	uint8_t C3_DATA_FORMAT_RTO : 1;
	379	uint8_t C3_SUPPLY_COMP_DIS : 1;
	380	uint8_t C3_ERM_OPEN_LOOP : 1;
	381	uint8_t C3_NG_THRESH : 2;
	382	} Bits;
4099536c	383	} DRVREG_CTRL3;
4099536c	384
b624f32f	385	typedef union DRVREG_CTRL4 { /* register 0x1E */
	386	uint8_t Byte;
	387	struct {
	388	uint8_t C4_OTP_PROGRAM : 1;
	389	uint8_t : 1;
	390	uint8_t C4_OTP_STATUS : 1;
	391	uint8_t : 1;
	392	uint8_t C4_AUTO_CAL_TIME : 2;
	393	uint8_t C4_ZC_DET_TIME : 2;
	394	} Bits;
4099536c	395	} DRVREG_CTRL4;
4099536c	396
b624f32f	397	typedef union DRVREG_CTRL5 { /* register 0x1F */
	398	uint8_t Byte;
	399	struct {
	400	uint8_t C5_IDISS_TIME : 2;
	401	uint8_t C5_BLANKING_TIME : 2;
	402	uint8_t C5_PLAYBACK_INTERVAL : 1;
	403	uint8_t C5_LRA_AUTO_OPEN_LOOP : 1;
	404	uint8_t C5_AUTO_OL_CNT : 2;
	405	} Bits;
4099536c	406	} DRVREG_CTRL5;