X-Git-Url: https://git.hcoop.net/jackhill/guix/guix.git/blobdiff_plain/c01ef97594a8b06e884906a5efbdfacf8ba33dc3..c02398edf43c393b858d57c7b9e4839514f85acb:/gnu/packages/fpga.scm diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm index f3dc805e36..f07c7260f7 100644 --- a/gnu/packages/fpga.scm +++ b/gnu/packages/fpga.scm @@ -1,6 +1,8 @@ ;;; GNU Guix --- Functional package management for GNU ;;; Copyright © 2016 Danny Milosavljevic ;;; Copyright © 2016, 2017 Theodoros Foradis +;;; Copyright © 2018, 2019, 2020 Tobias Geerinckx-Rice +;;; Copyright © 2019 Amin Bandali ;;; ;;; This file is part of GNU Guix. ;;; @@ -42,6 +44,9 @@ #:use-module (gnu packages gperf) #:use-module (gnu packages gawk) #:use-module (gnu packages version-control) + #:use-module (gnu packages qt) + #:use-module (gnu packages boost) + #:use-module (gnu packages algebra) #:use-module (gnu packages libftdi)) (define-public abc @@ -49,15 +54,15 @@ (revision "1")) (package (name "abc") - (version (string-append "0.0-" revision "-" (string-take commit 9))) + (version (git-version "0.0" revision commit)) (source (origin (method url-fetch) (uri (string-append "https://bitbucket.org/alanmi/abc/get/" commit ".zip")) (file-name (string-append name "-" version "-checkout.zip")) (sha256 - (base32 - "1syygi1x40rdryih3galr4q8yg1w5bvdzl75hd27v1xq0l5bz3d0")))) + (base32 + "1syygi1x40rdryih3galr4q8yg1w5bvdzl75hd27v1xq0l5bz3d0")))) (build-system gnu-build-system) (native-inputs `(("unzip" ,unzip))) @@ -73,7 +78,7 @@ (let* ((out (assoc-ref outputs "out")) (out-bin (string-append out "/bin"))) (install-file "abc" out-bin))))))) - (home-page "http://people.eecs.berkeley.edu/~alanmi/abc/") + (home-page "https://people.eecs.berkeley.edu/~alanmi/abc/") (synopsis "Sequential logic synthesis and formal verification") (description "ABC is a program for sequential logic synthesis and formal verification.") @@ -83,20 +88,20 @@ formal verification.") (define-public iverilog (package (name "iverilog") - (version "10.1.1") + (version "10.3") (source (origin (method url-fetch) (uri (string-append "ftp://ftp.icarus.com/pub/eda/verilog/v10/" "verilog-" version ".tar.gz")) (sha256 - (base32 - "1nnassxvq30rnn0r2p85rkb2zwxk97p109y13x3vr365wzgpbapx")))) + (base32 + "1vv88ckvfwq7mrysyjnilsrcrzm9d173kp9w5ivwh6rdw7klbgc6")))) (build-system gnu-build-system) (native-inputs `(("flex" ,flex) ("bison" ,bison) - ("ghostscript" ,ghostscript))) ; ps2pdf + ("ghostscript" ,ghostscript))) ; ps2pdf (home-page "http://iverilog.icarus.com/") (synopsis "FPGA Verilog simulation and synthesis tool") (description "Icarus Verilog is a Verilog simulation and synthesis tool. @@ -104,7 +109,7 @@ It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. -This intermediate form is executed by the ``vvp'' command. +This intermediate form is executed by @command{vvp}. For synthesis, the compiler generates netlists in the desired format.") ;; GPL2 only because of: ;; - ./driver/iverilog.man.in @@ -118,20 +123,23 @@ For synthesis, the compiler generates netlists in the desired format.") (define-public yosys (package (name "yosys") - (version "0.7") + (version "0.9") (source (origin - (method url-fetch) - (uri - (string-append "https://github.com/cliffordwolf/yosys/archive/" - name "-" version ".tar.gz")) + (method git-fetch) + (uri (git-reference + (url "https://github.com/cliffordwolf/yosys") + (commit (string-append "yosys-" version)) + (recursive? #t))) ; for the ‘iverilog’ submodule (sha256 (base32 - "0vkfdn4phvkjqlnpqlr6q5f97bgjc3312vj5jf0vf85zqv88dy9x")) - (file-name (string-append name "-" version "-checkout.tar.gz")) + "0lb9r055h8y1vj2z8gm4ip0v06j5mk7f9zx9gi67kkqb7g4rhjli")) + (file-name (git-file-name name version)) (modules '((guix build utils))) (snippet - '(substitute* "Makefile" - (("ABCREV = .*") "ABCREV = default\n"))))) + '(begin + (substitute* "Makefile" + (("ABCREV = .*") "ABCREV = default\n")) + #t)))) (build-system gnu-build-system) (arguments `(#:test-target "test" @@ -149,7 +157,7 @@ For synthesis, the compiler generates netlists in the desired format.") #t)) (replace 'configure (lambda* (#:key inputs (make-flags '()) #:allow-other-keys) - (zero? (apply system* "make" "config-gcc" make-flags)))) + (apply invoke "make" "config-gcc" make-flags))) (add-after 'configure 'prepare-abc (lambda* (#:key inputs #:allow-other-keys) (let* ((sourceabc (assoc-ref inputs "abc")) @@ -160,7 +168,7 @@ For synthesis, the compiler generates netlists in the desired format.") (lambda (port) (format port ".PHONY: all\nall:\n\tcp -f abc abc-default\n"))) (copy-file source "abc/abc") - (zero? (system* "chmod" "+w" "abc/abc"))))) + (invoke "chmod" "+w" "abc/abc")))) (add-before 'check 'fix-iverilog-references (lambda* (#:key inputs native-inputs #:allow-other-keys) (let* ((xinputs (or native-inputs inputs)) @@ -207,20 +215,20 @@ For synthesis, the compiler generates netlists in the desired format.") (license license:isc))) (define-public icestorm - (let ((commit "12b2295c9087d94b75e374bb205ae4d76cf17e2f") - (revision "1")) + (let ((commit "0ec00d892a91cc68e45479b46161f649caea2933") + (revision "3")) (package (name "icestorm") - (version (string-append "0.0-" revision "-" (string-take commit 9))) + (version (git-version "0.0" revision commit)) (source (origin (method git-fetch) (uri (git-reference - (url "https://github.com/cliffordwolf/icestorm.git") + (url "https://github.com/cliffordwolf/icestorm") (commit commit))) - (file-name (string-append name "-" version "-checkout")) + (file-name (git-file-name name version)) (sha256 (base32 - "1mmzlqvap6w8n4qzv3idvy51arkgn03692ssplwncy3akjrbsd2b")))) + "1qlh99fafb7xga702k64fmc9m700nsddrfgcq4x8qn8fplsb64f1")))) (build-system gnu-build-system) (arguments `(#:tests? #f ; no unit tests that don't need an FPGA exist. @@ -251,34 +259,68 @@ For synthesis, the compiler generates netlists in the desired format.") Includes the actual FTDI connector.") (license license:isc)))) +(define-public nextpnr-ice40 + (let [(commit "fbe486df459909065d6852a7495a212dfd2accef") + (revision "1")] + (package + (name "nextpnr-ice40") + (version (git-version "0.0.0" revision commit)) + (source + (origin + (method git-fetch) + (uri (git-reference + (url "git://github.com/YosysHQ/nextpnr") + (commit commit))) + (file-name (git-file-name name version)) + (sha256 + (base32 + "1fmxsywgs45g88ra7ips5s2niiiwrkyxdcy742ws18dfk2y4vi9c")))) + (inputs + `(("boost" ,boost) + ("eigen" ,eigen) + ("icestorm" ,icestorm) + ("python" ,python) + ("qtbase" ,qtbase) + ("yosys" ,yosys))) + (build-system cmake-build-system) + (arguments + `(#:configure-flags `("-DARCH=ice40" + ,(string-append "-DICEBOX_ROOT=" + (assoc-ref %build-inputs "icestorm") + "/share/icebox")) + #:tests? #f)) + (synopsis "Place-and-Route tool for FPGAs") + (description "Nextpnr aims to be a vendor neutral, timing driven, +FOSS FPGA place and route tool.") + (home-page "https://github.com/YosysHQ/nextpnr") + (license license:expat)))) + (define-public arachne-pnr - (let ((commit "52e69ed207342710080d85c7c639480e74a021d7") - (revision "1")) + (let ((commit "840bdfdeb38809f9f6af4d89dd7b22959b176fdd") + (revision "2")) (package (name "arachne-pnr") (version (string-append "0.0-" revision "-" (string-take commit 9))) (source (origin (method git-fetch) (uri (git-reference - (url "https://github.com/cseed/arachne-pnr.git") + (url "https://github.com/YosysHQ/arachne-pnr") (commit commit))) - (file-name (string-append name "-" version "-checkout")) + (file-name (git-file-name name version)) (sha256 (base32 - "15bdw5yxj76lxrwksp6liwmr6l1x77isf4bs50ys9rsnmiwh8c3w")))) + "1dqvjvgvsridybishv4pnigw9gypxh7r7nrqp9z9qq92v7c5rxzl")))) (build-system gnu-build-system) (arguments `(#:test-target "test" + #:make-flags + (list (string-append "DESTDIR=" (assoc-ref %outputs "out")) + (string-append "ICEBOX=" (string-append + (assoc-ref %build-inputs "icestorm") + "/share/icebox"))) #:phases (modify-phases %standard-phases (replace 'configure (lambda* (#:key outputs inputs #:allow-other-keys) - (substitute* '("Makefile") - (("DESTDIR = .*") (string-append "DESTDIR = " - (assoc-ref outputs "out") - "\n")) - (("ICEBOX = .*") (string-append "ICEBOX = " - (assoc-ref inputs "icestorm") - "/share/icebox\n"))) (substitute* '("./tests/fsm/generate.py" "./tests/combinatorial/generate.py") (("#!/usr/bin/python") "#!/usr/bin/python2")) @@ -290,7 +332,7 @@ Includes the actual FTDI connector.") ("yosys" ,yosys) ; for tests ("perl" ,perl) ; for shasum ("python-2" ,python-2))) ; for tests - (home-page "https://github.com/cseed/arachne-pnr") + (home-page "https://github.com/YosysHQ/arachne-pnr") (synopsis "Place-and-Route tool for FPGAs") (description "Arachne-PNR is a Place-and-Route Tool For FPGAs.") (license license:gpl2)))) @@ -298,14 +340,17 @@ Includes the actual FTDI connector.") (define-public gtkwave (package (name "gtkwave") - (version "3.3.76") - (source (origin - (method url-fetch) - (uri (string-append "http://gtkwave.sourceforge.net/" - name "-" version ".tar.gz")) - (sha256 - (base32 - "1vlvavszb1jwwiixiagld88agjrjg0ix8qa4xnxj4ziw0q87jbmn")))) + (version "3.3.106") + (source + (origin + (method url-fetch) + (uri (list (string-append "mirror://sourceforge/gtkwave/" + "gtkwave-" version "/" + "gtkwave-" version ".tar.gz") + (string-append "http://gtkwave.sourceforge.net/" + "gtkwave-" version ".tar.gz"))) + (sha256 + (base32 "1pyij6dlmapjyzrmn255fkf8gyhz8i4vaipd75a68i2bnq021nn8")))) (build-system gnu-build-system) (native-inputs `(("gperf" ,gperf) @@ -325,7 +370,7 @@ Includes the actual FTDI connector.") (synopsis "Waveform viewer for FPGA simulator trace files") (description "This package is a waveform viewer for FPGA -simulator trace files (FST).") +simulator trace files (@dfn{FST}).") (home-page "http://gtkwave.sourceforge.net/") - ;; Exception against free government use in tcl_np.c and tcl_np.h + ;; Exception against free government use in tcl_np.c and tcl_np.h. (license (list license:gpl2+ license:expat license:tcl/tk))))