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7f918cf1 CE |
1 | (* Copyright (C) 1999-2007 Henry Cejtin, Matthew Fluet, Suresh |
2 | * Jagannathan, and Stephen Weeks. | |
3 | * Copyright (C) 1997-2000 NEC Research Institute. | |
4 | * | |
5 | * MLton is released under a BSD-style license. | |
6 | * See the file MLton-LICENSE for details. | |
7 | *) | |
8 | ||
9 | signature AMD64_MLTON_STRUCTS = | |
10 | sig | |
11 | structure amd64MLtonBasic : AMD64_MLTON_BASIC | |
12 | structure amd64Liveness : AMD64_LIVENESS | |
13 | sharing amd64MLtonBasic.amd64 = amd64Liveness.amd64 | |
14 | end | |
15 | ||
16 | signature AMD64_MLTON = | |
17 | sig | |
18 | include AMD64_MLTON_STRUCTS | |
19 | include AMD64_MLTON_BASIC | |
20 | sharing amd64 = amd64MLtonBasic.amd64 | |
21 | sharing amd64 = amd64Liveness.amd64 | |
22 | sharing amd64.Label = Machine.Label | |
23 | sharing Machine = amd64MLtonBasic.Machine | |
24 | ||
25 | type transInfo = {addData : amd64.Assembly.t list -> unit, | |
26 | frameInfoToAMD64: (amd64MLtonBasic.Machine.FrameInfo.t | |
27 | -> amd64.FrameInfo.t), | |
28 | live: amd64.Label.t -> amd64.Operand.t list, | |
29 | liveInfo: amd64Liveness.LiveInfo.t} | |
30 | ||
31 | (* arith, c call, and primitive assembly sequences. *) | |
32 | val arith: {prim: RepType.t Machine.Prim.t, | |
33 | args: (amd64.Operand.t * amd64.Size.t) vector, | |
34 | dsts: (amd64.Operand.t * amd64.Size.t) vector, | |
35 | overflow: amd64.Label.t, | |
36 | success: amd64.Label.t, | |
37 | transInfo : transInfo} -> amd64.Block.t' AppendList.t | |
38 | val ccall: {args: (amd64.Operand.t * amd64.Size.t) vector, | |
39 | frameInfo: amd64.FrameInfo.t option, | |
40 | func: RepType.t Machine.CFunction.t, | |
41 | return: amd64.Label.t option, | |
42 | transInfo: transInfo} -> amd64.Block.t' AppendList.t | |
43 | val creturn: {dsts: (amd64.Operand.t * amd64.Size.t) vector, | |
44 | frameInfo: amd64.FrameInfo.t option, | |
45 | func: RepType.t Machine.CFunction.t, | |
46 | label: amd64.Label.t, | |
47 | transInfo: transInfo} -> amd64.Block.t' AppendList.t | |
48 | val implementsPrim: RepType.t Machine.Prim.t -> bool | |
49 | val prim: {prim: RepType.t Machine.Prim.t, | |
50 | args: (amd64.Operand.t * amd64.Size.t) vector, | |
51 | dsts: (amd64.Operand.t * amd64.Size.t) vector, | |
52 | transInfo: transInfo} -> amd64.Block.t' AppendList.t | |
53 | end |