Debugger sources code clean-up
[clinton/Virtual-Jaguar-Rx.git] / src / debugger / HWLABELManager.cpp
1 //
2 // ELFManager.cpp: HW Label manager
3 //
4 // by Jean-Paul Mari
5 //
6 // JPM = Jean-Paul Mari <djipi.mari@gmail.com>
7 //
8 // WHO WHEN WHAT
9 // --- ---------- ------------------------------------------------------------
10 // JPM 02/08/2017 Created this file
11 // JPM 02/08/2017 HW Label support
12 //
13
14 #include <stdlib.h>
15 #include <string.h>
16 #include "libelf/libelf.h"
17 #include "libelf/gelf.h"
18 #include "log.h"
19 #include "ELFManager.h"
20
21
22 typedef enum {
23 HWLABEL_NO_SIZE = 0,
24 HWLABEL_8BITS = 1,
25 HWLABEL_16BITS = 2,
26 HWLABEL_32BITS = 4,
27 HWLABEL_64BITS = 8
28 }HWLABELSIZE;
29
30 typedef enum {
31 HWLABEL_NO_ACCESS = 0,
32 HWLABEL_R = 0x1,
33 HWLABEL_W = 0x2,
34 HWLABEL_O = 0x4
35 }HWLABELACCESS;
36
37 typedef struct {
38 size_t HWLABELAdr;
39 const char *HWLABELSymbolName;
40 const char *HWLABELFulllName;
41 size_t HWLABELSize;
42 size_t HWLABELAccess;
43 }HWLABELTab;
44
45 #define NBHWLABELS (sizeof(HWLABELTabSectionType) / sizeof(HWLABELTab))
46
47
48 // Memory map list based on the scans from the Version 2.4 - June 7, 1995
49 HWLABELTab HWLABELTabSectionType[] = {
50 // Internal Memory Map
51 { 0xF00000, "MEMCON1", "Memory Configuration Register One", HWLABEL_16BITS, (HWLABEL_R | HWLABEL_W) },
52 { 0xF00002, "MEMCON2", "Memory Configuration Register Two", HWLABEL_16BITS, (HWLABEL_R | HWLABEL_W) },
53 { 0xF00004, "HC", "Horizontal Count", HWLABEL_16BITS, (HWLABEL_R | HWLABEL_W) },
54 { 0xF00006, "VC", "Vertical Count", HWLABEL_16BITS, (HWLABEL_R | HWLABEL_W) },
55 { 0xF00008, "LPH", "Horizontal Light-pen", HWLABEL_16BITS, (HWLABEL_R | HWLABEL_O) },
56 { 0xF0000A, "LPV", "Vertical Light-pen", HWLABEL_16BITS, (HWLABEL_R | HWLABEL_O) },
57 { 0xF00010, "OB[0]", "Object Code", HWLABEL_16BITS, (HWLABEL_R | HWLABEL_O) },
58 { 0xF00012, "OB[1]", "Object Code", HWLABEL_16BITS, (HWLABEL_R | HWLABEL_O) },
59 { 0xF00014, "OB[2]", "Object Code", HWLABEL_16BITS, (HWLABEL_R | HWLABEL_O) },
60 { 0xF00016, "OB[3]", "Object Code", HWLABEL_16BITS, (HWLABEL_R | HWLABEL_O) },
61 { 0xF00020, "OLP", "Object List Pointer", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },
62 { 0xF00026, "OBF", "Object Processor flag", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },
63 { 0xF00028, "VMODE", "Video Mode", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },
64 { 0xF0002A, "BORD1", "Border Colour (Red & Green)", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },
65 { 0xF0002C, "BORD2", "Border Colour (Blue)", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },
66 { 0xF0002E, "HP", "Horizontal Period", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },
67 { 0xF00030, "HBB", "Horizontal Blanking Begin", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },
68 { 0xF00032, "HBE", "Horizontal Blanking End", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },
69 { 0xF00034, "HS", "Horizontal Sync", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },
70 { 0xF00036, "HVS", "Horizontal Vertical Sync", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },
71 { 0xF00038, "HDB1", "Horizontal Display Begin 1", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },
72 { 0xF0003A, "HDB2", "Horizontal Display Begin 2", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },
73 { 0xF0003C, "HDE", "Horizontal Display End", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },
74 { 0xF0003E, "VP", "Vertical Period", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },
75 { 0xF00040, "VBB", "Vertical Blanking Begin", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },
76 { 0xF00042, "VBE", "Vertical Blanking End", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },
77 { 0xF00044, "VS", "Vertical Sync", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },
78 { 0xF00046, "VDB", "Vertical Display Begin", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },
79 { 0xF00048, "VDE", "Vertical Display End", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },
80 { 0xF0004A, "VEB", "Vertical Equalization Begin", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },
81 { 0xF0004C, "VEE", "Vertical Equalization End", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },
82 { 0xF0004E, "VI", "Vertical Interrupt", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },
83 { 0xF00050, "PIT[0]", "Programmable Interrupt Timer", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },
84 { 0xF00052, "PIT[1]", "Programmable Interrupt Timer", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },
85 { 0xF00054, "HEQ", "Horizontal equalization end", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },
86 { 0xF00058, "BG", "Background Colour", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },
87 { 0xF000E0, "INT1", "CPU Interrupt Control Register", HWLABEL_16BITS, (HWLABEL_R | HWLABEL_W) },
88 { 0xF000E2, "INT2", "CPU Interrupt resume register", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },
89 { 0xF00400, "CLUT", "Colour Look-Up Table", HWLABEL_16BITS, (HWLABEL_R | HWLABEL_W) },
90 { 0xF00800, "LBUF", "Line Buffer A", HWLABEL_32BITS, (HWLABEL_R | HWLABEL_W) },
91 { 0xF01000, "LBUF", "Line Buffer B", HWLABEL_32BITS, (HWLABEL_R | HWLABEL_W) },
92 { 0xF01800, "LBUF", "Line Buffer selected for writing", HWLABEL_32BITS, (HWLABEL_R | HWLABEL_W) },
93 // Internal registers of the Graphics processor
94 { 0xF02100, "G_FLAGS", "GPU Flags Register", HWLABEL_32BITS, (HWLABEL_R | HWLABEL_W) },
95 { 0xF02104, "G_MTXC", "Matrix Control Register", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },
96 { 0xF02108, "G_MTXA", "Matrix Address Register", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },
97 { 0xF0210C, "G_END", "Data Organisation Register", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },
98 { 0xF02110, "G_PC", "GPU Program Counter", HWLABEL_32BITS, (HWLABEL_R | HWLABEL_W) },
99 { 0xF02114, "G_CTRL", "GPU Control/Status Register", HWLABEL_32BITS, (HWLABEL_R | HWLABEL_W) },
100 { 0xF02118, "G_HIDATA", "High Data Register", HWLABEL_32BITS, (HWLABEL_R | HWLABEL_W) },
101 { 0xF0211C, "G_REMAIN", "Divide unit remainder", HWLABEL_32BITS, (HWLABEL_R | HWLABEL_O) },
102 { 0xF0211C, "G_DIVCTRL", "Divide unit Control", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },
103 // List of all the externally accessible locations within the Blitter.
104 { 0xF02200, "A1_BASE", "A1 Base Register", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },
105 { 0xF02204, "A1_FLAGS", "A1 Flags Register", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },
106 { 0xF02208, "A1_CLIP", "A1 Clipping Size", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },
107 { 0xF0220C, "A1_PIXEL", "A1 Pixel Pointer", HWLABEL_32BITS, (HWLABEL_R | HWLABEL_W) },
108 { 0xF02210, "A1_STEP", "A1 Step Value", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },
109 { 0xF02214, "A1_FSTEP", "A1 Step Fraction Value", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },
110 { 0xF02218, "A1_FPIXEL", "A1 Pixel Pointer Fraction", HWLABEL_32BITS, (HWLABEL_R | HWLABEL_W) },
111 { 0xF0221C, "A1_INC", "A1 Increment", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },
112 { 0xF02220, "A1_FINC", "A1 Increment Fraction", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },
113 { 0xF02224, "A2_BASE", "A2 Base Register", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },
114 { 0xF02228, "A2_FLAGS", "A2 Flags Register", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },
115 { 0xF0222C, "A2_MASK", "A2 Window Mask", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },
116 { 0xF02230, "A2_PIXEL", "A2 Pixel Pointer", HWLABEL_32BITS, (HWLABEL_R | HWLABEL_W) },
117 { 0xF02234, "A2_STEP", "A2 Step Value", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },
118 { 0xF02238, "B_CMD", "Command Register", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },
119 { 0xF02238, "B_CMD", "Status Register", HWLABEL_32BITS, (HWLABEL_R | HWLABEL_O) },
120 { 0xF0223C, "B_COUNT", "Counters Register", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },
121 { 0xF02240, "B_SRCD", "Source Data Register", HWLABEL_64BITS, (HWLABEL_W | HWLABEL_O) },
122 { 0xF02248, "B_DSTD", "Destination Data Register", HWLABEL_64BITS, (HWLABEL_W | HWLABEL_O) },
123 { 0xF02250, "B_DSTZ", "Destination Z Register", HWLABEL_64BITS, (HWLABEL_W | HWLABEL_O) },
124 { 0xF02258, "B_SRCZ1", "Source Z Register 1", HWLABEL_64BITS, (HWLABEL_W | HWLABEL_O) },
125 { 0xF02260, "B_SRCZ2", "Source Z Register 2", HWLABEL_64BITS, (HWLABEL_W | HWLABEL_O) },
126 { 0xF02268, "B_PATD", "Pattern Data Register", HWLABEL_64BITS, (HWLABEL_W | HWLABEL_O) },
127 { 0xF02270, "B_IINC", "Intensity Increment", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },
128 { 0xF02274, "B_ZINC", "Z Increment", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },
129 { 0xF02278, "B_STOP", "Collision control", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },
130 { 0xF0227C, "B_I3", "Intensity 3", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },
131 { 0xF02280, "B_I2", "Intensity 2", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },
132 { 0xF02284, "B_I1", "Intensity 1", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },
133 { 0xF02288, "B_I0", "Intensity 0", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },
134 { 0xF0228C, "B_Z3", "Z 3", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },
135 { 0xF02290, "B_Z2", "Z 2", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },
136 { 0xF02294, "B_Z1", "Z 1", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },
137 { 0xF02298, "B_Z0", "Z 0", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },
138 // GPU Ram base
139 //{ 0xF03000, "GPU_RAMBASE", "Local RAM base", HWLABEL_8BITS, (HWLABEL_R | HWLABEL_W) },
140 // Frequency dividers
141 { 0xF10010, "CLK1", "Processor clock divider", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },
142 { 0xF10012, "CLK2", "Video clock divider", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },
143 { 0xF10014, "CLK3", "Chroma clock divider", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },
144 // Programmable Timers
145 { 0xF10000, "JPIT1", "Timer 1 Pre-scaler", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },
146 { 0xF10004, "JPIT3", "Timer 2 Pre-scaler", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },
147 { 0xF10002, "JPIT2", "Timer 1 Divider", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },
148 { 0xF10006, "JPIT4", "Timer 2 Divider", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },
149 //{ 0xF10036, "JPIT1", "Timer 1 Pre-scaler", HWLABEL_16BITS, (HWLABEL_R | HWLABEL_O) },
150 //{ 0xF10038, "JPIT2", "Timer 1 Divider", HWLABEL_16BITS, (HWLABEL_R | HWLABEL_O) },
151 //{ 0xF1003A, "JPIT3", "Timer 2 Pre-scaler", HWLABEL_16BITS, (HWLABEL_R | HWLABEL_O) },
152 //{ 0xF1003C, "JPIT4", "Timer 2 Divider", HWLABEL_16BITS, (HWLABEL_R | HWLABEL_O) },
153 // Interrupts
154 { 0xF10020, "JINTCTRL", "Interrupt Control Register", HWLABEL_16BITS, (HWLABEL_R | HWLABEL_W) },
155 // JERRY Pulse Width Modulation DACs
156 //{ 0xF1A140, "DAC1", "Left DAC", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },
157 //{ 0xF1A144, "DAC2", "Right DAC", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },
158 // Synchronous Serial Interface
159 { 0xF1A150, "SCLK", "Serial Clock Frequency", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },
160 { 0xF1A154, "SMODE", "Serial Mode", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },
161 { 0xF1A148, "R_DAC", "Right transmit data (to DACs)", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },
162 { 0xF1A14C, "L_DAC", "Left transmit data (to DACs)", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },
163 { 0xF1A148, "LTXD", "Left transmit data (to I2S)", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },
164 { 0xF1A14C, "RTXD", "Right transmit data (to I2S)", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },
165 { 0xF1A148, "LRXD", "Left receive data (to I2S)", HWLABEL_32BITS, (HWLABEL_R | HWLABEL_O) },
166 { 0xF1A14C, "RRXD", "Right receive data (to I2S)", HWLABEL_32BITS, (HWLABEL_R | HWLABEL_O) },
167 { 0xF1A150, "SSTAT", "Serial Status", HWLABEL_32BITS, (HWLABEL_R | HWLABEL_O) },
168 // Asynchronous Serial Interface (ComLynx and Midi)
169 { 0xF10034, "ASICLK", "Asynchronous Serial Interface Clock", HWLABEL_16BITS, (HWLABEL_R | HWLABEL_W) },
170 { 0xF10032, "ASICTRL", "Asynchronous Serial Control", HWLABEL_16BITS, (HWLABEL_W | HWLABEL_O) },
171 { 0xF10032, "ASISTAT", "Asynchronous Serial Status", HWLABEL_16BITS, (HWLABEL_R | HWLABEL_O) },
172 { 0xF10030, "ASIDATA", "Asynchronous Serial Data", HWLABEL_16BITS, (HWLABEL_R | HWLABEL_W) },
173 // Joystick Interface
174 { 0xF14000, "JOYSTICK", "Joystick register", HWLABEL_16BITS, (HWLABEL_R | HWLABEL_W) },
175 { 0xF14002, "JOYBUTS", "Button register", HWLABEL_16BITS, (HWLABEL_R | HWLABEL_W) },
176 // Internal Registers
177 { 0xF1A100, "D_FLAGS", "DSP Flags Register", HWLABEL_32BITS, (HWLABEL_R | HWLABEL_W) },
178 { 0xF1A104, "D_MTXC", "DSP Matrix Control Register", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },
179 { 0xF1A108, "D_MTXA", "DSP Matrix Address Register", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },
180 { 0xF1A10C, "D_END", "DSP Data Organisation Register", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },
181 { 0xF1A110, "D_PC", "DSP Program Counter", HWLABEL_32BITS, (HWLABEL_R | HWLABEL_W) },
182 { 0xF1A114, "D_CTRL", "DSP Control/Status Register", HWLABEL_32BITS, (HWLABEL_R | HWLABEL_W) },
183 { 0xF1A118, "D_MOD", "Modulo instruction mask", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },
184 { 0xF1A11C, "D_REMAIN", "Divide unit remainder", HWLABEL_32BITS, (HWLABEL_R | HWLABEL_W) },
185 { 0xF1A11C, "D_DIVCTRL", "Divide unit Control", HWLABEL_32BITS, (HWLABEL_W | HWLABEL_O) },
186 { 0xF1A120, "D_MACHI", "Multiply & Acccumulate High Bits", HWLABEL_32BITS, (HWLABEL_R | HWLABEL_O) },
187 // End of the Memory map list
188 // { (size_t)-1, NULL, NULL, HWLABEL_NO_SIZE, HWLABEL_NO_ACCESS }
189 };
190
191
192 // Get Symbol name from his address
193 char *HWLABELManager_GetSymbolnameFromAdr(size_t Adr)
194 {
195 size_t i;
196
197 if ((Adr >= 0xF00000) && (Adr < 0xF1A124))
198 {
199 for (i = 0; i < NBHWLABELS; i++)
200 {
201 if ((HWLABELTabSectionType[i].HWLABELAdr == Adr))
202 {
203 return (char *)HWLABELTabSectionType[i].HWLABELSymbolName;
204 }
205 }
206 }
207
208 return NULL;
209
210 //while ((HWLABELTabSectionType[i].HWLABELAdr != Adr) && (HWLABELTabSectionType[i++].HWLABELAdr != (size_t)-1));
211 //return (char *)HWLABELTabSectionType[i].HWLABELSymbolName;
212 }
213