-/*Copyright (C) 2011 by Sagar G V, Thejasvi M V\r
-\r
-Permission is hereby granted, free of charge, to any person obtaining a copy\r
-of this software and associated documentation files (the "Software"), to deal\r
-in the Software without restriction, including without limitation the rights\r
-to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\r
-copies of the Software, and to permit persons to whom the Software is\r
-furnished to do so, subject to the following conditions:\r
-\r
-The above copyright notice and this permission notice shall be included in\r
-all copies or substantial portions of the Software.\r
-\r
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\r
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\r
-THE SOFTWARE.\r
-*/\r
-/* Updates: \r
- Arthur Wolf & Adam Green in 2011 - Updated to work with mbed.\r
-*/\r
-\r
-OUTPUT_FORMAT ("elf32-littlearm")\r
-ENTRY(Reset_Handler)\r
-SEARCH_DIR(.)\r
-\r
-MEMORY\r
-{\r
- /* LPC1768 : 512k ROM + 64k SRAM */\r
- /*------------------------------ */\r
-\r
- /* On-chip ROM is a readable (r), executable region (x) */\r
- /* On-chip SRAM is a readable (r), writable (w) and */\r
- /* executable region (x) */\r
-\r
- /* Main ROM region - 512k for LPC1768 */\r
- IROM (rx) : ORIGIN = 0x00000000, LENGTH = 512k\r
-\r
- /* local static RAM - 32k for LPC1768 */\r
- IRAM0 (rwx) : ORIGIN = 0x10000000, LENGTH = 32k\r
-\r
- /* AHB SRAM - 16k + 16k for LPC1768 */\r
- IRAM1 (rwx) : ORIGIN = 0x2007C000, LENGTH = 16k\r
- IRAM2 (rwx) : ORIGIN = 0x20080000, LENGTH = 16k\r
-}\r
-\r
-/* SECTION command : Define mapping of input sections */\r
-/* into output sections. */\r
-\r
-SECTIONS\r
-{\r
- /******************************************/\r
- /* code section */\r
-\r
- /* "normal" code */\r
-\r
- .text :\r
- {\r
- KEEP(*(RESET))\r
- *(.mbed_init)\r
- *(i.SystemInit)\r
- . = 0x000002FC;\r
- KEEP(*(.crp))\r
- . = 0x00000300;\r
- *(.text .text.*)\r
- *(.gnu.linkonce.t.*)\r
- *(.glue_7)\r
- *(.glue_7t)\r
- *(.gcc_except_table)\r
- *(.rodata .rodata*)\r
- *(.gnu.linkonce.r.*)\r
- . = ALIGN(4);\r
- KEEP(*(.init))\r
-\r
- . = ALIGN(4);\r
- __preinit_array_start = .;\r
- KEEP (*(.preinit_array))\r
- __preinit_array_end = .;\r
-\r
- . = ALIGN(4);\r
- __init_array_start = .;\r
- KEEP (*(SORT(.init_array.*)))\r
- KEEP (*(.init_array))\r
- __init_array_end = .;\r
-\r
- . = ALIGN(0x4);\r
- KEEP (*crtbegin.o(.ctors))\r
- KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\r
- KEEP (*(SORT(.ctors.*)))\r
- KEEP (*crtend.o(.ctors))\r
-\r
- . = ALIGN(4);\r
- KEEP(*(.fini))\r
-\r
- . = ALIGN(4);\r
- __fini_array_start = .;\r
- KEEP (*(.fini_array))\r
- KEEP (*(SORT(.fini_array.*)))\r
- __fini_array_end = .;\r
-\r
-\r
- . = ALIGN(0x4);\r
- KEEP (*crtbegin.o(.dtors))\r
- KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\r
- KEEP (*(SORT(.dtors.*)))\r
- KEEP (*crtend.o(.dtors))\r
-\r
- /* End Of .text section */\r
- _etext = .;\r
- _sifastcode = .;\r
- } >IROM\r
-\r
-\r
- __exidx_start = .;\r
- .ARM.exidx :\r
- {\r
- *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r
- } >IROM\r
- __exidx_end = .;\r
-\r
- /******************************************/\r
- /* data section */\r
- .data :\r
- {\r
- _sidata = LOADADDR (.data);\r
- . = ALIGN(4);\r
- _sdata = .;\r
- Image$$RW_IRAM1$$Base = .;\r
-\r
- *(.ARM.__AT_0x10000000)\r
- *(vtable vtable.*)\r
- *(.data .data.*)\r
- *(.gnu.linkonce.d*)\r
-\r
- . = ALIGN(4);\r
- _edata = . ;\r
- } >IRAM0 AT>IROM\r
-\r
- /******************************************/\r
- /* For no-init variables section */\r
- .bss (NOLOAD) :\r
- {\r
- . = ALIGN(4);\r
- _sbss = . ;\r
-\r
- *(.bss .bss.*)\r
- *(.gnu.linkonce.b*)\r
- *(COMMON)\r
-\r
- . = ALIGN(4);\r
- _ebss = . ;\r
- Image$$RW_IRAM1$$ZI$$Limit = . ;\r
- } >IRAM0\r
-\r
- /**************************************************/\r
- /* fastcode - copied at startup & executed in RAM */\r
-\r
- .fastcode :\r
- {\r
- _sifastcode = LOADADDR (.fastcode);\r
- . = ALIGN (4);\r
- _sfastcode = . ;\r
-\r
- *(.glue_7t) *(.glue_7)\r
- *(.fastcode)\r
- \r
- /* add other modules here ... */\r
-\r
- . = ALIGN (4);\r
- _efastcode = . ;\r
- } >IRAM0 AT>IROM\r
-\r
- /******************************************/\r
- /* For stack section */\r
- .stackarea (NOLOAD) :\r
- {\r
- . = ALIGN(8);\r
- _sstack = .;\r
-\r
- *(.stackarea .stackarea.*)\r
-\r
- . = ALIGN(8);\r
- _estack = .;\r
-\r
- . = ALIGN(4);\r
- _end = . ;\r
- PROVIDE (end = .);\r
- } > IRAM0\r
- _stack = ORIGIN(IRAM0) + LENGTH(IRAM0);\r
-\r
- /******************************************/\r
- /* Code can explicitly ask for data to be \r
- placed in these higher RAM banks where\r
- they will be left uninitialized. */\r
- .AHBSRAM0 (NOLOAD):\r
- {\r
- Image$$RW_IRAM2$$Base = . ;\r
- *(AHBSRAM0)\r
- Image$$RW_IRAM2$$ZI$$Limit = .;\r
- } > IRAM1\r
-\r
- .AHBSRAM1 (NOLOAD):\r
- {\r
- Image$$RW_IRAM3$$Base = . ;\r
- *(AHBSRAM1)\r
- Image$$RW_IRAM3$$ZI$$Limit = .;\r
- } > IRAM2\r
-\r
-\r
- /******************************************/\r
- /* Stabs debugging sections. */\r
- .stab 0 : { *(.stab) }\r
- .stabstr 0 : { *(.stabstr) }\r
- .stab.excl 0 : { *(.stab.excl) }\r
- .stab.exclstr 0 : { *(.stab.exclstr) }\r
- .stab.index 0 : { *(.stab.index) }\r
- .stab.indexstr 0 : { *(.stab.indexstr) }\r
- /* .comment 0 : { *(.comment) } */\r
- /* DWARF debug sections.\r
- Symbols in the DWARF debugging sections are relative to the beginning\r
- of the section so we begin them at 0. */\r
- /* DWARF 1 */\r
- .debug 0 : { *(.debug) }\r
- .line 0 : { *(.line) }\r
- /* GNU DWARF 1 extensions */\r
- .debug_srcinfo 0 : { *(.debug_srcinfo) }\r
- .debug_sfnames 0 : { *(.debug_sfnames) }\r
- /* DWARF 1.1 and DWARF 2 */\r
- .debug_aranges 0 : { *(.debug_aranges) }\r
- .debug_pubnames 0 : { *(.debug_pubnames) }\r
- /* DWARF 2 */\r
- .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }\r
- .debug_abbrev 0 : { *(.debug_abbrev) }\r
- .debug_line 0 : { *(.debug_line) }\r
- .debug_frame 0 : { *(.debug_frame) }\r
- .debug_str 0 : { *(.debug_str) }\r
- .debug_loc 0 : { *(.debug_loc) }\r
- .debug_macinfo 0 : { *(.debug_macinfo) }\r
- /* SGI/MIPS DWARF 2 extensions */\r
- .debug_weaknames 0 : { *(.debug_weaknames) }\r
- .debug_funcnames 0 : { *(.debug_funcnames) }\r
- .debug_typenames 0 : { *(.debug_typenames) }\r
- .debug_varnames 0 : { *(.debug_varnames) }\r
-}\r
+/* Linker script for mbed LPC1768 */\r
+MEMORY\r
+{\r
+/* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K */\r
+ FLASH (rx) : ORIGIN = 16K, LENGTH = (512K - 16K)\r
+ RAM (rwx) : ORIGIN = 0x100000C8, LENGTH = (32K - 0xC8)\r
+\r
+ USB_RAM(rwx) : ORIGIN = 0x2007C000, LENGTH = 16K\r
+ ETH_RAM(rwx) : ORIGIN = 0x20080000, LENGTH = 16K\r
+}\r
+\r
+/* Linker script to place sections and symbol values. Should be used together\r
+ * with other linker script that defines memory regions FLASH and RAM.\r
+ * It references following symbols, which must be defined in code:\r
+ * Reset_Handler : Entry of reset handler\r
+ * \r
+ * It defines following symbols, which code can use without definition:\r
+ * __exidx_start\r
+ * __exidx_end\r
+ * __etext\r
+ * __data_start__\r
+ * __preinit_array_start\r
+ * __preinit_array_end\r
+ * __init_array_start\r
+ * __init_array_end\r
+ * __fini_array_start\r
+ * __fini_array_end\r
+ * __data_end__\r
+ * __bss_start__\r
+ * __bss_end__\r
+ * __end__\r
+ * end\r
+ * __HeapLimit\r
+ * __StackLimit\r
+ * __StackTop\r
+ * __stack\r
+ */\r
+ENTRY(Reset_Handler)\r
+\r
+SECTIONS\r
+{\r
+ .text :\r
+ {\r
+ __cs3_region_start_rom = .;\r
+ KEEP(*(.isr_vector))\r
+ *(.text*)\r
+\r
+ KEEP(*(.init))\r
+ KEEP(*(.fini))\r
+\r
+ /* .ctors */\r
+ *crtbegin.o(.ctors)\r
+ *crtbegin?.o(.ctors)\r
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\r
+ *(SORT(.ctors.*))\r
+ *(.ctors)\r
+\r
+ /* .dtors */\r
+ *crtbegin.o(.dtors)\r
+ *crtbegin?.o(.dtors)\r
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\r
+ *(SORT(.dtors.*))\r
+ *(.dtors)\r
+\r
+ *(.rodata*)\r
+\r
+ KEEP(*(.eh_frame*))\r
+ } > FLASH\r
+\r
+ .ARM.extab : \r
+ {\r
+ *(.ARM.extab* .gnu.linkonce.armextab.*)\r
+ } > FLASH\r
+\r
+ __exidx_start = .;\r
+ .ARM.exidx :\r
+ {\r
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r
+ } > FLASH\r
+ __exidx_end = .;\r
+\r
+ __etext = .;\r
+ \r
+ .data : AT (__etext)\r
+ {\r
+ __cs3_region_start_ram = .;\r
+ __data_start__ = .;\r
+ Image$$RW_IRAM1$$Base = .;\r
+ *(vtable)\r
+ *(.data*)\r
+\r
+ . = ALIGN(4);\r
+ /* preinit data */\r
+ PROVIDE (__preinit_array_start = .);\r
+ KEEP(*(.preinit_array))\r
+ PROVIDE (__preinit_array_end = .);\r
+\r
+ . = ALIGN(4);\r
+ /* init data */\r
+ PROVIDE (__init_array_start = .);\r
+ KEEP(*(SORT(.init_array.*)))\r
+ KEEP(*(.init_array))\r
+ PROVIDE (__init_array_end = .);\r
+\r
+\r
+ . = ALIGN(4);\r
+ /* finit data */\r
+ PROVIDE (__fini_array_start = .);\r
+ KEEP(*(SORT(.fini_array.*)))\r
+ KEEP(*(.fini_array))\r
+ PROVIDE (__fini_array_end = .);\r
+\r
+ . = ALIGN(4);\r
+ /* All data end */\r
+ __data_end__ = .;\r
+\r
+ } > RAM\r
+\r
+ .bss :\r
+ {\r
+ __bss_start__ = .;\r
+ *(.bss*)\r
+ *(COMMON)\r
+ __bss_end__ = .;\r
+ Image$$RW_IRAM1$$ZI$$Limit = . ;\r
+ } > RAM\r
+ \r
+ .heap :\r
+ {\r
+ __end__ = .;\r
+ end = __end__;\r
+ *(.heap*)\r
+ __HeapLimit = .;\r
+ } > RAM\r
+\r
+ /* .stack_dummy section doesn't contains any symbols. It is only\r
+ * used for linker to calculate size of stack sections, and assign\r
+ * values to stack symbols later */\r
+ .stack_dummy :\r
+ {\r
+ *(.stack)\r
+ } > RAM\r
+\r
+ /* Set stack top to end of RAM, and stack limit move down by\r
+ * size of stack_dummy section */\r
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);\r
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);\r
+ PROVIDE(__stack = __StackTop);\r
+ \r
+ /* Check if data + heap + stack exceeds RAM limit */\r
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")\r
+\r
+\r
+ /* Code can explicitly ask for data to be \r
+ placed in these higher RAM banks where\r
+ they will be left uninitialized. \r
+ */\r
+ .AHBSRAM0 (NOLOAD):\r
+ {\r
+ Image$$RW_IRAM2$$Base = . ;\r
+ *(AHBSRAM0)\r
+ Image$$RW_IRAM2$$ZI$$Limit = .;\r
+ } > USB_RAM\r
+\r
+ .AHBSRAM1 (NOLOAD):\r
+ {\r
+ Image$$RW_IRAM3$$Base = . ;\r
+ *(AHBSRAM1)\r
+ Image$$RW_IRAM3$$ZI$$Limit = .;\r
+ } > ETH_RAM\r
+}\r
HCoop / clinton / Smoothieware.git / blobdiff