-/******************************************************************************\r
- * @file: LPC17xx.h\r
- * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File for \r
- * NXP LPC17xx Device Series \r
- * @version: V1.04\r
- * @date: 2. July 2009\r
- *----------------------------------------------------------------------------\r
+/**************************************************************************//**\r
+ * @file LPC17xx.h\r
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for \r
+ * NXP LPC17xx Device Series\r
+ * @version: V1.09\r
+ * @date: 17. March 2010\r
+\r
*\r
- * Copyright (C) 2008 ARM Limited. All rights reserved.\r
+ * @note\r
+ * Copyright (C) 2009 ARM Limited. All rights reserved.\r
*\r
- * ARM Limited (ARM) is supplying this software for use with Cortex-M3 \r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
* processor based microcontrollers. This file can be freely distributed \r
* within development tools that are supporting such ARM based processors. \r
*\r
+ * @par\r
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */\r
QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */\r
PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */\r
+ USBActivity_IRQn = 33, /* USB Activity interrupt */\r
+ CANActivity_IRQn = 34, /* CAN Activity interrupt */\r
} IRQn_Type;\r
\r
\r
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
\r
\r
-#include <core_cm3.h> /* Cortex-M3 processor and core peripherals */\r
+#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */\r
#include "system_LPC17xx.h" /* System Header */\r
\r
\r
__IO uint32_t CCLKCFG;\r
__IO uint32_t USBCLKCFG;\r
__IO uint32_t CLKSRCSEL;\r
- uint32_t RESERVED4[12];\r
+ __IO uint32_t CANSLEEPCLR;\r
+ __IO uint32_t CANWAKEFLAGS;\r
+ uint32_t RESERVED4[10];\r
__IO uint32_t EXTINT; /* External Interrupts */\r
uint32_t RESERVED5;\r
__IO uint32_t EXTMODE;\r
__IO uint32_t PCLKSEL1;\r
uint32_t RESERVED8[4];\r
__IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */\r
- uint32_t RESERVED9;\r
+ __IO uint32_t DMAREQSEL;\r
__IO uint32_t CLKOUTCFG; /* Clock Output Configuration */\r
} LPC_SC_TypeDef;\r
\r
/*------------- General Purpose Input/Output (GPIO) --------------------------*/\r
typedef struct\r
{\r
- __IO uint32_t FIODIR;\r
- uint32_t RESERVED0[3];\r
- __IO uint32_t FIOMASK;\r
- __IO uint32_t FIOPIN;\r
- __IO uint32_t FIOSET;\r
- __O uint32_t FIOCLR;\r
+ union {\r
+ __IO uint32_t FIODIR;\r
+ struct {\r
+ __IO uint16_t FIODIRL;\r
+ __IO uint16_t FIODIRH;\r
+ };\r
+ struct {\r
+ __IO uint8_t FIODIR0;\r
+ __IO uint8_t FIODIR1;\r
+ __IO uint8_t FIODIR2;\r
+ __IO uint8_t FIODIR3;\r
+ };\r
+ };\r
+ uint32_t RESERVED0[3];\r
+ union {\r
+ __IO uint32_t FIOMASK;\r
+ struct {\r
+ __IO uint16_t FIOMASKL;\r
+ __IO uint16_t FIOMASKH;\r
+ };\r
+ struct {\r
+ __IO uint8_t FIOMASK0;\r
+ __IO uint8_t FIOMASK1;\r
+ __IO uint8_t FIOMASK2;\r
+ __IO uint8_t FIOMASK3;\r
+ };\r
+ };\r
+ union {\r
+ __IO uint32_t FIOPIN;\r
+ struct {\r
+ __IO uint16_t FIOPINL;\r
+ __IO uint16_t FIOPINH;\r
+ };\r
+ struct {\r
+ __IO uint8_t FIOPIN0;\r
+ __IO uint8_t FIOPIN1;\r
+ __IO uint8_t FIOPIN2;\r
+ __IO uint8_t FIOPIN3;\r
+ };\r
+ };\r
+ union {\r
+ __IO uint32_t FIOSET;\r
+ struct {\r
+ __IO uint16_t FIOSETL;\r
+ __IO uint16_t FIOSETH;\r
+ };\r
+ struct {\r
+ __IO uint8_t FIOSET0;\r
+ __IO uint8_t FIOSET1;\r
+ __IO uint8_t FIOSET2;\r
+ __IO uint8_t FIOSET3;\r
+ };\r
+ };\r
+ union {\r
+ __O uint32_t FIOCLR;\r
+ struct {\r
+ __O uint16_t FIOCLRL;\r
+ __O uint16_t FIOCLRH;\r
+ };\r
+ struct {\r
+ __O uint8_t FIOCLR0;\r
+ __O uint8_t FIOCLR1;\r
+ __O uint8_t FIOCLR2;\r
+ __O uint8_t FIOCLR3;\r
+ };\r
+ };\r
} LPC_GPIO_TypeDef;\r
\r
typedef struct\r
uint8_t RESERVED5[7];\r
__IO uint8_t TER;\r
uint8_t RESERVED6[39];\r
- __I uint8_t FIFOLVL;\r
+ __IO uint32_t FIFOLVL;\r
} LPC_UART_TypeDef;\r
\r
typedef struct\r
uint8_t RESERVED5[7];\r
__IO uint8_t TER;\r
uint8_t RESERVED6[39];\r
- __I uint8_t FIFOLVL;\r
- uint8_t RESERVED7[363];\r
- __IO uint32_t DMAREQSEL;\r
+ __IO uint32_t FIFOLVL;\r
} LPC_UART0_TypeDef;\r
\r
typedef struct\r
uint8_t RESERVED10[3];\r
__IO uint8_t RS485DLY;\r
uint8_t RESERVED11[3];\r
- __I uint8_t FIFOLVL;\r
+ __IO uint32_t FIFOLVL;\r
} LPC_UART1_TypeDef;\r
\r
/*------------- Serial Peripheral Interface (SPI) ----------------------------*/\r
__O uint32_t USBSysErrIntSet;\r
uint32_t RESERVED4[15];\r
\r
+ union {\r
__I uint32_t I2C_RX; /* USB OTG I2C Registers */\r
- __O uint32_t I2C_WO;\r
+ __O uint32_t I2C_TX;\r
+ };\r
__I uint32_t I2C_STS;\r
__IO uint32_t I2C_CTL;\r
__IO uint32_t I2C_CLKHI;\r
__O uint32_t I2C_CLKLO;\r
- uint32_t RESERVED5[823];\r
+ uint32_t RESERVED5[824];\r
\r
union {\r
__IO uint32_t USBClkCtrl; /* USB Clock Control Registers */\r
} LPC_EMAC_TypeDef;\r
\r
#if defined ( __CC_ARM )\r
-#pragma anon_unions\r
+#pragma no_anon_unions\r
#endif\r
\r
\r